# messages

id: CL246
link: "\\Mac\iCloud\Repos\GR8RAM\cpld\GR8RAM.v":15:14:15:15|
kind: warning
message:
Input port bits 15 to 11 of BA[15:0] are unused. Assign logic for all port bits or change the input port size.


id: MF666
kind: note
message:
Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)


id: FX474
kind: warning
message:
User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 


id: BN362
link: "\\mac\icloud\repos\gr8ram\cpld\businterface.v":122:1:122:6
kind: note
message:
Removing sequential instance ROMRD (in view: work.BusInterface(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.


id: BN362
link: "\\mac\icloud\repos\gr8ram\cpld\slinkyregisters.v":65:1:65:6
kind: note
message:
Removing sequential instance Bank (in view: work.SlinkyRegisters(verilog)) of type view:PrimLib.sdffre(prim) because it does not drive other instances.


id: BN362
link: "\\mac\icloud\repos\gr8ram\cpld\businterface.v":97:1:97:6
kind: note
message:
Removing sequential instance BankWR (in view: work.BusInterface(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances.


id: BN362
link: "\\mac\icloud\repos\gr8ram\cpld\businterface.v":97:1:97:6
kind: note
message:
Removing sequential instance BankWRpre (in view: work.BusInterface(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances.


id: FX1143
kind: note
message:
Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.


id: FA239
link: "\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":168:4:168:7
kind: warning
message:
ROM nFCSout_2 (in view: work.InitController(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.


id: FA239
link: "\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":168:4:168:7
kind: warning
message:
ROM MOSIOE_2 (in view: work.InitController(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.


id: FA239
link: "\\mac\icloud\repos\gr8ram\cpld\initcontroller.v":168:4:168:7
kind: warning
message:
ROM RAMCmd_2[2:0] (in view: work.InitController(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RBA_1_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RBA_0_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.DQMH.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.DQML.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_12_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_11_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_10_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_9_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_8_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_7_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_6_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_5_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_4_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_3_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_2_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_1_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: BN291
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":58:1:58:6
kind: advice
message:
Boundary register ram.RA_0_.fb (in view: work.GR8RAM(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 


id: MT246
link: "\\mac\icloud\repos\gr8ram\cpld\sdramcontroller.v":203:8:203:16
kind: warning
message:
Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)


id: MT320
kind: note
message:
This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.


