[ START MERGED ]
ic.MISOr.CN CLK
RDOE_i ram/RDOE
ic.SetRestoreEN_i ic/SetRestoreEN
bi.nRESr.CN PHI0_c
bi/S_i[1] bi/S[1]
[ END MERGED ]
[ START CLIPPED ]
registers/GND
CLKin_c
CLKin
BA_c[11]
BA[11]
BA_c[12]
BA[12]
BA_c[13]
BA[13]
BA_c[14]
BA[14]
BA_c[15]
BA[15]
registers/un1_Addr_2_s_7_0_S1
registers/un1_Addr_2_s_7_0_COUT
registers/un1_Addr_1_cry_0_0_S0
registers/N_3
registers/un1_Addr_1_s_7_0_S1
registers/un1_Addr_1_s_7_0_COUT
registers/un1_Addr_cry_0_0_S0
registers/N_4
registers/un1_Addr_s_7_0_S1
registers/un1_Addr_s_7_0_COUT
registers/un1_Addr_2_cry_0_0_S0
registers/N_2
ic/un2_LS_1_cry_0_0_S1
ic/un2_LS_1_cry_0_0_S0
ic/N_1
ic/un2_LS_1_cry_11_0_COUT
ic/un2_CS_cry_0_0_S1
ic/un2_CS_cry_0_0_S0
ic/N_2
ic/un2_CS_cry_11_0_COUT
OSCH_inst_SEDSTDBY
[ END CLIPPED ]
[ START OSC ]
CLK 44.33
[ END OSC ]
[ START DESIGN PREFS ]
SCHEMATIC START ;
# map:  version Diamond (64-bit) 3.11.3.469 -- WARNING: Map write only section -- Sun Jul 14 06:18:49 2024

SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "BD[0]" SITE "65" ;
LOCATE COMP "LED" SITE "81" ;
LOCATE COMP "PHI0" SITE "17" ;
LOCATE COMP "FCK" SITE "96" ;
LOCATE COMP "nFCS" SITE "88" ;
LOCATE COMP "MOSI" SITE "97" ;
LOCATE COMP "MISO" SITE "98" ;
LOCATE COMP "RD[7]" SITE "31" ;
LOCATE COMP "RD[6]" SITE "30" ;
LOCATE COMP "RD[5]" SITE "29" ;
LOCATE COMP "RD[4]" SITE "28" ;
LOCATE COMP "RD[3]" SITE "27" ;
LOCATE COMP "RD[2]" SITE "21" ;
LOCATE COMP "RD[1]" SITE "24" ;
LOCATE COMP "RD[0]" SITE "25" ;
LOCATE COMP "DQMH" SITE "34" ;
LOCATE COMP "DQML" SITE "32" ;
LOCATE COMP "nRWE" SITE "35" ;
LOCATE COMP "nCAS" SITE "36" ;
LOCATE COMP "nRAS" SITE "37" ;
LOCATE COMP "RCKE" SITE "40" ;
LOCATE COMP "nRCS" SITE "41" ;
LOCATE COMP "RA[12]" SITE "42" ;
LOCATE COMP "RA[11]" SITE "45" ;
LOCATE COMP "RA[10]" SITE "47" ;
LOCATE COMP "RA[9]" SITE "49" ;
LOCATE COMP "RA[8]" SITE "53" ;
LOCATE COMP "RA[7]" SITE "57" ;
LOCATE COMP "RA[6]" SITE "62" ;
LOCATE COMP "RA[5]" SITE "52" ;
LOCATE COMP "RA[4]" SITE "51" ;
LOCATE COMP "RA[3]" SITE "60" ;
LOCATE COMP "RA[2]" SITE "58" ;
LOCATE COMP "RA[1]" SITE "59" ;
LOCATE COMP "RA[0]" SITE "54" ;
LOCATE COMP "RBA[1]" SITE "48" ;
LOCATE COMP "RBA[0]" SITE "43" ;
LOCATE COMP "RCLK" SITE "39" ;
LOCATE COMP "nIOSTRB" SITE "18" ;
LOCATE COMP "nDEVSEL" SITE "16" ;
LOCATE COMP "nIOSEL" SITE "15" ;
LOCATE COMP "nDinOE" SITE "77" ;
LOCATE COMP "nDoutOE" SITE "1" ;
LOCATE COMP "BD[7]" SITE "75" ;
LOCATE COMP "BD[6]" SITE "71" ;
LOCATE COMP "BD[5]" SITE "70" ;
LOCATE COMP "BD[4]" SITE "69" ;
LOCATE COMP "BD[3]" SITE "68" ;
LOCATE COMP "BD[2]" SITE "67" ;
LOCATE COMP "BD[1]" SITE "66" ;
LOCATE COMP "nWE" SITE "19" ;
LOCATE COMP "BA[10]" SITE "3" ;
LOCATE COMP "BA[9]" SITE "2" ;
LOCATE COMP "BA[8]" SITE "99" ;
LOCATE COMP "BA[7]" SITE "87" ;
LOCATE COMP "BA[6]" SITE "86" ;
LOCATE COMP "BA[5]" SITE "85" ;
LOCATE COMP "BA[4]" SITE "4" ;
LOCATE COMP "BA[3]" SITE "84" ;
LOCATE COMP "BA[2]" SITE "83" ;
LOCATE COMP "BA[1]" SITE "78" ;
LOCATE COMP "BA[0]" SITE "74" ;
LOCATE COMP "SW[2]" SITE "63" ;
LOCATE COMP "SW[1]" SITE "64" ;
LOCATE COMP "nIRQout" SITE "12" ;
LOCATE COMP "nRESout" SITE "7" ;
LOCATE COMP "nRESin" SITE "20" ;
FREQUENCY PORT "PHI0" 1.000000 MHz ;
FREQUENCY NET "CLK" 44.300000 MHz ;
SCHEMATIC END ;
[ END DESIGN PREFS ]