--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.11.3.469
Mon Jul 08 23:40:57 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design file: GR8RAM
Device,speed: LCMXO2-640HC,M
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: FREQUENCY PORT "PHI0" 1.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "CLK" 44.300000 MHz ;
10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.260ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ic/FCKEN (from CLK +)
Destination: FF Data in fck_oddr (to CLK +)
Delay: 0.304ns (43.8% logic, 56.3% route), 1 logic levels.
Constraint Details:
0.304ns physical path delay ic/SLICE_56 to FCK_MGIOL meets
-0.011ns DO_HLD and
0.000ns delay constraint less
-0.055ns skew requirement (totaling 0.044ns) by 0.260ns
Physical Path Details:
Data path ic/SLICE_56 to FCK_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R2C6B.CLK to R2C6B.Q0 ic/SLICE_56 (from CLK)
ROUTE 1 0.171 R2C6B.Q0 to IOL_T6D.ONEG FCKEN (to CLK)
--------
0.304 (43.8% logic, 56.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to ic/SLICE_56:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R2C6B.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to FCK_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.095 OSC.OSC to IOL_T6D.CLK CLK
--------
1.095 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q bi/AddrIncDelay[2] (from CLK +)
Destination: FF Data in bi/AddrIncDelay[3] (to CLK +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay bi/SLICE_140 to bi/SLICE_140 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path bi/SLICE_140 to bi/SLICE_140:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C13C.CLK to R3C13C.Q0 bi/SLICE_140 (from CLK)
ROUTE 1 0.152 R3C13C.Q0 to R3C13C.M1 bi/AddrIncDelay[2] (to CLK)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to bi/SLICE_140:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R3C13C.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to bi/SLICE_140:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R3C13C.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q bi/AddrIncDelay[0] (from CLK +)
Destination: FF Data in bi/AddrIncDelay[1] (to CLK +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay bi/SLICE_141 to bi/SLICE_141 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path bi/SLICE_141 to bi/SLICE_141:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C13A.CLK to R3C13A.Q0 bi/SLICE_141 (from CLK)
ROUTE 1 0.152 R3C13A.Q0 to R3C13A.M1 bi/AddrIncDelay[0] (to CLK)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to bi/SLICE_141:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R3C13A.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to bi/SLICE_141:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R3C13A.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.304ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q bi/AddrIncDelay[1] (from CLK +)
Destination: FF Data in bi/AddrIncDelay[2] (to CLK +)
Delay: 0.285ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.285ns physical path delay bi/SLICE_141 to bi/SLICE_140 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.304ns
Physical Path Details:
Data path bi/SLICE_141 to bi/SLICE_140:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C13A.CLK to R3C13A.Q1 bi/SLICE_141 (from CLK)
ROUTE 1 0.152 R3C13A.Q1 to R3C13C.M0 bi/AddrIncDelay[1] (to CLK)
--------
0.285 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to bi/SLICE_141:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R3C13A.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to bi/SLICE_140:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R3C13C.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ic/WRD[4] (from CLK +)
Destination: FF Data in ic/WRD[6] (to CLK +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay ic/SLICE_138 to ic/SLICE_169 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path ic/SLICE_138 to ic/SLICE_169:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C8D.CLK to R3C8D.Q0 ic/SLICE_138 (from CLK)
ROUTE 2 0.154 R3C8D.Q0 to R3C8A.M0 IC_WRD[4] (to CLK)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to ic/SLICE_138:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R3C8D.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to ic/SLICE_169:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R3C8A.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.306ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ic/WRD[2] (from CLK +)
Destination: FF Data in ic/WRD[4] (to CLK +)
Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels.
Constraint Details:
0.287ns physical path delay ic/SLICE_133 to ic/SLICE_138 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.306ns
Physical Path Details:
Data path ic/SLICE_133 to ic/SLICE_138:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R3C8C.CLK to R3C8C.Q0 ic/SLICE_133 (from CLK)
ROUTE 2 0.154 R3C8C.Q0 to R3C8D.M0 IC_WRD[2] (to CLK)
--------
0.287 (46.3% logic, 53.7% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to ic/SLICE_133:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R3C8C.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to ic/SLICE_138:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R3C8D.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.309ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ic/LS[0] (from CLK +)
Destination: FF Data in ic/RAMAddr[10] (to CLK +)
Delay: 0.290ns (45.9% logic, 54.1% route), 1 logic levels.
Constraint Details:
0.290ns physical path delay ic/SLICE_109 to ic/SLICE_215 meets
-0.019ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.019ns) by 0.309ns
Physical Path Details:
Data path ic/SLICE_109 to ic/SLICE_215:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C6C.CLK to R4C6C.Q0 ic/SLICE_109 (from CLK)
ROUTE 5 0.157 R4C6C.Q0 to R4C8C.M1 ic/LS[0] (to CLK)
--------
0.290 (45.9% logic, 54.1% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to ic/SLICE_109:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R4C6C.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to ic/SLICE_215:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R4C8C.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.345ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ram/RS[2] (from CLK +)
Destination: FF Data in ram/RDDLE (to CLK +)
Delay: 0.288ns (46.2% logic, 53.8% route), 1 logic levels.
Constraint Details:
0.288ns physical path delay ram/SLICE_119 to ram/SLICE_115 meets
-0.057ns LSR_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.057ns) by 0.345ns
Physical Path Details:
Data path ram/SLICE_119 to ram/SLICE_115:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R5C9D.CLK to R5C9D.Q1 ram/SLICE_119 (from CLK)
ROUTE 15 0.155 R5C9D.Q1 to R6C9D.LSR ram/RS[2] (to CLK)
--------
0.288 (46.2% logic, 53.8% route), 1 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to ram/SLICE_119:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R5C9D.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to ram/SLICE_115:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R6C9D.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ic/LS[6] (from CLK +)
Destination: FF Data in ic/LS[6] (to CLK +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay ic/SLICE_10 to ic/SLICE_10 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path ic/SLICE_10 to ic/SLICE_10:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R4C3D.CLK to R4C3D.Q1 ic/SLICE_10 (from CLK)
ROUTE 5 0.132 R4C3D.Q1 to R4C3D.A1 ic/LS[6]
CTOF_DEL --- 0.101 R4C3D.A1 to R4C3D.F1 ic/SLICE_10
ROUTE 1 0.000 R4C3D.F1 to R4C3D.DI1 ic/un2_LS_1_cry_5_0_S1 (to CLK)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to ic/SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R4C3D.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to ic/SLICE_10:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R4C3D.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.379ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ic/CS[7] (from CLK +)
Destination: FF Data in ic/CS[7] (to CLK +)
Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels.
Constraint Details:
0.366ns physical path delay ic/SLICE_2 to ic/SLICE_2 meets
-0.013ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.013ns) by 0.379ns
Physical Path Details:
Data path ic/SLICE_2 to ic/SLICE_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.133 R6C7A.CLK to R6C7A.Q0 ic/SLICE_2 (from CLK)
ROUTE 12 0.132 R6C7A.Q0 to R6C7A.A0 ic/CS[7]
CTOF_DEL --- 0.101 R6C7A.A0 to R6C7A.F0 ic/SLICE_2
ROUTE 1 0.000 R6C7A.F0 to R6C7A.DI0 ic/un2_CS_cry_7_0_S0 (to CLK)
--------
0.366 (63.9% logic, 36.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to ic/SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R6C7A.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to ic/SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 130 1.040 OSC.OSC to R6C7A.CLK CLK
--------
1.040 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI0" 1.000000 MHz ; | -| -| 0
| | |
FREQUENCY NET "CLK" 44.300000 MHz ; | 0.000 ns| 0.260 ns| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: PHI0_c Source: PHI0.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: CLK Source: OSCH_inst.OSC Loads: 130
Covered under: FREQUENCY NET "CLK" 44.300000 MHz ;
Data transfers from:
Clock Domain: PHI0_c Source: PHI0.PAD
Not reported because source and destination domains are unrelated.
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 3109 paths, 2 nets, and 1556 connections (89.48% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)