--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.11.3.469
Mon Jul 08 23:40:57 2024
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Design file: GR8RAM
Device,speed: LCMXO2-640HC,4
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 3.300 V
================================================================================
Preference: FREQUENCY PORT "PHI0" 1.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 993.340ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD PHI0
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "CLK" 44.300000 MHz ;
10 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 4.097ns (weighted slack = 8.194ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ram_RDDio[6] (from CLK -)
Destination: FF Data in bi_BDoutio[6] (to CLK +)
Delay: 7.037ns (25.5% logic, 74.5% route), 3 logic levels.
Constraint Details:
7.037ns physical path delay RD[6]_MGIOL to BD[6]_MGIOL meets
11.287ns delay constraint less
0.000ns skew and
0.153ns DO_SET requirement (totaling 11.134ns) by 4.097ns
Physical Path Details:
Data path RD[6]_MGIOL to BD[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_B4D.CLK to IOL_B4D.IN RD[6]_MGIOL (from CLK)
ROUTE 1 2.215 IOL_B4D.IN to R5C13C.A1 RDD[6]
CTOOFX_DEL --- 0.721 R5C13C.A1 to R5C13C.OFX0 bi/BDout_8_2[6]/SLICE_123
ROUTE 1 1.336 R5C13C.OFX0 to R2C13B.B0 bi/N_72
CTOF_DEL --- 0.495 R2C13B.B0 to R2C13B.F0 bi/SLICE_135
ROUTE 1 1.693 R2C13B.F0 to IOL_R2C.OPOS bi.BDout_8[6] (to CLK)
--------
7.037 (25.5% logic, 74.5% route), 3 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to RD[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_B4D.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to BD[6]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_R2C.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.325ns (weighted slack = 8.650ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ram_RDDio[2] (from CLK -)
Destination: FF Data in bi_BDoutio[2] (to CLK +)
Delay: 6.809ns (26.3% logic, 73.7% route), 3 logic levels.
Constraint Details:
6.809ns physical path delay RD[2]_MGIOL to BD[2]_MGIOL meets
11.287ns delay constraint less
0.000ns skew and
0.153ns DO_SET requirement (totaling 11.134ns) by 4.325ns
Physical Path Details:
Data path RD[2]_MGIOL to BD[2]_MGIOL:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L7B.CLK to IOL_L7B.IN RD[2]_MGIOL (from CLK)
ROUTE 1 1.995 IOL_L7B.IN to R5C13B.C1 RDD[2]
CTOOFX_DEL --- 0.721 R5C13B.C1 to R5C13B.OFX0 bi/BDout_8_2[2]/SLICE_126
ROUTE 1 0.986 R5C13B.OFX0 to R3C13D.A0 bi/N_68
CTOF_DEL --- 0.495 R3C13D.A0 to R3C13D.F0 bi/SLICE_193
ROUTE 1 2.035 R3C13D.F0 to IOL_R3C.OPOS bi.BDout_8[2] (to CLK)
--------
6.809 (26.3% logic, 73.7% route), 3 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to RD[2]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_L7B.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to BD[2]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_R3C.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.550ns (weighted slack = 9.100ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ram_RDDio[4] (from CLK -)
Destination: FF Data in bi_BDoutio[4] (to CLK +)
Delay: 6.584ns (27.2% logic, 72.8% route), 3 logic levels.
Constraint Details:
6.584ns physical path delay RD[4]_MGIOL to BD[4]_MGIOL meets
11.287ns delay constraint less
0.000ns skew and
0.153ns DO_SET requirement (totaling 11.134ns) by 4.550ns
Physical Path Details:
Data path RD[4]_MGIOL to BD[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_B4B.CLK to IOL_B4B.IN RD[4]_MGIOL (from CLK)
ROUTE 1 2.751 IOL_B4B.IN to R4C13C.B1 RDD[4]
CTOOFX_DEL --- 0.721 R4C13C.B1 to R4C13C.OFX0 bi/BDout_8_2[4]/SLICE_128
ROUTE 1 0.744 R4C13C.OFX0 to R3C13D.C1 bi/N_70
CTOF_DEL --- 0.495 R3C13D.C1 to R3C13D.F1 bi/SLICE_193
ROUTE 1 1.296 R3C13D.F1 to IOL_R3A.OPOS bi.BDout_8[4] (to CLK)
--------
6.584 (27.2% logic, 72.8% route), 3 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to RD[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_B4B.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to BD[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_R3A.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.682ns (weighted slack = 9.364ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ram_RDDio[3] (from CLK -)
Destination: FF Data in bi_BDoutio[3] (to CLK +)
Delay: 6.452ns (27.8% logic, 72.2% route), 3 logic levels.
Constraint Details:
6.452ns physical path delay RD[3]_MGIOL to BD[3]_MGIOL meets
11.287ns delay constraint less
0.000ns skew and
0.153ns DO_SET requirement (totaling 11.134ns) by 4.682ns
Physical Path Details:
Data path RD[3]_MGIOL to BD[3]_MGIOL:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_B4A.CLK to IOL_B4A.IN RD[3]_MGIOL (from CLK)
ROUTE 1 2.177 IOL_B4A.IN to R5C14B.D1 RDD[3]
CTOOFX_DEL --- 0.721 R5C14B.D1 to R5C14B.OFX0 bi/BDout_8_2[3]/SLICE_129
ROUTE 1 0.958 R5C14B.OFX0 to R3C13B.D0 bi/N_69
CTOF_DEL --- 0.495 R3C13B.D0 to R3C13B.F0 bi/SLICE_187
ROUTE 1 1.524 R3C13B.F0 to IOL_R3B.OPOS bi.BDout_8[3] (to CLK)
--------
6.452 (27.8% logic, 72.2% route), 3 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to RD[3]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_B4A.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to BD[3]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_R3B.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.751ns (weighted slack = 9.502ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ram_RDDio[7] (from CLK -)
Destination: FF Data in bi_BDoutio[7] (to CLK +)
Delay: 6.383ns (28.1% logic, 71.9% route), 3 logic levels.
Constraint Details:
6.383ns physical path delay RD[7]_MGIOL to BD[7]_MGIOL meets
11.287ns delay constraint less
0.000ns skew and
0.153ns DO_SET requirement (totaling 11.134ns) by 4.751ns
Physical Path Details:
Data path RD[7]_MGIOL to BD[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_B6A.CLK to IOL_B6A.IN RD[7]_MGIOL (from CLK)
ROUTE 1 1.995 IOL_B6A.IN to R5C14C.C1 RDD[7]
CTOOFX_DEL --- 0.721 R5C14C.C1 to R5C14C.OFX0 bi/BDout_8_2[7]/SLICE_124
ROUTE 1 1.299 R5C14C.OFX0 to R2C14C.A1 bi/N_73
CTOF_DEL --- 0.495 R2C14C.A1 to R2C14C.F1 bi/SLICE_188
ROUTE 1 1.296 R2C14C.F1 to IOL_R2A.OPOS bi.BDout_8[7] (to CLK)
--------
6.383 (28.1% logic, 71.9% route), 3 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to RD[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_B6A.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to BD[7]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_R2A.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.529ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ic/CS[10] (from CLK +)
Destination: FF Data in ic/RAMRef (to CLK +)
Delay: 12.762ns (22.9% logic, 77.1% route), 6 logic levels.
Constraint Details:
12.762ns physical path delay ic/SLICE_1 to ic/SLICE_74 meets
22.573ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 22.291ns) by 9.529ns
Physical Path Details:
Data path ic/SLICE_1 to ic/SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C7B.CLK to R6C7B.Q1 ic/SLICE_1 (from CLK)
ROUTE 5 1.496 R6C7B.Q1 to R5C8D.D1 ic/CS[10]
CTOF_DEL --- 0.495 R5C8D.D1 to R5C8D.F1 ic/SLICE_160
ROUTE 8 1.974 R5C8D.F1 to R2C6C.C1 ic/N_136
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 ic/SLICE_171
ROUTE 9 2.210 R2C6C.F1 to R5C8C.A0 ic/N_96_2
CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 ic/SLICE_176
ROUTE 1 0.967 R5C8C.F0 to R5C8A.A0 ic/RAMRef_2_sqmuxa_i_0_2
CTOF_DEL --- 0.495 R5C8A.A0 to R5C8A.F0 ic/SLICE_170
ROUTE 1 1.336 R5C8A.F0 to R4C7B.B0 ic/RAMRef_2_sqmuxa_i_0_5
CTOF_DEL --- 0.495 R4C7B.B0 to R4C7B.F0 ic/SLICE_167
ROUTE 3 1.852 R4C7B.F0 to R3C7A.CE ic/N_37 (to CLK)
--------
12.762 (22.9% logic, 77.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to ic/SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 130 2.996 OSC.OSC to R6C7B.CLK CLK
--------
2.996 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to ic/SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 130 2.996 OSC.OSC to R3C7A.CLK CLK
--------
2.996 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.549ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ic/CS[11] (from CLK +)
Destination: FF Data in ic/RAMRef (to CLK +)
Delay: 12.742ns (23.0% logic, 77.0% route), 6 logic levels.
Constraint Details:
12.742ns physical path delay SLICE_0 to ic/SLICE_74 meets
22.573ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 22.291ns) by 9.549ns
Physical Path Details:
Data path SLICE_0 to ic/SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C7C.CLK to R6C7C.Q0 SLICE_0 (from CLK)
ROUTE 5 1.476 R6C7C.Q0 to R5C8D.B1 ic/CS[11]
CTOF_DEL --- 0.495 R5C8D.B1 to R5C8D.F1 ic/SLICE_160
ROUTE 8 1.974 R5C8D.F1 to R2C6C.C1 ic/N_136
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 ic/SLICE_171
ROUTE 9 2.210 R2C6C.F1 to R5C8C.A0 ic/N_96_2
CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 ic/SLICE_176
ROUTE 1 0.967 R5C8C.F0 to R5C8A.A0 ic/RAMRef_2_sqmuxa_i_0_2
CTOF_DEL --- 0.495 R5C8A.A0 to R5C8A.F0 ic/SLICE_170
ROUTE 1 1.336 R5C8A.F0 to R4C7B.B0 ic/RAMRef_2_sqmuxa_i_0_5
CTOF_DEL --- 0.495 R4C7B.B0 to R4C7B.F0 ic/SLICE_167
ROUTE 3 1.852 R4C7B.F0 to R3C7A.CE ic/N_37 (to CLK)
--------
12.742 (23.0% logic, 77.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to SLICE_0:
Name Fanout Delay (ns) Site Resource
ROUTE 130 2.996 OSC.OSC to R6C7C.CLK CLK
--------
2.996 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to ic/SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 130 2.996 OSC.OSC to R3C7A.CLK CLK
--------
2.996 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.692ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ic/CS[9] (from CLK +)
Destination: FF Data in ic/RAMRef (to CLK +)
Delay: 12.599ns (23.2% logic, 76.8% route), 6 logic levels.
Constraint Details:
12.599ns physical path delay ic/SLICE_1 to ic/SLICE_74 meets
22.573ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 22.291ns) by 9.692ns
Physical Path Details:
Data path ic/SLICE_1 to ic/SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C7B.CLK to R6C7B.Q0 ic/SLICE_1 (from CLK)
ROUTE 5 1.333 R6C7B.Q0 to R5C8D.A1 ic/CS[9]
CTOF_DEL --- 0.495 R5C8D.A1 to R5C8D.F1 ic/SLICE_160
ROUTE 8 1.974 R5C8D.F1 to R2C6C.C1 ic/N_136
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 ic/SLICE_171
ROUTE 9 2.210 R2C6C.F1 to R5C8C.A0 ic/N_96_2
CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 ic/SLICE_176
ROUTE 1 0.967 R5C8C.F0 to R5C8A.A0 ic/RAMRef_2_sqmuxa_i_0_2
CTOF_DEL --- 0.495 R5C8A.A0 to R5C8A.F0 ic/SLICE_170
ROUTE 1 1.336 R5C8A.F0 to R4C7B.B0 ic/RAMRef_2_sqmuxa_i_0_5
CTOF_DEL --- 0.495 R4C7B.B0 to R4C7B.F0 ic/SLICE_167
ROUTE 3 1.852 R4C7B.F0 to R3C7A.CE ic/N_37 (to CLK)
--------
12.599 (23.2% logic, 76.8% route), 6 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to ic/SLICE_1:
Name Fanout Delay (ns) Site Resource
ROUTE 130 2.996 OSC.OSC to R6C7B.CLK CLK
--------
2.996 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to ic/SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 130 2.996 OSC.OSC to R3C7A.CLK CLK
--------
2.996 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 4.928ns (weighted slack = 9.856ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ram_RDDio[1] (from CLK -)
Destination: FF Data in bi_BDoutio[1] (to CLK +)
Delay: 6.206ns (28.9% logic, 71.1% route), 3 logic levels.
Constraint Details:
6.206ns physical path delay RD[1]_MGIOL to BD[1]_MGIOL meets
11.287ns delay constraint less
0.000ns skew and
0.153ns DO_SET requirement (totaling 11.134ns) by 4.928ns
Physical Path Details:
Data path RD[1]_MGIOL to BD[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
C2INP_DEL --- 0.577 IOL_L7C.CLK to IOL_L7C.IN RD[1]_MGIOL (from CLK)
ROUTE 1 2.494 IOL_L7C.IN to R4C13B.C1 RDD[1]
CTOOFX_DEL --- 0.721 R4C13B.C1 to R4C13B.OFX0 bi/BDout_8_2[1]/SLICE_122
ROUTE 1 0.623 R4C13B.OFX0 to R3C13C.D0 bi/N_67
CTOF_DEL --- 0.495 R3C13C.D0 to R3C13C.F0 bi/SLICE_140
ROUTE 1 1.296 R3C13C.F0 to IOL_R3D.OPOS bi.BDout_8[1] (to CLK)
--------
6.206 (28.9% logic, 71.1% route), 3 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to RD[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_L7C.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to BD[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 130 3.169 OSC.OSC to IOL_R3D.CLK CLK
--------
3.169 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 9.913ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q ic/CS[8] (from CLK +)
Destination: FF Data in ic/RAMRef (to CLK +)
Delay: 12.378ns (23.6% logic, 76.4% route), 6 logic levels.
Constraint Details:
12.378ns physical path delay ic/SLICE_2 to ic/SLICE_74 meets
22.573ns delay constraint less
0.000ns skew and
0.282ns CE_SET requirement (totaling 22.291ns) by 9.913ns
Physical Path Details:
Data path ic/SLICE_2 to ic/SLICE_74:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.452 R6C7A.CLK to R6C7A.Q1 ic/SLICE_2 (from CLK)
ROUTE 5 1.112 R6C7A.Q1 to R5C8D.C1 ic/CS[8]
CTOF_DEL --- 0.495 R5C8D.C1 to R5C8D.F1 ic/SLICE_160
ROUTE 8 1.974 R5C8D.F1 to R2C6C.C1 ic/N_136
CTOF_DEL --- 0.495 R2C6C.C1 to R2C6C.F1 ic/SLICE_171
ROUTE 9 2.210 R2C6C.F1 to R5C8C.A0 ic/N_96_2
CTOF_DEL --- 0.495 R5C8C.A0 to R5C8C.F0 ic/SLICE_176
ROUTE 1 0.967 R5C8C.F0 to R5C8A.A0 ic/RAMRef_2_sqmuxa_i_0_2
CTOF_DEL --- 0.495 R5C8A.A0 to R5C8A.F0 ic/SLICE_170
ROUTE 1 1.336 R5C8A.F0 to R4C7B.B0 ic/RAMRef_2_sqmuxa_i_0_5
CTOF_DEL --- 0.495 R4C7B.B0 to R4C7B.F0 ic/SLICE_167
ROUTE 3 1.852 R4C7B.F0 to R3C7A.CE ic/N_37 (to CLK)
--------
12.378 (23.6% logic, 76.4% route), 6 logic levels.
Clock Skew Details:
Source Clock Path OSCH_inst to ic/SLICE_2:
Name Fanout Delay (ns) Site Resource
ROUTE 130 2.996 OSC.OSC to R6C7A.CLK CLK
--------
2.996 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path OSCH_inst to ic/SLICE_74:
Name Fanout Delay (ns) Site Resource
ROUTE 130 2.996 OSC.OSC to R3C7A.CLK CLK
--------
2.996 (0.0% logic, 100.0% route), 0 logic levels.
Report: 69.551MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "PHI0" 1.000000 MHz ; | 1.000 MHz| 150.150 MHz| 0
| | |
FREQUENCY NET "CLK" 44.300000 MHz ; | 44.300 MHz| 69.551 MHz| 3
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 2 clocks:
Clock Domain: PHI0_c Source: PHI0.PAD Loads: 7
No transfer within this clock domain is found
Clock Domain: CLK Source: OSCH_inst.OSC Loads: 130
Covered under: FREQUENCY NET "CLK" 44.300000 MHz ;
Data transfers from:
Clock Domain: PHI0_c Source: PHI0.PAD
Not reported because source and destination domains are unrelated.
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 3109 paths, 2 nets, and 1556 connections (89.48% coverage)