335 lines
7.3 KiB
Verilog
335 lines
7.3 KiB
Verilog
module GR8RAM2(
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/* Clock signals */
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input C25M,
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input PHI0,
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input nRESin,
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output reg nRESout,
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input [1:0] SetFW,
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output reg nIRQout,
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input [15:0] BA,
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input nWE,
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inout [7:0] BD,
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output BDdir,
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/* Card select signals */
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input nIOSEL,
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input nDEVSEL,
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input nIOSTRB,
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/* SDRAM bus */
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output reg [1:0] RBA,
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output reg [12:0] RA,
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output nRCS,
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output reg nRAS,
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output reg nCAS,
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output reg nRWE,
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output reg DQML,
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output reg DQMH,
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output reg RCKE,
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output reg [7:0] RD,
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/* SPI NOR flash */
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output reg nFCS,
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output reg FCK,
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inout MISO,
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inout MOSI);
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/* PHI0 synchronization signals */
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reg PHI0r0, PHI0r1;
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always @(negedge C25M) begin PHI0r0 <= PHI0; end
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always @(posedge C25M) begin PHI0r1 <= PHI0r0; end
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/* Reset synchronization */
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reg nRESr0, nRESr;
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always @(negedge C25M) nRESr0 <= nRESin;
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always @(posedge C25M) nRESr <= nRESr0;
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wire RES = RES;
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/* Firmware select */
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input [1:0] SetFW;
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reg [1:0] SetFWr;
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reg SetFWLoaded = 0;
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always @(posedge C25M) begin
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if (!SetFWLoaded) begin
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SetFWLoaded <= 1;
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SetFWr[1:0] <= SetFW[1:0];
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end
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end
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wire [1:0] SetROM = ~SetFWr[1:0];
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wire SetEN16MB = SetROM[1:0]==2'b11;
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wire SetEN24b = SetROM[1];
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/* State counters */
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reg [2:0] IS = 0;
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reg [24:0] S = 0;
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wire Ready = IS[2];
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/* Reset output disable */
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assign nRESout = Ready;
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/* Init state counter control */
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// IS 0 - wait and issue NOP CKE (ends at S[19:0]==20'hFFFFF)
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// IS 1 - Load mode and AREF, issue SPI NOR read (ends at S[4:0]==5'h3F)
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// IS 2 - Write driver (ends at S[16:0]==17'h1FFFF)
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// IS 3 - Write image (ends at S[24:0]==25'h1FFFFFF)
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// IS 7 - Operating mode
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always @(posedge C25M) begin
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case (IS[2:0]) begin
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3'h0: if (S[19:0]== 20'hFFFFF) IS[2:0] <= 3'h1;
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3'h1: if (S[19:0]== 5'h3F) IS[2:0] <= 3'h2;
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3'h2: if (S[19:0]== 17'h1FFFF) IS[2:0] <= 3'h3;
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3'h3: if (S[19:0]==25'h1FFFFFF) IS[2:0] <= 3'h7;
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end
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end
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/* RAM state counter control */
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always @(posedge C25M) begin
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if (IS[2:0]==3'h0 && S[19:0]== 20'hFFFFF ||
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IS[2:0]==3'h1 && S[19:0]== 5'h3F ||
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IS[2:0]==3'h2 && S[19:0]== 17'h1FFFF ||
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IS[2:0]==3'h3 && S[19:0]==25'h1FFFFFF) S <= 0;
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else if (Ready) begin
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S[24:4] <= 0;
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if (S[3:0]==0 && PHI0r1) S[2:0] <= 4'h1;
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else if (S[3:0]!=0) S[3:0] <= S[3:0]+4'h1;
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end else S[24:0] <= S[24:0]+25'h1;
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end
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/* IOROMEN control */
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reg IOROMEN = 0;
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always @(posedge C25M) begin
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if (RES) IOROMEN <= 0;
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else if (S[2:0]==3'h2) begin
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if (!nIOSTRB && BA[10:0]==11'h7FF) IOROMEN <= 0;
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else if (!nIOSEL) IOROMEN <= 1;
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end
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end
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/* RegEN control */
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reg RegEN = 0;
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always @(posedge C25M) begin
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if (RES) RegEN <= 0;
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else if (S[2:0]==3'h2 && !nIOSEL) RegEN <= 1;
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end
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/* ROM bank register */
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reg Bank = 0;
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always @(posedge C25M, negedge nRESr) begin
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if (RES) Bank <= 0;
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else if (S[2:0]==3'h4 && BankSEL && !nWEr) begin
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Bank <= RD[0];
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end
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end
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/* RAMROMCS command signal */
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reg RAMROMCS;
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always @(posedge C25M) begin
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if (S[3:0]==4'h0) RAMROMCS <= !RES &&PHI0r1 && BA[15:12]==4'hC;
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else if S[3:0]==4'h1) begin
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RAMROMCS <= !RES && (
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(!nIOSEL) ||
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(!nIOSTRB && IOROMEN) ||
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(!nDEVSEL && RegEN && A[3:0]==4'h3));
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end else if (S[3:0]==4'h9) RAMROMCS <= !RES && RefC[2:0]==0;
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end
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/* Register select command signals */
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reg RAMRegSEL;
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reg AddrHWR, AddrMWR, AddrLWR;
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always @(posedge C25M) begin
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RAMRegSEL <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h3;
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AddrHWR <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h2;
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AddrMWR <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h1;
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AddrLWR <= !RES && S[3:0]==4'h6 !nDEVSEL && BA[3:0]==4'h0;
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end
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/* Slinky address registers */
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reg [23:0] Addr = 0;
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reg AddrIncL = 0;
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reg AddrIncM = 0;
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reg AddrIncH = 0;
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always @(posedge C25M, negedge nRESr) begin
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if (RES) begin
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Addr[23:0] <= 0;
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AddrIncL <= 0;
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AddrIncM <= 0;
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AddrIncH <= 0;
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end else begin
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if (RAMRegSEL) AddrIncL <= 1;
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else AddrIncL <= 0;
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if (AddrLWR) begin
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Addr[7:0] <= RD[7:0];
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AddrIncM <= Addr[7] && !RD[7];
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end else if (AddrIncL) begin
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Addr[7:0] <= Addr[7:0]+1;
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AddrIncM <= Addr[7:0]==8'hFF;
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end else AddrIncM <= 0;
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if (AddrMWR) begin
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Addr[15:8] <= RD[7:0];
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AddrIncH <= Addr[15] && !RD[7];
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end else if (AddrIncM) begin
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Addr[15:8] <= Addr[15:8]+1;
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AddrIncH <= Addr[15:8]==8'hFF;
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end else AddrIncH <= 0;
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if (AddrHWR) begin
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Addr[23:16] <= RD[7:0];
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end else if (AddrIncH) begin
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Addr[23:16] <= Addr[23:16]+1;
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end
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end
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end
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/* Apple II data output latch */
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reg [7:0] BDout;
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always @(negedge C25M) begin
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if (S[2:0]==4'h6) begin
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if (!nDEVSEL) case (BA[1:0])
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4'h3: BDout[7:0] <= RD[7:0];
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4'h2: BDout[7:0] <= SetEN24b ? Addr[23:16] { 4'hF, Addr[19:16] };
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4'h1: BDout[7:0] <= Addr[15:8];
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4'h0: BDout[7:0] <= Addr[7:0];
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defaut: BDout[7:0] <= 0;
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endcase else BDout[7:0] <= RD[7:0];
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end
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end
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always @(posedge C25M) begin
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case (IS[2:0])
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3'h0: begin
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// NOP CKE
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end 3'h1: case (S[4:0])
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5'h00: begin
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// PC all CKE
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end 5'h08: begin
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// LDM CKE
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end 5'h10, 5'h12, 5'h14, 5'h16,
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5'h18, 5'h1A, 5'h1C, 5'h1E: begin
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// AREF CKE
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end default: begin
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// NOP CKE
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end
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endcase 3'h2, 3'h3: case (S[2:0])
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3'h0: begin
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// NOP CKE
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end 3'h1: begin
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// AREF CKE
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end 3'h2: begin
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// NOP CKE
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end 3'h3: begin
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// ACT CKE
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end 3'h4: begin
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// WR CKE
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end 3'h5: begin
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// WR CKE
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end 3'h6: begin
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// NOP CKE
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end 3'h7: begin
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// PC all CKD
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end
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endcase default: case (S[3:0])
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4'h1: begin
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if (!RAMROMCS) begin
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// NOP CKD
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end else if (nWE) begin
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// NOP CKE
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end else begin
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// NOP CKD
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end
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end 4'h2: begin
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if (!RAMROMCS) begin
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// NOP CKD
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end else if (nWE) begin
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// ACT CKE
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end else begin
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// NOP CKD
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end
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end 4'h3: begin
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if (!RAMROMCS) begin
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// NOP CKD
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end else if (nWE) begin
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// RD CKE
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end else begin
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// NOP CKD
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end
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end 4'h4: begin
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if (!RAMROMCS) begin
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// NOP CKD
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end else if (nWE) begin
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// PC all CKE
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end else begin
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// NOP CKD
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end
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end 4'h5: begin
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if (!RAMROMCS) begin
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// NOP CKD
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end else if (nWE) begin
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// NOP CKD
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end else begin
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// NOP CKE
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end
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end 4'h6: begin
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if (!RAMROMCS) begin
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// NOP CKD
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end else if (nWE) begin
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// NOP CKD
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end else begin
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// ACT CKE
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end
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end 4'h7: begin
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if (!RAMROMCS) begin
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// NOP CKD
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end else if (nWE) begin
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// NOP CKD
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end else begin
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// WR CKE
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end
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end 4'h8: begin
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if (!RAMROMCS) begin
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// NOP CKD
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end else if (nWE) begin
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// NOP CKD
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end else begin
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// NOP CKE
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end
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end 4'h9: begin
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if (!RAMROMCS) begin
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// NOP CKD
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end else if (nWE) begin
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// NOP CKD
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end else begin
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// PC all CKD
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end
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end 4'hA: begin
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if (!RAMROMCS) begin
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// NOP CKD
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end else begin
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// NOP CKE
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end
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end 4'hB: begin
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if (!RAMROMCS) begin
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// NOP CKD
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end else begin
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// AREF CKE
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end
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end default: begin
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// NOP CKD
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end
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endcase
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endcase
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end
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/* DMA/INT in/out */
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input INTin, DMAin;
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output INTout = INTin;
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output DMAout = DMAin;
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/* Unused Pins */
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output RAdir = 1;
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output nDMAout = 1;
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output nNMIout = 1;
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output nINHout = 1;
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output nRDYout = 1;
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output nIRQout = 1;
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output RWout = 1;
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endmodule
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