788 lines
65 KiB
Plaintext
788 lines
65 KiB
Plaintext
Timing Analyzer report for GR8RAM
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Tue Mar 28 12:29:28 2023
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Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Timing Analyzer Summary
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3. Parallel Compilation
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4. SDC File List
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5. Clocks
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6. Fmax Summary
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7. Setup Summary
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8. Hold Summary
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9. Recovery Summary
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10. Removal Summary
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11. Minimum Pulse Width Summary
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12. Setup: 'C25M'
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13. Hold: 'C25M'
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14. Recovery: 'C25M'
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15. Removal: 'C25M'
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16. Setup Transfers
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17. Hold Transfers
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18. Recovery Transfers
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19. Removal Transfers
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20. Report TCCS
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21. Report RSKM
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22. Unconstrained Paths Summary
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23. Clock Status Summary
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24. Unconstrained Input Ports
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25. Unconstrained Output Ports
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26. Unconstrained Input Ports
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27. Unconstrained Output Ports
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28. Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2019 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+-----------------------------------------------------------------------------+
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; Timing Analyzer Summary ;
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+-----------------------+-----------------------------------------------------+
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; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ;
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; Timing Analyzer ; Legacy Timing Analyzer ;
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; Revision Name ; GR8RAM ;
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; Device Family ; MAX II ;
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; Device Name ; EPM240T100C5 ;
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; Timing Models ; Final ;
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; Delay Model ; Slow Model ;
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; Rise/Fall Delays ; Unavailable ;
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+-----------------------+-----------------------------------------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 1 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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+----------------------------+-------------+
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+---------------------------------------------------+
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; SDC File List ;
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+---------------+--------+--------------------------+
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; SDC File Path ; Status ; Read at ;
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+---------------+--------+--------------------------+
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; GR8RAM.sdc ; OK ; Tue Mar 28 12:29:28 2023 ;
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+---------------+--------+--------------------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Clocks ;
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+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
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; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
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+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
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; C25M ; Base ; 40.000 ; 25.0 MHz ; 0.000 ; 20.000 ; ; ; ; ; ; ; ; ; ; ; { C25M } ;
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; PHI0 ; Base ; 978.000 ; 1.02 MHz ; 0.000 ; 489.000 ; ; ; ; ; ; ; ; ; ; ; { PHI0 } ;
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+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
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+-------------------------------------------------+
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; Fmax Summary ;
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+-----------+-----------------+------------+------+
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; Fmax ; Restricted Fmax ; Clock Name ; Note ;
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+-----------+-----------------+------------+------+
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; 87.68 MHz ; 87.68 MHz ; C25M ; ;
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+-----------+-----------------+------------+------+
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This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
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+--------------------------------+
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; Setup Summary ;
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+-------+--------+---------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+---------------+
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; C25M ; 14.455 ; 0.000 ;
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+-------+--------+---------------+
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+-------------------------------+
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; Hold Summary ;
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+-------+-------+---------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+-------+---------------+
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; C25M ; 1.374 ; 0.000 ;
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+-------+-------+---------------+
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+--------------------------------+
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; Recovery Summary ;
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+-------+--------+---------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+---------------+
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; C25M ; 34.082 ; 0.000 ;
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+-------+--------+---------------+
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+-------------------------------+
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; Removal Summary ;
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+-------+-------+---------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+-------+---------------+
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; C25M ; 5.364 ; 0.000 ;
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+-------+-------+---------------+
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+---------------------------------+
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; Minimum Pulse Width Summary ;
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+-------+---------+---------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+---------+---------------+
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; C25M ; 19.734 ; 0.000 ;
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; PHI0 ; 974.000 ; 0.000 ;
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+-------+---------+---------------+
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+----------------------------------------------------------------------------------------------------------------+
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; Setup: 'C25M' ;
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+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
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; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
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+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
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; 14.455 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.212 ;
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; 14.456 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.211 ;
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; 14.456 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.211 ;
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; 14.456 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.211 ;
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; 14.549 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.118 ;
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; 14.550 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.117 ;
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; 14.550 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.117 ;
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; 14.550 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.117 ;
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; 14.596 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.071 ;
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; 14.690 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.977 ;
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; 14.774 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.893 ;
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; 14.775 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.892 ;
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; 14.775 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.892 ;
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; 14.775 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.892 ;
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; 14.915 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.752 ;
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; 15.094 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.573 ;
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; 15.114 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.553 ;
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; 15.114 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.553 ;
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; 15.115 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.552 ;
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; 15.115 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.552 ;
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; 15.115 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.552 ;
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; 15.156 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.511 ;
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; 15.156 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.511 ;
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; 15.185 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.482 ;
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; 15.250 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.417 ;
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; 15.250 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.417 ;
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; 15.255 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.412 ;
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; 15.352 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.315 ;
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; 15.365 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.302 ;
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; 15.475 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.192 ;
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; 15.475 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.192 ;
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; 15.494 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.173 ;
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; 15.532 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.135 ;
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; 15.569 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.098 ;
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; 15.599 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.068 ;
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; 15.646 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.021 ;
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; 15.650 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.017 ;
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; 15.659 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.008 ;
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; 15.663 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.004 ;
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; 15.667 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.000 ;
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; 15.684 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.983 ;
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; 15.712 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.955 ;
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; 15.720 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.947 ;
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; 15.755 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.912 ;
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; 15.779 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.888 ;
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; 15.795 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.872 ;
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; 15.815 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.852 ;
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; 15.815 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.852 ;
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; 15.888 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.779 ;
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; 16.002 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.665 ;
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; 16.004 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.663 ;
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; 16.098 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.569 ;
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; 16.175 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.492 ;
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; 16.228 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.439 ;
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; 16.304 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.363 ;
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; 16.850 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.817 ;
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; 28.595 ; IS.state_bit_0 ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.072 ;
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; 28.644 ; IS.state_bit_0 ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 11.023 ;
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; 28.780 ; IS.state_bit_0 ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.887 ;
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; 28.904 ; IS.state_bit_0 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.763 ;
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; 29.057 ; IS.state_bit_0 ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.610 ;
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; 29.188 ; Addr[23] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.479 ;
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; 29.237 ; Addr[23] ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.430 ;
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; 29.317 ; IS.state_bit_0 ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.350 ;
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; 29.332 ; IS.state_bit_1 ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.335 ;
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; 29.373 ; Addr[23] ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.294 ;
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; 29.381 ; IS.state_bit_1 ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.286 ;
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; 29.492 ; Addr[23] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.175 ;
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; 29.497 ; Addr[23] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.170 ;
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; 29.517 ; IS.state_bit_1 ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.150 ;
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; 29.544 ; LS[10] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.123 ;
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; 29.640 ; Addr[23] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.027 ;
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; 29.641 ; IS.state_bit_1 ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.026 ;
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; 29.650 ; Addr[23] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 10.017 ;
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; 29.673 ; LS[8] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.994 ;
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; 29.740 ; REGEN ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.927 ;
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; 29.764 ; LS[10] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.903 ;
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; 29.789 ; REGEN ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.878 ;
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; 29.794 ; IS.state_bit_1 ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.873 ;
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; 29.855 ; LS[11] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.812 ;
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; 29.893 ; LS[8] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.774 ;
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; 29.910 ; Addr[23] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.757 ;
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; 29.925 ; REGEN ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.742 ;
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; 30.044 ; REGEN ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.623 ;
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; 30.049 ; REGEN ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.618 ;
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; 30.054 ; IS.state_bit_1 ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.613 ;
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; 30.075 ; LS[11] ; IS.state_bit_0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.592 ;
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; 30.086 ; Addr[23] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.581 ;
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; 30.096 ; PS[3] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.571 ;
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; 30.145 ; PS[3] ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.522 ;
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; 30.177 ; LS[6] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.490 ;
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; 30.192 ; REGEN ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.475 ;
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; 30.202 ; REGEN ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.465 ;
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; 30.212 ; LS[9] ; IS.state_bit_1 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.455 ;
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; 30.230 ; IS.state_bit_0 ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.437 ;
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; 30.278 ; LS[10] ; IS.state_bit_2 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.389 ;
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; 30.281 ; PS[3] ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 9.386 ;
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; 30.336 ; PS[3] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.331 ;
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; 30.336 ; PS[3] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.331 ;
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; 30.336 ; PS[3] ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 9.331 ;
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+--------+----------------+----------------+--------------+-------------+--------------+------------+------------+
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+---------------------------------------------------------------------------------------------------------------+
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; Hold: 'C25M' ;
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+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
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; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
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+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
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; 1.374 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.595 ;
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; 1.403 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.624 ;
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; 1.413 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.634 ;
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; 1.650 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.871 ;
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; 1.699 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.920 ;
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; 1.854 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.075 ;
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; 1.964 ; IS.state_bit_0 ; IS.state_bit_0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.185 ;
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; 1.970 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.191 ;
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; 1.986 ; IS.state_bit_1 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.207 ;
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; 2.004 ; IS.state_bit_1 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.225 ;
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; 2.107 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ;
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; 2.108 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 2.329 ;
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; 2.117 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
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; 2.117 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
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; 2.118 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.339 ;
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; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ;
|
|
; 2.126 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
|
|
; 2.126 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
|
|
; 2.126 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
|
|
; 2.127 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ;
|
|
; 2.133 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ;
|
|
; 2.133 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.354 ;
|
|
; 2.135 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.356 ;
|
|
; 2.136 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.357 ;
|
|
; 2.142 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.363 ;
|
|
; 2.144 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
|
|
; 2.145 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ;
|
|
; 2.151 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ;
|
|
; 2.153 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.374 ;
|
|
; 2.172 ; PS[3] ; nRCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.393 ;
|
|
; 2.211 ; IS.state_bit_1 ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.432 ;
|
|
; 2.213 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.434 ;
|
|
; 2.221 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.442 ;
|
|
; 2.230 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
|
|
; 2.230 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.451 ;
|
|
; 2.231 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
|
|
; 2.231 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
|
|
; 2.231 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
|
|
; 2.231 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.452 ;
|
|
; 2.232 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
|
|
; 2.232 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
|
|
; 2.233 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.454 ;
|
|
; 2.239 ; RestoreDone ; RestoreDone ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ;
|
|
; 2.248 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.469 ;
|
|
; 2.249 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
|
|
; 2.249 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
|
|
; 2.250 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ;
|
|
; 2.251 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ;
|
|
; 2.256 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.477 ;
|
|
; 2.259 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.480 ;
|
|
; 2.260 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ;
|
|
; 2.260 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.481 ;
|
|
; 2.262 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.483 ;
|
|
; 2.266 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.487 ;
|
|
; 2.275 ; PS[1] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.496 ;
|
|
; 2.275 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.496 ;
|
|
; 2.294 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.515 ;
|
|
; 2.422 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.643 ;
|
|
; 2.440 ; PS[3] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.661 ;
|
|
; 2.525 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.746 ;
|
|
; 2.529 ; PHI0r2 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.750 ;
|
|
; 2.581 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.802 ;
|
|
; 2.591 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.812 ;
|
|
; 2.616 ; PS[3] ; SA[2]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.837 ;
|
|
; 2.634 ; AddrIncH ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.855 ;
|
|
; 2.653 ; AddrIncL ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.874 ;
|
|
; 2.666 ; nRESr ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.887 ;
|
|
; 2.716 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.937 ;
|
|
; 2.736 ; PS[1] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.957 ;
|
|
; 2.936 ; Addr[7] ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 3.157 ;
|
|
; 2.949 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
|
|
; 2.949 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
|
|
; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ;
|
|
; 2.958 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
|
|
; 2.958 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
|
|
; 2.959 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ;
|
|
; 2.965 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ;
|
|
; 2.965 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.186 ;
|
|
; 2.968 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.189 ;
|
|
; 2.974 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.195 ;
|
|
; 2.976 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
|
|
; 2.983 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.204 ;
|
|
; 2.985 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.206 ;
|
|
; 3.039 ; Bank ; nFCS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.260 ;
|
|
; 3.040 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.261 ;
|
|
; 3.041 ; PS[2] ; nCAS~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.262 ;
|
|
; 3.060 ; Addr[2] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
|
|
; 3.060 ; Addr[1] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.281 ;
|
|
; 3.067 ; PS[0] ; SA[2]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 3.288 ;
|
|
; 3.068 ; Addr[8] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.289 ;
|
|
; 3.069 ; Addr[10] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ;
|
|
; 3.069 ; Addr[17] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.290 ;
|
|
; 3.070 ; Addr[18] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.291 ;
|
|
; 3.076 ; Addr[16] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.297 ;
|
|
; 3.076 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.297 ;
|
|
; 3.079 ; Addr[9] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.300 ;
|
|
; 3.085 ; Addr[0] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.306 ;
|
|
; 3.087 ; LS[4] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.308 ;
|
|
; 3.094 ; LS[8] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.315 ;
|
|
; 3.096 ; LS[9] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.317 ;
|
|
+-------+----------------+----------------+--------------+-------------+--------------+------------+------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------+
|
|
; Recovery: 'C25M' ;
|
|
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
|
; 34.082 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
; 34.082 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 5.585 ;
|
|
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------+
|
|
; Removal: 'C25M' ;
|
|
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
|
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
|
; 5.364 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
; 5.364 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 5.585 ;
|
|
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------+
|
|
; Setup Transfers ;
|
|
+------------+----------+------------+------------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------+----------+------------+------------+----------+----------+
|
|
; C25M ; C25M ; 1404 ; 0 ; 56 ; 0 ;
|
|
; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ;
|
|
+------------+----------+------------+------------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
+-----------------------------------------------------------------------+
|
|
; Hold Transfers ;
|
|
+------------+----------+------------+------------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------+----------+------------+------------+----------+----------+
|
|
; C25M ; C25M ; 1404 ; 0 ; 56 ; 0 ;
|
|
; PHI0 ; C25M ; false path ; false path ; 0 ; 0 ;
|
|
+------------+----------+------------+------------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
+-------------------------------------------------------------------+
|
|
; Recovery Transfers ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; C25M ; C25M ; 28 ; 0 ; 0 ; 0 ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
+-------------------------------------------------------------------+
|
|
; Removal Transfers ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; C25M ; C25M ; 28 ; 0 ; 0 ; 0 ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
---------------
|
|
; Report TCCS ;
|
|
---------------
|
|
No dedicated SERDES Transmitter circuitry present in device or used in design
|
|
|
|
|
|
---------------
|
|
; Report RSKM ;
|
|
---------------
|
|
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
|
|
|
|
|
|
+------------------------------------------------+
|
|
; Unconstrained Paths Summary ;
|
|
+---------------------------------+-------+------+
|
|
; Property ; Setup ; Hold ;
|
|
+---------------------------------+-------+------+
|
|
; Illegal Clocks ; 0 ; 0 ;
|
|
; Unconstrained Clocks ; 0 ; 0 ;
|
|
; Unconstrained Input Ports ; 44 ; 44 ;
|
|
; Unconstrained Input Port Paths ; 906 ; 906 ;
|
|
; Unconstrained Output Ports ; 44 ; 44 ;
|
|
; Unconstrained Output Port Paths ; 115 ; 115 ;
|
|
+---------------------------------+-------+------+
|
|
|
|
|
|
+-------------------------------------+
|
|
; Clock Status Summary ;
|
|
+--------+-------+------+-------------+
|
|
; Target ; Clock ; Type ; Status ;
|
|
+--------+-------+------+-------------+
|
|
; C25M ; C25M ; Base ; Constrained ;
|
|
; PHI0 ; PHI0 ; Base ; Constrained ;
|
|
+--------+-------+------+-------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Input Ports ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; Input Port ; Comment ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; DMAin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; INTin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; MISO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; MOSI ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; PHI0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRES ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Output Ports ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; Output Port ; Comment ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; DMAout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; FCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; INTout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; MOSI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RDdir ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nFCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRESout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nSWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Input Ports ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; Input Port ; Comment ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
; DMAin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; INTin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; MISO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; MOSI ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; PHI0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RA[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRES ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+------------+--------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Output Ports ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; Output Port ; Comment ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; DMAout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; FCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; INTout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; MOSI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; RDdir ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; SD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nFCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nRESout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; nSWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
|
|
|
|
+--------------------------+
|
|
; Timing Analyzer Messages ;
|
|
+--------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus Prime Timing Analyzer
|
|
Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition
|
|
Info: Processing started: Tue Mar 28 12:29:27 2023
|
|
Info: Command: quartus_sta GR8RAM -c GR8RAM
|
|
Info: qsta_default_script.tcl version: #1
|
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
|
Info (21077): Low junction temperature is 0 degrees C
|
|
Info (21077): High junction temperature is 85 degrees C
|
|
Info (334003): Started post-fitting delay annotation
|
|
Info (334004): Delay annotation completed successfully
|
|
Info (332104): Reading SDC File: 'GR8RAM.sdc'
|
|
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
|
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
|
|
Info (332146): Worst-case setup slack is 14.455
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 14.455 0.000 C25M
|
|
Info (332146): Worst-case hold slack is 1.374
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 1.374 0.000 C25M
|
|
Info (332146): Worst-case recovery slack is 34.082
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 34.082 0.000 C25M
|
|
Info (332146): Worst-case removal slack is 5.364
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 5.364 0.000 C25M
|
|
Info (332146): Worst-case minimum pulse width slack is 19.734
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 19.734 0.000 C25M
|
|
Info (332119): 974.000 0.000 PHI0
|
|
Info (332001): The selected device family is not supported by the report_metastability command.
|
|
Info (332102): Design is not fully constrained for setup requirements
|
|
Info (332102): Design is not fully constrained for hold requirements
|
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
|
|
Info: Peak virtual memory: 13053 megabytes
|
|
Info: Processing ended: Tue Mar 28 12:29:28 2023
|
|
Info: Elapsed time: 00:00:01
|
|
Info: Total CPU time (on all processors): 00:00:01
|
|
|
|
|