565 lines
15 KiB
Verilog
565 lines
15 KiB
Verilog
module GR8RAM(C25M, PHI0, nRES, nRESout, SetFW,
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INTin, INTout, DMAin, DMAout,
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nNMIout, nIRQout, nRDYout, nINHout, RWout, nDMAout,
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RA, nWE, RD, RAdir, RDdir, nIOSEL, nDEVSEL, nIOSTRB,
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SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
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nFCS, FCK, MISO, MOSI);
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/* Clock signals */
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input C25M, PHI0;
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reg PHI0r1, PHI0r2;
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always @(posedge C25M) begin PHI0r1 <= PHI0; PHI0r2 <= PHI0r1; end
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/* Reset filter */
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input nRES;
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reg [3:0] nRESf = 0;
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reg nRESr = 0;
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always @(posedge C25M) begin
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nRESf[3:0] <= { nRESf[2:0], nRES };
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nRESr <= nRESf[3] || nRESf[2] || nRESf[1] || nRESf[0];
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end
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/* Firmware select */
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input [1:0] SetFW;
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wire [1:0] SetROM = 2'b00;
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wire SetEN16MB = 0;
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wire SetEN24bit = 1;
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/* State counter from PHI0 rising edge */
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reg [3:0] PS = 0;
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wire PSStart = PS==0 && PHI0r1 && ~PHI0r2;
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always @(posedge C25M) begin
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if (PSStart) PS <= 1;
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else if (PS==0) PS <= 0;
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else PS <= PS+1;
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end
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/* Long state counter: counts from 0 to $3FFF */
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reg [13:0] LS = 0;
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always @(posedge C25M) begin if (PS==15) LS <= LS+1; end
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/* Init state */
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output reg nRESout = 0;
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reg [2:0] IS = 0;
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always @(posedge C25M) begin
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if (IS==7) nRESout <= 1;
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else if (PS==15) begin
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if (LS==14'h1FCE) IS <= 1; // PC all + load mode
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else if (LS==14'h1FCF) IS <= 4; // AREF pause, SPI select
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else if (LS==14'h1FFA) IS <= 5; // SPI flash command
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else if (LS==14'h1FFF) IS <= 6; // Flash load driver
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else if (LS==14'h3FFF) IS <= 7; // Operating mode
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end
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end
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/* Apple IO area select signals */
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input nIOSEL, nDEVSEL, nIOSTRB;
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/* Apple address bus */
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input [15:0] RA; input nWE;
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reg [11:0] RAr; reg nWEr;
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reg CXXXr;
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always @(posedge PHI0) begin
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CXXXr <= RA[15:12]==4'hC;
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RAr[11:0] <= RA[11:0];
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nWEr <= nWE;
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end
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/* Apple select signals */
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wire ROMSpecRD = CXXXr && RAr[11:8]!=4'h0 && nWEr && ((RAr[11] && IOROMEN) || (~RAr[11]));
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wire REGSpecSEL = CXXXr && RAr[11:8]==4'h0 && RAr[7] && REGEN;
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wire BankSpecSEL = REGSpecSEL && RAr[3:0]==4'hF;
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wire SPITX1SpecSEL = REGSpecSEL && RAr[3:0]==4'hD;
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wire SPITX0SpecSEL = REGSpecSEL && RAr[3:0]==4'hC;
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wire RAMRegSpecSEL = REGSpecSEL && RAr[3:0]==4'h3;
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wire RAMSpecSEL = RAMRegSpecSEL && (~SetEN24bit || SetEN16MB || ~Addr[23]);
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wire AddrHSpecSEL = REGSpecSEL && RAr[3:0]==4'h2;
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wire AddrMSpecSEL = REGSpecSEL && RAr[3:0]==4'h1;
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wire AddrLSpecSEL = REGSpecSEL && RAr[3:0]==4'h0;
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wire BankSEL = REGEN && ~nDEVSEL && BankSpecSEL;
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wire RAMRegSEL = ~nDEVSEL && RAMRegSpecSEL;
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wire RAMSEL = ~nDEVSEL && RAMSpecSEL;
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wire RAMWR = RAMSEL && ~nWEr;
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wire AddrHSEL = REGEN && ~nDEVSEL && AddrHSpecSEL;
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wire AddrMSEL = REGEN && ~nDEVSEL && AddrMSpecSEL;
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wire AddrLSEL = REGEN && ~nDEVSEL && AddrLSpecSEL;
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/* IOROMEN and REGEN control */
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reg IOROMEN = 0;
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reg REGEN = 0;
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reg nIOSTRBr;
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wire IOROMRES = RAr[10:0]==11'h7FF && ~nIOSTRB && ~nIOSTRBr;
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always @(posedge C25M, negedge nRESr) begin
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if (~nRESr) REGEN <= 0;
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else if (PS==8 && ~nIOSEL) REGEN <= 1;
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end
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always @(posedge C25M) begin
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nIOSTRBr <= nIOSTRB;
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if (~nRESr) IOROMEN <= 0;
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else if (PS==8 && IOROMRES) IOROMEN <= 0;
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else if (PS==8 && ~nIOSEL) IOROMEN <= 1;
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end
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/* Apple data bus */
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inout [7:0] RD = RDdir ? 8'bZ : RDD[7:0];
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reg [7:0] RDD;
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output RDdir = ~(PHI0r2 && nWE && PHI0 &&
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(~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN && RA[10:0]!=11'h7FF)));
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/* Slinky address registers */
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reg [23:0] Addr = 0;
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reg AddrIncL = 0;
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reg AddrIncM = 0;
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reg AddrIncH = 0;
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always @(posedge C25M, negedge nRESr) begin
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if (~nRESr) begin
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Addr[23:0] <= 24'h000000;
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AddrIncL <= 0;
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AddrIncM <= 0;
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AddrIncH <= 0;
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end else begin
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if (PS==8 && RAMRegSEL) AddrIncL <= 1;
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else AddrIncL <= 0;
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if (PS==8 && AddrLSEL && ~nWEr) begin
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Addr[7:0] <= RD[7:0];
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AddrIncM <= Addr[7] && ~RD[7];
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end else if (AddrIncL) begin
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Addr[7:0] <= Addr[7:0]+1;
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AddrIncM <= Addr[7:0]==8'hFF;
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end else AddrIncM <= 0;
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if (PS==8 && AddrMSEL && ~nWEr) begin
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Addr[15:8] <= RD[7:0];
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AddrIncH <= Addr[15] && ~RD[7];
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end else if (AddrIncM) begin
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Addr[15:8] <= Addr[15:8]+1;
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AddrIncH <= Addr[15:8]==8'hFF;
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end else AddrIncH <= 0;
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if (PS==8 && AddrHSEL && ~nWEr) begin
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Addr[23:16] <= RD[7:0];
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end else if (AddrIncH) begin
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Addr[23:16] <= Addr[23:16]+1;
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end
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end
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end
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/* ROM bank register */
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reg Bank = 0;
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reg RestoreDone = 0;
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always @(posedge C25M, negedge nRESr) begin
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if (~nRESr) Bank <= 0;
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else if (PS==8 && BankSEL && ~nWEr) begin
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if (!RestoreDone) begin
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RestoreDone <= RD[1:0]==2'b11;
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end else Bank <= RD[0];
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end
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end
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/* SPI flash control signals */
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output reg nFCS = 1;
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output FCK = FCKout;
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reg FCKout = 0;
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inout MOSI = MOSIOE ? MOSIout : 1'bZ;
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reg MOSIOE = 0;
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input MISO;
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always @(posedge C25M) begin
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case (PS[3:0])
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0: begin // NOP CKE
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FCKout <= 1'b1;
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end 1: begin // ACT
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FCKout <= ~(IS==5 || IS==6);
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end 2: begin // RD
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FCKout <= 1'b1;
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end 3: begin // NOP CKE
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FCKout <= ~(IS==5 || IS==6);
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end 4: begin // NOP CKE
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FCKout <= 1'b1;
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end 5: begin // NOP CKE
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FCKout <= ~(IS==5 || IS==6);
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end 6: begin // NOP CKE
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FCKout <= 1'b1;
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end 7: begin // NOP CKE
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FCKout <= ~(IS==5 || IS==6 || (!nDEVSEL && RestoreDone && (SPITX0SpecSEL || SPITX1SpecSEL)));
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end 8: begin // WR AP
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FCKout <= 1'b1;
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end 9: begin // NOP CKE
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FCKout <= ~(IS==5);
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end 10: begin // PC all
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FCKout <= 1'b1;
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end 11: begin // AREF
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FCKout <= ~(IS==5);
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end 12: begin // NOP CKE
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FCKout <= 1'b1;
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end 13: begin // NOP CKE
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FCKout <= ~(IS==5);
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end 14: begin // NOP CKE
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FCKout <= 1'b1;
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end 15: begin // NOP CKE
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FCKout <= ~(IS==5);
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end
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endcase
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nFCS <= !(IS==4 || IS==5 || IS==6 || Bank);
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MOSIOE <= IS==5 || IS==7;
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end
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/* SPI flash MOSI control */
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reg MOSIout = 0;
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always @(posedge C25M) begin
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case (PS[3:0])
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1: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b0; // Command bit 7
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3'h4: MOSIout <= 1'b0; // Address bit 23
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3'h5: MOSIout <= 1'b1; // Address bit 15
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3'h6: MOSIout <= 1'b0; // Address bit 7
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default MOSIout <= 1'b0;
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endcase
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end 3: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b0; // Command bit 6
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3'h4: MOSIout <= 1'b0; // Address bit 22
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3'h5: MOSIout <= SetROM[1]; // Address bit 14
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3'h6: MOSIout <= 1'b0; // Address bit 6
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default MOSIout <= 1'b0;
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endcase
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end 5: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 5
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3'h4: MOSIout <= 1'b0; // Address bit 21
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3'h5: MOSIout <= SetROM[0]; // Address bit 13
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3'h6: MOSIout <= 1'b0; // Address bit 5
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default MOSIout <= 1'b0;
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endcase
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end 7: begin
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if (nRES) case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 4
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3'h4: MOSIout <= 1'b0; // Address bit 20
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3'h5: MOSIout <= 1'b0; // Address bit 12
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3'h6: MOSIout <= 1'b0; // Address bit 4
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default MOSIout <= 1'b0;
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endcase else MOSIout <= RAr[0];
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end 9: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 3
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3'h4: MOSIout <= 1'b0; // Address bit 19
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3'h5: MOSIout <= 1'b0; // Address bit 11
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3'h6: MOSIout <= 1'b0; // Address bit 3
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default MOSIout <= 1'b0;
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endcase
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end 11: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b0; // Command bit 2
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3'h4: MOSIout <= 1'b0; // Address bit 18
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3'h5: MOSIout <= 1'b0; // Address bit 10
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3'h6: MOSIout <= 1'b0; // Address bit 2
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default MOSIout <= 1'b0;
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endcase
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end 13: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 1
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3'h4: MOSIout <= 1'b0; // Address bit 16
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3'h5: MOSIout <= 1'b0; // Address bit 9
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3'h6: MOSIout <= 1'b0; // Address bit 1
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default MOSIout <= 1'b0;
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endcase
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end 15: begin
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case (LS[2:0])
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3'h3: MOSIout <= 1'b1; // Command bit 0
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3'h4: MOSIout <= 1'b0; // Address bit 15
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3'h5: MOSIout <= 1'b0; // Address bit 7
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3'h6: MOSIout <= 1'b0; // Address bit 0
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default MOSIout <= 1'b0;
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endcase
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end
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endcase
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end
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/* SDRAM data bus */
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inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
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reg [7:0] WRD;
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reg SDOE = 0;
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always @(posedge C25M) begin
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case (PS[3:0])
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0: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 1: begin // ACT
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end 2: begin // RD
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 3: begin // NOP CKE
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end 4: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 5: begin // NOP CKE
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end 6: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 7: begin // NOP CKE
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end 8: begin // WR AP
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 9: begin // NOP CKE
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end 10: begin // PC all
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 11: begin // AREF
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end 12: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 13: begin // NOP CKE
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end 14: begin // NOP CKE
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if (IS==6) WRD[7:0] <= { WRD[5:0], MISO, MOSI };
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else WRD[7:0] <= RD[7:0];
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end 15: begin // NOP CKE
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end
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endcase
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end
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/* Apple data bus from SDRAM */
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always @(negedge C25M) begin
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if (PS==5) begin
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if (AddrLSpecSEL) RDD[7:0] <= Addr[7:0];
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else if (AddrMSpecSEL) RDD[7:0] <= Addr[15:8];
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else if (AddrHSpecSEL) RDD[7:0] <= { SetEN24bit ? Addr[23:20] : 4'hF, Addr[19:16] };
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else if (BankSpecSEL) RDD[7:0] <= { MISO, 7'h7F };
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else RDD[7:0] <= SD[7:0];
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end
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end
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/* SDRAM command */
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output reg RCKE = 1;
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output reg nRCS = 1;
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output reg nRAS = 1;
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output reg nCAS = 1;
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output reg nSWE = 1;
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wire RefReqd = LS[1:0] == 2'b11;
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always @(posedge C25M) begin
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case (PS[3:0])
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0: begin // NOP CKE / NOP CKD
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RCKE <= PSStart && (IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 1: begin // ACT CKE / NOP CKD (ACT)
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RCKE <= IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL));
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nRCS <= ~(IS==6 || (IS==7 && (ROMSpecRD || RAMSpecSEL)));
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nRAS <= 0;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 2: begin // RD CKE / NOP CKD (RD)
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RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
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nRCS <= ~(IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL));
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nRAS <= 1;
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nCAS <= 0;
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nSWE <= 1;
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SDOE <= 0;
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end 3: begin // NOP CKE / CKD
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RCKE <= IS==7 && nWEr && (ROMSpecRD || RAMSpecSEL);
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 4: begin // NOP CKD
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RCKE <= 0;
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 5: begin // NOP CKD
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RCKE <= 0;
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 6: begin // NOP CKD
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RCKE <= 0;
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 7: begin // NOP CKE / CKD
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RCKE <= IS==6 || (RAMWR && IS==7);
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 8: begin // WR AP CKE / NOP CKD (WR AP)
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RCKE <= IS==6 || (RAMWR && IS==7);
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nRCS <= ~(IS==6 || (RAMWR && IS==7));
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nRAS <= 1;
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nCAS <= 0;
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nSWE <= 0;
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SDOE <= IS==6 || (RAMWR && IS==7);
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end 9: begin // NOP CKE / NOP CKD
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RCKE <= 1;
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end 10: begin // PC all CKE / PC all CKD
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RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
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nRCS <= 0;
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nRAS <= 0;
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nCAS <= 1;
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nSWE <= 0;
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SDOE <= 0;
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end 11: begin // LDM CKE / AREF CKE / NOP CKD
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RCKE <= IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd);
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nRCS <= ~(IS==1 || IS==4 || IS==5 || IS==6 || (IS==7 && RefReqd));
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nRAS <= 0;
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nCAS <= 0;
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nSWE <= ~(IS==1);
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SDOE <= 0;
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end default: begin // NOP CKD
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RCKE <= 0;
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nRCS <= 1;
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nRAS <= 1;
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nCAS <= 1;
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nSWE <= 1;
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SDOE <= 0;
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end
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endcase
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end
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/* SDRAM address */
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output reg DQML = 1;
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output reg DQMH = 1;
|
|
output reg [1:0] SBA;
|
|
output reg [12:0] SA;
|
|
always @(posedge C25M) begin
|
|
case (PS[3:0])
|
|
0: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 1: begin // ACT
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
if (IS==6) begin
|
|
SBA[1:0] <= 2'b10;
|
|
SA[12:0] <= { 10'b0011000100, LS[12:10] };
|
|
end else if (RAMSpecSEL) begin
|
|
SBA[1:0] <= { 1'b0, 1'b0 };
|
|
SA[12:10] <= SetEN24bit ? Addr[22:20] : 3'b000;
|
|
SA[9:0] <= Addr[19:10];
|
|
end else begin
|
|
SBA[1:0] <= 2'b10;
|
|
SA[12:0] <= { 10'b0011000100, RestoreDone ? (nIOSEL ? 1'b0 : Bank) : 1'b1, RAr[11:10] };
|
|
end
|
|
end 2: begin // RD
|
|
if (RAMSpecSEL) begin
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
|
DQML <= Addr[0];
|
|
DQMH <= ~Addr[0];
|
|
end else begin
|
|
SBA[1:0] <= 2'b10;
|
|
SA[12:0] <= { 4'b0011, RAr[9:1]};
|
|
DQML <= RAr[0];
|
|
DQMH <= ~RAr[0];
|
|
end
|
|
end 3: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 4: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 5: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 6: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 7: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 8: begin // WR AP
|
|
if (IS==6) begin
|
|
SBA[1:0] <= 2'b10;
|
|
SA[12:0] <= { 4'b0011, LS[9:1] };
|
|
DQML <= LS[0];
|
|
DQMH <= ~LS[0];
|
|
end else begin
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= { 4'b0011, Addr[9:1] };
|
|
DQML <= Addr[0];
|
|
DQMH <= ~Addr[0];
|
|
end
|
|
end 9: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 10: begin // PC all
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 11: begin // AREF / load mode
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0001000100000;
|
|
end 12: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 13: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 14: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end 15: begin // NOP CKE
|
|
DQML <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
SBA[1:0] <= 2'b00;
|
|
SA[12:0] <= 13'b0011000100000;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
/* DMA/INT in/out */
|
|
input INTin, DMAin;
|
|
output INTout = INTin;
|
|
output DMAout = DMAin;
|
|
|
|
/* Unused Pins */
|
|
output RAdir = 1;
|
|
output nDMAout = 1;
|
|
output nNMIout = 1;
|
|
output nINHout = 1;
|
|
output nRDYout = 1;
|
|
output nIRQout = 1;
|
|
output RWout = 1;
|
|
endmodule
|