mirror of
https://github.com/garrettsworkshop/GR8RAM.git
synced 2024-12-12 08:30:08 +00:00
141 lines
4.7 KiB
Plaintext
141 lines
4.7 KiB
Plaintext
Init sequence
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Init State SDRAM Flash Other
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--------------------------------------------------------------------------------
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$000000-$0FFFBF Wait for Vcc Wait for Vcc
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$000000 NOP CKE /CS hi, CLK lo
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...
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$0FFF90 NOP CKE /CS hi, CLK lo InitActv <= ~BODf
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....
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$0FFFA0 NOP CKE /CS lo, CLK lo
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...
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$0FFFAF NOP CKE /CS lo, CLK lo
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$0FFFB0-$0FFFBF Init: Precharge Send read cmd ($03)
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$0FFFB0 PC all CLK lo, MOSI 0 (b7)
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$0FFFB1 NOP CKE CLK hi
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$0FFFB2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFFB3 NOP CKE CLK hi
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$0FFFB4 NOP CKE CLK lo, MOSI 0 (b5)
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$0FFFB5 NOP CKE CLK hi
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$0FFFB6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFFB7 NOP CKE CLK hi
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$0FFFB8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFFB9 NOP CKE CLK hi
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$0FFFBA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFFBB NOP CKE CLK hi
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$0FFFBC NOP CKE CLK lo, MOSI 1 (b1)
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$0FFFBD NOP CKE CLK hi
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$0FFFBE NOP CKE CLK lo, MOSI 1 (b0)
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$0FFFBF NOP CKE CLK hi
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$0FFFC0-$0FFFEF Init: mode & ref Send address ($000000)
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$0FFFC0 Load mode CLK lo, MOSI 0 (b23)
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$0FFFC1 NOP CKE CLK hi
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$0FFFC2 NOP CKE CLK lo, MOSI 0 (b22)
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$0FFFC3 NOP CKE CLK hi
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$0FFFC4 AREF CLK lo, MOSI Firmware[1] (b21)
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$0FFFC5 NOP CKE CLK hi
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$0FFFC6 NOP CKE CLK lo, MOSI Firmware[0] (b20)
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$0FFFC7 NOP CKE CLK hi
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$0FFFC8 NOP CKE CLK lo, MOSI 0 (b19)
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$0FFFC9 NOP CKE CLK hi
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$0FFFCA NOP CKE CLK lo, MOSI 0 (b18)
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$0FFFCB NOP CKE CLK hi
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$0FFFCC AREF CLK lo, MOSI 0 (b17)
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$0FFFCD NOP CKE CLK hi
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$0FFFCE NOP CKE CLK lo, MOSI 0 (b16)
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$0FFFCF NOP CKE CLK hi
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$0FFFD0 NOP CKE CLK lo, MOSI 0 (b15)
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$0FFFD1 NOP CKE CLK hi
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$0FFFD2 NOP CKE CLK lo, MOSI 0 (b14)
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$0FFFD3 NOP CKE CLK hi
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$0FFFD4 AREF CLK lo, MOSI 0 (b13)
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$0FFFD5 NOP CKE CLK hi
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$0FFFD6 NOP CKE CLK lo, MOSI 0 (b12)
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$0FFFD7 NOP CKE CLK hi
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$0FFFD8 NOP CKE CLK lo, MOSI 0 (b11)
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$0FFFD9 NOP CKE CLK hi
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$0FFFDA NOP CKE CLK lo, MOSI 0 (b10)
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$0FFFDB NOP CKE CLK hi
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$0FFFDC AREF CLK lo, MOSI 0 (b9)
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$0FFFDD NOP CKE CLK hi
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$0FFFDE NOP CKE CLK lo, MOSI 0 (b8)
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$0FFFDF NOP CKE CLK hi
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$0FFFE0 NOP CKE CLK lo, MOSI 0 (b7)
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$0FFFE1 NOP CKE CLK hi
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$0FFFE2 NOP CKE CLK lo, MOSI 0 (b6)
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$0FFFE3 NOP CKE CLK hi
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$0FFFE4 AREF CLK lo, MOSI 0 (b5)
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$0FFFE5 NOP CKE CLK hi
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$0FFFE6 NOP CKE CLK lo, MOSI 0 (b4)
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$0FFFE7 NOP CKE CLK hi
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$0FFFE8 NOP CKE CLK lo, MOSI 0 (b3)
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$0FFFE9 NOP CKE CLK hi
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$0FFFEA NOP CKE CLK lo, MOSI 0 (b2)
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$0FFFEB NOP CKE CLK hi
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$0FFFEC AREF CLK lo, MOSI 0 (b1)
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$0FFFED NOP CKE CLK hi
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$0FFFEE NOP CKE CLK lo, MOSI 0 (b0)
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$0FFFEF NOP CKE CLK hi
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$0FFFF0-$0FFFFF Init: mode & ref 8 dummy clocks
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$0FFFF0 NOP CKE CLK lo, MOSIOE 0
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$0FFFF1 NOP CKE CLK hi
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$0FFFF2 NOP CKE CLK lo
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$0FFFF3 NOP CKE CLK hi
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$0FFFF4 AREF CLK lo
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$0FFFF5 NOP CKE CLK hi
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$0FFFF6 NOP CKE CLK lo
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$0FFFF7 NOP CKE CLK hi
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$0FFFF8 NOP CKE CLK lo
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$0FFFF9 NOP CKE CLK hi
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$0FFFFA NOP CKE CLK lo
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$0FFFFB NOP CKE CLK hi
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$0FFFFC AREF CLK lo
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$0FFFFD NOP CKE CLK hi
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$0FFFFE NOP CKE CLK lo
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$0FFFFF NOP CKE CLK hi
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Write ROM data Shift in read data
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$100000 NOP CKE CLK lo
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$100001 NOP CKE CLK hi, get b7:6 of $000000
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$100002 NOP CKE CLK lo
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$100003 NOP CKE CLK hi, get b5:4 of $000000
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$100004 AREF CLK lo
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$100005 NOP CKE CLK hi, get b3:2 of $000000
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$100006 ACT CLK lo
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$100007 NOP CKE CLK hi, get b1:0 of $000000
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$100008 WR AP CLK lo
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$100009 NOP CKE CLK hi, get b7:6 of $000001
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$10000A NOP CKE CLK lo
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$10000B NOP CKE CLK hi, get b5:4 of $000001
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$10000C AREF CLK lo
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$10000D NOP CKE CLK hi, get b3:2 of $000001
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$10000E ACT CLK lo
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$10000F NOP CKE CLK hi, get b1:0 of $000001
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...
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$507FF0 WR AP CLK lo
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$503FF1 NOP CKE CLK hi, get b7:6 of $0807FE
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$503FF2 NOP CKE CLK lo
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$503FF3 NOP CKE CLK hi, get b5:4 of $0807FE
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$503FF4 AREF CLK lo
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$503FF5 NOP CKE CLK hi, get b3:2 of $0807FE
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$503FF6 ACT CLK lo
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$503FF7 NOP CKE CLK hi, get b1:0 of $0807FE
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$503FF8 WR AP CLK lo
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$503FF9 NOP CKE CLK hi, get b7:6 of $0807FF
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$503FFA NOP CKE CLK lo
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$503FFB NOP CKE CLK hi, get b5:4 of $0807FF
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$503FFC AREF CLK lo
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$503FFD NOP CKE CLK hi, get b3:2 of $0807FF
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$503FFE ACT CLK lo
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$503FFF NOP CKE CLK hi, get b1:0 of $0807FF
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$504000 WR AP CLK lo, /CS hi
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$504001 NOP CKE CLK lo
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...
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$50400F NOP CKE CLK lo
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$504010 NOP CKE SDRAMActv <= InitActv && ~InitInterrupted
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...
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$5F5E0F flip 1hz, wrap
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