514 lines
14 KiB
Verilog
514 lines
14 KiB
Verilog
module GR8RAM(C25M, PHI0, nPBOD, nBOD, nRES,
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nIOSEL, nDEVSEL, nIOSTRB,
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RA, nWE, nWEout, Adir,
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RD, Ddir,
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DMAin, DMAout, INTin, INTout,
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nDMA, nRDY, nNMI, nIRQ, nINH, nRESout
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SBA, SA, nRCS, nRAS, nCAS, nSWE, DQML, DQMH, RCKE, SD,
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nFCS, FCK, MISO, MOSI);
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/* Clock signals */
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/* Outputs: C25M, PHI0r1, PHI0r2, */
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input C25M, PHI0;
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reg PHI0r0, PHI0r1, PHI0r2;
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always @(negedge C25M) begin PHI0r0 <= PHI0; end
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always @(posedge C25M) begin PHI0r1 <= PHI0r0; PHI0r2 <= PHI0r1; end
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/* Reset/brown-out detect synchronized inputs */
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/* Outputs: nRESr, nPBODr, nBODf */
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input nRES, nPBOD, nBOD;
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reg nRESr0, nRESr;
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reg nPBODr0, nPBODr;
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reg nBODr0, nBODr, nBODf0, nBODf;
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always @(posedge C25M) begin
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// Double-synchronize nBOD, nPBOD, nRES
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nPBODr0 <= nPBOD; nBODr0 <= nBOD; nRESr0 <= nRES;
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nPBODr <= nPBODr0; nBODr <= nBODr0; nRESr <= nRESr0;
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// Filter nBODr to get nBODf. Output hi when hi for $5E0F-$10000 cycles
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if (LS[15:0]==16'h5E0F) begin // When LS low-order is $5E0F
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nBODf0 <= nBODr; // "Precharge" nBODf0
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nBODf <= nBODf0; // "Evaluate" computed nBODf0 into nBODf
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end else if (nBODr2) begin // Else AND nBODf0 with nBODr
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nBODf0 <= nBODf0 && nBODr;
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end
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end
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/* Long state counter: counts from 0 to $5F5E0F (6,249,999) *
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* CSec: 1/2 Hz clock */
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/* Outputs: LS, CSec */
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reg [22:0] LS = 0;
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reg [1:0] CSec = 0;
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reg LSEN = 0;
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always @(posedge C25M) begin
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// Allow LS to fully count once nBODf active
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if (nBODf) LSEN <= 1;
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// LS rolls over at 24'h5F5E0F or at 16'h5E0F when LSEN is 0
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if ((LS[22:16]==7'h5F || ~LSEN) && LS[15:0]==16'h5E0F) LS <= 0;
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else LS <= LS+1;
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// Flip 1/2 Hz clocks when LS==23'h5F5E0F
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if (LS[22:0]==23'h5F5E0F) CSec <= CSec+1;
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end
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/* Init state */
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output reg nRESout = 0;
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reg InitActv = 0;
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reg InitIntr = 0;
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reg SDRAMActv = 0;
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always @(posedge C25M) begin
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if (~nBODf) begin
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nRESout <= 0;
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InitActv <= 0;
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InitIntr <= 1;
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end else if (LS[22:0]==23'h0FFF10) begin
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InitActv <= ~AppleActive;
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InitIntr <= 0;
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end else if (LS[22:0]==23'h504010) begin
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nRESout <= InitActv && ~InitIntr;
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InitActv <= 0;
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SDRAMActv <= InitActv && ~InitIntr;
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end
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end
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/* Apple IO area select signals */
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/* Outputs: DEVSELr */
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input nIOSEL, nDEVSEL, nIOSTRB;
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reg DEVSELr0, DEVSELr;
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always @(negedge C25M) begin DEVSELr0 <= ~nDEVSEL; end
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always @(posedge C25M) begin DEVSELr <= DEVSELr0; end
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/* DMA/IRQ daisy chain */
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input DMAin, INTin;
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output DMAout = DMAin;
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output INTout = INTin;
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/* Apple open-drain outputs */
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output nDMA = 1;
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output nRDY = 1;
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output nNMI = 1;
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output nIRQ = ~(TIRQEN && TIRQMask);
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output nINH = 1;
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/* Apple address bus */
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/* Outputs: RAr1, nWEr1 */
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input [15:0] RA;
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input nWE;
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output RAdir = 1;
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output nWEout = 1;
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reg [15:0] RAr0; reg nWEr0;
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reg [15:0] RAcur; reg nWEcur;
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always @(negedge C25M) begin RAr0 <= RA; nWEr0 <= nWE; end
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always @(posedge C25M) begin
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if (S==0 && PHI0r1 && ~PHI0r2) begin
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RAcur[15:0] <= RAr0[15:0];
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nWEcur <= nWEr0;
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end
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end
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/* Apple select signals */
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/* Outputs: ROMSpecRD, RAMSpecSEL, RAMSpecRD, RAMSpecWR, RAMSEL */
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wire ROMSpecRD = RAcur[15:12]==4'hC && RAcur[11:8]!=4'h0 && nWEcur;
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wire RAMSpecSEL = RAcur[15:12]==4'hC && RAcur[11:8]==4'h0 && RAcur[7] && RAcur[7:4]!=4'h8 && RAcur[3:0]==4'h3;
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wire RAMSpecRD = RAMSpecSEL && nWEcur;
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wire RAMSpecWR = RAMSpecSEL && ~nWEcur;
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reg RAMSEL = 0;
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wire RAMWR = RAMSEL && ~nWEcur;
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always @(posedge C25M) begin
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if (S==5) RAMSEL <= RAMSpecSEL && DEVSELr;
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else if (S==0) RAMSEL <= 0;
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end
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/* Apple data bus */
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inout [7:0] RD = RDdir ? 8'bZ : RDout[7:0];
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reg [7:0] RDout;
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reg RDOE = 0;
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output RDdir = ~((~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOEN)) &&
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PHI0 && PHI0r2 && nWE && RDOE && ~BODf);
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/* Slinky address registers */
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reg [24:0] Addr;
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wire AddrHSpecSEL = RAcur[3:0]==4'h2;
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wire AddrMSpecSEL = RAcur[3:0]==4'h1;
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wire AddrLSpecSEL = RAcur[3:0]==4'h0;
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always @(posedge C25M) begin
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if (~nRESr) begin
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Addr[24] <= 1'b0;
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Addr[23:20] <= SetFW[1] ? 4'h0 : 4'hF;
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Addr[19:0] <= 20'h00000;
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end else if (S==7 && DEVSELr) begin
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if (AddrHSpecSEL || AddrMSpecSEL || AddrLSpecSEL) begin
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Addr[24] <= 1'b0;
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end
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if (AddrHSpecSEL) begin
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Addr[23:16] <= { SetFW[1] ? RD[7:4] : 4'hF, RD[3:0] };
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end else if ((RAMSEL && Addr[15:0]==16'hFFFF) ||
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(AddrMSpecSEL && Addr[15] && ~RD[7]) ||
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(AddrLSpecSEL && Addr[7] && ~RD[7] && Addr[15:8]==8'hFF)) begin
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Addr[23:16] <= Addr[23:16]+1;
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end
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if (AddrMSpecSEL) begin
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Addr[15:8] <= RD[7:0];
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end else if ((RAMSEL && Addr[7:0]==8'hFF) ||
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(AddrLSpecSEL && Addr[7] && ~RD[7])) begin
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Addr[15:8] <= Addr[15:8]+1;
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end
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if (AddrLSpecSEL) begin
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Addr[7:0] <= RD[7:0];
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end else if (RAMSEL) begin
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Addr[7:0] <= Addr[7:0]+1;
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end
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end
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end
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/* SPI flash */
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output reg nFCS = 1;
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output reg FCK = 0;
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output reg MOSI = MOSIOE ? MOSIout : 1'bZ;
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reg MOSIOE = 0;
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reg MOSIout;
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input MISO;
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/* SPI flash control */
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always @(posedge C25M) begin
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if (InitActv) begin
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// Pulse clock from init states $0FFFC0 to $907FFF
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if (LS[22:0]>=23'h0FFFC0 && LS[22:0]<=23'h907FFF) FCK <= LS[0];
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end else FCK <= 0;
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// Flash /CS enabled from init states $0FFFB0 to s$90800F
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if (LS[22:0]>=23'h0FFFB0 && LS[22:0]<=23'h90800F) nFCS <= 0;
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end else nFCS <= 1;
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// Send command $3B (read) (MSB first)
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if (LS[22:0]==23'h0FFFB0 || LS[22:0]==23'h0FFFB1) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFB2 || LS[22:0]==23'h0FFFB3) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFB4 || LS[22:0]==23'h0FFFB5) MOSIout <= 1;
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else if (LS[22:0]==23'h0FFFB6 || LS[22:0]==23'h0FFFB7) MOSIout <= 1;
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else if (LS[22:0]==23'h0FFFB8 || LS[22:0]==23'h0FFFB9) MOSIout <= 1;
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else if (LS[22:0]==23'h0FFFBA || LS[22:0]==23'h0FFFBB) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFBC || LS[22:0]==23'h0FFFBD) MOSIout <= 1;
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else if (LS[22:0]==23'h0FFFBE || LS[22:0]==23'h0FFFBF) MOSIout <= 1;
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// Send 24-bit address (MSB first)
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else if (LS[22:0]==23'h0FFFC0 || LS[22:0]==23'h0FFFC1) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFC2 || LS[22:0]==23'h0FFFC3) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFC4 || LS[22:0]==23'h0FFFC5) MOSIout <= SetFW[1];
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else if (LS[22:0]==23'h0FFFC6 || LS[22:0]==23'h0FFFC7) MOSIout <= SetFW[0];
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else if (LS[22:0]==23'h0FFFC8 || LS[22:0]==23'h0FFFC9) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFCA || LS[22:0]==23'h0FFFCB) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFCC || LS[22:0]==23'h0FFFCD) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFCE || LS[22:0]==23'h0FFFCF) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFD0 || LS[22:0]==23'h0FFFD1) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFD2 || LS[22:0]==23'h0FFFD3) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFD4 || LS[22:0]==23'h0FFFD5) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFD6 || LS[22:0]==23'h0FFFD7) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFD8 || LS[22:0]==23'h0FFFD9) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFDA || LS[22:0]==23'h0FFFDB) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFDC || LS[22:0]==23'h0FFFDD) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFDE || LS[22:0]==23'h0FFFDF) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFE0 || LS[22:0]==23'h0FFFE1) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFE2 || LS[22:0]==23'h0FFFE3) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFE4 || LS[22:0]==23'h0FFFE5) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFE6 || LS[22:0]==23'h0FFFE7) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFE8 || LS[22:0]==23'h0FFFE9) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFEA || LS[22:0]==23'h0FFFEB) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFEC || LS[22:0]==23'h0FFFED) MOSIout <= 0;
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else if (LS[22:0]==23'h0FFFEE || LS[22:0]==23'h0FFFEF) MOSIout <= 0;
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else MOSIout <= 0;
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MOSIOE <= LS[22:0]<23'h0FFFF0;
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end else if (AppleActive) begin
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//TODO: control these with Apple II
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nFCS <= 1;
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FCK <= 0;
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MOSIout <= 0;
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MOSIOE <= 0;
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//TODO? sample nMenu when MOSI not outputting?
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end
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end
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/* SDRAM address/command */
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output reg [1:0] SBA;
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output reg [12:0] SA;
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output reg RCKE = 1;
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output reg nRCS = 1;
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output reg nRAS = 1;
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output reg nCAS = 1;
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output reg nSWE = 1;
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output reg DQMH = 1;
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output reg DQML = 1;
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/* SDRAM data bus */
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inout [7:0] SD = SDOE ? WRD[7:0] : 8'bZ;
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reg [7:0] WRD;
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reg SDOE = 0;
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always @(posedge C25M) begin
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// Shift { MISO, MOSI } in when InitActv. When ready, synchronize RD
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if (InitActv) if (LS[1]) WRD[7:0] <= { MISO, MOSI, WRD[5:0] };
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end else WRD[7:0] <= RD[7:0];
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// Output data on SDRAM data bus only during init and when writing
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SDOE <= InitActv || (RAMSEL && nWEcur && S==6);
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end
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/* State counters */
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reg [2:0] S = 0;
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always @(posedge C25M) begin
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if ( ~InitActv && SDRAMActv && S==0 && PHI0r1 && ~PHI0r2 && nRESr && nBODf) S <= 1;
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else if (S==0) S <= 0;
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else S <= S+1;
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end
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/* Refresh state */
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reg RefReady = 0;
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reg RefDone = 0;
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always @(posedge C25M) begin
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// Ready to refresh when init inactive, SDRAM active, S0 and refresh not already done
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RefReady <= ~InitActv && SDRAMActv && S==0 && ~RefDone;
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if (LS[6:0]==7'h00) RefDone <= 0; // Reset RefDone every 128 C25M cycles (5.12 us)
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else if (~InitActv && SDRAMActv && S==0 && ~RefDone && RefReady && ~(PHI0r1 && ~PHI0r2)) RefDone <= 1;
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end
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/* SDRAM control */
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always @(posedge C25M) begin
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if (S==0 && InitActv) begin
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if (LS[22:0]==23'h000000) begin
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end
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end else if (S==0 && ~SDRAMActv) begin
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// NOP CKE
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RCKE <= 1'b1;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end else if (S==0 && PHI0r1 && ~PHI0r2) begin
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// NOP CKE
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RCKE <= 1'b1;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end else if (S==0 && ~RefDone) begin
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// NOP CKE
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RCKE <= 1'b1;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end else if (S==0 && RefReady) begin
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// AREF
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RCKE <= 1'b1;
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nRCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end else if (S==0) begin
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// NOP CKD
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end else if (S==4'h1) begin
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if (ROMSpecRD || RAMSpecRD) begin
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// ACT
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RCKE <= 1'b1;
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nRCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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if (RAMSpecRD) begin
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RBA[1] <= Addr[24];
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RBA[0] <= Addr[23] & ~SetLim8M;
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RA[12:0] <= Addr[22:10];
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end else begin
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RBA[1] <= 1'b1;
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RBA[0] <= 1'b0;
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RA[12:10] <= 3'b000;
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if (RAcur[11]) begin // IOSTRB
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RA[9] <= 1'b0;
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RA[8:1] <= Bank[7:0];
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RA[0] <= RAcur[10];
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end else begin // IOSEL
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RA[9] <= 1'b1;
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RA[8:1] <= 8'h00;
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RA[0] <= RAcur[10];
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end
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end
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end else begin
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// NOP ckdis
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQMH <= 1'b1;
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DQML <= 1'b1;
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end
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end else if (S==4'h2) begin
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if (ROMSpecRD || RAMSpecRD) begin
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// RD auto-PC
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RCKE <= 1'b1;
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nRCS <= 1'b0;
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nRAS <= 1'b1;
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nCAS <= 1'b0;
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nSWE <= 1'b1;
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A[12:11] <= 1'b0; // don't care
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A[10] <= 1'b1; // auto-precharge
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A[9] <= 1'b0; // don't care
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if (RAMSpecRD) begin
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RBA[1] <= Addr[24];
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RBA[0] <= Addr[23];
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RA[8:0] <= Addr[9:1];
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DQMH <= ~Addr[0];
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DQML <= Addr[0];
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end else /* ROMSpecRD */ begin
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RBA[1] <= 1'b1;
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RBA[0] <= 1'b0;
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RA[8:0] <= RAcur[9:1];
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DQMH <= ~RAcur[0];
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DQML <= RAcur[0];
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end
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end else begin
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// NOP ckdis
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RCKE <= 1'b0;
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nRCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
DQML <= 1'b1;
|
|
end
|
|
end else if (S==4'h3) begin
|
|
if (ROMSpecRD || RAMSpecRD) begin
|
|
// NOP cken
|
|
RCKE <= 1'b1;
|
|
nRCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nSWE <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
DQML <= 1'b1;
|
|
end else begin
|
|
// NOP ckdis
|
|
RCKE <= 1'b0;
|
|
nRCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nSWE <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
DQML <= 1'b1;
|
|
end
|
|
end else if (S==4'h4) begin
|
|
if (RAMSpecWR) begin
|
|
// NOP cken
|
|
RCKE <= 1'b1;
|
|
nRCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nSWE <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
DQML <= 1'b1;
|
|
end else begin
|
|
// NOP ckdis
|
|
RCKE <= 1'b0;
|
|
nRCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nSWE <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
DQML <= 1'b1;
|
|
end
|
|
end else if (S==4'h5) begin
|
|
if (RAMSpecWR && DEVSELr) begin
|
|
// ACT
|
|
RCKE <= 1'b1;
|
|
nRCS <= 1'b0;
|
|
nRAS <= 1'b0;
|
|
nCAS <= 1'b1;
|
|
nSWE <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
DQML <= 1'b1;
|
|
|
|
BA[1] <= Addr[24];
|
|
BA[0] <= Addr[23];
|
|
A[12:0] <= Addr[22:10];
|
|
end else begin
|
|
// NOP ckdis
|
|
RCKE <= 1'b0;
|
|
nRCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nSWE <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
DQML <= 1'b1;
|
|
end
|
|
end else if (s==4'h6) begin
|
|
if (RAMWR) begin
|
|
// WR auto-PC
|
|
RCKE <= 1'b1;
|
|
nRCS <= 1'b0;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b0;
|
|
nSWE <= 1'b0;
|
|
|
|
BA[1] <= Addr[24];
|
|
BA[0] <= Addr[23];
|
|
A[12:11] <= 1'b0; // don't care
|
|
A[10] <= 1'b1; // auto-precharge
|
|
A[9:0] <= Addr[9:0];
|
|
DQMH <= ~Addr[10];
|
|
DQML <= Addr[10];
|
|
end else begin
|
|
// NOP ckdis
|
|
RCKE <= 1'b0;
|
|
nRCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nSWE <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
DQML <= 1'b1;
|
|
end
|
|
end else if (S==4'h7) begin
|
|
if (RAMSpecWR) begin
|
|
// NOP cken
|
|
RCKE <= 1'b1;
|
|
nRCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nSWE <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
DQML <= 1'b1;
|
|
end else begin
|
|
// NOP ckdis
|
|
RCKE <= 1'b0;
|
|
nRCS <= 1'b1;
|
|
nRAS <= 1'b1;
|
|
nCAS <= 1'b1;
|
|
nSWE <= 1'b1;
|
|
DQMH <= 1'b1;
|
|
DQML <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
endmodule
|