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GR8RAM/cpld/output_files/GR8RAM.map.rpt
Zane Kaminski 79dd794f45 New PLD revision 
For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
2019-10-18 15:07:38 -04:00

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Analysis & Synthesis report for GR8RAM
Fri Oct 18 15:01:54 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0
8. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0
9. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4
10. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3
11. Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5
12. Analysis & Synthesis Messages
13. Analysis & Synthesis Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Fri Oct 18 15:01:54 2019 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; GR8RAM ;
; Top-level Entity Name ; GR8RAM ;
; Family ; MAX7000S ;
; Total macrocells ; 105 ;
; Total pins ; 61 ;
+-----------------------------+-------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+-----------------+---------------+
; Device ; EPM7128SLC84-15 ; ;
; Top-level entity name ; GR8RAM ; GR8RAM ;
; Family name ; MAX7000S ; Cyclone IV GX ;
; State Machine Processing ; User-Encoded ; Auto ;
; Extract Verilog State Machines ; Off ; On ;
; Extract VHDL State Machines ; Off ; On ;
; Parallel Synthesis ; Off ; On ;
; Ignore LCELL Buffers ; Off ; Auto ;
; Auto Logic Cell Insertion ; Off ; On ;
; Auto Parallel Expanders ; Off ; On ;
; Pre-Mapping Resynthesis Optimization ; On ; Off ;
; Analysis & Synthesis Message Level ; High ; Medium ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; Safe State Machine ; Off ; Off ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; Off ; Off ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique ; Speed ; Speed ;
; Allow XOR Gate Usage ; On ; On ;
; Parallel Expander Chain Length ; 4 ; 4 ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Fan-in Per Macrocell ; 100 ; 100 ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Synthesis Seed ; 1 ; 1 ;
+----------------------------------------------------------------------------+-----------------+---------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
; GR8RAM.v ; yes ; User Verilog HDL File ; Z:/Repos/GR8RAM/cpld/GR8RAM.v ; ;
; lpm_counter.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
; lpm_constant.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; lpm_add_sub.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
; cmpconst.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/cmpconst.inc ; ;
; lpm_compare.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_compare.inc ; ;
; lpm_counter.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_counter.inc ; ;
; dffeea.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/dffeea.inc ; ;
; alt_counter_stratix.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_counter_stratix.inc ; ;
; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc ; ;
; lpm_add_sub.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_add_sub.tdf ; ;
; addcore.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.inc ; ;
; look_add.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/look_add.inc ; ;
; bypassff.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/bypassff.inc ; ;
; altshift.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.inc ; ;
; alt_stratix_add_sub.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ; ;
; addcore.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/addcore.tdf ; ;
; a_csnbuffer.inc ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_csnbuffer.inc ; ;
; a_csnbuffer.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_csnbuffer.tdf ; ;
; look_add.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/look_add.tdf ; ;
; altshift.tdf ; yes ; Megafunction ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altshift.tdf ; ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------------------------+---------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 105 ;
; Total registers ; 54 ;
; I/O pins ; 61 ;
; Shareable expanders ; 1 ;
; Maximum fan-out node ; C7M ;
; Maximum fan-out ; 54 ;
; Total fan-out ; 866 ;
; Average fan-out ; 5.19 ;
+----------------------+----------------------+
+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+------------+------+-------------------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+-------------------------------+--------------+
; |GR8RAM ; 105 ; 61 ; |GR8RAM ; work ;
; |lpm_counter:Ref_rtl_0| ; 4 ; 0 ; |GR8RAM|lpm_counter:Ref_rtl_0 ; work ;
+----------------------------+------------+------+-------------------------------+--------------+
+------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:Ref_rtl_0 ;
+------------------------+-------------------+---------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+---------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add0 ;
+------------------------+-------------+----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH ; 8 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_rnh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add4 ;
+------------------------+-------------+----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH ; 8 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_rnh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add3 ;
+------------------------+-------------+----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH ; 8 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_rnh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_add_sub:Add5 ;
+------------------------+-------------+----------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+----------------------------+
; LPM_WIDTH ; 8 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_rnh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Info: Processing started: Fri Oct 18 15:01:46 2019
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off GR8RAM -c GR8RAM
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file gr8ram.v
Info (12023): Found entity 1: GR8RAM
Info (12127): Elaborating entity "GR8RAM" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(30): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(123): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(128): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(160): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(165): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at GR8RAM.v(171): truncated value with size 32 to match size of target (8)
Info (19000): Inferred 1 megafunctions from design logic
Info (19001): Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "Ref_rtl_0"
Info (278001): Inferred 4 megafunctions from design logic
Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add0"
Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add4"
Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add3"
Info (278002): Inferred adder/subtractor megafunction ("lpm_add_sub") from the following logic: "Add5"
Info (12130): Elaborated megafunction instantiation "lpm_counter:Ref_rtl_0"
Info (12133): Instantiated megafunction "lpm_counter:Ref_rtl_0" with the following parameter:
Info (12134): Parameter "LPM_WIDTH" = "4"
Info (12134): Parameter "LPM_DIRECTION" = "UP"
Info (12134): Parameter "LPM_TYPE" = "LPM_COUNTER"
Info (12130): Elaborated megafunction instantiation "lpm_add_sub:Add0"
Info (12133): Instantiated megafunction "lpm_add_sub:Add0" with the following parameter:
Info (12134): Parameter "LPM_WIDTH" = "8"
Info (12134): Parameter "LPM_DIRECTION" = "ADD"
Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
Info (12134): Parameter "ONE_INPUT_IS_CONSTANT" = "YES"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[0]", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[0]|a_csnbuffer:oflow_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|addcore:adder[0]|a_csnbuffer:result_node", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|look_add:look_ahead_unit", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:result_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (12131): Elaborated megafunction instantiation "lpm_add_sub:Add0|altshift:carry_ext_latency_ffs", which is child of megafunction instantiation "lpm_add_sub:Add0"
Info (13014): Ignored 32 buffer(s)
Info (13019): Ignored 32 SOFT buffer(s)
Info (280013): Promoted pin-driven signal(s) to global signal
Info (280014): Promoted clock signal driven by pin "C7M" to global clock signal
Info (280015): Promoted clear signal driven by pin "nRES" to global clear signal
Warning (21074): Design contains 9 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "C7M_2"
Warning (15610): No output dependent on input pin "Q3"
Warning (15610): No output dependent on input pin "PHI0in"
Warning (15610): No output dependent on input pin "nMode"
Warning (15610): No output dependent on input pin "A[11]"
Warning (15610): No output dependent on input pin "A[12]"
Warning (15610): No output dependent on input pin "A[13]"
Warning (15610): No output dependent on input pin "A[14]"
Warning (15610): No output dependent on input pin "A[15]"
Info (21057): Implemented 167 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 27 input pins
Info (21059): Implemented 18 output pins
Info (21060): Implemented 16 bidirectional pins
Info (21063): Implemented 105 macrocells
Info (21073): Implemented 1 shareable expanders
Info (144001): Generated suppressed messages file Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 17 warnings
Info: Peak virtual memory: 308 megabytes
Info: Processing ended: Fri Oct 18 15:01:54 2019
Info: Elapsed time: 00:00:08
Info: Total CPU time (on all processors): 00:00:08
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in Z:/Repos/GR8RAM/cpld/output_files/GR8RAM.map.smsg.
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