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For write operations, register data is latched and CAS signal becomes in the middle of S6, 70ns before the end of PHI0. This gives more write data setup time, which may be needed on the Apple II with the 1 MHz 6502.
4 lines
288 B
Plaintext
Executable File
4 lines
288 B
Plaintext
Executable File
Warning (10273): Verilog HDL warning at GR8RAM.v(52): extended using "x" or "z"
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Warning (10273): Verilog HDL warning at GR8RAM.v(60): extended using "x" or "z"
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Warning (10268): Verilog HDL information at GR8RAM.v(191): always construct contains both blocking and non-blocking assignments
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