Apple-2-HW/GR8RAM
1
0
Fork 1
mirror of https://github.com/garrettsworkshop/GR8RAM.git synced 2024-12-13 00:29:30 +00:00
Code Issues Projects Releases Wiki Activity
b467eaac6b
GR8RAM/cpld/output_files/GR8RAM.sta.rpt
Zane Kaminski b1757d3d0f Compiled CPLD again
2023-02-28 11:23:37 -05:00

792 lines
64 KiB
Plaintext
Raw Blame History

Timing Analyzer report for GR8RAM
Tue Feb 28 11:21:29 2023
Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Parallel Compilation
4. SDC File List
5. Clocks
6. Fmax Summary
7. Setup Summary
8. Hold Summary
9. Recovery Summary
10. Removal Summary
11. Minimum Pulse Width Summary
12. Setup: 'C25M'
13. Hold: 'C25M'
14. Recovery: 'C25M'
15. Removal: 'C25M'
16. Setup Transfers
17. Hold Transfers
18. Recovery Transfers
19. Removal Transfers
20. Report TCCS
21. Report RSKM
22. Unconstrained Paths Summary
23. Clock Status Summary
24. Unconstrained Input Ports
25. Unconstrained Output Ports
26. Unconstrained Input Ports
27. Unconstrained Output Ports
28. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2022 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+--------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+-----------------------+--------------------------------------------------------+
; Quartus Prime Version ; Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition ;
; Timing Analyzer ; Legacy Timing Analyzer ;
; Revision Name ; GR8RAM ;
; Device Family ; MAX II ;
; Device Name ; EPM240T100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
+-----------------------+--------------------------------------------------------+
+------------------------------------------+
; Parallel Compilation ;
+----------------------------+-------------+
; Processors ; Number ;
+----------------------------+-------------+
; Number detected on machine ; 4 ;
; Maximum allowed ; 4 ;
; ; ;
; Average used ; 1.00 ;
; Maximum used ; 1 ;
; ; ;
; Usage by Processor ; % Time Used ;
; Processor 1 ; 100.0% ;
+----------------------------+-------------+
+---------------------------------------------------+
; SDC File List ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+---------------+--------+--------------------------+
; GR8RAM.sdc ; OK ; Tue Feb 28 11:21:29 2023 ;
+---------------+--------+--------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks ;
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
; C25M ; Base ; 40.000 ; 25.0 MHz ; 0.000 ; 20.000 ; ; ; ; ; ; ; ; ; ; ; { C25M } ;
; PHI0 ; Base ; 978.000 ; 1.02 MHz ; 0.000 ; 489.000 ; ; ; ; ; ; ; ; ; ; ; { PHI0 } ;
+------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
+-------------------------------------------------+
; Fmax Summary ;
+-----------+-----------------+------------+------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+-----------+-----------------+------------+------+
; 51.43 MHz ; 51.43 MHz ; C25M ; ;
+-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
+--------------------------------+
; Setup Summary ;
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; C25M ; 10.278 ; 0.000 ;
+-------+--------+---------------+
+-------------------------------+
; Hold Summary ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; C25M ; 1.376 ; 0.000 ;
+-------+-------+---------------+
+--------------------------------+
; Recovery Summary ;
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
; C25M ; 33.311 ; 0.000 ;
+-------+--------+---------------+
+-------------------------------+
; Removal Summary ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; C25M ; 6.135 ; 0.000 ;
+-------+-------+---------------+
+---------------------------------+
; Minimum Pulse Width Summary ;
+-------+---------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+---------+---------------+
; C25M ; 19.734 ; 0.000 ;
; PHI0 ; 488.734 ; 0.000 ;
+-------+---------+---------------+
+-------------------------------------------------------------------------------------------------------+
; Setup: 'C25M' ;
+--------+-----------+------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+------------+--------------+-------------+--------------+------------+------------+
; 10.278 ; REGEN ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.389 ;
; 10.285 ; REGEN ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.382 ;
; 10.289 ; REGEN ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.378 ;
; 10.642 ; REGEN ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 9.025 ;
; 11.085 ; REGEN ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.582 ;
; 11.357 ; REGEN ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.310 ;
; 11.401 ; REGEN ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.266 ;
; 11.402 ; REGEN ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 8.265 ;
; 12.395 ; PS[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.395 ; PS[0] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.395 ; PS[0] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.395 ; PS[0] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.272 ;
; 12.440 ; PS[0] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.440 ; PS[0] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.440 ; PS[0] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.440 ; PS[0] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.227 ;
; 12.450 ; PS[3] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.450 ; PS[3] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.450 ; PS[3] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.450 ; PS[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.217 ;
; 12.495 ; PS[3] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.495 ; PS[3] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.495 ; PS[3] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.495 ; PS[3] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 7.172 ;
; 12.804 ; PS[2] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.804 ; PS[2] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.804 ; PS[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.804 ; PS[2] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.863 ;
; 12.849 ; PS[2] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 12.849 ; PS[2] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 12.849 ; PS[2] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 12.849 ; PS[2] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.818 ;
; 13.331 ; Addr[12] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 6.336 ;
; 13.753 ; PS[1] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.753 ; PS[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.753 ; PS[1] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.753 ; PS[1] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.914 ;
; 13.798 ; PS[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.798 ; PS[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.798 ; PS[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.798 ; PS[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.869 ;
; 13.971 ; Addr[11] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.696 ;
; 14.103 ; Addr[7] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.564 ;
; 14.314 ; Addr[15] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 5.353 ;
; 14.675 ; Addr[14] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.992 ;
; 14.748 ; Addr[8] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.919 ;
; 14.753 ; Addr[9] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.914 ;
; 14.779 ; SetFWr[1] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.888 ;
; 14.780 ; SetFWr[1] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.887 ;
; 14.785 ; SetFWr[1] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.882 ;
; 14.975 ; Addr[4] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.692 ;
; 15.251 ; SetFWr[1] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.416 ;
; 15.322 ; Addr[10] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.345 ;
; 15.387 ; Addr[21] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.280 ;
; 15.489 ; Addr[6] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.178 ;
; 15.612 ; Addr[17] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.055 ;
; 15.651 ; Addr[13] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.016 ;
; 15.653 ; Addr[19] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 4.014 ;
; 15.700 ; Addr[5] ; RDD[5] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.967 ;
; 15.911 ; Addr[16] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.756 ;
; 16.065 ; Addr[22] ; RDD[6] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.602 ;
; 16.103 ; Addr[18] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.564 ;
; 16.349 ; Addr[23] ; RDD[7] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.318 ;
; 16.647 ; Addr[0] ; RDD[0] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.020 ;
; 16.656 ; Addr[3] ; RDD[3] ; C25M ; C25M ; 20.000 ; 0.000 ; 3.011 ;
; 16.711 ; Addr[1] ; RDD[1] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.956 ;
; 16.777 ; Addr[20] ; RDD[4] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.890 ;
; 17.105 ; Addr[2] ; RDD[2] ; C25M ; C25M ; 20.000 ; 0.000 ; 2.562 ;
; 22.720 ; Addr[23] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 16.947 ;
; 23.632 ; Addr[23] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 16.035 ;
; 23.717 ; REGEN ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.950 ;
; 23.986 ; SetFWr[0] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.681 ;
; 24.629 ; REGEN ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 15.038 ;
; 24.898 ; SetFWr[0] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.769 ;
; 25.067 ; SetFWr[1] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.600 ;
; 25.201 ; PS[1] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.466 ;
; 25.277 ; Addr[23] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.390 ;
; 25.323 ; PS[1] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 14.344 ;
; 25.783 ; Addr[23] ; SA[4]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.884 ;
; 25.876 ; Addr[23] ; RCKE~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.791 ;
; 25.979 ; SetFWr[1] ; SA[2]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.688 ;
; 26.015 ; Addr[23] ; SA[8]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.652 ;
; 26.018 ; Addr[23] ; SA[3]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.649 ;
; 26.117 ; Addr[23] ; SA[5]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.550 ;
; 26.222 ; PS[1] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.222 ; PS[1] ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 13.445 ;
; 26.274 ; REGEN ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.393 ;
; 26.312 ; Addr[23] ; SA[6]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.355 ;
; 26.361 ; LS[7] ; IS.000 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.306 ;
; 26.498 ; PS[0] ; SA[0]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.169 ;
; 26.543 ; SetFWr[0] ; SA[1]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.124 ;
; 26.596 ; Addr[23] ; SA[7]~reg0 ; C25M ; C25M ; 40.000 ; 0.000 ; 13.071 ;
; 26.722 ; PS[0] ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.945 ;
; 26.722 ; PS[0] ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 12.945 ;
+--------+-----------+------------+--------------+-------------+--------------+------------+------------+
+-----------------------------------------------------------------------------------------------------------+
; Hold: 'C25M' ;
+-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
; 1.376 ; PHI0r1 ; PHI0r2 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.597 ;
; 1.412 ; nRESf[1] ; nRESf[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ;
; 1.412 ; WRD[7] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.633 ;
; 1.419 ; WRD[4] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.640 ;
; 1.420 ; WRD[0] ; WRD[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.641 ;
; 1.426 ; nRESf[2] ; nRESf[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.647 ;
; 1.429 ; nRESf[0] ; nRESf[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.650 ;
; 1.646 ; WRD[2] ; WRD[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.867 ;
; 1.649 ; nRESout~reg0 ; nRESout~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.870 ;
; 1.652 ; WRD[5] ; WRD[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.873 ;
; 1.653 ; WRD[3] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.874 ;
; 1.661 ; Bank ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 1.882 ;
; 1.664 ; Addr[19] ; SA[9]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 1.885 ;
; 1.670 ; IS.000 ; FCKOE ; C25M ; C25M ; 0.000 ; 0.000 ; 1.891 ;
; 1.675 ; LS[0] ; LS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.896 ;
; 1.719 ; PS[0] ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 1.940 ;
; 1.720 ; PS[2] ; MOSIout ; C25M ; C25M ; 0.000 ; 0.000 ; 1.941 ;
; 1.793 ; WRD[2] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.014 ;
; 1.794 ; WRD[3] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.015 ;
; 1.806 ; WRD[6] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.027 ;
; 1.809 ; IS.101 ; MOSIOE ; C25M ; C25M ; 0.000 ; 0.000 ; 2.030 ;
; 1.846 ; WRD[1] ; WRD[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.067 ;
; 1.942 ; Addr[21] ; SA[11]~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.163 ;
; 1.948 ; nRESf[2] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.169 ;
; 2.048 ; nRESf[1] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.269 ;
; 2.063 ; LS[13] ; LS[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.284 ;
; 2.082 ; Addr[15] ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 2.303 ;
; 2.107 ; LS[7] ; LS[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.328 ;
; 2.115 ; Addr[0] ; DQML~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.336 ;
; 2.116 ; Addr[0] ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ;
; 2.116 ; Addr[16] ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.337 ;
; 2.117 ; Addr[23] ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[10] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[7] ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[17] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[18] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.117 ; Addr[9] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.338 ;
; 2.125 ; Addr[8] ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.346 ;
; 2.126 ; Addr[1] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
; 2.126 ; Addr[15] ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.347 ;
; 2.127 ; Addr[2] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.348 ;
; 2.128 ; nRESf[3] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.349 ;
; 2.137 ; IS.111 ; IS.111 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.358 ;
; 2.144 ; LS[4] ; LS[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.365 ;
; 2.145 ; LS[6] ; LS[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.366 ;
; 2.149 ; REGEN ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.370 ;
; 2.150 ; LS[0] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.371 ;
; 2.151 ; LS[8] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.372 ;
; 2.153 ; LS[9] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.374 ;
; 2.185 ; PS[2] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.406 ;
; 2.188 ; PS[2] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.409 ;
; 2.232 ; Addr[11] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
; 2.232 ; Addr[3] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
; 2.232 ; Addr[19] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.453 ;
; 2.239 ; Addr[22] ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.460 ;
; 2.240 ; Addr[20] ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.461 ;
; 2.241 ; PS[0] ; RCKE~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.462 ;
; 2.242 ; LS[10] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.463 ;
; 2.249 ; Addr[12] ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
; 2.249 ; Addr[21] ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.470 ;
; 2.250 ; Addr[4] ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ;
; 2.250 ; Addr[5] ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.471 ;
; 2.251 ; LS[5] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.472 ;
; 2.252 ; PS[1] ; PS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.473 ;
; 2.259 ; LS[11] ; LS[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.480 ;
; 2.261 ; Addr[13] ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
; 2.261 ; Addr[14] ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.482 ;
; 2.263 ; WRD[5] ; WRD[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.484 ;
; 2.264 ; nRESf[0] ; nRESr ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ;
; 2.264 ; WRD[4] ; WRD[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.485 ;
; 2.267 ; WRD[0] ; WRD[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.488 ;
; 2.270 ; LS[2] ; LS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.491 ;
; 2.271 ; LS[12] ; LS[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.492 ;
; 2.272 ; SetFWLoaded ; SetFWr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ;
; 2.272 ; LS[3] ; LS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ;
; 2.272 ; SetFWLoaded ; SetFWr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.493 ;
; 2.274 ; LS[1] ; LS[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.495 ;
; 2.276 ; IOROMEN ; IOROMEN ; C25M ; C25M ; 0.000 ; 0.000 ; 2.497 ;
; 2.287 ; PS[3] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.508 ;
; 2.573 ; Addr[6] ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.794 ;
; 2.686 ; WRD[1] ; WRD[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 2.907 ;
; 2.690 ; Addr[0] ; DQMH~reg0 ; C25M ; C25M ; 0.000 ; 0.000 ; 2.911 ;
; 2.902 ; PS[0] ; PS[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.123 ;
; 2.906 ; PS[0] ; PS[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.127 ;
; 2.939 ; LS[7] ; LS[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.160 ;
; 2.948 ; Addr[0] ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ;
; 2.948 ; Addr[16] ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.169 ;
; 2.949 ; Addr[9] ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[10] ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[17] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.949 ; Addr[18] ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.170 ;
; 2.957 ; Addr[8] ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.178 ;
; 2.958 ; Addr[1] ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.179 ;
; 2.959 ; Addr[2] ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.180 ;
; 2.976 ; LS[4] ; LS[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.197 ;
; 2.983 ; LS[8] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.204 ;
; 2.985 ; LS[9] ; LS[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.206 ;
; 3.001 ; PHI0r1 ; PS[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.222 ;
; 3.050 ; LS[7] ; LS[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.271 ;
; 3.059 ; Addr[16] ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 3.280 ;
+-------+--------------+--------------+--------------+-------------+--------------+------------+------------+
+-----------------------------------------------------------------------------------------------------+
; Recovery: 'C25M' ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
; 33.311 ; nRESr ; Addr[0] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; REGEN ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[23] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[10] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[1] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[11] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[2] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[12] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Bank ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[3] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[13] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[4] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[14] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[5] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[15] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[6] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[16] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[7] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[17] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[8] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[18] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[9] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[19] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[20] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[21] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; Addr[22] ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; AddrIncH ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; AddrIncM ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
; 33.311 ; nRESr ; AddrIncL ; C25M ; C25M ; 40.000 ; 0.000 ; 6.356 ;
+--------+-----------+----------+--------------+-------------+--------------+------------+------------+
+----------------------------------------------------------------------------------------------------+
; Removal: 'C25M' ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
; 6.135 ; nRESr ; Addr[0] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; REGEN ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[23] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[10] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[1] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[11] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[2] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[12] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Bank ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[3] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[13] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[4] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[14] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[5] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[15] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[6] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[16] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[7] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[17] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[8] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[18] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[9] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[19] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[20] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[21] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; Addr[22] ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; AddrIncH ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; AddrIncM ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
; 6.135 ; nRESr ; AddrIncL ; C25M ; C25M ; 0.000 ; 0.000 ; 6.356 ;
+-------+-----------+----------+--------------+-------------+--------------+------------+------------+
+-------------------------------------------------------------------------+
; Setup Transfers ;
+------------+----------+------------+------------+------------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+------------+------------+------------+----------+
; C25M ; C25M ; 1520 ; 0 ; 88 ; 0 ;
; PHI0 ; C25M ; false path ; false path ; false path ; 0 ;
+------------+----------+------------+------------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------------+
; Hold Transfers ;
+------------+----------+------------+------------+------------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+------------+------------+------------+----------+
; C25M ; C25M ; 1520 ; 0 ; 88 ; 0 ;
; PHI0 ; C25M ; false path ; false path ; false path ; 0 ;
+------------+----------+------------+------------+------------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------+
; Recovery Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C25M ; C25M ; 29 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
+-------------------------------------------------------------------+
; Removal Transfers ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; C25M ; C25M ; 29 ; 0 ; 0 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design
---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
+------------------------------------------------+
; Unconstrained Paths Summary ;
+---------------------------------+-------+------+
; Property ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks ; 0 ; 0 ;
; Unconstrained Clocks ; 0 ; 0 ;
; Unconstrained Input Ports ; 44 ; 44 ;
; Unconstrained Input Port Paths ; 246 ; 246 ;
; Unconstrained Output Ports ; 45 ; 45 ;
; Unconstrained Output Port Paths ; 217 ; 217 ;
+---------------------------------+-------+------+
+-------------------------------------+
; Clock Status Summary ;
+--------+-------+------+-------------+
; Target ; Clock ; Type ; Status ;
+--------+-------+------+-------------+
; C25M ; C25M ; Base ; Constrained ;
; PHI0 ; PHI0 ; Base ; Constrained ;
+--------+-------+------+-------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; DMAin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; INTin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MISO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MOSI ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PHI0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRES ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; DMAout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; FCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; INTout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MOSI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RDdir ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nFCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRESout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nSWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment ;
+------------+--------------------------------------------------------------------------------------+
; DMAin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; INTin ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MISO ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MOSI ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PHI0 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[10] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[11] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[12] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[13] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[14] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RA[15] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SetFW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SetFW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nDEVSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nIOSEL ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nIOSTRB ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRES ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment ;
+-------------+---------------------------------------------------------------------------------------+
; DMAout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; FCK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; INTout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; MOSI ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RCKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; RDdir ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SA[12] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SBA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nFCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nRESout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; nSWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
Info: Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition
Info: Processing started: Tue Feb 28 11:21:27 2023
Info: Command: quartus_sta GR8RAM -c GR8RAM
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332104): Reading SDC File: 'GR8RAM.sdc'
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Info (332146): Worst-case setup slack is 10.278
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 10.278 0.000 C25M
Info (332146): Worst-case hold slack is 1.376
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 1.376 0.000 C25M
Info (332146): Worst-case recovery slack is 33.311
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 33.311 0.000 C25M
Info (332146): Worst-case removal slack is 6.135
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 6.135 0.000 C25M
Info (332146): Worst-case minimum pulse width slack is 19.734
Info (332119): Slack End Point TNS Clock
Info (332119): ========= =================== =====================
Info (332119): 19.734 0.000 C25M
Info (332119): 488.734 0.000 PHI0
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 13081 megabytes
Info: Processing ended: Tue Feb 28 11:21:29 2023
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01
Reference in New Issue View Git Blame Copy Permalink