145 lines
6.5 KiB
Plaintext
Executable File
145 lines
6.5 KiB
Plaintext
Executable File
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 32-bit
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Date created = 13:41:40 March 15, 2021
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# GR8RAM_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "MAX II"
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set_global_assignment -name DEVICE EPM240T100C5
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set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:41:40 MARCH 15, 2021"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
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set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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set_global_assignment -name SAFE_STATE_MACHINE OFF
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set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
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set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS
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set_global_assignment -name AUTO_RESOURCE_SHARING ON
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set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
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set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
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set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
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set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
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set_global_assignment -name MUX_RESTRUCTURE ON
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set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
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set_global_assignment -name SYNTHESIS_SEED 123
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set_global_assignment -name SEED 235
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set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA"
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set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
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set_global_assignment -name VERILOG_FILE GR8RAM.v
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set_location_assignment PIN_1 -to RA[4]
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set_location_assignment PIN_2 -to RA[5]
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set_location_assignment PIN_3 -to RA[6]
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set_location_assignment PIN_4 -to RA[3]
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set_location_assignment PIN_5 -to nFCS
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set_location_assignment PIN_6 -to RA[7]
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set_location_assignment PIN_7 -to RA[8]
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set_location_assignment PIN_8 -to RA[9]
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set_location_assignment PIN_12 -to FCK
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set_location_assignment PIN_14 -to RA[10]
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set_location_assignment PIN_15 -to MOSI
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set_location_assignment PIN_16 -to MISO
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set_location_assignment PIN_17 -to Ddir
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set_location_assignment PIN_30 -to nRESout
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set_location_assignment PIN_34 -to RA[11]
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set_location_assignment PIN_35 -to RA[12]
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set_location_assignment PIN_36 -to RA[13]
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set_location_assignment PIN_37 -to RA[14]
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set_location_assignment PIN_38 -to RA[15]
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set_location_assignment PIN_39 -to nIOSEL
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set_location_assignment PIN_42 -to nIOSTRB
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set_location_assignment PIN_40 -to nDEVSEL
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set_location_assignment PIN_41 -to PHI0
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set_location_assignment PIN_43 -to nWE
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set_location_assignment PIN_44 -to nRES
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set_location_assignment PIN_47 -to SD[1]
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set_location_assignment PIN_50 -to SD[0]
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set_location_assignment PIN_51 -to SD[4]
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set_location_assignment PIN_100 -to RA[0]
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set_location_assignment PIN_99 -to RD[7]
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set_location_assignment PIN_52 -to SD[5]
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set_location_assignment PIN_54 -to SD[7]
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set_location_assignment PIN_55 -to SD[3]
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set_location_assignment PIN_56 -to SD[2]
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set_location_assignment PIN_53 -to SD[6]
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set_location_assignment PIN_57 -to DQMH
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set_location_assignment PIN_58 -to nSWE
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set_location_assignment PIN_62 -to nRAS
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set_location_assignment PIN_61 -to nCAS
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set_location_assignment PIN_64 -to C25M
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set_location_assignment PIN_66 -to RCKE
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set_location_assignment PIN_67 -to nRCS
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set_location_assignment PIN_68 -to SA[12]
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set_location_assignment PIN_69 -to SBA[0]
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set_location_assignment PIN_70 -to SA[11]
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set_location_assignment PIN_71 -to SBA[1]
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set_location_assignment PIN_72 -to SA[9]
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set_location_assignment PIN_73 -to SA[10]
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set_location_assignment PIN_74 -to SA[8]
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set_location_assignment PIN_75 -to SA[0]
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set_location_assignment PIN_76 -to SA[4]
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set_location_assignment PIN_77 -to SA[6]
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set_location_assignment PIN_78 -to SA[7]
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set_location_assignment PIN_81 -to SA[1]
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set_location_assignment PIN_82 -to SA[2]
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set_location_assignment PIN_83 -to SA[5]
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set_location_assignment PIN_84 -to SA[3]
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set_location_assignment PIN_85 -to DQML
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set_location_assignment PIN_86 -to RD[0]
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set_location_assignment PIN_87 -to RD[1]
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set_location_assignment PIN_88 -to RD[2]
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set_location_assignment PIN_89 -to RD[3]
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set_location_assignment PIN_90 -to RD[4]
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set_location_assignment PIN_91 -to RD[5]
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set_location_assignment PIN_92 -to RD[6]
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set_location_assignment PIN_97 -to RA[2]
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set_location_assignment PIN_98 -to RA[1]
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set_location_assignment PIN_96 -to SetFW[0]
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set_location_assignment PIN_95 -to SetFW[1]
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set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 1
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set_global_assignment -name IOBANK_VCCIO 3.3V -section_id 2 |