600 lines
14 KiB
Verilog
Executable File
600 lines
14 KiB
Verilog
Executable File
module GR8RAM(C25M, PHI1, nIOSEL, nDEVSEL, nIOSTRB,
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RA, RB6, nRWE, nROE, nAOE, Adir, nRCS,
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RD, nDOE, Ddir,
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SBA, SA, nSCS, nRAS, nCAS, nSWE, DQML, DQMH, SCKE, SD,
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nRST, nPreBOD,
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DMAin, DMAout, INTin, INTout,
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nIRQout, nINHout, nDMAout, nNMIout);
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/* Clock inputs */
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input C25M, PHI1;
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wire PHI0 = ~PHI1;
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/* Reset inputs */
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input nRST, nPreBOD;
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reg nRSTr0;
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always @(posedge C25M) begin
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nRSTr0 <= nRST;
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end
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/* Select inputs */
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input nIOSEL, nDEVSEL, nIOSTRB;
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/* Synchronized select inputs */
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reg nDEVSELr0, nDEVSELr1;
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reg nIOSELr0;
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reg nIOSTRBr0;
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always @(posedge C25M) begin
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nDEVSELr0 <= nDEVSEL;
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nDEVSELr1 <= nDEVSELr0;
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nIOSELr0 <= nIOSEL;
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nIOSTRBr0 <= nIOSTRB;
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end
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/* DEVSEL-based state counter */
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wire [9:0] DEVSELe = {DEVSELer[9:1], nDEVSELr1 && ~nDEVSELr0 && nRSTr0}
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reg [9:1] DEVSELer;
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always @(posedge C25M) begin
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DEVSELer[9:1] <= DEVSELe[8:0];
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end
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/* Flash Control */
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output nRCS = ~((~nIOSEL || (~nIOSTRB && IOROMEN)) && CSDBEN && nRST);
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output nROE = ~nRWE;
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/* 6502/Flash Data Bus */
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inout RD = RDOE ? Rdout : 8'bZ;
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wire RDOE = ~nDEVSEL && nRST;
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wire RDout =
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AddrLSelA ? Addr[7:0] :
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AddrMSelA ? Addr[15:8] :
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AddrHSelA ? Addr[23:16] :
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DataSelA ? Addr==0 ? Data0[7:0] : Data[7:0] :
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8'h57;
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output nDOE = ~((~nDEVSEL || ~nIOSEL || (~nIOSTRB && IOROMEN)) && CSDBEN && nRST);
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output Ddir = ~nRWE;
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/* Data bus / ROM chip select delay */
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reg CSDBEN = 0;
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always @(posedge C25M, negedge nRST) begin
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if (~nRST) CSDBEN <= 1'b0;
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else CSDBEN <= ~nDEVSELr0 || ~nIOSELr0 || ~nIOSTRBr0;
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end
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/* IOROMEN control */
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wire IOROMEN = IOROMEN0 ^ IOROMEN1;
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reg IOROMEN0 = 0;
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reg IOROMEN1 = 0;
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always @(negedge nIOSEL, negedge nRST) begin
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if (~nRST) IOROMEN0 <= 1'b0; // On reset, set both to 0; 0 ^ 0 == 0
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else IOROMEN0 <= ~IOROMEN1; // Enable; X ^ ~X == 1
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end
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always @(negedge nIOSTRB, negedge nRST) begin
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if (~nRST) IOROMEN1 <= 1'b0; // On reset, set both to 0; 0 ^ 0 == 0
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else if (RA[10:0] == 11'h7FF) IOROMEN1 <= IOROMEN0; // Disable; X^X==0
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end
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/* 6502/Flash Address Bus */
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input [15:0] RA;
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input nRWE;
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output nAOE = 0;
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output Adir = 1;
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reg [3:0] RAr;
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reg nRWEr;
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always @(posedge nDEVSEL) begin
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// Latch RA and nRWE at end of DEVSEL access
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RAr[3:0] <= RA[3:0];
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nRWEr <= nRWE;
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end
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/* Register Select Signals */
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wire AddrLSelA = RA[3:0] == 4'h0;
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wire AddrMSelA = RA[3:0] == 4'h1;
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wire AddrHSelA = RA[3:0] == 4'h2;
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wire DataSelA = RA[3:0] == 4'h3;
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wire DMAAddrLSelA = RA[3:0] == 4'h4;
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wire DMAAddrHSelA = RA[3:0] == 4'h5;
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wire DMALenLSelA = RA[3:0] == 4'h6;
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wire DMALenHSelA = RA[3:0] == 4'h7;
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wire MagicSelA = RA[3:0] == 4'h8;
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wire CfgSelA = RA[3:0] == 4'h9;
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wire RAMMaskSelA = RA[3:0] == 4'hB;
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wire BankHSelA = RA[3:0] == 4'hE;
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wire BankLSelA = RA[3:0] == 4'hF;
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/* SDRAM Address / Flash Bank Bus */
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output [1:0] SBA = SAmux ? SBAreg[1:0] :
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~nIOSTRB ? {
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BankC8[4], // SBA0, Bank4
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BankC8[2] // SBA1, Bank2
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} : { // IOSEL
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1'b1, // SBA0, Bank4
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1'b1 // SBA1, Bank2
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};
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output [12:0] SA = SAmux ? SAreg[12:0] :
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~nIOSTRB ? {
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SAreg[0], // SA0
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BankC8[11], // SA1, Bank11
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BankC8[8], // SA2, Bank8
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SAreg[3], // SA3
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SAreg[4], // SA4
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BankC8[7], // SA5, Bank7
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SAreg[6], // SA6
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BankC8[10], // SA7, Bank10
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BankC8[9], // SA8, Bank9
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BankC8[1], // SA9, Bank1
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BankC8[0], // SA10, Bank0
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BankC8[3], // SA11, Bank3
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BankC8[5] ^ BankCX[5] // SA12, Bank5
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} : { // IOSEL
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SAreg[0], // SA0
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1'b0, // SA1, Bank11
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1'b0, // SA2, Bank8
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SAreg[3], // SA3
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SAreg[4], // SA4
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1'b1, // SA5, Bank7
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SAreg[6], // SA6
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1'b0, // SA7, Bank10
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1'b0, // SA8, Bank9
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1'b1, // SA9, Bank1
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1'b1, // SA10, Bank0
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1'b1, // SA11, Bank3
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BankCX[5] // SA12, Bank5
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};
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output RB6 = ~nIOSTRB ? BankC8[6] ^ BankCX[6] : BankCX[6];
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reg SAmux = 1'b0;
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reg [1:0] SBAreg;
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reg [12:0] SAreg;
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/* SDRAM Data Bus */
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inout [7:0] SD = SDOE ? WRD : 8'bZ;
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reg SDOE = 0;
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reg [7:0] WRD = 0;
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always @(posedge nDEVSEL) begin
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WRD[7:0] <= RD[7:0];
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if (nRSTr0 && DataSelA && ~nRWE && Addr==0) Data0[7:0] <= RD[7:0];
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end
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/* SDRAM Control Bus */
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output reg nSCS = 1;
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output reg nRAS = 1;
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output reg nCAS = 1;
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output reg nSWE = 1;
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output reg DQML = 1;
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output reg DQMH = 1;
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output reg SCKE = 1;
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/* INT/DMA in/out */
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input DMAin;
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input INTin;
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output DMAout = DMAin;
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output INTout = INTin;
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/* IRQ, NMI, DMA, INH outputs (open-drain is external) */
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output nIRQ = 1;
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output nNMI = 1;
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output nDMA = 1;
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output nINH = 1;
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/* Refresh/Init Counter */
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reg [19:0] Tick;
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always @(posedge C25M) begin
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Tick <= Tick+1;
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end
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reg InitDone = 0;
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always @(posedge C25M) begin
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if (Tick[19:0]==20'hFFFFF) InitDone <= 1'b1;
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end
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reg RefWake = 0;
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reg RefDone = 0;
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/* User-Accessible Registers */
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reg [23:0] Addr = 0;
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reg [7:0] Data = 0;
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reg [7:0] Data0 = 0;
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reg [11:0] BankC8 = 0; // Bits 9:8 are XORed with BankCX
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reg [6:5] BankCX = 0; // Bank CX is init value
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reg ExtBankEN = 0;
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/* Set/Increment Address Register */
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always @(posedge C25M, negedge nRST) begin
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if (~nRST) begin
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Addr <= 0;
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end else begin
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if (DEVSELe[0] && ~nRWEr) begin // Write address register
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if (RAr[3:0]==4'h0) begin // AddrL
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Addr[7:0] <= WRD[7:0];
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if (Addr[7] & ~WRD[7]) Addr[23:8] <= Addr[23:8]+1;
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end else if (RAr[3:0]==4'h1) begin // AddrM
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Addr[15:8] <= WRD[7:0];
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if (Addr[15] & ~WRD[7]) Addr[23:16] <= Addr[23:16]+1;
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end else if (RAr[3:0]==4'h2) begin // AddrH
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Addr[23:16] <= WRD[7:0];
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end
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end else if (DEVSELe[2] && RAr[3:0]==4'h3) begin // R/W data
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Addr[23:0] <= Addr[23:0]+1;
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end
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end
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end
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/* Set bank */
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always @(posedge nDEVSEL, negedge nRST) begin
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if (~nRST) begin
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BankC8 <= 0;
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end else begin
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if (~nRWE) begin
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if (RAr[3:0]==4'hE && ExtBankEN) begin
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BankC8[11:10] <= WRD[3:2];
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BankC8[9:8] <= WRD[1:0] ^ BankCX[9:8];
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end else if (RAr[3:0]==4'hF) begin
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BankC8[7] <= WRD[7] & ExtBankEN;
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BankC8[6:0] <= WRD[6:0];
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end
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end
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end
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end
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/* Latch read data */
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always @(posedge C25M) begin
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if (DEVSELe[9]) Data[7:0] <= SDD[7:0];
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end
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/* SDRAM Control */
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always @(posedge C25M) begin
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if (~InitDone) begin
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if (Tick[19:8]==12'hFFF) begin
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if (Tick[3:0]==4'h8) begin
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if (Tick[7:4]==4'h0) begin
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// PC all
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SCKE <= 1'b1;
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nSCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nSWE <= 1'b0;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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SAreg[10] <= 1'b1; // "all"
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end else if (Tick[7:4]==4'h7) begin
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// Load mode register
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SCKE <= 1'b1;
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nSCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nSWE <= 1'b0;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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SAreg[11] <= 1'b0; // Reserved in mode register
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end else begin
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// AREF
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SCKE <= 1'b1;
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nSCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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end
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end else begin
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// NOP
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SCKE <= 1'b1;
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nSCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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end
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end else begin
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// NOP ckdis
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SCKE <= 1'b0;
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nSCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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end
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// Mode register contents
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SBAreg[1:0] <= 2'b00; // Reserved
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SAreg[11] <= 1'b0; // Reserved
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SAreg[9] <= 1'b1; // "1" for single write mode
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SAreg[8] <= 1'b0; // Reserved
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SAreg[7] <= 1'b0; // "0" for not test mode
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SAreg[6:4] <= 3'b010; // "2" for CAS latency 2
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SAreg[3] <= 1'b0; // "0" for sequential burst (not used)
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SAreg[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
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SAmux <= 1'b1;
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RefDone <= 1'b0;
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RefWake <= 1'b0;
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end else if (DEVSELe[0] && RAr[3:0]==4'h3) begin
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// NOP
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SCKE <= ~nRWEr;
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nSCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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SAmux <= 1'b1;
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RefWake <= 1'b0;
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end else if (DEVSELe[1] && RAr[3:0]==4'h3) begin
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// ACT
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SCKE <= ~nRWEr;
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nSCS <= nRWEr;
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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// Row address
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SBAreg[1:0] <= Addr[23:22];
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SAreg[12] <= 1'b0;
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SAreg[11:0] <= Addr[21:10];
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SAmux <= 1'b1;
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RefWake <= 1'b0;
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end else if (DEVSELe[2] && RAr[3:0]==4'h3) begin
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// WR/NOP
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SCKE <= ~nRWEr;
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nSCS <= nRWEr;
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nRAS <= 1'b1;
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nCAS <= 1'b0;
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nSWE <= 1'b0;
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DQML <= Addr[0];
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DQMH <= ~Addr[0];
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// Column address
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SBAreg[1:0] <= Addr[23:22];
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SAreg[12:11] <= 2'b00;
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SAreg[9] <= 1'b0;
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SAreg[8:0] <= Addr[9:1];
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// Auto-precharge only if row will increment
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SAreg[10] <= Addr[9:0]==10'h3FF;
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SAmux <= 1'b1;
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RefWake <= 1'b0;
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end else if (DEVSELe[3] && RAr[3:0]==4'h3) begin
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// NOP
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SCKE <= ~nRWEr;
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nSCS <= nRWEr;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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SAmux <= 1'b0;
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RefWake <= 1'b0;
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end else if (DEVSELe[4] && RAr[3:0]==4'h3) begin
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// NOP (auto-precharge from previous write)
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SCKE <= 1'b1;
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nSCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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SAmux <= 1'b0;
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RefWake <= 1'b0;
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end else if (DEVSELe[5] && RAr[3:0]==4'h3) begin
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// ACT only if WR AP just occurred / NOP
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SCKE <= 1'b1;
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nSCS <= ~nRWEr && ~SAreg[10];
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nRAS <= 1'b0;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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// Row address
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SBAreg[1:0] <= Addr[23:22];
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SAreg[12] <= 1'b0;
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SAreg[11:0] <= Addr[21:10];
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SAmux <= 1'b1;
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RefWake <= 1'b0;
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end else if (DEVSELe[6] && RAr[3:0]==4'h3) begin
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// RD
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SCKE <= 1'b1;
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nSCS <= 1'b0;
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nRAS <= 1'b1;
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nCAS <= 1'b0;
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nSWE <= 1'b1;
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DQML <= Addr[0];
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DQMH <= ~Addr[0];
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// Column address
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SBAreg[1:0] <= Addr[23:22];
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SAreg[12:11] <= 2'b00;
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SAreg[10] <= 1'b1; // auto-precharge
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SAreg[9] <= 1'b0;
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SAreg[8:0] <= Addr[9:1];
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SAmux <= 1'b1;
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RefWake <= 1'b0;
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end else if (DEVSELe[7] && RAr[3:0]==4'h3) begin
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// NOP
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SCKE <= 1'b1;
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nSCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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SAmux <= 1'b0;
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RefWake <= 1'b0;
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end else begin
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if (Tick[5] && ~RefDone) begin
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if (~RefWake) begin
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// NOP
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SCKE <= 1'b1;
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nSCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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RefWake <= 1'b1;
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end else begin
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// AREF
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SCKE <= 1'b1;
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nSCS <= 1'b0;
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nRAS <= 1'b0;
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nCAS <= 1'b0;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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RefWake <= 1'b0;
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RefDone <= 1'b1;
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end
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end else begin
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// NOP ckdis
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SCKE <= 1'b0;
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nSCS <= 1'b1;
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nRAS <= 1'b1;
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nCAS <= 1'b1;
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nSWE <= 1'b1;
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DQML <= 1'b1;
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DQMH <= 1'b1;
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RefWake <= 1'b0;
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if (Tick[5]) RefDone <= 1'b0;
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end
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SAmux <= 1'b0;
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end
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end
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|
|
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/* UFM Interface */
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reg ARCLK = 0; // UFM address register clock
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// UFM address register data input tied to 0
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reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
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reg DRCLK = 0; // UFM data register clock
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reg DRDIn = 0; // UFM data register input
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reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
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reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
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reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
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wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
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wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
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wire DRDOut; // UFM data output
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// UFM oscillator always enabled
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wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
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UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
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.arclk (ARCLK),
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.ardin (1'b0),
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.arshft (ARShift),
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.drclk (DRCLK),
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.drdin (DRDIn),
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.drshft (DRShift),
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.erase (UFMErase),
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.oscena (1'b1),
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.program (UFMProgram),
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.busy (UFMBusy),
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.drdout (DRDOut),
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.osc (UFMOsc),
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.rtpbusy (RTPBusy));
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reg UFMBr = 0; // UFMBusy registered to sync with C14M
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reg RTPBr = 0; // RTPBusy registered to sync with C14M
|
|
|
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reg [15:0] Cfg;
|
|
reg CfgLoaded = 0;
|
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// Do nothing when Tick15:14==2'h0
|
|
// Get ready when Tick15:14==2'h1
|
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// Zero AR
|
|
// Load Cfg when Tick15:14==2'h2
|
|
// Tick13:6 (256) - first half of UFM looked at
|
|
// Tick5:2 (16) - 16 bits loaded from UFM
|
|
// 0: set CfgLoaded if DRDout==1, otherwise shift DRDout into Cfg
|
|
// 1-14: continue shifting DRDout into Cfg[15:0]
|
|
// 15: shift last DRDout bit into Cfg[15:0] and increment AR
|
|
// Tick1:0 (4) - 1 bit shifted
|
|
// Do nothing when Tick15:14==2'h3
|
|
// Set CfgLoaded too
|
|
always @(posedge C25M) begin
|
|
if (~CfgLoaded) begin
|
|
if (Tick[15:14]==2'h0) begin
|
|
// Do nothing
|
|
ARShift <= 1;
|
|
ARCLK <= 0;
|
|
DRCLK <= 0;
|
|
end else if (Tick[15:14]==2'h1) begin
|
|
// Shift zeros into AR during first half
|
|
if (~Tick[13]) begin
|
|
ARShift <= 1;
|
|
ARCLK <= Tick[1];
|
|
end else begin
|
|
ARShift <= 0;
|
|
ARCLK <= 0;
|
|
end
|
|
|
|
// Load default config
|
|
Cfg[15:0] <= 16'hFFFF;
|
|
|
|
// Load indirect into DR at end
|
|
if (Tick[13:0]==14'h3FFC ||
|
|
Tick[13:0]==14'h3FFD ||
|
|
Tick[13:0]==14'h3FFE ||
|
|
Tick[13:0]==14'h3FFF || ) begin
|
|
DRCLK <= 1;
|
|
end else DRCLK <= 0;
|
|
end else if (Tick[15:14]==2'h2) begin
|
|
// Load 16 bits into Cfg register
|
|
if (Tick[5:2]==4'h0 && Tick[1:0]==0 && DRDout) begin
|
|
CfgLoaded <= 1;
|
|
end else if (Tick[1:0]==0) begin
|
|
Cfg[15:0] <= {Cfg[14:1], DRDout};
|
|
end
|
|
|
|
// Increment AR
|
|
if (Tick[5:2]==4'hE) begin
|
|
ARCLK <= 1;
|
|
end else begin
|
|
ARCLK <= 0;
|
|
end
|
|
|
|
// Load indirect into DR
|
|
if (Tick[5:2]==4'hF) begin
|
|
DRCLK <= 1;
|
|
end else begin
|
|
DRCLK <= 0;
|
|
end
|
|
|
|
ARShift <= 1'b0; // Only incrementing AR now
|
|
end else if (Tick[15:14]==2'h3) begin
|
|
// Do nothing
|
|
ARShift <= 1;
|
|
ARCLK <= 0;
|
|
DRCLK <= 0;
|
|
CfgLoaded <= 1; // in case setting at address 0xFF
|
|
end
|
|
|
|
DRShift <= 0; // Only reading DR during init, not writing UFM
|
|
DRDIn <= 0;
|
|
end else if (DEVSELe[0] && RAr[3:0]==4'h8) begin
|
|
|
|
end else begin
|
|
// Do nothing
|
|
ARShift <= 1;
|
|
ARCLK <= 0;
|
|
DRCLK <= 0;
|
|
DRShift <= 0;
|
|
DRDIn <= 0;
|
|
end
|
|
end
|
|
|
|
|
|
always @(posedge nDEVSEL, negedge nRST) begin
|
|
if (~nRST)
|
|
end
|
|
endmodule
|