74 lines
3.7 KiB
Plaintext
Executable File
74 lines
3.7 KiB
Plaintext
Executable File
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 1991-2013 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus II 32-bit
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# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
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# Date created = 13:41:40 March 15, 2021
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# GR8RAM_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "MAX II"
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set_global_assignment -name DEVICE EPM240T100C5
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set_global_assignment -name TOP_LEVEL_ENTITY GR8RAM
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:41:40 MARCH 15, 2021"
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
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set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
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set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE AREA
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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set_global_assignment -name SAFE_STATE_MACHINE OFF
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set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
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set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ALWAYS
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set_global_assignment -name AUTO_RESOURCE_SHARING ON
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set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
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set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
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set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
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set_global_assignment -name ALM_REGISTER_PACKING_EFFORT HIGH
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set_global_assignment -name MUX_RESTRUCTURE ON
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set_global_assignment -name STATE_MACHINE_PROCESSING "MINIMAL BITS"
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set_global_assignment -name SYNTHESIS_SEED 123
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set_global_assignment -name SEED 235
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set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII "MINIMIZE AREA"
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set_global_assignment -name ROUTER_REGISTER_DUPLICATION OFF
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set_global_assignment -name VERILOG_FILE GR8RAM.v |