    Synthesis Report
    #Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
    #install: C:\lscc\diamond\3.12\synpbase
    #OS: Windows 8 6.2
    #Hostname: ZANEMACWIN11

    # Thu Dec 28 23:23:19 2023

    #Implementation: impl1

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode
    ###########################################################[

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode
    @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
    @I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
    @I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
    @I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
    @I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
    Verilog syntax check successful!
    File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
    File \\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v changed - recompiling
    Selecting top level module RAM2E
    @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
    Running optimization stage 1 on VHI .......
    Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
    @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
    Running optimization stage 1 on VLO .......
    Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
    @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
    Running optimization stage 1 on EFB .......
    Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
    @N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
    Running optimization stage 1 on REFB .......
    Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
    @N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
    Running optimization stage 1 on RAM2E_UFM .......
    Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
    @N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
    Running optimization stage 1 on RAM2E .......
    Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
    Running optimization stage 2 on RAM2E .......
    @N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
    Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
    Running optimization stage 2 on RAM2E_UFM .......
    @N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
    Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
    Running optimization stage 2 on REFB .......
    Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
    Running optimization stage 2 on EFB .......
    Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
    Running optimization stage 2 on VLO .......
    Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
    Running optimization stage 2 on VHI .......
    Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)

    At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Dec 28 23:23:19 2023

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode
    File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\layer0.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Dec 28 23:23:20 2023

    ###########################################################]

    For a summary of runtime and memory usage for all design units, please see file:
    ==========================================================
    @L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv

    @END

    At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Dec 28 23:23:20 2023

    ###########################################################]
    ###########################################################[

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @

    @N|Running in 64-bit mode
    File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling

    At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime

    Process completed successfully.
    # Thu Dec 28 23:23:21 2023

    ###########################################################]
    # Thu Dec 28 23:23:21 2023

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)

    Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)

    Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
    @L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt
    See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt"
    @N: MF916 |Option synthesis_strategy=base is enabled.
    @N: MF248 |Running in 64-bit mode.
    @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)

    @N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
    @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.
    @N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
    @N: FX493 |Applying initial value "0" on instance PHI1r.
    @N: FX493 |Applying initial value "0" on instance RWSel.
    @N: FX493 |Applying initial value "0" on instance Ready.
    @N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
    @N: FX493 |Applying initial value "0" on instance CmdLEDGet.
    @N: FX493 |Applying initial value "0" on instance CmdLEDSet.
    @N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
    @N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
    @A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
    @N: FX493 |Applying initial value "1" on instance DQMH.
    @A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
    @N: FX493 |Applying initial value "1" on instance DQML.
    @A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
    @N: FX493 |Applying initial value "0000" on instance S[3:0].
    @N: FX493 |Applying initial value "1" on instance CKE.
    @N: FX493 |Applying initial value "1" on instance nRWE.
    @N: FX493 |Applying initial value "1" on instance nRWEout.
    @N: FX493 |Applying initial value "1" on instance nCAS.
    @N: FX493 |Applying initial value "1" on instance nCASout.
    @N: FX493 |Applying initial value "1" on instance nRAS.
    @N: FX493 |Applying initial value "1" on instance nRASout.

    Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)

    Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)

    Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)

    Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)

    @N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E

    Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)

    Clock Summary
    ******************

              Start      Requested     Requested     Clock        Clock                Clock
    Level     Clock      Frequency     Period        Type         Group                Load
    ----------------------------------------------------------------------------------------
    0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     122

    0 -       System     100.0 MHz     10.000        system       system_clkgroup      0
    ========================================================================================

    Clock Load Summary
    ***********************

               Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin
    Clock      Load      Pin            Seq Example     Seq Example       Comb Example
    ----------------------------------------------------------------------------------------
    C14M       122       C14M(port)     DOEEN.C         -                 un1_C14M.I[0](inv)

    System     0         -              -               -                 -
    ========================================================================================

    ICG Latch Removal Summary:
    Number of ICG latches removed: 0
    Number of ICG latches not removed:	0
    For details review file gcc_ICG_report.rpt

    @S |Clock Optimization Summary

    #### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[

    1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
    0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
    0 instances converted, 0 sequential instances remain driven by gated/generated clocks

    =========================== Non-Gated/Non-Generated Clocks ============================
    Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
    ---------------------------------------------------------------------------------------
    @KP:ckid0_0       C14M                port                   122        nRAS
    =======================================================================================

    ##### END OF CLOCK OPTIMIZATION REPORT ######

    @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
    Finished Pre Mapping Phase.

    Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)

    Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)

    Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)

    Pre-mapping successful!

    At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)

    Process took 0h:00m:01s realtime, 0h:00m:01s cputime
    # Thu Dec 28 23:23:23 2023

    ###########################################################]
    # Thu Dec 28 23:23:23 2023

    Copyright (C) 1994-2021 Synopsys, Inc.
    This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
    and may only be used pursuant to the terms and conditions of a written license agreement
    with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
    Synopsys software or the associated documentation is strictly prohibited.
    Tool: Synplify Pro (R)
    Build: R-2021.03L-SP1
    Install: C:\lscc\diamond\3.12\synpbase
    OS: Windows 6.2

    Hostname: ZANEMACWIN11

    Implementation : impl1
    Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @

    Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)

    @N: MF916 |Option synthesis_strategy=base is enabled.
    @N: MF248 |Running in 64-bit mode.
    @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)

    Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)

    Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)

    Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)

    Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)

    Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)

    Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)

    @N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0]
    @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved.

    Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)

    Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)

    Available hyper_sources - for debug and ip models
    	None Found

    Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)

    Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)

    Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)

    Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)

    Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)

    Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)

    Pass		 CPU time		Worst Slack		Luts / Registers
    ------------------------------------------------------------
       1		0h:00m:01s		    33.71ns		 284 /       122

    Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)

    @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
    @A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.
    @A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell.

    Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)

    Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)

    Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm

    Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)

    Writing EDIF Netlist and constraint files
    @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
    @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF

    Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)

    Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)

    Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)

    @W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
    @N: MT615 |Found clock C14M with period 69.84ns

    ##### START OF TIMING REPORT #####[
    # Timing report written on Thu Dec 28 23:23:26 2023
    #

    Top view:               RAM2E
    Requested Frequency:    14.3 MHz
    Wire load mode:         top
    Paths requested:        5
    Constraint File(s):    \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc

    @N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.

    @N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.

    Performance Summary
    *******************

    Worst slack in design: 33.707

                       Requested     Estimated     Requested     Estimated                Clock        Clock
    Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group
    -------------------------------------------------------------------------------------------------------------------
    C14M               14.3 MHz      128.0 MHz     69.841        7.813         33.707     declared     default_clkgroup
    System             100.0 MHz     NA            10.000        NA            67.088     system       system_clkgroup
    ===================================================================================================================
    Estimated period and frequency reported as NA means no slack depends directly on the clock waveform

    Clock Relationships
    *******************

    Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise
    ----------------------------------------------------------------------------------------------------------
    Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack
    ----------------------------------------------------------------------------------------------------------
    System    C14M    |  69.841      67.088  |  No paths    -      |  No paths    -       |  No paths    -
    C14M      System  |  69.841      68.797  |  No paths    -      |  No paths    -       |  No paths    -
    C14M      C14M    |  69.841      62.028  |  No paths    -      |  34.920      33.707  |  No paths    -
    ==========================================================================================================
     Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
           'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

    Interface Information
    *********************

    No IO constraint found

    ====================================
    Detailed Report for Clock: C14M
    ====================================

    Starting Points with Worst Slack
    ********************************

                 Starting                                    Arrival
    Instance     Reference     Type        Pin     Net       Time        Slack
                 Clock
    ---------------------------------------------------------------------------
    RA[0]        C14M          FD1P3AX     Q       RA[0]     1.108       33.707
    RA[3]        C14M          FD1P3AX     Q       RA[3]     1.108       33.707
    RA[1]        C14M          FD1P3AX     Q       RA[1]     1.044       33.771
    RA[2]        C14M          FD1P3AX     Q       RA[2]     1.044       33.771
    RA[4]        C14M          FD1P3AX     Q       RA[4]     1.044       33.771
    RA[5]        C14M          FD1P3AX     Q       RA[5]     1.044       33.771
    RA[6]        C14M          FD1P3AX     Q       RA[6]     1.044       33.771
    RA[7]        C14M          FD1P3AX     Q       RA[7]     1.044       33.771
    RA[8]        C14M          FD1P3AX     Q       RA[8]     1.044       33.771
    RA[9]        C14M          FD1P3AX     Q       RA[9]     1.044       33.771
    ===========================================================================

    Ending Points with Worst Slack
    ******************************

                     Starting                                     Required
    Instance         Reference     Type         Pin     Net       Time         Slack
                     Clock
    ---------------------------------------------------------------------------------
    RAout_0io[0]     C14M          OFS1P3DX     D       RA[0]     34.815       33.707
    RAout_0io[3]     C14M          OFS1P3DX     D       RA[3]     34.815       33.707
    RAout_0io[1]     C14M          OFS1P3DX     D       RA[1]     34.815       33.771
    RAout_0io[2]     C14M          OFS1P3DX     D       RA[2]     34.815       33.771
    RAout_0io[4]     C14M          OFS1P3DX     D       RA[4]     34.815       33.771
    RAout_0io[5]     C14M          OFS1P3DX     D       RA[5]     34.815       33.771
    RAout_0io[6]     C14M          OFS1P3DX     D       RA[6]     34.815       33.771
    RAout_0io[7]     C14M          OFS1P3DX     D       RA[7]     34.815       33.771
    RAout_0io[8]     C14M          OFS1P3DX     D       RA[8]     34.815       33.771
    RAout_0io[9]     C14M          OFS1P3DX     D       RA[9]     34.815       33.771
    =================================================================================

    Worst Path Information
    ***********************

    Path information for path number 1:
          Requested Period:                      34.920
        - Setup time:                            0.106
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         34.815

        - Propagation time:                      1.108
        - Clock delay at starting point:         0.000 (ideal)
        = Slack (critical) :                     33.707

        Number of logic level(s):                0
        Starting point:                          RA[0] / Q
        Ending point:                            RAout_0io[0] / D
        The start point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
        The end   point is clocked by            C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK

    Instance / Net                  Pin      Pin               Arrival     No. of
    Name               Type         Name     Dir     Delay     Time        Fan Out(s)
    ---------------------------------------------------------------------------------
    RA[0]              FD1P3AX      Q        Out     1.108     1.108 r     -
    RA[0]              Net          -        -       -         -           3
    RAout_0io[0]       OFS1P3DX     D        In      0.000     1.108 r     -
    =================================================================================

    ====================================
    Detailed Report for Clock: System
    ====================================

    Starting Points with Worst Slack
    ********************************

                                   Starting                                          Arrival
    Instance                       Reference     Type     Pin         Net            Time        Slack
                                   Clock
    ---------------------------------------------------------------------------------------------------
    ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
    ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
    ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
    ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
    ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
    ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
    ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
    ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
    ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
    ===================================================================================================

    Ending Points with Worst Slack
    ******************************

                             Starting                                                                  Required
    Instance                 Reference     Type        Pin     Net                                     Time         Slack
                             Clock
    ----------------------------------------------------------------------------------------------------------------------
    ram2e_ufm.RWMask[0]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
    ram2e_ufm.RWMask[1]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
    ram2e_ufm.RWMask[2]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
    ram2e_ufm.RWMask[3]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
    ram2e_ufm.RWMask[4]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
    ram2e_ufm.RWMask[5]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
    ram2e_ufm.RWMask[6]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
    ram2e_ufm.RWMask[7]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
    ram2e_ufm.LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0_0[0]           69.369       67.736
    ram2e_ufm.wb_cyc_stb     System        FD1P3AX     SP      un1_CmdSetRWBankFFChip13_1_i_0_0[0]     69.369       67.736
    ======================================================================================================================

    Worst Path Information
    ***********************

    Path information for path number 1:
          Requested Period:                      69.841
        - Setup time:                            0.472
        + Clock delay at ending point:           0.000 (ideal)
        = Required time:                         69.369

        - Propagation time:                      2.282
        - Clock delay at starting point:         0.000 (ideal)
        - Estimated clock delay at start point:  -0.000
        = Slack (non-critical) :                 67.088

        Number of logic level(s):                2
        Starting point:                          ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
        Ending point:                            ram2e_ufm.RWMask[0] / SP
        The start point is clocked by            System [rising]
        The end   point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK

    Instance / Net                                                 Pin        Pin               Arrival     No. of
    Name                                              Type         Name       Dir     Delay     Time        Fan Out(s)
    ------------------------------------------------------------------------------------------------------------------
    ram2e_ufm.ufmefb.EFBInst_0                        EFB          WBACKO     Out     0.000     0.000 r     -
    wb_ack                                            Net          -          -       -         -           5
    ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     B          In      0.000     0.000 r     -
    ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     Z          Out     1.017     1.017 r     -
    un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]               Net          -          -       -         -           1
    ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     D          In      0.000     1.017 r     -
    ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -
    un1_RWMask_0_sqmuxa_1_i_0_0[0]                    Net          -          -       -         -           8
    ram2e_ufm.RWMask[0]                               FD1P3AX      SP         In      0.000     2.282 r     -
    ==================================================================================================================

    ##### END OF TIMING REPORT #####]

    Timing exceptions that could not be applied

    Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)

    Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)

    ---------------------------------------
    Resource Usage Report
    Part: lcmxo2_1200hc-4

    Register bits: 122 of 1280 (10%)
    PIC Latch:       0
    I/O cells:       69

    Details:
    BB:             8
    CCU2D:          9
    EFB:            1
    FD1P3AX:        61
    FD1P3IX:        1
    FD1S3AX:        21
    FD1S3AY:        4
    FD1S3IX:        6
    GSR:            1
    IB:             21
    IFS1P3DX:       1
    INV:            1
    OB:             40
    OFS1P3BX:       5
    OFS1P3DX:       21
    OFS1P3IX:       2
    ORCALUT4:       277
    PFUMX:          3
    PUR:            1
    VHI:            3
    VLO:            3
    Mapper successful!

    At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 217MB)

    Process took 0h:00m:03s realtime, 0h:00m:03s cputime
    # Thu Dec 28 23:23:26 2023

    ###########################################################]