
Loading design for application trce from file ram2e_lcmxo2_640hc_impl1_map.ncd.
Design name: RAM2E
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-640HC
Package:     TQFP100
Performance: 4
Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
Package Status:                     Final          Version 1.39.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:23:29 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
Design file:     ram2e_lcmxo2_640hc_impl1_map.ncd
Preference file: ram2e_lcmxo2_640hc_impl1.prf
Device,speed:    LCMXO2-640HC,4
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
            1611 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 58.937ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              S[2]  (from C14M_c +)
   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)

   Delay:              10.827ns  (31.6% logic, 68.4% route), 7 logic levels.

 Constraint Details:

     10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
     69.930ns delay constraint less
      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns

 Physical Path Details:

      Data path SLICE_34 to ram2e_ufm/SLICE_47:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.452   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from C14M_c)
ROUTE        50   e 1.234    SLICE_34.Q0 to    SLICE_35.A0 S[2]
CTOF_DEL    ---     0.495    SLICE_35.A0 to    SLICE_35.F0 SLICE_35
ROUTE         7   e 1.234    SLICE_35.F0 to *m/SLICE_80.D1 N_551
CTOF_DEL    ---     0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
ROUTE         8   e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
CTOF_DEL    ---     0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
ROUTE         5   e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
CTOF_DEL    ---     0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
ROUTE         1   e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
CTOF_DEL    ---     0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
ROUTE         1   e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
CTOF_DEL    ---     0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
ROUTE         1   e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
                  --------
                   10.827   (31.6% logic, 68.4% route), 7 logic levels.

Report:   90.967MHz is the maximum frequency for this preference.

Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   90.967 MHz|   7  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 1 clocks:

Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;


Timing summary (Setup):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)

--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
Thu Dec 28 23:23:29 2023

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
Design file:     ram2e_lcmxo2_640hc_impl1_map.ncd
Preference file: ram2e_lcmxo2_640hc_impl1.prf
Device,speed:    LCMXO2-640HC,M
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------

BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------



================================================================================
Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
            1611 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------


Passed: The following path meets requirements by 0.447ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              FS[0]  (from C14M_c +)
   Destination:    FF         Data in        FS[0]  (to C14M_c +)

   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.

 Constraint Details:

      0.434ns physical path delay SLICE_0 to SLICE_0 meets
     -0.013ns DIN_HLD and
      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns

 Physical Path Details:

      Data path SLICE_0 to SLICE_0:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.133    SLICE_0.CLK to     SLICE_0.Q1 SLICE_0 (from C14M_c)
ROUTE         6   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
CTOF_DEL    ---     0.101     SLICE_0.A1 to     SLICE_0.F1 SLICE_0
ROUTE         1   e 0.001     SLICE_0.F1 to    SLICE_0.DI1 FS_s[0] (to C14M_c)
                  --------
                    0.434   (53.9% logic, 46.1% route), 2 logic levels.

Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   2  
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


Clock Domains Analysis
------------------------

Found 1 clocks:

Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;


Timing summary (Hold):
---------------

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)



Timing summary (Setup and Hold):
---------------

Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------

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