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301 lines
11 KiB
HTML
301 lines
11 KiB
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<HEAD><TITLE>Place & Route Report</TITLE>
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.3.469.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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Fri Jun 07 20:49:59 2024
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C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
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RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
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RAM2E_LCMXO2_640HC_impl1.prf -gui
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Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
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<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
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Level/ Number Worst Timing Worst Timing Run NCD
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Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
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---------- -------- ----- ------ ----------- ----------- ---- ------
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5_1 * 0 56.334 0 0.379 0 16 Completed
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* : Design saved.
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Total (real) run time for 1-seed: 16 secs
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par done!
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Note: user must run 'Trace' for timing closure signoff.
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Lattice Place and Route Report for Design "RAM2E_LCMXO2_640HC_impl1_map.ncd"
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Fri Jun 07 20:49:59 2024
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<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
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PAR: Place And Route Diamond (64-bit) 3.11.3.469.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
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Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
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Placement level-cost: 5-1.
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Routing Iterations: 6
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Loading design for application par from file RAM2E_LCMXO2_640HC_impl1_map.ncd.
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Design name: RAM2E
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NCD version: 3.3
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Vendor: LATTICE
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Device: LCMXO2-640HC
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Package: TQFP100
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Performance: 4
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Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.11_x64/ispfpga.
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Package Status: Final Version 1.39.
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Performance Hardware Data Status: Final Version 34.4.
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License checked out.
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Ignore Preference Error(s): True
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<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
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PIO (prelim) 70+4(JTAG)/80 93% used
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70+4(JTAG)/79 94% bonded
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IOLOGIC 22/80 27% used
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SLICE 148/320 46% used
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EFB 1/1 100% used
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Number of Signals: 465
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Number of Connections: 1330
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Pin Constraint Summary:
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70 out of 70 pins locked (100% locked).
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The following 1 signal is selected to use the primary clock routing resources:
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C14M_c (driver: C14M, clk load #: 85)
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WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
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The following 1 signal is selected to use the secondary clock routing resources:
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RWBank14 (driver: ram2e_ufm/SLICE_82, clk load #: 0, sr load #: 0, ce load #: 11)
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No signal is selected as Global Set/Reset.
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Starting Placer Phase 0.
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............
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Finished Placer Phase 0. REAL time: 2 secs
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Starting Placer Phase 1.
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.....................
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Placer score = 71540.
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Finished Placer Phase 1. REAL time: 9 secs
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Starting Placer Phase 2.
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.
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Placer score = 70933
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Finished Placer Phase 2. REAL time: 9 secs
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<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
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Global Clock Resources:
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CLK_PIN : 0 out of 8 (0%)
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General PIO: 1 out of 80 (1%)
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DCM : 0 out of 2 (0%)
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DCC : 0 out of 8 (0%)
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Global Clocks:
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PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 85
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SECONDARY "RWBank14" from F0 on comp "ram2e_ufm/SLICE_82" on site "R2C9D", clk load = 0, ce load = 11, sr load = 0
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PRIMARY : 1 out of 8 (12%)
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SECONDARY: 1 out of 8 (12%)
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I/O Usage Summary (final):
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70 + 4(JTAG) out of 80 (92.5%) PIO sites used.
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70 + 4(JTAG) out of 79 (93.7%) bonded PIO sites used.
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Number of PIO comps: 70; differential: 0.
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Number of Vref pins used: 0.
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I/O Bank Usage Summary:
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+----------+----------------+------------+-----------+
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| I/O Bank | Usage | Bank Vccio | Bank Vref |
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+----------+----------------+------------+-----------+
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| 0 | 11 / 19 ( 57%) | 3.3V | - |
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| 1 | 20 / 20 (100%) | 3.3V | - |
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| 2 | 19 / 20 ( 95%) | 3.3V | - |
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| 3 | 20 / 20 (100%) | 3.3V | - |
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+----------+----------------+------------+-----------+
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Total placer CPU time: 8 secs
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Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
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0 connections routed; 1330 unrouted.
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Starting router resource preassignment
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WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
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WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
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Signal=PHI1_c loads=5 clock_loads=3
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Completed router resource preassignment. Real time: 14 secs
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Start NBR router at 20:50:13 06/07/24
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*****************************************************************
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Info: NBR allows conflicts(one node used by more than one signal)
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in the earlier iterations. In each iteration, it tries to
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solve the conflicts while keeping the critical connections
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routed as short as possible. The routing process is said to
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be completed when no conflicts exist and all connections
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are routed.
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Note: NBR uses a different method to calculate timing slacks. The
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worst slack and total negative slack may not be the same as
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that in TRCE report. You should always run TRCE to verify
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your design.
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*****************************************************************
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Start NBR special constraint process at 20:50:13 06/07/24
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Start NBR section for initial routing at 20:50:13 06/07/24
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Level 4, iteration 1
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17(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 56.334ns/0.000ns; real time: 15 secs
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Info: Initial congestion level at 75% usage is 0
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Info: Initial congestion area at 75% usage is 0 (0.00%)
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Start NBR section for normal routing at 20:50:14 06/07/24
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Level 4, iteration 1
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7(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 56.334ns/0.000ns; real time: 15 secs
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Level 4, iteration 2
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 56.334ns/0.000ns; real time: 15 secs
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Start NBR section for setup/hold timing optimization with effort level 3 at 20:50:14 06/07/24
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Start NBR section for re-routing at 20:50:14 06/07/24
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Level 4, iteration 1
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
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Estimated worst slack/total negative slack<setup>: 56.334ns/0.000ns; real time: 15 secs
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Start NBR section for post-routing at 20:50:14 06/07/24
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End NBR router with 0 unrouted connection
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NBR Summary
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-----------
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Number of unrouted connections : 0 (0.00%)
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Number of connections with timing violations : 0 (0.00%)
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Estimated worst slack<setup> : 56.334ns
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Timing score<setup> : 0
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-----------
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Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
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WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
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Signal=PHI1_c loads=5 clock_loads=3
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Total CPU time 13 secs
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Total REAL time: 16 secs
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Completely routed.
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End of route. 1330 routed (100.00%); 0 unrouted.
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Hold time timing score: 0, hold timing errors: 0
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Timing score: 0
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Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
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All signals are completely routed.
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PAR_SUMMARY::Run status = Completed
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PAR_SUMMARY::Number of unrouted conns = 0
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PAR_SUMMARY::Worst slack<setup/<ns>> = 56.334
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PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
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PAR_SUMMARY::Worst slack<hold /<ns>> = 0.379
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PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
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PAR_SUMMARY::Number of errors = 0
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Total CPU time to completion: 13 secs
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Total REAL time to completion: 16 secs
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par done!
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Note: user must run 'Trace' for timing closure signoff.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
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