2024-06-09 05:17:38 +00:00
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Copyright (C) 1994-2018 Synopsys, Inc.
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This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
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and may only be used pursuant to the terms and conditions of a written license agreement
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with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
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Synopsys software or the associated documentation is strictly prohibited.
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Tool: Synplify Pro (R)
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Build: N-2018.03L-SP1-1
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Install: C:\lscc\diamond\3.11_x64\synpbase
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OS: Windows 6.2
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Hostname: ZANEMACWIN11
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Implementation : impl1
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2024-07-20 11:09:18 +00:00
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# Written on Fri Jul 12 16:07:14 2024
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2024-06-09 05:17:38 +00:00
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##### FILES SYNTAX CHECKED ##############################################
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Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc"
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#Run constraint checker to find more issues with constraints.
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#########################################################################
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No issues found in constraint syntax.
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Clock Summary
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*************
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Start Requested Requested Clock Clock Clock
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Level Clock Frequency Period Type Group Load
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-----------------------------------------------------------------------------------------------
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2024-07-20 11:09:18 +00:00
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0 - C14M 14.3 MHz 69.841 declared default_clkgroup 120
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0 - System 100.0 MHz 10.000 system system_clkgroup 0
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0 - RAM2E|PHI1 100.0 MHz 10.000 inferred Inferred_clkgroup_0 9
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===============================================================================================
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Clock Load Summary
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******************
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Clock Source Clock Pin Non-clock Pin Non-clock Pin
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Clock Load Pin Seq Example Seq Example Comb Example
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--------------------------------------------------------------------------------------------
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2024-07-20 11:09:18 +00:00
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C14M 120 C14M(port) RAT.C - un1_C14M.I[0](inv)
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2024-06-09 05:17:38 +00:00
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System 0 - - - -
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RAM2E|PHI1 9 PHI1(port) RefReq.C S[0].D[0] un1_PHI1.I[0](inv)
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============================================================================================
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