diff --git a/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html deleted file mode 100644 index 50e8def..0000000 --- a/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html +++ /dev/null @@ -1,140 +0,0 @@ - -Lattice TCL Log - - -
pn231218062259
-#Start recording tcl command: 12/5/2023 23:09:24
-#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
-prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-#Stop recording: 12/18/2023 06:22:59
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-pn231226182753
-#Start recording tcl command: 12/26/2023 18:26:59
-#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
-prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
-#Stop recording: 12/26/2023 18:27:53
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-pn231226232448
-#Start recording tcl command: 12/26/2023 21:40:03
-#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
-prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
-prj_run Export -impl impl1
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_src exclude "//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v"
-prj_src remove "//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v"
-#Stop recording: 12/26/2023 23:24:48
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-pn231226233648
-#Start recording tcl command: 12/26/2023 23:26:30
-#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
-prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-prj_run Export -impl impl1 -forceAll
-#Stop recording: 12/26/2023 23:36:48
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-pn231226233754
-#Start recording tcl command: 12/26/2023 23:36:58
-#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
-prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
-#Stop recording: 12/26/2023 23:37:54
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-pn231228231137
-#Start recording tcl command: 12/26/2023 23:38:54
-#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
-prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1
-#Stop recording: 12/28/2023 23:11:37
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-pn231228232404
-#Start recording tcl command: 12/28/2023 23:23:13
-#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
-prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
-prj_run Export -impl impl1
-#Stop recording: 12/28/2023 23:24:04
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- - diff --git a/CPLD/LCMXO2-1200HC/REFB.edn b/CPLD/LCMXO2-1200HC/REFB.edn deleted file mode 100644 index 034bc84..0000000 --- a/CPLD/LCMXO2-1200HC/REFB.edn +++ /dev/null @@ -1,550 +0,0 @@ -(edif REFB - (edifVersion 2 0 0) - (edifLevel 0) - (keywordMap (keywordLevel 0)) - (status - (written - (timestamp 2023 9 20 4 45 58) - (program "SCUBA" (version "Diamond (64-bit) 3.12.1.454")))) - (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 ") - (library ORCLIB - (edifLevel 0) - (technology - (numberDefinition)) - (cell VHI - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port Z - (direction OUTPUT))))) - (cell VLO - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port Z - (direction OUTPUT))))) - (cell EFB - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port WBCLKI - (direction INPUT)) - (port WBRSTI - (direction INPUT)) - (port WBCYCI - (direction INPUT)) - (port WBSTBI - (direction INPUT)) - (port WBWEI - (direction INPUT)) - (port WBADRI7 - (direction INPUT)) - (port WBADRI6 - (direction INPUT)) - (port WBADRI5 - (direction INPUT)) - (port WBADRI4 - (direction INPUT)) - (port WBADRI3 - (direction INPUT)) - (port WBADRI2 - (direction INPUT)) - (port WBADRI1 - (direction INPUT)) - (port WBADRI0 - (direction INPUT)) - (port WBDATI7 - (direction INPUT)) - (port WBDATI6 - (direction INPUT)) - (port WBDATI5 - (direction INPUT)) - (port WBDATI4 - (direction INPUT)) - (port WBDATI3 - (direction INPUT)) - (port WBDATI2 - (direction INPUT)) - (port WBDATI1 - (direction INPUT)) - (port WBDATI0 - (direction INPUT)) - (port PLL0DATI7 - (direction INPUT)) - (port PLL0DATI6 - (direction INPUT)) - (port PLL0DATI5 - (direction INPUT)) - (port PLL0DATI4 - (direction INPUT)) - (port PLL0DATI3 - (direction INPUT)) - (port PLL0DATI2 - (direction INPUT)) - (port PLL0DATI1 - (direction INPUT)) - (port PLL0DATI0 - (direction INPUT)) - (port PLL0ACKI - (direction INPUT)) - (port PLL1DATI7 - (direction INPUT)) - (port PLL1DATI6 - (direction INPUT)) - (port PLL1DATI5 - (direction INPUT)) - (port PLL1DATI4 - (direction INPUT)) - (port PLL1DATI3 - (direction INPUT)) - (port PLL1DATI2 - (direction INPUT)) - (port PLL1DATI1 - (direction INPUT)) - (port PLL1DATI0 - (direction INPUT)) - (port PLL1ACKI - (direction INPUT)) - (port I2C1SCLI - (direction INPUT)) - (port I2C1SDAI - (direction INPUT)) - (port I2C2SCLI - (direction INPUT)) - (port I2C2SDAI - (direction INPUT)) - (port SPISCKI - (direction INPUT)) - (port SPIMISOI - (direction INPUT)) - (port SPIMOSII - (direction INPUT)) - (port SPISCSN - (direction INPUT)) - (port TCCLKI - (direction INPUT)) - (port TCRSTN - (direction INPUT)) - (port TCIC - (direction INPUT)) - (port UFMSN - (direction INPUT)) - (port WBDATO7 - (direction OUTPUT)) - (port WBDATO6 - (direction OUTPUT)) - (port WBDATO5 - (direction OUTPUT)) - (port WBDATO4 - (direction OUTPUT)) - (port WBDATO3 - (direction OUTPUT)) - (port WBDATO2 - (direction OUTPUT)) - (port WBDATO1 - (direction OUTPUT)) - (port WBDATO0 - (direction OUTPUT)) - (port WBACKO - (direction OUTPUT)) - (port PLLCLKO - (direction OUTPUT)) - (port PLLRSTO - (direction OUTPUT)) - (port PLL0STBO - (direction OUTPUT)) - (port PLL1STBO - (direction OUTPUT)) - (port PLLWEO - (direction OUTPUT)) - (port PLLADRO4 - (direction OUTPUT)) - (port PLLADRO3 - (direction OUTPUT)) - (port PLLADRO2 - (direction OUTPUT)) - (port PLLADRO1 - (direction OUTPUT)) - (port PLLADRO0 - (direction OUTPUT)) - (port PLLDATO7 - (direction OUTPUT)) - (port PLLDATO6 - (direction OUTPUT)) - (port PLLDATO5 - (direction OUTPUT)) - (port PLLDATO4 - (direction OUTPUT)) - (port PLLDATO3 - (direction OUTPUT)) - (port PLLDATO2 - (direction OUTPUT)) - (port PLLDATO1 - (direction OUTPUT)) - (port PLLDATO0 - (direction OUTPUT)) - (port I2C1SCLO - (direction OUTPUT)) - (port I2C1SCLOEN - (direction OUTPUT)) - (port I2C1SDAO - (direction OUTPUT)) - (port I2C1SDAOEN - (direction OUTPUT)) - (port I2C2SCLO - (direction OUTPUT)) - (port I2C2SCLOEN - (direction OUTPUT)) - (port I2C2SDAO - (direction OUTPUT)) - (port I2C2SDAOEN - (direction OUTPUT)) - (port I2C1IRQO - (direction OUTPUT)) - (port I2C2IRQO - (direction OUTPUT)) - (port SPISCKO - (direction OUTPUT)) - (port SPISCKEN - (direction OUTPUT)) - (port SPIMISOO - (direction OUTPUT)) - (port SPIMISOEN - (direction OUTPUT)) - (port SPIMOSIO - (direction OUTPUT)) - (port SPIMOSIEN - (direction OUTPUT)) - (port SPIMCSN7 - (direction OUTPUT)) - (port SPIMCSN6 - (direction OUTPUT)) - (port SPIMCSN5 - (direction OUTPUT)) - (port SPIMCSN4 - (direction OUTPUT)) - (port SPIMCSN3 - (direction OUTPUT)) - (port SPIMCSN2 - (direction OUTPUT)) - (port SPIMCSN1 - (direction OUTPUT)) - (port SPIMCSN0 - (direction OUTPUT)) - (port SPICSNEN - (direction OUTPUT)) - (port SPIIRQO - (direction OUTPUT)) - (port TCINT - (direction OUTPUT)) - (port TCOC - (direction OUTPUT)) - (port WBCUFMIRQ - (direction OUTPUT)) - (port CFGWAKE - (direction OUTPUT)) - (port CFGSTDBY - (direction OUTPUT))))) - (cell REFB - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port wb_clk_i - (direction INPUT)) - (port wb_rst_i - (direction INPUT)) - (port wb_cyc_i - (direction INPUT)) - (port wb_stb_i - (direction INPUT)) - (port wb_we_i - (direction INPUT)) - (port (array (rename wb_adr_i "wb_adr_i(7:0)") 8) - (direction INPUT)) - (port (array (rename wb_dat_i "wb_dat_i(7:0)") 8) - (direction INPUT)) - (port (array (rename wb_dat_o "wb_dat_o(7:0)") 8) - (direction OUTPUT)) - (port wb_ack_o - (direction OUTPUT)) - (port wbc_ufm_irq - (direction OUTPUT))) - (property NGD_DRC_MASK (integer 1)) - (contents - (instance scuba_vhi_inst - (viewRef view1 - (cellRef VHI))) - (instance scuba_vlo_inst - (viewRef view1 - (cellRef VLO))) - (instance EFBInst_0 - (viewRef view1 - (cellRef EFB)) - (property UFM_INIT_FILE_FORMAT - (string "HEX")) - (property UFM_INIT_FILE_NAME - (string "../RAM2E-LCMXO2.mem")) - (property UFM_INIT_ALL_ZEROS - (string "DISABLED")) - (property UFM_INIT_START_PAGE - (string "190")) - (property UFM_INIT_PAGES - (string "321")) - (property DEV_DENSITY - (string "1200L")) - (property EFB_UFM - (string "ENABLED")) - (property TC_ICAPTURE - (string "DISABLED")) - (property TC_OVERFLOW - (string "DISABLED")) - (property TC_ICR_INT - (string "OFF")) - (property TC_OCR_INT - (string "OFF")) - (property TC_OV_INT - (string "OFF")) - (property TC_TOP_SEL - (string "OFF")) - (property TC_RESETN - (string "ENABLED")) - (property TC_OC_MODE - (string "TOGGLE")) - (property TC_OCR_SET - (string "32767")) - (property TC_TOP_SET - (string "65535")) - (property GSR - (string "ENABLED")) - (property TC_CCLK_SEL - (string "1")) - (property TC_MODE - (string "CTCM")) - (property TC_SCLK_SEL - (string "PCLOCK")) - (property EFB_TC_PORTMODE - (string "WB")) - (property EFB_TC - (string "DISABLED")) - (property SPI_WAKEUP - (string "DISABLED")) - (property SPI_INTR_RXOVR - (string "DISABLED")) - (property SPI_INTR_TXOVR - (string "DISABLED")) - (property SPI_INTR_RXRDY - (string "DISABLED")) - (property SPI_INTR_TXRDY - (string "DISABLED")) - (property SPI_SLAVE_HANDSHAKE - (string "DISABLED")) - (property SPI_PHASE_ADJ - (string "DISABLED")) - (property SPI_CLK_INV - (string "DISABLED")) - (property SPI_LSB_FIRST - (string "DISABLED")) - (property SPI_CLK_DIVIDER - (string "1")) - (property SPI_MODE - (string "MASTER")) - (property EFB_SPI - (string "DISABLED")) - (property I2C2_WAKEUP - (string "DISABLED")) - (property I2C2_GEN_CALL - (string "DISABLED")) - (property I2C2_CLK_DIVIDER - (string "1")) - (property I2C2_BUS_PERF - (string "100kHz")) - (property I2C2_SLAVE_ADDR - (string "0b1000010")) - (property I2C2_ADDRESSING - (string "7BIT")) - (property EFB_I2C2 - (string "DISABLED")) - (property I2C1_WAKEUP - (string "DISABLED")) - (property I2C1_GEN_CALL - (string "DISABLED")) - (property I2C1_CLK_DIVIDER - (string "1")) - (property I2C1_BUS_PERF - (string "100kHz")) - (property I2C1_SLAVE_ADDR - (string "0b1000001")) - (property I2C1_ADDRESSING - (string "7BIT")) - (property EFB_I2C1 - (string "DISABLED")) - (property EFB_WB_CLK_FREQ - (string "14.4"))) - (net scuba_vhi - (joined - (portRef Z (instanceRef scuba_vhi_inst)) - (portRef UFMSN (instanceRef EFBInst_0)))) - (net scuba_vlo - (joined - (portRef Z (instanceRef scuba_vlo_inst)) - (portRef PLL1DATI7 (instanceRef EFBInst_0)) - (portRef PLL1DATI6 (instanceRef EFBInst_0)) - (portRef PLL1DATI5 (instanceRef EFBInst_0)) - (portRef PLL1DATI4 (instanceRef EFBInst_0)) - (portRef PLL1DATI3 (instanceRef EFBInst_0)) - (portRef PLL1DATI2 (instanceRef EFBInst_0)) - (portRef PLL1DATI1 (instanceRef EFBInst_0)) - (portRef PLL1DATI0 (instanceRef EFBInst_0)) - (portRef PLL1ACKI (instanceRef EFBInst_0)) - (portRef PLL0DATI7 (instanceRef EFBInst_0)) - (portRef PLL0DATI6 (instanceRef EFBInst_0)) - (portRef PLL0DATI5 (instanceRef EFBInst_0)) - (portRef PLL0DATI4 (instanceRef EFBInst_0)) - (portRef PLL0DATI3 (instanceRef EFBInst_0)) - (portRef PLL0DATI2 (instanceRef EFBInst_0)) - (portRef PLL0DATI1 (instanceRef EFBInst_0)) - (portRef PLL0DATI0 (instanceRef EFBInst_0)) - (portRef PLL0ACKI (instanceRef EFBInst_0)) - (portRef TCIC (instanceRef EFBInst_0)) - (portRef TCRSTN (instanceRef EFBInst_0)) - (portRef TCCLKI (instanceRef EFBInst_0)) - (portRef SPISCSN (instanceRef EFBInst_0)) - (portRef SPIMOSII (instanceRef EFBInst_0)) - (portRef SPIMISOI (instanceRef EFBInst_0)) - (portRef SPISCKI (instanceRef EFBInst_0)) - (portRef I2C2SDAI (instanceRef EFBInst_0)) - (portRef I2C2SCLI (instanceRef EFBInst_0)) - (portRef I2C1SDAI (instanceRef EFBInst_0)) - (portRef I2C1SCLI (instanceRef EFBInst_0)))) - (net wbc_ufm_irq - (joined - (portRef wbc_ufm_irq) - (portRef WBCUFMIRQ (instanceRef EFBInst_0)))) - (net wb_ack_o - (joined - (portRef wb_ack_o) - (portRef WBACKO (instanceRef EFBInst_0)))) - (net wb_dat_o7 - (joined - (portRef (member wb_dat_o 0)) - (portRef WBDATO7 (instanceRef EFBInst_0)))) - (net wb_dat_o6 - (joined - (portRef (member wb_dat_o 1)) - (portRef WBDATO6 (instanceRef EFBInst_0)))) - (net wb_dat_o5 - (joined - (portRef (member wb_dat_o 2)) - (portRef WBDATO5 (instanceRef EFBInst_0)))) - (net wb_dat_o4 - (joined - (portRef (member wb_dat_o 3)) - (portRef WBDATO4 (instanceRef EFBInst_0)))) - (net wb_dat_o3 - (joined - (portRef (member wb_dat_o 4)) - (portRef WBDATO3 (instanceRef EFBInst_0)))) - (net wb_dat_o2 - (joined - (portRef (member wb_dat_o 5)) - (portRef WBDATO2 (instanceRef EFBInst_0)))) - (net wb_dat_o1 - (joined - (portRef (member wb_dat_o 6)) - (portRef WBDATO1 (instanceRef EFBInst_0)))) - (net wb_dat_o0 - (joined - (portRef (member wb_dat_o 7)) - (portRef WBDATO0 (instanceRef EFBInst_0)))) - (net wb_dat_i7 - (joined - (portRef (member wb_dat_i 0)) - (portRef WBDATI7 (instanceRef EFBInst_0)))) - (net wb_dat_i6 - (joined - (portRef (member wb_dat_i 1)) - (portRef WBDATI6 (instanceRef EFBInst_0)))) - (net wb_dat_i5 - (joined - (portRef (member wb_dat_i 2)) - (portRef WBDATI5 (instanceRef EFBInst_0)))) - (net wb_dat_i4 - (joined - (portRef (member wb_dat_i 3)) - (portRef WBDATI4 (instanceRef EFBInst_0)))) - (net wb_dat_i3 - (joined - (portRef (member wb_dat_i 4)) - (portRef WBDATI3 (instanceRef EFBInst_0)))) - (net wb_dat_i2 - (joined - (portRef (member wb_dat_i 5)) - (portRef WBDATI2 (instanceRef EFBInst_0)))) - (net wb_dat_i1 - (joined - (portRef (member wb_dat_i 6)) - (portRef WBDATI1 (instanceRef EFBInst_0)))) - (net wb_dat_i0 - (joined - (portRef (member wb_dat_i 7)) - (portRef WBDATI0 (instanceRef EFBInst_0)))) - (net wb_adr_i7 - (joined - (portRef (member wb_adr_i 0)) - (portRef WBADRI7 (instanceRef EFBInst_0)))) - (net wb_adr_i6 - (joined - (portRef (member wb_adr_i 1)) - (portRef WBADRI6 (instanceRef EFBInst_0)))) - (net wb_adr_i5 - (joined - (portRef (member wb_adr_i 2)) - (portRef WBADRI5 (instanceRef EFBInst_0)))) - (net wb_adr_i4 - (joined - (portRef (member wb_adr_i 3)) - (portRef WBADRI4 (instanceRef EFBInst_0)))) - (net wb_adr_i3 - (joined - (portRef (member wb_adr_i 4)) - (portRef WBADRI3 (instanceRef EFBInst_0)))) - (net wb_adr_i2 - (joined - (portRef (member wb_adr_i 5)) - (portRef WBADRI2 (instanceRef EFBInst_0)))) - (net wb_adr_i1 - (joined - (portRef (member wb_adr_i 6)) - (portRef WBADRI1 (instanceRef EFBInst_0)))) - (net wb_adr_i0 - (joined - (portRef (member wb_adr_i 7)) - (portRef WBADRI0 (instanceRef EFBInst_0)))) - (net wb_we_i - (joined - (portRef wb_we_i) - (portRef WBWEI (instanceRef EFBInst_0)))) - (net wb_stb_i - (joined - (portRef wb_stb_i) - (portRef WBSTBI (instanceRef EFBInst_0)))) - (net wb_cyc_i - (joined - (portRef wb_cyc_i) - (portRef WBCYCI (instanceRef EFBInst_0)))) - (net wb_rst_i - (joined - (portRef wb_rst_i) - (portRef WBRSTI (instanceRef EFBInst_0)))) - (net wb_clk_i - (joined - (portRef wb_clk_i) - (portRef WBCLKI (instanceRef EFBInst_0)))))))) - (design REFB - (cellRef REFB - (libraryRef ORCLIB))) -) diff --git a/CPLD/LCMXO2-1200HC/REFB.lpc b/CPLD/LCMXO2-1200HC/REFB.lpc deleted file mode 100644 index a1d3684..0000000 --- a/CPLD/LCMXO2-1200HC/REFB.lpc +++ /dev/null @@ -1,141 +0,0 @@ -[Device] -Family=machxo2 -PartType=LCMXO2-1200HC -PartName=LCMXO2-1200HC-4TG100C -SpeedGrade=4 -Package=TQFP100 -OperatingCondition=COM -Status=S - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=EFB -CoreRevision=1.2 -ModuleName=REFB -SourceFormat=Verilog HDL -ParameterFileVersion=1.0 -Date=09/20/2023 -Time=04:45:58 - -[Parameters] -Verilog=1 -VHDL=0 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -freq= -i2c1=0 -i2c1config=0 -i2c1_addr=7-Bit Addressing -i2c1_ce=0 -i2c1_freq=100 -i2c1_sa=10000 -i2c1_we=0 -i2c2=0 -i2c2_addr=7-Bit Addressing -i2c2_ce=0 -i2c2_freq=100 -i2c2_sa=10000 -i2c2_we=0 -ufm_addr=7-Bit Addressing -ufm_sa=10000 -pll=0 -pll_cnt=1 -spi=0 -spi_clkinv=0 -spi_cs=1 -spi_en=0 -spi_freq=1 -spi_lsb=0 -spi_mode=Slave -spi_ib=0 -spi_ph=0 -spi_hs=0 -spi_rxo=0 -spi_rxr=0 -spi_txo=0 -spi_txr=0 -spi_we=0 -static_tc=Static -tc=0 -tc_clkinv=Positive -tc_ctr=1 -tc_div=1 -tc_ipcap=0 -tc_mode=CTCM -tc_ocr=32767 -tc_oflow=1 -tc_o=TOGGLE -tc_opcomp=0 -tc_osc=0 -tc_sa_oflow=0 -tc_top=65535 -ufm=1 -ufm0=0 -ufm1=0 -ufm2=0 -ufm3=0 -ufm_cfg0=0 -ufm_cfg1=0 -wb_clk_freq=14.4 -ufm_usage=SHARED_EBR_TAG -ufm_ebr=190 -ufm_remain= -mem_size=321 -ufm_start= -ufm_init=mem -memfile=../RAM2E-LCMXO2.mem -ufm_dt=hex -ufm0_ebr= -mem_size0=1 -ufm0_init=0 -memfile0= -ufm0_dt=hex -ufm1_ebr= -mem_size1=1 -ufm1_init=0 -memfile1= -ufm1_dt=hex -ufm2_ebr= -mem_size2=1 -ufm2_init=0 -memfile2= -ufm2_dt=hex -ufm3_ebr= -mem_size3=1 -ufm3_init=0 -memfile3= -ufm3_dt=hex -ufm_cfg0_ebr= -mem_size_cfg0=1 -ufm_cfg0_init=0 -memfile_cfg0= -ufm_cfg0_dt=hex -ufm_cfg1_ebr= -mem_size_cfg1=1 -ufm_cfg1_init=0 -memfile_cfg1= -ufm_cfg1_dt=hex -wb=1 -boot_option=Internal -efb_ufm=0 -boot_option_internal=Single Boot -internal_ufm0=0 -internal_ufm1=0 -efb_ufm_boot= -tamperdr=0 -t_pwd=0 -t_lockflash=0 -t_manmode=0 -t_jtagport=0 -t_sspiport=0 -t_sic2port=0 -t_wbport=0 -t_portlock=0 - -[Command] -cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 diff --git a/CPLD/LCMXO2-1200HC/REFB.naf b/CPLD/LCMXO2-1200HC/REFB.naf deleted file mode 100644 index 5c239f5..0000000 --- a/CPLD/LCMXO2-1200HC/REFB.naf +++ /dev/null @@ -1,31 +0,0 @@ -wb_clk_i i -wb_rst_i i -wb_cyc_i i -wb_stb_i i -wb_we_i i -wb_adr_i[7] i -wb_adr_i[6] i -wb_adr_i[5] i -wb_adr_i[4] i -wb_adr_i[3] i -wb_adr_i[2] i -wb_adr_i[1] i -wb_adr_i[0] i -wb_dat_i[7] i -wb_dat_i[6] i -wb_dat_i[5] i -wb_dat_i[4] i -wb_dat_i[3] i -wb_dat_i[2] i -wb_dat_i[1] i -wb_dat_i[0] i -wb_dat_o[7] o -wb_dat_o[6] o -wb_dat_o[5] o -wb_dat_o[4] o -wb_dat_o[3] o -wb_dat_o[2] o -wb_dat_o[1] o -wb_dat_o[0] o -wb_ack_o o -wbc_ufm_irq o diff --git a/CPLD/LCMXO2-1200HC/REFB.sort b/CPLD/LCMXO2-1200HC/REFB.sort deleted file mode 100644 index 96fe0d5..0000000 --- a/CPLD/LCMXO2-1200HC/REFB.sort +++ /dev/null @@ -1 +0,0 @@ -REFB.v diff --git a/CPLD/LCMXO2-1200HC/REFB.srp b/CPLD/LCMXO2-1200HC/REFB.srp deleted file mode 100644 index b2c0184..0000000 --- a/CPLD/LCMXO2-1200HC/REFB.srp +++ /dev/null @@ -1,26 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.12.1.454 -Wed Sep 20 04:45:58 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 - Circuit name : REFB - Module type : efb - Module Version : 1.2 - Ports : - Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] - Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq - I/O buffer : not inserted - EDIF output : REFB.edn - Verilog output : REFB.v - Verilog template : REFB_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : REFB.srp - Element Usage : - EFB : 1 - Estimated Resource Usage: diff --git a/CPLD/LCMXO2-1200HC/REFB.sym b/CPLD/LCMXO2-1200HC/REFB.sym deleted file mode 100644 index 6588d30..0000000 Binary files a/CPLD/LCMXO2-1200HC/REFB.sym and /dev/null differ diff --git a/CPLD/LCMXO2-1200HC/REFB_generate.log b/CPLD/LCMXO2-1200HC/REFB_generate.log deleted file mode 100644 index dfa91b2..0000000 --- a/CPLD/LCMXO2-1200HC/REFB_generate.log +++ /dev/null @@ -1,44 +0,0 @@ -Starting process: Module - -Starting process: - -SCUBA, Version Diamond (64-bit) 3.12.1.454 -Wed Sep 20 04:45:58 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 - Circuit name : REFB - Module type : efb - Module Version : 1.2 - Ports : - Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] - Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq - I/O buffer : not inserted - EDIF output : REFB.edn - Verilog output : REFB.v - Verilog template : REFB_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : REFB.srp - Estimated Resource Usage: - -END SCUBA Module Synthesis - -File: REFB.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/CPLD/LCMXO2-1200HC/REFB_tmpl.v b/CPLD/LCMXO2-1200HC/REFB_tmpl.v deleted file mode 100644 index 41a1e6a..0000000 --- a/CPLD/LCMXO2-1200HC/REFB_tmpl.v +++ /dev/null @@ -1,8 +0,0 @@ -/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */ -/* Module Version: 1.2 */ -/* Wed Sep 20 04:45:58 2023 */ - -/* parameterized module instance */ -REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), - .wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ), - .wbc_ufm_irq( )); diff --git a/CPLD/LCMXO2-1200HC/_math_real.vhd b/CPLD/LCMXO2-1200HC/_math_real.vhd deleted file mode 100644 index e1215d8..0000000 --- a/CPLD/LCMXO2-1200HC/_math_real.vhd +++ /dev/null @@ -1,2574 +0,0 @@ - - ------------------------------------------------------------------------- --- --- Copyright 1996 by IEEE. All rights reserved. --- --- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard --- VHDL Mathematical Packages. This source file may not be copied, sold, or --- included with software that is sold without written permission from the IEEE --- Standards Department. This source file may be used to implement this standard --- and may be distributed in compiled form in any manner so long as the --- compiled form does not allow direct decompilation of the original source file. --- This source file may be copied for individual use between licensed users. --- This source file is provided on an AS IS basis. The IEEE disclaims ANY --- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY --- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source --- file shall indemnify and hold IEEE harmless from any damages or liability --- arising out of the use thereof. --- --- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, --- MATH_REAL) --- --- Library: This package shall be compiled into a library --- symbolically named IEEE. --- --- Developers: IEEE DASC VHDL Mathematical Packages Working Group --- --- Purpose: This package defines a standard for designers to use in --- describing VHDL models that make use of common REAL constants --- and common REAL elementary mathematical functions. --- --- Limitation: The values generated by the functions in this package may --- vary from platform to platform, and the precision of results --- is only guaranteed to be the minimum required by IEEE Std 1076- --- 1993. --- --- Notes: --- No declarations or definitions shall be included in, or --- excluded from, this package. --- The "package declaration" defines the types, subtypes, and --- declarations of MATH_REAL. --- The standard mathematical definition and conventional meaning --- of the mathematical functions that are part of this standard --- represent the formal semantics of the implementation of the --- MATH_REAL package declaration. The purpose of the MATH_REAL --- package body is to provide a guideline for implementations to --- verify their implementation of MATH_REAL. Tool developers may --- choose to implement the package body in the most efficient --- manner available to them. --- --- ----------------------------------------------------------------------------- --- Version : 1.5 --- Date : 24 July 1996 --- ----------------------------------------------------------------------------- - -package MATH_REAL is - constant CopyRightNotice: STRING - := "Copyright 1996 IEEE. All rights reserved."; - - -- - -- Constant Definitions - -- - constant MATH_E : REAL := 2.71828_18284_59045_23536; - -- Value of e - constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; - -- Value of 1/e - constant MATH_PI : REAL := 3.14159_26535_89793_23846; - -- Value of pi - constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; - -- Value of 2*pi - constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; - -- Value of 1/pi - constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; - -- Value of pi/2 - constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; - -- Value of pi/3 - constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; - -- Value of pi/4 - constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; - -- Value 3*pi/2 - constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; - -- Natural log of 2 - constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; - -- Natural log of 10 - constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; - -- Log base 2 of e - constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; - -- Log base 10 of e - constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; - -- square root of 2 - constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; - -- square root of 1/2 - constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; - -- square root of pi - constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; - -- Conversion factor from degree to radian - constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; - -- Conversion factor from radian to degree - - -- - -- Function Declarations - -- - function SIGN (X: in REAL ) return REAL; - -- Purpose: - -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 - -- Special values: - -- None - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(SIGN(X)) <= 1.0 - -- Notes: - -- None - - function CEIL (X : in REAL ) return REAL; - -- Purpose: - -- Returns smallest INTEGER value (as REAL) not less than X - -- Special values: - -- None - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- CEIL(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function FLOOR (X : in REAL ) return REAL; - -- Purpose: - -- Returns largest INTEGER value (as REAL) not greater than X - -- Special values: - -- FLOOR(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- FLOOR(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function ROUND (X : in REAL ) return REAL; - -- Purpose: - -- Rounds X to the nearest integer value (as real). If X is - -- halfway between two integers, rounding is away from 0.0 - -- Special values: - -- ROUND(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ROUND(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function TRUNC (X : in REAL ) return REAL; - -- Purpose: - -- Truncates X towards 0.0 and returns truncated value - -- Special values: - -- TRUNC(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- TRUNC(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function "MOD" (X, Y: in REAL ) return REAL; - -- Purpose: - -- Returns floating point modulus of X/Y, with the same sign as - -- Y, and absolute value less than the absolute value of Y, and - -- for some INTEGER value N the result satisfies the relation - -- X = Y*N + MOD(X,Y) - -- Special values: - -- None - -- Domain: - -- X in REAL; Y in REAL and Y /= 0.0 - -- Error conditions: - -- Error if Y = 0.0 - -- Range: - -- ABS(MOD(X,Y)) < ABS(Y) - -- Notes: - -- None - - function REALMAX (X, Y : in REAL ) return REAL; - -- Purpose: - -- Returns the algebraically larger of X and Y - -- Special values: - -- REALMAX(X,Y) = X when X = Y - -- Domain: - -- X in REAL; Y in REAL - -- Error conditions: - -- None - -- Range: - -- REALMAX(X,Y) is mathematically unbounded - -- Notes: - -- None - - function REALMIN (X, Y : in REAL ) return REAL; - -- Purpose: - -- Returns the algebraically smaller of X and Y - -- Special values: - -- REALMIN(X,Y) = X when X = Y - -- Domain: - -- X in REAL; Y in REAL - -- Error conditions: - -- None - -- Range: - -- REALMIN(X,Y) is mathematically unbounded - -- Notes: - -- None - - procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); - -- Purpose: - -- Returns, in X, a pseudo-random number with uniform - -- distribution in the open interval (0.0, 1.0). - -- Special values: - -- None - -- Domain: - -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 - -- Error conditions: - -- Error if SEED1 or SEED2 outside of valid domain - -- Range: - -- 0.0 < X < 1.0 - -- Notes: - -- a) The semantics for this function are described by the - -- algorithm published by Pierre L'Ecuyer in "Communications - -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. - -- The algorithm is based on the combination of two - -- multiplicative linear congruential generators for 32-bit - -- platforms. - -- - -- b) Before the first call to UNIFORM, the seed values - -- (SEED1, SEED2) have to be initialized to values in the range - -- [1, 2147483562] and [1, 2147483398] respectively. The - -- seed values are modified after each call to UNIFORM. - -- - -- c) This random number generator is portable for 32-bit - -- computers, and it has a period of ~2.30584*(10**18) for each - -- set of seed values. - -- - -- d) For information on spectral tests for the algorithm, refer - -- to the L'Ecuyer article. - - function SQRT (X : in REAL ) return REAL; - -- Purpose: - -- Returns square root of X - -- Special values: - -- SQRT(0.0) = 0.0 - -- SQRT(1.0) = 1.0 - -- Domain: - -- X >= 0.0 - -- Error conditions: - -- Error if X < 0.0 - -- Range: - -- SQRT(X) >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range of SQRT is - -- approximately given by: - -- SQRT(X) <= SQRT(REAL'HIGH) - - function CBRT (X : in REAL ) return REAL; - -- Purpose: - -- Returns cube root of X - -- Special values: - -- CBRT(0.0) = 0.0 - -- CBRT(1.0) = 1.0 - -- CBRT(-1.0) = -1.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- CBRT(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of CBRT is approximately given by: - -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) - - function "**" (X : in INTEGER; Y : in REAL) return REAL; - -- Purpose: - -- Returns Y power of X ==> X**Y - -- Special values: - -- X**0.0 = 1.0; X /= 0 - -- 0**Y = 0.0; Y > 0.0 - -- X**1.0 = REAL(X); X >= 0 - -- 1**Y = 1.0 - -- Domain: - -- X > 0 - -- X = 0 for Y > 0.0 - -- X < 0 for Y = 0.0 - -- Error conditions: - -- Error if X < 0 and Y /= 0.0 - -- Error if X = 0 and Y <= 0.0 - -- Range: - -- X**Y >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range for "**" is - -- approximately given by: - -- X**Y <= REAL'HIGH - - function "**" (X : in REAL; Y : in REAL) return REAL; - -- Purpose: - -- Returns Y power of X ==> X**Y - -- Special values: - -- X**0.0 = 1.0; X /= 0.0 - -- 0.0**Y = 0.0; Y > 0.0 - -- X**1.0 = X; X >= 0.0 - -- 1.0**Y = 1.0 - -- Domain: - -- X > 0.0 - -- X = 0.0 for Y > 0.0 - -- X < 0.0 for Y = 0.0 - -- Error conditions: - -- Error if X < 0.0 and Y /= 0.0 - -- Error if X = 0.0 and Y <= 0.0 - -- Range: - -- X**Y >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range for "**" is - -- approximately given by: - -- X**Y <= REAL'HIGH - - function EXP (X : in REAL ) return REAL; - -- Purpose: - -- Returns e**X; where e = MATH_E - -- Special values: - -- EXP(0.0) = 1.0 - -- EXP(1.0) = MATH_E - -- EXP(-1.0) = MATH_1_OVER_E - -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) - -- Domain: - -- X in REAL such that EXP(X) <= REAL'HIGH - -- Error conditions: - -- Error if X > LOG(REAL'HIGH) - -- Range: - -- EXP(X) >= 0.0 - -- Notes: - -- a) The usable domain of EXP is approximately given by: - -- X <= LOG(REAL'HIGH) - - function LOG (X : in REAL ) return REAL; - -- Purpose: - -- Returns natural logarithm of X - -- Special values: - -- LOG(1.0) = 0.0 - -- LOG(MATH_E) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG is approximately given by: - -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) - - function LOG2 (X : in REAL ) return REAL; - -- Purpose: - -- Returns logarithm base 2 of X - -- Special values: - -- LOG2(1.0) = 0.0 - -- LOG2(2.0) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG2(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG2 is approximately given by: - -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) - - function LOG10 (X : in REAL ) return REAL; - -- Purpose: - -- Returns logarithm base 10 of X - -- Special values: - -- LOG10(1.0) = 0.0 - -- LOG10(10.0) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG10(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG10 is approximately given by: - -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) - - function LOG (X: in REAL; BASE: in REAL) return REAL; - -- Purpose: - -- Returns logarithm base BASE of X - -- Special values: - -- LOG(1.0, BASE) = 0.0 - -- LOG(BASE, BASE) = 1.0 - -- Domain: - -- X > 0.0 - -- BASE > 0.0 - -- BASE /= 1.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Error if BASE <= 0.0 - -- Error if BASE = 1.0 - -- Range: - -- LOG(X, BASE) is mathematically unbounded - -- Notes: - -- a) When BASE > 1.0, the reachable range of LOG is - -- approximately given by: - -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) - -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is - -- approximately given by: - -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) - - function SIN (X : in REAL ) return REAL; - -- Purpose: - -- Returns sine of X; X in radians - -- Special values: - -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER - -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(SIN(X)) <= 1.0 - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function COS ( X : in REAL ) return REAL; - -- Purpose: - -- Returns cosine of X; X in radians - -- Special values: - -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER - -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(COS(X)) <= 1.0 - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function TAN (X : in REAL ) return REAL; - -- Purpose: - -- Returns tangent of X; X in radians - -- Special values: - -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER - -- Domain: - -- X in REAL and - -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER - -- Error conditions: - -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an - -- INTEGER - -- Range: - -- TAN(X) is mathematically unbounded - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function ARCSIN (X : in REAL ) return REAL; - -- Purpose: - -- Returns inverse sine of X - -- Special values: - -- ARCSIN(0.0) = 0.0 - -- ARCSIN(1.0) = MATH_PI_OVER_2 - -- ARCSIN(-1.0) = -MATH_PI_OVER_2 - -- Domain: - -- ABS(X) <= 1.0 - -- Error conditions: - -- Error if ABS(X) > 1.0 - -- Range: - -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 - -- Notes: - -- None - - function ARCCOS (X : in REAL ) return REAL; - -- Purpose: - -- Returns inverse cosine of X - -- Special values: - -- ARCCOS(1.0) = 0.0 - -- ARCCOS(0.0) = MATH_PI_OVER_2 - -- ARCCOS(-1.0) = MATH_PI - -- Domain: - -- ABS(X) <= 1.0 - -- Error conditions: - -- Error if ABS(X) > 1.0 - -- Range: - -- 0.0 <= ARCCOS(X) <= MATH_PI - -- Notes: - -- None - - function ARCTAN (Y : in REAL) return REAL; - -- Purpose: - -- Returns the value of the angle in radians of the point - -- (1.0, Y), which is in rectangular coordinates - -- Special values: - -- ARCTAN(0.0) = 0.0 - -- Domain: - -- Y in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 - -- Notes: - -- None - - function ARCTAN (Y : in REAL; X : in REAL) return REAL; - -- Purpose: - -- Returns the principal value of the angle in radians of - -- the point (X, Y), which is in rectangular coordinates - -- Special values: - -- ARCTAN(0.0, X) = 0.0 if X > 0.0 - -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 - -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 - -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 - -- Domain: - -- Y in REAL - -- X in REAL, X /= 0.0 when Y = 0.0 - -- Error conditions: - -- Error if X = 0.0 and Y = 0.0 - -- Range: - -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI - -- Notes: - -- None - - function SINH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic sine of X - -- Special values: - -- SINH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- SINH(X) is mathematically unbounded - -- Notes: - -- a) The usable domain of SINH is approximately given by: - -- ABS(X) <= LOG(REAL'HIGH) - - - function COSH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic cosine of X - -- Special values: - -- COSH(0.0) = 1.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- COSH(X) >= 1.0 - -- Notes: - -- a) The usable domain of COSH is approximately given by: - -- ABS(X) <= LOG(REAL'HIGH) - - function TANH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic tangent of X - -- Special values: - -- TANH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(TANH(X)) <= 1.0 - -- Notes: - -- None - - function ARCSINH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic sine of X - -- Special values: - -- ARCSINH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ARCSINH(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of ARCSINH is approximately given by: - -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) - - function ARCCOSH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic cosine of X - -- Special values: - -- ARCCOSH(1.0) = 0.0 - -- Domain: - -- X >= 1.0 - -- Error conditions: - -- Error if X < 1.0 - -- Range: - -- ARCCOSH(X) >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range of ARCCOSH is - -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) - - function ARCTANH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic tangent of X - -- Special values: - -- ARCTANH(0.0) = 0.0 - -- Domain: - -- ABS(X) < 1.0 - -- Error conditions: - -- Error if ABS(X) >= 1.0 - -- Range: - -- ARCTANH(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of ARCTANH is approximately given by: - -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) - -end MATH_REAL; - - - ------------------------------------------------------------------------- --- --- Copyright 1996 by IEEE. All rights reserved. - --- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard --- VHDL Mathematical Packages. This source file may not be copied, sold, or --- included with software that is sold without written permission from the IEEE --- Standards Department. This source file may be used to implement this standard --- and may be distributed in compiled form in any manner so long as the --- compiled form does not allow direct decompilation of the original source file. --- This source file may be copied for individual use between licensed users. --- This source file is provided on an AS IS basis. The IEEE disclaims ANY --- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY --- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source --- file shall indemnify and hold IEEE harmless from any damages or liability --- arising out of the use thereof. - --- --- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, --- MATH_REAL) --- --- Library: This package shall be compiled into a library --- symbolically named IEEE. --- --- Developers: IEEE DASC VHDL Mathematical Packages Working Group --- --- Purpose: This package body is a nonnormative implementation of the --- functionality defined in the MATH_REAL package declaration. --- --- Limitation: The values generated by the functions in this package may --- vary from platform to platform, and the precision of results --- is only guaranteed to be the minimum required by IEEE Std 1076 --- -1993. --- --- Notes: --- The "package declaration" defines the types, subtypes, and --- declarations of MATH_REAL. --- The standard mathematical definition and conventional meaning --- of the mathematical functions that are part of this standard --- represent the formal semantics of the implementation of the --- MATH_REAL package declaration. The purpose of the MATH_REAL --- package body is to clarify such semantics and provide a --- guideline for implementations to verify their implementation --- of MATH_REAL. Tool developers may choose to implement --- the package body in the most efficient manner available to them. --- --- ----------------------------------------------------------------------------- --- Version : 1.5 --- Date : 24 July 1996 --- ----------------------------------------------------------------------------- - -package body MATH_REAL is - - -- - -- Local Constants for Use in the Package Body Only - -- - constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 - constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 - constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi - constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic - constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries - constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria - constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic - - -- - -- Local Type Declarations for Cordic Operations - -- - type REAL_VECTOR is array (NATURAL range <>) of REAL; - type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; - subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); - subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); - subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); - subtype QUADRANT is INTEGER range 0 to 3; - type CORDIC_MODE_TYPE is (ROTATION, VECTORING); - - -- - -- Auxiliary Functions for Cordic Algorithms - -- - function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; - NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is - -- Description: - -- Returns power of two for a vector of values - -- Notes: - -- None - -- - variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); - variable TEMP : REAL := INITIAL_VALUE; - variable FLAG : BOOLEAN := TRUE; - begin - for I in 0 to NUMBER_OF_VALUES loop - V(I) := TEMP; - for P in D'RANGE loop - if I = D(P) then - FLAG := FALSE; - exit; - end if; - end loop; - if FLAG then - TEMP := TEMP/2.0; - end if; - FLAG := TRUE; - end loop; - return V; - end POWER_OF_2_SERIES; - - - constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( - NATURAL_VECTOR'(100, 90),1.0, - MAX_ITER); - - constant EPSILON : REAL_VECTOR_N := ( - 7.8539816339744827e-01, - 4.6364760900080606e-01, - 2.4497866312686413e-01, - 1.2435499454676144e-01, - 6.2418809995957351e-02, - 3.1239833430268277e-02, - 1.5623728620476830e-02, - 7.8123410601011116e-03, - 3.9062301319669717e-03, - 1.9531225164788189e-03, - 9.7656218955931937e-04, - 4.8828121119489829e-04, - 2.4414062014936175e-04, - 1.2207031189367021e-04, - 6.1035156174208768e-05, - 3.0517578115526093e-05, - 1.5258789061315760e-05, - 7.6293945311019699e-06, - 3.8146972656064960e-06, - 1.9073486328101870e-06, - 9.5367431640596080e-07, - 4.7683715820308876e-07, - 2.3841857910155801e-07, - 1.1920928955078067e-07, - 5.9604644775390553e-08, - 2.9802322387695303e-08, - 1.4901161193847654e-08, - 7.4505805969238281e-09 - ); - - function CORDIC ( X0 : in REAL; - Y0 : in REAL; - Z0 : in REAL; - N : in NATURAL; -- Precision factor - CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) - -- or vectoring (Y -> 0) - ) return REAL_ARR_3 is - -- Description: - -- Compute cordic values - -- Notes: - -- None - variable X : REAL := X0; - variable Y : REAL := Y0; - variable Z : REAL := Z0; - variable X_TEMP : REAL; - begin - if CORDIC_MODE = ROTATION then - for K in 0 to N loop - X_TEMP := X; - if ( Z >= 0.0) then - X := X - Y * TWO_AT_MINUS(K); - Y := Y + X_TEMP * TWO_AT_MINUS(K); - Z := Z - EPSILON(K); - else - X := X + Y * TWO_AT_MINUS(K); - Y := Y - X_TEMP * TWO_AT_MINUS(K); - Z := Z + EPSILON(K); - end if; - end loop; - else - for K in 0 to N loop - X_TEMP := X; - if ( Y < 0.0) then - X := X - Y * TWO_AT_MINUS(K); - Y := Y + X_TEMP * TWO_AT_MINUS(K); - Z := Z - EPSILON(K); - else - X := X + Y * TWO_AT_MINUS(K); - Y := Y - X_TEMP * TWO_AT_MINUS(K); - Z := Z + EPSILON(K); - end if; - end loop; - end if; - return REAL_ARR_3'(X, Y, Z); - end CORDIC; - - -- - -- Bodies for Global Mathematical Functions Start Here - -- - function SIGN (X: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- None - begin - if ( X > 0.0 ) then - return 1.0; - elsif ( X < 0.0 ) then - return -1.0; - else - return 0.0; - end if; - end SIGN; - - function CEIL (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) No conversion to an INTEGER type is expected, so truncate - -- cannot overflow for large arguments - -- b) The domain supported by this function is X <= LARGE - -- c) Returns X if ABS(X) >= LARGE - - constant LARGE: REAL := REAL(INTEGER'HIGH); - variable RD: REAL; - - begin - if ABS(X) >= LARGE then - return X; - end if; - - RD := REAL ( INTEGER(X)); - if RD = X then - return X; - end if; - - if X > 0.0 then - if RD >= X then - return RD; - else - return RD + 1.0; - end if; - elsif X = 0.0 then - return 0.0; - else - if RD <= X then - return RD + 1.0; - else - return RD; - end if; - end if; - end CEIL; - - function FLOOR (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) No conversion to an INTEGER type is expected, so truncate - -- cannot overflow for large arguments - -- b) The domain supported by this function is ABS(X) <= LARGE - -- c) Returns X if ABS(X) >= LARGE - - constant LARGE: REAL := REAL(INTEGER'HIGH); - variable RD: REAL; - - begin - if ABS( X ) >= LARGE then - return X; - end if; - - RD := REAL ( INTEGER(X)); - if RD = X then - return X; - end if; - - if X > 0.0 then - if RD <= X then - return RD; - else - return RD - 1.0; - end if; - elsif X = 0.0 then - return 0.0; - else - if RD >= X then - return RD - 1.0; - else - return RD; - end if; - end if; - end FLOOR; - - function ROUND (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 if X = 0.0 - -- b) Returns FLOOR(X + 0.5) if X > 0 - -- c) Returns CEIL(X - 0.5) if X < 0 - - begin - if X > 0.0 then - return FLOOR(X + 0.5); - elsif X < 0.0 then - return CEIL( X - 0.5); - else - return 0.0; - end if; - end ROUND; - - function TRUNC (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 if X = 0.0 - -- b) Returns FLOOR(X) if X > 0 - -- c) Returns CEIL(X) if X < 0 - - begin - if X > 0.0 then - return FLOOR(X); - elsif X < 0.0 then - return CEIL( X); - else - return 0.0; - end if; - end TRUNC; - - - - - function "MOD" (X, Y: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable XNEGATIVE : BOOLEAN := X < 0.0; - variable YNEGATIVE : BOOLEAN := Y < 0.0; - variable VALUE : REAL; - begin - -- Check validity of input arguments - if (Y = 0.0) then - assert FALSE - report "MOD(X, 0.0) is undefined" - severity ERROR; - return 0.0; - end if; - - -- Compute value - if ( XNEGATIVE ) then - if ( YNEGATIVE ) then - VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - end if; - else - if ( YNEGATIVE ) then - VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - end if; - end if; - - return VALUE; - end "MOD"; - - - function REALMAX (X, Y : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) REALMAX(X,Y) = X when X = Y - -- - begin - if X >= Y then - return X; - else - return Y; - end if; - end REALMAX; - - function REALMIN (X, Y : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) REALMIN(X,Y) = X when X = Y - -- - begin - if X <= Y then - return X; - else - return Y; - end if; - end REALMIN; - - - procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) - is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - -- - variable Z, K: INTEGER; - variable TSEED1 : INTEGER := INTEGER'(SEED1); - variable TSEED2 : INTEGER := INTEGER'(SEED2); - begin - -- Check validity of arguments - if SEED1 > 2147483562 then - assert FALSE - report "SEED1 > 2147483562 in UNIFORM" - severity ERROR; - X := 0.0; - return; - end if; - - if SEED2 > 2147483398 then - assert FALSE - report "SEED2 > 2147483398 in UNIFORM" - severity ERROR; - X := 0.0; - return; - end if; - - -- Compute new seed values and pseudo-random number - K := TSEED1/53668; - TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; - - if TSEED1 < 0 then - TSEED1 := TSEED1 + 2147483563; - end if; - - K := TSEED2/52774; - TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; - - if TSEED2 < 0 then - TSEED2 := TSEED2 + 2147483399; - end if; - - Z := TSEED1 - TSEED2; - if Z < 1 then - Z := Z + 2147483562; - end if; - - -- Get output values - SEED1 := POSITIVE'(TSEED1); - SEED2 := POSITIVE'(TSEED2); - X := REAL(Z)*4.656613e-10; - end UNIFORM; - - - - function SQRT (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Uses the Newton-Raphson approximation: - -- F(n+1) = 0.5*[F(n) + x/F(n)] - -- b) Returns 0.0 on error - -- - - constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor - - variable INIVAL: REAL; - variable OLDVAL : REAL ; - variable NEWVAL : REAL ; - variable COUNT : INTEGER := 1; - - begin - -- Check validity of argument - if ( X < 0.0 ) then - assert FALSE - report "X < 0.0 in SQRT(X)" - severity ERROR; - return 0.0; - end if; - - -- Get the square root for special cases - if X = 0.0 then - return 0.0; - else - if ( X = 1.0 ) then - return 1.0; - end if; - end if; - - -- Get the square root for general cases - INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise - OLDVAL := INIVAL; - NEWVAL := (X/OLDVAL + OLDVAL)*0.5; - - -- Check for relative and absolute error and max count - while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR - (ABS(NEWVAL - OLDVAL) > EPS) ) AND - (COUNT < MAX_COUNT) ) loop - OLDVAL := NEWVAL; - NEWVAL := (X/OLDVAL + OLDVAL)*0.5; - COUNT := COUNT + 1; - end loop; - return NEWVAL; - end SQRT; - - function CBRT (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Uses the Newton-Raphson approximation: - -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; - -- - constant EPS : REAL := BASE_EPS*BASE_EPS; - - variable INIVAL: REAL; - variable XLOCAL : REAL := X; - variable NEGATIVE : BOOLEAN := X < 0.0; - variable OLDVAL : REAL ; - variable NEWVAL : REAL ; - variable COUNT : INTEGER := 1; - - begin - - -- Compute root for special cases - if X = 0.0 then - return 0.0; - elsif ( X = 1.0 ) then - return 1.0; - else - if X = -1.0 then - return -1.0; - end if; - end if; - - -- Compute root for general cases - if NEGATIVE then - XLOCAL := -X; - end if; - - INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but - -- imprecise - OLDVAL := INIVAL; - NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; - - -- Check for relative and absolute errors and max count - while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR - (ABS(NEWVAL - OLDVAL) > EPS ) ) AND - ( COUNT < MAX_COUNT ) ) loop - OLDVAL := NEWVAL; - NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; - COUNT := COUNT + 1; - end loop; - - if NEGATIVE then - NEWVAL := -NEWVAL; - end if; - - return NEWVAL; - end CBRT; - - function "**" (X : in INTEGER; Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error condition - - begin - -- Check validity of argument - if ( ( X < 0 ) and ( Y /= 0.0 ) ) then - assert FALSE - report "X < 0 and Y /= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - if ( ( X = 0 ) and ( Y <= 0.0 ) ) then - assert FALSE - report "X = 0 and Y <= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - -- Get value for special cases - if ( X = 0 and Y > 0.0 ) then - return 0.0; - end if; - - if ( X = 1 ) then - return 1.0; - end if; - - if ( Y = 0.0 and X /= 0 ) then - return 1.0; - end if; - - if ( Y = 1.0) then - return (REAL(X)); - end if; - - -- Get value for general case - return EXP (Y * LOG (REAL(X))); - end "**"; - - function "**" (X : in REAL; Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error condition - - begin - -- Check validity of argument - if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then - assert FALSE - report "X < 0.0 and Y /= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then - assert FALSE - report "X = 0.0 and Y <= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - -- Get value for special cases - if ( X = 0.0 and Y > 0.0 ) then - return 0.0; - end if; - - if ( X = 1.0 ) then - return 1.0; - end if; - - if ( Y = 0.0 and X /= 0.0 ) then - return 1.0; - end if; - - if ( Y = 1.0) then - return (X); - end if; - - -- Get value for general case - return EXP (Y * LOG (X)); - end "**"; - - function EXP (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) This function computes the exponential using the following - -- series: - -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 - -- and reduces argument X to take advantage of exp(x+y) = - -- exp(x)*exp(y) - -- - -- b) This implementation limits X to be less than LOG(REAL'HIGH) - -- to avoid overflow. Returns REAL'HIGH when X reaches that - -- limit - -- - constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria - - variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument - variable XLOCAL : REAL := ABS(X); -- Use positive value - variable OLDVAL: REAL ; - variable COUNT: INTEGER ; - variable NEWVAL: REAL ; - variable LAST_TERM: REAL ; - variable FACTOR : REAL := 1.0; - - begin - -- Compute value for special cases - if X = 0.0 then - return 1.0; - end if; - - if XLOCAL = 1.0 then - if RECIPROCAL then - return MATH_1_OVER_E; - else - return MATH_E; - end if; - end if; - - if XLOCAL = 2.0 then - if RECIPROCAL then - return 1.0/MATH_E_P2; - else - return MATH_E_P2; - end if; - end if; - - if XLOCAL = 10.0 then - if RECIPROCAL then - return 1.0/MATH_E_P10; - else - return MATH_E_P10; - end if; - end if; - - if XLOCAL > LOG(REAL'HIGH) then - if RECIPROCAL then - return 0.0; - else - assert FALSE - report "X > LOG(REAL'HIGH) in EXP(X)" - severity NOTE; - return REAL'HIGH; - end if; - end if; - - -- Reduce argument to ABS(X) < 1.0 - while XLOCAL > 10.0 loop - XLOCAL := XLOCAL - 10.0; - FACTOR := FACTOR*MATH_E_P10; - end loop; - - while XLOCAL > 1.0 loop - XLOCAL := XLOCAL - 1.0; - FACTOR := FACTOR*MATH_E; - end loop; - - -- Compute value for case 0 < XLOCAL < 1 - OLDVAL := 1.0; - LAST_TERM := XLOCAL; - NEWVAL:= OLDVAL + LAST_TERM; - COUNT := 2; - - -- Check for relative and absolute errors and max count - while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR - (ABS(NEWVAL - OLDVAL) > EPS) ) AND - (COUNT < MAX_COUNT ) ) loop - OLDVAL := NEWVAL; - LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); - NEWVAL := OLDVAL + LAST_TERM; - COUNT := COUNT + 1; - end loop; - - -- Compute final value using exp(x+y) = exp(x)*exp(y) - NEWVAL := NEWVAL*FACTOR; - - if RECIPROCAL then - NEWVAL := 1.0/NEWVAL; - end if; - - return NEWVAL; - end EXP; - - - -- - -- Auxiliary Functions to Compute LOG - -- - function ILOGB(X: in REAL) return INTEGER IS - -- Description: - -- Returns n such that -1 <= ABS(X)/2^n < 2 - -- Notes: - -- None - - variable N: INTEGER := 0; - variable Y: REAL := ABS(X); - - begin - if(Y = 1.0 or Y = 0.0) then - return 0; - end if; - - if( Y > 1.0) then - while Y >= 2.0 loop - Y := Y/2.0; - N := N+1; - end loop; - return N; - end if; - - -- O < Y < 1 - while Y < 1.0 loop - Y := Y*2.0; - N := N -1; - end loop; - return N; - end ILOGB; - - function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS - -- Description: - -- Returns X*2^n - -- Notes: - -- None - begin - return X*(2.0 ** N); - end LDEXP; - - function LOG (X : in REAL ) return REAL IS - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- - -- Notes: - -- a) Returns REAL'LOW on error - -- - -- Copyright (c) 1992 Regents of the University of California. - -- All rights reserved. - -- - -- Redistribution and use in source and binary forms, with or without - -- modification, are permitted provided that the following conditions - -- are met: - -- 1. Redistributions of source code must retain the above copyright - -- notice, this list of conditions and the following disclaimer. - -- 2. Redistributions in binary form must reproduce the above copyright - -- notice, this list of conditions and the following disclaimer in the - -- documentation and/or other materials provided with the distribution. - -- 3. All advertising materials mentioning features or use of this - -- software must display the following acknowledgement: - -- This product includes software developed by the University of - -- California, Berkeley and its contributors. - -- 4. Neither the name of the University nor the names of its - -- contributors may be used to endorse or promote products derived - -- from this software without specific prior written permission. - -- - -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' - -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR - -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY - -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - -- DAMAGE. - -- - -- NOTE: This VHDL version was generated using the C version of the - -- original function by the IEEE VHDL Mathematical Package - -- Working Group (CS/JT) - - constant N: INTEGER := 128; - - -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. - -- Used for generation of extend precision logarithms. - -- The constant 35184372088832 is 2^45, so the divide is exact. - -- It ensures correct reading of logF_head, even for inaccurate - -- decimal-to-binary conversion routines. (Everybody gets the - -- right answer for INTEGERs less than 2^53.) - -- Values for LOG(F) were generated using error < 10^-57 absolute - -- with the bc -l package. - - type REAL_VECTOR is array (NATURAL range <>) of REAL; - - constant A1:REAL := 0.08333333333333178827; - constant A2:REAL := 0.01250000000377174923; - constant A3:REAL := 0.002232139987919447809; - constant A4:REAL := 0.0004348877777076145742; - - constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( - 0.0, - 0.007782140442060381246, - 0.015504186535963526694, - 0.023167059281547608406, - 0.030771658666765233647, - 0.038318864302141264488, - 0.045809536031242714670, - 0.053244514518837604555, - 0.060624621816486978786, - 0.067950661908525944454, - 0.075223421237524235039, - 0.082443669210988446138, - 0.089612158689760690322, - 0.096729626458454731618, - 0.103796793681567578460, - 0.110814366340264314203, - 0.117783035656430001836, - 0.124703478501032805070, - 0.131576357788617315236, - 0.138402322859292326029, - 0.145182009844575077295, - 0.151916042025732167530, - 0.158605030176659056451, - 0.165249572895390883786, - 0.171850256926518341060, - 0.178407657472689606947, - 0.184922338493834104156, - 0.191394852999565046047, - 0.197825743329758552135, - 0.204215541428766300668, - 0.210564769107350002741, - 0.216873938300523150246, - 0.223143551314024080056, - 0.229374101064877322642, - 0.235566071312860003672, - 0.241719936886966024758, - 0.247836163904594286577, - 0.253915209980732470285, - 0.259957524436686071567, - 0.265963548496984003577, - 0.271933715484010463114, - 0.277868451003087102435, - 0.283768173130738432519, - 0.289633292582948342896, - 0.295464212893421063199, - 0.301261330578199704177, - 0.307025035294827830512, - 0.312755710004239517729, - 0.318453731118097493890, - 0.324119468654316733591, - 0.329753286372579168528, - 0.335355541920762334484, - 0.340926586970454081892, - 0.346466767346100823488, - 0.351976423156884266063, - 0.357455888922231679316, - 0.362905493689140712376, - 0.368325561158599157352, - 0.373716409793814818840, - 0.379078352934811846353, - 0.384411698910298582632, - 0.389716751140440464951, - 0.394993808240542421117, - 0.400243164127459749579, - 0.405465108107819105498, - 0.410659924985338875558, - 0.415827895143593195825, - 0.420969294644237379543, - 0.426084395310681429691, - 0.431173464818130014464, - 0.436236766774527495726, - 0.441274560805140936281, - 0.446287102628048160113, - 0.451274644139630254358, - 0.456237433481874177232, - 0.461175715122408291790, - 0.466089729924533457960, - 0.470979715219073113985, - 0.475845904869856894947, - 0.480688529345570714212, - 0.485507815781602403149, - 0.490303988045525329653, - 0.495077266798034543171, - 0.499827869556611403822, - 0.504556010751912253908, - 0.509261901790523552335, - 0.513945751101346104405, - 0.518607764208354637958, - 0.523248143765158602036, - 0.527867089620485785417, - 0.532464798869114019908, - 0.537041465897345915436, - 0.541597282432121573947, - 0.546132437597407260909, - 0.550647117952394182793, - 0.555141507540611200965, - 0.559615787935399566777, - 0.564070138285387656651, - 0.568504735352689749561, - 0.572919753562018740922, - 0.577315365035246941260, - 0.581691739635061821900, - 0.586049045003164792433, - 0.590387446602107957005, - 0.594707107746216934174, - 0.599008189645246602594, - 0.603290851438941899687, - 0.607555250224322662688, - 0.611801541106615331955, - 0.616029877215623855590, - 0.620240409751204424537, - 0.624433288012369303032, - 0.628608659422752680256, - 0.632766669570628437213, - 0.636907462236194987781, - 0.641031179420679109171, - 0.645137961373620782978, - 0.649227946625615004450, - 0.653301272011958644725, - 0.657358072709030238911, - 0.661398482245203922502, - 0.665422632544505177065, - 0.669430653942981734871, - 0.673422675212350441142, - 0.677398823590920073911, - 0.681359224807238206267, - 0.685304003098281100392, - 0.689233281238557538017, - 0.693147180560117703862); - - constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( - 0.0, - -0.00000000000000543229938420049, - 0.00000000000000172745674997061, - -0.00000000000001323017818229233, - -0.00000000000001154527628289872, - -0.00000000000000466529469958300, - 0.00000000000005148849572685810, - -0.00000000000002532168943117445, - -0.00000000000005213620639136504, - -0.00000000000001819506003016881, - 0.00000000000006329065958724544, - 0.00000000000008614512936087814, - -0.00000000000007355770219435028, - 0.00000000000009638067658552277, - 0.00000000000007598636597194141, - 0.00000000000002579999128306990, - -0.00000000000004654729747598444, - -0.00000000000007556920687451336, - 0.00000000000010195735223708472, - -0.00000000000017319034406422306, - -0.00000000000007718001336828098, - 0.00000000000010980754099855238, - -0.00000000000002047235780046195, - -0.00000000000008372091099235912, - 0.00000000000014088127937111135, - 0.00000000000012869017157588257, - 0.00000000000017788850778198106, - 0.00000000000006440856150696891, - 0.00000000000016132822667240822, - -0.00000000000007540916511956188, - -0.00000000000000036507188831790, - 0.00000000000009120937249914984, - 0.00000000000018567570959796010, - -0.00000000000003149265065191483, - -0.00000000000009309459495196889, - 0.00000000000017914338601329117, - -0.00000000000001302979717330866, - 0.00000000000023097385217586939, - 0.00000000000023999540484211737, - 0.00000000000015393776174455408, - -0.00000000000036870428315837678, - 0.00000000000036920375082080089, - -0.00000000000009383417223663699, - 0.00000000000009433398189512690, - 0.00000000000041481318704258568, - -0.00000000000003792316480209314, - 0.00000000000008403156304792424, - -0.00000000000034262934348285429, - 0.00000000000043712191957429145, - -0.00000000000010475750058776541, - -0.00000000000011118671389559323, - 0.00000000000037549577257259853, - 0.00000000000013912841212197565, - 0.00000000000010775743037572640, - 0.00000000000029391859187648000, - -0.00000000000042790509060060774, - 0.00000000000022774076114039555, - 0.00000000000010849569622967912, - -0.00000000000023073801945705758, - 0.00000000000015761203773969435, - 0.00000000000003345710269544082, - -0.00000000000041525158063436123, - 0.00000000000032655698896907146, - -0.00000000000044704265010452446, - 0.00000000000034527647952039772, - -0.00000000000007048962392109746, - 0.00000000000011776978751369214, - -0.00000000000010774341461609578, - 0.00000000000021863343293215910, - 0.00000000000024132639491333131, - 0.00000000000039057462209830700, - -0.00000000000026570679203560751, - 0.00000000000037135141919592021, - -0.00000000000017166921336082431, - -0.00000000000028658285157914353, - -0.00000000000023812542263446809, - 0.00000000000006576659768580062, - -0.00000000000028210143846181267, - 0.00000000000010701931762114254, - 0.00000000000018119346366441110, - 0.00000000000009840465278232627, - -0.00000000000033149150282752542, - -0.00000000000018302857356041668, - -0.00000000000016207400156744949, - 0.00000000000048303314949553201, - -0.00000000000071560553172382115, - 0.00000000000088821239518571855, - -0.00000000000030900580513238244, - -0.00000000000061076551972851496, - 0.00000000000035659969663347830, - 0.00000000000035782396591276383, - -0.00000000000046226087001544578, - 0.00000000000062279762917225156, - 0.00000000000072838947272065741, - 0.00000000000026809646615211673, - -0.00000000000010960825046059278, - 0.00000000000002311949383800537, - -0.00000000000058469058005299247, - -0.00000000000002103748251144494, - -0.00000000000023323182945587408, - -0.00000000000042333694288141916, - -0.00000000000043933937969737844, - 0.00000000000041341647073835565, - 0.00000000000006841763641591466, - 0.00000000000047585534004430641, - 0.00000000000083679678674757695, - -0.00000000000085763734646658640, - 0.00000000000021913281229340092, - -0.00000000000062242842536431148, - -0.00000000000010983594325438430, - 0.00000000000065310431377633651, - -0.00000000000047580199021710769, - -0.00000000000037854251265457040, - 0.00000000000040939233218678664, - 0.00000000000087424383914858291, - 0.00000000000025218188456842882, - -0.00000000000003608131360422557, - -0.00000000000050518555924280902, - 0.00000000000078699403323355317, - -0.00000000000067020876961949060, - 0.00000000000016108575753932458, - 0.00000000000058527188436251509, - -0.00000000000035246757297904791, - -0.00000000000018372084495629058, - 0.00000000000088606689813494916, - 0.00000000000066486268071468700, - 0.00000000000063831615170646519, - 0.00000000000025144230728376072, - -0.00000000000017239444525614834); - - variable M, J:INTEGER; - variable F1, F2, G, Q, U, U2, V: REAL; - variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs - variable ONE: REAL := 1.0; --Made variable so no constant folding occurs - - -- double logb(), ldexp(); - - variable U1:REAL; - - begin - - -- Check validity of argument - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = MATH_E ) then - return 1.0; - end if; - - -- Argument reduction: 1 <= g < 2; x/2^m = g; - -- y = F*(1 + f/F) for |f| <= 2^-8 - - M := ILOGB(X); - G := LDEXP(X, -M); - J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding - F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] - F2 := G - F1; - - -- Approximate expansion for log(1+f2/F1) ~= u + q - G := 1.0/(2.0*F1+F2); - U := 2.0*F2*G; - V := U*U; - Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); - - -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, - -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. - -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. - -- - if ( J /= 0 or M /= 0) then - U1 := U + 513.0; - U1 := U1 - 513.0; - - -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero - -- u1 = u to 24 bits. - -- - else - U1 := U; - --TRUNC(U1); --In c this is u1 = (double) (float) (u1) - end if; - - U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; - -- u1 + u2 = 2f/(2F+f) to extra precision. - - -- log(x) = log(2^m*F1*(1+f2/F1)) = - -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); - -- (exact) + (tiny) - - U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact - U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny - U2 := U2 + LOGF_TAIL(N)*REAL(M); - return (U1 + U2); - end LOG; - - - function LOG2 (X: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG2(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = 2.0 ) then - return 1.0; - end if; - - -- Compute value for general case - return ( MATH_LOG2_OF_E*LOG(X) ); - end LOG2; - - - function LOG10 (X: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG10(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = 10.0 ) then - return 1.0; - end if; - - -- Compute value for general case - return ( MATH_LOG10_OF_E*LOG(X) ); - end LOG10; - - - function LOG (X: in REAL; BASE: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG(X, BASE)" - severity ERROR; - return(REAL'LOW); - end if; - - if ( BASE <= 0.0 or BASE = 1.0 ) then - assert FALSE - report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = BASE ) then - return 1.0; - end if; - - -- Compute value for general case - return ( LOG(X)/LOG(BASE)); - end LOG; - - - function SIN (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) SIN(-X) = -SIN(X) - -- b) SIN(X) = X if ABS(X) < EPS - -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS - -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) - -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS - -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if - -- EPS< ABS(X) MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in SIN(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then - return 0.0; - end if; - - if XLOCAL = MATH_PI_OVER_2 then - if NEGATIVE then - return -1.0; - else - return 1.0; - end if; - end if; - - if XLOCAL = MATH_3_PI_OVER_2 then - if NEGATIVE then - return 1.0; - else - return -1.0; - end if; - end if; - - if XLOCAL < EPS then - if NEGATIVE then - return -XLOCAL; - else - return XLOCAL; - end if; - else - if XLOCAL < BASE_EPS then - TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := MATH_PI - XLOCAL; - if ABS(TEMP) < EPS then - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - else - if ABS(TEMP) < BASE_EPS then - TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := MATH_2_PI - XLOCAL; - if ABS(TEMP) < EPS then - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - else - if ABS(TEMP) < BASE_EPS then - TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - end if; - end if; - - TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); - if TEMP < EPS then - TEMP := 1.0 - TEMP*TEMP*0.5; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - else - if TEMP < BASE_EPS then - TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); - if TEMP < EPS then - TEMP := 1.0 - TEMP*TEMP*0.5; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - else - if TEMP < BASE_EPS then - TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - end if; - end if; - - -- Compute value for general cases - if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then - VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); - end if; - - N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); - case QUADRANT( N mod 4) is - when 0 => - VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); - when 1 => - VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, - ROTATION)(0); - when 2 => - VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); - when 3 => - VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, - ROTATION)(0); - end case; - - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end SIN; - - - function COS (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) COS(-X) = COS(X) - -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) - -- c) COS(MATH_PI + X) = -COS(X) - -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS - -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if - -- EPS< ABS(X) MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in COS(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then - return 1.0; - end if; - - if XLOCAL = MATH_PI then - return -1.0; - end if; - - if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then - return 0.0; - end if; - - TEMP := ABS(XLOCAL); - if ( TEMP < EPS) then - return (1.0 - 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - TEMP := ABS(XLOCAL -MATH_2_PI); - if ( TEMP < EPS) then - return (1.0 - 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - TEMP := ABS (XLOCAL - MATH_PI); - if TEMP < EPS then - return (-1.0 + 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - -- Compute value for general cases - return SIN(MATH_PI_OVER_2 - XLOCAL); - end COS; - - function TAN (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) TAN(0.0) = 0.0 - -- b) TAN(-X) = -TAN(X) - -- c) Returns REAL'LOW on error if X < 0.0 - -- d) Returns REAL'HIGH on error if X > 0.0 - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X) ; - variable VALUE: REAL; - variable TEMP : REAL; - - begin - -- Make 0.0 <= XLOCAL <= MATH_2_PI - if XLOCAL > MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in TAN(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Check validity of argument - if XLOCAL = MATH_PI_OVER_2 then - assert FALSE - report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" - severity ERROR; - if NEGATIVE then - return(REAL'LOW); - else - return(REAL'HIGH); - end if; - end if; - - if XLOCAL = MATH_3_PI_OVER_2 then - assert FALSE - report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" - severity ERROR; - if NEGATIVE then - return(REAL'HIGH); - else - return(REAL'LOW); - end if; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_PI then - return 0.0; - end if; - - -- Compute value for general cases - VALUE := SIN(XLOCAL)/COS(XLOCAL); - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end TAN; - - function ARCSIN (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCSIN(-X) = -ARCSIN(X) - -- b) Returns X on error - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable VALUE : REAL; - - begin - -- Check validity of arguments - if XLOCAL > 1.0 then - assert FALSE - report "ABS(X) > 1.0 in ARCSIN(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - elsif XLOCAL = 1.0 then - if NEGATIVE then - return -MATH_PI_OVER_2; - else - return MATH_PI_OVER_2; - end if; - end if; - - -- Compute value for general cases - if XLOCAL < 0.9 then - VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); - else - VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); - end if; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCSIN; - - function ARCCOS (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) - -- b) Returns X on error - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable VALUE : REAL; - - begin - -- Check validity of argument - if XLOCAL > 1.0 then - assert FALSE - report "ABS(X) > 1.0 in ARCCOS(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 1.0 then - return 0.0; - elsif X = 0.0 then - return MATH_PI_OVER_2; - elsif X = -1.0 then - return MATH_PI; - end if; - - -- Compute value for general cases - if XLOCAL > 0.9 then - VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); - else - VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); - end if; - - - if NEGATIVE then - VALUE := MATH_PI - VALUE; - end if; - - return VALUE; - end ARCCOS; - - - function ARCTAN (Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCTAN(-Y) = -ARCTAN(Y) - -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 - -- c) ARCTAN(Y) = Y for |Y| < EPS - - constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; - - variable NEGATIVE : BOOLEAN := Y < 0.0; - variable RECIPROCAL : BOOLEAN; - variable YLOCAL : REAL := ABS(Y); - variable VALUE : REAL; - - begin - -- Make argument |Y| <=1.0 - if YLOCAL > 1.0 then - YLOCAL := 1.0/YLOCAL; - RECIPROCAL := TRUE; - else - RECIPROCAL := FALSE; - end if; - - -- Compute value for special cases - if YLOCAL = 0.0 then - if RECIPROCAL then - if NEGATIVE then - return (-MATH_PI_OVER_2); - else - return (MATH_PI_OVER_2); - end if; - else - return 0.0; - end if; - end if; - - if YLOCAL < EPS then - if NEGATIVE then - if RECIPROCAL then - return (-MATH_PI_OVER_2 + YLOCAL); - else - return -YLOCAL; - end if; - else - if RECIPROCAL then - return (MATH_PI_OVER_2 - YLOCAL); - else - return YLOCAL; - end if; - end if; - end if; - - -- Compute value for general cases - VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); - - if RECIPROCAL then - VALUE := MATH_PI_OVER_2 - VALUE; - end if; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCTAN; - - - function ARCTAN (Y : in REAL; X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable YLOCAL : REAL; - variable VALUE : REAL; - begin - - -- Check validity of arguments - if (Y = 0.0 and X = 0.0 ) then - assert FALSE report - "ARCTAN(0.0, 0.0) is undetermined" - severity ERROR; - return 0.0; - end if; - - -- Compute value for special cases - if Y = 0.0 then - if X > 0.0 then - return 0.0; - else - return MATH_PI; - end if; - end if; - - if X = 0.0 then - if Y > 0.0 then - return MATH_PI_OVER_2; - else - return -MATH_PI_OVER_2; - end if; - end if; - - - -- Compute value for general cases - YLOCAL := ABS(Y/X); - - VALUE := ARCTAN(YLOCAL); - - if X < 0.0 then - VALUE := MATH_PI - VALUE; - end if; - - if Y < 0.0 then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCTAN; - - - function SINH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) - EXP(-X))/2.0 - -- b) SINH(-X) = SINH(X) - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP - 1.0/TEMP)*0.5; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end SINH; - - function COSH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) + EXP(-X))/2.0 - -- b) COSH(-X) = COSH(X) - - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 1.0; - end if; - - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP + 1.0/TEMP)*0.5; - - return VALUE; - end COSH; - - function TANH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) - -- b) TANH(-X) = -TANH(X) - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); - - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end TANH; - - function ARCSINH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns LOG( X + SQRT( X*X + 1.0)) - - begin - -- Compute value for special cases - if X = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - return ( LOG( X + SQRT( X*X + 1.0)) ); - end ARCSINH; - - - - function ARCCOSH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 - -- b) Returns X on error - - begin - -- Check validity of arguments - if X < 1.0 then - assert FALSE - report "X < 1.0 in ARCCOSH(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 1.0 then - return 0.0; - end if; - - -- Compute value for general cases - return ( LOG( X + SQRT( X*X - 1.0))); - end ARCCOSH; - - function ARCTANH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 - -- b) Returns X on error - begin - -- Check validity of arguments - if ABS(X) >= 1.0 then - assert FALSE - report "ABS(X) >= 1.0 in ARCTANH(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); - end ARCTANH; - -end MATH_REAL; diff --git a/CPLD/LCMXO2-1200HC/generate_core.tcl b/CPLD/LCMXO2-1200HC/generate_core.tcl deleted file mode 100644 index 47f429b..0000000 --- a/CPLD/LCMXO2-1200HC/generate_core.tcl +++ /dev/null @@ -1,100 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -proc GetCmdLine {lpcfile} { - global Para - - if [catch {open $lpcfile r} fileid] { - puts "Cannot open $para_file file!" - exit -1 - } - - seek $fileid 0 start - set default_match 0 - while {[gets $fileid line] >= 0} { - if {[string first "\[Command\]" $line] == 0} { - set default_match 1 - continue - } - if {[string first "\[" $line] == 0} { - set default_match 0 - } - if {$default_match == 1} { - if [regexp {([^=]*)=(.*)} $line match parameter value] { - if [regexp {([ |\t]*;)} $parameter match] {continue} - if [regexp {(.*)[ |\t]*;} $value match temp] { - set Para($parameter) $temp - } else { - set Para($parameter) $value - } - } - } - } - set default_match 0 - close $fileid - - return $Para(cmd_line) -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" - -set scuba "$Para(FPGAPath)/scuba" -set modulename "REFB" -set lang "verilog" -set lpcfile "$Para(sbp_path)/$modulename.lpc" -set arch "xo2c00" -set cmd_line [GetCmdLine $lpcfile] -set fdcfile "$Para(sbp_path)/$modulename.fdc" -if {[file exists $fdcfile] == 0} { - append scuba " " $cmd_line -} else { - append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" -} -set Para(result) [catch {eval exec "$scuba"} msg] -#puts $msg diff --git a/CPLD/LCMXO2-1200HC/generate_ngd.tcl b/CPLD/LCMXO2-1200HC/generate_ngd.tcl deleted file mode 100644 index fcdb02c..0000000 --- a/CPLD/LCMXO2-1200HC/generate_ngd.tcl +++ /dev/null @@ -1,74 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" -set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" - -set Para(ModuleName) "REFB" -set Para(Module) "EFB" -set Para(libname) machxo2 -set Para(arch_name) xo2c00 -set Para(PartType) "LCMXO2-1200HC" - -set Para(tech_syn) machxo2 -set Para(tech_cae) machxo2 -set Para(Package) "TQFP100" -set Para(SpeedGrade) "4" -set Para(FMax) "100" -set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" - -#edif2ngd -set edif2ngd "$Para(FPGAPath)/edif2ngd" -set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] -#puts $msg - -#ngdbuild -set ngdbuild "$Para(FPGAPath)/ngdbuild" -set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] -#puts $msg diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt deleted file mode 100644 index fbfdb79..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt +++ /dev/null @@ -1,77 +0,0 @@ -NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * -NOTE All Rights Reserved * -NOTE DATE CREATED: Thu Dec 28 23:24:00 2023 * -NOTE DESIGN NAME: RAM2E * -NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 * -NOTE PIN ASSIGNMENTS * -NOTE PINS RD[0] : 36 : inout * -NOTE PINS LED : 35 : out * -NOTE PINS C14M : 62 : in * -NOTE PINS RD[7] : 43 : inout * -NOTE PINS RD[6] : 42 : inout * -NOTE PINS RD[5] : 41 : inout * -NOTE PINS RD[4] : 40 : inout * -NOTE PINS RD[3] : 39 : inout * -NOTE PINS RD[2] : 38 : inout * -NOTE PINS RD[1] : 37 : inout * -NOTE PINS DQMH : 49 : out * -NOTE PINS DQML : 48 : out * -NOTE PINS RAout[11] : 59 : out * -NOTE PINS RAout[10] : 64 : out * -NOTE PINS RAout[9] : 63 : out * -NOTE PINS RAout[8] : 65 : out * -NOTE PINS RAout[7] : 67 : out * -NOTE PINS RAout[6] : 69 : out * -NOTE PINS RAout[5] : 71 : out * -NOTE PINS RAout[4] : 75 : out * -NOTE PINS RAout[3] : 74 : out * -NOTE PINS RAout[2] : 70 : out * -NOTE PINS RAout[1] : 68 : out * -NOTE PINS RAout[0] : 66 : out * -NOTE PINS BA[1] : 60 : out * -NOTE PINS BA[0] : 58 : out * -NOTE PINS nRWEout : 51 : out * -NOTE PINS nCASout : 52 : out * -NOTE PINS nRASout : 54 : out * -NOTE PINS nCSout : 57 : out * -NOTE PINS CKEout : 53 : out * -NOTE PINS nVOE : 10 : out * -NOTE PINS Vout[7] : 12 : out * -NOTE PINS Vout[6] : 14 : out * -NOTE PINS Vout[5] : 16 : out * -NOTE PINS Vout[4] : 19 : out * -NOTE PINS Vout[3] : 13 : out * -NOTE PINS Vout[2] : 17 : out * -NOTE PINS Vout[1] : 15 : out * -NOTE PINS Vout[0] : 18 : out * -NOTE PINS nDOE : 20 : out * -NOTE PINS Dout[7] : 32 : out * -NOTE PINS Dout[6] : 31 : out * -NOTE PINS Dout[5] : 21 : out * -NOTE PINS Dout[4] : 24 : out * -NOTE PINS Dout[3] : 28 : out * -NOTE PINS Dout[2] : 25 : out * -NOTE PINS Dout[1] : 27 : out * -NOTE PINS Dout[0] : 30 : out * -NOTE PINS Din[7] : 87 : in * -NOTE PINS Din[6] : 88 : in * -NOTE PINS Din[5] : 99 : in * -NOTE PINS Din[4] : 1 : in * -NOTE PINS Din[3] : 9 : in * -NOTE PINS Din[2] : 98 : in * -NOTE PINS Din[1] : 97 : in * -NOTE PINS Din[0] : 96 : in * -NOTE PINS Ain[7] : 8 : in * -NOTE PINS Ain[6] : 86 : in * -NOTE PINS Ain[5] : 84 : in * -NOTE PINS Ain[4] : 78 : in * -NOTE PINS Ain[3] : 4 : in * -NOTE PINS Ain[2] : 7 : in * -NOTE PINS Ain[1] : 2 : in * -NOTE PINS Ain[0] : 3 : in * -NOTE PINS nC07X : 34 : in * -NOTE PINS nEN80 : 82 : in * -NOTE PINS nWE : 29 : in * -NOTE PINS PHI1 : 85 : in * -NOTE CONFIGURATION MODE: NONE * -NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr deleted file mode 100644 index 927a5fd..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr +++ /dev/null @@ -1,61 +0,0 @@ ----------------------------------------------------------------------- -Report for cell RAM2E.verilog - -Register bits: 122 of 1280 (10%) -PIC Latch: 0 -I/O cells: 69 - Cell usage: - cell count Res Usage(%) - BB 8 100.0 - CCU2D 9 100.0 - EFB 1 100.0 - FD1P3AX 61 100.0 - FD1P3IX 1 100.0 - FD1S3AX 21 100.0 - FD1S3AY 4 100.0 - FD1S3IX 6 100.0 - GSR 1 100.0 - IB 21 100.0 - IFS1P3DX 1 100.0 - INV 1 100.0 - OB 40 100.0 - OFS1P3BX 5 100.0 - OFS1P3DX 21 100.0 - OFS1P3IX 2 100.0 - ORCALUT4 277 100.0 - PFUMX 3 100.0 - PUR 1 100.0 - VHI 3 100.0 - VLO 3 100.0 -SUB MODULES - RAM2E_UFM 1 100.0 - REFB 1 100.0 - - TOTAL 492 ----------------------------------------------------------------------- -Report for cell RAM2E_UFM.netlist - Instance path: ram2e_ufm - Cell usage: - cell count Res Usage(%) - EFB 1 100.0 - FD1P3AX 30 49.2 - FD1P3IX 1 100.0 - FD1S3IX 1 16.7 - ORCALUT4 272 98.2 - PFUMX 3 100.0 - VHI 2 66.7 - VLO 2 66.7 -SUB MODULES - REFB 1 100.0 - - TOTAL 313 ----------------------------------------------------------------------- -Report for cell REFB.netlist - Instance path: ram2e_ufm.ufmefb - Cell usage: - cell count Res Usage(%) - EFB 1 100.0 - VHI 1 33.3 - VLO 1 33.3 - - TOTAL 3 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn deleted file mode 100644 index 9b2aaa0..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn +++ /dev/null @@ -1,86 +0,0 @@ -BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Dec 28 23:23:57 2023 - - -Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf - -Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. - -Running DRC. -DRC detected 0 errors and 0 warnings. -Reading Preference File from RAM2E_LCMXO2_1200HC_impl1.prf. - -Preference Summary: -+---------------------------------+---------------------------------+ -| Preference | Current Setting | -+---------------------------------+---------------------------------+ -| RamCfg | Reset** | -+---------------------------------+---------------------------------+ -| MCCLK_FREQ | 2.08** | -+---------------------------------+---------------------------------+ -| CONFIG_SECURE | OFF** | -+---------------------------------+---------------------------------+ -| INBUF | ON** | -+---------------------------------+---------------------------------+ -| JTAG_PORT | ENABLE** | -+---------------------------------+---------------------------------+ -| SDM_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| SLAVE_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MASTER_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| I2C_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MUX_CONFIGURATION_PORTS | DISABLE** | -+---------------------------------+---------------------------------+ -| CONFIGURATION | CFG** | -+---------------------------------+---------------------------------+ -| COMPRESS_CONFIG | ON** | -+---------------------------------+---------------------------------+ -| MY_ASSP | OFF** | -+---------------------------------+---------------------------------+ -| ONE_TIME_PROGRAM | OFF** | -+---------------------------------+---------------------------------+ -| ENABLE_TRANSFR | DISABLE** | -+---------------------------------+---------------------------------+ -| SHAREDEBRINIT | DISABLE** | -+---------------------------------+---------------------------------+ -| BACKGROUND_RECONFIG | OFF** | -+---------------------------------+---------------------------------+ - * Default setting. - ** The specified setting matches the default setting. - - -Creating bit map... - -Bitstream Status: Final Version 1.95. - -Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.jed". - -=========== -UFM Summary. -=========== -UFM Size: 511 Pages (128*511 Bits). -UFM Utilization: General Purpose Flash Memory. - -Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510). -Initialized UFM Pages: 321 Pages (Page 190 to Page 510). - -Total CPU Time: 3 secs -Total REAL Time: 3 secs -Peak Memory Usage: 275 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bit b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bit deleted file mode 100644 index 0141520..0000000 Binary files a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bit and /dev/null differ diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.edi b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.edi deleted file mode 100644 index c3293ce..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.edi +++ /dev/null @@ -1,5874 +0,0 @@ -(edif RAM2E - (edifVersion 2 0 0) - (edifLevel 0) - (keywordMap (keywordLevel 0)) - (status - (written - (timeStamp 2023 12 28 23 23 26) - (author "Synopsys, Inc.") - (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R")) - ) - ) - (library LUCENT - (edifLevel 0) - (technology (numberDefinition )) - (cell CCU2D (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A0 (direction INPUT)) - (port B0 (direction INPUT)) - (port C0 (direction INPUT)) - (port D0 (direction INPUT)) - (port A1 (direction INPUT)) - (port B1 (direction INPUT)) - (port C1 (direction INPUT)) - (port D1 (direction INPUT)) - (port CIN (direction INPUT)) - (port COUT (direction OUTPUT)) - (port S0 (direction OUTPUT)) - (port S1 (direction OUTPUT)) - ) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0000")) - (property INIT0 (string "0000")) - ) - ) - (cell BB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port B (direction INOUT)) - (port I (direction INPUT)) - (port T (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell OB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port I (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell IB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port I (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell FD1S3IX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1S3AY (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1S3AX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1P3IX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port CK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell OFS1P3IX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell OFS1P3DX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell IFS1P3DX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell OFS1P3BX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port PD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1P3AX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port CK (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell ORCALUT4 (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A (direction INPUT)) - (port B (direction INPUT)) - (port C (direction INPUT)) - (port D (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell PFUMX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port ALUT (direction INPUT)) - (port BLUT (direction INPUT)) - (port C0 (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell GSR (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port GSR (direction INPUT)) - ) - ) - ) - (cell INV (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell VHI (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port Z (direction OUTPUT)) - ) - ) - ) - (cell VLO (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port Z (direction OUTPUT)) - ) - ) - ) - ) - (library work - (edifLevel 0) - (technology (numberDefinition )) - (cell EFB (cellType GENERIC) - (view verilog (viewType NETLIST) - (interface - (port WBCLKI (direction INPUT)) - (port WBRSTI (direction INPUT)) - (port WBCYCI (direction INPUT)) - (port WBSTBI (direction INPUT)) - (port WBWEI (direction INPUT)) - (port WBADRI7 (direction INPUT)) - (port WBADRI6 (direction INPUT)) - (port WBADRI5 (direction INPUT)) - (port WBADRI4 (direction INPUT)) - (port WBADRI3 (direction INPUT)) - (port WBADRI2 (direction INPUT)) - (port WBADRI1 (direction INPUT)) - (port WBADRI0 (direction INPUT)) - (port WBDATI7 (direction INPUT)) - (port WBDATI6 (direction INPUT)) - (port WBDATI5 (direction INPUT)) - (port WBDATI4 (direction INPUT)) - (port WBDATI3 (direction INPUT)) - (port WBDATI2 (direction INPUT)) - (port WBDATI1 (direction INPUT)) - (port WBDATI0 (direction INPUT)) - (port PLL0DATI7 (direction INPUT)) - (port PLL0DATI6 (direction INPUT)) - (port PLL0DATI5 (direction INPUT)) - (port PLL0DATI4 (direction INPUT)) - (port PLL0DATI3 (direction INPUT)) - (port PLL0DATI2 (direction INPUT)) - (port PLL0DATI1 (direction INPUT)) - (port PLL0DATI0 (direction INPUT)) - (port PLL0ACKI (direction INPUT)) - (port PLL1DATI7 (direction INPUT)) - (port PLL1DATI6 (direction INPUT)) - (port PLL1DATI5 (direction INPUT)) - (port PLL1DATI4 (direction INPUT)) - (port PLL1DATI3 (direction INPUT)) - (port PLL1DATI2 (direction INPUT)) - (port PLL1DATI1 (direction INPUT)) - (port PLL1DATI0 (direction INPUT)) - (port PLL1ACKI (direction INPUT)) - (port I2C1SCLI (direction INPUT)) - (port I2C1SDAI (direction INPUT)) - (port I2C2SCLI (direction INPUT)) - (port I2C2SDAI (direction INPUT)) - (port SPISCKI (direction INPUT)) - (port SPIMISOI (direction INPUT)) - (port SPIMOSII (direction INPUT)) - (port SPISCSN (direction INPUT)) - (port TCCLKI (direction INPUT)) - (port TCRSTN (direction INPUT)) - (port TCIC (direction INPUT)) - (port UFMSN (direction INPUT)) - (port WBDATO7 (direction OUTPUT)) - (port WBDATO6 (direction OUTPUT)) - (port WBDATO5 (direction OUTPUT)) - (port WBDATO4 (direction OUTPUT)) - (port WBDATO3 (direction OUTPUT)) - (port WBDATO2 (direction OUTPUT)) - (port WBDATO1 (direction OUTPUT)) - (port WBDATO0 (direction OUTPUT)) - (port WBACKO (direction OUTPUT)) - (port PLLCLKO (direction OUTPUT)) - (port PLLRSTO (direction OUTPUT)) - (port PLL0STBO (direction OUTPUT)) - (port PLL1STBO (direction OUTPUT)) - (port PLLWEO (direction OUTPUT)) - (port PLLADRO4 (direction OUTPUT)) - (port PLLADRO3 (direction OUTPUT)) - (port PLLADRO2 (direction OUTPUT)) - (port PLLADRO1 (direction OUTPUT)) - (port PLLADRO0 (direction OUTPUT)) - (port PLLDATO7 (direction OUTPUT)) - (port PLLDATO6 (direction OUTPUT)) - (port PLLDATO5 (direction OUTPUT)) - (port PLLDATO4 (direction OUTPUT)) - (port PLLDATO3 (direction OUTPUT)) - (port PLLDATO2 (direction OUTPUT)) - (port PLLDATO1 (direction OUTPUT)) - (port PLLDATO0 (direction OUTPUT)) - (port I2C1SCLO (direction OUTPUT)) - (port I2C1SCLOEN (direction OUTPUT)) - (port I2C1SDAO (direction OUTPUT)) - (port I2C1SDAOEN (direction OUTPUT)) - (port I2C2SCLO (direction OUTPUT)) - (port I2C2SCLOEN (direction OUTPUT)) - (port I2C2SDAO (direction OUTPUT)) - (port I2C2SDAOEN (direction OUTPUT)) - (port I2C1IRQO (direction OUTPUT)) - (port I2C2IRQO (direction OUTPUT)) - (port SPISCKO (direction OUTPUT)) - (port SPISCKEN (direction OUTPUT)) - (port SPIMISOO (direction OUTPUT)) - (port SPIMISOEN (direction OUTPUT)) - (port SPIMOSIO (direction OUTPUT)) - (port SPIMOSIEN (direction OUTPUT)) - (port SPIMCSN0 (direction OUTPUT)) - (port SPIMCSN1 (direction OUTPUT)) - (port SPIMCSN2 (direction OUTPUT)) - (port SPIMCSN3 (direction OUTPUT)) - (port SPIMCSN4 (direction OUTPUT)) - (port SPIMCSN5 (direction OUTPUT)) - (port SPIMCSN6 (direction OUTPUT)) - (port SPIMCSN7 (direction OUTPUT)) - (port SPICSNEN (direction OUTPUT)) - (port SPIIRQO (direction OUTPUT)) - (port TCINT (direction OUTPUT)) - (port TCOC (direction OUTPUT)) - (port WBCUFMIRQ (direction OUTPUT)) - (port CFGWAKE (direction OUTPUT)) - (port CFGSTDBY (direction OUTPUT)) - ) - (property TC_ICAPTURE (string "DISABLED")) - (property TC_OVERFLOW (string "DISABLED")) - (property TC_ICR_INT (string "OFF")) - (property TC_OCR_INT (string "OFF")) - (property TC_OV_INT (string "OFF")) - (property TC_TOP_SEL (string "OFF")) - (property TC_RESETN (string "ENABLED")) - (property TC_OC_MODE (string "TOGGLE")) - (property TC_OCR_SET (integer 32767)) - (property TC_TOP_SET (integer 65535)) - (property GSR (string "ENABLED")) - (property TC_CCLK_SEL (integer 1)) - (property TC_SCLK_SEL (string "PCLOCK")) - (property TC_MODE (string "CTCM")) - (property SPI_WAKEUP (string "DISABLED")) - (property SPI_INTR_RXOVR (string "DISABLED")) - (property SPI_INTR_TXOVR (string "DISABLED")) - (property SPI_INTR_RXRDY (string "DISABLED")) - (property SPI_INTR_TXRDY (string "DISABLED")) - (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) - (property SPI_PHASE_ADJ (string "DISABLED")) - (property SPI_CLK_INV (string "DISABLED")) - (property SPI_LSB_FIRST (string "DISABLED")) - (property SPI_CLK_DIVIDER (integer 1)) - (property SPI_MODE (string "MASTER")) - (property I2C2_WAKEUP (string "DISABLED")) - (property I2C1_WAKEUP (string "DISABLED")) - (property I2C2_GEN_CALL (string "DISABLED")) - (property I2C1_GEN_CALL (string "DISABLED")) - (property I2C2_CLK_DIVIDER (integer 1)) - (property I2C1_CLK_DIVIDER (integer 1)) - (property I2C2_BUS_PERF (string "100kHz")) - (property I2C1_BUS_PERF (string "100kHz")) - (property I2C2_SLAVE_ADDR (string "0b1000010")) - (property I2C1_SLAVE_ADDR (string "0b1000001")) - (property I2C2_ADDRESSING (string "7BIT")) - (property I2C1_ADDRESSING (string "7BIT")) - (property UFM_INIT_FILE_FORMAT (string "HEX")) - (property UFM_INIT_FILE_NAME (string "../RAM2E-LCMXO2.mem")) - (property UFM_INIT_ALL_ZEROS (string "DISABLED")) - (property UFM_INIT_START_PAGE (integer 190)) - (property UFM_INIT_PAGES (integer 321)) - (property DEV_DENSITY (string "1200L")) - (property EFB_WB_CLK_FREQ (string "14.4")) - (property EFB_UFM (string "ENABLED")) - (property EFB_TC_PORTMODE (string "WB")) - (property EFB_TC (string "DISABLED")) - (property EFB_SPI (string "DISABLED")) - (property EFB_I2C2 (string "DISABLED")) - (property EFB_I2C1 (string "DISABLED")) - (property orig_inst_of (string "EFB")) - ) - ) - (cell REFB (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename wb_dato "wb_dato[7:0]") 8) (direction OUTPUT)) - (port (array (rename wb_dati "wb_dati[7:0]") 8) (direction INPUT)) - (port (array (rename wb_adr "wb_adr[7:0]") 8) (direction INPUT)) - (port wb_ack (direction OUTPUT)) - (port wb_we (direction INPUT)) - (port wb_cyc_stb (direction INPUT)) - (port wb_rst (direction INPUT)) - (port C14M_c (direction INPUT)) - ) - (contents - (instance EFBInst_0 (viewRef verilog (cellRef EFB)) - (property UFM_INIT_FILE_FORMAT (string "HEX")) - (property UFM_INIT_FILE_NAME (string "../RAM2E-LCMXO2.mem")) - (property UFM_INIT_ALL_ZEROS (string "DISABLED")) - (property UFM_INIT_START_PAGE (integer 190)) - (property UFM_INIT_PAGES (integer 321)) - (property DEV_DENSITY (string "1200L")) - (property EFB_UFM (string "ENABLED")) - (property TC_ICAPTURE (string "DISABLED")) - (property TC_OVERFLOW (string "DISABLED")) - (property TC_ICR_INT (string "OFF")) - (property TC_OCR_INT (string "OFF")) - (property TC_OV_INT (string "OFF")) - (property TC_TOP_SEL (string "OFF")) - (property TC_RESETN (string "ENABLED")) - (property TC_OC_MODE (string "TOGGLE")) - (property TC_OCR_SET (integer 32767)) - (property TC_TOP_SET (integer 65535)) - (property GSR (string "ENABLED")) - (property TC_CCLK_SEL (integer 1)) - (property TC_MODE (string "CTCM")) - (property TC_SCLK_SEL (string "PCLOCK")) - (property EFB_TC_PORTMODE (string "WB")) - (property EFB_TC (string "DISABLED")) - (property SPI_WAKEUP (string "DISABLED")) - (property SPI_INTR_RXOVR (string "DISABLED")) - (property SPI_INTR_TXOVR (string "DISABLED")) - (property SPI_INTR_RXRDY (string "DISABLED")) - (property SPI_INTR_TXRDY (string "DISABLED")) - (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) - (property SPI_PHASE_ADJ (string "DISABLED")) - (property SPI_CLK_INV (string "DISABLED")) - (property SPI_LSB_FIRST (string "DISABLED")) - (property SPI_CLK_DIVIDER (integer 1)) - (property SPI_MODE (string "MASTER")) - (property EFB_SPI (string "DISABLED")) - (property I2C2_WAKEUP (string "DISABLED")) - (property I2C2_GEN_CALL (string "DISABLED")) - (property I2C2_CLK_DIVIDER (integer 1)) - (property I2C2_BUS_PERF (string "100kHz")) - (property I2C2_SLAVE_ADDR (string "0b1000010")) - (property I2C2_ADDRESSING (string "7BIT")) - (property EFB_I2C2 (string "DISABLED")) - (property I2C1_WAKEUP (string "DISABLED")) - (property I2C1_GEN_CALL (string "DISABLED")) - (property I2C1_CLK_DIVIDER (integer 1)) - (property I2C1_BUS_PERF (string "100kHz")) - (property I2C1_SLAVE_ADDR (string "0b1000001")) - (property I2C1_ADDRESSING (string "7BIT")) - (property EFB_I2C1 (string "DISABLED")) - (property EFB_WB_CLK_FREQ (string "14.4")) - ) - (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net C14M_c (joined - (portRef C14M_c) - (portRef WBCLKI (instanceRef EFBInst_0)) - )) - (net wb_rst (joined - (portRef wb_rst) - (portRef WBRSTI (instanceRef EFBInst_0)) - )) - (net wb_cyc_stb (joined - (portRef wb_cyc_stb) - (portRef WBSTBI (instanceRef EFBInst_0)) - (portRef WBCYCI (instanceRef EFBInst_0)) - )) - (net wb_we (joined - (portRef wb_we) - (portRef WBWEI (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_7 "wb_adr[7]") (joined - (portRef (member wb_adr 0)) - (portRef WBADRI7 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_6 "wb_adr[6]") (joined - (portRef (member wb_adr 1)) - (portRef WBADRI6 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_5 "wb_adr[5]") (joined - (portRef (member wb_adr 2)) - (portRef WBADRI5 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_4 "wb_adr[4]") (joined - (portRef (member wb_adr 3)) - (portRef WBADRI4 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_3 "wb_adr[3]") (joined - (portRef (member wb_adr 4)) - (portRef WBADRI3 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_2 "wb_adr[2]") (joined - (portRef (member wb_adr 5)) - (portRef WBADRI2 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_1 "wb_adr[1]") (joined - (portRef (member wb_adr 6)) - (portRef WBADRI1 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_0 "wb_adr[0]") (joined - (portRef (member wb_adr 7)) - (portRef WBADRI0 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_7 "wb_dati[7]") (joined - (portRef (member wb_dati 0)) - (portRef WBDATI7 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_6 "wb_dati[6]") (joined - (portRef (member wb_dati 1)) - (portRef WBDATI6 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_5 "wb_dati[5]") (joined - (portRef (member wb_dati 2)) - (portRef WBDATI5 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_4 "wb_dati[4]") (joined - (portRef (member wb_dati 3)) - (portRef WBDATI4 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_3 "wb_dati[3]") (joined - (portRef (member wb_dati 4)) - (portRef WBDATI3 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_2 "wb_dati[2]") (joined - (portRef (member wb_dati 5)) - (portRef WBDATI2 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_1 "wb_dati[1]") (joined - (portRef (member wb_dati 6)) - (portRef WBDATI1 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_0 "wb_dati[0]") (joined - (portRef (member wb_dati 7)) - (portRef WBDATI0 (instanceRef EFBInst_0)) - )) - (net GND (joined - (portRef Z (instanceRef GND)) - (portRef TCIC (instanceRef EFBInst_0)) - (portRef TCRSTN (instanceRef EFBInst_0)) - (portRef TCCLKI (instanceRef EFBInst_0)) - (portRef SPISCSN (instanceRef EFBInst_0)) - (portRef SPIMOSII (instanceRef EFBInst_0)) - (portRef SPIMISOI (instanceRef EFBInst_0)) - (portRef SPISCKI (instanceRef EFBInst_0)) - (portRef I2C2SDAI (instanceRef EFBInst_0)) - (portRef I2C2SCLI (instanceRef EFBInst_0)) - (portRef I2C1SDAI (instanceRef EFBInst_0)) - (portRef I2C1SCLI (instanceRef EFBInst_0)) - (portRef PLL1ACKI (instanceRef EFBInst_0)) - (portRef PLL1DATI0 (instanceRef EFBInst_0)) - (portRef PLL1DATI1 (instanceRef EFBInst_0)) - (portRef PLL1DATI2 (instanceRef EFBInst_0)) - (portRef PLL1DATI3 (instanceRef EFBInst_0)) - (portRef PLL1DATI4 (instanceRef EFBInst_0)) - (portRef PLL1DATI5 (instanceRef EFBInst_0)) - (portRef PLL1DATI6 (instanceRef EFBInst_0)) - (portRef PLL1DATI7 (instanceRef EFBInst_0)) - (portRef PLL0ACKI (instanceRef EFBInst_0)) - (portRef PLL0DATI0 (instanceRef EFBInst_0)) - (portRef PLL0DATI1 (instanceRef EFBInst_0)) - (portRef PLL0DATI2 (instanceRef EFBInst_0)) - (portRef PLL0DATI3 (instanceRef EFBInst_0)) - (portRef PLL0DATI4 (instanceRef EFBInst_0)) - (portRef PLL0DATI5 (instanceRef EFBInst_0)) - (portRef PLL0DATI6 (instanceRef EFBInst_0)) - (portRef PLL0DATI7 (instanceRef EFBInst_0)) - )) - (net VCC (joined - (portRef Z (instanceRef VCC)) - (portRef UFMSN (instanceRef EFBInst_0)) - )) - (net (rename wb_dato_7 "wb_dato[7]") (joined - (portRef WBDATO7 (instanceRef EFBInst_0)) - (portRef (member wb_dato 0)) - )) - (net (rename wb_dato_6 "wb_dato[6]") (joined - (portRef WBDATO6 (instanceRef EFBInst_0)) - (portRef (member wb_dato 1)) - )) - (net (rename wb_dato_5 "wb_dato[5]") (joined - (portRef WBDATO5 (instanceRef EFBInst_0)) - (portRef (member wb_dato 2)) - )) - (net (rename wb_dato_4 "wb_dato[4]") (joined - (portRef WBDATO4 (instanceRef EFBInst_0)) - (portRef (member wb_dato 3)) - )) - (net (rename wb_dato_3 "wb_dato[3]") (joined - (portRef WBDATO3 (instanceRef EFBInst_0)) - (portRef (member wb_dato 4)) - )) - (net (rename wb_dato_2 "wb_dato[2]") (joined - (portRef WBDATO2 (instanceRef EFBInst_0)) - (portRef (member wb_dato 5)) - )) - (net (rename wb_dato_1 "wb_dato[1]") (joined - (portRef WBDATO1 (instanceRef EFBInst_0)) - (portRef (member wb_dato 6)) - )) - (net (rename wb_dato_0 "wb_dato[0]") (joined - (portRef WBDATO0 (instanceRef EFBInst_0)) - (portRef (member wb_dato 7)) - )) - (net wb_ack (joined - (portRef WBACKO (instanceRef EFBInst_0)) - (portRef wb_ack) - )) - (net PLLCLKO (joined - (portRef PLLCLKO (instanceRef EFBInst_0)) - )) - (net PLLRSTO (joined - (portRef PLLRSTO (instanceRef EFBInst_0)) - )) - (net PLL0STBO (joined - (portRef PLL0STBO (instanceRef EFBInst_0)) - )) - (net PLL1STBO (joined - (portRef PLL1STBO (instanceRef EFBInst_0)) - )) - (net PLLWEO (joined - (portRef PLLWEO (instanceRef EFBInst_0)) - )) - (net PLLADRO4 (joined - (portRef PLLADRO4 (instanceRef EFBInst_0)) - )) - (net PLLADRO3 (joined - (portRef PLLADRO3 (instanceRef EFBInst_0)) - )) - (net PLLADRO2 (joined - (portRef PLLADRO2 (instanceRef EFBInst_0)) - )) - (net PLLADRO1 (joined - (portRef PLLADRO1 (instanceRef EFBInst_0)) - )) - (net PLLADRO0 (joined - (portRef PLLADRO0 (instanceRef EFBInst_0)) - )) - (net PLLDATO7 (joined - (portRef PLLDATO7 (instanceRef EFBInst_0)) - )) - (net PLLDATO6 (joined - (portRef PLLDATO6 (instanceRef EFBInst_0)) - )) - (net PLLDATO5 (joined - (portRef PLLDATO5 (instanceRef EFBInst_0)) - )) - (net PLLDATO4 (joined - (portRef PLLDATO4 (instanceRef EFBInst_0)) - )) - (net PLLDATO3 (joined - (portRef PLLDATO3 (instanceRef EFBInst_0)) - )) - (net PLLDATO2 (joined - (portRef PLLDATO2 (instanceRef EFBInst_0)) - )) - (net PLLDATO1 (joined - (portRef PLLDATO1 (instanceRef EFBInst_0)) - )) - (net PLLDATO0 (joined - (portRef PLLDATO0 (instanceRef EFBInst_0)) - )) - (net I2C1SCLO (joined - (portRef I2C1SCLO (instanceRef EFBInst_0)) - )) - (net I2C1SCLOEN (joined - (portRef I2C1SCLOEN (instanceRef EFBInst_0)) - )) - (net I2C1SDAO (joined - (portRef I2C1SDAO (instanceRef EFBInst_0)) - )) - (net I2C1SDAOEN (joined - (portRef I2C1SDAOEN (instanceRef EFBInst_0)) - )) - (net I2C2SCLO (joined - (portRef I2C2SCLO (instanceRef EFBInst_0)) - )) - (net I2C2SCLOEN (joined - (portRef I2C2SCLOEN (instanceRef EFBInst_0)) - )) - (net I2C2SDAO (joined - (portRef I2C2SDAO (instanceRef EFBInst_0)) - )) - (net I2C2SDAOEN (joined - (portRef I2C2SDAOEN (instanceRef EFBInst_0)) - )) - (net I2C1IRQO (joined - (portRef I2C1IRQO (instanceRef EFBInst_0)) - )) - (net I2C2IRQO (joined - (portRef I2C2IRQO (instanceRef EFBInst_0)) - )) - (net SPISCKO (joined - (portRef SPISCKO (instanceRef EFBInst_0)) - )) - (net SPISCKEN (joined - (portRef SPISCKEN (instanceRef EFBInst_0)) - )) - (net SPIMISOO (joined - (portRef SPIMISOO (instanceRef EFBInst_0)) - )) - (net SPIMISOEN (joined - (portRef SPIMISOEN (instanceRef EFBInst_0)) - )) - (net SPIMOSIO (joined - (portRef SPIMOSIO (instanceRef EFBInst_0)) - )) - (net SPIMOSIEN (joined - (portRef SPIMOSIEN (instanceRef EFBInst_0)) - )) - (net SPIMCSN0 (joined - (portRef SPIMCSN0 (instanceRef EFBInst_0)) - )) - (net SPIMCSN1 (joined - (portRef SPIMCSN1 (instanceRef EFBInst_0)) - )) - (net SPIMCSN2 (joined - (portRef SPIMCSN2 (instanceRef EFBInst_0)) - )) - (net SPIMCSN3 (joined - (portRef SPIMCSN3 (instanceRef EFBInst_0)) - )) - (net SPIMCSN4 (joined - (portRef SPIMCSN4 (instanceRef EFBInst_0)) - )) - (net SPIMCSN5 (joined - (portRef SPIMCSN5 (instanceRef EFBInst_0)) - )) - (net SPIMCSN6 (joined - (portRef SPIMCSN6 (instanceRef EFBInst_0)) - )) - (net SPIMCSN7 (joined - (portRef SPIMCSN7 (instanceRef EFBInst_0)) - )) - (net SPICSNEN (joined - (portRef SPICSNEN (instanceRef EFBInst_0)) - )) - (net SPIIRQO (joined - (portRef SPIIRQO (instanceRef EFBInst_0)) - )) - (net TCINT (joined - (portRef TCINT (instanceRef EFBInst_0)) - )) - (net TCOC (joined - (portRef TCOC (instanceRef EFBInst_0)) - )) - (net wbc_ufm_irq (joined - (portRef WBCUFMIRQ (instanceRef EFBInst_0)) - )) - (net CFGWAKE (joined - (portRef CFGWAKE (instanceRef EFBInst_0)) - )) - (net CFGSTDBY (joined - (portRef CFGSTDBY (instanceRef EFBInst_0)) - )) - ) - (property NGD_DRC_MASK (integer 1)) - (property orig_inst_of (string "REFB")) - ) - ) - (cell RAM2E_UFM (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename ra_35 "RA_35[11:0]") 12) (direction OUTPUT)) - (port (array (rename ain_c "Ain_c[7:0]") 8) (direction INPUT)) - (port CmdTout_3_0 (direction OUTPUT)) - (port (array (rename rwbank "RWBank[7:0]") 8) (direction INPUT)) - (port (array (rename fs "FS[15:0]") 16) (direction INPUT)) - (port (array (rename ra "RA[11:0]") 12) (direction INPUT)) - (port (array (rename rc_3 "RC_3[2:1]") 2) (direction OUTPUT)) - (port (array (rename rwbank_3 "RWBank_3[7:0]") 8) (direction OUTPUT)) - (port (array (rename din_c "Din_c[7:0]") 8) (direction INPUT)) - (port S_s_0_0_0 (direction OUTPUT)) - (port (array (rename ba_4 "BA_4[1:0]") 2) (direction OUTPUT)) - (port (array (rename cs "CS[2:0]") 3) (direction INPUT)) - (port (array (rename cmdtout "CmdTout[2:1]") 2) (direction INPUT)) - (port (array (rename rc "RC[2:1]") 2) (direction INPUT)) - (port (array (rename s "S[3:0]") 4) (direction INPUT)) - (port N_359_i (direction OUTPUT)) - (port CmdRWMaskSet_3 (direction OUTPUT)) - (port CmdLEDSet_3 (direction OUTPUT)) - (port N_667 (direction OUTPUT)) - (port N_666 (direction OUTPUT)) - (port N_665 (direction OUTPUT)) - (port N_664 (direction OUTPUT)) - (port N_663 (direction OUTPUT)) - (port N_662 (direction OUTPUT)) - (port N_648 (direction OUTPUT)) - (port CmdSetRWBankFFLED (direction INPUT)) - (port CmdLEDGet (direction INPUT)) - (port Vout3 (direction OUTPUT)) - (port un9_VOEEN_0_a2_0_a3_0_a3_1z (direction OUTPUT)) - (port N_263_i_1z (direction OUTPUT)) - (port N_508 (direction OUTPUT)) - (port RWSel_2 (direction OUTPUT)) - (port nC07X_c (direction INPUT)) - (port RDOE_i_1z (direction OUTPUT)) - (port LED_c (direction OUTPUT)) - (port Ready (direction INPUT)) - (port nDOE_c (direction OUTPUT)) - (port DOEEN (direction INPUT)) - (port nEN80_c (direction INPUT)) - (port N_360_i_1z (direction OUTPUT)) - (port N_368_i_1z (direction OUTPUT)) - (port N_507_i_1z (direction OUTPUT)) - (port un2_S_2_i_0_0_o3_RNIHFHN3_1z (direction OUTPUT)) - (port CmdLEDGet_3 (direction OUTPUT)) - (port N_126 (direction OUTPUT)) - (port N_362_i (direction OUTPUT)) - (port N_369_i_1z (direction OUTPUT)) - (port Ready3 (direction OUTPUT)) - (port CmdSetRWBankFFLED_4 (direction OUTPUT)) - (port N_361_i (direction OUTPUT)) - (port N_223 (direction OUTPUT)) - (port CmdLEDSet (direction INPUT)) - (port CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_1z (direction OUTPUT)) - (port CmdRWMaskSet (direction INPUT)) - (port CmdExecMXO2_3_0_a3_0_RNI6S1P8_1z (direction OUTPUT)) - (port N_370_i (direction OUTPUT)) - (port nWE_c (direction INPUT)) - (port N_358_i (direction OUTPUT)) - (port un1_CS_0_sqmuxa_i (direction OUTPUT)) - (port N_547_i (direction OUTPUT)) - (port C14M_c (direction INPUT)) - (port CO0_0 (direction INPUT)) - (port N_187_i_1z (direction OUTPUT)) - (port N_185_i (direction OUTPUT)) - (port CKE_7_RNIS77M1_1z (direction OUTPUT)) - (port N_372_i (direction OUTPUT)) - (port S_1 (direction INPUT)) - (port RWSel (direction INPUT)) - (port N_201_i_1z (direction OUTPUT)) - (port N_225_i_1z (direction OUTPUT)) - (port BA_0_sqmuxa (direction OUTPUT)) - (port CO0_1 (direction INPUT)) - (port RC12 (direction OUTPUT)) - (port N_551 (direction OUTPUT)) - ) - (contents - (instance wb_rst16_i_i_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) - ) - (instance (rename wb_dati_7_0_0_0_RNO_7 "wb_dati_7_0_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A))+D (B A))")) - ) - (instance nRAS_s_i_0_a3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A))")) - ) - (instance un1_RC12_i_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B+A))")) - ) - (instance (rename wb_dati_7_0_0_a3_3_4 "wb_dati_7_0_0_a3_3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B !A)))")) - ) - (instance (rename RA_35_2_0_a3_5_10 "RA_35_2_0_a3_5[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)))")) - ) - (instance (rename un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0 "un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B A)))")) - ) - (instance (rename wb_dati_7_0_0_0_0_RNO_7 "wb_dati_7_0_0_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B !A)))")) - ) - (instance (rename S_s_0_0_RNO_0 "S_s_0_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C !A)")) - ) - (instance CKE_7_m1_0_0_o2_RNI7FOA1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance CKE_7_m1_0_0_o2_RNIGC501 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance (rename RC_3_0_0_1 "RC_3_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A+B !A)+C (B !A))")) - ) - (instance N_314_i_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(!B+!A)))")) - ) - (instance nRAS_s_i_0_a3_5_RNIH7J73 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)))")) - ) - (instance (rename wb_dati_7_0_0_a3_8_3 "wb_dati_7_0_0_a3_8[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B !A)))")) - ) - (instance CKE_7_m1_0_0_o2_RNICM8E1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance (rename S_r_i_0_o2_RNIP4KI1_1 "S_r_i_0_o2_RNIP4KI1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)))")) - ) - (instance nRAS_s_i_0_a3_5_RNIH7J73_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)))")) - ) - (instance N_225_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B+!A)))")) - ) - (instance N_201_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B+!A)))")) - ) - (instance (rename S_r_i_0_o2_RNIOGTF1_1 "S_r_i_0_o2_RNIOGTF1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C+(!B+!A)))")) - ) - (instance (rename RA_35_0_0_RNO_0 "RA_35_0_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) - ) - (instance (rename RA_35_2_0_RNO_10 "RA_35_2_0_RNO[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance (rename S_r_i_0_o2_RNIFNP81_0_2 "S_r_i_0_o2_RNIFNP81_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C A)+D (!C (!B+A)))")) - ) - (instance wb_req_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) - ) - (instance CmdBitbangMXO2_RNINSM62 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B+C (B+A))+D B)")) - ) - (instance wb_we_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B+C (B+A))+D B)")) - ) - (instance (rename wb_dati_7_0_0_a3_13_RNI81UL_7 "wb_dati_7_0_0_a3_13_RNI81UL[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) - ) - (instance CKE_7_RNIS77M1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B+A)+C A)+D A)")) - ) - (instance (rename S_r_i_0_o2_RNIBAU51_1 "S_r_i_0_o2_RNIBAU51[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A))")) - ) - (instance N_187_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B A)")) - ) - (instance un1_CS_0_sqmuxa_0_0_0 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) - (instance un1_CS_0_sqmuxa_0_0_0_bm (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C !A+C (B+!A))+D !A)")) - ) - (instance un1_CS_0_sqmuxa_0_0_0_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C+(!B+!A))")) - ) - (instance wb_we (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance wb_rst (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance wb_req (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_0 "wb_dati[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_1 "wb_dati[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_2 "wb_dati[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_3 "wb_dati[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_4 "wb_dati[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_5 "wb_dati[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_6 "wb_dati[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_dati_7 "wb_dati[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance wb_cyc_stb (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_0 "wb_adr[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_1 "wb_adr[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_2 "wb_adr[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_3 "wb_adr[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_4 "wb_adr[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_5 "wb_adr[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_6 "wb_adr[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename wb_adr_7 "wb_adr[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_0 "RWMask[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_1 "RWMask[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_2 "RWMask[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_3 "RWMask[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_4 "RWMask[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_5 "RWMask[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_6 "RWMask[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_7 "RWMask[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdSetRWBankFFChip (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdExecMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdBitbangMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename S_r_i_0_o2_RNIVM0LF_1 "S_r_i_0_o2_RNIVM0LF[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B+A))")) - ) - (instance un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance (rename S_r_i_0_o2_RNI3VQTC_1 "S_r_i_0_o2_RNI3VQTC[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B !A)))")) - ) - (instance (rename wb_adr_7_i_i_0 "wb_adr_7_i_i[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B A)))")) - ) - (instance un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (!B A))+D (C A))")) - ) - (instance nRAS_s_i_0_0_RNI0PC64 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance nCAS_s_i_0_a3_RNIO1UQ3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A))+D (!B !A))")) - ) - (instance (rename wb_dati_7_0_0_5 "wb_dati_7_0_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_2 "wb_dati_7_0_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_0_7 "wb_dati_7_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) - ) - (instance CmdExecMXO2_3_0_a3_0_RNI6S1P8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C (B !A)+C !A))")) - ) - (instance (rename wb_dati_7_0_0_6 "wb_dati_7_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_4 "wb_dati_7_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) - ) - (instance un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C !B)+D (!C (!B !A)+C !B))")) - ) - (instance un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C (!B !A)))")) - ) - (instance (rename un1_RWMask_0_sqmuxa_1_i_0_0_0 "un1_RWMask_0_sqmuxa_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B A)+D (C+(!B A)))")) - ) - (instance (rename wb_dati_7_0_0_0_0 "wb_dati_7_0_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_1 "wb_dati_7_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A+B !A)+C B)+D (!C (B !A)+C B))")) - ) - (instance (rename wb_dati_7_0_0_0_3 "wb_dati_7_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance (rename wb_adr_7_i_i_4_0 "wb_adr_7_i_i_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) - ) - (instance (rename wb_adr_7_i_i_5_0 "wb_adr_7_i_i_5[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(B !A)))")) - ) - (instance un1_CS_0_sqmuxa_0_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B+!A)+C (B A))")) - ) - (instance un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C (!B !A)))")) - ) - (instance (rename un1_LEDEN_0_sqmuxa_1_i_0_0_0 "un1_LEDEN_0_sqmuxa_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B A)+D (C+(!B A)))")) - ) - (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B !A))+D (C+!A))")) - ) - (instance (rename wb_dati_7_0_0_RNO_0_7 "wb_dati_7_0_0_RNO_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D (!C (B A)+C B))")) - ) - (instance (rename wb_dati_7_0_0_0_a3_7 "wb_dati_7_0_0_0_a3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B !A+B A)))")) - ) - (instance (rename wb_adr_7_i_i_a3_6_0 "wb_adr_7_i_i_a3_6[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B A))")) - ) - (instance (rename RA_35_0_0_0_7 "RA_35_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B A))")) - ) - (instance (rename RA_35_0_0_0_6 "RA_35_0_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B A))")) - ) - (instance (rename RA_35_0_0_4 "RA_35_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B A))")) - ) - (instance (rename RA_35_0_0_3 "RA_35_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B A))")) - ) - (instance (rename wb_dati_7_0_0_a3_2_4 "wb_dati_7_0_0_a3_2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B !A)))")) - ) - (instance CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C A)+D (!C (!B A)+C A))")) - ) - (instance (rename wb_dati_7_0_0_0_0_3 "wb_dati_7_0_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_0_6 "wb_dati_7_0_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_0_4 "wb_dati_7_0_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B A)+D (C+(B A)))")) - ) - (instance CKE_7_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A))")) - ) - (instance CKE_7 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) - (instance wb_cyc_stb_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C A+C (B+A))")) - ) - (instance CmdExecMXO2_3_0_a3_0_RNIPG3P2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C (!B A)))")) - ) - (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)+C B)+D B)")) - ) - (instance nRAS_s_i_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B !A))+D !A)")) - ) - (instance nCAS_s_i_0_a3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (B !A)+C !A))")) - ) - (instance (rename wb_dati_7_0_0_a3_4 "wb_dati_7_0_0_a3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (B !A))")) - ) - (instance (rename RA_35_i_i_0_1 "RA_35_i_i_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B A)))")) - ) - (instance (rename RA_35_0_0_2 "RA_35_0_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B A)))")) - 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(libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)))")) - ) - (instance (rename RA_35_0_0_0_4 "RA_35_0_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B A)+D (C+(B A)))")) - ) - (instance (rename RA_35_0_0_0_0_6 "RA_35_0_0_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B A)+D (C+(B A)))")) - ) - (instance (rename RA_35_0_0_0_0_7 "RA_35_0_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B A)+D (C+(B A)))")) - ) - (instance (rename RA_35_0_0_0_3 "RA_35_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B A)+D (C+(B A)))")) - ) - (instance (rename wb_dati_7_0_0_0_1 "wb_dati_7_0_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_0_0_7 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RAout_pad_11 "RAout_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_10 "RAout_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_9 "RAout_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_8 "RAout_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_7 "RAout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_6 "RAout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_5 "RAout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_4 "RAout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_3 "RAout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_2 "RAout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_1 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Vout_pad_5 "Vout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_4 "Vout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_3 "Vout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_2 "Vout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_1 "Vout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_0 "Vout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance nDOE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef 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nEN80_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance nWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance PHI1_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance C14M_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance nVOE_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+A)")) - ) - (instance (rename SZ0Z_1 "S_1") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B A))")) - ) - (instance (rename FS_s_0_15 "FS_s_0[15]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x5002")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_13 "FS_cry_0[13]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_11 "FS_cry_0[11]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_9 "FS_cry_0[9]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_7 "FS_cry_0[7]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_5 "FS_cry_0[5]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_3 "FS_cry_0[3]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_1 "FS_cry_0[1]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance ram2e_ufm (viewRef netlist (cellRef RAM2E_UFM)) - ) - (net un9_VOEEN_0_a2_0_a3_0_a3 (joined - (portRef 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a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.mrp +++ /dev/null @@ -1,468 +0,0 @@ - - Lattice Mapping Report File for Design Module 'RAM2E' - - -Design Information ------------------- - -Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial - RAM2E_LCMXO2_1200HC_impl1.ngd -o RAM2E_LCMXO2_1200HC_impl1_map.ncd -pr - RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/ - iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synpl - ify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui - -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml -Target Vendor: LATTICE -Target Device: LCMXO2-1200HCTQFP100 -Target Performance: 4 -Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 12/28/23 23:23:27 - -Design Summary --------------- - - Number of registers: 122 out of 1520 (8%) - PFU registers: 93 out of 1280 (7%) - PIO registers: 29 out of 240 (12%) - Number of SLICEs: 148 out of 640 (23%) - SLICEs as Logic/ROM: 148 out of 640 (23%) - SLICEs as RAM: 0 out of 480 (0%) - SLICEs as Carry: 9 out of 640 (1%) - Number of LUT4s: 296 out of 1280 (23%) - Number used as logic LUTs: 278 - Number used as distributed RAM: 0 - Number used as ripple logic: 18 - Number used as shift registers: 0 - Number of PIO sites used: 69 + 4(JTAG) out of 80 (91%) - Number of block RAMs: 0 out of 7 (0%) - Number of GSRs: 0 out of 1 (0%) - EFB used : Yes - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - POR : On - Bandgap : On - Number of Power Controller: 0 out of 1 (0%) - Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) - Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) - Number of DCCA: 0 out of 8 (0%) - Number of DCMA: 0 out of 2 (0%) - Number of PLLs: 0 out of 1 (0%) - Number of DQSDLLs: 0 out of 2 (0%) - Number of CLKDIVC: 0 out of 4 (0%) - Number of ECLKSYNCA: 0 out of 4 (0%) - Number of ECLKBRIDGECS: 0 out of 2 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of - distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and - ripple logic. - Number of clocks: 1 - Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M ) - Number of Clock Enables: 14 - - Page 1 - - - - -Design: RAM2E Date: 12/28/23 23:23:27 - -Design Summary (cont) ---------------------- - Net N_225_i: 2 loads, 0 LSLICEs - Net N_201_i: 2 loads, 0 LSLICEs - Net N_187_i: 11 loads, 11 LSLICEs - Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs - Net RC12: 2 loads, 2 LSLICEs - Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs - Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs - Net N_185_i: 2 loads, 2 LSLICEs - Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs - Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs - Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs - Net N_126: 6 loads, 6 LSLICEs - Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs - Net Vout3: 8 loads, 0 LSLICEs - Number of LSRs: 7 - Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs - Net BA_0_sqmuxa: 2 loads, 0 LSLICEs - Net S[2]: 1 loads, 1 LSLICEs - Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs - Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs - Net N_1080_0: 1 loads, 1 LSLICEs - Net N_1078_0: 1 loads, 1 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net S[2]: 50 loads - Net S[3]: 45 loads - Net S[0]: 37 loads - Net S[1]: 34 loads - Net FS[12]: 24 loads - Net FS[11]: 22 loads - Net FS[10]: 19 loads - Net FS[13]: 19 loads - Net FS[9]: 19 loads - Net FS[8]: 18 loads - - - - - Number of warnings: 3 - Number of errors: 0 - - -Design Errors/Warnings ----------------------- - -WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(93): Semantic - error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port - "nWE80" does not exist in the design. This preference has been disabled. -WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will - temporarily disable certain features of the device including Power - Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port. - Functionality is restored after the Flash Memory (UFM/Configuration) - Interface is disabled using Disable Configuration Interface command 0x26 - followed by Bypass command 0xFF. -WARNING - map: IO buffer missing for top level port nWE80...logic will be - discarded. - - Page 2 - - - - -Design: RAM2E Date: 12/28/23 23:23:27 - - -IO (PIO) Attributes -------------------- - -+---------------------+-----------+-----------+------------+ -| IO Name | Direction | Levelmode | IO | -| | | IO_TYPE | Register | -+---------------------+-----------+-----------+------------+ -| RD[0] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| LED | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| C14M | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[7] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[6] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[5] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[4] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[3] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[2] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[1] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| DQMH | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| DQML | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[11] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[10] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[9] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[8] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[7] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[6] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[5] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[4] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[3] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[2] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[1] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[0] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| BA[1] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ - - Page 3 - - - - -Design: RAM2E Date: 12/28/23 23:23:27 - -IO (PIO) Attributes (cont) --------------------------- -| BA[0] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nRWEout | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nCASout | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nRASout | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nCSout | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| CKEout | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nVOE | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Vout[7] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[6] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[5] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[4] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[3] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[2] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[1] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[0] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nDOE | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[7] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[6] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[5] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[4] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[3] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[2] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[1] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[0] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[7] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[6] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[5] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[4] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ - - Page 4 - - - - -Design: RAM2E Date: 12/28/23 23:23:27 - -IO (PIO) Attributes (cont) --------------------------- -| Din[3] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[2] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[1] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[0] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[7] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[6] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[5] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[4] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[3] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[2] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[1] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[0] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| nC07X | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| nEN80 | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| nWE | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| PHI1 | INPUT | LVCMOS33 | IN | -+---------------------+-----------+-----------+------------+ - -Removed logic -------------- - -Block GSR_INST undriven or does not drive anything - clipped. -Block ram2e_ufm/VCC undriven or does not drive anything - clipped. -Block ram2e_ufm/GND undriven or does not drive anything - clipped. -Signal CKEout.CN was merged into signal C14M_c -Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped. -Signal FS_s_0_S1[15] undriven or does not drive anything - clipped. -Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything - - clipped. -Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped. - - Page 5 - - - - -Design: RAM2E Date: 12/28/23 23:23:27 - -Removed logic (cont) --------------------- -Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped. - -Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped. - -Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything - - clipped. -Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything - - clipped. -Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything - - clipped. -Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything - - clipped. -Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped. -Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped. -Signal N_1 undriven or does not drive anything - clipped. -Block nCASout.CN was optimized away. -Block ram2e_ufm/ufmefb/VCC was optimized away. -Block ram2e_ufm/ufmefb/GND was optimized away. - - - -Embedded Functional Block Connection Summary --------------------------------------------- - - Desired WISHBONE clock frequency: 14.4 MHz - - Page 6 - - - - -Design: RAM2E Date: 12/28/23 23:23:27 - -Embedded Functional Block Connection Summary (cont) ---------------------------------------------------- - Clock source: C14M_c - Reset source: ram2e_ufm/wb_rst - Functions mode: - I2C #1 (Primary) Function: DISABLED - I2C #2 (Secondary) Function: DISABLED - SPI Function: DISABLED - Timer/Counter Function: DISABLED - Timer/Counter Mode: WB - UFM Connection: ENABLED - PLL0 Connection: DISABLED - PLL1 Connection: DISABLED - I2C Function Summary: - -------------------- - None - SPI Function Summary: - -------------------- - None - Timer/Counter Function Summary: - ------------------------------ - None - UFM Function Summary: - -------------------- - UFM Utilization: General Purpose Flash Memory - Initialized UFM Pages: 321 Pages (321*128 Bits) - Available General - Purpose Flash Memory: 511 Pages (511*128 Bits) - - EBR Blocks with Unique - Initialization Data: 0 - - WID EBR Instance - --- ------------ - - -ASIC Components ---------------- - -Instance Name: ram2e_ufm/ufmefb/EFBInst_0 - Type: EFB - -Run Time and Memory Usage -------------------------- - - Total CPU Time: 0 secs - Total REAL Time: 0 secs - Peak Memory Usage: 64 MB - - - - - - - - - - - - Page 7 - - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. - Copyright (c) 1995 AT&T Corp. All rights reserved. - Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. - Copyright (c) 2001 Agere Systems All rights reserved. - Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights - reserved. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.pad b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.pad deleted file mode 100644 index ab624a7..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.pad +++ /dev/null @@ -1,313 +0,0 @@ -PAD Specification File -*************************** - -PART TYPE: LCMXO2-1200HC -Performance Grade: 4 -PACKAGE: TQFP100 -Package Status: Final Version 1.44 - -Thu Dec 28 23:23:38 2023 - -Pinout by Port Name: -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ -| Ain[0] | 3/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[1] | 2/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[2] | 7/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[3] | 4/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[4] | 78/0 | LVCMOS33_IN | PT16C | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[5] | 84/0 | LVCMOS33_IN | PT15A | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[6] | 86/0 | LVCMOS33_IN | PT12C | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[7] | 8/3 | LVCMOS33_IN | PL3D | | | CLAMP:ON HYSTERESIS:SMALL | -| BA[0] | 58/1 | LVCMOS33_OUT | PR9A | | | DRIVE:4mA SLEW:SLOW | -| BA[1] | 60/1 | LVCMOS33_OUT | PR8C | | | DRIVE:4mA SLEW:SLOW | -| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL | -| CKEout | 53/1 | LVCMOS33_OUT | PR9D | | | DRIVE:4mA SLEW:SLOW | -| DQMH | 49/2 | LVCMOS33_OUT | PB20D | | | DRIVE:4mA SLEW:SLOW | -| DQML | 48/2 | LVCMOS33_OUT | PB20C | | | DRIVE:4mA SLEW:SLOW | -| Din[0] | 96/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[1] | 97/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[2] | 98/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[3] | 9/3 | LVCMOS33_IN | PL4A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[4] | 1/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[5] | 99/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[6] | 88/0 | LVCMOS33_IN | PT12A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[7] | 87/0 | LVCMOS33_IN | PT12B | | | CLAMP:ON HYSTERESIS:SMALL | -| Dout[0] | 30/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW | -| Dout[1] | 27/2 | LVCMOS33_OUT | PB4C | | | DRIVE:4mA SLEW:SLOW | -| Dout[2] | 25/3 | LVCMOS33_OUT | PL10D | | | DRIVE:4mA SLEW:SLOW | -| Dout[3] | 28/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW | -| Dout[4] | 24/3 | LVCMOS33_OUT | PL10C | | | DRIVE:4mA SLEW:SLOW | -| Dout[5] | 21/3 | LVCMOS33_OUT | PL9B | | | DRIVE:4mA SLEW:SLOW | -| Dout[6] | 31/2 | LVCMOS33_OUT | PB6C | | | DRIVE:4mA SLEW:SLOW | -| Dout[7] | 32/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW | -| LED | 35/2 | LVCMOS33_OUT | PB9B | | | DRIVE:4mA SLEW:SLOW | -| PHI1 | 85/0 | LVCMOS33_IN | PT12D | | | CLAMP:ON HYSTERESIS:SMALL | -| RAout[0] | 66/1 | LVCMOS33_OUT | PR4D | | | DRIVE:4mA SLEW:SLOW | -| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW | -| RAout[11] | 59/1 | LVCMOS33_OUT | PR8D | | | DRIVE:4mA SLEW:SLOW | -| RAout[1] | 68/1 | LVCMOS33_OUT | PR4B | | | DRIVE:4mA SLEW:SLOW | -| RAout[2] | 70/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW | -| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW | -| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW | -| RAout[5] | 71/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW | -| RAout[6] | 69/1 | LVCMOS33_OUT | PR4A | | | DRIVE:4mA SLEW:SLOW | -| RAout[7] | 67/1 | LVCMOS33_OUT | PR4C | | | DRIVE:4mA SLEW:SLOW | -| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW | -| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW | -| RD[0] | 36/2 | LVCMOS33_BIDI | PB11C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[1] | 37/2 | LVCMOS33_BIDI | PB11D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[2] | 38/2 | LVCMOS33_BIDI | PB11A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[3] | 39/2 | LVCMOS33_BIDI | PB11B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[4] | 40/2 | LVCMOS33_BIDI | PB15A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[5] | 41/2 | LVCMOS33_BIDI | PB15B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[6] | 42/2 | LVCMOS33_BIDI | PB18A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[7] | 43/2 | LVCMOS33_BIDI | PB18B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| Vout[0] | 18/3 | LVCMOS33_OUT | PL8C | | | DRIVE:4mA SLEW:SLOW | -| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW | -| Vout[2] | 17/3 | LVCMOS33_OUT | PL8B | | | DRIVE:4mA SLEW:SLOW | -| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW | -| Vout[4] | 19/3 | LVCMOS33_OUT | PL8D | | | DRIVE:4mA SLEW:SLOW | -| Vout[5] | 16/3 | LVCMOS33_OUT | PL8A | | | DRIVE:4mA SLEW:SLOW | -| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW | -| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW | -| nC07X | 34/2 | LVCMOS33_IN | PB9A | | | CLAMP:ON HYSTERESIS:SMALL | -| nCASout | 52/1 | LVCMOS33_OUT | PR10C | | | DRIVE:4mA SLEW:SLOW | -| nCSout | 57/1 | LVCMOS33_OUT | PR9B | | | DRIVE:4mA SLEW:SLOW | -| nDOE | 20/3 | LVCMOS33_OUT | PL9A | | | DRIVE:4mA SLEW:SLOW | -| nEN80 | 82/0 | LVCMOS33_IN | PT15C | | | CLAMP:ON HYSTERESIS:SMALL | -| nRASout | 54/1 | LVCMOS33_OUT | PR9C | | | DRIVE:4mA SLEW:SLOW | -| nRWEout | 51/1 | LVCMOS33_OUT | PR10D | | | DRIVE:4mA SLEW:SLOW | -| nVOE | 10/3 | LVCMOS33_OUT | PL4B | | | DRIVE:4mA SLEW:SLOW | -| nWE | 29/2 | LVCMOS33_IN | PB6A | | | CLAMP:ON HYSTERESIS:SMALL | -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 3.3V | -| 1 | 3.3V | -| 2 | 3.3V | -| 3 | 3.3V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2C | L_GPLLT_IN | | | -| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2D | L_GPLLC_IN | | | -| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL3A | PCLKT3_2 | | | -| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL3B | PCLKC3_2 | | | -| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3C | | | | -| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3D | | | | -| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL4A | | | | -| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL4B | | | | -| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | | -| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | | -| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | | -| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | | -| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL8A | | | | -| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL8B | | | | -| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL8C | | | | -| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL8D | | | | -| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL9A | PCLKT3_0 | | | -| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL9B | PCLKC3_0 | | | -| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL10C | | | | -| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL10D | | | | -| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4C | CSSPIN | | | -| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4D | | | | -| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB6A | | | | -| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB6B | | | | -| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6C | MCLK/CCLK | | | -| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6D | SO/SPISO | | | -| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB9A | PCLKT2_0 | | | -| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB9B | PCLKC2_0 | | | -| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB11C | | | | -| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB11D | | | | -| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB11A | PCLKT2_1 | | | -| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB11B | PCLKC2_1 | | | -| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB15A | | | | -| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB15B | | | | -| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB18A | | | | -| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB18B | | | | -| 45/2 | unused, PULL:DOWN | | | PB18C | | | | -| 47/2 | unused, PULL:DOWN | | | PB18D | | | | -| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB20C | SN | | | -| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB20D | SI/SISPI | | | -| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR10D | DQ1 | | | -| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR10C | DQ1 | | | -| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR9D | DQ1 | | | -| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR9C | DQ1 | | | -| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR9B | DQ1 | | | -| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR9A | DQ1 | | | -| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR8D | DQ1 | | | -| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR8C | DQ1 | | | -| 61/1 | unused, PULL:DOWN | | | PR8A | DQS1 | | | -| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0/DQ0 | | | -| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0/DQ0 | | | -| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | DQS0N | | | -| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | DQS0 | | | -| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR4D | DQ0 | | | -| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR4C | DQ0 | | | -| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR4B | DQ0 | | | -| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR4A | DQ0 | | | -| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR3B | DQ0 | | | -| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR3A | DQ0 | | | -| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | DQ0 | | | -| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | DQ0 | | | -| 76/0 | unused, PULL:DOWN | | | PT17D | DONE | | | -| 77/0 | unused, PULL:DOWN | | | PT17C | INITN | | | -| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT16C | | | | -| 81/0 | unused, PULL:DOWN | | | PT15D | PROGRAMN | | | -| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT15C | JTAGENB | | | -| 83/0 | unused, PULL:DOWN | | | PT15B | | | | -| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT15A | | | | -| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT12D | SDA/PCLKC0_0 | | | -| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT12C | SCL/PCLKT0_0 | | | -| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT12B | PCLKC0_1 | | | -| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT12A | PCLKT0_1 | | | -| 90/0 | Reserved: sysCONFIG | | | PT11D | TMS | | | -| 91/0 | Reserved: sysCONFIG | | | PT11C | TCK | | | -| 94/0 | Reserved: sysCONFIG | | | PT10D | TDI | | | -| 95/0 | Reserved: sysCONFIG | | | PT10C | TDO | | | -| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT10B | | | | -| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT10A | | | | -| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT9B | | | | -| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT9A | | | | -| PB4A/2 | unused, PULL:DOWN | | | PB4A | | | | -| PB4B/2 | unused, PULL:DOWN | | | PB4B | | | | -| PB9C/2 | unused, PULL:DOWN | | | PB9C | | | | -| PB9D/2 | unused, PULL:DOWN | | | PB9D | | | | -| PB15C/2 | unused, PULL:DOWN | | | PB15C | | | | -| PB15D/2 | unused, PULL:DOWN | | | PB15D | | | | -| PB20A/2 | unused, PULL:DOWN | | | PB20A | | | | -| PB20B/2 | unused, PULL:DOWN | | | PB20B | | | | -| PL2A/3 | unused, PULL:DOWN | | | PL2A | L_GPLLT_FB | | | -| PL2B/3 | unused, PULL:DOWN | | | PL2B | L_GPLLC_FB | | | -| PL4C/3 | unused, PULL:DOWN | | | PL4C | | | | -| PL4D/3 | unused, PULL:DOWN | | | PL4D | | | | -| PL10A/3 | unused, PULL:DOWN | | | PL10A | | | | -| PL10B/3 | unused, PULL:DOWN | | | PL10B | | | | -| PR2C/1 | unused, PULL:DOWN | | | PR2C | DQ0 | | | -| PR2D/1 | unused, PULL:DOWN | | | PR2D | DQ0 | | | -| PR8B/1 | unused, PULL:DOWN | | | PR8B | DQS1N | | | -| PR10A/1 | unused, PULL:DOWN | | | PR10A | DQ1 | | | -| PR10B/1 | unused, PULL:DOWN | | | PR10B | DQ1 | | | -| PT9C/0 | unused, PULL:DOWN | | | PT9C | | | | -| PT9D/0 | unused, PULL:DOWN | | | PT9D | | | | -| PT11A/0 | unused, PULL:DOWN | | | PT11A | | | | -| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | -| PT16A/0 | unused, PULL:DOWN | | | PT16A | | | | -| PT16B/0 | unused, PULL:DOWN | | | PT16B | | | | -| PT16D/0 | unused, PULL:DOWN | | | PT16D | | | | -| PT17A/0 | unused, PULL:DOWN | | | PT17A | | | | -| PT17B/0 | unused, PULL:DOWN | | | PT17B | | | | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ - -sysCONFIG Pins: -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| PT11D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | -| PT11C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | -| PT10D | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | -| PT10C | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | -+----------+--------------------+--------------------+----------+-------------+-------------------+ - -Dedicated sysCONFIG Pins: - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "Ain[0]" SITE "3"; -LOCATE COMP "Ain[1]" SITE "2"; -LOCATE COMP "Ain[2]" SITE "7"; -LOCATE COMP "Ain[3]" SITE "4"; -LOCATE COMP "Ain[4]" SITE "78"; -LOCATE COMP "Ain[5]" SITE "84"; -LOCATE COMP "Ain[6]" SITE "86"; -LOCATE COMP "Ain[7]" SITE "8"; -LOCATE COMP "BA[0]" SITE "58"; -LOCATE COMP "BA[1]" SITE "60"; -LOCATE COMP "C14M" SITE "62"; -LOCATE COMP "CKEout" SITE "53"; -LOCATE COMP "DQMH" SITE "49"; -LOCATE COMP "DQML" SITE "48"; -LOCATE COMP "Din[0]" SITE "96"; -LOCATE COMP "Din[1]" SITE "97"; -LOCATE COMP "Din[2]" SITE "98"; -LOCATE COMP "Din[3]" SITE "9"; -LOCATE COMP "Din[4]" SITE "1"; -LOCATE COMP "Din[5]" SITE "99"; -LOCATE COMP "Din[6]" SITE "88"; -LOCATE COMP "Din[7]" SITE "87"; -LOCATE COMP "Dout[0]" SITE "30"; -LOCATE COMP "Dout[1]" SITE "27"; -LOCATE COMP "Dout[2]" SITE "25"; -LOCATE COMP "Dout[3]" SITE "28"; -LOCATE COMP "Dout[4]" SITE "24"; -LOCATE COMP "Dout[5]" SITE "21"; -LOCATE COMP "Dout[6]" SITE "31"; -LOCATE COMP "Dout[7]" SITE "32"; -LOCATE COMP "LED" SITE "35"; -LOCATE COMP "PHI1" SITE "85"; -LOCATE COMP "RAout[0]" SITE "66"; -LOCATE COMP "RAout[10]" SITE "64"; -LOCATE COMP "RAout[11]" SITE "59"; -LOCATE COMP "RAout[1]" SITE "68"; -LOCATE COMP "RAout[2]" SITE "70"; -LOCATE COMP "RAout[3]" SITE "74"; -LOCATE COMP "RAout[4]" SITE "75"; -LOCATE COMP "RAout[5]" SITE "71"; -LOCATE COMP "RAout[6]" SITE "69"; -LOCATE COMP "RAout[7]" SITE "67"; -LOCATE COMP "RAout[8]" SITE "65"; -LOCATE COMP "RAout[9]" SITE "63"; -LOCATE COMP "RD[0]" SITE "36"; -LOCATE COMP "RD[1]" SITE "37"; -LOCATE COMP "RD[2]" SITE "38"; -LOCATE COMP "RD[3]" SITE "39"; -LOCATE COMP "RD[4]" SITE "40"; -LOCATE COMP "RD[5]" SITE "41"; -LOCATE COMP "RD[6]" SITE "42"; -LOCATE COMP "RD[7]" SITE "43"; -LOCATE COMP "Vout[0]" SITE "18"; -LOCATE COMP "Vout[1]" SITE "15"; -LOCATE COMP "Vout[2]" SITE "17"; -LOCATE COMP "Vout[3]" SITE "13"; -LOCATE COMP "Vout[4]" SITE "19"; -LOCATE COMP "Vout[5]" SITE "16"; -LOCATE COMP "Vout[6]" SITE "14"; -LOCATE COMP "Vout[7]" SITE "12"; -LOCATE COMP "nC07X" SITE "34"; -LOCATE COMP "nCASout" SITE "52"; -LOCATE COMP "nCSout" SITE "57"; -LOCATE COMP "nDOE" SITE "20"; -LOCATE COMP "nEN80" SITE "82"; -LOCATE COMP "nRASout" SITE "54"; -LOCATE COMP "nRWEout" SITE "51"; -LOCATE COMP "nVOE" SITE "10"; -LOCATE COMP "nWE" SITE "29"; - - - - - -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Dec 28 23:23:42 2023 - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.prf b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.prf deleted file mode 100644 index 1c72043..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.prf +++ /dev/null @@ -1,126 +0,0 @@ -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:23:28 2023 - -SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "LED" SITE "35" ; -LOCATE COMP "C14M" SITE "62" ; -LOCATE COMP "RD[7]" SITE "43" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "DQMH" SITE "49" ; -LOCATE COMP "DQML" SITE "48" ; -LOCATE COMP "RAout[11]" SITE "59" ; -LOCATE COMP "RAout[10]" SITE "64" ; -LOCATE COMP "RAout[9]" SITE "63" ; -LOCATE COMP "RAout[8]" SITE "65" ; -LOCATE COMP "RAout[7]" SITE "67" ; -LOCATE COMP "RAout[6]" SITE "69" ; -LOCATE COMP "RAout[5]" SITE "71" ; -LOCATE COMP "RAout[4]" SITE "75" ; -LOCATE COMP "RAout[3]" SITE "74" ; -LOCATE COMP "RAout[2]" SITE "70" ; -LOCATE COMP "RAout[1]" SITE "68" ; -LOCATE COMP "RAout[0]" SITE "66" ; -LOCATE COMP "BA[1]" SITE "60" ; -LOCATE COMP "BA[0]" SITE "58" ; -LOCATE COMP "nRWEout" SITE "51" ; -LOCATE COMP "nCASout" SITE "52" ; -LOCATE COMP "nRASout" SITE "54" ; -LOCATE COMP "nCSout" SITE "57" ; -LOCATE COMP "CKEout" SITE "53" ; -LOCATE COMP "nVOE" SITE "10" ; -LOCATE COMP "Vout[7]" SITE "12" ; -LOCATE COMP "Vout[6]" SITE "14" ; -LOCATE COMP "Vout[5]" SITE "16" ; -LOCATE COMP "Vout[4]" SITE "19" ; -LOCATE COMP "Vout[3]" SITE "13" ; -LOCATE COMP "Vout[2]" SITE "17" ; -LOCATE COMP "Vout[1]" SITE "15" ; -LOCATE COMP "Vout[0]" SITE "18" ; -LOCATE COMP "nDOE" SITE "20" ; -LOCATE COMP "Dout[7]" SITE "32" ; -LOCATE COMP "Dout[6]" SITE "31" ; -LOCATE COMP "Dout[5]" SITE "21" ; -LOCATE COMP "Dout[4]" SITE "24" ; -LOCATE COMP "Dout[3]" SITE "28" ; -LOCATE COMP "Dout[2]" SITE "25" ; -LOCATE COMP "Dout[1]" SITE "27" ; -LOCATE COMP "Dout[0]" SITE "30" ; -LOCATE COMP "Din[7]" SITE "87" ; -LOCATE COMP "Din[6]" SITE "88" ; -LOCATE COMP "Din[5]" SITE "99" ; -LOCATE COMP "Din[4]" SITE "1" ; -LOCATE COMP "Din[3]" SITE "9" ; -LOCATE COMP "Din[2]" SITE "98" ; -LOCATE COMP "Din[1]" SITE "97" ; -LOCATE COMP "Din[0]" SITE "96" ; -LOCATE COMP "Ain[7]" SITE "8" ; -LOCATE COMP "Ain[6]" SITE "86" ; -LOCATE COMP "Ain[5]" SITE "84" ; -LOCATE COMP "Ain[4]" SITE "78" ; -LOCATE COMP "Ain[3]" SITE "4" ; -LOCATE COMP "Ain[2]" SITE "7" ; -LOCATE COMP "Ain[1]" SITE "2" ; -LOCATE COMP "Ain[0]" SITE "3" ; -LOCATE COMP "nC07X" SITE "34" ; -LOCATE COMP "nEN80" SITE "82" ; -LOCATE COMP "nWE" SITE "29" ; -LOCATE COMP "PHI1" SITE "85" ; -FREQUENCY PORT "C14M" 14.300000 MHz ; -SCHEMATIC END ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -OUTPUT PORT "LED" LOAD 100.000000 pF ; -OUTPUT PORT "BA[1]" LOAD 5.000000 pF ; -OUTPUT PORT "BA[0]" LOAD 5.000000 pF ; -OUTPUT PORT "CKEout" LOAD 5.000000 pF ; -OUTPUT PORT "DQMH" LOAD 5.000000 pF ; -OUTPUT PORT "DQML" LOAD 5.000000 pF ; -OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ; -OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ; -OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[3]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ; -OUTPUT PORT "nCASout" LOAD 5.000000 pF ; -OUTPUT PORT "nCSout" LOAD 5.000000 pF ; -OUTPUT PORT "nDOE" LOAD 10.000000 pF ; -OUTPUT PORT "nRASout" LOAD 5.000000 pF ; -OUTPUT PORT "nRWEout" LOAD 5.000000 pF ; -OUTPUT PORT "nVOE" LOAD 10.000000 pF ; -OUTPUT PORT "RD[0]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[1]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[2]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[3]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[4]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[5]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[6]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[7]" LOAD 9.000000 pF ; -COMMERCIAL ; diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.srr b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.srr deleted file mode 100644 index 8b15111..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.srr +++ /dev/null @@ -1,696 +0,0 @@ -#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 -#install: C:\lscc\diamond\3.12\synpbase -#OS: Windows 8 6.2 -#Hostname: ZANEMACWIN11 - -# Thu Dec 28 23:23:19 2023 - -#Implementation: impl1 - - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ - -@N|Running in 64-bit mode -###########################################################[ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ - -@N|Running in 64-bit mode -@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) -@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) -@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work) -@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work) -@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work) -Verilog syntax check successful! -File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling -File \\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v changed - recompiling -Selecting top level module RAM2E -@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. -Running optimization stage 1 on VHI ....... -Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) -@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. -Running optimization stage 1 on VLO ....... -Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) -@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. -Running optimization stage 1 on EFB ....... -Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) -@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work. -Running optimization stage 1 on REFB ....... -Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) -@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work. -Running optimization stage 1 on RAM2E_UFM ....... -Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) -@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work. -Running optimization stage 1 on RAM2E ....... -Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) -Running optimization stage 2 on RAM2E ....... -@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused. -Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) -Running optimization stage 2 on RAM2E_UFM ....... -@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused. -Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -Running optimization stage 2 on REFB ....... -Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -Running optimization stage 2 on EFB ....... -Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -Running optimization stage 2 on VLO ....... -Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -Running optimization stage 2 on VHI ....... -Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Thu Dec 28 23:23:19 2023 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ - -@N|Running in 64-bit mode -File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\layer0.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Thu Dec 28 23:23:20 2023 - -###########################################################] - -For a summary of runtime and memory usage for all design units, please see file: -========================================================== -@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv - -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Thu Dec 28 23:23:20 2023 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ - -@N|Running in 64-bit mode -File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Thu Dec 28 23:23:21 2023 - -###########################################################] -# Thu Dec 28 23:23:21 2023 - - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) - - -Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB) - -Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc -@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt -See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt" -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB) - -@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2. -@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. -@N: FX493 |Applying initial value "0" on instance CmdExecMXO2. -@N: FX493 |Applying initial value "0" on instance PHI1r. -@N: FX493 |Applying initial value "0" on instance RWSel. -@N: FX493 |Applying initial value "0" on instance Ready. -@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0]. -@N: FX493 |Applying initial value "0" on instance CmdLEDGet. -@N: FX493 |Applying initial value "0" on instance CmdLEDSet. -@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet. -@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED. -@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP. -@N: FX493 |Applying initial value "1" on instance DQMH. -@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP. -@N: FX493 |Applying initial value "1" on instance DQML. -@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP. -@N: FX493 |Applying initial value "0000" on instance S[3:0]. -@N: FX493 |Applying initial value "1" on instance CKE. -@N: FX493 |Applying initial value "1" on instance nRWE. -@N: FX493 |Applying initial value "1" on instance nRWEout. -@N: FX493 |Applying initial value "1" on instance nCAS. -@N: FX493 |Applying initial value "1" on instance nCASout. -@N: FX493 |Applying initial value "1" on instance nRAS. -@N: FX493 |Applying initial value "1" on instance nRASout. - -Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) - - -Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) - - -Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) - - -Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) - -@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------- -0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122 - -0 - System 100.0 MHz 10.000 system system_clkgroup 0 -======================================================================================== - - - -Clock Load Summary -*********************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example ----------------------------------------------------------------------------------------- -C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv) - -System 0 - - - - -======================================================================================== - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -For details review file gcc_ICG_report.rpt - - -@S |Clock Optimization Summary - - - -#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ - -1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - -=========================== Non-Gated/Non-Generated Clocks ============================ -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------- -@KP:ckid0_0 C14M port 122 nRAS -======================================================================================= - - -##### END OF CLOCK OPTIMIZATION REPORT ###### - -@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) - - -Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Dec 28 23:23:23 2023 - -###########################################################] -# Thu Dec 28 23:23:23 2023 - - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) - -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB) - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) - -@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0] -@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. - -Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB) - - -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:01s 33.71ns 284 / 122 - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB) - - -Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB) - -Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) - - -Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB) - -@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@N: MT615 |Found clock C14M with period 69.84ns - - -##### START OF TIMING REPORT #####[ -# Timing report written on Thu Dec 28 23:23:26 2023 -# - - -Top view: RAM2E -Requested Frequency: 14.3 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 33.707 - - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------- -C14M 14.3 MHz 128.0 MHz 69.841 7.813 33.707 declared default_clkgroup -System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup -=================================================================================================================== -Estimated period and frequency reported as NA means no slack depends directly on the clock waveform - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------- -System C14M | 69.841 67.088 | No paths - | No paths - | No paths - -C14M System | 69.841 68.797 | No paths - | No paths - | No paths - -C14M C14M | 69.841 62.028 | No paths - | 34.920 33.707 | No paths - -========================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: C14M -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------- -RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707 -RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707 -RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771 -RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771 -RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771 -RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771 -RA[6] C14M FD1P3AX Q RA[6] 1.044 33.771 -RA[7] C14M FD1P3AX Q RA[7] 1.044 33.771 -RA[8] C14M FD1P3AX Q RA[8] 1.044 33.771 -RA[9] C14M FD1P3AX Q RA[9] 1.044 33.771 -=========================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------- -RAout_0io[0] C14M OFS1P3DX D RA[0] 34.815 33.707 -RAout_0io[3] C14M OFS1P3DX D RA[3] 34.815 33.707 -RAout_0io[1] C14M OFS1P3DX D RA[1] 34.815 33.771 -RAout_0io[2] C14M OFS1P3DX D RA[2] 34.815 33.771 -RAout_0io[4] C14M OFS1P3DX D RA[4] 34.815 33.771 -RAout_0io[5] C14M OFS1P3DX D RA[5] 34.815 33.771 -RAout_0io[6] C14M OFS1P3DX D RA[6] 34.815 33.771 -RAout_0io[7] C14M OFS1P3DX D RA[7] 34.815 33.771 -RAout_0io[8] C14M OFS1P3DX D RA[8] 34.815 33.771 -RAout_0io[9] C14M OFS1P3DX D RA[9] 34.815 33.771 -================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 34.920 - - Setup time: 0.106 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 34.815 - - - Propagation time: 1.108 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : 33.707 - - Number of logic level(s): 0 - Starting point: RA[0] / Q - Ending point: RAout_0io[0] / D - The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK - The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -RA[0] FD1P3AX Q Out 1.108 1.108 r - -RA[0] Net - - - - 3 -RAout_0io[0] OFS1P3DX D In 0.000 1.108 r - -================================================================================= - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------- -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313 -=================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------- -ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0_0[0] 69.369 67.736 -ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdSetRWBankFFChip13_1_i_0_0[0] 69.369 67.736 -====================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 69.841 - - Setup time: 0.472 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 69.369 - - - Propagation time: 2.282 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 67.088 - - Number of logic level(s): 2 - Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO - Ending point: ram2e_ufm.RWMask[0] / SP - The start point is clocked by System [rising] - The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- -ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r - -wb_ack Net - - - - 5 -ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 B In 0.000 0.000 r - -ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 Z Out 1.017 1.017 r - -un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] Net - - - - 1 -ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 D In 0.000 1.017 r - -ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 Z Out 1.265 2.282 r - -un1_RWMask_0_sqmuxa_1_i_0_0[0] Net - - - - 8 -ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 r - -================================================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied - -Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB) - - -Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB) - ---------------------------------------- -Resource Usage Report -Part: lcmxo2_1200hc-4 - -Register bits: 122 of 1280 (10%) -PIC Latch: 0 -I/O cells: 69 - - -Details: -BB: 8 -CCU2D: 9 -EFB: 1 -FD1P3AX: 61 -FD1P3IX: 1 -FD1S3AX: 21 -FD1S3AY: 4 -FD1S3IX: 6 -GSR: 1 -IB: 21 -IFS1P3DX: 1 -INV: 1 -OB: 40 -OFS1P3BX: 5 -OFS1P3DX: 21 -OFS1P3IX: 2 -ORCALUT4: 277 -PFUMX: 3 -PUR: 1 -VHI: 3 -VLO: 3 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 217MB) - -Process took 0h:00m:03s realtime, 0h:00m:03s cputime -# Thu Dec 28 23:23:26 2023 - -###########################################################] diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.tw1 b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.tw1 deleted file mode 100644 index badd0c1..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.tw1 +++ /dev/null @@ -1,215 +0,0 @@ - -Loading design for application trce from file ram2e_lcmxo2_1200hc_impl1_map.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:23:29 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf -Design file: ram2e_lcmxo2_1200hc_impl1_map.ncd -Preference file: ram2e_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,4 -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; - 1611 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 58.937ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[2] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 10.827ns (31.6% logic, 68.4% route), 7 logic levels. - - Constraint Details: - - 10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from C14M_c) -ROUTE 50 e 1.234 SLICE_34.Q0 to SLICE_35.A0 S[2] -CTOF_DEL --- 0.495 SLICE_35.A0 to SLICE_35.F0 SLICE_35 -ROUTE 7 e 1.234 SLICE_35.F0 to *m/SLICE_80.D1 N_551 -CTOF_DEL --- 0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80 -ROUTE 8 e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98 -ROUTE 5 e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781 -CTOF_DEL --- 0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99 -ROUTE 1 e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0] -CTOF_DEL --- 0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86 -ROUTE 1 e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47 -ROUTE 1 e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 10.827 (31.6% logic, 68.4% route), 7 logic levels. - -Report: 90.967MHz is the maximum frequency for this preference. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 90.967 MHz| 7 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 1 clocks: - -Clock Domain: C14M_c Source: C14M.PAD Loads: 89 - Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; - - -Timing summary (Setup): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:23:29 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf -Design file: ram2e_lcmxo2_1200hc_impl1_map.ncd -Preference file: ram2e_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,M -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; - 1611 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.447ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[0] (from C14M_c +) - Destination: FF Data in FS[0] (to C14M_c +) - - Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. - - Constraint Details: - - 0.434ns physical path delay SLICE_0 to SLICE_0 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns - - Physical Path Details: - - Data path SLICE_0 to SLICE_0: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c) -ROUTE 6 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0] -CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0 -ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c) - -------- - 0.434 (53.9% logic, 46.1% route), 2 logic levels. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 1 clocks: - -Clock Domain: C14M_c Source: C14M.PAD Loads: 89 - Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 0 (setup), 0 (hold) -Score: 0 (setup), 0 (hold) -Cumulative negative slack: 0 (0+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.twr b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.twr deleted file mode 100644 index 850b55d..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.twr +++ /dev/null @@ -1,1135 +0,0 @@ - -Loading design for application trce from file ram2e_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:23:45 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -Design file: ram2e_lcmxo2_1200hc_impl1.ncd -Preference file: ram2e_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,4 -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; - 1611 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 58.069ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[2] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 11.695ns (29.3% logic, 70.7% route), 7 logic levels. - - Constraint Details: - - 11.695ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.069ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q0 SLICE_34 (from C14M_c) -ROUTE 50 1.472 R5C13B.Q0 to R5C11D.A0 S[2] -CTOF_DEL --- 0.495 R5C11D.A0 to R5C11D.F0 SLICE_35 -ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 -CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 -ROUTE 5 1.755 R3C6C.F1 to R2C7D.A0 ram2e_ufm/N_781 -CTOF_DEL --- 0.495 R2C7D.A0 to R2C7D.F0 ram2e_ufm/SLICE_99 -ROUTE 1 1.023 R2C7D.F0 to R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0] -CTOF_DEL --- 0.495 R3C7A.B0 to R3C7A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 11.695 (29.3% logic, 70.7% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.138ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[2] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 11.626ns (29.4% logic, 70.6% route), 7 logic levels. - - Constraint Details: - - 11.626ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.138ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q0 SLICE_34 (from C14M_c) -ROUTE 50 1.472 R5C13B.Q0 to R5C11D.A0 S[2] -CTOF_DEL --- 0.495 R5C11D.A0 to R5C11D.F0 SLICE_35 -ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 -CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 -ROUTE 5 1.962 R3C6C.F1 to R3C7C.C0 ram2e_ufm/N_781 -CTOF_DEL --- 0.495 R3C7C.C0 to R3C7C.F0 ram2e_ufm/SLICE_126 -ROUTE 1 0.747 R3C7C.F0 to R3C7A.C0 ram2e_ufm/N_753 -CTOF_DEL --- 0.495 R3C7A.C0 to R3C7A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 11.626 (29.4% logic, 70.6% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.247ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[2] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_dati[7] (to C14M_c +) - - Delay: 11.517ns (25.4% logic, 74.6% route), 6 logic levels. - - Constraint Details: - - 11.517ns physical path delay SLICE_34 to ram2e_ufm/SLICE_55 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.247ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_55: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q0 SLICE_34 (from C14M_c) -ROUTE 50 1.472 R5C13B.Q0 to R5C11D.A0 S[2] -CTOF_DEL --- 0.495 R5C11D.A0 to R5C11D.F0 SLICE_35 -ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 -CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.631 R5C10B.F1 to R3C6A.A1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C6A.A1 to R3C6A.F1 ram2e_ufm/SLICE_81 -ROUTE 4 1.963 R3C6A.F1 to R3C10A.C0 ram2e_ufm/N_856 -CTOF_DEL --- 0.495 R3C10A.C0 to R3C10A.F0 ram2e_ufm/SLICE_131 -ROUTE 1 1.535 R3C10A.F0 to R3C6B.B1 ram2e_ufm/N_602 -CTOF_DEL --- 0.495 R3C6B.B1 to R3C6B.F1 ram2e_ufm/SLICE_55 -ROUTE 1 0.000 R3C6B.F1 to R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c) - -------- - 11.517 (25.4% logic, 74.6% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_55: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R3C6B.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.444ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[3] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 11.320ns (30.2% logic, 69.8% route), 7 logic levels. - - Constraint Details: - - 11.320ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.444ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q1 SLICE_34 (from C14M_c) -ROUTE 45 1.097 R5C13B.Q1 to R5C11D.B0 S[3] -CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_35 -ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 -CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 -ROUTE 5 1.755 R3C6C.F1 to R2C7D.A0 ram2e_ufm/N_781 -CTOF_DEL --- 0.495 R2C7D.A0 to R2C7D.F0 ram2e_ufm/SLICE_99 -ROUTE 1 1.023 R2C7D.F0 to R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0] -CTOF_DEL --- 0.495 R3C7A.B0 to R3C7A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 11.320 (30.2% logic, 69.8% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.513ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[3] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 11.251ns (30.4% logic, 69.6% route), 7 logic levels. - - Constraint Details: - - 11.251ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.513ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q1 SLICE_34 (from C14M_c) -ROUTE 45 1.097 R5C13B.Q1 to R5C11D.B0 S[3] -CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_35 -ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 -CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 -ROUTE 5 1.962 R3C6C.F1 to R3C7C.C0 ram2e_ufm/N_781 -CTOF_DEL --- 0.495 R3C7C.C0 to R3C7C.F0 ram2e_ufm/SLICE_126 -ROUTE 1 0.747 R3C7C.F0 to R3C7A.C0 ram2e_ufm/N_753 -CTOF_DEL --- 0.495 R3C7A.C0 to R3C7A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 11.251 (30.4% logic, 69.6% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.525ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[0] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 11.239ns (26.0% logic, 74.0% route), 6 logic levels. - - Constraint Details: - - 11.239ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.525ns - - Physical Path Details: - - Data path SLICE_33 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C13D.CLK to R5C13D.Q0 SLICE_33 (from C14M_c) -ROUTE 37 2.500 R5C13D.Q0 to R5C10B.C1 S[0] -CTOF_DEL --- 0.495 R5C10B.C1 to R5C10B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 -ROUTE 5 1.755 R3C6C.F1 to R2C7D.A0 ram2e_ufm/N_781 -CTOF_DEL --- 0.495 R2C7D.A0 to R2C7D.F0 ram2e_ufm/SLICE_99 -ROUTE 1 1.023 R2C7D.F0 to R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0] -CTOF_DEL --- 0.495 R3C7A.B0 to R3C7A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 11.239 (26.0% logic, 74.0% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R5C13D.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.594ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[0] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 11.170ns (26.2% logic, 73.8% route), 6 logic levels. - - Constraint Details: - - 11.170ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.594ns - - Physical Path Details: - - Data path SLICE_33 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C13D.CLK to R5C13D.Q0 SLICE_33 (from C14M_c) -ROUTE 37 2.500 R5C13D.Q0 to R5C10B.C1 S[0] -CTOF_DEL --- 0.495 R5C10B.C1 to R5C10B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.411 R5C10B.F1 to R3C6C.C1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C6C.C1 to R3C6C.F1 ram2e_ufm/SLICE_98 -ROUTE 5 1.962 R3C6C.F1 to R3C7C.C0 ram2e_ufm/N_781 -CTOF_DEL --- 0.495 R3C7C.C0 to R3C7C.F0 ram2e_ufm/SLICE_126 -ROUTE 1 0.747 R3C7C.F0 to R3C7A.C0 ram2e_ufm/N_753 -CTOF_DEL --- 0.495 R3C7A.C0 to R3C7A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 11.170 (26.2% logic, 73.8% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R5C13D.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.622ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[3] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_dati[7] (to C14M_c +) - - Delay: 11.142ns (26.3% logic, 73.7% route), 6 logic levels. - - Constraint Details: - - 11.142ns physical path delay SLICE_34 to ram2e_ufm/SLICE_55 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.622ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_55: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q1 SLICE_34 (from C14M_c) -ROUTE 45 1.097 R5C13B.Q1 to R5C11D.B0 S[3] -CTOF_DEL --- 0.495 R5C11D.B0 to R5C11D.F0 SLICE_35 -ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 -CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.631 R5C10B.F1 to R3C6A.A1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C6A.A1 to R3C6A.F1 ram2e_ufm/SLICE_81 -ROUTE 4 1.963 R3C6A.F1 to R3C10A.C0 ram2e_ufm/N_856 -CTOF_DEL --- 0.495 R3C10A.C0 to R3C10A.F0 ram2e_ufm/SLICE_131 -ROUTE 1 1.535 R3C10A.F0 to R3C6B.B1 ram2e_ufm/N_602 -CTOF_DEL --- 0.495 R3C6B.B1 to R3C6B.F1 ram2e_ufm/SLICE_55 -ROUTE 1 0.000 R3C6B.F1 to R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c) - -------- - 11.142 (26.3% logic, 73.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_55: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R3C6B.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.703ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[0] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_dati[7] (to C14M_c +) - - Delay: 11.061ns (22.0% logic, 78.0% route), 5 logic levels. - - Constraint Details: - - 11.061ns physical path delay SLICE_33 to ram2e_ufm/SLICE_55 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.703ns - - Physical Path Details: - - Data path SLICE_33 to ram2e_ufm/SLICE_55: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C13D.CLK to R5C13D.Q0 SLICE_33 (from C14M_c) -ROUTE 37 2.500 R5C13D.Q0 to R5C10B.C1 S[0] -CTOF_DEL --- 0.495 R5C10B.C1 to R5C10B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.631 R5C10B.F1 to R3C6A.A1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C6A.A1 to R3C6A.F1 ram2e_ufm/SLICE_81 -ROUTE 4 1.963 R3C6A.F1 to R3C10A.C0 ram2e_ufm/N_856 -CTOF_DEL --- 0.495 R3C10A.C0 to R3C10A.F0 ram2e_ufm/SLICE_131 -ROUTE 1 1.535 R3C10A.F0 to R3C6B.B1 ram2e_ufm/N_602 -CTOF_DEL --- 0.495 R3C6B.B1 to R3C6B.F1 ram2e_ufm/SLICE_55 -ROUTE 1 0.000 R3C6B.F1 to R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c) - -------- - 11.061 (22.0% logic, 78.0% route), 5 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R5C13D.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_55: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R3C6B.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.866ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[2] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 10.898ns (31.4% logic, 68.6% route), 7 logic levels. - - Constraint Details: - - 10.898ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.866ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R5C13B.CLK to R5C13B.Q0 SLICE_34 (from C14M_c) -ROUTE 50 1.472 R5C13B.Q0 to R5C11D.A0 S[2] -CTOF_DEL --- 0.495 R5C11D.A0 to R5C11D.F0 SLICE_35 -ROUTE 7 0.989 R5C11D.F0 to R5C10B.A1 N_551 -CTOF_DEL --- 0.495 R5C10B.A1 to R5C10B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 3.058 R5C10B.F1 to R3C5D.A1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C5D.A1 to R3C5D.F1 ram2e_ufm/SLICE_89 -ROUTE 6 0.348 R3C5D.F1 to R3C5C.D1 ram2e_ufm/N_783 -CTOF_DEL --- 0.495 R3C5C.D1 to R3C5C.F1 ram2e_ufm/SLICE_68 -ROUTE 1 0.986 R3C5C.F1 to R3C7A.A0 ram2e_ufm/wb_adr_7_i_i_3[0] -CTOF_DEL --- 0.495 R3C7A.A0 to R3C7A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 0.623 R3C7A.F0 to R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R2C7A.D0 to R2C7A.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R2C7A.F0 to R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 10.898 (31.4% logic, 68.6% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R5C13B.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 4.865 62.PADDI to R2C7A.CLK C14M_c - -------- - 4.865 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 84.310MHz is the maximum frequency for this preference. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 84.310 MHz| 7 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 1 clocks: - -Clock Domain: C14M_c Source: C14M.PAD Loads: 89 - Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; - - -Timing summary (Setup): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:23:45 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -Design file: ram2e_lcmxo2_1200hc_impl1.ncd -Preference file: ram2e_lcmxo2_1200hc_impl1.prf -Device,speed: LCMXO2-1200HC,m -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; - 1611 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.342ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q ram2e_ufm/wb_dati[6] (from C14M_c +) - Destination: EFB Port ram2e_ufm/ufmefb/EFBInst_0(ASIC) (to C14M_c +) - - Delay: 0.305ns (43.6% logic, 56.4% route), 1 logic levels. - - Constraint Details: - - 0.305ns physical path delay ram2e_ufm/SLICE_55 to ram2e_ufm/ufmefb/EFBInst_0 meets - -0.091ns WBDATI_HLD and - 0.000ns delay constraint less - -0.054ns skew requirement (totaling -0.037ns) by 0.342ns - - Physical Path Details: - - Data path ram2e_ufm/SLICE_55 to ram2e_ufm/ufmefb/EFBInst_0: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R3C6B.CLK to R3C6B.Q0 ram2e_ufm/SLICE_55 (from C14M_c) -ROUTE 1 0.172 R3C6B.Q0 to EFB.WBDATI6 ram2e_ufm/wb_dati[6] (to C14M_c) - -------- - 0.305 (43.6% logic, 56.4% route), 1 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to ram2e_ufm/SLICE_55: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R3C6B.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/ufmefb/EFBInst_0: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.722 62.PADDI to EFB.WBCLKI C14M_c - -------- - 1.722 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[15] (from C14M_c +) - Destination: FF Data in FS[15] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_1 to SLICE_1 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_1: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C12A.CLK to R2C12A.Q0 SLICE_1 (from C14M_c) -ROUTE 9 0.132 R2C12A.Q0 to R2C12A.A0 FS[15] -CTOF_DEL --- 0.101 R2C12A.A0 to R2C12A.F0 SLICE_1 -ROUTE 1 0.000 R2C12A.F0 to R2C12A.DI0 FS_s[15] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R2C12A.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R2C12A.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdTout[2] (from C14M_c +) - Destination: FF Data in CmdTout[2] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_18 to SLICE_18 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_18 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R8C11A.CLK to R8C11A.Q1 SLICE_18 (from C14M_c) -ROUTE 2 0.132 R8C11A.Q1 to R8C11A.A1 CmdTout[2] -CTOF_DEL --- 0.101 R8C11A.A1 to R8C11A.F1 SLICE_18 -ROUTE 1 0.000 R8C11A.F1 to R8C11A.DI1 N_369_i (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R8C11A.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R8C11A.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdTout[1] (from C14M_c +) - Destination: FF Data in CmdTout[1] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_18 to SLICE_18 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_18 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R8C11A.CLK to R8C11A.Q0 SLICE_18 (from C14M_c) -ROUTE 3 0.132 R8C11A.Q0 to R8C11A.A0 CmdTout[1] -CTOF_DEL --- 0.101 R8C11A.A0 to R8C11A.F0 SLICE_18 -ROUTE 1 0.000 R8C11A.F0 to R8C11A.DI0 N_368_i (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R8C11A.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R8C11A.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from C14M_c +) - Destination: FF Data in FS[13] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_2 to SLICE_2 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_2: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C11D.CLK to R2C11D.Q0 SLICE_2 (from C14M_c) -ROUTE 19 0.132 R2C11D.Q0 to R2C11D.A0 FS[13] -CTOF_DEL --- 0.101 R2C11D.A0 to R2C11D.F0 SLICE_2 -ROUTE 1 0.000 R2C11D.F0 to R2C11D.DI0 FS_s[13] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R2C11D.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R2C11D.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA[9] (from C14M_c +) - Destination: FF Data in RA[9] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_24 to SLICE_24 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_24 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11C.CLK to R5C11C.Q1 SLICE_24 (from C14M_c) -ROUTE 2 0.132 R5C11C.Q1 to R5C11C.A1 RA[9] -CTOF_DEL --- 0.101 R5C11C.A1 to R5C11C.F1 SLICE_24 -ROUTE 1 0.000 R5C11C.F1 to R5C11C.DI1 RA_35[9] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R5C11C.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R5C11C.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA[8] (from C14M_c +) - Destination: FF Data in RA[8] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_24 to SLICE_24 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_24 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11C.CLK to R5C11C.Q0 SLICE_24 (from C14M_c) -ROUTE 2 0.132 R5C11C.Q0 to R5C11C.A0 RA[8] -CTOF_DEL --- 0.101 R5C11C.A0 to R5C11C.F0 SLICE_24 -ROUTE 1 0.000 R5C11C.F0 to R5C11C.DI0 un2_S_2_i_0_0_o3_RNIHFHN3 (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R5C11C.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R5C11C.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA[11] (from C14M_c +) - Destination: FF Data in RA[11] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_25 to SLICE_25 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_25 to SLICE_25: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C12D.CLK to R5C12D.Q1 SLICE_25 (from C14M_c) -ROUTE 2 0.132 R5C12D.Q1 to R5C12D.A1 RA[11] -CTOF_DEL --- 0.101 R5C12D.A1 to R5C12D.F1 SLICE_25 -ROUTE 1 0.000 R5C12D.F1 to R5C12D.DI1 RA_35[11] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_25: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R5C12D.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_25: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R5C12D.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RC[2] (from C14M_c +) - Destination: FF Data in RC[2] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_26 to SLICE_26 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_26 to SLICE_26: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R4C15C.CLK to R4C15C.Q1 SLICE_26 (from C14M_c) -ROUTE 5 0.132 R4C15C.Q1 to R4C15C.A1 RC[2] -CTOF_DEL --- 0.101 R4C15C.A1 to R4C15C.F1 SLICE_26 -ROUTE 1 0.000 R4C15C.F1 to R4C15C.DI1 RC_3[2] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_26: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R4C15C.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_26: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R4C15C.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[12] (from C14M_c +) - Destination: FF Data in FS[12] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_3 to SLICE_3 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_3 to SLICE_3: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C11C.CLK to R2C11C.Q1 SLICE_3 (from C14M_c) -ROUTE 24 0.132 R2C11C.Q1 to R2C11C.A1 FS[12] -CTOF_DEL --- 0.101 R2C11C.A1 to R2C11C.F1 SLICE_3 -ROUTE 1 0.000 R2C11C.F1 to R2C11C.DI1 FS_s[12] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R2C11C.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.668 62.PADDI to R2C11C.CLK C14M_c - -------- - 1.668 (0.0% logic, 100.0% route), 0 logic levels. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 1 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 1 clocks: - -Clock Domain: C14M_c Source: C14M.PAD Loads: 89 - Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 0 (setup), 0 (hold) -Score: 0 (setup), 0 (hold) -Cumulative negative slack: 0 (0+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html deleted file mode 100644 index 3f9ee4c..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html +++ /dev/null @@ -1,152 +0,0 @@ - -Bitgen Report - - -
BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Dec 28 23:23:57 2023
-
-
-Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
-
-Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 4
-Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2E_LCMXO2_1200HC_impl1.prf.
-
-
-Preference Summary:
-
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                         RamCfg  |                        Reset**  |
-+---------------------------------+---------------------------------+
-|                     MCCLK_FREQ  |                         2.08**  |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                      JTAG_PORT  |                       ENABLE**  |
-+---------------------------------+---------------------------------+
-|                       SDM_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                 SLAVE_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                MASTER_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                       I2C_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                  CONFIGURATION  |                          CFG**  |
-+---------------------------------+---------------------------------+
-|                COMPRESS_CONFIG  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                        MY_ASSP  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|               ONE_TIME_PROGRAM  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                 ENABLE_TRANSFR  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                  SHAREDEBRINIT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|            BACKGROUND_RECONFIG  |                          OFF**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
- 
-Bitstream Status: Final           Version 1.95.
- 
-Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.jed".
- 
-===========
-UFM Summary.
-===========
-UFM Size:        511 Pages (128*511 Bits).
-UFM Utilization: General Purpose Flash Memory.
- 
-Available General Purpose Flash Memory:  511 Pages (Page 0 to Page 510).
-Initialized UFM Pages:                   321 Pages (Page 190 to Page 510).
- 
-Total CPU Time: 3 secs 
-Total REAL Time: 3 secs 
-Peak Memory Usage: 275 MB
-
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- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt deleted file mode 100644 index 1127160..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt +++ /dev/null @@ -1,152 +0,0 @@ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 - -# Written on Thu Dec 28 23:23:22 2023 - -##### DESIGN INFO ####################################################### - -Top View: "RAM2E" -Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc" - - - - -##### SUMMARY ############################################################ - -Found 0 issues in 0 out of 1 constraints - - -##### DETAILS ############################################################ - - - -Clock Relationships -******************* - -Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------ -System C14M | 69.841 | No paths | No paths | No paths -C14M System | 69.841 | No paths | No paths | No paths -C14M C14M | 69.841 | No paths | 34.920 | No paths -=================================================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - -Unconstrained Start/End Points -****************************** - -p:Ain[0] -p:Ain[1] -p:Ain[2] -p:Ain[3] -p:Ain[4] -p:Ain[5] -p:Ain[6] -p:Ain[7] -p:BA[0] -p:BA[1] -p:CKEout -p:DQMH -p:DQML -p:Din[0] -p:Din[1] -p:Din[2] -p:Din[3] -p:Din[4] -p:Din[5] -p:Din[6] -p:Din[7] -p:Dout[0] -p:Dout[1] -p:Dout[2] -p:Dout[3] -p:Dout[4] -p:Dout[5] -p:Dout[6] -p:Dout[7] -p:LED -p:PHI1 -p:RAout[0] -p:RAout[1] -p:RAout[2] -p:RAout[3] -p:RAout[4] -p:RAout[5] -p:RAout[6] -p:RAout[7] -p:RAout[8] -p:RAout[9] -p:RAout[10] -p:RAout[11] -p:RD[0] (bidir end point) -p:RD[0] (bidir start point) -p:RD[1] (bidir end point) -p:RD[1] (bidir start point) -p:RD[2] (bidir end point) -p:RD[2] (bidir start point) -p:RD[3] (bidir end point) -p:RD[3] (bidir start point) -p:RD[4] (bidir end point) -p:RD[4] (bidir start point) -p:RD[5] (bidir end point) -p:RD[5] (bidir start point) -p:RD[6] (bidir end point) -p:RD[6] (bidir start point) -p:RD[7] (bidir end point) -p:RD[7] (bidir start point) -p:Vout[0] -p:Vout[1] -p:Vout[2] -p:Vout[3] -p:Vout[4] -p:Vout[5] -p:Vout[6] -p:Vout[7] -p:nC07X -p:nCASout -p:nCSout -p:nDOE -p:nEN80 -p:nRASout -p:nRWEout -p:nVOE -p:nWE -p:nWE80 - - -Inapplicable constraints -************************ - -(none) - - -Applicable constraints with issues -********************************** - -(none) - - -Constraints with matching wildcard expressions -********************************************** - -(none) - - -Library Report -************** - - -# End of Constraint Checker Report diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_iotiming.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_iotiming.html deleted file mode 100644 index e0b3e0f..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_iotiming.html +++ /dev/null @@ -1,183 +0,0 @@ - -I/O Timing Report - - -
I/O Timing Report
-Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 6
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-// Design: RAM2E
-// Package: TQFP100
-// ncd File: ram2e_lcmxo2_1200hc_impl1.ncd
-// Version: Diamond (64-bit) 3.12.1.454
-// Written on Thu Dec 28 23:23:48 2023
-// M: Minimum Performance Grade
-// iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 6, 5, 4):
-
-// Input Setup and Hold Times
-
-Port   Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-Ain[0] C14M  R     0.163      4       1.694     4
-Ain[1] C14M  R    -0.150      M       2.217     4
-Ain[2] C14M  R    -0.080      M       2.156     4
-Ain[3] C14M  R     0.466      4       1.338     4
-Ain[4] C14M  R     0.215      4       1.597     4
-Ain[5] C14M  R    -0.331      M       2.651     4
-Ain[6] C14M  R     0.065      M       1.882     4
-Ain[7] C14M  R     0.284      4       1.683     4
-Din[0] C14M  R     6.887      4       2.257     4
-Din[1] C14M  R     8.753      4       2.907     4
-Din[2] C14M  R     6.379      4       2.740     4
-Din[3] C14M  R     7.129      4       1.402     4
-Din[4] C14M  R     6.869      4       2.791     4
-Din[5] C14M  R     6.514      4       2.334     4
-Din[6] C14M  R     6.735      4       1.914     4
-Din[7] C14M  R     8.094      4       1.968     4
-PHI1   C14M  R     1.557      4       4.842     4
-RD[0]  C14M  R    -0.266      M       2.342     4
-RD[1]  C14M  R    -0.248      M       2.283     4
-RD[2]  C14M  R    -0.407      M       2.610     4
-RD[3]  C14M  R    -0.243      M       2.193     4
-RD[4]  C14M  R    -0.246      M       2.201     4
-RD[5]  C14M  R    -0.243      M       2.193     4
-RD[6]  C14M  R    -0.087      M       1.756     4
-RD[7]  C14M  R    -0.092      M       1.769     4
-nC07X  C14M  R    -0.320      M       2.703     4
-nEN80  C14M  R     4.607      4       1.925     4
-nWE    C14M  R     4.609      4       2.010     4
-
-
-// Clock to Output Delay
-
-Port      Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-BA[0]     C14M  R    10.424         4        3.355          M
-BA[1]     C14M  R    10.424         4        3.355          M
-CKEout    C14M  F    10.424         4        3.355          M
-DQMH      C14M  R    10.404         4        3.362          M
-DQML      C14M  R    10.404         4        3.362          M
-LED       C14M  R    22.936         4        8.890          M
-RAout[0]  C14M  F    10.490         4        3.360          M
-RAout[10] C14M  F    10.490         4        3.360          M
-RAout[11] C14M  F    10.424         4        3.355          M
-RAout[1]  C14M  F    10.490         4        3.360          M
-RAout[2]  C14M  F    10.490         4        3.360          M
-RAout[3]  C14M  F    10.490         4        3.360          M
-RAout[4]  C14M  F    10.490         4        3.360          M
-RAout[5]  C14M  F    10.490         4        3.360          M
-RAout[6]  C14M  F    10.490         4        3.360          M
-RAout[7]  C14M  F    10.490         4        3.360          M
-RAout[8]  C14M  F    10.490         4        3.360          M
-RAout[9]  C14M  F    10.490         4        3.360          M
-RD[0]     C14M  R    13.733         4        3.707          M
-RD[1]     C14M  R    13.745         4        3.707          M
-RD[2]     C14M  R    14.285         4        3.790          M
-RD[3]     C14M  R    13.348         4        3.790          M
-RD[4]     C14M  R    14.450         4        3.952          M
-RD[5]     C14M  R    14.480         4        3.952          M
-RD[6]     C14M  R    14.784         4        3.952          M
-RD[7]     C14M  R    14.247         4        3.952          M
-Vout[0]   C14M  R    11.348         4        3.872          M
-Vout[1]   C14M  R    11.434         4        3.871          M
-Vout[2]   C14M  R    11.348         4        3.872          M
-Vout[3]   C14M  R    11.434         4        3.871          M
-Vout[4]   C14M  R    11.348         4        3.872          M
-Vout[5]   C14M  R    11.348         4        3.872          M
-Vout[6]   C14M  R    11.434         4        3.871          M
-Vout[7]   C14M  R    11.434         4        3.871          M
-nCASout   C14M  F    10.424         4        3.355          M
-nDOE      C14M  R    13.929         4        4.309          M
-nRASout   C14M  F    10.424         4        3.355          M
-nRWEout   C14M  F    10.424         4        3.355          M
-nVOE      C14M  R    13.926         4        4.281          M
-WARNING: you must also run trce with hold speed: 4
-WARNING: you must also run trce with setup speed: M
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- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf deleted file mode 100644 index 7753439..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf +++ /dev/null @@ -1,5500 +0,0 @@ -(DELAYFILE - (SDFVERSION "3.0") - (DESIGN "RAM2E") - (DATE "Thu Dec 28 23:23:31 2023") - (VENDOR "Lattice") - (PROGRAM "ldbanno") - (VERSION "Diamond (64-bit) 3.12.1.454") - (DIVIDER /) - (VOLTAGE 1.26:1.20:1.14) - (PROCESS "default") - (TEMPERATURE -40:25:85) - (TIMESCALE 1ps) - (CELL - (CELLTYPE "SLICE_0") - (INSTANCE SLICE_0) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 FCO (718:803:889)(718:803:889)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_1") - (INSTANCE SLICE_1) - (DELAY - (ABSOLUTE - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH FCI F0 (473:529:585)(473:529:585)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_2") - (INSTANCE SLICE_2) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 FCO (718:803:889)(718:803:889)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F1 (718:803:889)(718:803:889)) - (IOPATH A0 FCO (827:925:1023)(827:925:1023)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - (IOPATH FCI F0 (473:529:585)(473:529:585)) - (IOPATH FCI F1 (519:581:643)(519:581:643)) - (IOPATH FCI FCO (130:146:162)(130:146:162)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_3") - (INSTANCE SLICE_3) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 FCO (718:803:889)(718:803:889)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F1 (718:803:889)(718:803:889)) - (IOPATH A0 FCO (827:925:1023)(827:925:1023)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - (IOPATH FCI F0 (473:529:585)(473:529:585)) - (IOPATH FCI F1 (519:581:643)(519:581:643)) - (IOPATH FCI FCO (130:146:162)(130:146:162)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_4") - (INSTANCE SLICE_4) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 FCO (718:803:889)(718:803:889)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F1 (718:803:889)(718:803:889)) - (IOPATH A0 FCO (827:925:1023)(827:925:1023)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - (IOPATH FCI F0 (473:529:585)(473:529:585)) - (IOPATH FCI F1 (519:581:643)(519:581:643)) - (IOPATH FCI FCO (130:146:162)(130:146:162)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_5") - (INSTANCE SLICE_5) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 FCO (718:803:889)(718:803:889)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F1 (718:803:889)(718:803:889)) - (IOPATH A0 FCO (827:925:1023)(827:925:1023)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - (IOPATH FCI F0 (473:529:585)(473:529:585)) - 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(IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_48") - (INSTANCE ram2e_ufm\/SLICE_48) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_49") - (INSTANCE ram2e_ufm\/SLICE_49) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_50") - (INSTANCE ram2e_ufm\/SLICE_50) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_51") - (INSTANCE ram2e_ufm\/SLICE_51) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_52") - (INSTANCE ram2e_ufm\/SLICE_52) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_53") - (INSTANCE ram2e_ufm\/SLICE_53) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_54") - (INSTANCE ram2e_ufm\/SLICE_54) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_55") - (INSTANCE ram2e_ufm\/SLICE_55) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_56") - (INSTANCE ram2e_ufm\/SLICE_56) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_57") - (INSTANCE ram2e_ufm\/SLICE_57) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) - ) - (TIMINGCHECK - (WIDTH (posedge LSR) (4000:4000:4000)) - (WIDTH (negedge LSR) (4000:4000:4000)) - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_58") - (INSTANCE ram2e_ufm\/SLICE_58) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SUM0_i_m3_0_SLICE_59") - (INSTANCE ram2e_ufm\/SUM0_i_m3_0\/SLICE_59) - (DELAY - (ABSOLUTE - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH B1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60") - (INSTANCE ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH B1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_CKE_7_SLICE_61") - (INSTANCE ram2e_ufm\/CKE_7\/SLICE_61) - (DELAY - (ABSOLUTE - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH B1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_62") - (INSTANCE ram2e_ufm\/SLICE_62) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_63") - (INSTANCE ram2e_ufm\/SLICE_63) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_64") - (INSTANCE ram2e_ufm\/SLICE_64) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_65") - (INSTANCE ram2e_ufm\/SLICE_65) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_66") - (INSTANCE ram2e_ufm\/SLICE_66) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_67") - (INSTANCE ram2e_ufm\/SLICE_67) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_68") - (INSTANCE ram2e_ufm\/SLICE_68) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_69") - (INSTANCE ram2e_ufm\/SLICE_69) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_70") - (INSTANCE ram2e_ufm\/SLICE_70) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_71") - (INSTANCE ram2e_ufm\/SLICE_71) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_72") - (INSTANCE ram2e_ufm\/SLICE_72) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_73") - (INSTANCE ram2e_ufm\/SLICE_73) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_74") - (INSTANCE ram2e_ufm\/SLICE_74) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_75") - (INSTANCE ram2e_ufm\/SLICE_75) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_76") - (INSTANCE ram2e_ufm\/SLICE_76) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_77") - (INSTANCE ram2e_ufm\/SLICE_77) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_78") - (INSTANCE ram2e_ufm\/SLICE_78) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_79") - (INSTANCE ram2e_ufm\/SLICE_79) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_80") - (INSTANCE ram2e_ufm\/SLICE_80) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_81") - (INSTANCE ram2e_ufm\/SLICE_81) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_82") - (INSTANCE ram2e_ufm\/SLICE_82) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_83") - (INSTANCE ram2e_ufm\/SLICE_83) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_84") - (INSTANCE ram2e_ufm\/SLICE_84) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_85") - (INSTANCE ram2e_ufm\/SLICE_85) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_86") - (INSTANCE ram2e_ufm\/SLICE_86) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_87") - (INSTANCE ram2e_ufm\/SLICE_87) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_88") - (INSTANCE ram2e_ufm\/SLICE_88) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_89") - (INSTANCE ram2e_ufm\/SLICE_89) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_90") - (INSTANCE ram2e_ufm\/SLICE_90) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_91") - (INSTANCE ram2e_ufm\/SLICE_91) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_92") - (INSTANCE ram2e_ufm\/SLICE_92) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_93") - (INSTANCE ram2e_ufm\/SLICE_93) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_94") - (INSTANCE ram2e_ufm\/SLICE_94) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_95") - (INSTANCE ram2e_ufm\/SLICE_95) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_96") - (INSTANCE ram2e_ufm\/SLICE_96) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_97") - (INSTANCE ram2e_ufm\/SLICE_97) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_98") - (INSTANCE ram2e_ufm\/SLICE_98) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_99") - (INSTANCE ram2e_ufm\/SLICE_99) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_100") - (INSTANCE ram2e_ufm\/SLICE_100) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_101") - (INSTANCE ram2e_ufm\/SLICE_101) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_102") - (INSTANCE ram2e_ufm\/SLICE_102) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_103") - (INSTANCE ram2e_ufm\/SLICE_103) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_104") - (INSTANCE ram2e_ufm\/SLICE_104) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_105") - (INSTANCE ram2e_ufm\/SLICE_105) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_106") - (INSTANCE ram2e_ufm\/SLICE_106) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_107") - (INSTANCE ram2e_ufm\/SLICE_107) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_108") - (INSTANCE ram2e_ufm\/SLICE_108) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_109") - (INSTANCE ram2e_ufm\/SLICE_109) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_110") - (INSTANCE ram2e_ufm\/SLICE_110) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_111") - (INSTANCE ram2e_ufm\/SLICE_111) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_112") - (INSTANCE ram2e_ufm\/SLICE_112) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_113") - (INSTANCE ram2e_ufm\/SLICE_113) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_114") - (INSTANCE ram2e_ufm\/SLICE_114) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_115") - (INSTANCE ram2e_ufm\/SLICE_115) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_116") - (INSTANCE ram2e_ufm\/SLICE_116) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_117") - (INSTANCE ram2e_ufm\/SLICE_117) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_118") - (INSTANCE ram2e_ufm\/SLICE_118) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_119") - (INSTANCE ram2e_ufm\/SLICE_119) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_120") - (INSTANCE ram2e_ufm\/SLICE_120) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_121") - (INSTANCE ram2e_ufm\/SLICE_121) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_122") - (INSTANCE ram2e_ufm\/SLICE_122) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_123") - (INSTANCE ram2e_ufm\/SLICE_123) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_124") - (INSTANCE ram2e_ufm\/SLICE_124) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_125") - (INSTANCE ram2e_ufm\/SLICE_125) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_126") - (INSTANCE ram2e_ufm\/SLICE_126) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_127") - (INSTANCE ram2e_ufm\/SLICE_127) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_128") - (INSTANCE ram2e_ufm\/SLICE_128) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_129") - (INSTANCE ram2e_ufm\/SLICE_129) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_130") - (INSTANCE ram2e_ufm\/SLICE_130) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_131") - (INSTANCE ram2e_ufm\/SLICE_131) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_132") - (INSTANCE ram2e_ufm\/SLICE_132) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_133") - (INSTANCE ram2e_ufm\/SLICE_133) - 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(SETUPHOLD WBRSTIin (posedge WBCLKIin) (3138:3170:3203)(-3138:-1966:-794)) - (SETUPHOLD WBCYCIin (posedge WBCLKIin) (2616:2649:2682)(-2616:-1558:-501)) - (SETUPHOLD WBSTBIin (posedge WBCLKIin) (2605:2637:2670)(-2605:-1494:-384)) - (SETUPHOLD WBWEIin (posedge WBCLKIin) (1409:1442:1475)(-1409:-837:-266)) - (SETUPHOLD WBADRI0in (posedge WBCLKIin) (2058:2123:2188)(-2058:-1191:-324)) - (SETUPHOLD WBADRI1in (posedge WBCLKIin) (2068:2104:2140)(-2068:-1234:-401)) - (SETUPHOLD WBADRI2in (posedge WBCLKIin) (1928:1993:2058)(-1928:-1110:-292)) - (SETUPHOLD WBADRI3in (posedge WBCLKIin) (2167:2196:2226)(-2167:-1264:-361)) - (SETUPHOLD WBADRI4in (posedge WBCLKIin) (2072:2101:2130)(-2072:-1198:-324)) - (SETUPHOLD WBADRI5in (posedge WBCLKIin) (1611:1640:1670)(-1611:-950:-289)) - (SETUPHOLD WBADRI6in (posedge WBCLKIin) (2532:2564:2597)(-2532:-1380:-229)) - (SETUPHOLD WBADRI7in (posedge WBCLKIin) (2519:2551:2584)(-2519:-1377:-235)) - (SETUPHOLD WBDATI0in (posedge WBCLKIin) (1057:1262:1467)(-1037:-712:-388)) - (SETUPHOLD WBDATI1in (posedge WBCLKIin) (1114:1338:1563)(-1108:-785:-462)) - (SETUPHOLD WBDATI2in (posedge WBCLKIin) (916:1076:1237)(-912:-636:-360)) - (SETUPHOLD WBDATI3in (posedge WBCLKIin) (1145:1359:1573)(-1115:-782:-449)) - (SETUPHOLD WBDATI4in (posedge WBCLKIin) (1192:1400:1609)(-1176:-820:-464)) - (SETUPHOLD WBDATI5in (posedge WBCLKIin) (1027:1222:1418)(-1000:-706:-413)) - (SETUPHOLD WBDATI6in (posedge WBCLKIin) (1034:1248:1463)(-1034:-756:-479)) - (SETUPHOLD WBDATI7in (posedge WBCLKIin) (528:614:701)(-528:-398:-268)) - ) - (TIMINGCHECK - (WIDTH (posedge WBCLKIin) (4887:4887:4887)) - (WIDTH (negedge WBCLKIin) (4887:4887:4887)) - ) - ) - (CELL - (CELLTYPE "RAM2E") - (INSTANCE ) - (DELAY - (ABSOLUTE - (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_51/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_69/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_105/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_108/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_146/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_11/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_13/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_15/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_16/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_17/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_27/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_28/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_39/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_40/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_41/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_42/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_43/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_44/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_45/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_46/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_47/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_48/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_49/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_50/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_51/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_52/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_53/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_54/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_55/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_56/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_57/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_58/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI DQMH_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI DQML_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[11\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[10\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[9\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[8\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[7\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[6\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[5\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[4\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[3\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[2\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI RAout\[0\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI BA\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI BA\[0\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI nRWEout_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI nCASout_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI nRASout_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI CKEout_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI Vout\[7\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI Vout\[6\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI Vout\[5\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI Vout\[4\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI Vout\[3\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI Vout\[2\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI Vout\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI Vout\[0\]_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI PHI1_MGIOL/CLK (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin - (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_9/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_69/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_80/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_105/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_23/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_50/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_51/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_56/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_66/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_70/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_81/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_85/B1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_89/C1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_98/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_109/A1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 SLICE_23/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_56/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_58/A0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_64/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_70/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_75/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_76/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_81/C0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_85/D1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_89/A1 (0:0:0)(0:0:0)) - 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(INTERCONNECT Ain\[7\]_I/PADDI ram2e_ufm\/SLICE_132/A0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_136/F0 nDOE_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F0 LED_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT PHI1_I/PADDI SLICE_139/A1 (0:0:0)(0:0:0)) - (INTERCONNECT PHI1_I/PADDI SLICE_139/A0 (0:0:0)(0:0:0)) - (INTERCONNECT PHI1_I/PADDI PHI1_MGIOL/DI (0:0:0)(0:0:0)) - (INTERCONNECT PHI1_MGIOL/IN SLICE_139/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_139/F1 nVOE_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_141/F0 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_141/F1 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_142/F0 RD\[4\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_143/F0 RD\[7\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_143/F1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_144/F0 RD\[6\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_144/F1 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F0 RD\[5\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[0\]_I/PADDI Vout\[0\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[11\]_MGIOL/IOLDO RAout\[11\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[10\]_MGIOL/IOLDO RAout\[10\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[9\]_MGIOL/IOLDO RAout\[9\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[8\]_MGIOL/IOLDO RAout\[8\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[7\]_MGIOL/IOLDO RAout\[7\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[6\]_MGIOL/IOLDO RAout\[6\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[5\]_MGIOL/IOLDO RAout\[5\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[4\]_MGIOL/IOLDO RAout\[4\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[3\]_MGIOL/IOLDO RAout\[3\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[2\]_MGIOL/IOLDO RAout\[2\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[1\]_MGIOL/IOLDO RAout\[1\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[0\]_MGIOL/IOLDO RAout\[0\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT nRWEout_MGIOL/IOLDO nRWEout_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT nCASout_MGIOL/IOLDO nCASout_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT nRASout_MGIOL/IOLDO nRASout_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT CKEout_MGIOL/IOLDO CKEout_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[4\]_MGIOL/IOLDO Vout\[4\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[3\]_MGIOL/IOLDO Vout\[3\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (0:0:0)(0:0:0)) - ) - ) - ) -) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo deleted file mode 100644 index 3fe5efa..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo +++ /dev/null @@ -1,7135 +0,0 @@ - -// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 - -// ldbanno -n Verilog -o RAM2E_LCMXO2_1200HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd -// Netlist created on Thu Dec 28 23:23:27 2023 -// Netlist written on Thu Dec 28 23:23:31 2023 -// Design is for device LCMXO2-1200HC -// Design is for package TQFP100 -// Design is for performance grade 4 - -`timescale 1 ns / 1 ps - -module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, - Vout, nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout, BA, - RAout, DQML, DQMH, RD ); - input C14M, PHI1, nWE, nWE80, nEN80, nC07X; - input [7:0] Ain; - input [7:0] Din; - output LED; - output [7:0] Dout; - output nDOE; - output [7:0] Vout; - output nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout; - output [1:0] BA; - output [11:0] RAout; - output DQML, DQMH; - inout [7:0] RD; - wire \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , - \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , - \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , - \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , - \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , - \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , - \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_551, - \S[1] , \S[0] , \ram2e_ufm/CKE_7 , CKE_7_RNIS77M1, CKE, - \ram2e_ufm/wb_adr_0_sqmuxa_1_i , RWSel, CO0_0, \CmdTout_3[0] , - N_185_i, GND, \RC[2] , CO0_1, \RC[1] , N_360_i, RC12, - \ram2e_ufm/N_821 , \ram2e_ufm/SUM1_0_0 , \ram2e_ufm/SUM0_i_a3_4_0 , - \ram2e_ufm/N_886 , \ram2e_ufm/N_215 , \ram2e_ufm/SUM0_i_4 , \CS[2] , - \CS[1] , CmdExecMXO2_3_0_a3_0_RNI6S1P8, N_547_i, un1_CS_0_sqmuxa_i, - \CS[0] , \ram2e_ufm/N_234 , CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514, - \ram2e_ufm/N_800 , \Din_c[5] , \Din_c[3] , - \ram2e_ufm/CmdLEDGet_3_0_a3_1 , \ram2e_ufm/N_847 , \Din_c[2] , - \Din_c[1] , CmdLEDGet_3, N_187_i, CmdLEDGet, \Din_c[7] , \Din_c[4] , - \ram2e_ufm/N_883 , CmdLEDSet_3, CmdLEDSet, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 , CmdRWMaskSet_3, CmdRWMaskSet, - \ram2e_ufm/N_850 , \Din_c[0] , CmdSetRWBankFFLED_4, CmdSetRWBankFFLED, - \CmdTout[2] , \CmdTout[1] , N_369_i, N_368_i, \RA[1] , - \ram2e_ufm/N_186 , \S[3] , N_1080_0, \ram2e_ufm/N_660 , DOEEN, - \ram2e_ufm/N_193 , \ram2e_ufm/N_659 , \ram2e_ufm/N_182 , \Ain_c[1] , - \ram2e_ufm/RA_35_0_0_1[0] , \ram2e_ufm/N_801 , \ram2e_ufm/N_684 , - N_223, \RA_35[0] , N_126, \RA[0] , \ram2e_ufm/RA_35_0_0_0[3] , - \ram2e_ufm/N_680 , \ram2e_ufm/N_679 , \Ain_c[2] , \RA_35[3] , - \RA_35[2] , \RA[2] , \RA[3] , \ram2e_ufm/RA_35_0_0_0[5] , - \ram2e_ufm/N_621 , \Ain_c[5] , \ram2e_ufm/RA_35_0_0_0[4] , \RA_35[5] , - \RA_35[4] , \RA[4] , \RA[5] , \ram2e_ufm/RA_35_0_0_0_0[7] , - \ram2e_ufm/RA_35_0_0_0_0[6] , \RA_35[7] , \RA_35[6] , \RA[6] , - \RA[7] , \ram2e_ufm/RA_35_0_0_0[9] , \RA[9] , \ram2e_ufm/N_242 , - \RA[8] , \ram2e_ufm/N_699 , \ram2e_ufm/N_698 , \ram2e_ufm/N_221 , - \RA_35[9] , un2_S_2_i_0_0_o3_RNIHFHN3, \RWBank[4] , \RA[11] , - \ram2e_ufm/N_845 , \ram2e_ufm/RA_35_2_0_0[10] , \ram2e_ufm/N_628 , - \ram2e_ufm/N_627 , \ram2e_ufm/N_624 , \RA_35[11] , \RA_35[10] , - \RA[10] , \RC_3[2] , \RC_3[1] , \ram2e_ufm/RWMask[1] , - \ram2e_ufm/N_188 , \ram2e_ufm/RWMask[0] , \RWBank_3[1] , - \RWBank_3[0] , \RWBank[0] , \RWBank[1] , \ram2e_ufm/RWMask[3] , - \ram2e_ufm/RWMask[2] , \RWBank_3[3] , \RWBank_3[2] , \RWBank[2] , - \RWBank[3] , \ram2e_ufm/RWMask[5] , \ram2e_ufm/RWMask[4] , - \RWBank_3[5] , \RWBank_3[4] , \RWBank[5] , \ram2e_ufm/RWMask[7] , - \ram2e_ufm/RWMask[6] , \Din_c[6] , \RWBank_3[7] , \RWBank_3[6] , - \RWBank[6] , \RWBank[7] , \Ain_c[3] , nWE_c, nC07X_c, RWSel_2, - un9_VOEEN_0_a2_0_a3_0_a3, \ram2e_ufm/Ready3_0_a3_5 , - \ram2e_ufm/Ready3_0_a3_4 , \ram2e_ufm/Ready3_0_a3_3 , - \ram2e_ufm/N_885 , Ready, Ready3, N_1026_0, \ram2e_ufm/S_r_i_0_o2[1] , - \ram2e_ufm/N_271 , \ram2e_ufm/N_194 , S_1, \ram2e_ufm/N_643 , N_362_i, - \S_s_0_0[0] , \S[2] , N_372_i, N_361_i, N_1078_0, VOEEN, BA_0_sqmuxa, - \ram2e_ufm/N_285_i , \ram2e_ufm/N_804 , \ram2e_ufm/N_872 , - \ram2e_ufm/N_641 , \ram2e_ufm/N_640 , N_370_i, nCAS, - \ram2e_ufm/nRAS_s_i_0_0 , \ram2e_ufm/N_617 , \ram2e_ufm/N_616 , - \ram2e_ufm/N_615 , N_358_i, nRAS, \ram2e_ufm/N_226 , - \ram2e_ufm/N_866 , \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] , N_359_i, nRWE, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 , - \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 , \ram2e_ufm/CmdBitbangMXO2_3 , - \ram2e_ufm/CmdBitbangMXO2 , \ram2e_ufm/N_851 , - \ram2e_ufm/CmdExecMXO2_3 , \ram2e_ufm/CmdExecMXO2 , - \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 , \ram2e_ufm/N_190 , - \ram2e_ufm/CmdSetRWBankFFChip_3 , \ram2e_ufm/CmdSetRWBankFFChip , - \ram2e_ufm/wb_dato[0] , \ram2e_ufm/N_295 , - \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] , \ram2e_ufm/LEDEN , - \ram2e_ufm/N_212 , \ram2e_ufm/wb_dato[1] , \ram2e_ufm/N_307_i , - \ram2e_ufm/N_309_i , \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] , - \ram2e_ufm/wb_dato[3] , \ram2e_ufm/wb_dato[2] , \ram2e_ufm/N_302_i , - \ram2e_ufm/N_304_i , \ram2e_ufm/wb_dato[5] , \ram2e_ufm/wb_dato[4] , - \ram2e_ufm/N_301_i , \ram2e_ufm/N_310_i , \ram2e_ufm/wb_dato[7] , - \ram2e_ufm/wb_dato[6] , \ram2e_ufm/N_296 , \ram2e_ufm/N_300_i , - \ram2e_ufm/wb_adr_7_5_41_0_1 , \ram2e_ufm/N_768 , - \ram2e_ufm/wb_adr_7_i_i_5[0] , \ram2e_ufm/wb_adr_7_i_i_4[0] , - \ram2e_ufm/N_793 , \ram2e_ufm/wb_adr_RNO[1] , - \ram2e_ufm/wb_adr_7_i_i[0] , \ram2e_ufm/CmdBitbangMXO2_RNINSM62 , - \ram2e_ufm/wb_adr[0] , \ram2e_ufm/wb_adr[1] , \ram2e_ufm/N_268_i , - \ram2e_ufm/N_80_i , \ram2e_ufm/wb_adr[2] , \ram2e_ufm/wb_adr[3] , - \ram2e_ufm/N_290 , \ram2e_ufm/N_294 , \ram2e_ufm/wb_adr[4] , - \ram2e_ufm/wb_adr[5] , \ram2e_ufm/N_267_i , \ram2e_ufm/N_284 , - \ram2e_ufm/wb_adr[6] , \ram2e_ufm/wb_adr[7] , \ram2e_ufm/wb_ack , - \ram2e_ufm/N_336 , \ram2e_ufm/N_687 , \ram2e_ufm/wb_cyc_stb_RNO , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] , - \ram2e_ufm/wb_cyc_stb , \ram2e_ufm/wb_dati_7_0_0_0[1] , - \ram2e_ufm/N_849 , \ram2e_ufm/N_611 , - \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] , \ram2e_ufm/N_856 , - \ram2e_ufm/wb_dati_7[1] , \ram2e_ufm/wb_dati_7[0] , - \ram2e_ufm/wb_dati[0] , \ram2e_ufm/wb_dati[1] , - \ram2e_ufm/wb_dati_7_0_0_0_0[3] , \ram2e_ufm/N_783 , - \ram2e_ufm/wb_dati_7_0_0_o3_0[2] , \ram2e_ufm/N_760 , - \ram2e_ufm/wb_dati_7[3] , \ram2e_ufm/wb_dati_7[2] , - \ram2e_ufm/wb_dati[2] , \ram2e_ufm/wb_dati[3] , - \ram2e_ufm/wb_dati_7_0_0_0[4] , \ram2e_ufm/N_763 , \ram2e_ufm/N_757 , - \ram2e_ufm/wb_dati_7[5] , \ram2e_ufm/wb_dati_7[4] , - \ram2e_ufm/wb_dati[4] , \ram2e_ufm/wb_dati[5] , - \ram2e_ufm/wb_dati_7_0_0_0_0[7] , \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] , - \ram2e_ufm/N_604 , \ram2e_ufm/N_602 , \ram2e_ufm/wb_dati_7_0_0_0[6] , - \ram2e_ufm/wb_dati_7[7] , \ram2e_ufm/wb_dati_7[6] , - \ram2e_ufm/wb_dati[6] , \ram2e_ufm/wb_dati[7] , \ram2e_ufm/wb_reqc_1 , - \ram2e_ufm/wb_reqc_i , \ram2e_ufm/wb_req , \ram2e_ufm/wb_rst8 , - \ram2e_ufm/wb_rst16_i , \ram2e_ufm/wb_rst , - \ram2e_ufm/wb_we_7_iv_0_0_3_0_0 , \ram2e_ufm/N_799 , - \ram2e_ufm/wb_we_7_iv_0_0_3_0_1 , \ram2e_ufm/N_208 , - \ram2e_ufm/wb_we_RNO , \ram2e_ufm/wb_we_RNO_0 , \ram2e_ufm/wb_we , - \ram2e_ufm/N_338 , \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 , \ram2e_ufm/N_817 , - \ram2e_ufm/CKE_7_sm0 , \ram2e_ufm/N_720_tz , \ram2e_ufm/SUM0_i_0 , - \ram2e_ufm/N_350 , \ram2e_ufm/SUM0_i_3 , \ram2e_ufm/SUM0_i_1 , - \ram2e_ufm/N_187 , \ram2e_ufm/N_755 , \ram2e_ufm/N_735 , - \ram2e_ufm/N_345 , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] , - \ram2e_ufm/N_777 , \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] , - \ram2e_ufm/N_250 , \ram2e_ufm/N_256 , \ram2e_ufm/wb_adr_7_i_i_3_1[0] , - \ram2e_ufm/wb_adr_7_i_i_3[0] , \ram2e_ufm/N_254 , \ram2e_ufm/N_807 , - \ram2e_ufm/N_876 , \ram2e_ufm/N_784 , \ram2e_ufm/N_560 , \BA_4[0] , - \ram2e_ufm/N_873 , \ram2e_ufm/N_781 , \ram2e_ufm/N_184 , - \ram2e_ufm/N_625 , \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] , - \ram2e_ufm/N_811 , \ram2e_ufm/N_206 , - \ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] , \ram2e_ufm/N_185 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S , \ram2e_ufm/N_637 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 , \ram2e_ufm/N_592 , - \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] , - \ram2e_ufm/wb_adr_7_i_i_1[0] , \ram2e_ufm/N_753 , \ram2e_ufm/N_634 , - \ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] , - \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] , - \ram2e_ufm/wb_dati_7_0_0_a3_1[6] , \ram2e_ufm/N_890 , - \ram2e_ufm/N_220 , \ram2e_ufm/N_196 , \ram2e_ufm/N_243 , \Ain_c[4] , - \Ain_c[6] , \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] , - \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] , \ram2e_ufm/N_565 , - \ram2e_ufm/CKE_7s2_0_0_0 , \ram2e_ufm/wb_adr_7_5_41_a3_3_0 , - \ram2e_ufm/N_204 , \ram2e_ufm/N_595 , \ram2e_ufm/nRWE_s_i_0_63_1 , - \ram2e_ufm/N_792 , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] , - \ram2e_ufm/N_553 , nEN80_c, \ram2e_ufm/N_241_i , \ram2e_ufm/N_814 , - N_225_i, N_201_i, N_507_i, N_508, Vout3, \BA_4[1] , \Ain_c[0] , - \Ain_c[7] , nDOE_c, LED_c, RDOE_i, PHI1_c, PHI1r, nVOE_c, N_263_i, - N_667, N_648, N_662, N_666, N_663, N_665, N_664, \RD_in[0] , - \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , - \RD_in[2] , \RD_in[1] , DQMH_c, DQML_c, \RAout_c[11] , \RAout_c[10] , - \RAout_c[9] , \RAout_c[8] , \RAout_c[7] , \RAout_c[6] , \RAout_c[5] , - \RAout_c[4] , \RAout_c[3] , \RAout_c[2] , \RAout_c[1] , \RAout_c[0] , - \BA_c[1] , \BA_c[0] , nRWEout_c, nCASout_c, nRASout_c, CKEout_c, - \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] , - \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , VCCI; - - SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), - .Q1(\FS[0] ), .FCO(\FS_cry[0] )); - SLICE_1 SLICE_1( .A0(\FS[15] ), .DI0(\FS_s[15] ), .CLK(C14M_c), - .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), .Q0(\FS[15] )); - SLICE_2 SLICE_2( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), - .DI0(\FS_s[13] ), .CLK(C14M_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), - .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] )); - SLICE_3 SLICE_3( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), - .DI0(\FS_s[11] ), .CLK(C14M_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), - .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] )); - SLICE_4 SLICE_4( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), - .DI0(\FS_s[9] ), .CLK(C14M_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), - .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] )); - SLICE_5 SLICE_5( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), - .DI0(\FS_s[7] ), .CLK(C14M_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), - .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] )); - SLICE_6 SLICE_6( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), - .DI0(\FS_s[5] ), .CLK(C14M_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), - .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] )); - SLICE_7 SLICE_7( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), - .DI0(\FS_s[3] ), .CLK(C14M_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), - .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] )); - SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), - .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), - .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); - SLICE_9 SLICE_9( .D1(N_551), .C1(\S[1] ), .B1(\S[0] ), .A1(\FS[15] ), - .D0(N_551), .C0(\S[1] ), .B0(\S[0] ), .A0(\ram2e_ufm/CKE_7 ), - .DI0(CKE_7_RNIS77M1), .CLK(C14M_c), .F0(CKE_7_RNIS77M1), .Q0(CKE), - .F1(\ram2e_ufm/wb_adr_0_sqmuxa_1_i )); - SLICE_10 SLICE_10( .B0(RWSel), .A0(CO0_0), .DI0(\CmdTout_3[0] ), - .CE(N_185_i), .CLK(C14M_c), .F0(\CmdTout_3[0] ), .Q0(CO0_0), .F1(GND)); - SLICE_11 SLICE_11( .B1(\RC[2] ), .A1(CO0_1), .C0(\RC[2] ), .B0(\RC[1] ), - .A0(CO0_1), .DI0(N_360_i), .CE(RC12), .CLK(C14M_c), .F0(N_360_i), - .Q0(CO0_1), .F1(\ram2e_ufm/N_821 )); - SLICE_12 SLICE_12( .D1(\ram2e_ufm/SUM1_0_0 ), .C1(\ram2e_ufm/SUM0_i_a3_4_0 ), - .B1(\ram2e_ufm/N_886 ), .A1(\ram2e_ufm/N_215 ), .D0(\ram2e_ufm/SUM0_i_4 ), - .C0(\ram2e_ufm/N_215 ), .B0(\CS[2] ), .A0(\CS[1] ), - .DI1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .DI0(N_547_i), - .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_547_i), .Q0(\CS[0] ), - .F1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .Q1(\CS[1] )); - SLICE_13 SLICE_13( .D1(\ram2e_ufm/N_234 ), .C1(\ram2e_ufm/N_215 ), - .B1(\CS[2] ), .A1(\CS[1] ), .D0(\ram2e_ufm/N_234 ), .C0(\ram2e_ufm/N_215 ), - .B0(\CS[2] ), .A0(\CS[1] ), .DI0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), - .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), - .F0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), .Q0(\CS[2] ), - .F1(\ram2e_ufm/SUM1_0_0 )); - SLICE_14 SLICE_14( .C1(\ram2e_ufm/N_800 ), .B1(\Din_c[5] ), .A1(\Din_c[3] ), - .D0(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ), .C0(\ram2e_ufm/N_847 ), - .B0(\Din_c[2] ), .A0(\Din_c[1] ), .DI0(CmdLEDGet_3), .CE(N_187_i), - .CLK(C14M_c), .F0(CmdLEDGet_3), .Q0(CmdLEDGet), .F1(\ram2e_ufm/N_847 )); - SLICE_15 SLICE_15( .C1(\Din_c[7] ), .B1(\Din_c[1] ), .A1(\CS[2] ), - .D0(\Din_c[4] ), .C0(\Din_c[7] ), .B0(\Din_c[1] ), .A0(\ram2e_ufm/N_883 ), - .DI0(CmdLEDSet_3), .CE(N_187_i), .CLK(C14M_c), .F0(CmdLEDSet_3), - .Q0(CmdLEDSet), .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 )); - SLICE_16 SLICE_16( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[3] ), - .A1(\Din_c[1] ), .D0(\Din_c[4] ), .C0(\Din_c[7] ), .B0(\Din_c[1] ), - .A0(\ram2e_ufm/N_883 ), .DI0(CmdRWMaskSet_3), .CE(N_187_i), .CLK(C14M_c), - .F0(CmdRWMaskSet_3), .Q0(CmdRWMaskSet), .F1(\ram2e_ufm/N_850 )); - SLICE_17 SLICE_17( .C1(\ram2e_ufm/N_847 ), .B1(\Din_c[2] ), .A1(\Din_c[0] ), - .D0(\ram2e_ufm/N_883 ), .C0(\Din_c[7] ), .B0(\Din_c[4] ), .A0(\Din_c[1] ), - .DI0(CmdSetRWBankFFLED_4), .CE(N_187_i), .CLK(C14M_c), - .F0(CmdSetRWBankFFLED_4), .Q0(CmdSetRWBankFFLED), .F1(\ram2e_ufm/N_883 )); - SLICE_18 SLICE_18( .D1(RWSel), .C1(\CmdTout[2] ), .B1(\CmdTout[1] ), - .A1(CO0_0), .C0(RWSel), .B0(\CmdTout[1] ), .A0(CO0_0), .DI1(N_369_i), - .DI0(N_368_i), .CE(N_185_i), .CLK(C14M_c), .F0(N_368_i), .Q0(\CmdTout[1] ), - .F1(N_369_i), .Q1(\CmdTout[2] )); - SLICE_19 SLICE_19( .B1(\CS[2] ), .A1(\CS[1] ), .B0(\RA[1] ), - .A0(\ram2e_ufm/N_186 ), .M0(\S[3] ), .LSR(N_1080_0), .CLK(C14M_c), - .F0(\ram2e_ufm/N_660 ), .Q0(DOEEN), .F1(\ram2e_ufm/N_193 )); - SLICE_20 SLICE_20( .D1(\ram2e_ufm/N_660 ), .C1(\ram2e_ufm/N_659 ), - .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[1] ), .D0(\ram2e_ufm/RA_35_0_0_1[0] ), - .C0(\ram2e_ufm/N_801 ), .B0(\ram2e_ufm/N_684 ), .A0(\FS[7] ), .DI1(N_223), - .DI0(\RA_35[0] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[0] ), .Q0(\RA[0] ), - .F1(N_223), .Q1(\RA[1] )); - SLICE_21 SLICE_21( .C1(\ram2e_ufm/RA_35_0_0_0[3] ), .B1(\ram2e_ufm/N_801 ), - .A1(\FS[10] ), .D0(\ram2e_ufm/N_680 ), .C0(\ram2e_ufm/N_679 ), - .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[2] ), .DI1(\RA_35[3] ), - .DI0(\RA_35[2] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[2] ), .Q0(\RA[2] ), - .F1(\RA_35[3] ), .Q1(\RA[3] )); - SLICE_22 SLICE_22( .D1(\ram2e_ufm/RA_35_0_0_0[5] ), .C1(\ram2e_ufm/N_621 ), - .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[5] ), .C0(\ram2e_ufm/RA_35_0_0_0[4] ), - .B0(\ram2e_ufm/N_801 ), .A0(\FS[11] ), .DI1(\RA_35[5] ), .DI0(\RA_35[4] ), - .CE(N_126), .CLK(C14M_c), .F0(\RA_35[4] ), .Q0(\RA[4] ), .F1(\RA_35[5] ), - .Q1(\RA[5] )); - SLICE_23 SLICE_23( .C1(\ram2e_ufm/RA_35_0_0_0_0[7] ), .B1(\ram2e_ufm/N_801 ), - .A1(\FS[14] ), .C0(\ram2e_ufm/RA_35_0_0_0_0[6] ), .B0(\ram2e_ufm/N_801 ), - .A0(\FS[13] ), .DI1(\RA_35[7] ), .DI0(\RA_35[6] ), .CE(N_126), - .CLK(C14M_c), .F0(\RA_35[6] ), .Q0(\RA[6] ), .F1(\RA_35[7] ), .Q1(\RA[7] )); - SLICE_24 SLICE_24( .C1(\ram2e_ufm/RA_35_0_0_0[9] ), .B1(\RA[9] ), - .A1(\ram2e_ufm/N_242 ), .D0(\RA[8] ), .C0(\ram2e_ufm/N_699 ), - .B0(\ram2e_ufm/N_698 ), .A0(\ram2e_ufm/N_221 ), .DI1(\RA_35[9] ), - .DI0(un2_S_2_i_0_0_o3_RNIHFHN3), .CE(N_126), .CLK(C14M_c), - .F0(un2_S_2_i_0_0_o3_RNIHFHN3), .Q0(\RA[8] ), .F1(\RA_35[9] ), - .Q1(\RA[9] )); - SLICE_25 SLICE_25( .D1(\RWBank[4] ), .C1(\RA[11] ), .B1(\ram2e_ufm/N_845 ), - .A1(\ram2e_ufm/N_242 ), .D0(\ram2e_ufm/RA_35_2_0_0[10] ), - .C0(\ram2e_ufm/N_628 ), .B0(\ram2e_ufm/N_627 ), .A0(\ram2e_ufm/N_624 ), - .DI1(\RA_35[11] ), .DI0(\RA_35[10] ), .CE(N_126), .CLK(C14M_c), - .F0(\RA_35[10] ), .Q0(\RA[10] ), .F1(\RA_35[11] ), .Q1(\RA[11] )); - SLICE_26 SLICE_26( .C1(\RC[2] ), .B1(\RC[1] ), .A1(CO0_1), .C0(\RC[2] ), - .B0(CO0_1), .A0(\RC[1] ), .DI1(\RC_3[2] ), .DI0(\RC_3[1] ), .CE(RC12), - .CLK(C14M_c), .F0(\RC_3[1] ), .Q0(\RC[1] ), .F1(\RC_3[2] ), .Q1(\RC[2] )); - SLICE_27 SLICE_27( .C1(\ram2e_ufm/RWMask[1] ), .B1(\ram2e_ufm/N_188 ), - .A1(\Din_c[1] ), .C0(\ram2e_ufm/RWMask[0] ), .B0(\ram2e_ufm/N_188 ), - .A0(\Din_c[0] ), .DI1(\RWBank_3[1] ), .DI0(\RWBank_3[0] ), .CE(N_187_i), - .CLK(C14M_c), .F0(\RWBank_3[0] ), .Q0(\RWBank[0] ), .F1(\RWBank_3[1] ), - .Q1(\RWBank[1] )); - SLICE_28 SLICE_28( .C1(\ram2e_ufm/RWMask[3] ), .B1(\ram2e_ufm/N_188 ), - .A1(\Din_c[3] ), .C0(\ram2e_ufm/RWMask[2] ), .B0(\ram2e_ufm/N_188 ), - .A0(\Din_c[2] ), .DI1(\RWBank_3[3] ), .DI0(\RWBank_3[2] ), .CE(N_187_i), - .CLK(C14M_c), .F0(\RWBank_3[2] ), .Q0(\RWBank[2] ), .F1(\RWBank_3[3] ), - .Q1(\RWBank[3] )); - SLICE_29 SLICE_29( .C1(\ram2e_ufm/RWMask[5] ), .B1(\ram2e_ufm/N_188 ), - .A1(\Din_c[5] ), .C0(\ram2e_ufm/RWMask[4] ), .B0(\ram2e_ufm/N_188 ), - .A0(\Din_c[4] ), .DI1(\RWBank_3[5] ), .DI0(\RWBank_3[4] ), .CE(N_187_i), - .CLK(C14M_c), .F0(\RWBank_3[4] ), .Q0(\RWBank[4] ), .F1(\RWBank_3[5] ), - .Q1(\RWBank[5] )); - SLICE_30 SLICE_30( .C1(\ram2e_ufm/RWMask[7] ), .B1(\ram2e_ufm/N_188 ), - .A1(\Din_c[7] ), .C0(\ram2e_ufm/RWMask[6] ), .B0(\ram2e_ufm/N_188 ), - .A0(\Din_c[6] ), .DI1(\RWBank_3[7] ), .DI0(\RWBank_3[6] ), .CE(N_187_i), - .CLK(C14M_c), .F0(\RWBank_3[6] ), .Q0(\RWBank[6] ), .F1(\RWBank_3[7] ), - .Q1(\RWBank[7] )); - SLICE_31 SLICE_31( .D1(\RA[3] ), .C1(\ram2e_ufm/N_186 ), - .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[3] ), .D0(nWE_c), .C0(nC07X_c), - .B0(\RA[3] ), .A0(\RA[0] ), .DI0(RWSel_2), .CE(un9_VOEEN_0_a2_0_a3_0_a3), - .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(\ram2e_ufm/RA_35_0_0_0[3] )); - SLICE_32 SLICE_32( .D1(\ram2e_ufm/Ready3_0_a3_5 ), - .C1(\ram2e_ufm/Ready3_0_a3_4 ), .B1(\ram2e_ufm/Ready3_0_a3_3 ), - .A1(\ram2e_ufm/N_885 ), .B0(Ready), .A0(Ready3), .DI0(N_1026_0), - .CLK(C14M_c), .F0(N_1026_0), .Q0(Ready), .F1(Ready3)); - SLICE_33 SLICE_33( .D1(\ram2e_ufm/S_r_i_0_o2[1] ), .C1(\ram2e_ufm/N_271 ), - .B1(\ram2e_ufm/N_194 ), .A1(S_1), .D0(\S[1] ), .C0(\ram2e_ufm/N_643 ), - .B0(\ram2e_ufm/N_271 ), .A0(S_1), .DI1(N_362_i), .DI0(\S_s_0_0[0] ), - .CLK(C14M_c), .F0(\S_s_0_0[0] ), .Q0(\S[0] ), .F1(N_362_i), .Q1(\S[1] )); - SLICE_34 SLICE_34( .D1(\S[2] ), .C1(S_1), .B1(\ram2e_ufm/N_194 ), - .A1(\S[3] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\ram2e_ufm/N_194 ), .A0(S_1), - .DI1(N_372_i), .DI0(N_361_i), .CLK(C14M_c), .F0(N_361_i), .Q0(\S[2] ), - .F1(N_372_i), .Q1(\S[3] )); - SLICE_35 SLICE_35( .D1(N_551), .C1(\S[1] ), .B1(\S[0] ), .A1(\FS[4] ), - .B0(\S[3] ), .A0(\S[2] ), .DI0(N_551), .LSR(N_1078_0), .CLK(C14M_c), - .F0(N_551), .Q0(VOEEN), .F1(BA_0_sqmuxa)); - SLICE_36 SLICE_36( .D1(\ram2e_ufm/N_285_i ), .C1(\S[0] ), .B1(\S[1] ), - .A1(\ram2e_ufm/N_804 ), .D0(nWE_c), .C0(\ram2e_ufm/N_872 ), - .B0(\ram2e_ufm/N_641 ), .A0(\ram2e_ufm/N_640 ), .DI0(N_370_i), - .CLK(C14M_c), .F0(N_370_i), .Q0(nCAS), .F1(\ram2e_ufm/N_872 )); - SLICE_37 SLICE_37( .D1(\S[0] ), .C1(\S[1] ), .B1(\ram2e_ufm/N_285_i ), - .A1(\ram2e_ufm/N_804 ), .D0(\ram2e_ufm/nRAS_s_i_0_0 ), - .C0(\ram2e_ufm/N_617 ), .B0(\ram2e_ufm/N_616 ), .A0(\ram2e_ufm/N_615 ), - .DI0(N_358_i), .CLK(C14M_c), .F0(N_358_i), .Q0(nRAS), - .F1(\ram2e_ufm/N_617 )); - SLICE_38 SLICE_38( .D1(\S[2] ), .C1(\ram2e_ufm/S_r_i_0_o2[1] ), - .B1(\ram2e_ufm/N_226 ), .A1(\ram2e_ufm/N_285_i ), .D0(\ram2e_ufm/N_804 ), - .C0(\ram2e_ufm/N_866 ), .B0(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ), - .A0(\ram2e_ufm/N_615 ), .DI0(N_359_i), .CLK(C14M_c), .F0(N_359_i), - .Q0(nRWE), .F1(\ram2e_ufm/N_615 )); - ram2e_ufm_SLICE_39 \ram2e_ufm/SLICE_39 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ), - .B1(\Din_c[0] ), .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), - .D0(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ), .C0(\ram2e_ufm/N_800 ), - .B0(\Din_c[2] ), .A0(\Din_c[1] ), .DI0(\ram2e_ufm/CmdBitbangMXO2_3 ), - .CE(N_187_i), .CLK(C14M_c), .F0(\ram2e_ufm/CmdBitbangMXO2_3 ), - .Q0(\ram2e_ufm/CmdBitbangMXO2 ), .F1(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 )); - ram2e_ufm_SLICE_40 \ram2e_ufm/SLICE_40 ( .D1(\CS[1] ), .C1(\CS[2] ), - .B1(\CS[0] ), .A1(\Din_c[6] ), .B0(\ram2e_ufm/N_851 ), - .A0(\ram2e_ufm/N_800 ), .DI0(\ram2e_ufm/CmdExecMXO2_3 ), .CE(N_187_i), - .CLK(C14M_c), .F0(\ram2e_ufm/CmdExecMXO2_3 ), .Q0(\ram2e_ufm/CmdExecMXO2 ), - .F1(\ram2e_ufm/N_800 )); - ram2e_ufm_SLICE_41 \ram2e_ufm/SLICE_41 ( .D1(\Din_c[0] ), .C1(\Din_c[1] ), - .B1(\Din_c[2] ), .A1(\Din_c[4] ), - .D0(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ), .C0(\ram2e_ufm/N_800 ), - .B0(\ram2e_ufm/N_190 ), .A0(\Din_c[7] ), - .DI0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .CE(N_187_i), .CLK(C14M_c), - .F0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .Q0(\ram2e_ufm/CmdSetRWBankFFChip ), - .F1(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 )); - ram2e_ufm_SLICE_42 \ram2e_ufm/SLICE_42 ( .C1(\Din_c[6] ), .B1(\Din_c[2] ), - .A1(\Din_c[0] ), .C0(\ram2e_ufm/wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), - .DI0(\ram2e_ufm/N_295 ), .CE(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_295 ), .Q0(\ram2e_ufm/LEDEN ), - .F1(\ram2e_ufm/N_212 )); - ram2e_ufm_SLICE_43 \ram2e_ufm/SLICE_43 ( .C1(\ram2e_ufm/wb_dato[1] ), - .B1(\S[3] ), .A1(\Din_c[1] ), .C0(\ram2e_ufm/wb_dato[0] ), .B0(\S[3] ), - .A0(\Din_c[0] ), .DI1(\ram2e_ufm/N_307_i ), .DI0(\ram2e_ufm/N_309_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_309_i ), .Q0(\ram2e_ufm/RWMask[0] ), - .F1(\ram2e_ufm/N_307_i ), .Q1(\ram2e_ufm/RWMask[1] )); - ram2e_ufm_SLICE_44 \ram2e_ufm/SLICE_44 ( .C1(\ram2e_ufm/wb_dato[3] ), - .B1(\S[3] ), .A1(\Din_c[3] ), .C0(\ram2e_ufm/wb_dato[2] ), .B0(\S[3] ), - .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_302_i ), .DI0(\ram2e_ufm/N_304_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_304_i ), .Q0(\ram2e_ufm/RWMask[2] ), - .F1(\ram2e_ufm/N_302_i ), .Q1(\ram2e_ufm/RWMask[3] )); - ram2e_ufm_SLICE_45 \ram2e_ufm/SLICE_45 ( .C1(\ram2e_ufm/wb_dato[5] ), - .B1(\S[3] ), .A1(\Din_c[5] ), .C0(\ram2e_ufm/wb_dato[4] ), .B0(\S[3] ), - .A0(\Din_c[4] ), .DI1(\ram2e_ufm/N_301_i ), .DI0(\ram2e_ufm/N_310_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_310_i ), .Q0(\ram2e_ufm/RWMask[4] ), - .F1(\ram2e_ufm/N_301_i ), .Q1(\ram2e_ufm/RWMask[5] )); - ram2e_ufm_SLICE_46 \ram2e_ufm/SLICE_46 ( .C1(\ram2e_ufm/wb_dato[7] ), - .B1(\S[3] ), .A1(\Din_c[7] ), .C0(\ram2e_ufm/wb_dato[6] ), .B0(\S[3] ), - .A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_296 ), .DI0(\ram2e_ufm/N_300_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_300_i ), .Q0(\ram2e_ufm/RWMask[6] ), - .F1(\ram2e_ufm/N_296 ), .Q1(\ram2e_ufm/RWMask[7] )); - ram2e_ufm_SLICE_47 \ram2e_ufm/SLICE_47 ( .D1(\ram2e_ufm/wb_adr_7_5_41_0_1 ), - .C1(\S[2] ), .B1(\ram2e_ufm/N_768 ), .A1(\Din_c[1] ), - .D0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), - .B0(\ram2e_ufm/N_793 ), .A0(\FS[10] ), .DI1(\ram2e_ufm/wb_adr_RNO[1] ), - .DI0(\ram2e_ufm/wb_adr_7_i_i[0] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_adr_7_i_i[0] ), .Q0(\ram2e_ufm/wb_adr[0] ), - .F1(\ram2e_ufm/wb_adr_RNO[1] ), .Q1(\ram2e_ufm/wb_adr[1] )); - ram2e_ufm_SLICE_48 \ram2e_ufm/SLICE_48 ( .B1(\S[2] ), .A1(\Din_c[3] ), - .B0(\S[2] ), .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_268_i ), - .DI0(\ram2e_ufm/N_80_i ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_80_i ), .Q0(\ram2e_ufm/wb_adr[2] ), - .F1(\ram2e_ufm/N_268_i ), .Q1(\ram2e_ufm/wb_adr[3] )); - ram2e_ufm_SLICE_49 \ram2e_ufm/SLICE_49 ( .C1(\S[2] ), .B1(\FS[14] ), - .A1(\Din_c[5] ), .C0(\S[2] ), .B0(\FS[14] ), .A0(\Din_c[4] ), - .DI1(\ram2e_ufm/N_290 ), .DI0(\ram2e_ufm/N_294 ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_294 ), .Q0(\ram2e_ufm/wb_adr[4] ), .F1(\ram2e_ufm/N_290 ), - .Q1(\ram2e_ufm/wb_adr[5] )); - ram2e_ufm_SLICE_50 \ram2e_ufm/SLICE_50 ( .B1(\S[2] ), .A1(\Din_c[7] ), - .C0(\S[2] ), .B0(\FS[14] ), .A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_267_i ), - .DI0(\ram2e_ufm/N_284 ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_284 ), .Q0(\ram2e_ufm/wb_adr[6] ), - .F1(\ram2e_ufm/N_267_i ), .Q1(\ram2e_ufm/wb_adr[7] )); - ram2e_ufm_SLICE_51 \ram2e_ufm/SLICE_51 ( .D1(\ram2e_ufm/wb_ack ), - .C1(\ram2e_ufm/N_336 ), .B1(\FS[14] ), .A1(\FS[0] ), - .C0(\ram2e_ufm/CmdExecMXO2 ), .B0(\S[3] ), .A0(\ram2e_ufm/N_687 ), - .DI0(\ram2e_ufm/wb_cyc_stb_RNO ), - .CE(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_cyc_stb_RNO ), .Q0(\ram2e_ufm/wb_cyc_stb ), - .F1(\ram2e_ufm/N_687 )); - ram2e_ufm_SLICE_52 \ram2e_ufm/SLICE_52 ( .D1(\ram2e_ufm/wb_dati_7_0_0_0[1] ), - .C1(\ram2e_ufm/N_849 ), .B1(\ram2e_ufm/N_793 ), .A1(\ram2e_ufm/N_611 ), - .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ), .C0(\ram2e_ufm/wb_adr[0] ), - .B0(\S[2] ), .A0(\ram2e_ufm/N_856 ), .DI1(\ram2e_ufm/wb_dati_7[1] ), - .DI0(\ram2e_ufm/wb_dati_7[0] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[0] ), .Q0(\ram2e_ufm/wb_dati[0] ), - .F1(\ram2e_ufm/wb_dati_7[1] ), .Q1(\ram2e_ufm/wb_dati[1] )); - ram2e_ufm_SLICE_53 \ram2e_ufm/SLICE_53 ( - .D1(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .C1(\ram2e_ufm/N_849 ), - .B1(\ram2e_ufm/N_783 ), .A1(\ram2e_ufm/N_611 ), - .D0(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C0(\ram2e_ufm/wb_adr[2] ), - .B0(\S[2] ), .A0(\ram2e_ufm/N_760 ), .DI1(\ram2e_ufm/wb_dati_7[3] ), - .DI0(\ram2e_ufm/wb_dati_7[2] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[2] ), .Q0(\ram2e_ufm/wb_dati[2] ), - .F1(\ram2e_ufm/wb_dati_7[3] ), .Q1(\ram2e_ufm/wb_dati[3] )); - ram2e_ufm_SLICE_54 \ram2e_ufm/SLICE_54 ( - .D1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C1(\ram2e_ufm/wb_adr[5] ), - .B1(\S[2] ), .A1(\ram2e_ufm/N_760 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0[4] ), - .C0(\ram2e_ufm/N_763 ), .B0(\ram2e_ufm/N_760 ), .A0(\ram2e_ufm/N_757 ), - .DI1(\ram2e_ufm/wb_dati_7[5] ), .DI0(\ram2e_ufm/wb_dati_7[4] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_dati_7[4] ), .Q0(\ram2e_ufm/wb_dati[4] ), - .F1(\ram2e_ufm/wb_dati_7[5] ), .Q1(\ram2e_ufm/wb_dati[5] )); - ram2e_ufm_SLICE_55 \ram2e_ufm/SLICE_55 ( - .D1(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), - .C1(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), .B1(\ram2e_ufm/N_604 ), - .A1(\ram2e_ufm/N_602 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), - .C0(\ram2e_ufm/N_849 ), .B0(\ram2e_ufm/N_793 ), .A0(\ram2e_ufm/N_757 ), - .DI1(\ram2e_ufm/wb_dati_7[7] ), .DI0(\ram2e_ufm/wb_dati_7[6] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_dati_7[6] ), .Q0(\ram2e_ufm/wb_dati[6] ), - .F1(\ram2e_ufm/wb_dati_7[7] ), .Q1(\ram2e_ufm/wb_dati[7] )); - ram2e_ufm_SLICE_56 \ram2e_ufm/SLICE_56 ( .D1(\S[3] ), .C1(\S[1] ), - .B1(\S[0] ), .A1(\FS[14] ), .D0(\ram2e_ufm/wb_reqc_1 ), .C0(\FS[13] ), - .B0(\FS[12] ), .A0(\FS[11] ), .DI0(\ram2e_ufm/wb_reqc_i ), - .CE(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ), .LSR(\S[2] ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_reqc_i ), .Q0(\ram2e_ufm/wb_req ), - .F1(\ram2e_ufm/wb_reqc_1 )); - ram2e_ufm_SLICE_57 \ram2e_ufm/SLICE_57 ( .D1(\FS[15] ), .C1(\FS[14] ), - .B1(\FS[4] ), .A1(\FS[2] ), .B0(\FS[15] ), .A0(\FS[14] ), - .DI0(\ram2e_ufm/wb_rst8 ), .LSR(\ram2e_ufm/wb_rst16_i ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_rst8 ), .Q0(\ram2e_ufm/wb_rst ), - .F1(\ram2e_ufm/Ready3_0_a3_4 )); - ram2e_ufm_SLICE_58 \ram2e_ufm/SLICE_58 ( - .D1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), .C1(\ram2e_ufm/N_885 ), - .B1(\ram2e_ufm/N_799 ), .A1(\FS[12] ), - .D0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ), .C0(\ram2e_ufm/N_799 ), - .B0(\ram2e_ufm/N_208 ), .A0(\FS[13] ), .DI0(\ram2e_ufm/wb_we_RNO ), - .CE(\ram2e_ufm/wb_we_RNO_0 ), .CLK(C14M_c), .F0(\ram2e_ufm/wb_we_RNO ), - .Q0(\ram2e_ufm/wb_we ), .F1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 )); - ram2e_ufm_SUM0_i_m3_0_SLICE_59 \ram2e_ufm/SUM0_i_m3_0/SLICE_59 ( - .C1(\CS[1] ), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .C0(\Din_c[7] ), - .B0(\Din_c[5] ), .A0(\Din_c[3] ), .M0(\Din_c[1] ), - .OFX0(\ram2e_ufm/N_338 )); - ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60 ( .D1(\CS[0] ), .C1(\Din_c[6] ), - .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), .A1(\ram2e_ufm/N_193 ), - .C0(CO0_0), .B0(\CmdTout[1] ), .A0(\CmdTout[2] ), .M0(RWSel), - .OFX0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 )); - ram2e_ufm_CKE_7_SLICE_61 \ram2e_ufm/CKE_7/SLICE_61 ( .C1(\RC[1] ), - .B1(\ram2e_ufm/N_821 ), .A1(\ram2e_ufm/N_817 ), .C0(nWE_c), .B0(\S[1] ), - .A0(\ram2e_ufm/N_804 ), .M0(\ram2e_ufm/CKE_7_sm0 ), - .OFX0(\ram2e_ufm/CKE_7 )); - ram2e_ufm_SLICE_62 \ram2e_ufm/SLICE_62 ( .D1(\ram2e_ufm/N_851 ), - .C1(\Din_c[6] ), .B1(\CS[2] ), .A1(\CS[1] ), - .D0(\ram2e_ufm/SUM0_i_a3_4_0 ), .C0(\ram2e_ufm/N_234 ), .B0(\CS[2] ), - .A0(\CS[1] ), .F0(\ram2e_ufm/N_720_tz ), .F1(\ram2e_ufm/SUM0_i_a3_4_0 )); - ram2e_ufm_SLICE_63 \ram2e_ufm/SLICE_63 ( .D1(\ram2e_ufm/SUM0_i_0 ), - .C1(\ram2e_ufm/N_350 ), .B1(\CS[2] ), .A1(\CS[0] ), - .D0(\ram2e_ufm/SUM0_i_3 ), .C0(\ram2e_ufm/SUM0_i_1 ), - .B0(\ram2e_ufm/N_187 ), .A0(\CS[0] ), .F0(\ram2e_ufm/SUM0_i_4 ), - .F1(\ram2e_ufm/SUM0_i_1 )); - ram2e_ufm_SLICE_64 \ram2e_ufm/SLICE_64 ( .C1(\ram2e_ufm/N_793 ), - .B1(\FS[11] ), .A1(\FS[9] ), .D0(\ram2e_ufm/N_856 ), - .C0(\ram2e_ufm/N_755 ), .B0(\FS[13] ), .A0(\FS[11] ), - .F0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .F1(\ram2e_ufm/N_755 )); - ram2e_ufm_SLICE_65 \ram2e_ufm/SLICE_65 ( .D1(\ram2e_ufm/N_193 ), - .C1(\Din_c[6] ), .B1(\Din_c[0] ), .A1(\CS[0] ), .D0(\ram2e_ufm/N_735 ), - .C0(\ram2e_ufm/N_345 ), .B0(\CS[1] ), .A0(\CS[0] ), - .F0(\ram2e_ufm/SUM0_i_0 ), .F1(\ram2e_ufm/N_735 )); - ram2e_ufm_SLICE_66 \ram2e_ufm/SLICE_66 ( .D1(\ram2e_ufm/wb_ack ), - .C1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), - .B1(\ram2e_ufm/N_777 ), .A1(\FS[14] ), .D0(\ram2e_ufm/wb_ack ), - .C0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ), - .B0(\ram2e_ufm/CmdExecMXO2 ), .A0(\ram2e_ufm/N_187 ), - .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), - .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] )); - ram2e_ufm_SLICE_67 \ram2e_ufm/SLICE_67 ( .C1(\FS[3] ), .B1(\FS[2] ), - .A1(\FS[1] ), .D0(\S[1] ), .C0(\ram2e_ufm/N_250 ), .B0(\FS[4] ), - .A0(\FS[3] ), .F0(\ram2e_ufm/N_256 ), .F1(\ram2e_ufm/N_250 )); - ram2e_ufm_SLICE_68 \ram2e_ufm/SLICE_68 ( - .D1(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .C1(\ram2e_ufm/N_783 ), .B1(\FS[9] ), - .A1(\FS[8] ), .D0(\FS[12] ), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[8] ), - .F0(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .F1(\ram2e_ufm/wb_adr_7_i_i_3[0] )); - ram2e_ufm_SLICE_69 \ram2e_ufm/SLICE_69 ( .D1(\ram2e_ufm/N_254 ), - .C1(\ram2e_ufm/wb_rst16_i ), .B1(\FS[15] ), .A1(\FS[0] ), .D0(\S[2] ), - .C0(\S[3] ), .B0(\S[1] ), .A0(\S[0] ), .F0(\ram2e_ufm/wb_rst16_i ), - .F1(\ram2e_ufm/N_641 )); - ram2e_ufm_SLICE_70 \ram2e_ufm/SLICE_70 ( .C1(\FS[14] ), - .B1(\ram2e_ufm/N_777 ), .A1(\FS[8] ), .D0(\FS[12] ), .C0(\FS[13] ), - .B0(\ram2e_ufm/N_807 ), .A0(\ram2e_ufm/N_876 ), .F0(\ram2e_ufm/N_604 ), - .F1(\ram2e_ufm/N_807 )); - ram2e_ufm_SLICE_71 \ram2e_ufm/SLICE_71 ( .C1(\FS[4] ), - .B1(\ram2e_ufm/N_784 ), .A1(\FS[3] ), .C0(\S[2] ), .B0(\S[3] ), - .A0(\S[0] ), .F0(\ram2e_ufm/N_784 ), .F1(\ram2e_ufm/N_801 )); - ram2e_ufm_SLICE_72 \ram2e_ufm/SLICE_72 ( .D1(\S[0] ), .C1(\RWBank[5] ), - .B1(\ram2e_ufm/N_560 ), .A1(\FS[4] ), .C0(\S[2] ), .B0(\S[3] ), - .A0(\S[1] ), .F0(\ram2e_ufm/N_560 ), .F1(\BA_4[0] )); - ram2e_ufm_SLICE_73 \ram2e_ufm/SLICE_73 ( .D1(\ram2e_ufm/N_873 ), - .C1(\ram2e_ufm/N_781 ), .B1(\ram2e_ufm/N_611 ), .A1(\ram2e_ufm/N_184 ), - .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), - .F0(\ram2e_ufm/N_873 ), .F1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] )); - ram2e_ufm_SLICE_74 \ram2e_ufm/SLICE_74 ( .C1(\RWBank[3] ), - .B1(\ram2e_ufm/N_845 ), .A1(\ram2e_ufm/N_625 ), .D0(\S[0] ), .C0(\S[1] ), - .B0(\S[2] ), .A0(\S[3] ), .F0(\ram2e_ufm/N_845 ), - .F1(\ram2e_ufm/RA_35_2_0_0[10] )); - ram2e_ufm_SLICE_75 \ram2e_ufm/SLICE_75 ( .C1(\FS[11] ), .B1(\FS[10] ), - .A1(\FS[9] ), .D0(\FS[12] ), .C0(\FS[13] ), .B0(\ram2e_ufm/N_876 ), - .A0(\ram2e_ufm/wb_ack ), - .F0(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), - .F1(\ram2e_ufm/N_876 )); - ram2e_ufm_SLICE_76 \ram2e_ufm/SLICE_76 ( .B1(\FS[11] ), .A1(\FS[10] ), - .D0(\FS[12] ), .C0(\FS[13] ), .B0(\ram2e_ufm/N_811 ), - .A0(\ram2e_ufm/N_206 ), .F0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), - .F1(\ram2e_ufm/N_811 )); - ram2e_ufm_SLICE_77 \ram2e_ufm/SLICE_77 ( .C1(\ram2e_ufm/N_185 ), .B1(RWSel), - .A1(\CS[0] ), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), - .F0(\ram2e_ufm/N_185 ), .F1(\ram2e_ufm/N_215 )); - ram2e_ufm_SLICE_78 \ram2e_ufm/SLICE_78 ( .B1(\S[1] ), .A1(\S[0] ), - .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\RWBank[1] ), - .F0(\ram2e_ufm/N_699 ), .F1(\ram2e_ufm/S_r_i_0_o2[1] )); - ram2e_ufm_SLICE_79 \ram2e_ufm/SLICE_79 ( - .D1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), - .C1(\ram2e_ufm/N_807 ), .B1(\ram2e_ufm/N_187 ), .A1(CmdLEDSet), - .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(RWSel), - .F0(\ram2e_ufm/N_187 ), .F1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] )); - ram2e_ufm_SLICE_80 \ram2e_ufm/SLICE_80 ( .D1(N_551), .C1(\S[1] ), - .B1(\S[0] ), .A1(\FS[15] ), .D0(\ram2e_ufm/N_185 ), .C0(RWSel), - .B0(\ram2e_ufm/N_777 ), .A0(\ram2e_ufm/CmdBitbangMXO2 ), - .F0(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .F1(\ram2e_ufm/N_777 )); - ram2e_ufm_SLICE_81 \ram2e_ufm/SLICE_81 ( .D1(\FS[8] ), - .C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), .A1(\FS[9] ), .D0(\FS[12] ), - .C0(\FS[13] ), .B0(\ram2e_ufm/N_811 ), .A0(\ram2e_ufm/N_856 ), - .F0(\ram2e_ufm/N_757 ), .F1(\ram2e_ufm/N_856 )); - ram2e_ufm_SLICE_82 \ram2e_ufm/SLICE_82 ( - .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ), - .C1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .B1(\Din_c[6] ), .A1(\CS[0] ), - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ), - .C0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), - .B0(\ram2e_ufm/N_637 ), .A0(\ram2e_ufm/N_185 ), .F0(un1_CS_0_sqmuxa_i), - .F1(\ram2e_ufm/N_637 )); - ram2e_ufm_SLICE_83 \ram2e_ufm/SLICE_83 ( .C1(\ram2e_ufm/N_851 ), - .B1(\Din_c[6] ), .A1(\CS[2] ), .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ), - .C0(RWSel), .B0(\ram2e_ufm/N_592 ), .A0(\CS[0] ), - .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 )); - ram2e_ufm_SLICE_84 \ram2e_ufm/SLICE_84 ( .D1(\ram2e_ufm/N_850 ), - .C1(\ram2e_ufm/N_212 ), .B1(\Din_c[4] ), .A1(\CS[2] ), - .D0(\ram2e_ufm/N_886 ), .C0(\ram2e_ufm/N_720_tz ), .B0(\ram2e_ufm/N_187 ), - .A0(\CS[1] ), .F0(\ram2e_ufm/SUM0_i_3 ), .F1(\ram2e_ufm/N_886 )); - ram2e_ufm_SLICE_85 \ram2e_ufm/SLICE_85 ( .D1(\FS[13] ), - .C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), .A1(\FS[12] ), - .D0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), - .C0(\ram2e_ufm/N_793 ), .B0(\ram2e_ufm/N_187 ), .A0(CmdRWMaskSet), - .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .F1(\ram2e_ufm/N_793 )); - ram2e_ufm_SLICE_86 \ram2e_ufm/SLICE_86 ( .B1(\S[2] ), .A1(\Din_c[0] ), - .D0(\ram2e_ufm/wb_adr_7_i_i_3[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), - .B0(\ram2e_ufm/N_753 ), .A0(\ram2e_ufm/N_634 ), - .F0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), .F1(\ram2e_ufm/N_634 )); - ram2e_ufm_SLICE_87 \ram2e_ufm/SLICE_87 ( - .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C1(\ram2e_ufm/N_212 ), - .B1(\ram2e_ufm/N_190 ), .A1(\Din_c[1] ), .C0(\ram2e_ufm/N_886 ), - .B0(\ram2e_ufm/N_234 ), .A0(\CS[1] ), .F0(\ram2e_ufm/N_592 ), - .F1(\ram2e_ufm/N_234 )); - ram2e_ufm_SLICE_88 \ram2e_ufm/SLICE_88 ( .B1(\FS[11] ), .A1(\FS[10] ), - .D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\ram2e_ufm/N_876 ), - .B0(\ram2e_ufm/N_793 ), .A0(\ram2e_ufm/N_206 ), - .F0(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] )); - ram2e_ufm_SLICE_89 \ram2e_ufm/SLICE_89 ( .C1(\FS[14] ), - .B1(\ram2e_ufm/N_777 ), .A1(\FS[13] ), - .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .C0(\ram2e_ufm/wb_adr[3] ), - .B0(\S[2] ), .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), - .F1(\ram2e_ufm/N_783 )); - ram2e_ufm_SLICE_90 \ram2e_ufm/SLICE_90 ( .D1(\ram2e_ufm/N_206 ), - .C1(\FS[12] ), .B1(\FS[11] ), .A1(\FS[10] ), - .D0(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ), .C0(\ram2e_ufm/wb_adr[6] ), - .B0(\S[2] ), .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] )); - ram2e_ufm_SLICE_91 \ram2e_ufm/SLICE_91 ( .D1(CO0_1), .C1(\RC[2] ), - .B1(\ram2e_ufm/N_817 ), .A1(\RC[1] ), .D0(\ram2e_ufm/N_890 ), - .C0(\ram2e_ufm/N_784 ), .B0(\ram2e_ufm/N_256 ), .A0(\ram2e_ufm/N_285_i ), - .F0(\ram2e_ufm/nRAS_s_i_0_0 ), .F1(\ram2e_ufm/N_890 )); - ram2e_ufm_SLICE_92 \ram2e_ufm/SLICE_92 ( .D1(nWE_c), .C1(\S[1] ), - .B1(\ram2e_ufm/N_804 ), .A1(N_551), .D0(\S[0] ), .C0(\ram2e_ufm/N_890 ), - .B0(\ram2e_ufm/N_220 ), .A0(\ram2e_ufm/N_285_i ), .F0(\ram2e_ufm/N_640 ), - .F1(\ram2e_ufm/N_220 )); - ram2e_ufm_SLICE_93 \ram2e_ufm/SLICE_93 ( .D1(\FS[11] ), .C1(\FS[10] ), - .B1(\FS[9] ), .A1(\FS[8] ), .C0(\ram2e_ufm/N_783 ), .B0(\ram2e_ufm/N_196 ), - .A0(\FS[12] ), .F0(\ram2e_ufm/N_760 ), .F1(\ram2e_ufm/N_196 )); - ram2e_ufm_SLICE_94 \ram2e_ufm/SLICE_94 ( .B1(\Din_c[7] ), .A1(\Din_c[4] ), - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C0(\ram2e_ufm/N_243 ), - .B0(\Din_c[0] ), .A0(\CS[2] ), .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 )); - ram2e_ufm_SLICE_95 \ram2e_ufm/SLICE_95 ( .D1(\S[3] ), .C1(\S[2] ), - .B1(\S[1] ), .A1(\S[0] ), .D0(\RA[4] ), .C0(\ram2e_ufm/N_186 ), - .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[4] ), .F0(\ram2e_ufm/RA_35_0_0_0[4] ), - .F1(\ram2e_ufm/N_182 )); - ram2e_ufm_SLICE_96 \ram2e_ufm/SLICE_96 ( .D1(\S[3] ), .C1(\S[2] ), - .B1(\S[1] ), .A1(\S[0] ), .D0(\RA[6] ), .C0(\ram2e_ufm/N_186 ), - .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[6] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[6] ), - .F1(\ram2e_ufm/N_186 )); - ram2e_ufm_SLICE_97 \ram2e_ufm/SLICE_97 ( .C1(\ram2e_ufm/N_873 ), - .B1(\FS[13] ), .A1(\FS[12] ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ), - .C0(\ram2e_ufm/wb_adr[1] ), .B0(\S[2] ), .A0(\ram2e_ufm/N_781 ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0[1] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] )); - ram2e_ufm_SLICE_98 \ram2e_ufm/SLICE_98 ( .B1(\ram2e_ufm/N_777 ), - .A1(\FS[14] ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), - .C0(\ram2e_ufm/wb_adr[7] ), .B0(\S[2] ), .A0(\ram2e_ufm/N_781 ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), .F1(\ram2e_ufm/N_781 )); - ram2e_ufm_SLICE_99 \ram2e_ufm/SLICE_99 ( .C1(\FS[11] ), .B1(\FS[10] ), - .A1(\FS[8] ), .D0(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ), - .C0(\ram2e_ufm/N_781 ), .B0(\ram2e_ufm/N_565 ), .A0(\FS[12] ), - .F0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), - .F1(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] )); - ram2e_ufm_SLICE_100 \ram2e_ufm/SLICE_100 ( .D1(\Din_c[5] ), .C1(\Din_c[3] ), - .B1(\Din_c[2] ), .A1(\Din_c[1] ), .D0(\ram2e_ufm/N_243 ), .C0(\Din_c[7] ), - .B0(\Din_c[4] ), .A0(\CS[2] ), .F0(\ram2e_ufm/N_345 ), - .F1(\ram2e_ufm/N_243 )); - ram2e_ufm_SLICE_101 \ram2e_ufm/SLICE_101 ( .B1(\Din_c[5] ), .A1(\Din_c[3] ), - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ), .C0(\ram2e_ufm/N_850 ), - .B0(\ram2e_ufm/N_190 ), .A0(\CS[1] ), - .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .F1(\ram2e_ufm/N_190 )); - ram2e_ufm_SLICE_102 \ram2e_ufm/SLICE_102 ( .C1(\S[3] ), .B1(\S[2] ), - .A1(\S[1] ), .C0(\ram2e_ufm/CKE_7s2_0_0_0 ), .B0(\ram2e_ufm/N_817 ), - .A0(\ram2e_ufm/N_220 ), .F0(\ram2e_ufm/CKE_7_sm0 ), .F1(\ram2e_ufm/N_817 )); - ram2e_ufm_SLICE_103 \ram2e_ufm/SLICE_103 ( .B1(\FS[13] ), .A1(\FS[12] ), - .D0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), .C0(\ram2e_ufm/N_799 ), - .B0(\ram2e_ufm/N_204 ), .A0(\ram2e_ufm/N_184 ), - .F0(\ram2e_ufm/wb_adr_7_5_41_0_1 ), .F1(\ram2e_ufm/N_184 )); - ram2e_ufm_SLICE_104 \ram2e_ufm/SLICE_104 ( .D1(\FS[11] ), .C1(\FS[10] ), - .B1(\FS[9] ), .A1(\FS[8] ), .B0(\ram2e_ufm/N_595 ), .A0(\FS[12] ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .F1(\ram2e_ufm/N_595 )); - ram2e_ufm_SLICE_105 \ram2e_ufm/SLICE_105 ( .D1(\ram2e_ufm/nRWE_s_i_0_63_1 ), - .C1(\S[3] ), .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\ram2e_ufm/N_285_i ), - .C0(\ram2e_ufm/wb_rst16_i ), .B0(\FS[15] ), .A0(\FS[0] ), - .F0(\ram2e_ufm/N_285_i ), .F1(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] )); - ram2e_ufm_SLICE_106 \ram2e_ufm/SLICE_106 ( .B1(\S[1] ), .A1(\S[0] ), - .D0(\S[2] ), .C0(\RA[10] ), .B0(\ram2e_ufm/S_r_i_0_o2[1] ), - .A0(\ram2e_ufm/N_194 ), .F0(\ram2e_ufm/N_624 ), .F1(\ram2e_ufm/N_194 )); - ram2e_ufm_SLICE_107 \ram2e_ufm/SLICE_107 ( .D1(\S[0] ), .C1(\FS[4] ), - .B1(\S[3] ), .A1(\S[2] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[8] ), - .B0(\FS[5] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_659 ), .F1(\ram2e_ufm/N_792 )); - ram2e_ufm_SLICE_108 \ram2e_ufm/SLICE_108 ( - .D1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ), .C1(\FS[7] ), - .B1(\FS[5] ), .A1(\FS[4] ), .C0(\ram2e_ufm/wb_req ), - .B0(\ram2e_ufm/N_336 ), .A0(\FS[0] ), - .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), - .F1(\ram2e_ufm/N_336 )); - ram2e_ufm_SLICE_109 \ram2e_ufm/SLICE_109 ( .B1(\S[2] ), .A1(\FS[14] ), - .D0(\ram2e_ufm/N_799 ), .C0(\ram2e_ufm/N_634 ), .B0(\ram2e_ufm/N_184 ), - .A0(\FS[11] ), .F0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), - .F1(\ram2e_ufm/N_799 )); - ram2e_ufm_SLICE_110 \ram2e_ufm/SLICE_110 ( .D1(\FS[8] ), .C1(\FS[9] ), - .B1(\FS[11] ), .A1(\FS[10] ), .B0(\ram2e_ufm/wb_ack ), - .A0(\ram2e_ufm/N_885 ), - .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), - .F1(\ram2e_ufm/N_885 )); - ram2e_ufm_SLICE_111 \ram2e_ufm/SLICE_111 ( .C1(\ram2e_ufm/N_807 ), - .B1(\ram2e_ufm/N_553 ), .A1(\FS[12] ), - .D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\ram2e_ufm/N_811 ), - .B0(\FS[13] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_553 ), - .F1(\ram2e_ufm/N_611 )); - ram2e_ufm_SLICE_112 \ram2e_ufm/SLICE_112 ( .C1(\S[1] ), .B1(\S[0] ), - .A1(\ram2e_ufm/N_285_i ), .D0(nWE_c), .C0(nEN80_c), .B0(\S[2] ), - .A0(\ram2e_ufm/N_866 ), .F0(\ram2e_ufm/N_616 ), .F1(\ram2e_ufm/N_866 )); - ram2e_ufm_SLICE_113 \ram2e_ufm/SLICE_113 ( .C1(nEN80_c), .B1(\S[3] ), - .A1(\S[2] ), .D0(nWE_c), .C0(\S[1] ), .B0(\S[0] ), .A0(\ram2e_ufm/N_804 ), - .F0(\ram2e_ufm/N_628 ), .F1(\ram2e_ufm/N_804 )); - ram2e_ufm_SLICE_114 \ram2e_ufm/SLICE_114 ( .C1(\FS[10] ), .B1(\FS[9] ), - .A1(\FS[8] ), .D0(\ram2e_ufm/N_799 ), .C0(\ram2e_ufm/N_241_i ), - .B0(\FS[12] ), .A0(\FS[11] ), .F0(\ram2e_ufm/N_768 ), - .F1(\ram2e_ufm/N_241_i )); - ram2e_ufm_SLICE_115 \ram2e_ufm/SLICE_115 ( .B1(\S[2] ), .A1(\S[1] ), - .D0(nEN80_c), .C0(\S[3] ), .B0(\S[0] ), .A0(\ram2e_ufm/N_221 ), - .F0(\ram2e_ufm/CKE_7s2_0_0_0 ), .F1(\ram2e_ufm/N_221 )); - ram2e_ufm_SLICE_116 \ram2e_ufm/SLICE_116 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ), - .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .A1(\ram2e_ufm/N_814 ), - .C0(\Din_c[2] ), .B0(\Din_c[1] ), .A0(\Din_c[0] ), .F0(\ram2e_ufm/N_814 ), - .F1(\ram2e_ufm/N_851 )); - ram2e_ufm_SLICE_117 \ram2e_ufm/SLICE_117 ( .D1(\S[1] ), .C1(\S[0] ), - .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[0] ), - .A0(\S[3] ), .F0(N_225_i), .F1(\ram2e_ufm/N_643 )); - ram2e_ufm_SLICE_118 \ram2e_ufm/SLICE_118 ( .D1(\S[1] ), .C1(\S[0] ), - .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[0] ), - .A0(\S[3] ), .F0(N_201_i), .F1(RC12)); - ram2e_ufm_SLICE_119 \ram2e_ufm/SLICE_119 ( .D1(\S[2] ), .C1(\S[3] ), - .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), - .A0(\S[0] ), .F0(N_126), .F1(N_185_i)); - ram2e_ufm_SLICE_120 \ram2e_ufm/SLICE_120 ( .D1(\S[3] ), .C1(\S[0] ), - .B1(\RWBank[0] ), .A1(\FS[15] ), .D0(\S[3] ), .C0(\S[0] ), - .B0(\RWBank[0] ), .A0(\FS[15] ), .F0(N_507_i), .F1(N_508)); - ram2e_ufm_SLICE_121 \ram2e_ufm/SLICE_121 ( .D1(\S[3] ), .C1(\S[2] ), - .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), - .A0(\S[0] ), .F0(\ram2e_ufm/N_242 ), .F1(Vout3)); - ram2e_ufm_SLICE_122 \ram2e_ufm/SLICE_122 ( .D1(\FS[4] ), .C1(\FS[3] ), - .B1(\FS[2] ), .A1(\FS[1] ), .D0(\FS[4] ), .C0(\FS[3] ), .B0(\FS[2] ), - .A0(\FS[1] ), .F0(\ram2e_ufm/N_254 ), .F1(\ram2e_ufm/nRWE_s_i_0_63_1 )); - ram2e_ufm_SLICE_123 \ram2e_ufm/SLICE_123 ( .C1(\FS[11] ), .B1(\FS[9] ), - .A1(\FS[8] ), .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[10] ), - .F0(\ram2e_ufm/N_849 ), .F1(\ram2e_ufm/N_204 )); - ram2e_ufm_SLICE_124 \ram2e_ufm/SLICE_124 ( .D1(\ram2e_ufm/N_784 ), - .C1(\FS[12] ), .B1(\FS[4] ), .A1(\FS[3] ), .D0(\FS[4] ), - .C0(\ram2e_ufm/N_784 ), .B0(\FS[1] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_684 ), - .F1(\ram2e_ufm/RA_35_0_0_0[5] )); - ram2e_ufm_SLICE_125 \ram2e_ufm/SLICE_125 ( .D1(\FS[13] ), .C1(\FS[11] ), - .B1(\FS[9] ), .A1(\FS[8] ), .D0(\ram2e_ufm/N_793 ), .C0(\FS[11] ), - .B0(\FS[9] ), .A0(\FS[8] ), .F0(\ram2e_ufm/N_763 ), .F1(\ram2e_ufm/N_565 )); - ram2e_ufm_SLICE_126 \ram2e_ufm/SLICE_126 ( .D1(\FS[12] ), .C1(\FS[10] ), - .B1(\FS[9] ), .A1(\FS[8] ), .D0(\ram2e_ufm/N_781 ), .C0(\FS[12] ), - .B0(\FS[10] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_753 ), - .F1(\ram2e_ufm/N_208 )); - ram2e_ufm_SLICE_127 \ram2e_ufm/SLICE_127 ( .D1(\S[3] ), .C1(\S[2] ), - .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[0] ), - .A0(\RWBank[7] ), .F0(\ram2e_ufm/N_698 ), .F1(un9_VOEEN_0_a2_0_a3_0_a3)); - ram2e_ufm_SLICE_128 \ram2e_ufm/SLICE_128 ( .D1(\FS[13] ), .C1(\FS[12] ), - .B1(\FS[11] ), .A1(\FS[10] ), .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ), - .F0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), - .F1(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] )); - ram2e_ufm_SLICE_129 \ram2e_ufm/SLICE_129 ( .D1(\S[0] ), .C1(\RWBank[6] ), - .B1(\ram2e_ufm/N_560 ), .A1(\FS[4] ), .D0(N_551), .C0(\S[0] ), - .B0(\FS[1] ), .A0(\FS[4] ), .F0(\ram2e_ufm/N_627 ), .F1(\BA_4[1] )); - ram2e_ufm_SLICE_130 \ram2e_ufm/SLICE_130 ( .B1(\ram2e_ufm/N_185 ), - .A1(RWSel), .D0(\ram2e_ufm/N_185 ), .C0(RWSel), .B0(\ram2e_ufm/N_777 ), - .A0(\ram2e_ufm/CmdExecMXO2 ), .F0(\ram2e_ufm/wb_we_RNO_0 ), .F1(N_187_i)); - ram2e_ufm_SLICE_131 \ram2e_ufm/SLICE_131 ( .D1(\FS[13] ), .C1(\FS[12] ), - .B1(\FS[3] ), .A1(\FS[1] ), .D0(\ram2e_ufm/N_856 ), .C0(\ram2e_ufm/N_811 ), - .B0(\FS[13] ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_602 ), - .F1(\ram2e_ufm/Ready3_0_a3_5 )); - ram2e_ufm_SLICE_132 \ram2e_ufm/SLICE_132 ( .D1(\RA[0] ), - .C1(\ram2e_ufm/N_186 ), .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[0] ), - .D0(\RA[7] ), .C0(\ram2e_ufm/N_186 ), .B0(\ram2e_ufm/N_182 ), - .A0(\Ain_c[7] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[7] ), - .F1(\ram2e_ufm/RA_35_0_0_1[0] )); - ram2e_ufm_SLICE_133 \ram2e_ufm/SLICE_133 ( .D1(RWSel), .C1(\Din_c[4] ), - .B1(\Din_c[2] ), .A1(\Din_c[0] ), .C0(\ram2e_ufm/N_338 ), .B0(\Din_c[4] ), - .A0(\Din_c[2] ), .F0(\ram2e_ufm/N_350 ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 )); - ram2e_ufm_SLICE_134 \ram2e_ufm/SLICE_134 ( .D1(\FS[6] ), .C1(\FS[3] ), - .B1(\FS[2] ), .A1(\FS[1] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[9] ), - .B0(\FS[6] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_679 ), - .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] )); - ram2e_ufm_SLICE_135 \ram2e_ufm/SLICE_135 ( .B1(\S[3] ), .A1(\S[2] ), - .D0(nEN80_c), .C0(\S[3] ), .B0(\S[2] ), .A0(\ram2e_ufm/S_r_i_0_o2[1] ), - .F0(\ram2e_ufm/N_625 ), .F1(\ram2e_ufm/N_271 )); - ram2e_ufm_SLICE_136 \ram2e_ufm/SLICE_136 ( .C1(nWE_c), .B1(nEN80_c), - .A1(\S[3] ), .C0(nWE_c), .B0(nEN80_c), .A0(DOEEN), .F0(nDOE_c), - .F1(\ram2e_ufm/N_226 )); - ram2e_ufm_SLICE_137 \ram2e_ufm/SLICE_137 ( .C1(nWE_c), .B1(nEN80_c), - .A1(Ready), .C0(nEN80_c), .B0(Ready), .A0(\ram2e_ufm/LEDEN ), .F0(LED_c), - .F1(RDOE_i)); - SLICE_138 SLICE_138( .C1(\S[0] ), .B1(\S[1] ), .A1(\S[3] ), .C0(\S[0] ), - .B0(\S[1] ), .A0(\S[2] ), .F0(N_1080_0), .F1(N_1078_0)); - SLICE_139 SLICE_139( .B1(VOEEN), .A1(PHI1_c), .C0(Ready), .B0(PHI1r), - .A0(PHI1_c), .F0(S_1), .F1(nVOE_c)); - ram2e_ufm_SLICE_140 \ram2e_ufm/SLICE_140 ( .B1(\RA[2] ), - .A1(\ram2e_ufm/N_186 ), .B0(\RA[5] ), .A0(\ram2e_ufm/N_186 ), - .F0(\ram2e_ufm/N_621 ), .F1(\ram2e_ufm/N_680 )); - ram2e_ufm_SLICE_141 \ram2e_ufm/SLICE_141 ( .B1(Ready), .A1(\Din_c[0] ), - .B0(Ready), .A0(\Din_c[3] ), .F0(N_263_i), .F1(N_667)); - ram2e_ufm_SLICE_142 \ram2e_ufm/SLICE_142 ( .C1(\Din_c[4] ), .B1(\Din_c[7] ), - .A1(\Din_c[0] ), .B0(Ready), .A0(\Din_c[4] ), .F0(N_648), - .F1(\ram2e_ufm/CmdLEDGet_3_0_a3_1 )); - ram2e_ufm_SLICE_143 \ram2e_ufm/SLICE_143 ( .B1(Ready), .A1(\Din_c[1] ), - .B0(Ready), .A0(\Din_c[7] ), .F0(N_662), .F1(N_666)); - ram2e_ufm_SLICE_144 \ram2e_ufm/SLICE_144 ( .B1(Ready), .A1(\Din_c[2] ), - .B0(Ready), .A0(\Din_c[6] ), .F0(N_663), .F1(N_665)); - ram2e_ufm_SLICE_145 \ram2e_ufm/SLICE_145 ( .D1(\ram2e_ufm/wb_adr[4] ), - .C1(\S[2] ), .B1(\ram2e_ufm/N_873 ), .A1(\ram2e_ufm/N_783 ), .B0(\FS[9] ), - .A0(\FS[8] ), .F0(\ram2e_ufm/N_206 ), .F1(\ram2e_ufm/wb_dati_7_0_0_0[4] )); - ram2e_ufm_SLICE_146 \ram2e_ufm/SLICE_146 ( .D1(\RWBank[2] ), - .C1(\ram2e_ufm/N_845 ), .B1(\ram2e_ufm/N_784 ), .A1(\FS[4] ), .D0(\FS[7] ), - .C0(\FS[6] ), .B0(\FS[5] ), .A0(\FS[0] ), .F0(\ram2e_ufm/Ready3_0_a3_3 ), - .F1(\ram2e_ufm/RA_35_0_0_0[9] )); - ram2e_ufm_SLICE_147 \ram2e_ufm/SLICE_147 ( .D1(\ram2e_ufm/LEDEN ), - .C1(CmdSetRWBankFFLED), .B1(\ram2e_ufm/CmdSetRWBankFFChip ), - .A1(CmdLEDGet), .B0(Ready), .A0(\Din_c[5] ), .F0(N_664), - .F1(\ram2e_ufm/N_188 )); - RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(N_667), - .RD0(RD[0])); - LED LED_I( .PADDO(LED_c), .LED(LED)); - C14M C14M_I( .PADDI(C14M_c), .C14M(C14M)); - RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(N_662), - .RD7(RD[7])); - RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(N_663), - .RD6(RD[6])); - RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(N_664), - .RD5(RD[5])); - RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(N_648), - .RD4(RD[4])); - RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(N_263_i), - .RD3(RD[3])); - RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(N_665), - .RD2(RD[2])); - RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(N_666), - .RD1(RD[1])); - DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH)); - DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_508), .CE(N_201_i), - .CLK(C14M_c)); - DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML)); - DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_507_i), .CE(N_201_i), - .CLK(C14M_c)); - RAout_11_ \RAout[11]_I ( .IOLDO(\RAout_c[11] ), .RAout11(RAout[11])); - RAout_11__MGIOL \RAout[11]_MGIOL ( .IOLDO(\RAout_c[11] ), .OPOS(\RA[11] ), - .CLK(C14M_c)); - RAout_10_ \RAout[10]_I ( .IOLDO(\RAout_c[10] ), .RAout10(RAout[10])); - RAout_10__MGIOL \RAout[10]_MGIOL ( .IOLDO(\RAout_c[10] ), .OPOS(\RA[10] ), - .CLK(C14M_c)); - RAout_9_ \RAout[9]_I ( .IOLDO(\RAout_c[9] ), .RAout9(RAout[9])); - RAout_9__MGIOL \RAout[9]_MGIOL ( .IOLDO(\RAout_c[9] ), .OPOS(\RA[9] ), - .CLK(C14M_c)); - RAout_8_ \RAout[8]_I ( .IOLDO(\RAout_c[8] ), .RAout8(RAout[8])); - RAout_8__MGIOL \RAout[8]_MGIOL ( .IOLDO(\RAout_c[8] ), .OPOS(\RA[8] ), - .CLK(C14M_c)); - RAout_7_ \RAout[7]_I ( .IOLDO(\RAout_c[7] ), .RAout7(RAout[7])); - RAout_7__MGIOL \RAout[7]_MGIOL ( .IOLDO(\RAout_c[7] ), .OPOS(\RA[7] ), - .CLK(C14M_c)); - RAout_6_ \RAout[6]_I ( .IOLDO(\RAout_c[6] ), .RAout6(RAout[6])); - RAout_6__MGIOL \RAout[6]_MGIOL ( .IOLDO(\RAout_c[6] ), .OPOS(\RA[6] ), - .CLK(C14M_c)); - RAout_5_ \RAout[5]_I ( .IOLDO(\RAout_c[5] ), .RAout5(RAout[5])); - RAout_5__MGIOL \RAout[5]_MGIOL ( .IOLDO(\RAout_c[5] ), .OPOS(\RA[5] ), - .CLK(C14M_c)); - RAout_4_ \RAout[4]_I ( .IOLDO(\RAout_c[4] ), .RAout4(RAout[4])); - RAout_4__MGIOL \RAout[4]_MGIOL ( .IOLDO(\RAout_c[4] ), .OPOS(\RA[4] ), - .CLK(C14M_c)); - RAout_3_ \RAout[3]_I ( .IOLDO(\RAout_c[3] ), .RAout3(RAout[3])); - RAout_3__MGIOL \RAout[3]_MGIOL ( .IOLDO(\RAout_c[3] ), .OPOS(\RA[3] ), - .CLK(C14M_c)); - RAout_2_ \RAout[2]_I ( .IOLDO(\RAout_c[2] ), .RAout2(RAout[2])); - RAout_2__MGIOL \RAout[2]_MGIOL ( .IOLDO(\RAout_c[2] ), .OPOS(\RA[2] ), - .CLK(C14M_c)); - RAout_1_ \RAout[1]_I ( .IOLDO(\RAout_c[1] ), .RAout1(RAout[1])); - RAout_1__MGIOL \RAout[1]_MGIOL ( .IOLDO(\RAout_c[1] ), .OPOS(\RA[1] ), - .CLK(C14M_c)); - RAout_0_ \RAout[0]_I ( .IOLDO(\RAout_c[0] ), .RAout0(RAout[0])); - RAout_0__MGIOL \RAout[0]_MGIOL ( .IOLDO(\RAout_c[0] ), .OPOS(\RA[0] ), - .CLK(C14M_c)); - BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1])); - BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), .CE(N_225_i), - .LSR(BA_0_sqmuxa), .CLK(C14M_c)); - BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0])); - BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), .CE(N_225_i), - .LSR(BA_0_sqmuxa), .CLK(C14M_c)); - nRWEout nRWEout_I( .IOLDO(nRWEout_c), .nRWEout(nRWEout)); - nRWEout_MGIOL nRWEout_MGIOL( .IOLDO(nRWEout_c), .OPOS(nRWE), .CLK(C14M_c)); - nCASout nCASout_I( .IOLDO(nCASout_c), .nCASout(nCASout)); - nCASout_MGIOL nCASout_MGIOL( .IOLDO(nCASout_c), .OPOS(nCAS), .CLK(C14M_c)); - nRASout nRASout_I( .IOLDO(nRASout_c), .nRASout(nRASout)); - nRASout_MGIOL nRASout_MGIOL( .IOLDO(nRASout_c), .OPOS(nRAS), .CLK(C14M_c)); - nCSout nCSout_I( .PADDO(GND), .nCSout(nCSout)); - CKEout CKEout_I( .IOLDO(CKEout_c), .CKEout(CKEout)); - CKEout_MGIOL CKEout_MGIOL( .IOLDO(CKEout_c), .OPOS(CKE), .CLK(C14M_c)); - nVOE nVOE_I( .PADDO(nVOE_c), .nVOE(nVOE)); - Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7])); - Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_6_ \Vout[6]_I ( .IOLDO(\Vout_c[6] ), .Vout6(Vout[6])); - Vout_6__MGIOL \Vout[6]_MGIOL ( .IOLDO(\Vout_c[6] ), .OPOS(\RD_in[6] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_5_ \Vout[5]_I ( .IOLDO(\Vout_c[5] ), .Vout5(Vout[5])); - Vout_5__MGIOL \Vout[5]_MGIOL ( .IOLDO(\Vout_c[5] ), .OPOS(\RD_in[5] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_4_ \Vout[4]_I ( .IOLDO(\Vout_c[4] ), .Vout4(Vout[4])); - Vout_4__MGIOL \Vout[4]_MGIOL ( .IOLDO(\Vout_c[4] ), .OPOS(\RD_in[4] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_3_ \Vout[3]_I ( .IOLDO(\Vout_c[3] ), .Vout3(Vout[3])); - Vout_3__MGIOL \Vout[3]_MGIOL ( .IOLDO(\Vout_c[3] ), .OPOS(\RD_in[3] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_2_ \Vout[2]_I ( .IOLDO(\Vout_c[2] ), .Vout2(Vout[2])); - Vout_2__MGIOL \Vout[2]_MGIOL ( .IOLDO(\Vout_c[2] ), .OPOS(\RD_in[2] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_1_ \Vout[1]_I ( .IOLDO(\Vout_c[1] ), .Vout1(Vout[1])); - Vout_1__MGIOL \Vout[1]_MGIOL ( .IOLDO(\Vout_c[1] ), .OPOS(\RD_in[1] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_0_ \Vout[0]_I ( .IOLDO(\Vout_c[0] ), .Vout0(Vout[0])); - Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), - .CE(Vout3), .CLK(C14M_c)); - nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE)); - Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7])); - Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6])); - Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5])); - Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4])); - Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3])); - Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2])); - Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1])); - Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0])); - Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7])); - Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6])); - Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5])); - Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4])); - Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3])); - Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2])); - Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1])); - Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0])); - Ain_7_ \Ain[7]_I ( .PADDI(\Ain_c[7] ), .Ain7(Ain[7])); - Ain_6_ \Ain[6]_I ( .PADDI(\Ain_c[6] ), .Ain6(Ain[6])); - Ain_5_ \Ain[5]_I ( .PADDI(\Ain_c[5] ), .Ain5(Ain[5])); - Ain_4_ \Ain[4]_I ( .PADDI(\Ain_c[4] ), .Ain4(Ain[4])); - Ain_3_ \Ain[3]_I ( .PADDI(\Ain_c[3] ), .Ain3(Ain[3])); - Ain_2_ \Ain[2]_I ( .PADDI(\Ain_c[2] ), .Ain2(Ain[2])); - Ain_1_ \Ain[1]_I ( .PADDI(\Ain_c[1] ), .Ain1(Ain[1])); - Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0])); - nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X)); - nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80)); - nWE nWE_I( .PADDI(nWE_c), .nWE(nWE)); - PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1)); - PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1r)); - ram2e_ufm_ufmefb_EFBInst_0 \ram2e_ufm/ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), - .WBRSTI(\ram2e_ufm/wb_rst ), .WBCYCI(\ram2e_ufm/wb_cyc_stb ), - .WBSTBI(\ram2e_ufm/wb_cyc_stb ), .WBWEI(\ram2e_ufm/wb_we ), - .WBADRI0(\ram2e_ufm/wb_adr[0] ), .WBADRI1(\ram2e_ufm/wb_adr[1] ), - .WBADRI2(\ram2e_ufm/wb_adr[2] ), .WBADRI3(\ram2e_ufm/wb_adr[3] ), - .WBADRI4(\ram2e_ufm/wb_adr[4] ), .WBADRI5(\ram2e_ufm/wb_adr[5] ), - .WBADRI6(\ram2e_ufm/wb_adr[6] ), .WBADRI7(\ram2e_ufm/wb_adr[7] ), - .WBDATI0(\ram2e_ufm/wb_dati[0] ), .WBDATI1(\ram2e_ufm/wb_dati[1] ), - .WBDATI2(\ram2e_ufm/wb_dati[2] ), .WBDATI3(\ram2e_ufm/wb_dati[3] ), - .WBDATI4(\ram2e_ufm/wb_dati[4] ), .WBDATI5(\ram2e_ufm/wb_dati[5] ), - .WBDATI6(\ram2e_ufm/wb_dati[6] ), .WBDATI7(\ram2e_ufm/wb_dati[7] ), - .WBDATO0(\ram2e_ufm/wb_dato[0] ), .WBDATO1(\ram2e_ufm/wb_dato[1] ), - .WBDATO2(\ram2e_ufm/wb_dato[2] ), .WBDATO3(\ram2e_ufm/wb_dato[3] ), - .WBDATO4(\ram2e_ufm/wb_dato[4] ), .WBDATO5(\ram2e_ufm/wb_dato[5] ), - .WBDATO6(\ram2e_ufm/wb_dato[6] ), .WBDATO7(\ram2e_ufm/wb_dato[7] ), - .WBACKO(\ram2e_ufm/wb_ack )); - VHI VHI_INST( .Z(VCCI)); - PUR PUR_INST( .PUR(VCCI)); - GSR GSR_INST( .GSR(VCCI)); -endmodule - -module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly; - - vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module vcc ( output PWR1 ); - - VHI INST1( .Z(PWR1)); -endmodule - -module gnd ( output PWR0 ); - - VLO INST1( .Z(PWR0)); -endmodule - -module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h000A; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - ccu20001 \FS_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); - - specify - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h5002; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h300A; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut4 \ram2e_ufm/wb_req_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40003 \ram2e_ufm/CKE_7_RNIS77M1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 CKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut4 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40003 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_10 ( input B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40005 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40006 \ram2e_ufm/CmdTout_3_0_a3_0_a3[0] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40005 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40006 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_11 ( input B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40006 \ram2e_ufm/RC_3_0_0_a3_1[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40007 \ram2e_ufm/N_360_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \RC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40007 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_12 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - - lut40008 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNI6S1P8 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40009 \ram2e_ufm/S_r_i_0_o2_RNIVM0LF[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0010 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0010 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40008 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40009 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0010 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_13 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output - F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40011 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0010 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40011 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA2A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40012 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC4C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40013 \ram2e_ufm/CmdLEDGet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40014 \ram2e_ufm/CmdLEDGet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40013 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40014 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_15 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40013 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40015 \ram2e_ufm/CmdLEDSet_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40015 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_16 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40017 \ram2e_ufm/CmdRWMaskSet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40016 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40017 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_17 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40018 \ram2e_ufm/CmdRWMaskSet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40019 \ram2e_ufm/CmdSetRWBankFFLED_4_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40018 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40019 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40020 \ram2e_ufm/N_369_i ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 \ram2e_ufm/N_368_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CmdTout[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40020 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0078) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40021 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0606) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_19 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, M0_dly, CLK_dly, LSR_dly; - - lut40022 \ram2e_ufm/SUM0_i_o2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/RA_35_i_i_0_a3_0[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0010 DOEEN( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40022 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40023 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40024 \ram2e_ufm/RA_35_i_i_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40025 \ram2e_ufm/RA_35_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40024 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40025 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \ram2e_ufm/RA_35_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40024 \ram2e_ufm/RA_35_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40026 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_22 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40024 \ram2e_ufm/RA_35_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40026 \ram2e_ufm/RA_35_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \ram2e_ufm/RA_35_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40026 \ram2e_ufm/RA_35_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre \RA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \ram2e_ufm/RA_35_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40027 \ram2e_ufm/un2_S_2_i_0_0_o3_RNIHFHN3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \RA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40027 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_25 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40028 \ram2e_ufm/RA_35_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut4 \ram2e_ufm/RA_35_2_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40028 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_26 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40029 \ram2e_ufm/RC_3_0_0[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40030 \ram2e_ufm/RC_3_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \RC[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RC[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40029 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3838) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40030 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4646) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_27 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40031 \ram2e_ufm/RWBank_3_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40031 \ram2e_ufm/RWBank_3_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40031 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_28 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40031 \ram2e_ufm/RWBank_3_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40031 \ram2e_ufm/RWBank_3_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40031 \ram2e_ufm/RWBank_3_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40031 \ram2e_ufm/RWBank_3_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40032 \ram2e_ufm/RWBank_3_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40031 \ram2e_ufm/RWBank_3_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40032 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40033 \ram2e_ufm/RA_35_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40034 \ram2e_ufm/RWSel_2_0_a3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40033 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40034 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; - - lut40035 \ram2e_ufm/Ready3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40036 Ready_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40035 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40036 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40037 \ram2e_ufm/S_r_i_0_o2_0_RNI36E21[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40038 \ram2e_ufm/S_s_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40037 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40038 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFBFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40039 \ram2e_ufm/S_r_i_0_o2_RNIFNP81_0[2] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40040 \ram2e_ufm/S_r_i_0_o2_RNIFNP81[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \S[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40039 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0B0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40040 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_35 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40016 \ram2e_ufm/CKE_7_m1_0_0_o2_RNICM8E1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40036 \ram2e_ufm/CKE_7_m1_0_0_o2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0010 VOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40041 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40042 \ram2e_ufm/nCAS_s_i_0_a3_RNIO1UQ3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 nCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40041 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40042 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40034 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40016 \ram2e_ufm/nRAS_s_i_0_0_RNI0PC64 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 nRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_38 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40043 \ram2e_ufm/nRAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40044 \ram2e_ufm/nRAS_s_i_0_a3_0_RNIIR094 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0004 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40043 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40044 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_39 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40045 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40019 \ram2e_ufm/CmdBitbangMXO2_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/CmdBitbangMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40045 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_40 ( input D1, C1, B1, A1, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40014 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40023 \ram2e_ufm/CmdExecMXO2_3_0_a3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/CmdExecMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40046 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40014 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/CmdSetRWBankFFChip ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40046 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_42 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40047 \ram2e_ufm/SUM1_0_o3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40048 \ram2e_ufm/LEDEN_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/LEDEN ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40047 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40048 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_43 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40049 \ram2e_ufm/RWMask_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 \ram2e_ufm/RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40049 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7474) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_44 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40049 \ram2e_ufm/RWMask_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 \ram2e_ufm/RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_45 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40049 \ram2e_ufm/RWMask_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 \ram2e_ufm/RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_46 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40048 \ram2e_ufm/RWMask_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 \ram2e_ufm/RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40050 \ram2e_ufm/wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40024 \ram2e_ufm/wb_adr_7_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40050 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_48 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40023 \ram2e_ufm/wb_adr_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/wb_adr_RNO[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_49 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40051 \ram2e_ufm/wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40051 \ram2e_ufm/wb_adr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40051 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_50 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40023 \ram2e_ufm/wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40051 \ram2e_ufm/wb_adr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_51 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40052 \ram2e_ufm/wb_cyc_stb_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40053 \ram2e_ufm/wb_cyc_stb_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_cyc_stb ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40052 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40053 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40054 \ram2e_ufm/wb_dati_7_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40055 \ram2e_ufm/wb_dati_7_0_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40054 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40055 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40054 \ram2e_ufm/wb_dati_7_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40054 \ram2e_ufm/wb_dati_7_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40054 \ram2e_ufm/wb_dati_7_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut4 \ram2e_ufm/wb_dati_7_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut4 \ram2e_ufm/wb_dati_7_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40054 \ram2e_ufm/wb_dati_7_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut4 \ram2e_ufm/wb_reqc_1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40056 \ram2e_ufm/wb_req_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0010 \ram2e_ufm/wb_req ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40056 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_57 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40035 \ram2e_ufm/Ready3_0_a3_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40006 \ram2e_ufm/wb_rst8_0_a3_0_a3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0010 \ram2e_ufm/wb_rst ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40057 \ram2e_ufm/wb_we_RNO_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40057 \ram2e_ufm/wb_we_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_we ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40057 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SUM0_i_m3_0_SLICE_59 ( input C1, B1, A1, C0, B0, A0, M0, - output OFX0 ); - wire GNDI, - \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 , - \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ; - - lut40058 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40059 \ram2e_ufm/SUM0_i_m3_0/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 )); - selmux2 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K0K1MUX ( - .D0(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ), - .D1(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ), - .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40058 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40059 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module selmux2 ( input D0, D1, SD, output Z ); - - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 ( input D1, C1, B1, A1, C0, B0, - A0, M0, output OFX0 ); - wire - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 - , GNDI, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 - ; - - lut40060 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1 ( .A(A1), .B(B1), - .C(C1), .D(D1), - .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 ) - ); - lut40061 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - selmux2 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K0K1MUX ( - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 ) - , - .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40060 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h55D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40061 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_CKE_7_SLICE_61 ( input C1, B1, A1, C0, B0, A0, M0, output - OFX0 ); - wire GNDI, \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 , - \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ; - - lut40062 \ram2e_ufm/CKE_7/SLICE_61_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40063 \ram2e_ufm/CKE_7/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 )); - selmux2 \ram2e_ufm/CKE_7/SLICE_61_K0K1MUX ( - .D0(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ), - .D1(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ), .SD(M0), - .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40062 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5D5D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40063 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40043 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIAJ811 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40064 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIPG3P2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40064 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40065 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40066 \ram2e_ufm/S_r_i_0_o2_RNI3VQTC[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40065 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40066 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40067 \ram2e_ufm/wb_adr_7_i_i_a3_6[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40068 \ram2e_ufm/wb_adr_7_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40067 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40068 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40069 \ram2e_ufm/SUM0_i_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40065 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40069 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40070 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40071 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40070 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40071 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF5F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40072 \ram2e_ufm/nRAS_s_i_0_m3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40073 \ram2e_ufm/nRAS_s_i_0_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40072 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40073 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40074 \ram2e_ufm/wb_adr_7_i_i_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40075 \ram2e_ufm/wb_adr_7_i_i_3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40074 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40075 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h01A1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40076 \ram2e_ufm/nCAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut4 \ram2e_ufm/wb_rst16_i_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40076 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_70 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40077 \ram2e_ufm/wb_dati_7_0_0_a3_12[7] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40078 \ram2e_ufm/wb_dati_7_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40077 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40078 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_71 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40013 \ram2e_ufm/RA_35_0_0_a3_4[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40079 \ram2e_ufm/nRAS_s_i_0_a3_4 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40079 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40080 \ram2e_ufm/BA_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40047 \ram2e_ufm/un1_RC12_i_0_o3 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40080 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40081 \ram2e_ufm/wb_dati_7_0_0_o3_0[2] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40082 \ram2e_ufm/wb_dati_7_0_0_a3_3[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40081 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40082 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40053 \ram2e_ufm/RA_35_2_0_0[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40034 \ram2e_ufm/RA_35_2_0_a3_5[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40079 \ram2e_ufm/wb_dati_7_0_0_a3_15[7] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40015 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40083 \ram2e_ufm/wb_dati_7_0_0_a3_13[7] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40019 \ram2e_ufm/wb_dati_7_0_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40083 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40084 \ram2e_ufm/SUM2_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40085 \ram2e_ufm/N_314_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40084 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40085 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40036 \ram2e_ufm/S_r_i_0_o2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \ram2e_ufm/S_r_i_0_o2_RNIP4KI1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_79 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40086 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40087 \ram2e_ufm/S_r_i_0_o2_RNIOGTF1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40086 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40087 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40034 \ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40088 \ram2e_ufm/CmdBitbangMXO2_RNINSM62 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40088 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40017 \ram2e_ufm/wb_dati_7_0_0_a3_14[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40035 \ram2e_ufm/wb_dati_7_0_0_a3_13_RNI81UL[7] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40019 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_83 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40067 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40089 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40089 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40082 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40090 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40090 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3130) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40017 \ram2e_ufm/wb_dati_7_0_0_a3_10[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40086 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_86 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40023 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_1 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut4 \ram2e_ufm/wb_adr_7_i_i_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40091 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40092 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_m3 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40091 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40092 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8D8D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40093 \ram2e_ufm/wb_dati_7_0_0_a3_4_1_0[7] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40094 \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40093 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40094 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC8C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_89 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40077 \ram2e_ufm/wb_dati_7_0_0_a3_7[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40055 \ram2e_ufm/wb_dati_7_0_0_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40095 \ram2e_ufm/wb_dati_7_0_0_a3_1_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40055 \ram2e_ufm/wb_dati_7_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40095 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0021) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40096 \ram2e_ufm/nRAS_s_i_0_a3_8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40097 \ram2e_ufm/nRAS_s_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40096 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40097 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40098 \ram2e_ufm/CKE_7s2_0_0_o3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40099 \ram2e_ufm/nCAS_s_i_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40098 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5C50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40099 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_93 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40100 \ram2e_ufm/wb_dati_7_0_0_o2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40013 \ram2e_ufm/wb_dati_7_0_0_a3[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40100 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40101 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40101 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40102 \ram2e_ufm/RA_35_0_0_o2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40033 \ram2e_ufm/RA_35_0_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40102 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAE8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40103 \ram2e_ufm/RA_35_0_0_o2_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40033 \ram2e_ufm/RA_35_0_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40103 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1512) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_97 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40104 \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40055 \ram2e_ufm/wb_dati_7_0_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40104 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_98 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40093 \ram2e_ufm/wb_dati_7_0_0_a3_9[7] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40055 \ram2e_ufm/wb_dati_7_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_99 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40105 \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40106 \ram2e_ufm/wb_adr_7_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40105 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40106 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut4 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40107 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40107 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBF8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_101 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40022 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40108 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40108 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB1A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_102 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40077 \ram2e_ufm/CKE_7s2_0_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40047 \ram2e_ufm/CKE_7s2_0_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_103 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40101 \ram2e_ufm/wb_dati_7_0_0_0_o2[7] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40109 \ram2e_ufm/wb_adr_RNO_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40109 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_104 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40110 \ram2e_ufm/wb_dati_7_0_0_o2_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40093 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40110 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_105 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40016 \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40111 \ram2e_ufm/N_285_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40111 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_106 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40022 \ram2e_ufm/S_r_i_0_o2[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40112 \ram2e_ufm/RA_35_2_0_a3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40112 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_107 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40113 \ram2e_ufm/CKE_7_m1_0_0_o2_RNIGC501 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40114 \ram2e_ufm/RA_35_i_i_0_a3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40113 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40114 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_108 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut4 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40115 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ( .A(A0), - .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40115 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3131) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_109 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40006 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_6 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40068 \ram2e_ufm/wb_we_RNO_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_110 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40035 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_7 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40023 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ( .A(A0), .B(B0), - .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_111 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40104 \ram2e_ufm/wb_dati_7_0_0_a3_2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40116 \ram2e_ufm/wb_dati_7_0_0_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40116 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h9180) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_112 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40018 \ram2e_ufm/nRAS_s_i_0_a3_6 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40117 \ram2e_ufm/nRAS_s_i_0_a3_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40117 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_113 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40077 \ram2e_ufm/nRAS_s_i_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40014 \ram2e_ufm/RA_35_2_0_a3_3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_114 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40118 \ram2e_ufm/wb_adr_RNO_2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40117 \ram2e_ufm/wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40118 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8787) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40036 \ram2e_ufm/un2_S_2_i_0_0_o3 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40119 \ram2e_ufm/CKE_7s2_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40119 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0C4C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_116 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40014 \ram2e_ufm/CmdExecMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40067 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ( .A(A0), .B(B0), - .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_117 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40120 \ram2e_ufm/S_s_0_0_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40121 \ram2e_ufm/N_225_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40120 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0F0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40121 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_118 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40113 \ram2e_ufm/CKE_7_m1_0_0_o2_RNI7FOA1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40122 \ram2e_ufm/N_201_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40122 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_119 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40123 \ram2e_ufm/S_r_i_0_o2_RNIBAU51[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40124 \ram2e_ufm/un1_CKE75_0_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40123 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40124 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD79B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_120 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40125 \ram2e_ufm/DQMH_4_iv_0_0_i_i_a3_0_a3 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40126 \ram2e_ufm/N_507_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40125 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h31F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40126 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCD05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_121 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40127 \ram2e_ufm/Vout3_0_a3_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40128 \ram2e_ufm/RA_35_0_0_o2[11] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40127 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40128 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFCF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_122 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40129 \ram2e_ufm/nRWE_s_i_0_63_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40130 \ram2e_ufm/nCAS_s_i_0_m2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40129 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4FFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40130 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h37FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_123 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40131 \ram2e_ufm/wb_adr_RNO_3[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40019 \ram2e_ufm/wb_dati_7_0_0_a3_8[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40131 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_124 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40132 \ram2e_ufm/RA_35_0_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40035 \ram2e_ufm/RA_35_0_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40132 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_125 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40133 \ram2e_ufm/wb_adr_7_i_i_o2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40045 \ram2e_ufm/wb_dati_7_0_0_a3_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40133 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F70) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_126 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40134 \ram2e_ufm/wb_we_RNO_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40117 \ram2e_ufm/wb_adr_7_i_i_a3_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40134 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F07) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_127 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40117 \ram2e_ufm/un9_VOEEN_0_a2_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40046 \ram2e_ufm/RA_35_2_30_a3_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_128 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40135 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40136 \ram2e_ufm/wb_adr_RNO_4[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40135 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40136 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40080 \ram2e_ufm/BA_4[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40016 \ram2e_ufm/RA_35_2_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_130 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40083 \ram2e_ufm/N_187_i ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40088 \ram2e_ufm/wb_we_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_131 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40035 \ram2e_ufm/Ready3_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40137 \ram2e_ufm/wb_dati_7_0_0_0_a3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40137 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_132 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40138 \ram2e_ufm/RA_35_0_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40033 \ram2e_ufm/RA_35_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40138 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_133 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40035 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40084 \ram2e_ufm/SUM0_i_o2_2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_134 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut4 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40114 \ram2e_ufm/RA_35_0_0_a3[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_135 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40022 \ram2e_ufm/S_r_i_0_o2_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40139 \ram2e_ufm/RA_35_2_0_a3_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40139 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_136 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40140 \ram2e_ufm/nRAS_s_i_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40141 \ram2e_ufm/un1_nDOE_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40140 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5757) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40141 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_137 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40142 \ram2e_ufm/RDOE_i ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40084 \ram2e_ufm/LEDEN_RNI6G6M ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40142 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_138 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40007 VOEEN_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40007 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_139 ( input B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40101 nVOE_pad_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40067 S_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_140 ( input B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40023 \ram2e_ufm/RA_35_0_0_a3_0[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/RA_35_0_0_a3[5] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_141 ( input B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40023 \ram2e_ufm/RDout_i_0_i_a3[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/N_263_i ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_142 ( input C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40136 \ram2e_ufm/CmdLEDGet_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/RDout_i_i_a3[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_143 ( input B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40023 \ram2e_ufm/RDout_i_0_i_a3[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/RDout_i_0_i_a3[7] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_144 ( input B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40023 \ram2e_ufm/RDout_i_0_i_a3[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/RDout_i_0_i_a3[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_145 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40033 \ram2e_ufm/wb_dati_7_0_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40143 \ram2e_ufm/wb_dati_7_0_0_o2_0[7] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40143 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_146 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40144 \ram2e_ufm/RA_35_0_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40035 \ram2e_ufm/Ready3_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40144 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_147 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40027 \ram2e_ufm/RWBank_3_0_0_o3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40023 \ram2e_ufm/RDout_i_0_i_a3[5] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); - - xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); - - specify - (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD0) = (0:0:0,0:0:0); - (RD0 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD0, 0:0:0); - $width (negedge RD0, 0:0:0); - endspecify - -endmodule - -module xo2iobuf ( input I, T, output Z, PAD, input PADI ); - - IB INST1( .I(PADI), .O(Z)); - OBW INST2( .I(I), .T(T), .O(PAD)); -endmodule - -module LED ( input PADDO, output LED ); - - xo2iobuf0145 LED_pad( .I(PADDO), .PAD(LED)); - - specify - (PADDO => LED) = (0:0:0,0:0:0); - endspecify - -endmodule - -module xo2iobuf0145 ( input I, output PAD ); - - OB INST5( .I(I), .O(PAD)); -endmodule - -module C14M ( output PADDI, input C14M ); - - xo2iobuf0146 C14M_pad( .Z(PADDI), .PAD(C14M)); - - specify - (C14M => PADDI) = (0:0:0,0:0:0); - $width (posedge C14M, 0:0:0); - $width (negedge C14M, 0:0:0); - endspecify - -endmodule - -module xo2iobuf0146 ( output Z, input PAD ); - - IB INST1( .I(PAD), .O(Z)); -endmodule - -module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); - - xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7)); - - specify - (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD7) = (0:0:0,0:0:0); - (RD7 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD7, 0:0:0); - $width (negedge RD7, 0:0:0); - endspecify - -endmodule - -module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); - - xo2iobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6)); - - specify - (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD6) = (0:0:0,0:0:0); - (RD6 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD6, 0:0:0); - $width (negedge RD6, 0:0:0); - endspecify - -endmodule - -module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); - - xo2iobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5)); - - specify - (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD5) = (0:0:0,0:0:0); - (RD5 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD5, 0:0:0); - $width (negedge RD5, 0:0:0); - endspecify - -endmodule - -module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); - - xo2iobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4)); - - specify - (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD4) = (0:0:0,0:0:0); - (RD4 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD4, 0:0:0); - $width (negedge RD4, 0:0:0); - endspecify - -endmodule - -module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); - - xo2iobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3)); - - specify - (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD3) = (0:0:0,0:0:0); - (RD3 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD3, 0:0:0); - $width (negedge RD3, 0:0:0); - endspecify - -endmodule - -module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); - - xo2iobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2)); - - specify - (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD2) = (0:0:0,0:0:0); - (RD2 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD2, 0:0:0); - $width (negedge RD2, 0:0:0); - endspecify - -endmodule - -module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); - - xo2iobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1)); - - specify - (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD1) = (0:0:0,0:0:0); - (RD1 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD1, 0:0:0); - $width (negedge RD1, 0:0:0); - endspecify - -endmodule - -module DQMH ( input IOLDO, output DQMH ); - - xo2iobuf0145 DQMH_pad( .I(IOLDO), .PAD(DQMH)); - - specify - (IOLDO => DQMH) = (0:0:0,0:0:0); - endspecify - -endmodule - -module DQMH_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre DQMH_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module mfflsre ( input D0, SP, CK, LSR, output Q ); - - FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module DQML ( input IOLDO, output DQML ); - - xo2iobuf0145 DQML_pad( .I(IOLDO), .PAD(DQML)); - - specify - (IOLDO => DQML) = (0:0:0,0:0:0); - endspecify - -endmodule - -module DQML_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre DQML_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module RAout_11_ ( input IOLDO, output RAout11 ); - - xo2iobuf0145 \RAout_pad[11] ( .I(IOLDO), .PAD(RAout11)); - - specify - (IOLDO => RAout11) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_11__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module mfflsre0147 ( input D0, SP, CK, LSR, output Q ); - - FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module inverter ( input I, output Z ); - - INV INST1( .A(I), .Z(Z)); -endmodule - -module RAout_10_ ( input IOLDO, output RAout10 ); - - xo2iobuf0145 \RAout_pad[10] ( .I(IOLDO), .PAD(RAout10)); - - specify - (IOLDO => RAout10) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_10__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_9_ ( input IOLDO, output RAout9 ); - - xo2iobuf0145 \RAout_pad[9] ( .I(IOLDO), .PAD(RAout9)); - - specify - (IOLDO => RAout9) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_9__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_8_ ( input IOLDO, output RAout8 ); - - xo2iobuf0145 \RAout_pad[8] ( .I(IOLDO), .PAD(RAout8)); - - specify - (IOLDO => RAout8) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_8__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_7_ ( input IOLDO, output RAout7 ); - - xo2iobuf0145 \RAout_pad[7] ( .I(IOLDO), .PAD(RAout7)); - - specify - (IOLDO => RAout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_7__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_6_ ( input IOLDO, output RAout6 ); - - xo2iobuf0145 \RAout_pad[6] ( .I(IOLDO), .PAD(RAout6)); - - specify - (IOLDO => RAout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_6__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_5_ ( input IOLDO, output RAout5 ); - - xo2iobuf0145 \RAout_pad[5] ( .I(IOLDO), .PAD(RAout5)); - - specify - (IOLDO => RAout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_5__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_4_ ( input IOLDO, output RAout4 ); - - xo2iobuf0145 \RAout_pad[4] ( .I(IOLDO), .PAD(RAout4)); - - specify - (IOLDO => RAout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_4__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_3_ ( input IOLDO, output RAout3 ); - - xo2iobuf0145 \RAout_pad[3] ( .I(IOLDO), .PAD(RAout3)); - - specify - (IOLDO => RAout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_3__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_2_ ( input IOLDO, output RAout2 ); - - xo2iobuf0145 \RAout_pad[2] ( .I(IOLDO), .PAD(RAout2)); - - specify - (IOLDO => RAout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_2__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_1_ ( input IOLDO, output RAout1 ); - - xo2iobuf0145 \RAout_pad[1] ( .I(IOLDO), .PAD(RAout1)); - - specify - (IOLDO => RAout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_1__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_0_ ( input IOLDO, output RAout0 ); - - xo2iobuf0145 \RAout_pad[0] ( .I(IOLDO), .PAD(RAout0)); - - specify - (IOLDO => RAout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_0__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module BA_1_ ( input IOLDO, output BA1 ); - - xo2iobuf0145 \BA_pad[1] ( .I(IOLDO), .PAD(BA1)); - - specify - (IOLDO => BA1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module BA_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0148 \BA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module mfflsre0148 ( input D0, SP, CK, LSR, output Q ); - - FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module BA_0_ ( input IOLDO, output BA0 ); - - xo2iobuf0145 \BA_pad[0] ( .I(IOLDO), .PAD(BA0)); - - specify - (IOLDO => BA0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module BA_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0148 \BA_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module nRWEout ( input IOLDO, output nRWEout ); - - xo2iobuf0145 nRWEout_pad( .I(IOLDO), .PAD(nRWEout)); - - specify - (IOLDO => nRWEout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRWEout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nRWEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nCASout ( input IOLDO, output nCASout ); - - xo2iobuf0145 nCASout_pad( .I(IOLDO), .PAD(nCASout)); - - specify - (IOLDO => nCASout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nCASout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nCASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nRASout ( input IOLDO, output nRASout ); - - xo2iobuf0145 nRASout_pad( .I(IOLDO), .PAD(nRASout)); - - specify - (IOLDO => nRASout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRASout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nRASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nCSout ( input PADDO, output nCSout ); - - xo2iobuf0145 nCSout_pad( .I(PADDO), .PAD(nCSout)); - - specify - (PADDO => nCSout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CKEout ( input IOLDO, output CKEout ); - - xo2iobuf0145 CKEout_pad( .I(IOLDO), .PAD(CKEout)); - - specify - (IOLDO => CKEout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CKEout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 CKEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nVOE ( input PADDO, output nVOE ); - - xo2iobuf0145 nVOE_pad( .I(PADDO), .PAD(nVOE)); - - specify - (PADDO => nVOE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_7_ ( input IOLDO, output Vout7 ); - - xo2iobuf0145 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7)); - - specify - (IOLDO => Vout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_6_ ( input IOLDO, output Vout6 ); - - xo2iobuf0145 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6)); - - specify - (IOLDO => Vout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_5_ ( input IOLDO, output Vout5 ); - - xo2iobuf0145 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5)); - - specify - (IOLDO => Vout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_4_ ( input IOLDO, output Vout4 ); - - xo2iobuf0145 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4)); - - specify - (IOLDO => Vout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_3_ ( input IOLDO, output Vout3 ); - - xo2iobuf0145 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3)); - - specify - (IOLDO => Vout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_2_ ( input IOLDO, output Vout2 ); - - xo2iobuf0145 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2)); - - specify - (IOLDO => Vout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_1_ ( input IOLDO, output Vout1 ); - - xo2iobuf0145 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1)); - - specify - (IOLDO => Vout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_0_ ( input IOLDO, output Vout0 ); - - xo2iobuf0145 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0)); - - specify - (IOLDO => Vout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module nDOE ( input PADDO, output nDOE ); - - xo2iobuf0145 nDOE_pad( .I(PADDO), .PAD(nDOE)); - - specify - (PADDO => nDOE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_7_ ( input PADDO, output Dout7 ); - - xo2iobuf0145 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); - - specify - (PADDO => Dout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_6_ ( input PADDO, output Dout6 ); - - xo2iobuf0145 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); - - specify - (PADDO => Dout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_5_ ( input PADDO, output Dout5 ); - - xo2iobuf0145 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); - - specify - (PADDO => Dout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_4_ ( input PADDO, output Dout4 ); - - xo2iobuf0145 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); - - specify - (PADDO => Dout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_3_ ( input PADDO, output Dout3 ); - - xo2iobuf0145 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); - - specify - (PADDO => Dout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_2_ ( input PADDO, output Dout2 ); - - xo2iobuf0145 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); - - specify - (PADDO => Dout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_1_ ( input PADDO, output Dout1 ); - - xo2iobuf0145 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); - - specify - (PADDO => Dout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_0_ ( input PADDO, output Dout0 ); - - xo2iobuf0145 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); - - specify - (PADDO => Dout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Din_7_ ( output PADDI, input Din7 ); - - xo2iobuf0146 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); - - specify - (Din7 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din7, 0:0:0); - $width (negedge Din7, 0:0:0); - endspecify - -endmodule - -module Din_6_ ( output PADDI, input Din6 ); - - xo2iobuf0146 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); - - specify - (Din6 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din6, 0:0:0); - $width (negedge Din6, 0:0:0); - endspecify - -endmodule - -module Din_5_ ( output PADDI, input Din5 ); - - xo2iobuf0146 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); - - specify - (Din5 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din5, 0:0:0); - $width (negedge Din5, 0:0:0); - endspecify - -endmodule - -module Din_4_ ( output PADDI, input Din4 ); - - xo2iobuf0146 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); - - specify - (Din4 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din4, 0:0:0); - $width (negedge Din4, 0:0:0); - endspecify - -endmodule - -module Din_3_ ( output PADDI, input Din3 ); - - xo2iobuf0146 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); - - specify - (Din3 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din3, 0:0:0); - $width (negedge Din3, 0:0:0); - endspecify - -endmodule - -module Din_2_ ( output PADDI, input Din2 ); - - xo2iobuf0146 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); - - specify - (Din2 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din2, 0:0:0); - $width (negedge Din2, 0:0:0); - endspecify - -endmodule - -module Din_1_ ( output PADDI, input Din1 ); - - xo2iobuf0146 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); - - specify - (Din1 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din1, 0:0:0); - $width (negedge Din1, 0:0:0); - endspecify - -endmodule - -module Din_0_ ( output PADDI, input Din0 ); - - xo2iobuf0146 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); - - specify - (Din0 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din0, 0:0:0); - $width (negedge Din0, 0:0:0); - endspecify - -endmodule - -module Ain_7_ ( output PADDI, input Ain7 ); - - xo2iobuf0146 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7)); - - specify - (Ain7 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain7, 0:0:0); - $width (negedge Ain7, 0:0:0); - endspecify - -endmodule - -module Ain_6_ ( output PADDI, input Ain6 ); - - xo2iobuf0146 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6)); - - specify - (Ain6 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain6, 0:0:0); - $width (negedge Ain6, 0:0:0); - endspecify - -endmodule - -module Ain_5_ ( output PADDI, input Ain5 ); - - xo2iobuf0146 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5)); - - specify - (Ain5 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain5, 0:0:0); - $width (negedge Ain5, 0:0:0); - endspecify - -endmodule - -module Ain_4_ ( output PADDI, input Ain4 ); - - xo2iobuf0146 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4)); - - specify - (Ain4 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain4, 0:0:0); - $width (negedge Ain4, 0:0:0); - endspecify - -endmodule - -module Ain_3_ ( output PADDI, input Ain3 ); - - xo2iobuf0146 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3)); - - specify - (Ain3 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain3, 0:0:0); - $width (negedge Ain3, 0:0:0); - endspecify - -endmodule - -module Ain_2_ ( output PADDI, input Ain2 ); - - xo2iobuf0146 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2)); - - specify - (Ain2 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain2, 0:0:0); - $width (negedge Ain2, 0:0:0); - endspecify - -endmodule - -module Ain_1_ ( output PADDI, input Ain1 ); - - xo2iobuf0146 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1)); - - specify - (Ain1 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain1, 0:0:0); - $width (negedge Ain1, 0:0:0); - endspecify - -endmodule - -module Ain_0_ ( output PADDI, input Ain0 ); - - xo2iobuf0146 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0)); - - specify - (Ain0 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain0, 0:0:0); - $width (negedge Ain0, 0:0:0); - endspecify - -endmodule - -module nC07X ( output PADDI, input nC07X ); - - xo2iobuf0146 nC07X_pad( .Z(PADDI), .PAD(nC07X)); - - specify - (nC07X => PADDI) = (0:0:0,0:0:0); - $width (posedge nC07X, 0:0:0); - $width (negedge nC07X, 0:0:0); - endspecify - -endmodule - -module nEN80 ( output PADDI, input nEN80 ); - - xo2iobuf0146 nEN80_pad( .Z(PADDI), .PAD(nEN80)); - - specify - (nEN80 => PADDI) = (0:0:0,0:0:0); - $width (posedge nEN80, 0:0:0); - $width (negedge nEN80, 0:0:0); - endspecify - -endmodule - -module nWE ( output PADDI, input nWE ); - - xo2iobuf0146 nWE_pad( .Z(PADDI), .PAD(nWE)); - - specify - (nWE => PADDI) = (0:0:0,0:0:0); - $width (posedge nWE, 0:0:0); - $width (negedge nWE, 0:0:0); - endspecify - -endmodule - -module PHI1 ( output PADDI, input PHI1 ); - - xo2iobuf0146 PHI1_pad( .Z(PADDI), .PAD(PHI1)); - - specify - (PHI1 => PADDI) = (0:0:0,0:0:0); - $width (posedge PHI1, 0:0:0); - $width (negedge PHI1, 0:0:0); - endspecify - -endmodule - -module PHI1_MGIOL ( input DI, CLK, output IN ); - wire VCCI, GNDI, DI_dly, CLK_dly; - - smuxlregsre PHI1r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), - .Q(IN)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IN) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module smuxlregsre ( input D0, SP, CK, LSR, output Q ); - - IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module ram2e_ufm_ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, - WBWEI, WBADRI0, WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, - WBADRI7, WBDATI0, WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, - WBDATI7, output WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, - WBDATO6, WBDATO7, WBACKO ); - wire VCCI, GNDI; - - EFB_B \ram2e_ufm/ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), - .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), - .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), - .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), - .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), - .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), - .WBDATO1(WBDATO1), .WBDATO2(WBDATO2), .WBDATO3(WBDATO3), .WBDATO4(WBDATO4), - .WBDATO5(WBDATO5), .WBDATO6(WBDATO6), .WBDATO7(WBDATO7), .WBACKO(WBACKO), - .WBCUFMIRQ(), .UFMSN(VCCI), .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), - .I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), - .I2C2SCLI(GNDI), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), - .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), - .SPISCKEN(), .SPIMISOI(GNDI), .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), - .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), - .SPIMCSN3(), .SPIMCSN4(), .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), - .SPICSNEN(), .SPISCSN(GNDI), .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), - .TCIC(GNDI), .TCINT(), .TCOC(), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), - .PLL1STBO(), .PLLWEO(), .PLLADRO0(), .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), - .PLLADRO4(), .PLLDATO0(), .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), - .PLLDATO4(), .PLLDATO5(), .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), - .PLL0DATI1(GNDI), .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), - .PLL0DATI5(GNDI), .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), - .PLL1DATI0(GNDI), .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), - .PLL1DATI4(GNDI), .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), - .PLL1ACKI(GNDI)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); -endmodule - -module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, - WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, - WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, - WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, - WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output - I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input - I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, - I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, - input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output - SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, - SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, - input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, - PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, - PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, - PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, - PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, - PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI ); - wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, - WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, - WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, - WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, - WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, - PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, - PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, - PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, - PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, - I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, - SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, - UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, - WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, - PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, - PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, - PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, - PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, - I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, - I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, - I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, - SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, - SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, - SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, - CFGWAKE_buf, CFGSTDBY_buf; - - EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), - .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), - .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), - .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), - .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), - .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), - .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), - .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), - .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), - .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), - .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), - .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), - .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), - .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), - .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), - .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), - .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), - .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), - .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), - .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), - .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), - .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), - .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), - .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), - .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), - .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), - .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), - .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), - .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), - .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), - .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), - .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), - .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), - .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), - .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), - .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), - .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), - .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), - .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), - .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), - .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), - .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf)); - defparam INST10.DEV_DENSITY = "1200L"; - defparam INST10.EFB_I2C1 = "DISABLED"; - defparam INST10.EFB_I2C2 = "DISABLED"; - defparam INST10.EFB_SPI = "DISABLED"; - defparam INST10.EFB_TC = "DISABLED"; - defparam INST10.EFB_TC_PORTMODE = "WB"; - defparam INST10.EFB_UFM = "ENABLED"; - defparam INST10.EFB_WB_CLK_FREQ = "14.4"; - defparam INST10.GSR = "ENABLED"; - defparam INST10.I2C1_ADDRESSING = "7BIT"; - defparam INST10.I2C1_BUS_PERF = "100kHz"; - defparam INST10.I2C1_CLK_DIVIDER = 1; - defparam INST10.I2C1_GEN_CALL = "DISABLED"; - defparam INST10.I2C1_SLAVE_ADDR = "0b1000001"; - defparam INST10.I2C1_WAKEUP = "DISABLED"; - defparam INST10.I2C2_ADDRESSING = "7BIT"; - defparam INST10.I2C2_BUS_PERF = "100kHz"; - defparam INST10.I2C2_CLK_DIVIDER = 1; - defparam INST10.I2C2_GEN_CALL = "DISABLED"; - defparam INST10.I2C2_SLAVE_ADDR = "0b1000010"; - defparam INST10.I2C2_WAKEUP = "DISABLED"; - defparam INST10.SPI_CLK_DIVIDER = 1; - defparam INST10.SPI_CLK_INV = "DISABLED"; - defparam INST10.SPI_INTR_RXOVR = "DISABLED"; - defparam INST10.SPI_INTR_RXRDY = "DISABLED"; - defparam INST10.SPI_INTR_TXOVR = "DISABLED"; - defparam INST10.SPI_INTR_TXRDY = "DISABLED"; - defparam INST10.SPI_LSB_FIRST = "DISABLED"; - defparam INST10.SPI_MODE = "MASTER"; - defparam INST10.SPI_PHASE_ADJ = "DISABLED"; - defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED"; - defparam INST10.SPI_WAKEUP = "DISABLED"; - defparam INST10.TC_CCLK_SEL = 1; - defparam INST10.TC_ICAPTURE = "DISABLED"; - defparam INST10.TC_ICR_INT = "OFF"; - defparam INST10.TC_MODE = "CTCM"; - defparam INST10.TC_OCR_INT = "OFF"; - defparam INST10.TC_OCR_SET = 32767; - defparam INST10.TC_OC_MODE = "TOGGLE"; - defparam INST10.TC_OVERFLOW = "DISABLED"; - defparam INST10.TC_OV_INT = "OFF"; - defparam INST10.TC_RESETN = "ENABLED"; - defparam INST10.TC_SCLK_SEL = "PCLOCK"; - defparam INST10.TC_TOP_SEL = "OFF"; - defparam INST10.TC_TOP_SET = 65535; - defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED"; - defparam INST10.UFM_INIT_FILE_FORMAT = "HEX"; - defparam INST10.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem"; - defparam INST10.UFM_INIT_PAGES = 321; - defparam INST10.UFM_INIT_START_PAGE = 190; - EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), - .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), - .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), - .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), - .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), - .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), - .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), - .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), - .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), - .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), - .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), - .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), - .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), - .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), - .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), - .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), - .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), - .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), - .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), - .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), - .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), - .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), - .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), - .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), - .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), - .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), - .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), - .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), - .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), - .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), - .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), - .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), - .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), - .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), - .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), - .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), - .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), - .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), - .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), - .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), - .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), - .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), - .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), - .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), - .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), - .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), - .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), - .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), - .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), - .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), - .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), - .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), - .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), - .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), - .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), - .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), - .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), - .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), - .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), - .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), - .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), - .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), - .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), - .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), - .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), - .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), - .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), - .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), - .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), - .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), - .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), - .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), - .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), - .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), - .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), - .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), - .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), - .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), - .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), - .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), - .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), - .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), - .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), - .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), - .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), - .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), - .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), - .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), - .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), - .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), - .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), - .CFGSTDBYin(CFGSTDBY_buf)); -endmodule - -module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, - output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, - output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output - WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output - WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output - WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output - WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output - WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output - WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output - WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output - WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output - PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, - output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input - PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, - input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output - PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, - output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input - PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, - input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output - PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, - output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input - I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, - input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, - input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, - input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, - input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input - TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input - WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input - WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input - WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input - WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input - WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input - PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, - input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, - input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, - input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, - input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, - input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, - input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, - input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, - input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output - I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, - output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input - I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, - input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output - I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, - output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, - output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input - SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, - input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output - SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, - output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, - output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, - output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, - output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, - output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, - output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin ); - wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, - WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, - WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, - WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, - WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly; - - BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout)); - BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout)); - BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout)); - BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout)); - BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout)); - BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out)); - BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out)); - BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out)); - BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out)); - BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out)); - BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out)); - BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out)); - BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out)); - BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out)); - BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out)); - BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out)); - BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out)); - BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out)); - BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out)); - BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out)); - BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out)); - BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out)); - BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out)); - BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out)); - BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out)); - BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out)); - BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out)); - BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out)); - BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out)); - BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout)); - BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out)); - BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out)); - BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out)); - BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out)); - BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out)); - BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out)); - BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out)); - BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out)); - BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout)); - BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout)); - BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout)); - BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout)); - BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout)); - BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout)); - BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout)); - BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout)); - BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout)); - BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout)); - BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout)); - BUFBA TCIC_buf( .A(TCICin), .Z(TCICout)); - BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout)); - BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out)); - BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out)); - BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out)); - BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out)); - BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out)); - BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out)); - BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out)); - BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out)); - BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout)); - BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout)); - BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout)); - BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout)); - BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout)); - BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout)); - BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out)); - BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out)); - BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out)); - BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out)); - BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out)); - BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out)); - BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out)); - BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out)); - BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out)); - BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out)); - BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out)); - BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out)); - BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out)); - BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout)); - BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout)); - BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout)); - BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout)); - BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout)); - BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout)); - BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout)); - BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout)); - BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout)); - BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout)); - BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout)); - BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout)); - BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout)); - BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout)); - BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout)); - BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout)); - BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out)); - BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out)); - BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out)); - BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out)); - BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out)); - BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out)); - BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out)); - BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out)); - BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout)); - BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout)); - BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout)); - BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout)); - BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout)); - BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout)); - BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout)); - - specify - (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO2out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO3out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO4out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO5out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO6out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO7out) = (0:0:0,0:0:0); - (WBCLKIin => WBACKOout) = (0:0:0,0:0:0); - $setuphold - (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly); - $setuphold - (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly); - $setuphold - (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly); - $setuphold - (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly); - $setuphold - (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly); - $setuphold - (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly); - $setuphold - (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly); - $setuphold - (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly); - $setuphold - (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly); - $setuphold - (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly); - $setuphold - (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly); - $setuphold - (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly); - $setuphold - (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly); - $setuphold - (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly); - $setuphold - (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly); - $setuphold - (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly); - $setuphold - (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly); - $setuphold - (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly); - $setuphold - (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly); - $setuphold - (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly); - $width (posedge WBCLKIin, 0:0:0); - $width (negedge WBCLKIin, 0:0:0); - endspecify - -endmodule diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html deleted file mode 100644 index 3534442..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html +++ /dev/null @@ -1,487 +0,0 @@ - -Project Summary - - -

-            Lattice Mapping Report File for Design Module 'RAM2E'
-
-
-
-Design Information
-
-Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
-     RAM2E_LCMXO2_1200HC_impl1.ngd -o RAM2E_LCMXO2_1200HC_impl1_map.ncd -pr
-     RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
-     iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synpl
-     ify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
-     -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml 
-Target Vendor:  LATTICE
-Target Device:  LCMXO2-1200HCTQFP100
-Target Performance:   4
-Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  12/28/23  23:23:27
-
-
-Design Summary
-   Number of registers:    122 out of  1520 (8%)
-      PFU registers:           93 out of  1280 (7%)
-      PIO registers:           29 out of   240 (12%)
-   Number of SLICEs:       148 out of   640 (23%)
-      SLICEs as Logic/ROM:    148 out of   640 (23%)
-      SLICEs as RAM:            0 out of   480 (0%)
-      SLICEs as Carry:          9 out of   640 (1%)
-   Number of LUT4s:        296 out of  1280 (23%)
-      Number used as logic LUTs:        278
-      Number used as distributed RAM:     0
-      Number used as ripple logic:       18
-      Number used as shift registers:     0
-   Number of PIO sites used: 69 + 4(JTAG) out of 80 (91%)
-   Number of block RAMs:  0 out of 7 (0%)
-   Number of GSRs:        0 out of 1 (0%)
-   EFB used :        Yes
-   JTAG used :       No
-   Readback used :   No
-   Oscillator used : No
-   Startup used :    No
-   POR :             On
-   Bandgap :         On
-   Number of Power Controller:  0 out of 1 (0%)
-   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
-   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
-   Number of DCCA:  0 out of 8 (0%)
-   Number of DCMA:  0 out of 2 (0%)
-   Number of PLLs:  0 out of 1 (0%)
-   Number of DQSDLLs:  0 out of 2 (0%)
-   Number of CLKDIVC:  0 out of 4 (0%)
-   Number of ECLKSYNCA:  0 out of 4 (0%)
-   Number of ECLKBRIDGECS:  0 out of 2 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
-     distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and
-     ripple logic.
-   Number of clocks:  1
-     Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M )
-   Number of Clock Enables:  14
-
-     Net N_225_i: 2 loads, 0 LSLICEs
-     Net N_201_i: 2 loads, 0 LSLICEs
-     Net N_187_i: 11 loads, 11 LSLICEs
-     Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
-     Net RC12: 2 loads, 2 LSLICEs
-     Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs
-     Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs
-     Net N_185_i: 2 loads, 2 LSLICEs
-     Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs
-     Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs
-     Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs
-     Net N_126: 6 loads, 6 LSLICEs
-     Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs
-     Net Vout3: 8 loads, 0 LSLICEs
-   Number of LSRs:  7
-     Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
-     Net BA_0_sqmuxa: 2 loads, 0 LSLICEs
-     Net S[2]: 1 loads, 1 LSLICEs
-     Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
-     Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs
-     Net N_1080_0: 1 loads, 1 LSLICEs
-     Net N_1078_0: 1 loads, 1 LSLICEs
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net S[2]: 50 loads
-     Net S[3]: 45 loads
-     Net S[0]: 37 loads
-     Net S[1]: 34 loads
-     Net FS[12]: 24 loads
-     Net FS[11]: 22 loads
-     Net FS[10]: 19 loads
-     Net FS[13]: 19 loads
-     Net FS[9]: 19 loads
-     Net FS[8]: 18 loads
-
-
-
-
-   Number of warnings:  3
-   Number of errors:    0
-     
-
-
-
-
-Design Errors/Warnings
-
-WARNING - map: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf(93): Semantic
-     error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
-     "nWE80" does not exist in the design. This preference has been disabled.
-WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
-     temporarily disable certain features of the device including Power
-     Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
-     Functionality is restored after the Flash Memory (UFM/Configuration)
-     Interface is disabled using Disable Configuration Interface command 0x26
-     followed by Bypass command 0xFF. 
-WARNING - map: IO buffer missing for top level port nWE80...logic will be
-     discarded.
-
-
-
-
-IO (PIO) Attributes
-
-+---------------------+-----------+-----------+------------+
-| IO Name             | Direction | Levelmode | IO         |
-|                     |           |  IO_TYPE  | Register   |
-+---------------------+-----------+-----------+------------+
-| RD[0]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| LED                 | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| C14M                | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[7]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[6]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[5]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[4]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[3]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[2]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[1]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| DQML                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[11]           | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[10]           | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[9]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[8]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[7]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[6]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[5]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[4]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[3]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[2]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[1]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[0]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| BA[1]               | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-
-| BA[0]               | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nRWEout             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nCASout             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nRASout             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nCSout              | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| CKEout              | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nVOE                | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Vout[7]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[6]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[5]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[4]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[3]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[2]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[1]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[0]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nDOE                | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[7]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[6]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[5]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[4]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[3]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[2]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[1]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[0]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[7]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[6]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[5]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[4]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-
-| Din[3]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[2]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[1]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[0]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[7]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[6]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[5]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[4]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[3]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[2]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[1]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[0]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| nC07X               | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| nEN80               | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| nWE                 | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| PHI1                | INPUT     | LVCMOS33  | IN         |
-+---------------------+-----------+-----------+------------+
-
-
-
-Removed logic
-
-Block GSR_INST undriven or does not drive anything - clipped.
-Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
-Block ram2e_ufm/GND undriven or does not drive anything - clipped.
-Signal CKEout.CN was merged into signal C14M_c
-Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
-Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
-Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
-     clipped.
-Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
-
-Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
-     
-Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
-     
-Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
-     clipped.
-Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
-     clipped.
-Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
-     clipped.
-Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
-     clipped.
-Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
-Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
-Signal N_1 undriven or does not drive anything - clipped.
-Block nCASout.CN was optimized away.
-Block ram2e_ufm/ufmefb/VCC was optimized away.
-Block ram2e_ufm/ufmefb/GND was optimized away.
-
-     
-
-
-
-Embedded Functional Block Connection Summary
-
-   Desired WISHBONE clock frequency: 14.4 MHz
-
-   Clock source:                     C14M_c
-   Reset source:                     ram2e_ufm/wb_rst
-   Functions mode:
-      I2C #1 (Primary) Function:     DISABLED
-      I2C #2 (Secondary) Function:   DISABLED
-      SPI Function:                  DISABLED
-      Timer/Counter Function:        DISABLED
-      Timer/Counter Mode:            WB
-      UFM Connection:                ENABLED
-      PLL0 Connection:               DISABLED
-      PLL1 Connection:               DISABLED
-   I2C Function Summary:
-   --------------------
-      None
-   SPI Function Summary:
-   --------------------
-      None
-   Timer/Counter Function Summary:
-   ------------------------------
-      None
-   UFM Function Summary:
-   --------------------
-      UFM Utilization:        General Purpose Flash Memory
-      Initialized UFM Pages:  321 Pages (321*128 Bits)
-      Available General
-      Purpose Flash Memory:   511 Pages (511*128 Bits)
-
-           EBR Blocks with Unique
-      Initialization Data:    0
-
-           WID		EBR Instance
-      ---		------------
-
-
-
-
-ASIC Components
----------------
-
-Instance Name: ram2e_ufm/ufmefb/EFBInst_0
-         Type: EFB
-
-
-
-Run Time and Memory Usage
--------------------------
-
-   Total CPU Time: 0 secs  
-   Total REAL Time: 0 secs  
-   Peak Memory Usage: 64 MB
-        
-
-
-
-
-
-
-
-
-
-
-
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-     Copyright (c) 1995 AT&T Corp.   All rights reserved.
-     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-     Copyright (c) 2001 Agere Systems   All rights reserved.
-     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
-     reserved.
-
-
-
-

-

-

-

-

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-

-

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-

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-

-

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-
- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html deleted file mode 100644 index 64cc09c..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html +++ /dev/null @@ -1,378 +0,0 @@ - -PAD Specification File - - -
PAD Specification File
-***************************
-
-PART TYPE:        LCMXO2-1200HC
-Performance Grade:      4
-PACKAGE:          TQFP100
-Package Status:                     Final          Version 1.44
-
-Thu Dec 28 23:23:38 2023
-
-Pinout by Port Name:
-+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
-| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                                 |
-+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
-| Ain[0]    | 3/3      | LVCMOS33_IN   | PL3A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[1]    | 2/3      | LVCMOS33_IN   | PL2D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[2]    | 7/3      | LVCMOS33_IN   | PL3C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[3]    | 4/3      | LVCMOS33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[4]    | 78/0     | LVCMOS33_IN   | PT16C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[5]    | 84/0     | LVCMOS33_IN   | PT15A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[6]    | 86/0     | LVCMOS33_IN   | PT12C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[7]    | 8/3      | LVCMOS33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| BA[0]     | 58/1     | LVCMOS33_OUT  | PR9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| BA[1]     | 60/1     | LVCMOS33_OUT  | PR8C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| C14M      | 62/1     | LVCMOS33_IN   | PR5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| CKEout    | 53/1     | LVCMOS33_OUT  | PR9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| DQMH      | 49/2     | LVCMOS33_OUT  | PB20D |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| DQML      | 48/2     | LVCMOS33_OUT  | PB20C |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Din[0]    | 96/0     | LVCMOS33_IN   | PT10B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[1]    | 97/0     | LVCMOS33_IN   | PT10A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[2]    | 98/0     | LVCMOS33_IN   | PT9B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[3]    | 9/3      | LVCMOS33_IN   | PL4A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[4]    | 1/3      | LVCMOS33_IN   | PL2C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[5]    | 99/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[6]    | 88/0     | LVCMOS33_IN   | PT12A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[7]    | 87/0     | LVCMOS33_IN   | PT12B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| LED       | 35/2     | LVCMOS33_OUT  | PB9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| PHI1      | 85/0     | LVCMOS33_IN   | PT12D |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| RAout[0]  | 66/1     | LVCMOS33_OUT  | PR4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[10] | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[11] | 59/1     | LVCMOS33_OUT  | PR8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[1]  | 68/1     | LVCMOS33_OUT  | PR4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[2]  | 70/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[3]  | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[4]  | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[5]  | 71/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[6]  | 69/1     | LVCMOS33_OUT  | PR4A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[7]  | 67/1     | LVCMOS33_OUT  | PR4C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[8]  | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[9]  | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RD[0]     | 36/2     | LVCMOS33_BIDI | PB11C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[1]     | 37/2     | LVCMOS33_BIDI | PB11D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[2]     | 38/2     | LVCMOS33_BIDI | PB11A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[3]     | 39/2     | LVCMOS33_BIDI | PB11B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[4]     | 40/2     | LVCMOS33_BIDI | PB15A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[5]     | 41/2     | LVCMOS33_BIDI | PB15B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[6]     | 42/2     | LVCMOS33_BIDI | PB18A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[7]     | 43/2     | LVCMOS33_BIDI | PB18B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| Vout[0]   | 18/3     | LVCMOS33_OUT  | PL8C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[1]   | 15/3     | LVCMOS33_OUT  | PL5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[2]   | 17/3     | LVCMOS33_OUT  | PL8B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[3]   | 13/3     | LVCMOS33_OUT  | PL5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[4]   | 19/3     | LVCMOS33_OUT  | PL8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[5]   | 16/3     | LVCMOS33_OUT  | PL8A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[6]   | 14/3     | LVCMOS33_OUT  | PL5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[7]   | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nC07X     | 34/2     | LVCMOS33_IN   | PB9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nCASout   | 52/1     | LVCMOS33_OUT  | PR10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nCSout    | 57/1     | LVCMOS33_OUT  | PR9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nDOE      | 20/3     | LVCMOS33_OUT  | PL9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nEN80     | 82/0     | LVCMOS33_IN   | PT15C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nRASout   | 54/1     | LVCMOS33_OUT  | PR9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nRWEout   | 51/1     | LVCMOS33_OUT  | PR10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nVOE      | 10/3     | LVCMOS33_OUT  | PL4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nWE       | 29/2     | LVCMOS33_IN   | PB6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
-
-Vccio by Bank:
-+------+-------+
-| Bank | Vccio |
-+------+-------+
-| 0    | 3.3V  |
-| 1    | 3.3V  |
-| 2    | 3.3V  |
-| 3    | 3.3V  |
-+------+-------+
-
-
-Vref by Bank:
-+------+-----+-----------------+---------+
-| Vref | Pin | Bank # / Vref # | Load(s) |
-+------+-----+-----------------+---------+
-+------+-----+-----------------+---------+
-
-Pinout by Pin Number:
-+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
-| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
-+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
-| 1/3      | Din[4]                | LOCATED    | LVCMOS33_IN   | PL2C  | L_GPLLT_IN    |           |           |
-| 2/3      | Ain[1]                | LOCATED    | LVCMOS33_IN   | PL2D  | L_GPLLC_IN    |           |           |
-| 3/3      | Ain[0]                | LOCATED    | LVCMOS33_IN   | PL3A  | PCLKT3_2      |           |           |
-| 4/3      | Ain[3]                | LOCATED    | LVCMOS33_IN   | PL3B  | PCLKC3_2      |           |           |
-| 7/3      | Ain[2]                | LOCATED    | LVCMOS33_IN   | PL3C  |               |           |           |
-| 8/3      | Ain[7]                | LOCATED    | LVCMOS33_IN   | PL3D  |               |           |           |
-| 9/3      | Din[3]                | LOCATED    | LVCMOS33_IN   | PL4A  |               |           |           |
-| 10/3     | nVOE                  | LOCATED    | LVCMOS33_OUT  | PL4B  |               |           |           |
-| 12/3     | Vout[7]               | LOCATED    | LVCMOS33_OUT  | PL5A  | PCLKT3_1      |           |           |
-| 13/3     | Vout[3]               | LOCATED    | LVCMOS33_OUT  | PL5B  | PCLKC3_1      |           |           |
-| 14/3     | Vout[6]               | LOCATED    | LVCMOS33_OUT  | PL5C  |               |           |           |
-| 15/3     | Vout[1]               | LOCATED    | LVCMOS33_OUT  | PL5D  |               |           |           |
-| 16/3     | Vout[5]               | LOCATED    | LVCMOS33_OUT  | PL8A  |               |           |           |
-| 17/3     | Vout[2]               | LOCATED    | LVCMOS33_OUT  | PL8B  |               |           |           |
-| 18/3     | Vout[0]               | LOCATED    | LVCMOS33_OUT  | PL8C  |               |           |           |
-| 19/3     | Vout[4]               | LOCATED    | LVCMOS33_OUT  | PL8D  |               |           |           |
-| 20/3     | nDOE                  | LOCATED    | LVCMOS33_OUT  | PL9A  | PCLKT3_0      |           |           |
-| 21/3     | Dout[5]               | LOCATED    | LVCMOS33_OUT  | PL9B  | PCLKC3_0      |           |           |
-| 24/3     | Dout[4]               | LOCATED    | LVCMOS33_OUT  | PL10C |               |           |           |
-| 25/3     | Dout[2]               | LOCATED    | LVCMOS33_OUT  | PL10D |               |           |           |
-| 27/2     | Dout[1]               | LOCATED    | LVCMOS33_OUT  | PB4C  | CSSPIN        |           |           |
-| 28/2     | Dout[3]               | LOCATED    | LVCMOS33_OUT  | PB4D  |               |           |           |
-| 29/2     | nWE                   | LOCATED    | LVCMOS33_IN   | PB6A  |               |           |           |
-| 30/2     | Dout[0]               | LOCATED    | LVCMOS33_OUT  | PB6B  |               |           |           |
-| 31/2     | Dout[6]               | LOCATED    | LVCMOS33_OUT  | PB6C  | MCLK/CCLK     |           |           |
-| 32/2     | Dout[7]               | LOCATED    | LVCMOS33_OUT  | PB6D  | SO/SPISO      |           |           |
-| 34/2     | nC07X                 | LOCATED    | LVCMOS33_IN   | PB9A  | PCLKT2_0      |           |           |
-| 35/2     | LED                   | LOCATED    | LVCMOS33_OUT  | PB9B  | PCLKC2_0      |           |           |
-| 36/2     | RD[0]                 | LOCATED    | LVCMOS33_BIDI | PB11C |               |           |           |
-| 37/2     | RD[1]                 | LOCATED    | LVCMOS33_BIDI | PB11D |               |           |           |
-| 38/2     | RD[2]                 | LOCATED    | LVCMOS33_BIDI | PB11A | PCLKT2_1      |           |           |
-| 39/2     | RD[3]                 | LOCATED    | LVCMOS33_BIDI | PB11B | PCLKC2_1      |           |           |
-| 40/2     | RD[4]                 | LOCATED    | LVCMOS33_BIDI | PB15A |               |           |           |
-| 41/2     | RD[5]                 | LOCATED    | LVCMOS33_BIDI | PB15B |               |           |           |
-| 42/2     | RD[6]                 | LOCATED    | LVCMOS33_BIDI | PB18A |               |           |           |
-| 43/2     | RD[7]                 | LOCATED    | LVCMOS33_BIDI | PB18B |               |           |           |
-| 45/2     |     unused, PULL:DOWN |            |               | PB18C |               |           |           |
-| 47/2     |     unused, PULL:DOWN |            |               | PB18D |               |           |           |
-| 48/2     | DQML                  | LOCATED    | LVCMOS33_OUT  | PB20C | SN            |           |           |
-| 49/2     | DQMH                  | LOCATED    | LVCMOS33_OUT  | PB20D | SI/SISPI      |           |           |
-| 51/1     | nRWEout               | LOCATED    | LVCMOS33_OUT  | PR10D | DQ1           |           |           |
-| 52/1     | nCASout               | LOCATED    | LVCMOS33_OUT  | PR10C | DQ1           |           |           |
-| 53/1     | CKEout                | LOCATED    | LVCMOS33_OUT  | PR9D  | DQ1           |           |           |
-| 54/1     | nRASout               | LOCATED    | LVCMOS33_OUT  | PR9C  | DQ1           |           |           |
-| 57/1     | nCSout                | LOCATED    | LVCMOS33_OUT  | PR9B  | DQ1           |           |           |
-| 58/1     | BA[0]                 | LOCATED    | LVCMOS33_OUT  | PR9A  | DQ1           |           |           |
-| 59/1     | RAout[11]             | LOCATED    | LVCMOS33_OUT  | PR8D  | DQ1           |           |           |
-| 60/1     | BA[1]                 | LOCATED    | LVCMOS33_OUT  | PR8C  | DQ1           |           |           |
-| 61/1     |     unused, PULL:DOWN |            |               | PR8A  | DQS1          |           |           |
-| 62/1     | C14M                  | LOCATED    | LVCMOS33_IN   | PR5D  | PCLKC1_0/DQ0  |           |           |
-| 63/1     | RAout[9]              | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0/DQ0  |           |           |
-| 64/1     | RAout[10]             | LOCATED    | LVCMOS33_OUT  | PR5B  | DQS0N         |           |           |
-| 65/1     | RAout[8]              | LOCATED    | LVCMOS33_OUT  | PR5A  | DQS0          |           |           |
-| 66/1     | RAout[0]              | LOCATED    | LVCMOS33_OUT  | PR4D  | DQ0           |           |           |
-| 67/1     | RAout[7]              | LOCATED    | LVCMOS33_OUT  | PR4C  | DQ0           |           |           |
-| 68/1     | RAout[1]              | LOCATED    | LVCMOS33_OUT  | PR4B  | DQ0           |           |           |
-| 69/1     | RAout[6]              | LOCATED    | LVCMOS33_OUT  | PR4A  | DQ0           |           |           |
-| 70/1     | RAout[2]              | LOCATED    | LVCMOS33_OUT  | PR3B  | DQ0           |           |           |
-| 71/1     | RAout[5]              | LOCATED    | LVCMOS33_OUT  | PR3A  | DQ0           |           |           |
-| 74/1     | RAout[3]              | LOCATED    | LVCMOS33_OUT  | PR2B  | DQ0           |           |           |
-| 75/1     | RAout[4]              | LOCATED    | LVCMOS33_OUT  | PR2A  | DQ0           |           |           |
-| 76/0     |     unused, PULL:DOWN |            |               | PT17D | DONE          |           |           |
-| 77/0     |     unused, PULL:DOWN |            |               | PT17C | INITN         |           |           |
-| 78/0     | Ain[4]                | LOCATED    | LVCMOS33_IN   | PT16C |               |           |           |
-| 81/0     |     unused, PULL:DOWN |            |               | PT15D | PROGRAMN      |           |           |
-| 82/0     | nEN80                 | LOCATED    | LVCMOS33_IN   | PT15C | JTAGENB       |           |           |
-| 83/0     |     unused, PULL:DOWN |            |               | PT15B |               |           |           |
-| 84/0     | Ain[5]                | LOCATED    | LVCMOS33_IN   | PT15A |               |           |           |
-| 85/0     | PHI1                  | LOCATED    | LVCMOS33_IN   | PT12D | SDA/PCLKC0_0  |           |           |
-| 86/0     | Ain[6]                | LOCATED    | LVCMOS33_IN   | PT12C | SCL/PCLKT0_0  |           |           |
-| 87/0     | Din[7]                | LOCATED    | LVCMOS33_IN   | PT12B | PCLKC0_1      |           |           |
-| 88/0     | Din[6]                | LOCATED    | LVCMOS33_IN   | PT12A | PCLKT0_1      |           |           |
-| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
-| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
-| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
-| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
-| 96/0     | Din[0]                | LOCATED    | LVCMOS33_IN   | PT10B |               |           |           |
-| 97/0     | Din[1]                | LOCATED    | LVCMOS33_IN   | PT10A |               |           |           |
-| 98/0     | Din[2]                | LOCATED    | LVCMOS33_IN   | PT9B  |               |           |           |
-| 99/0     | Din[5]                | LOCATED    | LVCMOS33_IN   | PT9A  |               |           |           |
-| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
-| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
-| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
-| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
-| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
-| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
-| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
-| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
-| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
-| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
-| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
-| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
-| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
-| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
-| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
-| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
-| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
-| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
-| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
-| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
-| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
-| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
-| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
-| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
-| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
-| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
-| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
-| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
-+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
-
-sysCONFIG Pins:
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
-| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
-| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
-| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-
-Dedicated sysCONFIG Pins:
-
-
-List of All Pins' Locate Preferences Based on Final Placement After PAR 
-to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
-
-LOCATE  COMP  "Ain[0]"  SITE  "3";
-LOCATE  COMP  "Ain[1]"  SITE  "2";
-LOCATE  COMP  "Ain[2]"  SITE  "7";
-LOCATE  COMP  "Ain[3]"  SITE  "4";
-LOCATE  COMP  "Ain[4]"  SITE  "78";
-LOCATE  COMP  "Ain[5]"  SITE  "84";
-LOCATE  COMP  "Ain[6]"  SITE  "86";
-LOCATE  COMP  "Ain[7]"  SITE  "8";
-LOCATE  COMP  "BA[0]"  SITE  "58";
-LOCATE  COMP  "BA[1]"  SITE  "60";
-LOCATE  COMP  "C14M"  SITE  "62";
-LOCATE  COMP  "CKEout"  SITE  "53";
-LOCATE  COMP  "DQMH"  SITE  "49";
-LOCATE  COMP  "DQML"  SITE  "48";
-LOCATE  COMP  "Din[0]"  SITE  "96";
-LOCATE  COMP  "Din[1]"  SITE  "97";
-LOCATE  COMP  "Din[2]"  SITE  "98";
-LOCATE  COMP  "Din[3]"  SITE  "9";
-LOCATE  COMP  "Din[4]"  SITE  "1";
-LOCATE  COMP  "Din[5]"  SITE  "99";
-LOCATE  COMP  "Din[6]"  SITE  "88";
-LOCATE  COMP  "Din[7]"  SITE  "87";
-LOCATE  COMP  "Dout[0]"  SITE  "30";
-LOCATE  COMP  "Dout[1]"  SITE  "27";
-LOCATE  COMP  "Dout[2]"  SITE  "25";
-LOCATE  COMP  "Dout[3]"  SITE  "28";
-LOCATE  COMP  "Dout[4]"  SITE  "24";
-LOCATE  COMP  "Dout[5]"  SITE  "21";
-LOCATE  COMP  "Dout[6]"  SITE  "31";
-LOCATE  COMP  "Dout[7]"  SITE  "32";
-LOCATE  COMP  "LED"  SITE  "35";
-LOCATE  COMP  "PHI1"  SITE  "85";
-LOCATE  COMP  "RAout[0]"  SITE  "66";
-LOCATE  COMP  "RAout[10]"  SITE  "64";
-LOCATE  COMP  "RAout[11]"  SITE  "59";
-LOCATE  COMP  "RAout[1]"  SITE  "68";
-LOCATE  COMP  "RAout[2]"  SITE  "70";
-LOCATE  COMP  "RAout[3]"  SITE  "74";
-LOCATE  COMP  "RAout[4]"  SITE  "75";
-LOCATE  COMP  "RAout[5]"  SITE  "71";
-LOCATE  COMP  "RAout[6]"  SITE  "69";
-LOCATE  COMP  "RAout[7]"  SITE  "67";
-LOCATE  COMP  "RAout[8]"  SITE  "65";
-LOCATE  COMP  "RAout[9]"  SITE  "63";
-LOCATE  COMP  "RD[0]"  SITE  "36";
-LOCATE  COMP  "RD[1]"  SITE  "37";
-LOCATE  COMP  "RD[2]"  SITE  "38";
-LOCATE  COMP  "RD[3]"  SITE  "39";
-LOCATE  COMP  "RD[4]"  SITE  "40";
-LOCATE  COMP  "RD[5]"  SITE  "41";
-LOCATE  COMP  "RD[6]"  SITE  "42";
-LOCATE  COMP  "RD[7]"  SITE  "43";
-LOCATE  COMP  "Vout[0]"  SITE  "18";
-LOCATE  COMP  "Vout[1]"  SITE  "15";
-LOCATE  COMP  "Vout[2]"  SITE  "17";
-LOCATE  COMP  "Vout[3]"  SITE  "13";
-LOCATE  COMP  "Vout[4]"  SITE  "19";
-LOCATE  COMP  "Vout[5]"  SITE  "16";
-LOCATE  COMP  "Vout[6]"  SITE  "14";
-LOCATE  COMP  "Vout[7]"  SITE  "12";
-LOCATE  COMP  "nC07X"  SITE  "34";
-LOCATE  COMP  "nCASout"  SITE  "52";
-LOCATE  COMP  "nCSout"  SITE  "57";
-LOCATE  COMP  "nDOE"  SITE  "20";
-LOCATE  COMP  "nEN80"  SITE  "82";
-LOCATE  COMP  "nRASout"  SITE  "54";
-LOCATE  COMP  "nRWEout"  SITE  "51";
-LOCATE  COMP  "nVOE"  SITE  "10";
-LOCATE  COMP  "nWE"  SITE  "29";
-
-
-
-
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Dec 28 23:23:42 2023
-
-
-
-
-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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-

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-

-
- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html deleted file mode 100644 index 4309f56..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html +++ /dev/null @@ -1,299 +0,0 @@ - -Place & Route Report - - -
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Dec 28 23:23:31 2023
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
-RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
-RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset
-//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
-
-
-Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
-
-Cost Table Summary
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            58.069       0            0.342        0            13           Completed
-* : Design saved.
-
-Total (real) run time for 1-seed: 13 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Lattice Place and Route Report for Design "RAM2E_LCMXO2_1200HC_impl1_map.ncd"
-Thu Dec 28 23:23:31 2023
-
-
-Best Par Run
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
-Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2E_LCMXO2_1200HC_impl1_map.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 4
-Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-
-Device utilization summary:
-
-   PIO (prelim)   69+4(JTAG)/108     68% used
-                  69+4(JTAG)/80      91% bonded
-   IOLOGIC           29/108          26% used
-
-   SLICE            148/640          23% used
-
-   EFB                1/1           100% used
-
-
-Number of Signals: 459
-Number of Connections: 1330
-
-Pin Constraint Summary:
-   69 out of 69 pins locked (100% locked).
-
-The following 1 signal is selected to use the primary clock routing resources:
-    C14M_c (driver: C14M, clk load #: 89)
-
-WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-
-The following 1 signal is selected to use the secondary clock routing resources:
-    N_187_i (driver: ram2e_ufm/SLICE_130, clk load #: 0, sr load #: 0, ce load #: 11)
-
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-........
-Finished Placer Phase 0.  REAL time: 2 secs 
-
-Starting Placer Phase 1.
-....................
-Placer score = 82860.
-Finished Placer Phase 1.  REAL time: 7 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  82610
-Finished Placer Phase 2.  REAL time: 7 secs 
-
-
-
-Clock Report
-
-Global Clock Resources:
-  CLK_PIN    : 0 out of 8 (0%)
-  General PIO: 1 out of 108 (0%)
-  PLL        : 0 out of 1 (0%)
-  DCM        : 0 out of 2 (0%)
-  DCC        : 0 out of 8 (0%)
-
-Global Clocks:
-  PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 89
-  SECONDARY "N_187_i" from F1 on comp "ram2e_ufm/SLICE_130" on site "R7C12C", clk load = 0, ce load = 11, sr load = 0
-
-  PRIMARY  : 1 out of 8 (12%)
-  SECONDARY: 1 out of 8 (12%)
-
-Edge Clocks:
-  No edge clock selected.
-
-
-
-
-I/O Usage Summary (final):
-   69 + 4(JTAG) out of 108 (67.6%) PIO sites used.
-   69 + 4(JTAG) out of 80 (91.3%) bonded PIO sites used.
-   Number of PIO comps: 69; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+-----------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref |
-+----------+----------------+------------+-----------+
-| 0        | 11 / 19 ( 57%) | 3.3V       | -         |
-| 1        | 20 / 21 ( 95%) | 3.3V       | -         |
-| 2        | 18 / 20 ( 90%) | 3.3V       | -         |
-| 3        | 20 / 20 (100%) | 3.3V       | -         |
-+----------+----------------+------------+-----------+
-
-Total placer CPU time: 6 secs 
-
-Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
-
-0 connections routed; 1330 unrouted.
-Starting router resource preassignment
-WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
-
-Completed router resource preassignment. Real time: 12 secs 
-
-Start NBR router at 23:23:43 12/28/23
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 23:23:43 12/28/23
-
-Start NBR section for initial routing at 23:23:43 12/28/23
-Level 4, iteration 1
-19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 58.075ns/0.000ns; real time: 12 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 23:23:43 12/28/23
-Level 4, iteration 1
-3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 12 secs 
-Level 4, iteration 2
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 12 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 23:23:43 12/28/23
-
-Start NBR section for re-routing at 23:23:43 12/28/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 12 secs 
-
-Start NBR section for post-routing at 23:23:43 12/28/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack<setup> : 58.069ns
-  Timing score<setup> : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-Total CPU time 12 secs 
-Total REAL time: 13 secs 
-Completely routed.
-End of route.  1330 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack<setup/<ns>> = 58.069
-PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
-PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.342
-PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 12 secs 
-Total REAL time to completion: 13 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
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- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt deleted file mode 100644 index 500b722..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt +++ /dev/null @@ -1,51 +0,0 @@ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 - -# Written on Thu Dec 28 23:23:22 2023 - -##### FILES SYNTAX CHECKED ############################################## -Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc" - -#Run constraint checker to find more issues with constraints. -######################################################################### - - - -No issues found in constraint syntax. - - - -Clock Summary -************* - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------- -0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122 - -0 - System 100.0 MHz 10.000 system system_clkgroup 0 -======================================================================================== - - -Clock Load Summary -****************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example ----------------------------------------------------------------------------------------- -C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv) - -System 0 - - - - -======================================================================================== diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html deleted file mode 100644 index e62cbf0..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html +++ /dev/null @@ -1,83 +0,0 @@ - -Project Summary - - -

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RAM2E_LCMXO2_1200HC project summary
Module Name:RAM2E_LCMXO2_1200HCSynthesis:SynplifyPro
Implementation Name:impl1Strategy Name:Strategy1
Last Process:State:
Target Device:LCMXO2-1200HC-4TG100CDevice Family:MachXO2
Device Type:LCMXO2-1200HCPackage Type:TQFP100
Performance grade:4Operating conditions:COM
Logic preference file:RAM2E-LCMXO2.lpf
Physical Preference file:impl1/RAM2E_LCMXO2_1200HC_impl1.prf
Product Version:3.12.1.454Patch Version:
Updated:2024/01/05 05:57:03
Implementation Location://Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1
Project File://Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf

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- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html deleted file mode 100644 index 51a4fa0..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html +++ /dev/null @@ -1,761 +0,0 @@ - -Synthesis Report - - -
Synthesis Report
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEMACWIN11
-
-# Thu Dec 28 23:23:19 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v" (library work)
-@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work)
-@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
-Verilog syntax check successful!
-File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling
-File \\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v changed - recompiling
-Selecting top level module RAM2E
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
-Running optimization stage 1 on VHI .......
-Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
-Running optimization stage 1 on VLO .......
-Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
-Running optimization stage 1 on EFB .......
-Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
-Running optimization stage 1 on REFB .......
-Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
-Running optimization stage 1 on RAM2E_UFM .......
-Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
-@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
-Running optimization stage 1 on RAM2E .......
-Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
-Running optimization stage 2 on RAM2E .......
-@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
-Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
-Running optimization stage 2 on RAM2E_UFM .......
-@N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
-Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-Running optimization stage 2 on REFB .......
-Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-Running optimization stage 2 on EFB .......
-Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-Running optimization stage 2 on VLO .......
-Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-Running optimization stage 2 on VHI .......
-Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Dec 28 23:23:19 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\layer0.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Dec 28 23:23:20 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Dec 28 23:23:20 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Dec 28 23:23:21 2023
-
-###########################################################]
-# Thu Dec 28 23:23:21 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
-
-Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
-@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt 
-See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 140MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
-
-@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
-@N: FX493 |Applying initial value "0" on instance PHI1r.
-@N: FX493 |Applying initial value "0" on instance RWSel.
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
-@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
-@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
-@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
-@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "1" on instance DQMH.
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "1" on instance DQML.
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "0000" on instance S[3:0].
-@N: FX493 |Applying initial value "1" on instance CKE.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-@N: FX493 |Applying initial value "1" on instance nRWEout.
-@N: FX493 |Applying initial value "1" on instance nCAS.
-@N: FX493 |Applying initial value "1" on instance nCASout.
-@N: FX493 |Applying initial value "1" on instance nRAS.
-@N: FX493 |Applying initial value "1" on instance nRASout.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
-
-
-
-Clock Summary
-******************
-
-          Start      Requested     Requested     Clock        Clock                Clock
-Level     Clock      Frequency     Period        Type         Group                Load 
-----------------------------------------------------------------------------------------
-0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     122  
-                                                                                        
-0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
-========================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-           Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock      Load      Pin            Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-C14M       122       C14M(port)     DOEEN.C         -                 un1_C14M.I[0](inv)
-                                                                                        
-System     0         -              -               -                 -                 
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       C14M                port                   122        nRAS           
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Dec 28 23:23:23 2023
-
-###########################################################]
-# Thu Dec 28 23:23:23 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
-
-@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-
-Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:01s		    33.71ns		 284 /       122
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
-@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
-
-Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)
-
-@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@N: MT615 |Found clock C14M with period 69.84ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Thu Dec 28 23:23:26 2023
-#
-
-
-Top view:               RAM2E
-Requested Frequency:    14.3 MHz
-Wire load mode:         top
-Paths requested:        5
-Constraint File(s):    \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 33.707
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-C14M               14.3 MHz      128.0 MHz     69.841        7.813         33.707     declared     default_clkgroup
-System             100.0 MHz     NA            10.000        NA            67.088     system       system_clkgroup 
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack
-----------------------------------------------------------------------------------------------------------
-System    C14M    |  69.841      67.088  |  No paths    -      |  No paths    -       |  No paths    -    
-C14M      System  |  69.841      68.797  |  No paths    -      |  No paths    -       |  No paths    -    
-C14M      C14M    |  69.841      62.028  |  No paths    -      |  34.920      33.707  |  No paths    -    
-==========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: C14M
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                    Arrival           
-Instance     Reference     Type        Pin     Net       Time        Slack 
-             Clock                                                         
----------------------------------------------------------------------------
-RA[0]        C14M          FD1P3AX     Q       RA[0]     1.108       33.707
-RA[3]        C14M          FD1P3AX     Q       RA[3]     1.108       33.707
-RA[1]        C14M          FD1P3AX     Q       RA[1]     1.044       33.771
-RA[2]        C14M          FD1P3AX     Q       RA[2]     1.044       33.771
-RA[4]        C14M          FD1P3AX     Q       RA[4]     1.044       33.771
-RA[5]        C14M          FD1P3AX     Q       RA[5]     1.044       33.771
-RA[6]        C14M          FD1P3AX     Q       RA[6]     1.044       33.771
-RA[7]        C14M          FD1P3AX     Q       RA[7]     1.044       33.771
-RA[8]        C14M          FD1P3AX     Q       RA[8]     1.044       33.771
-RA[9]        C14M          FD1P3AX     Q       RA[9]     1.044       33.771
-===========================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                     Required           
-Instance         Reference     Type         Pin     Net       Time         Slack 
-                 Clock                                                           
----------------------------------------------------------------------------------
-RAout_0io[0]     C14M          OFS1P3DX     D       RA[0]     34.815       33.707
-RAout_0io[3]     C14M          OFS1P3DX     D       RA[3]     34.815       33.707
-RAout_0io[1]     C14M          OFS1P3DX     D       RA[1]     34.815       33.771
-RAout_0io[2]     C14M          OFS1P3DX     D       RA[2]     34.815       33.771
-RAout_0io[4]     C14M          OFS1P3DX     D       RA[4]     34.815       33.771
-RAout_0io[5]     C14M          OFS1P3DX     D       RA[5]     34.815       33.771
-RAout_0io[6]     C14M          OFS1P3DX     D       RA[6]     34.815       33.771
-RAout_0io[7]     C14M          OFS1P3DX     D       RA[7]     34.815       33.771
-RAout_0io[8]     C14M          OFS1P3DX     D       RA[8]     34.815       33.771
-RAout_0io[9]     C14M          OFS1P3DX     D       RA[9]     34.815       33.771
-=================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      34.920
-    - Setup time:                            0.106
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         34.815
-
-    - Propagation time:                      1.108
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     33.707
-
-    Number of logic level(s):                0
-    Starting point:                          RA[0] / Q
-    Ending point:                            RAout_0io[0] / D
-    The start point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
-    The end   point is clocked by            C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-RA[0]              FD1P3AX      Q        Out     1.108     1.108 r     -         
-RA[0]              Net          -        -       -         -           3         
-RAout_0io[0]       OFS1P3DX     D        In      0.000     1.108 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                               Starting                                          Arrival           
-Instance                       Reference     Type     Pin         Net            Time        Slack 
-                               Clock                                                               
----------------------------------------------------------------------------------------------------
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
-===================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                         Starting                                                                  Required           
-Instance                 Reference     Type        Pin     Net                                     Time         Slack 
-                         Clock                                                                                        
-----------------------------------------------------------------------------------------------------------------------
-ram2e_ufm.RWMask[0]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[1]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[2]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[3]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[4]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[5]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[6]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[7]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0_0[0]           69.369       67.736
-ram2e_ufm.wb_cyc_stb     System        FD1P3AX     SP      un1_CmdSetRWBankFFChip13_1_i_0_0[0]     69.369       67.736
-======================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      69.841
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         69.369
-
-    - Propagation time:                      2.282
-    - Clock delay at starting point:         0.000 (ideal)
-    - Estimated clock delay at start point:  -0.000
-    = Slack (non-critical) :                 67.088
-
-    Number of logic level(s):                2
-    Starting point:                          ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
-    Ending point:                            ram2e_ufm.RWMask[0] / SP
-    The start point is clocked by            System [rising]
-    The end   point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
-
-Instance / Net                                                 Pin        Pin               Arrival     No. of    
-Name                                              Type         Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
-ram2e_ufm.ufmefb.EFBInst_0                        EFB          WBACKO     Out     0.000     0.000 r     -         
-wb_ack                                            Net          -          -       -         -           5         
-ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     B          In      0.000     0.000 r     -         
-ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     Z          Out     1.017     1.017 r     -         
-un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]               Net          -          -       -         -           1         
-ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
-ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
-un1_RWMask_0_sqmuxa_1_i_0_0[0]                    Net          -          -       -         -           8         
-ram2e_ufm.RWMask[0]                               FD1P3AX      SP         In      0.000     2.282 r     -         
-==================================================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo2_1200hc-4
-
-Register bits: 122 of 1280 (10%)
-PIC Latch:       0
-I/O cells:       69
-
-
-Details:
-BB:             8
-CCU2D:          9
-EFB:            1
-FD1P3AX:        61
-FD1P3IX:        1
-FD1S3AX:        21
-FD1S3AY:        4
-FD1S3IX:        6
-GSR:            1
-IB:             21
-IFS1P3DX:       1
-INV:            1
-OB:             40
-OFS1P3BX:       5
-OFS1P3DX:       21
-OFS1P3IX:       2
-ORCALUT4:       277
-PFUMX:          3
-PUR:            1
-VHI:            3
-VLO:            3
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 217MB)
-
-Process took 0h:00m:03s realtime, 0h:00m:03s cputime
-# Thu Dec 28 23:23:26 2023
-
-###########################################################]
-
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- - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html deleted file mode 100644 index 96c2755..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html +++ /dev/null @@ -1,289 +0,0 @@ - -Lattice Map TRACE Report - - -
Map TRACE Report
-
-Loading design for application trce from file ram2e_lcmxo2_1200hc_impl1_map.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Dec 28 23:23:29 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
-Design file:     ram2e_lcmxo2_1200hc_impl1_map.ncd
-Preference file: ram2e_lcmxo2_1200hc_impl1.prf
-Device,speed:    LCMXO2-1200HC,4
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1611 items scored, 0 timing errors detected.
-Report:   90.967MHz is the maximum frequency for this preference.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1611 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 58.937ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[2]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              10.827ns  (31.6% logic, 68.4% route), 7 logic levels.
-
- Constraint Details:
-
-     10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from C14M_c)
-ROUTE        50   e 1.234    SLICE_34.Q0 to    SLICE_35.A0 S[2]
-CTOF_DEL    ---     0.495    SLICE_35.A0 to    SLICE_35.F0 SLICE_35
-ROUTE         7   e 1.234    SLICE_35.F0 to *m/SLICE_80.D1 N_551
-CTOF_DEL    ---     0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
-ROUTE         8   e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
-ROUTE         5   e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
-CTOF_DEL    ---     0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
-ROUTE         1   e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
-CTOF_DEL    ---     0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
-ROUTE         1   e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
-ROUTE         1   e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   10.827   (31.6% logic, 68.4% route), 7 logic levels.
-
-Report:   90.967MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   90.967 MHz|   7  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 1 clocks:
-
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
-   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Dec 28 23:23:29 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
-Design file:     ram2e_lcmxo2_1200hc_impl1_map.ncd
-Preference file: ram2e_lcmxo2_1200hc_impl1.prf
-Device,speed:    LCMXO2-1200HC,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1611 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1611 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.447ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[0]  (from C14M_c +)
-   Destination:    FF         Data in        FS[0]  (to C14M_c +)
-
-   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.434ns physical path delay SLICE_0 to SLICE_0 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
-
- Physical Path Details:
-
-      Data path SLICE_0 to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    SLICE_0.CLK to     SLICE_0.Q1 SLICE_0 (from C14M_c)
-ROUTE         6   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
-CTOF_DEL    ---     0.101     SLICE_0.A1 to     SLICE_0.F1 SLICE_0
-ROUTE         1   e 0.001     SLICE_0.F1 to    SLICE_0.DI1 FS_s[0] (to C14M_c)
-                  --------
-                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   2  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 1 clocks:
-
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
-   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
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-
    - - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html deleted file mode 100644 index 6596462..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html +++ /dev/null @@ -1,1209 +0,0 @@ - -Lattice TRACE Report - - -
    Place & Route TRACE Report
-
-Loading design for application trce from file ram2e_lcmxo2_1200hc_impl1.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-1200HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.44.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Dec 28 23:23:45 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
-Design file:     ram2e_lcmxo2_1200hc_impl1.ncd
-Preference file: ram2e_lcmxo2_1200hc_impl1.prf
-Device,speed:    LCMXO2-1200HC,4
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1611 items scored, 0 timing errors detected.
-Report:   84.310MHz is the maximum frequency for this preference.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1611 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 58.069ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[2]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.695ns  (29.3% logic, 70.7% route), 7 logic levels.
-
- Constraint Details:
-
-     11.695ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.069ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
-ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
-CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
-ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
-CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
-ROUTE         5     1.755       R3C6C.F1 to       R2C7D.A0 ram2e_ufm/N_781
-CTOF_DEL    ---     0.495       R2C7D.A0 to       R2C7D.F0 ram2e_ufm/SLICE_99
-ROUTE         1     1.023       R2C7D.F0 to       R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0]
-CTOF_DEL    ---     0.495       R3C7A.B0 to       R3C7A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   11.695   (29.3% logic, 70.7% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.138ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[2]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.626ns  (29.4% logic, 70.6% route), 7 logic levels.
-
- Constraint Details:
-
-     11.626ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.138ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
-ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
-CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
-ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
-CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
-ROUTE         5     1.962       R3C6C.F1 to       R3C7C.C0 ram2e_ufm/N_781
-CTOF_DEL    ---     0.495       R3C7C.C0 to       R3C7C.F0 ram2e_ufm/SLICE_126
-ROUTE         1     0.747       R3C7C.F0 to       R3C7A.C0 ram2e_ufm/N_753
-CTOF_DEL    ---     0.495       R3C7A.C0 to       R3C7A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   11.626   (29.4% logic, 70.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.247ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[2]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_dati[7]  (to C14M_c +)
-
-   Delay:              11.517ns  (25.4% logic, 74.6% route), 6 logic levels.
-
- Constraint Details:
-
-     11.517ns physical path delay SLICE_34 to ram2e_ufm/SLICE_55 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.247ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
-ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
-CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
-ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
-CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.631      R5C10B.F1 to       R3C6A.A1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 ram2e_ufm/SLICE_81
-ROUTE         4     1.963       R3C6A.F1 to      R3C10A.C0 ram2e_ufm/N_856
-CTOF_DEL    ---     0.495      R3C10A.C0 to      R3C10A.F0 ram2e_ufm/SLICE_131
-ROUTE         1     1.535      R3C10A.F0 to       R3C6B.B1 ram2e_ufm/N_602
-CTOF_DEL    ---     0.495       R3C6B.B1 to       R3C6B.F1 ram2e_ufm/SLICE_55
-ROUTE         1     0.000       R3C6B.F1 to      R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c)
-                  --------
-                   11.517   (25.4% logic, 74.6% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to      R3C6B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.444ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[3]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.320ns  (30.2% logic, 69.8% route), 7 logic levels.
-
- Constraint Details:
-
-     11.320ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.444ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q1 SLICE_34 (from C14M_c)
-ROUTE        45     1.097      R5C13B.Q1 to      R5C11D.B0 S[3]
-CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_35
-ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
-CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
-ROUTE         5     1.755       R3C6C.F1 to       R2C7D.A0 ram2e_ufm/N_781
-CTOF_DEL    ---     0.495       R2C7D.A0 to       R2C7D.F0 ram2e_ufm/SLICE_99
-ROUTE         1     1.023       R2C7D.F0 to       R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0]
-CTOF_DEL    ---     0.495       R3C7A.B0 to       R3C7A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   11.320   (30.2% logic, 69.8% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.513ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[3]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.251ns  (30.4% logic, 69.6% route), 7 logic levels.
-
- Constraint Details:
-
-     11.251ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.513ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q1 SLICE_34 (from C14M_c)
-ROUTE        45     1.097      R5C13B.Q1 to      R5C11D.B0 S[3]
-CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_35
-ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
-CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
-ROUTE         5     1.962       R3C6C.F1 to       R3C7C.C0 ram2e_ufm/N_781
-CTOF_DEL    ---     0.495       R3C7C.C0 to       R3C7C.F0 ram2e_ufm/SLICE_126
-ROUTE         1     0.747       R3C7C.F0 to       R3C7A.C0 ram2e_ufm/N_753
-CTOF_DEL    ---     0.495       R3C7A.C0 to       R3C7A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   11.251   (30.4% logic, 69.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.525ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.239ns  (26.0% logic, 74.0% route), 6 logic levels.
-
- Constraint Details:
-
-     11.239ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.525ns
-
- Physical Path Details:
-
-      Data path SLICE_33 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C13D.CLK to      R5C13D.Q0 SLICE_33 (from C14M_c)
-ROUTE        37     2.500      R5C13D.Q0 to      R5C10B.C1 S[0]
-CTOF_DEL    ---     0.495      R5C10B.C1 to      R5C10B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
-ROUTE         5     1.755       R3C6C.F1 to       R2C7D.A0 ram2e_ufm/N_781
-CTOF_DEL    ---     0.495       R2C7D.A0 to       R2C7D.F0 ram2e_ufm/SLICE_99
-ROUTE         1     1.023       R2C7D.F0 to       R3C7A.B0 ram2e_ufm/wb_adr_7_i_i_1[0]
-CTOF_DEL    ---     0.495       R3C7A.B0 to       R3C7A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   11.239   (26.0% logic, 74.0% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to     R5C13D.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.594ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.170ns  (26.2% logic, 73.8% route), 6 logic levels.
-
- Constraint Details:
-
-     11.170ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.594ns
-
- Physical Path Details:
-
-      Data path SLICE_33 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C13D.CLK to      R5C13D.Q0 SLICE_33 (from C14M_c)
-ROUTE        37     2.500      R5C13D.Q0 to      R5C10B.C1 S[0]
-CTOF_DEL    ---     0.495      R5C10B.C1 to      R5C10B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.411      R5C10B.F1 to       R3C6C.C1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C6C.C1 to       R3C6C.F1 ram2e_ufm/SLICE_98
-ROUTE         5     1.962       R3C6C.F1 to       R3C7C.C0 ram2e_ufm/N_781
-CTOF_DEL    ---     0.495       R3C7C.C0 to       R3C7C.F0 ram2e_ufm/SLICE_126
-ROUTE         1     0.747       R3C7C.F0 to       R3C7A.C0 ram2e_ufm/N_753
-CTOF_DEL    ---     0.495       R3C7A.C0 to       R3C7A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   11.170   (26.2% logic, 73.8% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to     R5C13D.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.622ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[3]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_dati[7]  (to C14M_c +)
-
-   Delay:              11.142ns  (26.3% logic, 73.7% route), 6 logic levels.
-
- Constraint Details:
-
-     11.142ns physical path delay SLICE_34 to ram2e_ufm/SLICE_55 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.622ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q1 SLICE_34 (from C14M_c)
-ROUTE        45     1.097      R5C13B.Q1 to      R5C11D.B0 S[3]
-CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_35
-ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
-CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.631      R5C10B.F1 to       R3C6A.A1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 ram2e_ufm/SLICE_81
-ROUTE         4     1.963       R3C6A.F1 to      R3C10A.C0 ram2e_ufm/N_856
-CTOF_DEL    ---     0.495      R3C10A.C0 to      R3C10A.F0 ram2e_ufm/SLICE_131
-ROUTE         1     1.535      R3C10A.F0 to       R3C6B.B1 ram2e_ufm/N_602
-CTOF_DEL    ---     0.495       R3C6B.B1 to       R3C6B.F1 ram2e_ufm/SLICE_55
-ROUTE         1     0.000       R3C6B.F1 to      R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c)
-                  --------
-                   11.142   (26.3% logic, 73.7% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to      R3C6B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.703ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_dati[7]  (to C14M_c +)
-
-   Delay:              11.061ns  (22.0% logic, 78.0% route), 5 logic levels.
-
- Constraint Details:
-
-     11.061ns physical path delay SLICE_33 to ram2e_ufm/SLICE_55 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.703ns
-
- Physical Path Details:
-
-      Data path SLICE_33 to ram2e_ufm/SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C13D.CLK to      R5C13D.Q0 SLICE_33 (from C14M_c)
-ROUTE        37     2.500      R5C13D.Q0 to      R5C10B.C1 S[0]
-CTOF_DEL    ---     0.495      R5C10B.C1 to      R5C10B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.631      R5C10B.F1 to       R3C6A.A1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 ram2e_ufm/SLICE_81
-ROUTE         4     1.963       R3C6A.F1 to      R3C10A.C0 ram2e_ufm/N_856
-CTOF_DEL    ---     0.495      R3C10A.C0 to      R3C10A.F0 ram2e_ufm/SLICE_131
-ROUTE         1     1.535      R3C10A.F0 to       R3C6B.B1 ram2e_ufm/N_602
-CTOF_DEL    ---     0.495       R3C6B.B1 to       R3C6B.F1 ram2e_ufm/SLICE_55
-ROUTE         1     0.000       R3C6B.F1 to      R3C6B.DI1 ram2e_ufm/wb_dati_7[7] (to C14M_c)
-                  --------
-                   11.061   (22.0% logic, 78.0% route), 5 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to     R5C13D.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to      R3C6B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.866ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[2]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              10.898ns  (31.4% logic, 68.6% route), 7 logic levels.
-
- Constraint Details:
-
-     10.898ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.866ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R5C13B.CLK to      R5C13B.Q0 SLICE_34 (from C14M_c)
-ROUTE        50     1.472      R5C13B.Q0 to      R5C11D.A0 S[2]
-CTOF_DEL    ---     0.495      R5C11D.A0 to      R5C11D.F0 SLICE_35
-ROUTE         7     0.989      R5C11D.F0 to      R5C10B.A1 N_551
-CTOF_DEL    ---     0.495      R5C10B.A1 to      R5C10B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     3.058      R5C10B.F1 to       R3C5D.A1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C5D.A1 to       R3C5D.F1 ram2e_ufm/SLICE_89
-ROUTE         6     0.348       R3C5D.F1 to       R3C5C.D1 ram2e_ufm/N_783
-CTOF_DEL    ---     0.495       R3C5C.D1 to       R3C5C.F1 ram2e_ufm/SLICE_68
-ROUTE         1     0.986       R3C5C.F1 to       R3C7A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
-CTOF_DEL    ---     0.495       R3C7A.A0 to       R3C7A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     0.623       R3C7A.F0 to       R2C7A.D0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R2C7A.D0 to       R2C7A.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R2C7A.F0 to      R2C7A.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   10.898   (31.4% logic, 68.6% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to     R5C13B.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     4.865       62.PADDI to      R2C7A.CLK C14M_c
-                  --------
-                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   84.310MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   84.310 MHz|   7  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 1 clocks:
-
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
-   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Dec 28 23:23:45 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
-Design file:     ram2e_lcmxo2_1200hc_impl1.ncd
-Preference file: ram2e_lcmxo2_1200hc_impl1.prf
-Device,speed:    LCMXO2-1200HC,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1611 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1611 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.342ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              ram2e_ufm/wb_dati[6]  (from C14M_c +)
-   Destination:    EFB        Port           ram2e_ufm/ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
-
-   Delay:               0.305ns  (43.6% logic, 56.4% route), 1 logic levels.
-
- Constraint Details:
-
-      0.305ns physical path delay ram2e_ufm/SLICE_55 to ram2e_ufm/ufmefb/EFBInst_0 meets
-     -0.091ns WBDATI_HLD and
-      0.000ns delay constraint less
-     -0.054ns skew requirement (totaling -0.037ns) by 0.342ns
-
- Physical Path Details:
-
-      Data path ram2e_ufm/SLICE_55 to ram2e_ufm/ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R3C6B.CLK to       R3C6B.Q0 ram2e_ufm/SLICE_55 (from C14M_c)
-ROUTE         1     0.172       R3C6B.Q0 to    EFB.WBDATI6 ram2e_ufm/wb_dati[6] (to C14M_c)
-                  --------
-                    0.305   (43.6% logic, 56.4% route), 1 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to ram2e_ufm/SLICE_55:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to      R3C6B.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/ufmefb/EFBInst_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.722       62.PADDI to     EFB.WBCLKI C14M_c
-                  --------
-                    1.722   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[15]  (from C14M_c +)
-   Destination:    FF         Data in        FS[15]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_1 to SLICE_1 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R2C12A.CLK to      R2C12A.Q0 SLICE_1 (from C14M_c)
-ROUTE         9     0.132      R2C12A.Q0 to      R2C12A.A0 FS[15]
-CTOF_DEL    ---     0.101      R2C12A.A0 to      R2C12A.F0 SLICE_1
-ROUTE         1     0.000      R2C12A.F0 to     R2C12A.DI0 FS_s[15] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R2C12A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R2C12A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdTout[2]  (from C14M_c +)
-   Destination:    FF         Data in        CmdTout[2]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_18 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R8C11A.CLK to      R8C11A.Q1 SLICE_18 (from C14M_c)
-ROUTE         2     0.132      R8C11A.Q1 to      R8C11A.A1 CmdTout[2]
-CTOF_DEL    ---     0.101      R8C11A.A1 to      R8C11A.F1 SLICE_18
-ROUTE         1     0.000      R8C11A.F1 to     R8C11A.DI1 N_369_i (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdTout[1]  (from C14M_c +)
-   Destination:    FF         Data in        CmdTout[1]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_18 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R8C11A.CLK to      R8C11A.Q0 SLICE_18 (from C14M_c)
-ROUTE         3     0.132      R8C11A.Q0 to      R8C11A.A0 CmdTout[1]
-CTOF_DEL    ---     0.101      R8C11A.A0 to      R8C11A.F0 SLICE_18
-ROUTE         1     0.000      R8C11A.F0 to     R8C11A.DI0 N_368_i (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R8C11A.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from C14M_c +)
-   Destination:    FF         Data in        FS[13]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_2 to SLICE_2 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R2C11D.CLK to      R2C11D.Q0 SLICE_2 (from C14M_c)
-ROUTE        19     0.132      R2C11D.Q0 to      R2C11D.A0 FS[13]
-CTOF_DEL    ---     0.101      R2C11D.A0 to      R2C11D.F0 SLICE_2
-ROUTE         1     0.000      R2C11D.F0 to     R2C11D.DI0 FS_s[13] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R2C11D.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R2C11D.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA[9]  (from C14M_c +)
-   Destination:    FF         Data in        RA[9]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_24 to SLICE_24 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_24 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C11C.CLK to      R5C11C.Q1 SLICE_24 (from C14M_c)
-ROUTE         2     0.132      R5C11C.Q1 to      R5C11C.A1 RA[9]
-CTOF_DEL    ---     0.101      R5C11C.A1 to      R5C11C.F1 SLICE_24
-ROUTE         1     0.000      R5C11C.F1 to     R5C11C.DI1 RA_35[9] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA[8]  (from C14M_c +)
-   Destination:    FF         Data in        RA[8]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_24 to SLICE_24 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_24 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C11C.CLK to      R5C11C.Q0 SLICE_24 (from C14M_c)
-ROUTE         2     0.132      R5C11C.Q0 to      R5C11C.A0 RA[8]
-CTOF_DEL    ---     0.101      R5C11C.A0 to      R5C11C.F0 SLICE_24
-ROUTE         1     0.000      R5C11C.F0 to     R5C11C.DI0 un2_S_2_i_0_0_o3_RNIHFHN3 (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R5C11C.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA[11]  (from C14M_c +)
-   Destination:    FF         Data in        RA[11]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_25 to SLICE_25 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_25 to SLICE_25:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C12D.CLK to      R5C12D.Q1 SLICE_25 (from C14M_c)
-ROUTE         2     0.132      R5C12D.Q1 to      R5C12D.A1 RA[11]
-CTOF_DEL    ---     0.101      R5C12D.A1 to      R5C12D.F1 SLICE_25
-ROUTE         1     0.000      R5C12D.F1 to     R5C12D.DI1 RA_35[11] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_25:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R5C12D.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_25:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R5C12D.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RC[2]  (from C14M_c +)
-   Destination:    FF         Data in        RC[2]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_26 to SLICE_26 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_26 to SLICE_26:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R4C15C.CLK to      R4C15C.Q1 SLICE_26 (from C14M_c)
-ROUTE         5     0.132      R4C15C.Q1 to      R4C15C.A1 RC[2]
-CTOF_DEL    ---     0.101      R4C15C.A1 to      R4C15C.F1 SLICE_26
-ROUTE         1     0.000      R4C15C.F1 to     R4C15C.DI1 RC_3[2] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_26:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R4C15C.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_26:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R4C15C.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[12]  (from C14M_c +)
-   Destination:    FF         Data in        FS[12]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_3 to SLICE_3 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R2C11C.CLK to      R2C11C.Q1 SLICE_3 (from C14M_c)
-ROUTE        24     0.132      R2C11C.Q1 to      R2C11C.A1 FS[12]
-CTOF_DEL    ---     0.101      R2C11C.A1 to      R2C11C.F1 SLICE_3
-ROUTE         1     0.000      R2C11C.F1 to     R2C11C.DI1 FS_s[12] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R2C11C.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.668       62.PADDI to     R2C11C.CLK C14M_c
-                  --------
-                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   1  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 1 clocks:
-
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
-   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
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    - - diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf deleted file mode 100644 index e58d2ec..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf +++ /dev/null @@ -1,5985 +0,0 @@ -(DELAYFILE - (SDFVERSION "3.0") - (DESIGN "RAM2E") - (DATE "Thu Dec 28 23:23:53 2023") - (VENDOR "Lattice") - (PROGRAM "ldbanno") - (VERSION "Diamond (64-bit) 3.12.1.454") - (DIVIDER /) - (VOLTAGE 1.26:1.20:1.14) - (PROCESS "default") - (TEMPERATURE -40:25:85) - (TIMESCALE 1ps) - (CELL - (CELLTYPE "SLICE_0") - (INSTANCE SLICE_0) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 FCO (718:803:889)(718:803:889)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_1") - (INSTANCE SLICE_1) - (DELAY - (ABSOLUTE - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH FCI F0 (473:529:585)(473:529:585)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_2") - (INSTANCE SLICE_2) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 FCO (718:803:889)(718:803:889)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F1 (718:803:889)(718:803:889)) - (IOPATH A0 FCO (827:925:1023)(827:925:1023)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - (IOPATH FCI F0 (473:529:585)(473:529:585)) - (IOPATH FCI F1 (519:581:643)(519:581:643)) - (IOPATH FCI FCO (130:146:162)(130:146:162)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - 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(CELLTYPE "ram2e_ufm_SLICE_58") - (INSTANCE ram2e_ufm\/SLICE_58) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SUM0_i_m3_0_SLICE_59") - (INSTANCE ram2e_ufm\/SUM0_i_m3_0\/SLICE_59) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH B1 OFX0 (457:589:721)(457:589:721)) - (IOPATH D0 OFX0 (457:589:721)(457:589:721)) - (IOPATH C0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60") - (INSTANCE ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH B1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_CKE_7_SLICE_61") - (INSTANCE ram2e_ufm\/CKE_7\/SLICE_61) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH D0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_62") - (INSTANCE ram2e_ufm\/SLICE_62) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_63") - (INSTANCE ram2e_ufm\/SLICE_63) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_64") - (INSTANCE ram2e_ufm\/SLICE_64) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_65") - (INSTANCE ram2e_ufm\/SLICE_65) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_66") - (INSTANCE ram2e_ufm\/SLICE_66) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_67") - (INSTANCE ram2e_ufm\/SLICE_67) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_68") - (INSTANCE ram2e_ufm\/SLICE_68) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_69") - (INSTANCE ram2e_ufm\/SLICE_69) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_70") - (INSTANCE ram2e_ufm\/SLICE_70) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_71") - (INSTANCE ram2e_ufm\/SLICE_71) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_72") - (INSTANCE ram2e_ufm\/SLICE_72) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_73") - (INSTANCE ram2e_ufm\/SLICE_73) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_74") - (INSTANCE ram2e_ufm\/SLICE_74) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_75") - (INSTANCE ram2e_ufm\/SLICE_75) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_76") - (INSTANCE ram2e_ufm\/SLICE_76) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_77") - (INSTANCE ram2e_ufm\/SLICE_77) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_78") - (INSTANCE ram2e_ufm\/SLICE_78) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_79") - (INSTANCE ram2e_ufm\/SLICE_79) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_80") - (INSTANCE ram2e_ufm\/SLICE_80) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_81") - (INSTANCE ram2e_ufm\/SLICE_81) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_82") - (INSTANCE ram2e_ufm\/SLICE_82) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_83") - (INSTANCE ram2e_ufm\/SLICE_83) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_84") - (INSTANCE ram2e_ufm\/SLICE_84) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_85") - (INSTANCE ram2e_ufm\/SLICE_85) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_86") - (INSTANCE ram2e_ufm\/SLICE_86) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_87") - (INSTANCE ram2e_ufm\/SLICE_87) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_88") - (INSTANCE ram2e_ufm\/SLICE_88) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_89") - (INSTANCE ram2e_ufm\/SLICE_89) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_90") - (INSTANCE ram2e_ufm\/SLICE_90) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_91") - (INSTANCE ram2e_ufm\/SLICE_91) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_92") - (INSTANCE ram2e_ufm\/SLICE_92) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_93") - (INSTANCE ram2e_ufm\/SLICE_93) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_94") - (INSTANCE ram2e_ufm\/SLICE_94) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_95") - (INSTANCE ram2e_ufm\/SLICE_95) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_96") - (INSTANCE ram2e_ufm\/SLICE_96) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_97") - (INSTANCE ram2e_ufm\/SLICE_97) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_98") - (INSTANCE ram2e_ufm\/SLICE_98) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_99") - (INSTANCE ram2e_ufm\/SLICE_99) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_100") - (INSTANCE ram2e_ufm\/SLICE_100) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_101") - (INSTANCE ram2e_ufm\/SLICE_101) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_102") - (INSTANCE ram2e_ufm\/SLICE_102) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_103") - (INSTANCE ram2e_ufm\/SLICE_103) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_104") - (INSTANCE ram2e_ufm\/SLICE_104) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_105") - (INSTANCE ram2e_ufm\/SLICE_105) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_106") - (INSTANCE ram2e_ufm\/SLICE_106) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_107") - (INSTANCE ram2e_ufm\/SLICE_107) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_108") - (INSTANCE ram2e_ufm\/SLICE_108) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_109") - (INSTANCE ram2e_ufm\/SLICE_109) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_110") - (INSTANCE ram2e_ufm\/SLICE_110) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_111") - (INSTANCE ram2e_ufm\/SLICE_111) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_112") - (INSTANCE ram2e_ufm\/SLICE_112) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_113") - (INSTANCE ram2e_ufm\/SLICE_113) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_114") - (INSTANCE ram2e_ufm\/SLICE_114) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_115") - (INSTANCE ram2e_ufm\/SLICE_115) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_116") - (INSTANCE ram2e_ufm\/SLICE_116) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_117") - (INSTANCE ram2e_ufm\/SLICE_117) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_118") - (INSTANCE ram2e_ufm\/SLICE_118) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_119") - (INSTANCE ram2e_ufm\/SLICE_119) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_120") - (INSTANCE ram2e_ufm\/SLICE_120) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_121") - (INSTANCE ram2e_ufm\/SLICE_121) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_122") - (INSTANCE ram2e_ufm\/SLICE_122) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_123") - (INSTANCE ram2e_ufm\/SLICE_123) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_124") - (INSTANCE ram2e_ufm\/SLICE_124) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_125") - (INSTANCE ram2e_ufm\/SLICE_125) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_126") - (INSTANCE ram2e_ufm\/SLICE_126) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_127") - (INSTANCE ram2e_ufm\/SLICE_127) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_128") - (INSTANCE ram2e_ufm\/SLICE_128) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - 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(WIDTH (posedge Din0) (3330:3330:3330)) - (WIDTH (negedge Din0) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_7_") - (INSTANCE Ain\[7\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain7 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain7) (3330:3330:3330)) - (WIDTH (negedge Ain7) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_6_") - (INSTANCE Ain\[6\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain6 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain6) (3330:3330:3330)) - (WIDTH (negedge Ain6) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_5_") - (INSTANCE Ain\[5\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain5 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain5) (3330:3330:3330)) - (WIDTH (negedge Ain5) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_4_") - (INSTANCE Ain\[4\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain4 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain4) (3330:3330:3330)) - (WIDTH (negedge Ain4) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_3_") - (INSTANCE Ain\[3\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain3 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain3) (3330:3330:3330)) - (WIDTH (negedge Ain3) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_2_") - (INSTANCE Ain\[2\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain2 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain2) (3330:3330:3330)) - (WIDTH (negedge Ain2) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_1_") - (INSTANCE Ain\[1\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain1 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain1) (3330:3330:3330)) - (WIDTH (negedge Ain1) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_0_") - (INSTANCE Ain\[0\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain0 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain0) (3330:3330:3330)) - (WIDTH (negedge Ain0) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "nC07X") - (INSTANCE nC07X_I) - (DELAY - (ABSOLUTE - (IOPATH nC07X PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge nC07X) (3330:3330:3330)) - (WIDTH (negedge nC07X) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "nEN80") - (INSTANCE nEN80_I) - (DELAY - (ABSOLUTE - (IOPATH nEN80 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge nEN80) (3330:3330:3330)) - (WIDTH (negedge nEN80) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "nWE") - (INSTANCE nWE_I) - (DELAY - (ABSOLUTE - (IOPATH nWE PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge nWE) (3330:3330:3330)) - (WIDTH (negedge nWE) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "PHI1") - (INSTANCE PHI1_I) - (DELAY - (ABSOLUTE - (IOPATH PHI1 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge PHI1) (3330:3330:3330)) - (WIDTH (negedge PHI1) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "PHI1_MGIOL") - (INSTANCE PHI1_MGIOL) - (DELAY - (ABSOLUTE - (IOPATH CLK IN (577:577:577)(577:577:577)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1855:1855:1855)) - (WIDTH (negedge CLK) (1855:1855:1855)) - ) - ) - (CELL - (CELLTYPE "EFB_Buffer_Block") - (INSTANCE ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20) - (DELAY - (ABSOLUTE - (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278)) - (IOPATH WBCLKIin WBDATO1out (947:3204:5461)(947:3204:5461)) - (IOPATH WBCLKIin WBDATO2out (955:3211:5468)(955:3211:5468)) - (IOPATH WBCLKIin WBDATO3out (910:3173:5436)(910:3173:5436)) - (IOPATH WBCLKIin WBDATO4out (944:3217:5491)(944:3217:5491)) - (IOPATH WBCLKIin WBDATO5out (917:3672:6428)(917:3672:6428)) - (IOPATH WBCLKIin WBDATO6out (926:3191:5457)(926:3191:5457)) - (IOPATH WBCLKIin WBDATO7out (939:3201:5464)(939:3201:5464)) - (IOPATH WBCLKIin WBACKOout (903:1623:2343)(903:1623:2343)) - ) - ) - (TIMINGCHECK - (SETUPHOLD WBRSTIin (posedge WBCLKIin) (3138:3170:3203)(-3138:-1966:-794)) - (SETUPHOLD WBCYCIin (posedge WBCLKIin) (2616:2649:2682)(-2616:-1558:-501)) - (SETUPHOLD WBSTBIin (posedge WBCLKIin) (2605:2637:2670)(-2605:-1494:-384)) - (SETUPHOLD WBWEIin (posedge WBCLKIin) (1409:1442:1475)(-1409:-837:-266)) - (SETUPHOLD WBADRI0in (posedge WBCLKIin) (2058:2123:2188)(-2058:-1191:-324)) - (SETUPHOLD WBADRI1in (posedge WBCLKIin) (2068:2104:2140)(-2068:-1234:-401)) - (SETUPHOLD WBADRI2in (posedge WBCLKIin) (1928:1993:2058)(-1928:-1110:-292)) - (SETUPHOLD WBADRI3in (posedge WBCLKIin) (2167:2196:2226)(-2167:-1264:-361)) - (SETUPHOLD WBADRI4in (posedge WBCLKIin) (2072:2101:2130)(-2072:-1198:-324)) - (SETUPHOLD WBADRI5in (posedge WBCLKIin) (1611:1640:1670)(-1611:-950:-289)) - (SETUPHOLD WBADRI6in (posedge WBCLKIin) (2532:2564:2597)(-2532:-1380:-229)) - (SETUPHOLD WBADRI7in (posedge WBCLKIin) (2519:2551:2584)(-2519:-1377:-235)) - (SETUPHOLD WBDATI0in (posedge WBCLKIin) (1057:1262:1467)(-1037:-712:-388)) - (SETUPHOLD WBDATI1in (posedge WBCLKIin) (1114:1338:1563)(-1108:-785:-462)) - (SETUPHOLD WBDATI2in (posedge WBCLKIin) (916:1076:1237)(-912:-636:-360)) - (SETUPHOLD WBDATI3in (posedge WBCLKIin) (1145:1359:1573)(-1115:-782:-449)) - (SETUPHOLD WBDATI4in (posedge WBCLKIin) (1192:1400:1609)(-1176:-820:-464)) - (SETUPHOLD WBDATI5in (posedge WBCLKIin) (1027:1222:1418)(-1000:-706:-413)) - (SETUPHOLD WBDATI6in (posedge WBCLKIin) (1034:1248:1463)(-1034:-756:-479)) - (SETUPHOLD WBDATI7in (posedge WBCLKIin) (528:614:701)(-528:-398:-268)) - ) - (TIMINGCHECK - (WIDTH (posedge WBCLKIin) (4887:4887:4887)) - (WIDTH (negedge WBCLKIin) (4887:4887:4887)) - ) - ) - (CELL - (CELLTYPE "RAM2E") - (INSTANCE ) - (DELAY - (ABSOLUTE - (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_51/A1 (1337:1526:1716)(1337:1526:1716)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_69/D1 (1534:1686:1839)(1534:1686:1839)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_105/D0 (1534:1686:1839)(1534:1686:1839)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_108/B0 (783:913:1043)(783:913:1043)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_146/C0 (552:669:786)(552:669:786)) - (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_0/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_1/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_2/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_2/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_3/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_3/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_4/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_4/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_5/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_5/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_6/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_6/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_7/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_7/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_9/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_11/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_13/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_14/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_15/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_16/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_17/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_23/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_23/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_24/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_24/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_25/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_25/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_26/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_26/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_27/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_27/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_28/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_28/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_29/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_29/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_30/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_30/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_31/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_32/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_33/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_33/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (4198:4531:4865)(4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_39/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_40/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_41/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_42/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_43/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_43/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_44/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_44/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_45/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_45/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_46/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_46/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_47/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_47/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_48/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_48/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_49/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_49/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_50/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_50/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_51/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_52/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_52/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_53/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_53/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_54/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_54/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_55/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_55/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_56/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_57/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_58/CLK (4198:4531:4865) - (4198:4531:4865)) - (INTERCONNECT C14M_I/PADDI DQMH_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI DQML_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[11\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[10\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[9\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[8\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[7\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[6\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[5\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[4\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[3\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[2\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI RAout\[0\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI BA\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI BA\[0\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI nRWEout_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI nCASout_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI nRASout_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI CKEout_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI Vout\[7\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI Vout\[6\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI Vout\[5\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI Vout\[4\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI Vout\[3\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI Vout\[2\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI Vout\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI Vout\[0\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI PHI1_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT C14M_I/PADDI - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin - (4345:4691:5038)(4345:4691:5038)) - (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_1/Q0 SLICE_9/C1 (998:1155:1313)(998:1155:1313)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/A1 (1562:1761:1961)(1562:1761:1961)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/A0 (1562:1761:1961)(1562:1761:1961)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_69/C1 (993:1150:1307)(993:1150:1307)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_80/B1 (1224:1394:1564)(1224:1394:1564)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_105/A0 (1192:1359:1527)(1192:1359:1527)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/C1 (998:1155:1313)(998:1155:1313)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/C0 (998:1155:1313)(998:1155:1313)) - (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_2/Q1 SLICE_23/B1 (777:906:1036)(777:906:1036)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/C1 (821:966:1111)(821:966:1111)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/C0 (821:966:1111)(821:966:1111)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_50/D0 (1190:1313:1436)(1190:1313:1436)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_51/C1 (1196:1373:1551)(1196:1373:1551)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_56/A1 (2097:2352:2608)(2097:2352:2608)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/C1 (1571:1781:1991)(1571:1781:1991)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/C0 (1571:1781:1991)(1571:1781:1991)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_66/D1 (1185:1307:1430)(1185:1307:1430)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_70/C1 (1565:1774:1984)(1565:1774:1984)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_81/D1 (1903:2095:2288)(1903:2095:2288)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_85/B1 (1759:1985:2211)(1759:1985:2211)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_89/C1 (1940:2182:2424)(1940:2182:2424)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_98/D1 (1903:2095:2288)(1903:2095:2288)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_109/C1 (1576:1786:1997)(1576:1786:1997)) - (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_2/Q0 SLICE_23/B0 (786:914:1043)(786:914:1043)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_56/D0 (914:1006:1099)(914:1006:1099)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_58/A0 (1884:2108:2332)(1884:2108:2332)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_64/B0 (2607:2900:3193)(2607:2900:3193)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_70/B0 (1911:2137:2363)(1911:2137:2363)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_75/D0 (1294:1419:1545)(1294:1419:1545)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_76/B0 (1911:2137:2363)(1911:2137:2363)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_81/A0 (2586:2877:3169)(2586:2877:3169)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_85/D1 (1294:1419:1545)(1294:1419:1545)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_89/D1 (2049:2240:2431)(2049:2240:2431)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_97/C1 (2430:2708:2986)(2430:2708:2986)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_103/D1 (1674:1832:1991)(1674:1832:1991)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_111/D0 (1996:2189:2382)(1996:2189:2382)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_125/D1 (2794:3049:3305)(2794:3049:3305)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_128/D1 (2794:3049:3305)(2794:3049:3305)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_128/D0 (2794:3049:3305)(2794:3049:3305)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_131/D1 (914:1006:1099)(914:1006:1099)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_131/D0 (914:1006:1099)(914:1006:1099)) - (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_56/C0 (1305:1485:1666)(1305:1485:1666)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_58/A1 (1524:1717:1910)(1524:1717:1910)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_68/C0 (1695:1909:2124)(1695:1909:2124)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_70/A0 (2269:2526:2784)(2269:2526:2784)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_75/A0 (1894:2119:2344)(1894:2119:2344)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_76/D0 (2397:2626:2855)(2397:2626:2855)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_81/C0 (1695:1909:2124)(1695:1909:2124)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_85/C1 (1996:2243:2490)(1996:2243:2490)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_90/A1 (1904:2130:2356)(1904:2130:2356)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_93/A0 (1904:2130:2356)(1904:2130:2356)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_97/B1 (2300:2560:2820)(2300:2560:2820)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_99/B0 (1931:2159:2387)(1931:2159:2387)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_103/C1 (1700:1915:2130)(1700:1915:2130)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_104/A0 (2269:2526:2784)(2269:2526:2784)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_111/D1 (2397:2626:2855)(2397:2626:2855)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_114/B0 (2258:2521:2784)(2258:2521:2784)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_124/D1 (539:599:659)(539:599:659)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_126/C1 (1299:1479:1659)(1299:1479:1659)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_126/A0 (1524:1717:1910)(1524:1717:1910)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_128/B1 (2997:3324:3651)(2997:3324:3651)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_128/C0 (2075:2322:2570)(2075:2322:2570)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_131/C1 (1262:1445:1629)(1262:1445:1629)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_131/A0 (1134:1293:1452)(1134:1293:1452)) - (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_3/Q0 SLICE_22/C0 (811:959:1107)(811:959:1107)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_56/A0 (1374:1564:1754)(1374:1564:1754)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_64/C1 (1597:1821:2046)(1597:1821:2046)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_64/D0 (1259:1393:1528)(1259:1393:1528)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_68/A0 (1844:2076:2309)(1844:2076:2309)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_73/A0 (1448:1646:1844)(1448:1646:1844)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_75/A1 (1844:2076:2309)(1844:2076:2309)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_76/C1 (1275:1465:1655)(1275:1465:1655)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_88/B1 (1506:1709:1912)(1506:1709:1912)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_90/B1 (1506:1709:1912)(1506:1709:1912)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_93/A1 (1844:2076:2309)(1844:2076:2309)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_99/D1 (1259:1393:1528)(1259:1393:1528)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_104/A1 (1838:2070:2302)(1838:2070:2302)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_109/C0 (1634:1855:2076)(1634:1855:2076)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_110/A1 (1844:2076:2309)(1844:2076:2309)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_114/D0 (1259:1393:1528)(1259:1393:1528)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_123/D1 (1623:1789:1955)(1623:1789:1955)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_123/D0 (1623:1789:1955)(1623:1789:1955)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_125/B1 (1865:2099:2333)(1865:2099:2333)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_125/B0 (1865:2099:2333)(1865:2099:2333)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_128/C1 (1634:1855:2076)(1634:1855:2076)) - (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_4/Q1 SLICE_21/B1 (777:906:1036)(777:906:1036)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_47/A0 (1458:1654:1851)(1458:1654:1851)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_68/D0 (1670:1830:1990)(1670:1830:1990)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_73/D0 (1290:1417:1544)(1290:1417:1544)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_75/D1 (2050:2243:2436)(2050:2243:2436)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_76/D1 (2050:2243:2436)(2050:2243:2436)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_88/D1 (2050:2243:2436)(2050:2243:2436)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_90/C1 (1671:1885:2099)(1671:1885:2099)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_93/B1 (1912:2140:2368)(1912:2140:2368)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_99/A1 (1458:1654:1851)(1458:1654:1851)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_104/C1 (1681:1896:2111)(1681:1896:2111)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_110/B1 (2656:2948:3241)(2656:2948:3241)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_114/D1 (910:1004:1098)(910:1004:1098)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_123/A0 (1848:2079:2311)(1848:2079:2311)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_126/D1 (2030:2221:2412)(2030:2221:2412)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_126/D0 (2030:2221:2412)(2030:2221:2412)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_128/A1 (1848:2079:2311)(1848:2079:2311)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_128/A0 (1848:2079:2311)(1848:2079:2311)) - (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_64/A1 (1006:1166:1326)(1006:1166:1326)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_68/B1 (1231:1403:1576)(1231:1403:1576)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_73/C0 (1369:1560:1752)(1369:1560:1752)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_75/B1 (1606:1811:2016)(1606:1811:2016)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_81/C1 (1739:1962:2186)(1739:1962:2186)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_93/C1 (1369:1560:1752)(1369:1560:1752)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_104/B1 (1558:1765:1973)(1558:1765:1973)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_110/D1 (1728:1896:2065)(1728:1896:2065)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_111/A0 (1901:2138:2376)(1901:2138:2376)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_114/B1 (1241:1414:1588)(1241:1414:1588)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_123/B1 (1241:1414:1588)(1241:1414:1588)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_123/B0 (1241:1414:1588)(1241:1414:1588)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_125/A1 (1536:1742:1948)(1536:1742:1948)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_125/D0 (1326:1466:1607)(1326:1466:1607)) - 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(INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_74/C0 (929:1091:1254)(929:1091:1254)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_77/A0 (2655:2960:3266)(2655:2960:3266)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_78/D1 (1967:2173:2379)(1967:2173:2379)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_80/C1 (1978:2239:2500)(1978:2239:2500)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_92/D0 (817:923:1029)(817:923:1029)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_95/B1 (1429:1635:1841)(1429:1635:1841)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_96/B1 (1429:1635:1841)(1429:1635:1841)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_106/C1 (540:656:772)(540:656:772)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_107/B1 (2188:2460:2732)(2188:2460:2732)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_112/B1 (1444:1651:1859)(1444:1651:1859)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_113/B0 (1444:1651:1859)(1444:1651:1859)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_115/D0 (534:598:662)(534:598:662)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_117/C1 (874:1044:1214)(874:1044:1214)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_117/C0 (874:1044:1214)(874:1044:1214)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_118/B1 (1105:1288:1471)(1105:1288:1471)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_118/B0 (1105:1288:1471)(1105:1288:1471)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_119/D1 (570:638:707)(570:638:707)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_119/D0 (570:638:707)(570:638:707)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_120/D1 (545:611:677)(545:611:677)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_120/D0 (545:611:677)(545:611:677)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_121/A1 (2177:2448:2720)(2177:2448:2720)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_121/A0 (2177:2448:2720)(2177:2448:2720)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_127/D1 (570:638:707)(570:638:707)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_127/D0 (570:638:707)(570:638:707)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_129/C1 (929:1091:1254)(929:1091:1254)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_129/C0 (929:1091:1254)(929:1091:1254)) - (INTERCONNECT SLICE_33/Q0 SLICE_138/A1 (3352:3724:4097)(3352:3724:4097)) - (INTERCONNECT SLICE_33/Q0 SLICE_138/B0 (3057:3397:3737)(3057:3397:3737)) - (INTERCONNECT SLICE_35/F0 SLICE_9/A1 (1019:1185:1351)(1019:1185:1351)) - (INTERCONNECT SLICE_35/F0 SLICE_9/A0 (1019:1185:1351)(1019:1185:1351)) - (INTERCONNECT SLICE_35/F0 SLICE_35/C1 (284:372:461)(284:372:461)) - (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (7:16:25)(7:16:25)) - (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_80/A1 (740:864:989)(740:864:989)) - (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_92/A1 (1383:1580:1778)(1383:1580:1778)) - (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_129/D0 (532:597:662)(532:597:662)) - (INTERCONNECT ram2e_ufm\/CKE_7\/SLICE_61/OFX0 SLICE_9/B0 (1099:1259:1420) - (1099:1259:1420)) - (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_9/Q0 CKEout_MGIOL/OPOS (2313:2510:2707)(2313:2510:2707)) - (INTERCONNECT SLICE_9/F1 ram2e_ufm\/SLICE_56/CE (1277:1401:1526)(1277:1401:1526)) - (INTERCONNECT SLICE_31/Q0 SLICE_10/B0 (1252:1425:1598)(1252:1425:1598)) - (INTERCONNECT SLICE_31/Q0 SLICE_18/D1 (1010:1115:1220)(1010:1115:1220)) - (INTERCONNECT SLICE_31/Q0 SLICE_18/D0 (1010:1115:1220)(1010:1115:1220)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/M0 - (975:1068:1162)(975:1068:1162)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_77/B1 (1237:1408:1580)(1237:1408:1580)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_79/C0 (805:952:1100)(805:952:1100)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_80/B0 (1467:1663:1859)(1467:1663:1859)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_83/B0 (1616:1820:2025)(1616:1820:2025)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_130/C1 (1006:1164:1323)(1006:1164:1323)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_130/C0 (1006:1164:1323)(1006:1164:1323)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_133/B1 (1601:1804:2007)(1601:1804:2007)) - (INTERCONNECT SLICE_10/Q0 SLICE_10/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_10/Q0 SLICE_18/C1 (547:661:775)(547:661:775)) - (INTERCONNECT SLICE_10/Q0 SLICE_18/B0 (767:892:1017)(767:892:1017)) - (INTERCONNECT SLICE_10/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/C0 - (547:661:775)(547:661:775)) - (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_10/CE (1258:1384:1510)(1258:1384:1510)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_18/CE (1258:1384:1510)(1258:1384:1510)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_18/CE (1258:1384:1510)(1258:1384:1510)) - (INTERCONNECT SLICE_10/F1 nCSout_I/PADDO (1536:1697:1858)(1536:1697:1858)) - (INTERCONNECT SLICE_26/Q1 SLICE_11/D1 (554:615:676)(554:615:676)) - (INTERCONNECT SLICE_26/Q1 SLICE_11/D0 (554:615:676)(554:615:676)) - (INTERCONNECT SLICE_26/Q1 SLICE_26/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_26/Q1 SLICE_26/D0 (554:615:676)(554:615:676)) - (INTERCONNECT SLICE_26/Q1 ram2e_ufm\/SLICE_91/D1 (554:615:676)(554:615:676)) - (INTERCONNECT SLICE_11/Q0 SLICE_11/A1 (748:874:1001)(748:874:1001)) - (INTERCONNECT SLICE_11/Q0 SLICE_11/A0 (483:579:675)(483:579:675)) - (INTERCONNECT SLICE_11/Q0 SLICE_26/D1 (527:586:645)(527:586:645)) - (INTERCONNECT SLICE_11/Q0 SLICE_26/A0 (748:874:1001)(748:874:1001)) - (INTERCONNECT SLICE_11/Q0 ram2e_ufm\/SLICE_91/B1 (769:896:1023)(769:896:1023)) - (INTERCONNECT SLICE_26/Q0 SLICE_11/B0 (788:917:1046)(788:917:1046)) - (INTERCONNECT SLICE_26/Q0 SLICE_26/B1 (788:917:1046)(788:917:1046)) - (INTERCONNECT SLICE_26/Q0 SLICE_26/B0 (788:917:1046)(788:917:1046)) - (INTERCONNECT SLICE_26/Q0 ram2e_ufm\/CKE_7\/SLICE_61/A1 (745:872:999)(745:872:999)) - (INTERCONNECT SLICE_26/Q0 ram2e_ufm\/SLICE_91/C1 (536:648:760)(536:648:760)) - (INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_11/CE (1002:1104:1207)(1002:1104:1207)) - (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_26/CE (1002:1104:1207)(1002:1104:1207)) - (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_26/CE (1002:1104:1207)(1002:1104:1207)) - (INTERCONNECT SLICE_11/F1 ram2e_ufm\/CKE_7\/SLICE_61/D1 (523:573:623)(523:573:623)) - (INTERCONNECT SLICE_13/F1 SLICE_12/D1 (520:573:626)(520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_62/F1 SLICE_12/C1 (534:645:756)(534:645:756)) - (INTERCONNECT ram2e_ufm\/SLICE_62/F1 ram2e_ufm\/SLICE_62/C0 (280:362:445) - (280:362:445)) - (INTERCONNECT ram2e_ufm\/SLICE_84/F1 SLICE_12/B1 (513:611:710)(513:611:710)) - (INTERCONNECT ram2e_ufm\/SLICE_84/F1 ram2e_ufm\/SLICE_84/B0 (767:894:1021) - (767:894:1021)) - (INTERCONNECT ram2e_ufm\/SLICE_84/F1 ram2e_ufm\/SLICE_87/D0 (535:598:662) - (535:598:662)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_12/A1 (1081:1244:1407)(1081:1244:1407)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_12/B0 (770:897:1024)(770:897:1024)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_13/A1 (1081:1244:1407)(1081:1244:1407)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_13/D0 (528:587:646)(528:587:646)) - (INTERCONNECT SLICE_12/Q1 SLICE_12/D0 (576:643:710)(576:643:710)) - (INTERCONNECT SLICE_12/Q1 SLICE_13/C1 (587:709:831)(587:709:831)) - (INTERCONNECT SLICE_12/Q1 SLICE_13/C0 (587:709:831)(587:709:831)) - (INTERCONNECT SLICE_12/Q1 SLICE_19/C1 (552:669:786)(552:669:786)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_40/C1 (552:669:786)(552:669:786)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/C1 (542:663:784) - (542:663:784)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_62/A1 (786:918:1051)(786:918:1051)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_62/A0 (786:918:1051)(786:918:1051)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_65/A0 (1013:1179:1346)(1013:1179:1346)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_84/A0 (741:872:1004)(741:872:1004)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_87/B0 (818:953:1088)(818:953:1088)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_101/C0 (814:970:1126)(814:970:1126)) - (INTERCONNECT ram2e_ufm\/SLICE_63/F0 SLICE_12/C0 (534:639:744)(534:639:744)) - (INTERCONNECT SLICE_13/Q0 SLICE_12/A0 (770:902:1035)(770:902:1035)) - (INTERCONNECT SLICE_13/Q0 SLICE_13/D1 (560:627:694)(560:627:694)) - (INTERCONNECT SLICE_13/Q0 SLICE_13/A0 (485:583:681)(485:583:681)) - (INTERCONNECT SLICE_13/Q0 SLICE_15/B1 (1043:1215:1388)(1043:1215:1388)) - (INTERCONNECT SLICE_13/Q0 SLICE_19/B1 (787:921:1055)(787:921:1055)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_40/B1 (787:921:1055)(787:921:1055)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_62/B1 (802:937:1072)(802:937:1072)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_62/B0 (802:937:1072)(802:937:1072)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_63/D1 (535:605:675)(535:605:675)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_83/B1 (792:926:1061)(792:926:1061)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_84/D1 (535:605:675)(535:605:675)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_94/A0 (760:892:1024)(760:892:1024)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_100/C0 (561:682:804)(561:682:804)) - (INTERCONNECT SLICE_12/F1 SLICE_12/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_12/LSR (933:1041:1149)(933:1041:1149)) - (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_12/LSR (933:1041:1149)(933:1041:1149)) - (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_13/LSR (933:1041:1149)(933:1041:1149)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_40/A1 (1089:1253:1418)(1089:1253:1418)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/B1 - (1153:1315:1477)(1153:1315:1477)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_63/A1 (1078:1240:1403)(1078:1240:1403)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_63/D0 (868:965:1062)(868:965:1062)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_65/B1 (2225:2487:2750)(2225:2487:2750)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_65/B0 (2225:2487:2750)(2225:2487:2750)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_77/A1 (1089:1253:1418)(1089:1253:1418)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_82/B1 (1850:2079:2308)(1850:2079:2308)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_83/A0 (745:872:999)(745:872:999)) - (INTERCONNECT ram2e_ufm\/SLICE_87/F1 SLICE_13/B1 (769:899:1029)(769:899:1029)) - (INTERCONNECT ram2e_ufm\/SLICE_87/F1 SLICE_13/B0 (515:616:718)(515:616:718)) - (INTERCONNECT ram2e_ufm\/SLICE_87/F1 ram2e_ufm\/SLICE_62/D0 (527:589:651) - (527:589:651)) - (INTERCONNECT ram2e_ufm\/SLICE_87/F1 ram2e_ufm\/SLICE_87/C0 (284:372:461) - (284:372:461)) - (INTERCONNECT SLICE_13/F0 SLICE_13/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_14/D1 (2505:2694:2883)(2505:2694:2883)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_16/B1 (3122:3411:3701)(3122:3411:3701)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_28/B1 (3210:3494:3779)(3210:3494:3779)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_39/C1 (3432:3753:4074) - (3432:3753:4074)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_44/A1 (3505:3822:4139) - (3505:3822:4139)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_48/B1 (3938:4285:4633) - (3938:4285:4633)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/B1 - (2286:2514:2742)(2286:2514:2742)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/B0 - (2286:2514:2742)(2286:2514:2742)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_100/B1 (3122:3411:3701) - (3122:3411:3701)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_101/B1 (3122:3411:3701) - (3122:3411:3701)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_116/D1 (3421:3687:3953) - (3421:3687:3953)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_141/A0 (3042:3331:3621) - (3042:3331:3621)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_14/C1 (2207:2423:2640)(2207:2423:2640)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_16/C1 (2587:2836:3086)(2587:2836:3086)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_29/B1 (2278:2507:2737)(2278:2507:2737)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_39/B1 (2438:2667:2897) - (2438:2667:2897)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_45/B1 (2315:2541:2767) - (2315:2541:2767)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_49/B1 (2309:2534:2760) - (2309:2534:2760)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/D1 - (3381:3644:3908)(3381:3644:3908)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/C0 - (3065:3348:3632)(3065:3348:3632)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_100/C1 (2587:2836:3086) - (2587:2836:3086)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_101/C1 (2587:2836:3086) - (2587:2836:3086)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_116/C1 (2207:2423:2640) - (2207:2423:2640)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_147/B0 (2438:2667:2897) - (2438:2667:2897)) - (INTERCONNECT ram2e_ufm\/SLICE_40/F1 SLICE_14/A1 (751:880:1010)(751:880:1010)) - (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_39/B0 (513:611:710) - (513:611:710)) - (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_40/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_41/C0 (552:671:790) - (552:671:790)) - (INTERCONNECT ram2e_ufm\/SLICE_142/F1 SLICE_14/D0 (523:573:623)(523:573:623)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_14/C0 (1743:1927:2111)(1743:1927:2111)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_15/A1 (3034:3332:3630)(3034:3332:3630)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_15/A0 (3034:3332:3630)(3034:3332:3630)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_16/A1 (2686:2945:3204)(2686:2945:3204)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_16/A0 (2686:2945:3204)(2686:2945:3204)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_17/D0 (1732:1861:1990)(1732:1861:1990)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_27/C1 (2191:2410:2629)(2191:2410:2629)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_39/A0 (4310:4724:5139) - (4310:4724:5139)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_41/D1 (3622:3937:4252) - (3622:3937:4252)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_43/C1 (2555:2805:3056) - (2555:2805:3056)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_47/C1 (1705:1883:2061) - (1705:1883:2061)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/M0 - (2441:2623:2805)(2441:2623:2805)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_87/C1 (1727:1909:2092) - (1727:1909:2092)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_100/D1 (3350:3630:3910) - (3350:3630:3910)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_116/B0 (4342:4759:5176) - (4342:4759:5176)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_143/C1 (2107:2322:2538) - (2107:2322:2538)) - (INTERCONNECT SLICE_14/F1 SLICE_14/B0 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_14/F1 SLICE_17/B1 (765:889:1013)(765:889:1013)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_14/A0 (2322:2538:2754)(2322:2538:2754)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_17/D1 (2439:2624:2810)(2439:2624:2810)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_28/B0 (1872:2056:2240)(1872:2056:2240)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_39/D0 (2112:2262:2413) - (2112:2262:2413)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_41/C1 (2123:2328:2534) - (2123:2328:2534)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_42/C1 (2016:2219:2423) - (2016:2219:2423)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_44/A0 (2579:2824:3070) - (2579:2824:3070)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_48/A0 (2943:3220:3497) - (2943:3220:3497)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_100/A1 (2692:2940:3188) - (2692:2940:3188)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_116/A0 (2322:2538:2754) - (2322:2538:2754)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_133/C1 (2971:3242:3514) - (2971:3242:3514)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_133/C0 (2971:3242:3514) - (2971:3242:3514)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_144/C1 (2814:3086:3358) - (2814:3086:3358)) - (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_14/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_15/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_16/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_17/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_27/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_27/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_28/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_28/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_29/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_29/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_30/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_30/CE (2023:2253:2484)(2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_39/CE (2023:2253:2484) - (2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_40/CE (2023:2253:2484) - (2023:2253:2484)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_41/CE (2023:2253:2484) - (2023:2253:2484)) - (INTERCONNECT SLICE_14/Q0 ram2e_ufm\/SLICE_147/B1 (762:883:1004)(762:883:1004)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_15/D1 (2882:3133:3384)(2882:3133:3384)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_15/B0 (2786:3068:3350)(2786:3068:3350)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_16/D1 (2882:3133:3384)(2882:3133:3384)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_16/B0 (2786:3068:3350)(2786:3068:3350)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_17/B0 (2776:3057:3338)(2776:3057:3338)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_30/A1 (2655:2908:3162)(2655:2908:3162)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_41/A0 (3502:3821:4141) - (3502:3821:4141)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_46/A1 (3019:3304:3589) - (3019:3304:3589)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_50/A1 (2644:2896:3149) - (2644:2896:3149)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/D0 - (3016:3263:3511)(3016:3263:3511)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_94/B1 (3170:3460:3751) - (3170:3460:3751)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_100/D0 (2928:3150:3373) - (2928:3150:3373)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_142/C1 (2915:3215:3515) - (2915:3215:3515)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_143/B0 (3510:3854:4199) - (3510:3854:4199)) - (INTERCONNECT SLICE_17/F1 SLICE_15/D0 (539:600:661)(539:600:661)) - (INTERCONNECT SLICE_17/F1 SLICE_16/D0 (539:600:661)(539:600:661)) - (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (280:362:445)(280:362:445)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_15/C0 (2089:2307:2526)(2089:2307:2526)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_16/C0 (2089:2307:2526)(2089:2307:2526)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_17/A0 (2663:2924:3186)(2663:2924:3186)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_29/C0 (2069:2285:2502)(2069:2285:2502)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_41/A1 (2663:2924:3186) - (2663:2924:3186)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_45/A0 (2595:2857:3119) - (2595:2857:3119)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_49/B0 (1821:2020:2220) - (1821:2020:2220)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_84/A1 (3104:3404:3704) - (3104:3404:3704)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_94/C1 (2089:2307:2526) - (2089:2307:2526)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_100/A0 (2615:2879:3143) - (2615:2879:3143)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_133/A1 (2766:3029:3292) - (2766:3029:3292)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_133/B0 (3136:3438:3741) - (3136:3438:3741)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_142/D1 (2823:3051:3279) - (2823:3051:3279)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_142/D0 (2823:3051:3279) - (2823:3051:3279)) - (INTERCONNECT SLICE_15/F0 SLICE_15/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_15/Q0 ram2e_ufm\/SLICE_79/D1 (1233:1354:1476)(1233:1354:1476)) - (INTERCONNECT SLICE_15/F1 ram2e_ufm\/SLICE_101/D0 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 ram2e_ufm\/SLICE_85/A0 (1443:1630:1817)(1443:1630:1817)) - (INTERCONNECT SLICE_16/F1 ram2e_ufm\/SLICE_84/B1 (768:889:1010)(768:889:1010)) - (INTERCONNECT SLICE_16/F1 ram2e_ufm\/SLICE_101/B0 (511:606:702)(511:606:702)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_17/C1 (2376:2622:2868)(2376:2622:2868)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_27/C0 (2355:2599:2843)(2355:2599:2843)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_39/D1 (1985:2143:2301) - (1985:2143:2301)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_41/B1 (2934:3228:3522) - (2934:3228:3522)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_42/A1 (2929:3216:3503) - (2929:3216:3503)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_42/A0 (2929:3216:3503) - (2929:3216:3503)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_43/A0 (2929:3216:3503) - (2929:3216:3503)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_65/C1 (2355:2599:2843) - (2355:2599:2843)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_86/D1 (1957:2111:2265) - (1957:2111:2265)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_94/B0 (2330:2553:2776) - (2330:2553:2776)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_116/D0 (1985:2143:2301) - (1985:2143:2301)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_133/D1 (1980:2137:2295) - (1980:2137:2295)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_141/B1 (2607:2866:3125) - (2607:2866:3125)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_142/A1 (2575:2831:3088) - (2575:2831:3088)) - (INTERCONNECT SLICE_17/F0 SLICE_17/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_17/Q0 ram2e_ufm\/SLICE_147/D1 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_18/Q0 SLICE_18/B1 (776:901:1026)(776:901:1026)) - (INTERCONNECT SLICE_18/Q0 SLICE_18/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_18/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/A0 - (744:866:989)(744:866:989)) - (INTERCONNECT SLICE_18/Q1 SLICE_18/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_18/Q1 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/B0 - (765:888:1011)(765:888:1011)) - (INTERCONNECT SLICE_18/F1 SLICE_18/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_20/Q1 SLICE_19/B0 (1224:1391:1559)(1224:1391:1559)) - (INTERCONNECT SLICE_20/Q1 RAout\[1\]_MGIOL/OPOS (2318:2516:2715)(2318:2516:2715)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 SLICE_19/A0 (1562:1763:1965)(1562:1763:1965)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 SLICE_31/A1 (2409:2676:2944)(2409:2676:2944)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_95/A0 (756:884:1013) - (756:884:1013)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_96/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_132/B1 (2441:2711:2981) - (2441:2711:2981)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_132/B0 (2441:2711:2981) - (2441:2711:2981)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_140/A1 (756:884:1013) - (756:884:1013)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_140/A0 (756:884:1013) - (756:884:1013)) - (INTERCONNECT SLICE_34/Q1 SLICE_19/M0 (1263:1395:1527)(1263:1395:1527)) - (INTERCONNECT SLICE_34/Q1 SLICE_34/A1 (485:583:681)(485:583:681)) - (INTERCONNECT SLICE_34/Q1 SLICE_34/D0 (550:615:680)(550:615:680)) - (INTERCONNECT SLICE_34/Q1 SLICE_35/B0 (822:959:1097)(822:959:1097)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_42/D0 (1344:1480:1616)(1344:1480:1616)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_43/D1 (1344:1480:1616)(1344:1480:1616)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_43/D0 (1344:1480:1616)(1344:1480:1616)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_44/D1 (1724:1893:2062)(1724:1893:2062)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_44/D0 (1724:1893:2062)(1724:1893:2062)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_45/D1 (1344:1480:1616)(1344:1480:1616)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_45/D0 (1344:1480:1616)(1344:1480:1616)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_46/D1 (1344:1480:1616)(1344:1480:1616)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_46/D0 (1344:1480:1616)(1344:1480:1616)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_51/D0 (2099:2300:2502)(2099:2300:2502)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_56/D1 (2479:2713:2948)(2479:2713:2948)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_69/C0 (976:1134:1292)(976:1134:1292)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_71/B0 (1571:1773:1976)(1571:1773:1976)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_72/B0 (822:959:1097)(822:959:1097)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_74/B0 (822:959:1097)(822:959:1097)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_77/D0 (1335:1475:1615)(1335:1475:1615)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_78/B0 (2721:3023:3326)(2721:3023:3326)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_79/A0 (1934:2168:2403)(1934:2168:2403)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_95/C1 (976:1134:1292)(976:1134:1292)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_96/A1 (1175:1343:1512)(1175:1343:1512)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_102/B1 (1375:1577:1779)(1375:1577:1779)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_105/A1 (1175:1343:1512)(1175:1343:1512)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_107/D1 (2099:2300:2502)(2099:2300:2502)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_113/B1 (776:908:1040)(776:908:1040)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_115/A0 (1728:1963:2198)(1728:1963:2198)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_117/B1 (1208:1384:1560)(1208:1384:1560)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_117/B0 (1208:1384:1560)(1208:1384:1560)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_118/A1 (1514:1724:1935)(1514:1724:1935)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_118/A0 (1514:1724:1935)(1514:1724:1935)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_119/B1 (822:959:1097)(822:959:1097)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_119/B0 (822:959:1097)(822:959:1097)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_120/B1 (1760:1997:2235)(1760:1997:2235)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_120/B0 (1760:1997:2235)(1760:1997:2235)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_121/C1 (2490:2779:3069)(2490:2779:3069)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_121/C0 (2490:2779:3069)(2490:2779:3069)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_127/B1 (822:959:1097)(822:959:1097)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_127/B0 (822:959:1097)(822:959:1097)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_135/C1 (561:681:801)(561:681:801)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_135/C0 (561:681:801)(561:681:801)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_136/B1 (1213:1389:1566)(1213:1389:1566)) - (INTERCONNECT SLICE_34/Q1 SLICE_138/B1 (1213:1389:1566)(1213:1389:1566)) - (INTERCONNECT SLICE_138/F0 SLICE_19/LSR (539:596:653)(539:596:653)) - (INTERCONNECT SLICE_19/F0 SLICE_20/B1 (1219:1385:1551)(1219:1385:1551)) - (INTERCONNECT SLICE_19/Q0 ram2e_ufm\/SLICE_136/D0 (520:573:626)(520:573:626)) - (INTERCONNECT SLICE_19/F1 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/C1 - (547:660:773)(547:660:773)) - (INTERCONNECT SLICE_19/F1 ram2e_ufm\/SLICE_65/D1 (1264:1385:1506)(1264:1385:1506)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_20/D1 (535:618:701)(535:618:701)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_21/B0 (777:928:1079)(777:928:1079)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_22/D1 (273:306:340)(273:306:340)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_31/B1 (1043:1228:1414)(1043:1228:1414)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_95/C0 (284:372:461) - (284:372:461)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_96/D0 (273:306:340) - (273:306:340)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_132/D1 (535:618:701) - (535:618:701)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_132/D0 (535:618:701) - (535:618:701)) - (INTERCONNECT Ain\[1\]_I/PADDI SLICE_20/C1 (2395:2638:2881)(2395:2638:2881)) - (INTERCONNECT ram2e_ufm\/SLICE_107/F0 SLICE_20/A1 (740:863:986)(740:863:986)) - (INTERCONNECT ram2e_ufm\/SLICE_132/F1 SLICE_20/D0 (520:573:626)(520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_20/C0 (539:668:797)(539:668:797)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_21/A1 (738:877:1017)(738:877:1017)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_22/A0 (1004:1178:1352)(1004:1178:1352)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_23/A1 (738:877:1017)(738:877:1017)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_23/A0 (738:877:1017)(738:877:1017)) - (INTERCONNECT ram2e_ufm\/SLICE_124/F0 SLICE_20/A0 (1067:1225:1383)(1067:1225:1383)) - (INTERCONNECT SLICE_20/F1 SLICE_20/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_20/CE (827:920:1013)(827:920:1013)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_20/CE (827:920:1013)(827:920:1013)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_21/CE (827:920:1013)(827:920:1013)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_21/CE (827:920:1013)(827:920:1013)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_22/CE (1197:1322:1447)(1197:1322:1447)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_22/CE (1197:1322:1447)(1197:1322:1447)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_23/CE (827:920:1013)(827:920:1013)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_23/CE (827:920:1013)(827:920:1013)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_24/CE (542:602:662)(542:602:662)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_24/CE (542:602:662)(542:602:662)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_25/CE (1561:1717:1874)(1561:1717:1874)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_25/CE (1561:1717:1874)(1561:1717:1874)) - (INTERCONNECT SLICE_20/Q0 SLICE_31/D0 (539:599:659)(539:599:659)) - (INTERCONNECT SLICE_20/Q0 ram2e_ufm\/SLICE_132/A1 (733:853:974)(733:853:974)) - (INTERCONNECT SLICE_20/Q0 RAout\[0\]_MGIOL/OPOS (2163:2372:2582)(2163:2372:2582)) - (INTERCONNECT SLICE_31/F1 SLICE_21/D1 (523:573:623)(523:573:623)) - (INTERCONNECT ram2e_ufm\/SLICE_140/F1 SLICE_21/D0 (857:949:1042)(857:949:1042)) - (INTERCONNECT ram2e_ufm\/SLICE_134/F0 SLICE_21/C0 (534:639:744)(534:639:744)) - (INTERCONNECT Ain\[2\]_I/PADDI SLICE_21/A0 (2456:2723:2990)(2456:2723:2990)) - (INTERCONNECT SLICE_21/F1 SLICE_21/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_21/Q0 ram2e_ufm\/SLICE_140/B1 (767:891:1015)(767:891:1015)) - (INTERCONNECT SLICE_21/Q0 RAout\[2\]_MGIOL/OPOS (1785:1948:2112)(1785:1948:2112)) - (INTERCONNECT SLICE_21/Q1 SLICE_31/C1 (877:1027:1177)(877:1027:1177)) - (INTERCONNECT SLICE_21/Q1 SLICE_31/A0 (749:874:1000)(749:874:1000)) - (INTERCONNECT SLICE_21/Q1 RAout\[3\]_MGIOL/OPOS (1530:1666:1802)(1530:1666:1802)) - (INTERCONNECT Ain\[5\]_I/PADDI SLICE_22/C1 (1961:2162:2364)(1961:2162:2364)) - (INTERCONNECT ram2e_ufm\/SLICE_124/F1 SLICE_22/B1 (1031:1183:1336)(1031:1183:1336)) - (INTERCONNECT ram2e_ufm\/SLICE_140/F0 SLICE_22/A1 (730:848:967)(730:848:967)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F0 SLICE_22/D0 (266:290:315)(266:290:315)) - (INTERCONNECT SLICE_22/F1 SLICE_22/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_22/Q0 ram2e_ufm\/SLICE_95/D0 (523:578:633)(523:578:633)) - (INTERCONNECT SLICE_22/Q0 RAout\[4\]_MGIOL/OPOS (1894:2061:2229)(1894:2061:2229)) - (INTERCONNECT SLICE_22/Q1 ram2e_ufm\/SLICE_140/C0 (534:644:754)(534:644:754)) - (INTERCONNECT SLICE_22/Q1 RAout\[5\]_MGIOL/OPOS (1429:1575:1721)(1429:1575:1721)) - (INTERCONNECT ram2e_ufm\/SLICE_132/F0 SLICE_23/C1 (531:639:747)(531:639:747)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F0 SLICE_23/C0 (534:639:744)(534:639:744)) - (INTERCONNECT SLICE_23/F1 SLICE_23/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_23/Q0 ram2e_ufm\/SLICE_96/A0 (735:856:978)(735:856:978)) - (INTERCONNECT SLICE_23/Q0 RAout\[6\]_MGIOL/OPOS (2067:2267:2467)(2067:2267:2467)) - (INTERCONNECT SLICE_23/Q1 ram2e_ufm\/SLICE_132/A0 (733:853:974)(733:853:974)) - (INTERCONNECT SLICE_23/Q1 RAout\[7\]_MGIOL/OPOS (1857:2028:2199)(1857:2028:2199)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F0 SLICE_24/D1 (536:594:652)(536:594:652)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F0 SLICE_25/C1 (874:1022:1170)(874:1022:1170)) - (INTERCONNECT ram2e_ufm\/SLICE_146/F1 SLICE_24/C1 (800:939:1079)(800:939:1079)) - (INTERCONNECT SLICE_24/Q1 SLICE_24/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_24/Q1 RAout\[9\]_MGIOL/OPOS (1863:2048:2233)(1863:2048:2233)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F0 SLICE_24/D0 (857:949:1042)(857:949:1042)) - (INTERCONNECT ram2e_ufm\/SLICE_115/F1 SLICE_24/C0 (803:945:1088)(803:945:1088)) - (INTERCONNECT ram2e_ufm\/SLICE_115/F1 ram2e_ufm\/SLICE_115/C0 (280:362:445) - (280:362:445)) - (INTERCONNECT ram2e_ufm\/SLICE_127/F0 SLICE_24/B0 (762:883:1004)(762:883:1004)) - (INTERCONNECT SLICE_24/Q0 SLICE_24/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_24/Q0 RAout\[8\]_MGIOL/OPOS (1793:1970:2148)(1793:1970:2148)) - (INTERCONNECT SLICE_24/F1 SLICE_24/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_74/F0 SLICE_25/D1 (271:301:332)(271:301:332)) - (INTERCONNECT ram2e_ufm\/SLICE_74/F0 ram2e_ufm\/SLICE_74/C1 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_74/F0 ram2e_ufm\/SLICE_146/D1 (794:884:975) - (794:884:975)) - (INTERCONNECT SLICE_29/Q0 SLICE_25/B1 (1136:1293:1450)(1136:1293:1450)) - (INTERCONNECT SLICE_25/Q1 SLICE_25/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_25/Q1 RAout\[11\]_MGIOL/OPOS (1998:2162:2326)(1998:2162:2326)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F0 SLICE_25/D0 (1449:1580:1712)(1449:1580:1712)) - (INTERCONNECT ram2e_ufm\/SLICE_129/F0 SLICE_25/C0 (277:356:436)(277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_106/F0 SLICE_25/B0 (508:600:693)(508:600:693)) - (INTERCONNECT ram2e_ufm\/SLICE_74/F1 SLICE_25/A0 (476:566:656)(476:566:656)) - (INTERCONNECT SLICE_25/F1 SLICE_25/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_25/Q0 ram2e_ufm\/SLICE_106/D0 (536:594:652)(536:594:652)) - (INTERCONNECT SLICE_25/Q0 RAout\[10\]_MGIOL/OPOS (1432:1576:1721)(1432:1576:1721)) - (INTERCONNECT SLICE_26/F1 SLICE_26/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_27/D1 (846:940:1035)(846:940:1035)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_27/D0 (846:940:1035)(846:940:1035)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/A1 (1811:2036:2262)(1811:2036:2262)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/A0 (1811:2036:2262)(1811:2036:2262)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_29/D1 (1231:1359:1487)(1231:1359:1487)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_29/D0 (1231:1359:1487)(1231:1359:1487)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/D1 (1231:1359:1487)(1231:1359:1487)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/D0 (1231:1359:1487)(1231:1359:1487)) - (INTERCONNECT ram2e_ufm\/SLICE_43/Q1 SLICE_27/B1 (772:897:1023)(772:897:1023)) - (INTERCONNECT ram2e_ufm\/SLICE_43/Q0 SLICE_27/B0 (772:897:1023)(772:897:1023)) - (INTERCONNECT SLICE_27/F1 SLICE_27/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/A1 (1180:1342:1505)(1180:1342:1505)) - (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/A0 (1180:1342:1505)(1180:1342:1505)) - (INTERCONNECT SLICE_27/Q1 ram2e_ufm\/SLICE_78/C0 (531:639:747)(531:639:747)) - (INTERCONNECT ram2e_ufm\/SLICE_44/Q1 SLICE_28/C1 (868:1015:1163)(868:1015:1163)) - (INTERCONNECT ram2e_ufm\/SLICE_44/Q0 SLICE_28/D0 (523:573:623)(523:573:623)) - (INTERCONNECT SLICE_28/F1 SLICE_28/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_28/F0 SLICE_28/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_28/Q0 ram2e_ufm\/SLICE_146/C1 (534:639:744)(534:639:744)) - (INTERCONNECT SLICE_28/Q1 ram2e_ufm\/SLICE_74/A1 (1174:1336:1498)(1174:1336:1498)) - (INTERCONNECT ram2e_ufm\/SLICE_45/Q1 SLICE_29/A1 (740:863:986)(740:863:986)) - (INTERCONNECT ram2e_ufm\/SLICE_45/Q0 SLICE_29/A0 (740:863:986)(740:863:986)) - (INTERCONNECT SLICE_29/F1 SLICE_29/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_29/Q1 ram2e_ufm\/SLICE_72/B1 (1136:1293:1450)(1136:1293:1450)) - (INTERCONNECT ram2e_ufm\/SLICE_46/Q1 SLICE_30/B1 (765:883:1001)(765:883:1001)) - (INTERCONNECT ram2e_ufm\/SLICE_46/Q0 SLICE_30/C0 (534:639:744)(534:639:744)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_30/A0 (2705:2960:3215)(2705:2960:3215)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_40/D1 (2049:2212:2375) - (2049:2212:2375)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_42/D1 (2913:3132:3351) - (2913:3132:3351)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_46/A0 (3123:3407:3692) - (3123:3407:3692)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_50/C0 (3288:3593:3899) - (3288:3593:3899)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/A1 - (2628:2888:3149)(2628:2888:3149)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_62/D1 (2413:2607:2802) - (2413:2607:2802)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_65/A1 (3220:3505:3791) - (3220:3505:3791)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_82/D1 (2461:2653:2845) - (2461:2653:2845)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_83/D1 (2461:2653:2845) - (2461:2653:2845)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_144/B0 (2333:2561:2789) - (2333:2561:2789)) - (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_30/Q0 ram2e_ufm\/SLICE_129/D1 (789:873:958)(789:873:958)) - (INTERCONNECT SLICE_30/Q1 ram2e_ufm\/SLICE_127/C0 (541:653:766)(541:653:766)) - (INTERCONNECT Ain\[3\]_I/PADDI SLICE_31/D1 (2384:2572:2760)(2384:2572:2760)) - (INTERCONNECT nC07X_I/PADDI SLICE_31/C0 (1909:2116:2323)(1909:2116:2323)) - (INTERCONNECT nWE_I/PADDI SLICE_31/B0 (2602:2880:3158)(2602:2880:3158)) - (INTERCONNECT nWE_I/PADDI SLICE_36/D0 (3105:3379:3654)(3105:3379:3654)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/CKE_7\/SLICE_61/B0 (3341:3683:4025) - (3341:3683:4025)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_92/D1 (3105:3379:3654)(3105:3379:3654)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_112/D0 (3073:3352:3632)(3073:3352:3632)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_113/D0 (3073:3352:3632)(3073:3352:3632)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_136/C1 (2698:2998:3298)(2698:2998:3298)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_136/B0 (2602:2880:3158)(2602:2880:3158)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_137/B1 (2214:2429:2644)(2214:2429:2644)) - (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_127/F1 SLICE_31/CE (549:610:672)(549:610:672)) - (INTERCONNECT ram2e_ufm\/SLICE_57/F1 SLICE_32/D1 (520:573:626)(520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_110/F1 SLICE_32/C1 (546:664:783)(546:664:783)) - (INTERCONNECT ram2e_ufm\/SLICE_110/F1 ram2e_ufm\/SLICE_58/B1 (1036:1194:1353) - (1036:1194:1353)) - (INTERCONNECT ram2e_ufm\/SLICE_110/F1 ram2e_ufm\/SLICE_110/B0 (513:611:710) - (513:611:710)) - (INTERCONNECT ram2e_ufm\/SLICE_131/F1 SLICE_32/B1 (765:883:1001)(765:883:1001)) - (INTERCONNECT ram2e_ufm\/SLICE_146/F0 SLICE_32/A1 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_32/F1 SLICE_32/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_137/C1 (1388:1580:1773)(1388:1580:1773)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_137/C0 (1388:1580:1773)(1388:1580:1773)) - (INTERCONNECT SLICE_32/Q0 SLICE_139/B0 (777:906:1036)(777:906:1036)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_141/D1 (1003:1108:1213)(1003:1108:1213)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_141/D0 (1003:1108:1213)(1003:1108:1213)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_142/C0 (1014:1174:1334)(1014:1174:1334)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_143/D1 (1377:1514:1652)(1377:1514:1652)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_143/D0 (1377:1514:1652)(1377:1514:1652)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_144/A1 (1587:1790:1993)(1587:1790:1993)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_144/A0 (1587:1790:1993)(1587:1790:1993)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_147/C0 (1014:1174:1334)(1014:1174:1334)) - (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_139/F0 SLICE_33/D1 (1248:1376:1505)(1248:1376:1505)) - (INTERCONNECT SLICE_139/F0 SLICE_33/D0 (1248:1376:1505)(1248:1376:1505)) - (INTERCONNECT SLICE_139/F0 SLICE_34/D1 (900:989:1079)(900:989:1079)) - (INTERCONNECT SLICE_139/F0 SLICE_34/B0 (1490:1686:1883)(1490:1686:1883)) - (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_33/C1 (538:655:772)(538:655:772)) - (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_34/C1 (538:655:772)(538:655:772)) - (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_34/C0 (284:372:461)(284:372:461)) - (INTERCONNECT ram2e_ufm\/SLICE_106/F1 ram2e_ufm\/SLICE_106/B0 (515:616:718) - (515:616:718)) - (INTERCONNECT ram2e_ufm\/SLICE_135/F1 SLICE_33/B1 (511:606:702)(511:606:702)) - (INTERCONNECT ram2e_ufm\/SLICE_135/F1 SLICE_33/C0 (534:645:756)(534:645:756)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 SLICE_33/A1 (1025:1183:1341)(1025:1183:1341)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 SLICE_38/B1 (1748:1975:2202)(1748:1975:2202)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_78/D0 (525:584:643) - (525:584:643)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_79/B0 (1036:1194:1353) - (1036:1194:1353)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_105/B1 (1421:1613:1805) - (1421:1613:1805)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_106/A0 (1025:1183:1341) - (1025:1183:1341)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_135/D0 (1142:1269:1397) - (1142:1269:1397)) - (INTERCONNECT ram2e_ufm\/SLICE_117/F1 SLICE_33/A0 (1372:1566:1760)(1372:1566:1760)) - (INTERCONNECT SLICE_33/F1 SLICE_33/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_34/Q0 SLICE_34/B1 (800:933:1066)(800:933:1066)) - (INTERCONNECT SLICE_34/Q0 SLICE_34/A0 (483:579:675)(483:579:675)) - (INTERCONNECT SLICE_34/Q0 SLICE_35/A0 (1126:1299:1472)(1126:1299:1472)) - (INTERCONNECT SLICE_34/Q0 SLICE_38/A1 (746:897:1049)(746:897:1049)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_47/A1 (1478:1705:1932)(1478:1705:1932)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_48/D1 (1248:1407:1567)(1248:1407:1567)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_48/D0 (1248:1407:1567)(1248:1407:1567)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_49/A1 (1853:2112:2372)(1853:2112:2372)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_49/A0 (1853:2112:2372)(1853:2112:2372)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_50/B1 (2265:2560:2855)(2265:2560:2855)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_50/B0 (2265:2560:2855)(2265:2560:2855)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_52/A0 (1868:2129:2390)(1868:2129:2390)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_53/D0 (2028:2255:2483)(2028:2255:2483)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_54/A1 (1868:2129:2390)(1868:2129:2390)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_56/LSR (2733:3030:3328)(2733:3030:3328)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_69/D0 (813:934:1056)(813:934:1056)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_71/D0 (813:934:1056)(813:934:1056)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_72/D0 (886:987:1089)(886:987:1089)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_74/D0 (886:987:1089)(886:987:1089)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_77/B0 (1972:2234:2496)(1972:2234:2496)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_78/A0 (1468:1694:1920)(1468:1694:1920)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_79/D0 (2023:2250:2477)(2023:2250:2477)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_86/A1 (1478:1705:1932)(1478:1705:1932)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_89/B0 (2270:2565:2861)(2270:2565:2861)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_90/B0 (2270:2565:2861)(2270:2565:2861)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_95/A1 (1393:1612:1831)(1393:1612:1831)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_96/C1 (1194:1402:1611)(1194:1402:1611)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_97/A0 (1868:2129:2390)(1868:2129:2390)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_98/A0 (2565:2893:3221)(2565:2893:3221)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_102/A1 (1018:1204:1391)(1018:1204:1391)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_106/C0 (569:689:809)(569:689:809)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_107/C1 (2007:2286:2566)(2007:2286:2566)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_109/B1 (1510:1739:1969)(1510:1739:1969)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_112/A0 (746:897:1049)(746:897:1049)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_113/C1 (547:688:829)(547:688:829)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_115/B1 (1420:1641:1862)(1420:1641:1862)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_117/A1 (1876:2129:2383)(1876:2129:2383)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_117/A0 (1876:2129:2383)(1876:2129:2383)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_118/D1 (1666:1854:2042)(1666:1854:2042)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_118/D0 (1666:1854:2042)(1666:1854:2042)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_119/A1 (1126:1299:1472)(1126:1299:1472)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_119/A0 (1126:1299:1472)(1126:1299:1472)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_121/B1 (1500:1728:1957)(1500:1728:1957)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_121/B0 (1500:1728:1957)(1500:1728:1957)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_127/A1 (1126:1299:1472)(1126:1299:1472)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_127/A0 (1126:1299:1472)(1126:1299:1472)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_135/A1 (768:898:1029)(768:898:1029)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_135/A0 (768:898:1029)(768:898:1029)) - (INTERCONNECT SLICE_34/Q0 SLICE_138/A0 (1557:1755:1954)(1557:1755:1954)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_145/A1 (1868:2129:2390)(1868:2129:2390)) - (INTERCONNECT SLICE_34/F1 SLICE_34/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_34/F0 SLICE_34/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_138/F1 SLICE_35/LSR (873:967:1062)(873:967:1062)) - (INTERCONNECT SLICE_35/Q0 SLICE_139/A1 (733:848:964)(733:848:964)) - (INTERCONNECT SLICE_35/F1 BA\[1\]_MGIOL/LSR (2019:2186:2354)(2019:2186:2354)) - (INTERCONNECT SLICE_35/F1 BA\[0\]_MGIOL/LSR (2019:2186:2354)(2019:2186:2354)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_36/C1 (545:668:791)(545:668:791)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_37/A1 (739:869:1000)(739:869:1000)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_38/D0 (275:311:348)(275:311:348)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/CKE_7\/SLICE_61/D0 (532:594:656) - (532:594:656)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/SLICE_92/C1 (545:668:791) - (545:668:791)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/SLICE_113/C0 (286:377:469) - (286:377:469)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_36/A1 (1092:1256:1420)(1092:1256:1420)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_37/C1 (903:1058:1214)(903:1058:1214)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_38/C1 (903:1058:1214)(903:1058:1214)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_91/B0 (1150:1311:1472) - (1150:1311:1472)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_92/A0 (1092:1256:1420) - (1092:1256:1420)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_105/C1 (280:362:445) - (280:362:445)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_112/C1 (903:1058:1214) - (903:1058:1214)) - (INTERCONNECT SLICE_36/F1 SLICE_36/C0 (277:356:436)(277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_69/F1 SLICE_36/B0 (772:897:1023)(772:897:1023)) - (INTERCONNECT ram2e_ufm\/SLICE_92/F0 SLICE_36/A0 (476:566:656)(476:566:656)) - (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_36/Q0 nCASout_MGIOL/OPOS (1549:1684:1820)(1549:1684:1820)) - (INTERCONNECT SLICE_38/F1 SLICE_37/D0 (523:579:635)(523:579:635)) - (INTERCONNECT SLICE_38/F1 SLICE_38/B0 (511:606:702)(511:606:702)) - (INTERCONNECT SLICE_37/F1 SLICE_37/C0 (277:356:436)(277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_112/F0 SLICE_37/B0 (508:600:693)(508:600:693)) - (INTERCONNECT ram2e_ufm\/SLICE_91/F0 SLICE_37/A0 (1067:1225:1383)(1067:1225:1383)) - (INTERCONNECT SLICE_37/F0 SLICE_37/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_37/Q0 nRASout_MGIOL/OPOS (1986:2148:2310)(1986:2148:2310)) - (INTERCONNECT ram2e_ufm\/SLICE_136/F1 SLICE_38/D1 (977:1075:1173)(977:1075:1173)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F1 SLICE_38/C0 (534:639:744)(534:639:744)) - (INTERCONNECT ram2e_ufm\/SLICE_112/F1 SLICE_38/A0 (733:854:976)(733:854:976)) - (INTERCONNECT ram2e_ufm\/SLICE_112/F1 ram2e_ufm\/SLICE_112/C0 (280:362:445) - (280:362:445)) - (INTERCONNECT SLICE_38/F0 SLICE_38/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_38/Q0 nRWEout_MGIOL/OPOS (1913:2080:2247)(1913:2080:2247)) - (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_39/A1 (1059:1222:1385) - (1059:1222:1385)) - (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_87/D1 (1213:1342:1471) - (1213:1342:1471)) - (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_94/C0 (280:362:445) - (280:362:445)) - (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_116/B1 (1091:1256:1422) - (1091:1256:1422)) - (INTERCONNECT ram2e_ufm\/SLICE_39/F1 ram2e_ufm\/SLICE_39/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_39/F0 ram2e_ufm\/SLICE_39/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_39/Q0 ram2e_ufm\/SLICE_80/D0 (854:944:1035) - (854:944:1035)) - (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_40/B0 (511:606:702) - (511:606:702)) - (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_62/C1 (550:666:782) - (550:666:782)) - (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_83/A1 (1113:1271:1429) - (1113:1271:1429)) - (INTERCONNECT ram2e_ufm\/SLICE_40/F0 ram2e_ufm\/SLICE_40/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_51/A0 (1642:1834:2027) - (1642:1834:2027)) - (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_66/D0 (1759:1921:2083) - (1759:1921:2083)) - (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_130/A0 (743:868:993) - (743:868:993)) - (INTERCONNECT ram2e_ufm\/SLICE_41/F1 ram2e_ufm\/SLICE_41/D0 (520:573:626) - (520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_41/B0 (781:910:1039) - (781:910:1039)) - (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_87/B1 (1253:1415:1578) - (1253:1415:1578)) - (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_101/A0 (733:854:976) - (733:854:976)) - (INTERCONNECT ram2e_ufm\/SLICE_41/F0 ram2e_ufm\/SLICE_41/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_41/Q0 ram2e_ufm\/SLICE_147/A1 (730:848:967) - (730:848:967)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO0 ram2e_ufm\/SLICE_42/C0 - (1531:1730:1930)(1531:1730:1930)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO0 ram2e_ufm\/SLICE_43/B0 - (1762:1974:2187)(1762:1974:2187)) - (INTERCONNECT ram2e_ufm\/SLICE_42/F0 ram2e_ufm\/SLICE_42/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F1 ram2e_ufm\/SLICE_42/CE (876:972:1069) - (876:972:1069)) - (INTERCONNECT ram2e_ufm\/SLICE_42/Q0 ram2e_ufm\/SLICE_137/B0 (1670:1864:2058) - (1670:1864:2058)) - (INTERCONNECT ram2e_ufm\/SLICE_42/Q0 ram2e_ufm\/SLICE_147/C1 (993:1147:1302) - (993:1147:1302)) - (INTERCONNECT ram2e_ufm\/SLICE_42/F1 ram2e_ufm\/SLICE_84/C1 (849:1000:1152) - (849:1000:1152)) - (INTERCONNECT ram2e_ufm\/SLICE_42/F1 ram2e_ufm\/SLICE_87/A1 (1215:1374:1534) - (1215:1374:1534)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO1 ram2e_ufm\/SLICE_43/B1 - (1769:1982:2196)(1769:1982:2196)) - (INTERCONNECT ram2e_ufm\/SLICE_43/F1 ram2e_ufm\/SLICE_43/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_43/F0 ram2e_ufm\/SLICE_43/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_43/CE (900:1003:1107) - (900:1003:1107)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_43/CE (900:1003:1107) - (900:1003:1107)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_44/CE (542:602:662) - (542:602:662)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_44/CE (542:602:662) - (542:602:662)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_45/CE (900:1003:1107) - (900:1003:1107)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_45/CE (900:1003:1107) - (900:1003:1107)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_46/CE (900:1003:1107) - (900:1003:1107)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_46/CE (900:1003:1107) - (900:1003:1107)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO3 ram2e_ufm\/SLICE_44/B1 - (1686:1890:2095)(1686:1890:2095)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO2 ram2e_ufm\/SLICE_44/C0 - (1174:1343:1512)(1174:1343:1512)) - (INTERCONNECT ram2e_ufm\/SLICE_44/F1 ram2e_ufm\/SLICE_44/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_44/F0 ram2e_ufm\/SLICE_44/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO5 ram2e_ufm\/SLICE_45/C1 - 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(INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_54/CE (1744:1910:2077) - (1744:1910:2077)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_54/CE (1744:1910:2077) - (1744:1910:2077)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_55/CE (2108:2306:2504) - (2108:2306:2504)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_55/CE (2108:2306:2504) - (2108:2306:2504)) - (INTERCONNECT ram2e_ufm\/SLICE_47/Q0 ram2e_ufm\/SLICE_52/B0 (767:891:1015) - (767:891:1015)) - (INTERCONNECT ram2e_ufm\/SLICE_47/Q0 - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in - (1272:1405:1538)(1272:1405:1538)) - (INTERCONNECT ram2e_ufm\/SLICE_47/Q1 ram2e_ufm\/SLICE_97/D0 (1297:1429:1561) - (1297:1429:1561)) - (INTERCONNECT ram2e_ufm\/SLICE_47/Q1 - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in - (1451:1590:1730)(1451:1590:1730)) - (INTERCONNECT ram2e_ufm\/SLICE_48/F1 ram2e_ufm\/SLICE_48/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_48/F0 ram2e_ufm\/SLICE_48/DI0 (0:0:0)(0:0:0)) - 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(544:604:664)) - (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_114/C0 (539:653:767) - (539:653:767)) - (INTERCONNECT ram2e_ufm\/SLICE_109/F0 ram2e_ufm\/SLICE_58/C1 (531:639:747) - (531:639:747)) - (INTERCONNECT ram2e_ufm\/SLICE_58/F1 ram2e_ufm\/SLICE_58/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_126/F1 ram2e_ufm\/SLICE_58/B0 (508:600:693) - (508:600:693)) - (INTERCONNECT ram2e_ufm\/SLICE_58/F0 ram2e_ufm\/SLICE_58/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F0 ram2e_ufm\/SLICE_58/CE (2142:2337:2532) - (2142:2337:2532)) - (INTERCONNECT ram2e_ufm\/SLICE_58/Q0 - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin - (1081:1188:1296)(1081:1188:1296)) - (INTERCONNECT ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/OFX0 ram2e_ufm\/SLICE_133/D0 - (520:573:626)(520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_94/F0 - ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/D1 (530:587:645)(530:587:645)) - (INTERCONNECT ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/OFX0 - ram2e_ufm\/SLICE_82/D0 (1220:1340:1460)(1220:1340:1460)) - (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/CKE_7\/SLICE_61/C1 (536:650:764) - (536:650:764)) - (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/SLICE_91/A1 (481:577:673) - (481:577:673)) - (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/SLICE_102/D0 (525:584:643) - (525:584:643)) - (INTERCONNECT ram2e_ufm\/SLICE_102/F0 ram2e_ufm\/CKE_7\/SLICE_61/M0 (485:526:568) - (485:526:568)) - (INTERCONNECT ram2e_ufm\/SLICE_62/F0 ram2e_ufm\/SLICE_84/D0 (530:587:645) - (530:587:645)) - (INTERCONNECT ram2e_ufm\/SLICE_65/F0 ram2e_ufm\/SLICE_63/C1 (534:639:744) - (534:639:744)) - (INTERCONNECT ram2e_ufm\/SLICE_133/F0 ram2e_ufm\/SLICE_63/B1 (762:883:1004) - (762:883:1004)) - (INTERCONNECT ram2e_ufm\/SLICE_84/F0 ram2e_ufm\/SLICE_63/C0 (531:639:747) - (531:639:747)) - (INTERCONNECT ram2e_ufm\/SLICE_63/F1 ram2e_ufm\/SLICE_63/B0 (762:883:1004) - (762:883:1004)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_63/A0 (1225:1391:1557) - (1225:1391:1557)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_66/A0 (1006:1165:1324) - (1006:1165:1324)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_79/C1 (284:372:461) - (284:372:461)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_84/C0 (1026:1181:1337) - (1026:1181:1337)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_85/D0 (527:589:651) - (527:589:651)) - (INTERCONNECT ram2e_ufm\/SLICE_64/F1 ram2e_ufm\/SLICE_64/A0 (730:848:967) - (730:848:967)) - (INTERCONNECT ram2e_ufm\/SLICE_100/F0 ram2e_ufm\/SLICE_65/D0 (523:573:623) - (523:573:623)) - (INTERCONNECT ram2e_ufm\/SLICE_65/F1 ram2e_ufm\/SLICE_65/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_108/F0 ram2e_ufm\/SLICE_66/C1 (868:1015:1163) - (868:1015:1163)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_66/B1 (1042:1201:1360) - (1042:1201:1360)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_70/A1 (1750:1970:2191) - (1750:1970:2191)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_80/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_81/A1 (2125:2378:2631) - (2125:2378:2631)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_85/A1 (1380:1568:1757) - (1380:1568:1757)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_89/A1 (2489:2773:3058) - (2489:2773:3058)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_98/C1 (1926:2168:2411) - (1926:2168:2411)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_130/B0 (1249:1414:1579) - (1249:1414:1579)) - (INTERCONNECT ram2e_ufm\/SLICE_66/F1 ram2e_ufm\/SLICE_66/B0 (762:883:1004) - (762:883:1004)) - (INTERCONNECT ram2e_ufm\/SLICE_67/F1 ram2e_ufm\/SLICE_67/B0 (508:600:693) - (508:600:693)) - (INTERCONNECT ram2e_ufm\/SLICE_67/F0 ram2e_ufm\/SLICE_91/A0 (999:1149:1299) - (999:1149:1299)) - (INTERCONNECT ram2e_ufm\/SLICE_68/F0 ram2e_ufm\/SLICE_68/A1 (730:848:967) - (730:848:967)) - (INTERCONNECT ram2e_ufm\/SLICE_68/F1 ram2e_ufm\/SLICE_86/A0 (740:863:986) - (740:863:986)) - (INTERCONNECT ram2e_ufm\/SLICE_122/F0 ram2e_ufm\/SLICE_69/A1 (730:848:967) - (730:848:967)) - (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_70/D0 (528:584:640) - (528:584:640)) - (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_75/B0 (513:611:710) - (513:611:710)) - (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_88/A0 (738:859:981) - (738:859:981)) - (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_70/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_79/B1 (777:908:1040) - (777:908:1040)) - (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_111/C1 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_71/C1 (286:377:469) - (286:377:469)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_91/D0 (973:1081:1190) - (973:1081:1190)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_124/C1 (540:660:780) - (540:660:780)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_124/D0 (529:594:659) - (529:594:659)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_146/B1 (774:904:1034) - (774:904:1034)) - (INTERCONNECT ram2e_ufm\/SLICE_72/F0 ram2e_ufm\/SLICE_72/C1 (534:645:756) - (534:645:756)) - (INTERCONNECT ram2e_ufm\/SLICE_72/F0 ram2e_ufm\/SLICE_129/A1 (733:854:976) - (733:854:976)) - (INTERCONNECT ram2e_ufm\/SLICE_72/F1 BA\[0\]_MGIOL/OPOS (2268:2466:2665) - (2268:2466:2665)) - (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_73/D1 (862:960:1059) - (862:960:1059)) - (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_103/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_109/B0 (777:908:1040) - (777:908:1040)) - (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_73/B1 (767:894:1021) - (767:894:1021)) - (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_97/D1 (525:584:643) - (525:584:643)) - (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_145/C1 (536:650:764) - (536:650:764)) - (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_73/A1 (1013:1167:1321) - (1013:1167:1321)) - (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_97/B0 (1045:1201:1358) - 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(523:573:623)) - (INTERCONNECT ram2e_ufm\/SLICE_99/F1 ram2e_ufm\/SLICE_99/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_115/F0 ram2e_ufm\/SLICE_102/C0 (534:639:744) - (534:639:744)) - (INTERCONNECT ram2e_ufm\/SLICE_128/F0 ram2e_ufm\/SLICE_103/D0 (857:949:1042) - (857:949:1042)) - (INTERCONNECT ram2e_ufm\/SLICE_123/F1 ram2e_ufm\/SLICE_103/B0 (772:897:1023) - (772:897:1023)) - (INTERCONNECT ram2e_ufm\/SLICE_104/F1 ram2e_ufm\/SLICE_104/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_122/F1 ram2e_ufm\/SLICE_105/D1 (520:573:626) - (520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_107/F1 ram2e_ufm\/SLICE_107/A0 (733:854:976) - (733:854:976)) - (INTERCONNECT ram2e_ufm\/SLICE_107/F1 ram2e_ufm\/SLICE_134/D0 (523:579:635) - (523:579:635)) - (INTERCONNECT ram2e_ufm\/SLICE_134/F1 ram2e_ufm\/SLICE_108/C1 (531:639:747) - (531:639:747)) - (INTERCONNECT ram2e_ufm\/SLICE_111/F0 ram2e_ufm\/SLICE_111/A1 (476:566:656) - (476:566:656)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_112/B0 (1960:2153:2347) - (1960:2153:2347)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_113/D1 (2045:2205:2366) - (2045:2205:2366)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_115/B0 (2699:2956:3214) - (2699:2956:3214)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_135/B0 (2335:2561:2787) - (2335:2561:2787)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_136/A1 (3150:3439:3729) - (3150:3439:3729)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_136/A0 (3150:3439:3729) - (3150:3439:3729)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_137/A1 (3520:3841:4163) - (3520:3841:4163)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_137/A0 (3520:3841:4163) - (3520:3841:4163)) - (INTERCONNECT ram2e_ufm\/SLICE_114/F1 ram2e_ufm\/SLICE_114/A0 (730:848:967) - (730:848:967)) - (INTERCONNECT ram2e_ufm\/SLICE_116/F0 ram2e_ufm\/SLICE_116/A1 (476:566:656) - (476:566:656)) - (INTERCONNECT ram2e_ufm\/SLICE_117/F0 BA\[1\]_MGIOL/CE (1617:1766:1916) - (1617:1766:1916)) - (INTERCONNECT ram2e_ufm\/SLICE_117/F0 BA\[0\]_MGIOL/CE (1617:1766:1916) - (1617:1766:1916)) - (INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQMH_MGIOL/CE (1617:1766:1916) - (1617:1766:1916)) - (INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQML_MGIOL/CE (1617:1766:1916) - (1617:1766:1916)) - (INTERCONNECT ram2e_ufm\/SLICE_120/F0 DQML_MGIOL/OPOS (1549:1684:1820) - (1549:1684:1820)) - (INTERCONNECT ram2e_ufm\/SLICE_120/F1 DQMH_MGIOL/OPOS (1867:2037:2208) - (1867:2037:2208)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[7\]_MGIOL/CE (1550:1706:1862) - (1550:1706:1862)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[6\]_MGIOL/CE (1550:1706:1862) - (1550:1706:1862)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[5\]_MGIOL/CE (2402:2624:2847) - (2402:2624:2847)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[4\]_MGIOL/CE (2402:2624:2847) - (2402:2624:2847)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[3\]_MGIOL/CE (1550:1706:1862) - (1550:1706:1862)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[2\]_MGIOL/CE (2402:2624:2847) - (2402:2624:2847)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[1\]_MGIOL/CE (1550:1706:1862) - (1550:1706:1862)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[0\]_MGIOL/CE (2402:2624:2847) - (2402:2624:2847)) - (INTERCONNECT ram2e_ufm\/SLICE_129/F1 BA\[1\]_MGIOL/OPOS (2322:2519:2716) - (2322:2519:2716)) - (INTERCONNECT Ain\[0\]_I/PADDI ram2e_ufm\/SLICE_132/C1 (2031:2242:2454) - (2031:2242:2454)) - (INTERCONNECT Ain\[7\]_I/PADDI ram2e_ufm\/SLICE_132/C0 (2031:2242:2454) - (2031:2242:2454)) - (INTERCONNECT ram2e_ufm\/SLICE_136/F0 nDOE_I/PADDO (1902:2078:2254) - (1902:2078:2254)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F0 LED_I/PADDO (1300:1433:1567)(1300:1433:1567)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[0\]_I/PADDT (688:769:851)(688:769:851)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[7\]_I/PADDT (1491:1644:1798) - (1491:1644:1798)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[6\]_I/PADDT (1491:1644:1798) - (1491:1644:1798)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[5\]_I/PADDT (1491:1644:1798) - (1491:1644:1798)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[4\]_I/PADDT (1491:1644:1798) - (1491:1644:1798)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[3\]_I/PADDT (947:1055:1164) - (947:1055:1164)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[2\]_I/PADDT (947:1055:1164) - (947:1055:1164)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[1\]_I/PADDT (688:769:851)(688:769:851)) - (INTERCONNECT PHI1_I/PADDI SLICE_139/B1 (2525:2775:3025)(2525:2775:3025)) - (INTERCONNECT PHI1_I/PADDI SLICE_139/A0 (2166:2378:2591)(2166:2378:2591)) - (INTERCONNECT PHI1_I/PADDI PHI1_MGIOL/DI (544:554:565)(544:554:565)) - (INTERCONNECT PHI1_MGIOL/IN SLICE_139/C0 (1174:1343:1512)(1174:1343:1512)) - (INTERCONNECT SLICE_139/F1 nVOE_I/PADDO (1534:1723:1913)(1534:1723:1913)) - (INTERCONNECT ram2e_ufm\/SLICE_141/F0 RD\[3\]_I/PADDO (936:1038:1140) - (936:1038:1140)) - (INTERCONNECT ram2e_ufm\/SLICE_141/F1 RD\[0\]_I/PADDO (1300:1433:1567) - (1300:1433:1567)) - (INTERCONNECT ram2e_ufm\/SLICE_142/F0 RD\[4\]_I/PADDO (1802:1982:2163) - (1802:1982:2163)) - (INTERCONNECT ram2e_ufm\/SLICE_143/F0 RD\[7\]_I/PADDO (1367:1504:1642) - (1367:1504:1642)) - (INTERCONNECT ram2e_ufm\/SLICE_143/F1 RD\[1\]_I/PADDO (936:1038:1140) - (936:1038:1140)) - (INTERCONNECT ram2e_ufm\/SLICE_144/F0 RD\[6\]_I/PADDO (1557:1697:1838) - (1557:1697:1838)) - (INTERCONNECT ram2e_ufm\/SLICE_144/F1 RD\[2\]_I/PADDO (1111:1225:1339) - (1111:1225:1339)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F0 RD\[5\]_I/PADDO (1839:2016:2193) - (1839:2016:2193)) - (INTERCONNECT RD\[0\]_I/PADDI Vout\[0\]_MGIOL/OPOS (2735:2961:3187) - (2735:2961:3187)) - (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2000:2173:2346)(2000:2173:2346)) - (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (3308:3554:3800) - (3308:3554:3800)) - (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (2446:2645:2845)(2446:2645:2845)) - (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (3321:3568:3816) - (3321:3568:3816)) - (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (3437:3693:3950)(3437:3693:3950)) - (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (2884:3105:3326) - (2884:3105:3326)) - (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (2910:3136:3363)(2910:3136:3363)) - (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (2876:3096:3316) - (2876:3096:3316)) - (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (3652:3942:4232)(3652:3942:4232)) - (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (2884:3105:3326) - (2884:3105:3326)) - (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2000:2173:2346)(2000:2173:2346)) - (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (2467:2657:2847) - (2467:2657:2847)) - (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (3206:3469:3733)(3206:3469:3733)) - (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (2794:3032:3271) - (2794:3032:3271)) - (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (1924:2084:2244)(1924:2084:2244)) - (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (30:36:43)(30:36:43)) - (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (30:36:43)(30:36:43)) - (INTERCONNECT RAout\[11\]_MGIOL/IOLDO RAout\[11\]_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT RAout\[10\]_MGIOL/IOLDO RAout\[10\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[9\]_MGIOL/IOLDO RAout\[9\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[8\]_MGIOL/IOLDO RAout\[8\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[7\]_MGIOL/IOLDO RAout\[7\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[6\]_MGIOL/IOLDO RAout\[6\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[5\]_MGIOL/IOLDO RAout\[5\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[4\]_MGIOL/IOLDO RAout\[4\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[3\]_MGIOL/IOLDO RAout\[3\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[2\]_MGIOL/IOLDO RAout\[2\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[1\]_MGIOL/IOLDO RAout\[1\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[0\]_MGIOL/IOLDO RAout\[0\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT nRWEout_MGIOL/IOLDO nRWEout_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT nCASout_MGIOL/IOLDO nCASout_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT nRASout_MGIOL/IOLDO nRASout_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT CKEout_MGIOL/IOLDO CKEout_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (7:62:118)(7:62:118)) - (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (7:62:118)(7:62:118)) - (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (11:21:32)(11:21:32)) - (INTERCONNECT Vout\[4\]_MGIOL/IOLDO Vout\[4\]_I/IOLDO (11:21:32)(11:21:32)) - (INTERCONNECT Vout\[3\]_MGIOL/IOLDO Vout\[3\]_I/IOLDO (7:62:118)(7:62:118)) - (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (11:21:32)(11:21:32)) - (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (7:62:118)(7:62:118)) - (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (11:21:32)(11:21:32)) - ) - ) - ) -) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo deleted file mode 100644 index a280446..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo +++ /dev/null @@ -1,7703 +0,0 @@ - -// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 - -// ldbanno -n Verilog -o RAM2E_LCMXO2_1200HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd -// Netlist created on Thu Dec 28 23:23:27 2023 -// Netlist written on Thu Dec 28 23:23:52 2023 -// Design is for device LCMXO2-1200HC -// Design is for package TQFP100 -// Design is for performance grade 4 - -`timescale 1 ns / 1 ps - -module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, - Vout, nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout, BA, - RAout, DQML, DQMH, RD ); - input C14M, PHI1, nWE, nWE80, nEN80, nC07X; - input [7:0] Ain; - input [7:0] Din; - output LED; - output [7:0] Dout; - output nDOE; - output [7:0] Vout; - output nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout; - output [1:0] BA; - output [11:0] RAout; - output DQML, DQMH; - inout [7:0] RD; - wire \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , - \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , - \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , - \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , - \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , - \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , - \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , - \S[1] , \S[0] , N_551, \ram2e_ufm/CKE_7 , CKE_7_RNIS77M1, CKE, - \ram2e_ufm/wb_adr_0_sqmuxa_1_i , RWSel, CO0_0, \CmdTout_3[0] , - N_185_i, GND, \RC[2] , CO0_1, \RC[1] , N_360_i, RC12, - \ram2e_ufm/N_821 , \ram2e_ufm/SUM1_0_0 , \ram2e_ufm/SUM0_i_a3_4_0 , - \ram2e_ufm/N_886 , \ram2e_ufm/N_215 , \CS[1] , \ram2e_ufm/SUM0_i_4 , - \CS[2] , CmdExecMXO2_3_0_a3_0_RNI6S1P8, N_547_i, un1_CS_0_sqmuxa_i, - \CS[0] , \ram2e_ufm/N_234 , CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514, - \Din_c[3] , \Din_c[5] , \ram2e_ufm/N_800 , - \ram2e_ufm/CmdLEDGet_3_0_a3_1 , \Din_c[1] , \ram2e_ufm/N_847 , - \Din_c[2] , CmdLEDGet_3, N_187_i, CmdLEDGet, \Din_c[7] , - \ram2e_ufm/N_883 , \Din_c[4] , CmdLEDSet_3, CmdLEDSet, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 , CmdRWMaskSet_3, CmdRWMaskSet, - \ram2e_ufm/N_850 , \Din_c[0] , CmdSetRWBankFFLED_4, CmdSetRWBankFFLED, - \CmdTout[1] , \CmdTout[2] , N_369_i, N_368_i, \RA[1] , - \ram2e_ufm/N_186 , \S[3] , N_1080_0, \ram2e_ufm/N_660 , DOEEN, - \ram2e_ufm/N_193 , \ram2e_ufm/N_182 , \Ain_c[1] , \ram2e_ufm/N_659 , - \ram2e_ufm/RA_35_0_0_1[0] , \ram2e_ufm/N_801 , \ram2e_ufm/N_684 , - N_223, \RA_35[0] , N_126, \RA[0] , \ram2e_ufm/RA_35_0_0_0[3] , - \ram2e_ufm/N_680 , \ram2e_ufm/N_679 , \Ain_c[2] , \RA_35[3] , - \RA_35[2] , \RA[2] , \RA[3] , \Ain_c[5] , \ram2e_ufm/RA_35_0_0_0[5] , - \ram2e_ufm/N_621 , \ram2e_ufm/RA_35_0_0_0[4] , \RA_35[5] , \RA_35[4] , - \RA[4] , \RA[5] , \ram2e_ufm/RA_35_0_0_0_0[7] , - \ram2e_ufm/RA_35_0_0_0_0[6] , \RA_35[7] , \RA_35[6] , \RA[6] , - \RA[7] , \ram2e_ufm/N_242 , \ram2e_ufm/RA_35_0_0_0[9] , \RA[9] , - \ram2e_ufm/N_699 , \ram2e_ufm/N_221 , \ram2e_ufm/N_698 , \RA[8] , - \RA_35[9] , un2_S_2_i_0_0_o3_RNIHFHN3, \ram2e_ufm/N_845 , \RWBank[4] , - \RA[11] , \ram2e_ufm/N_628 , \ram2e_ufm/N_627 , \ram2e_ufm/N_624 , - \ram2e_ufm/RA_35_2_0_0[10] , \RA_35[11] , \RA_35[10] , \RA[10] , - \RC_3[2] , \RC_3[1] , \ram2e_ufm/N_188 , \ram2e_ufm/RWMask[1] , - \ram2e_ufm/RWMask[0] , \RWBank_3[1] , \RWBank_3[0] , \RWBank[0] , - \RWBank[1] , \ram2e_ufm/RWMask[3] , \ram2e_ufm/RWMask[2] , - \RWBank_3[3] , \RWBank_3[2] , \RWBank[2] , \RWBank[3] , - \ram2e_ufm/RWMask[5] , \ram2e_ufm/RWMask[4] , \RWBank_3[5] , - \RWBank_3[4] , \RWBank[5] , \ram2e_ufm/RWMask[7] , - \ram2e_ufm/RWMask[6] , \Din_c[6] , \RWBank_3[7] , \RWBank_3[6] , - \RWBank[6] , \RWBank[7] , \Ain_c[3] , nC07X_c, nWE_c, RWSel_2, - un9_VOEEN_0_a2_0_a3_0_a3, \ram2e_ufm/Ready3_0_a3_4 , - \ram2e_ufm/N_885 , \ram2e_ufm/Ready3_0_a3_5 , - \ram2e_ufm/Ready3_0_a3_3 , Ready3, Ready, N_1026_0, S_1, - \ram2e_ufm/N_194 , \ram2e_ufm/N_271 , \ram2e_ufm/S_r_i_0_o2[1] , - \ram2e_ufm/N_643 , N_362_i, \S_s_0_0[0] , \S[2] , N_372_i, N_361_i, - N_1078_0, VOEEN, BA_0_sqmuxa, \ram2e_ufm/N_804 , \ram2e_ufm/N_285_i , - \ram2e_ufm/N_872 , \ram2e_ufm/N_641 , \ram2e_ufm/N_640 , N_370_i, - nCAS, \ram2e_ufm/N_615 , \ram2e_ufm/N_617 , \ram2e_ufm/N_616 , - \ram2e_ufm/nRAS_s_i_0_0 , N_358_i, nRAS, \ram2e_ufm/N_226 , - \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] , \ram2e_ufm/N_866 , N_359_i, nRWE, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 , - \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 , \ram2e_ufm/CmdBitbangMXO2_3 , - \ram2e_ufm/CmdBitbangMXO2 , \ram2e_ufm/N_851 , - \ram2e_ufm/CmdExecMXO2_3 , \ram2e_ufm/CmdExecMXO2 , - \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 , \ram2e_ufm/N_190 , - \ram2e_ufm/CmdSetRWBankFFChip_3 , \ram2e_ufm/CmdSetRWBankFFChip , - \ram2e_ufm/wb_dato[0] , \ram2e_ufm/N_295 , - \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] , \ram2e_ufm/LEDEN , - \ram2e_ufm/N_212 , \ram2e_ufm/wb_dato[1] , \ram2e_ufm/N_307_i , - \ram2e_ufm/N_309_i , \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] , - \ram2e_ufm/wb_dato[3] , \ram2e_ufm/wb_dato[2] , \ram2e_ufm/N_302_i , - \ram2e_ufm/N_304_i , \ram2e_ufm/wb_dato[5] , \ram2e_ufm/wb_dato[4] , - \ram2e_ufm/N_301_i , \ram2e_ufm/N_310_i , \ram2e_ufm/wb_dato[7] , - \ram2e_ufm/wb_dato[6] , \ram2e_ufm/N_296 , \ram2e_ufm/N_300_i , - \ram2e_ufm/wb_adr_7_5_41_0_1 , \ram2e_ufm/N_768 , - \ram2e_ufm/wb_adr_7_i_i_4[0] , \ram2e_ufm/wb_adr_7_i_i_5[0] , - \ram2e_ufm/N_793 , \ram2e_ufm/wb_adr_RNO[1] , - \ram2e_ufm/wb_adr_7_i_i[0] , \ram2e_ufm/CmdBitbangMXO2_RNINSM62 , - \ram2e_ufm/wb_adr[0] , \ram2e_ufm/wb_adr[1] , \ram2e_ufm/N_268_i , - \ram2e_ufm/N_80_i , \ram2e_ufm/wb_adr[2] , \ram2e_ufm/wb_adr[3] , - \ram2e_ufm/N_290 , \ram2e_ufm/N_294 , \ram2e_ufm/wb_adr[4] , - \ram2e_ufm/wb_adr[5] , \ram2e_ufm/N_267_i , \ram2e_ufm/N_284 , - \ram2e_ufm/wb_adr[6] , \ram2e_ufm/wb_adr[7] , \ram2e_ufm/wb_ack , - \ram2e_ufm/N_336 , \ram2e_ufm/N_687 , \ram2e_ufm/wb_cyc_stb_RNO , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] , - \ram2e_ufm/wb_cyc_stb , \ram2e_ufm/wb_dati_7_0_0_0[1] , - \ram2e_ufm/N_611 , \ram2e_ufm/N_849 , \ram2e_ufm/N_856 , - \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] , \ram2e_ufm/wb_dati_7[1] , - \ram2e_ufm/wb_dati_7[0] , \ram2e_ufm/wb_dati[0] , - \ram2e_ufm/wb_dati[1] , \ram2e_ufm/N_783 , - \ram2e_ufm/wb_dati_7_0_0_0_0[3] , \ram2e_ufm/wb_dati_7_0_0_o3_0[2] , - \ram2e_ufm/N_760 , \ram2e_ufm/wb_dati_7[3] , \ram2e_ufm/wb_dati_7[2] , - \ram2e_ufm/wb_dati[2] , \ram2e_ufm/wb_dati[3] , \ram2e_ufm/N_763 , - \ram2e_ufm/N_757 , \ram2e_ufm/wb_dati_7_0_0_0[4] , - \ram2e_ufm/wb_dati_7[5] , \ram2e_ufm/wb_dati_7[4] , - \ram2e_ufm/wb_dati[4] , \ram2e_ufm/wb_dati[5] , - \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] , \ram2e_ufm/N_604 , - \ram2e_ufm/N_602 , \ram2e_ufm/wb_dati_7_0_0_0_0[7] , - \ram2e_ufm/wb_dati_7_0_0_0[6] , \ram2e_ufm/wb_dati_7[7] , - \ram2e_ufm/wb_dati_7[6] , \ram2e_ufm/wb_dati[6] , - \ram2e_ufm/wb_dati[7] , \ram2e_ufm/wb_reqc_1 , \ram2e_ufm/wb_reqc_i , - \ram2e_ufm/wb_req , \ram2e_ufm/wb_rst8 , \ram2e_ufm/wb_rst16_i , - \ram2e_ufm/wb_rst , \ram2e_ufm/N_799 , - \ram2e_ufm/wb_we_7_iv_0_0_3_0_0 , \ram2e_ufm/wb_we_7_iv_0_0_3_0_1 , - \ram2e_ufm/N_208 , \ram2e_ufm/wb_we_RNO , \ram2e_ufm/wb_we_RNO_0 , - \ram2e_ufm/wb_we , \ram2e_ufm/N_338 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 , \ram2e_ufm/N_817 , - \ram2e_ufm/CKE_7_sm0 , \ram2e_ufm/N_720_tz , \ram2e_ufm/SUM0_i_0 , - \ram2e_ufm/N_350 , \ram2e_ufm/SUM0_i_3 , \ram2e_ufm/SUM0_i_1 , - \ram2e_ufm/N_187 , \ram2e_ufm/N_755 , \ram2e_ufm/N_345 , - \ram2e_ufm/N_735 , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] , - \ram2e_ufm/N_777 , \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] , - \ram2e_ufm/N_250 , \ram2e_ufm/N_256 , \ram2e_ufm/wb_adr_7_i_i_3_1[0] , - \ram2e_ufm/wb_adr_7_i_i_3[0] , \ram2e_ufm/N_254 , \ram2e_ufm/N_876 , - \ram2e_ufm/N_807 , \ram2e_ufm/N_784 , \ram2e_ufm/N_560 , \BA_4[0] , - \ram2e_ufm/N_184 , \ram2e_ufm/N_873 , \ram2e_ufm/N_781 , - \ram2e_ufm/N_625 , \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] , - \ram2e_ufm/N_811 , \ram2e_ufm/N_206 , - \ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] , \ram2e_ufm/N_185 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S , \ram2e_ufm/N_637 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 , \ram2e_ufm/N_592 , - \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] , \ram2e_ufm/N_634 , - \ram2e_ufm/N_753 , \ram2e_ufm/wb_adr_7_i_i_1[0] , - \ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] , - \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] , - \ram2e_ufm/wb_dati_7_0_0_a3_1[6] , \ram2e_ufm/N_890 , - \ram2e_ufm/N_220 , \ram2e_ufm/N_196 , \ram2e_ufm/N_243 , \Ain_c[4] , - \Ain_c[6] , \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] , \ram2e_ufm/N_565 , - \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] , \ram2e_ufm/CKE_7s2_0_0_0 , - \ram2e_ufm/wb_adr_7_5_41_a3_3_0 , \ram2e_ufm/N_204 , - \ram2e_ufm/N_595 , \ram2e_ufm/nRWE_s_i_0_63_1 , \ram2e_ufm/N_792 , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] , - \ram2e_ufm/N_553 , nEN80_c, \ram2e_ufm/N_241_i , \ram2e_ufm/N_814 , - N_225_i, N_201_i, N_507_i, N_508, Vout3, \BA_4[1] , \Ain_c[0] , - \Ain_c[7] , nDOE_c, LED_c, RDOE_i, PHI1_c, PHI1r, nVOE_c, N_263_i, - N_667, N_648, N_662, N_666, N_663, N_665, N_664, \RD_in[0] , - \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , - \RD_in[2] , \RD_in[1] , DQMH_c, DQML_c, \RAout_c[11] , \RAout_c[10] , - \RAout_c[9] , \RAout_c[8] , \RAout_c[7] , \RAout_c[6] , \RAout_c[5] , - \RAout_c[4] , \RAout_c[3] , \RAout_c[2] , \RAout_c[1] , \RAout_c[0] , - \BA_c[1] , \BA_c[0] , nRWEout_c, nCASout_c, nRASout_c, CKEout_c, - \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] , - \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , VCCI; - - SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), - .Q1(\FS[0] ), .FCO(\FS_cry[0] )); - SLICE_1 SLICE_1( .A0(\FS[15] ), .DI0(\FS_s[15] ), .CLK(C14M_c), - .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), .Q0(\FS[15] )); - SLICE_2 SLICE_2( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), - .DI0(\FS_s[13] ), .CLK(C14M_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), - .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] )); - SLICE_3 SLICE_3( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), - .DI0(\FS_s[11] ), .CLK(C14M_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), - .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] )); - SLICE_4 SLICE_4( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), - .DI0(\FS_s[9] ), .CLK(C14M_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), - .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] )); - SLICE_5 SLICE_5( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), - .DI0(\FS_s[7] ), .CLK(C14M_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), - .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] )); - SLICE_6 SLICE_6( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), - .DI0(\FS_s[5] ), .CLK(C14M_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), - .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] )); - SLICE_7 SLICE_7( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), - .DI0(\FS_s[3] ), .CLK(C14M_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), - .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] )); - SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), - .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), - .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); - SLICE_9 SLICE_9( .D1(\S[1] ), .C1(\FS[15] ), .B1(\S[0] ), .A1(N_551), - .D0(\S[1] ), .C0(\S[0] ), .B0(\ram2e_ufm/CKE_7 ), .A0(N_551), - .DI0(CKE_7_RNIS77M1), .CLK(C14M_c), .F0(CKE_7_RNIS77M1), .Q0(CKE), - .F1(\ram2e_ufm/wb_adr_0_sqmuxa_1_i )); - SLICE_10 SLICE_10( .B0(RWSel), .A0(CO0_0), .DI0(\CmdTout_3[0] ), - .CE(N_185_i), .CLK(C14M_c), .F0(\CmdTout_3[0] ), .Q0(CO0_0), .F1(GND)); - SLICE_11 SLICE_11( .D1(\RC[2] ), .A1(CO0_1), .D0(\RC[2] ), .B0(\RC[1] ), - .A0(CO0_1), .DI0(N_360_i), .CE(RC12), .CLK(C14M_c), .F0(N_360_i), - .Q0(CO0_1), .F1(\ram2e_ufm/N_821 )); - SLICE_12 SLICE_12( .D1(\ram2e_ufm/SUM1_0_0 ), .C1(\ram2e_ufm/SUM0_i_a3_4_0 ), - .B1(\ram2e_ufm/N_886 ), .A1(\ram2e_ufm/N_215 ), .D0(\CS[1] ), - .C0(\ram2e_ufm/SUM0_i_4 ), .B0(\ram2e_ufm/N_215 ), .A0(\CS[2] ), - .DI1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .DI0(N_547_i), - .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_547_i), .Q0(\CS[0] ), - .F1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .Q1(\CS[1] )); - SLICE_13 SLICE_13( .D1(\CS[2] ), .C1(\CS[1] ), .B1(\ram2e_ufm/N_234 ), - .A1(\ram2e_ufm/N_215 ), .D0(\ram2e_ufm/N_215 ), .C0(\CS[1] ), - .B0(\ram2e_ufm/N_234 ), .A0(\CS[2] ), - .DI0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), .LSR(un1_CS_0_sqmuxa_i), - .CLK(C14M_c), .F0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), .Q0(\CS[2] ), - .F1(\ram2e_ufm/SUM1_0_0 )); - SLICE_14 SLICE_14( .D1(\Din_c[3] ), .C1(\Din_c[5] ), .A1(\ram2e_ufm/N_800 ), - .D0(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ), .C0(\Din_c[1] ), - .B0(\ram2e_ufm/N_847 ), .A0(\Din_c[2] ), .DI0(CmdLEDGet_3), .CE(N_187_i), - .CLK(C14M_c), .F0(CmdLEDGet_3), .Q0(CmdLEDGet), .F1(\ram2e_ufm/N_847 )); - SLICE_15 SLICE_15( .D1(\Din_c[7] ), .B1(\CS[2] ), .A1(\Din_c[1] ), - .D0(\ram2e_ufm/N_883 ), .C0(\Din_c[4] ), .B0(\Din_c[7] ), .A0(\Din_c[1] ), - .DI0(CmdLEDSet_3), .CE(N_187_i), .CLK(C14M_c), .F0(CmdLEDSet_3), - .Q0(CmdLEDSet), .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 )); - SLICE_16 SLICE_16( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[3] ), - .A1(\Din_c[1] ), .D0(\ram2e_ufm/N_883 ), .C0(\Din_c[4] ), .B0(\Din_c[7] ), - .A0(\Din_c[1] ), .DI0(CmdRWMaskSet_3), .CE(N_187_i), .CLK(C14M_c), - .F0(CmdRWMaskSet_3), .Q0(CmdRWMaskSet), .F1(\ram2e_ufm/N_850 )); - SLICE_17 SLICE_17( .D1(\Din_c[2] ), .C1(\Din_c[0] ), .B1(\ram2e_ufm/N_847 ), - .D0(\Din_c[1] ), .C0(\ram2e_ufm/N_883 ), .B0(\Din_c[7] ), .A0(\Din_c[4] ), - .DI0(CmdSetRWBankFFLED_4), .CE(N_187_i), .CLK(C14M_c), - .F0(CmdSetRWBankFFLED_4), .Q0(CmdSetRWBankFFLED), .F1(\ram2e_ufm/N_883 )); - SLICE_18 SLICE_18( .D1(RWSel), .C1(CO0_0), .B1(\CmdTout[1] ), - .A1(\CmdTout[2] ), .D0(RWSel), .B0(CO0_0), .A0(\CmdTout[1] ), - .DI1(N_369_i), .DI0(N_368_i), .CE(N_185_i), .CLK(C14M_c), .F0(N_368_i), - .Q0(\CmdTout[1] ), .F1(N_369_i), .Q1(\CmdTout[2] )); - SLICE_19 SLICE_19( .C1(\CS[1] ), .B1(\CS[2] ), .B0(\RA[1] ), - .A0(\ram2e_ufm/N_186 ), .M0(\S[3] ), .LSR(N_1080_0), .CLK(C14M_c), - .F0(\ram2e_ufm/N_660 ), .Q0(DOEEN), .F1(\ram2e_ufm/N_193 )); - SLICE_20 SLICE_20( .D1(\ram2e_ufm/N_182 ), .C1(\Ain_c[1] ), - .B1(\ram2e_ufm/N_660 ), .A1(\ram2e_ufm/N_659 ), - .D0(\ram2e_ufm/RA_35_0_0_1[0] ), .C0(\ram2e_ufm/N_801 ), .B0(\FS[7] ), - .A0(\ram2e_ufm/N_684 ), .DI1(N_223), .DI0(\RA_35[0] ), .CE(N_126), - .CLK(C14M_c), .F0(\RA_35[0] ), .Q0(\RA[0] ), .F1(N_223), .Q1(\RA[1] )); - SLICE_21 SLICE_21( .D1(\ram2e_ufm/RA_35_0_0_0[3] ), .B1(\FS[10] ), - .A1(\ram2e_ufm/N_801 ), .D0(\ram2e_ufm/N_680 ), .C0(\ram2e_ufm/N_679 ), - .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[2] ), .DI1(\RA_35[3] ), - .DI0(\RA_35[2] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[2] ), .Q0(\RA[2] ), - .F1(\RA_35[3] ), .Q1(\RA[3] )); - SLICE_22 SLICE_22( .D1(\ram2e_ufm/N_182 ), .C1(\Ain_c[5] ), - .B1(\ram2e_ufm/RA_35_0_0_0[5] ), .A1(\ram2e_ufm/N_621 ), - .D0(\ram2e_ufm/RA_35_0_0_0[4] ), .C0(\FS[11] ), .A0(\ram2e_ufm/N_801 ), - .DI1(\RA_35[5] ), .DI0(\RA_35[4] ), .CE(N_126), .CLK(C14M_c), - .F0(\RA_35[4] ), .Q0(\RA[4] ), .F1(\RA_35[5] ), .Q1(\RA[5] )); - SLICE_23 SLICE_23( .C1(\ram2e_ufm/RA_35_0_0_0_0[7] ), .B1(\FS[14] ), - .A1(\ram2e_ufm/N_801 ), .C0(\ram2e_ufm/RA_35_0_0_0_0[6] ), .B0(\FS[13] ), - .A0(\ram2e_ufm/N_801 ), .DI1(\RA_35[7] ), .DI0(\RA_35[6] ), .CE(N_126), - .CLK(C14M_c), .F0(\RA_35[6] ), .Q0(\RA[6] ), .F1(\RA_35[7] ), .Q1(\RA[7] )); - SLICE_24 SLICE_24( .D1(\ram2e_ufm/N_242 ), .C1(\ram2e_ufm/RA_35_0_0_0[9] ), - .A1(\RA[9] ), .D0(\ram2e_ufm/N_699 ), .C0(\ram2e_ufm/N_221 ), - .B0(\ram2e_ufm/N_698 ), .A0(\RA[8] ), .DI1(\RA_35[9] ), - .DI0(un2_S_2_i_0_0_o3_RNIHFHN3), .CE(N_126), .CLK(C14M_c), - .F0(un2_S_2_i_0_0_o3_RNIHFHN3), .Q0(\RA[8] ), .F1(\RA_35[9] ), - .Q1(\RA[9] )); - SLICE_25 SLICE_25( .D1(\ram2e_ufm/N_845 ), .C1(\ram2e_ufm/N_242 ), - .B1(\RWBank[4] ), .A1(\RA[11] ), .D0(\ram2e_ufm/N_628 ), - .C0(\ram2e_ufm/N_627 ), .B0(\ram2e_ufm/N_624 ), - .A0(\ram2e_ufm/RA_35_2_0_0[10] ), .DI1(\RA_35[11] ), .DI0(\RA_35[10] ), - .CE(N_126), .CLK(C14M_c), .F0(\RA_35[10] ), .Q0(\RA[10] ), - .F1(\RA_35[11] ), .Q1(\RA[11] )); - SLICE_26 SLICE_26( .D1(CO0_1), .B1(\RC[1] ), .A1(\RC[2] ), .D0(\RC[2] ), - .B0(\RC[1] ), .A0(CO0_1), .DI1(\RC_3[2] ), .DI0(\RC_3[1] ), .CE(RC12), - .CLK(C14M_c), .F0(\RC_3[1] ), .Q0(\RC[1] ), .F1(\RC_3[2] ), .Q1(\RC[2] )); - SLICE_27 SLICE_27( .D1(\ram2e_ufm/N_188 ), .C1(\Din_c[1] ), - .B1(\ram2e_ufm/RWMask[1] ), .D0(\ram2e_ufm/N_188 ), .C0(\Din_c[0] ), - .B0(\ram2e_ufm/RWMask[0] ), .DI1(\RWBank_3[1] ), .DI0(\RWBank_3[0] ), - .CE(N_187_i), .CLK(C14M_c), .F0(\RWBank_3[0] ), .Q0(\RWBank[0] ), - .F1(\RWBank_3[1] ), .Q1(\RWBank[1] )); - SLICE_28 SLICE_28( .C1(\ram2e_ufm/RWMask[3] ), .B1(\Din_c[3] ), - .A1(\ram2e_ufm/N_188 ), .D0(\ram2e_ufm/RWMask[2] ), .B0(\Din_c[2] ), - .A0(\ram2e_ufm/N_188 ), .DI1(\RWBank_3[3] ), .DI0(\RWBank_3[2] ), - .CE(N_187_i), .CLK(C14M_c), .F0(\RWBank_3[2] ), .Q0(\RWBank[2] ), - .F1(\RWBank_3[3] ), .Q1(\RWBank[3] )); - SLICE_29 SLICE_29( .D1(\ram2e_ufm/N_188 ), .B1(\Din_c[5] ), - .A1(\ram2e_ufm/RWMask[5] ), .D0(\ram2e_ufm/N_188 ), .C0(\Din_c[4] ), - .A0(\ram2e_ufm/RWMask[4] ), .DI1(\RWBank_3[5] ), .DI0(\RWBank_3[4] ), - .CE(N_187_i), .CLK(C14M_c), .F0(\RWBank_3[4] ), .Q0(\RWBank[4] ), - .F1(\RWBank_3[5] ), .Q1(\RWBank[5] )); - SLICE_30 SLICE_30( .D1(\ram2e_ufm/N_188 ), .B1(\ram2e_ufm/RWMask[7] ), - .A1(\Din_c[7] ), .D0(\ram2e_ufm/N_188 ), .C0(\ram2e_ufm/RWMask[6] ), - .A0(\Din_c[6] ), .DI1(\RWBank_3[7] ), .DI0(\RWBank_3[6] ), .CE(N_187_i), - .CLK(C14M_c), .F0(\RWBank_3[6] ), .Q0(\RWBank[6] ), .F1(\RWBank_3[7] ), - .Q1(\RWBank[7] )); - SLICE_31 SLICE_31( .D1(\Ain_c[3] ), .C1(\RA[3] ), .B1(\ram2e_ufm/N_182 ), - .A1(\ram2e_ufm/N_186 ), .D0(\RA[0] ), .C0(nC07X_c), .B0(nWE_c), - .A0(\RA[3] ), .DI0(RWSel_2), .CE(un9_VOEEN_0_a2_0_a3_0_a3), .CLK(C14M_c), - .F0(RWSel_2), .Q0(RWSel), .F1(\ram2e_ufm/RA_35_0_0_0[3] )); - SLICE_32 SLICE_32( .D1(\ram2e_ufm/Ready3_0_a3_4 ), .C1(\ram2e_ufm/N_885 ), - .B1(\ram2e_ufm/Ready3_0_a3_5 ), .A1(\ram2e_ufm/Ready3_0_a3_3 ), - .C0(Ready3), .A0(Ready), .DI0(N_1026_0), .CLK(C14M_c), .F0(N_1026_0), - .Q0(Ready), .F1(Ready3)); - SLICE_33 SLICE_33( .D1(S_1), .C1(\ram2e_ufm/N_194 ), .B1(\ram2e_ufm/N_271 ), - .A1(\ram2e_ufm/S_r_i_0_o2[1] ), .D0(S_1), .C0(\ram2e_ufm/N_271 ), - .B0(\S[1] ), .A0(\ram2e_ufm/N_643 ), .DI1(N_362_i), .DI0(\S_s_0_0[0] ), - .CLK(C14M_c), .F0(\S_s_0_0[0] ), .Q0(\S[0] ), .F1(N_362_i), .Q1(\S[1] )); - SLICE_34 SLICE_34( .D1(S_1), .C1(\ram2e_ufm/N_194 ), .B1(\S[2] ), - .A1(\S[3] ), .D0(\S[3] ), .C0(\ram2e_ufm/N_194 ), .B0(S_1), .A0(\S[2] ), - .DI1(N_372_i), .DI0(N_361_i), .CLK(C14M_c), .F0(N_361_i), .Q0(\S[2] ), - .F1(N_372_i), .Q1(\S[3] )); - SLICE_35 SLICE_35( .D1(\S[0] ), .C1(N_551), .B1(\S[1] ), .A1(\FS[4] ), - .B0(\S[3] ), .A0(\S[2] ), .DI0(N_551), .LSR(N_1078_0), .CLK(C14M_c), - .F0(N_551), .Q0(VOEEN), .F1(BA_0_sqmuxa)); - SLICE_36 SLICE_36( .D1(\S[1] ), .C1(\ram2e_ufm/N_804 ), .B1(\S[0] ), - .A1(\ram2e_ufm/N_285_i ), .D0(nWE_c), .C0(\ram2e_ufm/N_872 ), - .B0(\ram2e_ufm/N_641 ), .A0(\ram2e_ufm/N_640 ), .DI0(N_370_i), - .CLK(C14M_c), .F0(N_370_i), .Q0(nCAS), .F1(\ram2e_ufm/N_872 )); - SLICE_37 SLICE_37( .D1(\S[1] ), .C1(\ram2e_ufm/N_285_i ), .B1(\S[0] ), - .A1(\ram2e_ufm/N_804 ), .D0(\ram2e_ufm/N_615 ), .C0(\ram2e_ufm/N_617 ), - .B0(\ram2e_ufm/N_616 ), .A0(\ram2e_ufm/nRAS_s_i_0_0 ), .DI0(N_358_i), - .CLK(C14M_c), .F0(N_358_i), .Q0(nRAS), .F1(\ram2e_ufm/N_617 )); - SLICE_38 SLICE_38( .D1(\ram2e_ufm/N_226 ), .C1(\ram2e_ufm/N_285_i ), - .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\S[2] ), .D0(\ram2e_ufm/N_804 ), - .C0(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ), .B0(\ram2e_ufm/N_615 ), - .A0(\ram2e_ufm/N_866 ), .DI0(N_359_i), .CLK(C14M_c), .F0(N_359_i), - .Q0(nRWE), .F1(\ram2e_ufm/N_615 )); - ram2e_ufm_SLICE_39 \ram2e_ufm/SLICE_39 ( .D1(\Din_c[0] ), .C1(\Din_c[3] ), - .B1(\Din_c[5] ), .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .D0(\Din_c[2] ), - .C0(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ), .B0(\ram2e_ufm/N_800 ), - .A0(\Din_c[1] ), .DI0(\ram2e_ufm/CmdBitbangMXO2_3 ), .CE(N_187_i), - .CLK(C14M_c), .F0(\ram2e_ufm/CmdBitbangMXO2_3 ), - .Q0(\ram2e_ufm/CmdBitbangMXO2 ), .F1(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 )); - ram2e_ufm_SLICE_40 \ram2e_ufm/SLICE_40 ( .D1(\Din_c[6] ), .C1(\CS[1] ), - .B1(\CS[2] ), .A1(\CS[0] ), .C0(\ram2e_ufm/N_800 ), .B0(\ram2e_ufm/N_851 ), - .DI0(\ram2e_ufm/CmdExecMXO2_3 ), .CE(N_187_i), .CLK(C14M_c), - .F0(\ram2e_ufm/CmdExecMXO2_3 ), .Q0(\ram2e_ufm/CmdExecMXO2 ), - .F1(\ram2e_ufm/N_800 )); - ram2e_ufm_SLICE_41 \ram2e_ufm/SLICE_41 ( .D1(\Din_c[1] ), .C1(\Din_c[2] ), - .B1(\Din_c[0] ), .A1(\Din_c[4] ), - .D0(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ), .C0(\ram2e_ufm/N_800 ), - .B0(\ram2e_ufm/N_190 ), .A0(\Din_c[7] ), - .DI0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .CE(N_187_i), .CLK(C14M_c), - .F0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .Q0(\ram2e_ufm/CmdSetRWBankFFChip ), - .F1(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 )); - ram2e_ufm_SLICE_42 \ram2e_ufm/SLICE_42 ( .D1(\Din_c[6] ), .C1(\Din_c[2] ), - .A1(\Din_c[0] ), .D0(\S[3] ), .C0(\ram2e_ufm/wb_dato[0] ), .A0(\Din_c[0] ), - .DI0(\ram2e_ufm/N_295 ), .CE(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_295 ), .Q0(\ram2e_ufm/LEDEN ), - .F1(\ram2e_ufm/N_212 )); - ram2e_ufm_SLICE_43 \ram2e_ufm/SLICE_43 ( .D1(\S[3] ), .C1(\Din_c[1] ), - .B1(\ram2e_ufm/wb_dato[1] ), .D0(\S[3] ), .B0(\ram2e_ufm/wb_dato[0] ), - .A0(\Din_c[0] ), .DI1(\ram2e_ufm/N_307_i ), .DI0(\ram2e_ufm/N_309_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_309_i ), .Q0(\ram2e_ufm/RWMask[0] ), - .F1(\ram2e_ufm/N_307_i ), .Q1(\ram2e_ufm/RWMask[1] )); - ram2e_ufm_SLICE_44 \ram2e_ufm/SLICE_44 ( .D1(\S[3] ), - .B1(\ram2e_ufm/wb_dato[3] ), .A1(\Din_c[3] ), .D0(\S[3] ), - .C0(\ram2e_ufm/wb_dato[2] ), .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_302_i ), - .DI0(\ram2e_ufm/N_304_i ), .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_304_i ), .Q0(\ram2e_ufm/RWMask[2] ), - .F1(\ram2e_ufm/N_302_i ), .Q1(\ram2e_ufm/RWMask[3] )); - ram2e_ufm_SLICE_45 \ram2e_ufm/SLICE_45 ( .D1(\S[3] ), - .C1(\ram2e_ufm/wb_dato[5] ), .B1(\Din_c[5] ), .D0(\S[3] ), - .C0(\ram2e_ufm/wb_dato[4] ), .A0(\Din_c[4] ), .DI1(\ram2e_ufm/N_301_i ), - .DI0(\ram2e_ufm/N_310_i ), .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_310_i ), .Q0(\ram2e_ufm/RWMask[4] ), - .F1(\ram2e_ufm/N_301_i ), .Q1(\ram2e_ufm/RWMask[5] )); - ram2e_ufm_SLICE_46 \ram2e_ufm/SLICE_46 ( .D1(\S[3] ), - .C1(\ram2e_ufm/wb_dato[7] ), .A1(\Din_c[7] ), .D0(\S[3] ), - .C0(\ram2e_ufm/wb_dato[6] ), .A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_296 ), - .DI0(\ram2e_ufm/N_300_i ), .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_300_i ), .Q0(\ram2e_ufm/RWMask[6] ), - .F1(\ram2e_ufm/N_296 ), .Q1(\ram2e_ufm/RWMask[7] )); - ram2e_ufm_SLICE_47 \ram2e_ufm/SLICE_47 ( .D1(\ram2e_ufm/wb_adr_7_5_41_0_1 ), - .C1(\Din_c[1] ), .B1(\ram2e_ufm/N_768 ), .A1(\S[2] ), - .D0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), - .B0(\ram2e_ufm/N_793 ), .A0(\FS[10] ), .DI1(\ram2e_ufm/wb_adr_RNO[1] ), - .DI0(\ram2e_ufm/wb_adr_7_i_i[0] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_adr_7_i_i[0] ), .Q0(\ram2e_ufm/wb_adr[0] ), - .F1(\ram2e_ufm/wb_adr_RNO[1] ), .Q1(\ram2e_ufm/wb_adr[1] )); - ram2e_ufm_SLICE_48 \ram2e_ufm/SLICE_48 ( .D1(\S[2] ), .B1(\Din_c[3] ), - .D0(\S[2] ), .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_268_i ), - .DI0(\ram2e_ufm/N_80_i ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_80_i ), .Q0(\ram2e_ufm/wb_adr[2] ), - .F1(\ram2e_ufm/N_268_i ), .Q1(\ram2e_ufm/wb_adr[3] )); - ram2e_ufm_SLICE_49 \ram2e_ufm/SLICE_49 ( .C1(\FS[14] ), .B1(\Din_c[5] ), - .A1(\S[2] ), .C0(\FS[14] ), .B0(\Din_c[4] ), .A0(\S[2] ), - .DI1(\ram2e_ufm/N_290 ), .DI0(\ram2e_ufm/N_294 ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_294 ), .Q0(\ram2e_ufm/wb_adr[4] ), .F1(\ram2e_ufm/N_290 ), - .Q1(\ram2e_ufm/wb_adr[5] )); - ram2e_ufm_SLICE_50 \ram2e_ufm/SLICE_50 ( .B1(\S[2] ), .A1(\Din_c[7] ), - .D0(\FS[14] ), .C0(\Din_c[6] ), .B0(\S[2] ), .DI1(\ram2e_ufm/N_267_i ), - .DI0(\ram2e_ufm/N_284 ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_284 ), .Q0(\ram2e_ufm/wb_adr[6] ), - .F1(\ram2e_ufm/N_267_i ), .Q1(\ram2e_ufm/wb_adr[7] )); - ram2e_ufm_SLICE_51 \ram2e_ufm/SLICE_51 ( .D1(\ram2e_ufm/wb_ack ), - .C1(\FS[14] ), .B1(\ram2e_ufm/N_336 ), .A1(\FS[0] ), .D0(\S[3] ), - .B0(\ram2e_ufm/N_687 ), .A0(\ram2e_ufm/CmdExecMXO2 ), - .DI0(\ram2e_ufm/wb_cyc_stb_RNO ), - .CE(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_cyc_stb_RNO ), .Q0(\ram2e_ufm/wb_cyc_stb ), - .F1(\ram2e_ufm/N_687 )); - ram2e_ufm_SLICE_52 \ram2e_ufm/SLICE_52 ( .D1(\ram2e_ufm/wb_dati_7_0_0_0[1] ), - .C1(\ram2e_ufm/N_611 ), .B1(\ram2e_ufm/N_793 ), .A1(\ram2e_ufm/N_849 ), - .D0(\ram2e_ufm/N_856 ), .C0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ), - .B0(\ram2e_ufm/wb_adr[0] ), .A0(\S[2] ), .DI1(\ram2e_ufm/wb_dati_7[1] ), - .DI0(\ram2e_ufm/wb_dati_7[0] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[0] ), .Q0(\ram2e_ufm/wb_dati[0] ), - .F1(\ram2e_ufm/wb_dati_7[1] ), .Q1(\ram2e_ufm/wb_dati[1] )); - ram2e_ufm_SLICE_53 \ram2e_ufm/SLICE_53 ( .D1(\ram2e_ufm/N_849 ), - .C1(\ram2e_ufm/N_611 ), .B1(\ram2e_ufm/N_783 ), - .A1(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .D0(\S[2] ), - .C0(\ram2e_ufm/wb_adr[2] ), .B0(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), - .A0(\ram2e_ufm/N_760 ), .DI1(\ram2e_ufm/wb_dati_7[3] ), - .DI0(\ram2e_ufm/wb_dati_7[2] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[2] ), .Q0(\ram2e_ufm/wb_dati[2] ), - .F1(\ram2e_ufm/wb_dati_7[3] ), .Q1(\ram2e_ufm/wb_dati[3] )); - ram2e_ufm_SLICE_54 \ram2e_ufm/SLICE_54 ( - .D1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C1(\ram2e_ufm/N_760 ), - .B1(\ram2e_ufm/wb_adr[5] ), .A1(\S[2] ), .D0(\ram2e_ufm/N_763 ), - .C0(\ram2e_ufm/N_760 ), .B0(\ram2e_ufm/N_757 ), - .A0(\ram2e_ufm/wb_dati_7_0_0_0[4] ), .DI1(\ram2e_ufm/wb_dati_7[5] ), - .DI0(\ram2e_ufm/wb_dati_7[4] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[4] ), .Q0(\ram2e_ufm/wb_dati[4] ), - .F1(\ram2e_ufm/wb_dati_7[5] ), .Q1(\ram2e_ufm/wb_dati[5] )); - ram2e_ufm_SLICE_55 \ram2e_ufm/SLICE_55 ( - .D1(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), .C1(\ram2e_ufm/N_604 ), - .B1(\ram2e_ufm/N_602 ), .A1(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), - .D0(\ram2e_ufm/N_757 ), .C0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), - .B0(\ram2e_ufm/N_849 ), .A0(\ram2e_ufm/N_793 ), - .DI1(\ram2e_ufm/wb_dati_7[7] ), .DI0(\ram2e_ufm/wb_dati_7[6] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_dati_7[6] ), .Q0(\ram2e_ufm/wb_dati[6] ), - .F1(\ram2e_ufm/wb_dati_7[7] ), .Q1(\ram2e_ufm/wb_dati[7] )); - ram2e_ufm_SLICE_56 \ram2e_ufm/SLICE_56 ( .D1(\S[3] ), .C1(\S[1] ), - .B1(\S[0] ), .A1(\FS[14] ), .D0(\FS[13] ), .C0(\FS[12] ), - .B0(\ram2e_ufm/wb_reqc_1 ), .A0(\FS[11] ), .DI0(\ram2e_ufm/wb_reqc_i ), - .CE(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ), .LSR(\S[2] ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_reqc_i ), .Q0(\ram2e_ufm/wb_req ), - .F1(\ram2e_ufm/wb_reqc_1 )); - ram2e_ufm_SLICE_57 \ram2e_ufm/SLICE_57 ( .D1(\FS[4] ), .C1(\FS[14] ), - .B1(\FS[2] ), .A1(\FS[15] ), .C0(\FS[14] ), .A0(\FS[15] ), - .DI0(\ram2e_ufm/wb_rst8 ), .LSR(\ram2e_ufm/wb_rst16_i ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_rst8 ), .Q0(\ram2e_ufm/wb_rst ), - .F1(\ram2e_ufm/Ready3_0_a3_4 )); - ram2e_ufm_SLICE_58 \ram2e_ufm/SLICE_58 ( .D1(\ram2e_ufm/N_799 ), - .C1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), .B1(\ram2e_ufm/N_885 ), - .A1(\FS[12] ), .D0(\ram2e_ufm/N_799 ), - .C0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ), .B0(\ram2e_ufm/N_208 ), - .A0(\FS[13] ), .DI0(\ram2e_ufm/wb_we_RNO ), .CE(\ram2e_ufm/wb_we_RNO_0 ), - .CLK(C14M_c), .F0(\ram2e_ufm/wb_we_RNO ), .Q0(\ram2e_ufm/wb_we ), - .F1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 )); - ram2e_ufm_SUM0_i_m3_0_SLICE_59 \ram2e_ufm/SUM0_i_m3_0/SLICE_59 ( - .D1(\Din_c[5] ), .C1(\CS[1] ), .B1(\Din_c[3] ), .D0(\Din_c[7] ), - .C0(\Din_c[5] ), .B0(\Din_c[3] ), .M0(\Din_c[1] ), - .OFX0(\ram2e_ufm/N_338 )); - ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60 ( - .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), .C1(\ram2e_ufm/N_193 ), - .B1(\CS[0] ), .A1(\Din_c[6] ), .C0(CO0_0), .B0(\CmdTout[2] ), - .A0(\CmdTout[1] ), .M0(RWSel), .OFX0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 )); - ram2e_ufm_CKE_7_SLICE_61 \ram2e_ufm/CKE_7/SLICE_61 ( .D1(\ram2e_ufm/N_821 ), - .C1(\ram2e_ufm/N_817 ), .A1(\RC[1] ), .D0(\ram2e_ufm/N_804 ), .B0(nWE_c), - .A0(\S[1] ), .M0(\ram2e_ufm/CKE_7_sm0 ), .OFX0(\ram2e_ufm/CKE_7 )); - ram2e_ufm_SLICE_62 \ram2e_ufm/SLICE_62 ( .D1(\Din_c[6] ), - .C1(\ram2e_ufm/N_851 ), .B1(\CS[2] ), .A1(\CS[1] ), .D0(\ram2e_ufm/N_234 ), - .C0(\ram2e_ufm/SUM0_i_a3_4_0 ), .B0(\CS[2] ), .A0(\CS[1] ), - .F0(\ram2e_ufm/N_720_tz ), .F1(\ram2e_ufm/SUM0_i_a3_4_0 )); - ram2e_ufm_SLICE_63 \ram2e_ufm/SLICE_63 ( .D1(\CS[2] ), - .C1(\ram2e_ufm/SUM0_i_0 ), .B1(\ram2e_ufm/N_350 ), .A1(\CS[0] ), - .D0(\CS[0] ), .C0(\ram2e_ufm/SUM0_i_3 ), .B0(\ram2e_ufm/SUM0_i_1 ), - .A0(\ram2e_ufm/N_187 ), .F0(\ram2e_ufm/SUM0_i_4 ), - .F1(\ram2e_ufm/SUM0_i_1 )); - ram2e_ufm_SLICE_64 \ram2e_ufm/SLICE_64 ( .D1(\ram2e_ufm/N_793 ), - .C1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[11] ), .C0(\ram2e_ufm/N_856 ), - .B0(\FS[13] ), .A0(\ram2e_ufm/N_755 ), .F0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), - .F1(\ram2e_ufm/N_755 )); - ram2e_ufm_SLICE_65 \ram2e_ufm/SLICE_65 ( .D1(\ram2e_ufm/N_193 ), - .C1(\Din_c[0] ), .B1(\CS[0] ), .A1(\Din_c[6] ), .D0(\ram2e_ufm/N_345 ), - .C0(\ram2e_ufm/N_735 ), .B0(\CS[0] ), .A0(\CS[1] ), - .F0(\ram2e_ufm/SUM0_i_0 ), .F1(\ram2e_ufm/N_735 )); - ram2e_ufm_SLICE_66 \ram2e_ufm/SLICE_66 ( .D1(\FS[14] ), - .C1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), - .B1(\ram2e_ufm/N_777 ), .A1(\ram2e_ufm/wb_ack ), - .D0(\ram2e_ufm/CmdExecMXO2 ), .C0(\ram2e_ufm/wb_ack ), - .B0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ), - .A0(\ram2e_ufm/N_187 ), - .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), - .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] )); - ram2e_ufm_SLICE_67 \ram2e_ufm/SLICE_67 ( .D1(\FS[1] ), .B1(\FS[2] ), - .A1(\FS[3] ), .D0(\S[1] ), .C0(\FS[4] ), .B0(\ram2e_ufm/N_250 ), - .A0(\FS[3] ), .F0(\ram2e_ufm/N_256 ), .F1(\ram2e_ufm/N_250 )); - ram2e_ufm_SLICE_68 \ram2e_ufm/SLICE_68 ( .D1(\ram2e_ufm/N_783 ), - .C1(\FS[8] ), .B1(\FS[9] ), .A1(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), - .D0(\FS[10] ), .C0(\FS[12] ), .B0(\FS[8] ), .A0(\FS[11] ), - .F0(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .F1(\ram2e_ufm/wb_adr_7_i_i_3[0] )); - ram2e_ufm_SLICE_69 \ram2e_ufm/SLICE_69 ( .D1(\FS[0] ), .C1(\FS[15] ), - .B1(\ram2e_ufm/wb_rst16_i ), .A1(\ram2e_ufm/N_254 ), .D0(\S[2] ), - .C0(\S[3] ), .B0(\S[0] ), .A0(\S[1] ), .F0(\ram2e_ufm/wb_rst16_i ), - .F1(\ram2e_ufm/N_641 )); - ram2e_ufm_SLICE_70 \ram2e_ufm/SLICE_70 ( .C1(\FS[14] ), .B1(\FS[8] ), - .A1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/N_876 ), .C0(\ram2e_ufm/N_807 ), - .B0(\FS[13] ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_604 ), - .F1(\ram2e_ufm/N_807 )); - ram2e_ufm_SLICE_71 \ram2e_ufm/SLICE_71 ( .C1(\ram2e_ufm/N_784 ), - .B1(\FS[4] ), .A1(\FS[3] ), .D0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), - .F0(\ram2e_ufm/N_784 ), .F1(\ram2e_ufm/N_801 )); - ram2e_ufm_SLICE_72 \ram2e_ufm/SLICE_72 ( .D1(\S[0] ), .C1(\ram2e_ufm/N_560 ), - .B1(\RWBank[5] ), .A1(\FS[4] ), .D0(\S[2] ), .B0(\S[3] ), .A0(\S[1] ), - .F0(\ram2e_ufm/N_560 ), .F1(\BA_4[0] )); - ram2e_ufm_SLICE_73 \ram2e_ufm/SLICE_73 ( .D1(\ram2e_ufm/N_184 ), - .C1(\ram2e_ufm/N_611 ), .B1(\ram2e_ufm/N_873 ), .A1(\ram2e_ufm/N_781 ), - .D0(\FS[10] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[11] ), - .F0(\ram2e_ufm/N_873 ), .F1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] )); - ram2e_ufm_SLICE_74 \ram2e_ufm/SLICE_74 ( .C1(\ram2e_ufm/N_845 ), - .B1(\ram2e_ufm/N_625 ), .A1(\RWBank[3] ), .D0(\S[2] ), .C0(\S[0] ), - .B0(\S[3] ), .A0(\S[1] ), .F0(\ram2e_ufm/N_845 ), - .F1(\ram2e_ufm/RA_35_2_0_0[10] )); - ram2e_ufm_SLICE_75 \ram2e_ufm/SLICE_75 ( .D1(\FS[10] ), .B1(\FS[9] ), - .A1(\FS[11] ), .D0(\FS[13] ), .C0(\ram2e_ufm/wb_ack ), - .B0(\ram2e_ufm/N_876 ), .A0(\FS[12] ), - .F0(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), - .F1(\ram2e_ufm/N_876 )); - ram2e_ufm_SLICE_76 \ram2e_ufm/SLICE_76 ( .D1(\FS[10] ), .C1(\FS[11] ), - .D0(\FS[12] ), .C0(\ram2e_ufm/N_811 ), .B0(\FS[13] ), - .A0(\ram2e_ufm/N_206 ), .F0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), - .F1(\ram2e_ufm/N_811 )); - ram2e_ufm_SLICE_77 \ram2e_ufm/SLICE_77 ( .C1(\ram2e_ufm/N_185 ), .B1(RWSel), - .A1(\CS[0] ), .D0(\S[3] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[0] ), - .F0(\ram2e_ufm/N_185 ), .F1(\ram2e_ufm/N_215 )); - ram2e_ufm_SLICE_78 \ram2e_ufm/SLICE_78 ( .D1(\S[0] ), .B1(\S[1] ), - .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\RWBank[1] ), .B0(\S[3] ), .A0(\S[2] ), - .F0(\ram2e_ufm/N_699 ), .F1(\ram2e_ufm/S_r_i_0_o2[1] )); - ram2e_ufm_SLICE_79 \ram2e_ufm/SLICE_79 ( .D1(CmdLEDSet), - .C1(\ram2e_ufm/N_187 ), .B1(\ram2e_ufm/N_807 ), - .A1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), .D0(\S[2] ), - .C0(RWSel), .B0(\ram2e_ufm/S_r_i_0_o2[1] ), .A0(\S[3] ), - .F0(\ram2e_ufm/N_187 ), .F1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] )); - ram2e_ufm_SLICE_80 \ram2e_ufm/SLICE_80 ( .D1(\S[1] ), .C1(\S[0] ), - .B1(\FS[15] ), .A1(N_551), .D0(\ram2e_ufm/CmdBitbangMXO2 ), - .C0(\ram2e_ufm/N_777 ), .B0(RWSel), .A0(\ram2e_ufm/N_185 ), - .F0(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .F1(\ram2e_ufm/N_777 )); - ram2e_ufm_SLICE_81 \ram2e_ufm/SLICE_81 ( .D1(\FS[14] ), .C1(\FS[9] ), - .B1(\FS[8] ), .A1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/N_811 ), - .C0(\FS[12] ), .B0(\ram2e_ufm/N_856 ), .A0(\FS[13] ), - .F0(\ram2e_ufm/N_757 ), .F1(\ram2e_ufm/N_856 )); - ram2e_ufm_SLICE_82 \ram2e_ufm/SLICE_82 ( .D1(\Din_c[6] ), - .C1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .B1(\CS[0] ), - .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ), - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ), - .C0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), - .B0(\ram2e_ufm/N_185 ), .A0(\ram2e_ufm/N_637 ), .F0(un1_CS_0_sqmuxa_i), - .F1(\ram2e_ufm/N_637 )); - ram2e_ufm_SLICE_83 \ram2e_ufm/SLICE_83 ( .D1(\Din_c[6] ), .B1(\CS[2] ), - .A1(\ram2e_ufm/N_851 ), .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ), - .C0(\ram2e_ufm/N_592 ), .B0(RWSel), .A0(\CS[0] ), - .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 )); - ram2e_ufm_SLICE_84 \ram2e_ufm/SLICE_84 ( .D1(\CS[2] ), - .C1(\ram2e_ufm/N_212 ), .B1(\ram2e_ufm/N_850 ), .A1(\Din_c[4] ), - .D0(\ram2e_ufm/N_720_tz ), .C0(\ram2e_ufm/N_187 ), .B0(\ram2e_ufm/N_886 ), - .A0(\CS[1] ), .F0(\ram2e_ufm/SUM0_i_3 ), .F1(\ram2e_ufm/N_886 )); - ram2e_ufm_SLICE_85 \ram2e_ufm/SLICE_85 ( .D1(\FS[13] ), .C1(\FS[12] ), - .B1(\FS[14] ), .A1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/N_187 ), - .C0(\ram2e_ufm/N_793 ), - .B0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), .A0(CmdRWMaskSet), - .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .F1(\ram2e_ufm/N_793 )); - ram2e_ufm_SLICE_86 \ram2e_ufm/SLICE_86 ( .D1(\Din_c[0] ), .A1(\S[2] ), - .D0(\ram2e_ufm/N_634 ), .C0(\ram2e_ufm/N_753 ), - .B0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), .A0(\ram2e_ufm/wb_adr_7_i_i_3[0] ), - .F0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), .F1(\ram2e_ufm/N_634 )); - ram2e_ufm_SLICE_87 \ram2e_ufm/SLICE_87 ( - .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C1(\Din_c[1] ), - .B1(\ram2e_ufm/N_190 ), .A1(\ram2e_ufm/N_212 ), .D0(\ram2e_ufm/N_886 ), - .C0(\ram2e_ufm/N_234 ), .B0(\CS[1] ), .F0(\ram2e_ufm/N_592 ), - .F1(\ram2e_ufm/N_234 )); - ram2e_ufm_SLICE_88 \ram2e_ufm/SLICE_88 ( .D1(\FS[10] ), .B1(\FS[11] ), - .D0(\ram2e_ufm/N_793 ), .C0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), - .B0(\ram2e_ufm/N_206 ), .A0(\ram2e_ufm/N_876 ), - .F0(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] )); - ram2e_ufm_SLICE_89 \ram2e_ufm/SLICE_89 ( .D1(\FS[13] ), .C1(\FS[14] ), - .A1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), - .C0(\ram2e_ufm/N_783 ), .B0(\S[2] ), .A0(\ram2e_ufm/wb_adr[3] ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .F1(\ram2e_ufm/N_783 )); - ram2e_ufm_SLICE_90 \ram2e_ufm/SLICE_90 ( .D1(\ram2e_ufm/N_206 ), - .C1(\FS[10] ), .B1(\FS[11] ), .A1(\FS[12] ), .D0(\ram2e_ufm/wb_adr[6] ), - .C0(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ), .B0(\S[2] ), - .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] )); - ram2e_ufm_SLICE_91 \ram2e_ufm/SLICE_91 ( .D1(\RC[2] ), .C1(\RC[1] ), - .B1(CO0_1), .A1(\ram2e_ufm/N_817 ), .D0(\ram2e_ufm/N_784 ), - .C0(\ram2e_ufm/N_890 ), .B0(\ram2e_ufm/N_285_i ), .A0(\ram2e_ufm/N_256 ), - .F0(\ram2e_ufm/nRAS_s_i_0_0 ), .F1(\ram2e_ufm/N_890 )); - ram2e_ufm_SLICE_92 \ram2e_ufm/SLICE_92 ( .D1(nWE_c), .C1(\ram2e_ufm/N_804 ), - .B1(\S[1] ), .A1(N_551), .D0(\S[0] ), .C0(\ram2e_ufm/N_890 ), - .B0(\ram2e_ufm/N_220 ), .A0(\ram2e_ufm/N_285_i ), .F0(\ram2e_ufm/N_640 ), - .F1(\ram2e_ufm/N_220 )); - ram2e_ufm_SLICE_93 \ram2e_ufm/SLICE_93 ( .D1(\FS[8] ), .C1(\FS[9] ), - .B1(\FS[10] ), .A1(\FS[11] ), .D0(\ram2e_ufm/N_196 ), - .B0(\ram2e_ufm/N_783 ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_760 ), - .F1(\ram2e_ufm/N_196 )); - ram2e_ufm_SLICE_94 \ram2e_ufm/SLICE_94 ( .C1(\Din_c[4] ), .B1(\Din_c[7] ), - .D0(\ram2e_ufm/N_243 ), .C0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), - .B0(\Din_c[0] ), .A0(\CS[2] ), .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 )); - ram2e_ufm_SLICE_95 \ram2e_ufm/SLICE_95 ( .D1(\S[1] ), .C1(\S[3] ), - .B1(\S[0] ), .A1(\S[2] ), .D0(\RA[4] ), .C0(\ram2e_ufm/N_182 ), - .B0(\Ain_c[4] ), .A0(\ram2e_ufm/N_186 ), .F0(\ram2e_ufm/RA_35_0_0_0[4] ), - .F1(\ram2e_ufm/N_182 )); - ram2e_ufm_SLICE_96 \ram2e_ufm/SLICE_96 ( .D1(\S[1] ), .C1(\S[2] ), - .B1(\S[0] ), .A1(\S[3] ), .D0(\ram2e_ufm/N_182 ), .C0(\ram2e_ufm/N_186 ), - .B0(\Ain_c[6] ), .A0(\RA[6] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[6] ), - .F1(\ram2e_ufm/N_186 )); - ram2e_ufm_SLICE_97 \ram2e_ufm/SLICE_97 ( .D1(\ram2e_ufm/N_873 ), - .C1(\FS[13] ), .B1(\FS[12] ), .D0(\ram2e_ufm/wb_adr[1] ), - .C0(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ), .B0(\ram2e_ufm/N_781 ), - .A0(\S[2] ), .F0(\ram2e_ufm/wb_dati_7_0_0_0[1] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] )); - ram2e_ufm_SLICE_98 \ram2e_ufm/SLICE_98 ( .D1(\FS[14] ), - .C1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), - .C0(\ram2e_ufm/N_781 ), .B0(\ram2e_ufm/wb_adr[7] ), .A0(\S[2] ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), .F1(\ram2e_ufm/N_781 )); - ram2e_ufm_SLICE_99 \ram2e_ufm/SLICE_99 ( .D1(\FS[11] ), .C1(\FS[8] ), - .A1(\FS[10] ), .D0(\ram2e_ufm/N_565 ), - .C0(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ), .B0(\FS[12] ), - .A0(\ram2e_ufm/N_781 ), .F0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), - .F1(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] )); - ram2e_ufm_SLICE_100 \ram2e_ufm/SLICE_100 ( .D1(\Din_c[1] ), .C1(\Din_c[5] ), - .B1(\Din_c[3] ), .A1(\Din_c[2] ), .D0(\Din_c[7] ), .C0(\CS[2] ), - .B0(\ram2e_ufm/N_243 ), .A0(\Din_c[4] ), .F0(\ram2e_ufm/N_345 ), - .F1(\ram2e_ufm/N_243 )); - ram2e_ufm_SLICE_101 \ram2e_ufm/SLICE_101 ( .C1(\Din_c[5] ), .B1(\Din_c[3] ), - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ), .C0(\CS[1] ), - .B0(\ram2e_ufm/N_850 ), .A0(\ram2e_ufm/N_190 ), - .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .F1(\ram2e_ufm/N_190 )); - ram2e_ufm_SLICE_102 \ram2e_ufm/SLICE_102 ( .C1(\S[1] ), .B1(\S[3] ), - .A1(\S[2] ), .D0(\ram2e_ufm/N_817 ), .C0(\ram2e_ufm/CKE_7s2_0_0_0 ), - .B0(\ram2e_ufm/N_220 ), .F0(\ram2e_ufm/CKE_7_sm0 ), .F1(\ram2e_ufm/N_817 )); - ram2e_ufm_SLICE_103 \ram2e_ufm/SLICE_103 ( .D1(\FS[13] ), .C1(\FS[12] ), - .D0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), .C0(\ram2e_ufm/N_184 ), - .B0(\ram2e_ufm/N_204 ), .A0(\ram2e_ufm/N_799 ), - .F0(\ram2e_ufm/wb_adr_7_5_41_0_1 ), .F1(\ram2e_ufm/N_184 )); - ram2e_ufm_SLICE_104 \ram2e_ufm/SLICE_104 ( .D1(\FS[8] ), .C1(\FS[10] ), - .B1(\FS[9] ), .A1(\FS[11] ), .C0(\ram2e_ufm/N_595 ), .A0(\FS[12] ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .F1(\ram2e_ufm/N_595 )); - ram2e_ufm_SLICE_105 \ram2e_ufm/SLICE_105 ( .D1(\ram2e_ufm/nRWE_s_i_0_63_1 ), - .C1(\ram2e_ufm/N_285_i ), .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\S[3] ), - .D0(\FS[0] ), .C0(\ram2e_ufm/wb_rst16_i ), .A0(\FS[15] ), - .F0(\ram2e_ufm/N_285_i ), .F1(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] )); - ram2e_ufm_SLICE_106 \ram2e_ufm/SLICE_106 ( .C1(\S[0] ), .B1(\S[1] ), - .D0(\RA[10] ), .C0(\S[2] ), .B0(\ram2e_ufm/N_194 ), - .A0(\ram2e_ufm/S_r_i_0_o2[1] ), .F0(\ram2e_ufm/N_624 ), - .F1(\ram2e_ufm/N_194 )); - ram2e_ufm_SLICE_107 \ram2e_ufm/SLICE_107 ( .D1(\S[3] ), .C1(\S[2] ), - .B1(\S[0] ), .A1(\FS[4] ), .D0(\FS[5] ), .C0(\FS[3] ), .B0(\FS[8] ), - .A0(\ram2e_ufm/N_792 ), .F0(\ram2e_ufm/N_659 ), .F1(\ram2e_ufm/N_792 )); - ram2e_ufm_SLICE_108 \ram2e_ufm/SLICE_108 ( .D1(\FS[7] ), - .C1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ), .B1(\FS[4] ), - .A1(\FS[5] ), .D0(\ram2e_ufm/wb_req ), .C0(\ram2e_ufm/N_336 ), - .B0(\FS[0] ), .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), - .F1(\ram2e_ufm/N_336 )); - ram2e_ufm_SLICE_109 \ram2e_ufm/SLICE_109 ( .C1(\FS[14] ), .B1(\S[2] ), - .D0(\ram2e_ufm/N_799 ), .C0(\FS[11] ), .B0(\ram2e_ufm/N_184 ), - .A0(\ram2e_ufm/N_634 ), .F0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), - .F1(\ram2e_ufm/N_799 )); - ram2e_ufm_SLICE_110 \ram2e_ufm/SLICE_110 ( .D1(\FS[9] ), .C1(\FS[8] ), - .B1(\FS[10] ), .A1(\FS[11] ), .C0(\ram2e_ufm/wb_ack ), - .B0(\ram2e_ufm/N_885 ), - .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), - .F1(\ram2e_ufm/N_885 )); - ram2e_ufm_SLICE_111 \ram2e_ufm/SLICE_111 ( .D1(\FS[12] ), - .C1(\ram2e_ufm/N_807 ), .A1(\ram2e_ufm/N_553 ), .D0(\FS[13] ), - .C0(\ram2e_ufm/N_811 ), .B0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), - .A0(\FS[9] ), .F0(\ram2e_ufm/N_553 ), .F1(\ram2e_ufm/N_611 )); - ram2e_ufm_SLICE_112 \ram2e_ufm/SLICE_112 ( .D1(\S[1] ), - .C1(\ram2e_ufm/N_285_i ), .B1(\S[0] ), .D0(nWE_c), .C0(\ram2e_ufm/N_866 ), - .B0(nEN80_c), .A0(\S[2] ), .F0(\ram2e_ufm/N_616 ), .F1(\ram2e_ufm/N_866 )); - ram2e_ufm_SLICE_113 \ram2e_ufm/SLICE_113 ( .D1(nEN80_c), .C1(\S[2] ), - .B1(\S[3] ), .D0(nWE_c), .C0(\ram2e_ufm/N_804 ), .B0(\S[0] ), .A0(\S[1] ), - .F0(\ram2e_ufm/N_628 ), .F1(\ram2e_ufm/N_804 )); - ram2e_ufm_SLICE_114 \ram2e_ufm/SLICE_114 ( .D1(\FS[10] ), .C1(\FS[8] ), - .B1(\FS[9] ), .D0(\FS[11] ), .C0(\ram2e_ufm/N_799 ), .B0(\FS[12] ), - .A0(\ram2e_ufm/N_241_i ), .F0(\ram2e_ufm/N_768 ), .F1(\ram2e_ufm/N_241_i )); - ram2e_ufm_SLICE_115 \ram2e_ufm/SLICE_115 ( .D1(\S[1] ), .B1(\S[2] ), - .D0(\S[0] ), .C0(\ram2e_ufm/N_221 ), .B0(nEN80_c), .A0(\S[3] ), - .F0(\ram2e_ufm/CKE_7s2_0_0_0 ), .F1(\ram2e_ufm/N_221 )); - ram2e_ufm_SLICE_116 \ram2e_ufm/SLICE_116 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ), - .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .A1(\ram2e_ufm/N_814 ), - .D0(\Din_c[0] ), .B0(\Din_c[1] ), .A0(\Din_c[2] ), .F0(\ram2e_ufm/N_814 ), - .F1(\ram2e_ufm/N_851 )); - ram2e_ufm_SLICE_117 \ram2e_ufm/SLICE_117 ( .D1(\S[1] ), .C1(\S[0] ), - .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[0] ), .B0(\S[3] ), - .A0(\S[2] ), .F0(N_225_i), .F1(\ram2e_ufm/N_643 )); - ram2e_ufm_SLICE_118 \ram2e_ufm/SLICE_118 ( .D1(\S[2] ), .C1(\S[1] ), - .B1(\S[0] ), .A1(\S[3] ), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[0] ), - .A0(\S[3] ), .F0(N_201_i), .F1(RC12)); - ram2e_ufm_SLICE_119 \ram2e_ufm/SLICE_119 ( .D1(\S[0] ), .C1(\S[1] ), - .B1(\S[3] ), .A1(\S[2] ), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[3] ), - .A0(\S[2] ), .F0(N_126), .F1(N_185_i)); - ram2e_ufm_SLICE_120 \ram2e_ufm/SLICE_120 ( .D1(\S[0] ), .C1(\FS[15] ), - .B1(\S[3] ), .A1(\RWBank[0] ), .D0(\S[0] ), .C0(\FS[15] ), .B0(\S[3] ), - .A0(\RWBank[0] ), .F0(N_507_i), .F1(N_508)); - ram2e_ufm_SLICE_121 \ram2e_ufm/SLICE_121 ( .D1(\S[1] ), .C1(\S[3] ), - .B1(\S[2] ), .A1(\S[0] ), .D0(\S[1] ), .C0(\S[3] ), .B0(\S[2] ), - .A0(\S[0] ), .F0(\ram2e_ufm/N_242 ), .F1(Vout3)); - ram2e_ufm_SLICE_122 \ram2e_ufm/SLICE_122 ( .D1(\FS[1] ), .C1(\FS[4] ), - .B1(\FS[2] ), .A1(\FS[3] ), .D0(\FS[1] ), .C0(\FS[4] ), .B0(\FS[2] ), - .A0(\FS[3] ), .F0(\ram2e_ufm/N_254 ), .F1(\ram2e_ufm/nRWE_s_i_0_63_1 )); - ram2e_ufm_SLICE_123 \ram2e_ufm/SLICE_123 ( .D1(\FS[11] ), .C1(\FS[8] ), - .B1(\FS[9] ), .D0(\FS[11] ), .C0(\FS[8] ), .B0(\FS[9] ), .A0(\FS[10] ), - .F0(\ram2e_ufm/N_849 ), .F1(\ram2e_ufm/N_204 )); - ram2e_ufm_SLICE_124 \ram2e_ufm/SLICE_124 ( .D1(\FS[12] ), - .C1(\ram2e_ufm/N_784 ), .B1(\FS[4] ), .A1(\FS[3] ), .D0(\ram2e_ufm/N_784 ), - .C0(\FS[1] ), .B0(\FS[4] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_684 ), - .F1(\ram2e_ufm/RA_35_0_0_0[5] )); - ram2e_ufm_SLICE_125 \ram2e_ufm/SLICE_125 ( .D1(\FS[13] ), .C1(\FS[8] ), - .B1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[9] ), .C0(\ram2e_ufm/N_793 ), - .B0(\FS[11] ), .A0(\FS[8] ), .F0(\ram2e_ufm/N_763 ), - .F1(\ram2e_ufm/N_565 )); - ram2e_ufm_SLICE_126 \ram2e_ufm/SLICE_126 ( .D1(\FS[10] ), .C1(\FS[12] ), - .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[10] ), .C0(\ram2e_ufm/N_781 ), - .B0(\FS[9] ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_753 ), - .F1(\ram2e_ufm/N_208 )); - ram2e_ufm_SLICE_127 \ram2e_ufm/SLICE_127 ( .D1(\S[0] ), .C1(\S[1] ), - .B1(\S[3] ), .A1(\S[2] ), .D0(\S[0] ), .C0(\RWBank[7] ), .B0(\S[3] ), - .A0(\S[2] ), .F0(\ram2e_ufm/N_698 ), .F1(un9_VOEEN_0_a2_0_a3_0_a3)); - ram2e_ufm_SLICE_128 \ram2e_ufm/SLICE_128 ( .D1(\FS[13] ), .C1(\FS[11] ), - .B1(\FS[12] ), .A1(\FS[10] ), .D0(\FS[13] ), .C0(\FS[12] ), .A0(\FS[10] ), - .F0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), - .F1(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] )); - ram2e_ufm_SLICE_129 \ram2e_ufm/SLICE_129 ( .D1(\RWBank[6] ), .C1(\S[0] ), - .B1(\FS[4] ), .A1(\ram2e_ufm/N_560 ), .D0(N_551), .C0(\S[0] ), - .B0(\FS[4] ), .A0(\FS[1] ), .F0(\ram2e_ufm/N_627 ), .F1(\BA_4[1] )); - ram2e_ufm_SLICE_130 \ram2e_ufm/SLICE_130 ( .D1(\ram2e_ufm/N_185 ), - .C1(RWSel), .D0(\ram2e_ufm/N_185 ), .C0(RWSel), .B0(\ram2e_ufm/N_777 ), - .A0(\ram2e_ufm/CmdExecMXO2 ), .F0(\ram2e_ufm/wb_we_RNO_0 ), .F1(N_187_i)); - ram2e_ufm_SLICE_131 \ram2e_ufm/SLICE_131 ( .D1(\FS[13] ), .C1(\FS[12] ), - .B1(\FS[1] ), .A1(\FS[3] ), .D0(\FS[13] ), .C0(\ram2e_ufm/N_856 ), - .B0(\ram2e_ufm/N_811 ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_602 ), - .F1(\ram2e_ufm/Ready3_0_a3_5 )); - ram2e_ufm_SLICE_132 \ram2e_ufm/SLICE_132 ( .D1(\ram2e_ufm/N_182 ), - .C1(\Ain_c[0] ), .B1(\ram2e_ufm/N_186 ), .A1(\RA[0] ), - .D0(\ram2e_ufm/N_182 ), .C0(\Ain_c[7] ), .B0(\ram2e_ufm/N_186 ), - .A0(\RA[7] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[7] ), - .F1(\ram2e_ufm/RA_35_0_0_1[0] )); - ram2e_ufm_SLICE_133 \ram2e_ufm/SLICE_133 ( .D1(\Din_c[0] ), .C1(\Din_c[2] ), - .B1(RWSel), .A1(\Din_c[4] ), .D0(\ram2e_ufm/N_338 ), .C0(\Din_c[2] ), - .B0(\Din_c[4] ), .F0(\ram2e_ufm/N_350 ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 )); - ram2e_ufm_SLICE_134 \ram2e_ufm/SLICE_134 ( .D1(\FS[3] ), .C1(\FS[6] ), - .B1(\FS[1] ), .A1(\FS[2] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[9] ), - .B0(\FS[3] ), .A0(\FS[6] ), .F0(\ram2e_ufm/N_679 ), - .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] )); - ram2e_ufm_SLICE_135 \ram2e_ufm/SLICE_135 ( .C1(\S[3] ), .A1(\S[2] ), - .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[3] ), .B0(nEN80_c), .A0(\S[2] ), - .F0(\ram2e_ufm/N_625 ), .F1(\ram2e_ufm/N_271 )); - ram2e_ufm_SLICE_136 \ram2e_ufm/SLICE_136 ( .C1(nWE_c), .B1(\S[3] ), - .A1(nEN80_c), .D0(DOEEN), .B0(nWE_c), .A0(nEN80_c), .F0(nDOE_c), - .F1(\ram2e_ufm/N_226 )); - ram2e_ufm_SLICE_137 \ram2e_ufm/SLICE_137 ( .C1(Ready), .B1(nWE_c), - .A1(nEN80_c), .C0(Ready), .B0(\ram2e_ufm/LEDEN ), .A0(nEN80_c), .F0(LED_c), - .F1(RDOE_i)); - SLICE_138 SLICE_138( .D1(\S[1] ), .B1(\S[3] ), .A1(\S[0] ), .D0(\S[1] ), - .B0(\S[0] ), .A0(\S[2] ), .F0(N_1080_0), .F1(N_1078_0)); - SLICE_139 SLICE_139( .B1(PHI1_c), .A1(VOEEN), .C0(PHI1r), .B0(Ready), - .A0(PHI1_c), .F0(S_1), .F1(nVOE_c)); - ram2e_ufm_SLICE_140 \ram2e_ufm/SLICE_140 ( .B1(\RA[2] ), - .A1(\ram2e_ufm/N_186 ), .C0(\RA[5] ), .A0(\ram2e_ufm/N_186 ), - .F0(\ram2e_ufm/N_621 ), .F1(\ram2e_ufm/N_680 )); - ram2e_ufm_SLICE_141 \ram2e_ufm/SLICE_141 ( .D1(Ready), .B1(\Din_c[0] ), - .D0(Ready), .A0(\Din_c[3] ), .F0(N_263_i), .F1(N_667)); - ram2e_ufm_SLICE_142 \ram2e_ufm/SLICE_142 ( .D1(\Din_c[4] ), .C1(\Din_c[7] ), - .A1(\Din_c[0] ), .D0(\Din_c[4] ), .C0(Ready), .F0(N_648), - .F1(\ram2e_ufm/CmdLEDGet_3_0_a3_1 )); - ram2e_ufm_SLICE_143 \ram2e_ufm/SLICE_143 ( .D1(Ready), .C1(\Din_c[1] ), - .D0(Ready), .B0(\Din_c[7] ), .F0(N_662), .F1(N_666)); - ram2e_ufm_SLICE_144 \ram2e_ufm/SLICE_144 ( .C1(\Din_c[2] ), .A1(Ready), - .B0(\Din_c[6] ), .A0(Ready), .F0(N_663), .F1(N_665)); - ram2e_ufm_SLICE_145 \ram2e_ufm/SLICE_145 ( .D1(\ram2e_ufm/N_783 ), - .C1(\ram2e_ufm/N_873 ), .B1(\ram2e_ufm/wb_adr[4] ), .A1(\S[2] ), - .D0(\FS[8] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_206 ), - .F1(\ram2e_ufm/wb_dati_7_0_0_0[4] )); - ram2e_ufm_SLICE_146 \ram2e_ufm/SLICE_146 ( .D1(\ram2e_ufm/N_845 ), - .C1(\RWBank[2] ), .B1(\ram2e_ufm/N_784 ), .A1(\FS[4] ), .D0(\FS[7] ), - .C0(\FS[0] ), .B0(\FS[6] ), .A0(\FS[5] ), .F0(\ram2e_ufm/Ready3_0_a3_3 ), - .F1(\ram2e_ufm/RA_35_0_0_0[9] )); - ram2e_ufm_SLICE_147 \ram2e_ufm/SLICE_147 ( .D1(CmdSetRWBankFFLED), - .C1(\ram2e_ufm/LEDEN ), .B1(CmdLEDGet), - .A1(\ram2e_ufm/CmdSetRWBankFFChip ), .C0(Ready), .B0(\Din_c[5] ), - .F0(N_664), .F1(\ram2e_ufm/N_188 )); - RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(N_667), - .RD0(RD[0])); - LED LED_I( .PADDO(LED_c), .LED(LED)); - C14M C14M_I( .PADDI(C14M_c), .C14M(C14M)); - RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(N_662), - .RD7(RD[7])); - RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(N_663), - .RD6(RD[6])); - RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(N_664), - .RD5(RD[5])); - RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(N_648), - .RD4(RD[4])); - RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(N_263_i), - .RD3(RD[3])); - RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(N_665), - .RD2(RD[2])); - RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(N_666), - .RD1(RD[1])); - DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH)); - DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_508), .CE(N_201_i), - .CLK(C14M_c)); - DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML)); - DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_507_i), .CE(N_201_i), - .CLK(C14M_c)); - RAout_11_ \RAout[11]_I ( .IOLDO(\RAout_c[11] ), .RAout11(RAout[11])); - RAout_11__MGIOL \RAout[11]_MGIOL ( .IOLDO(\RAout_c[11] ), .OPOS(\RA[11] ), - .CLK(C14M_c)); - RAout_10_ \RAout[10]_I ( .IOLDO(\RAout_c[10] ), .RAout10(RAout[10])); - RAout_10__MGIOL \RAout[10]_MGIOL ( .IOLDO(\RAout_c[10] ), .OPOS(\RA[10] ), - .CLK(C14M_c)); - RAout_9_ \RAout[9]_I ( .IOLDO(\RAout_c[9] ), .RAout9(RAout[9])); - RAout_9__MGIOL \RAout[9]_MGIOL ( .IOLDO(\RAout_c[9] ), .OPOS(\RA[9] ), - .CLK(C14M_c)); - RAout_8_ \RAout[8]_I ( .IOLDO(\RAout_c[8] ), .RAout8(RAout[8])); - RAout_8__MGIOL \RAout[8]_MGIOL ( .IOLDO(\RAout_c[8] ), .OPOS(\RA[8] ), - .CLK(C14M_c)); - RAout_7_ \RAout[7]_I ( .IOLDO(\RAout_c[7] ), .RAout7(RAout[7])); - RAout_7__MGIOL \RAout[7]_MGIOL ( .IOLDO(\RAout_c[7] ), .OPOS(\RA[7] ), - .CLK(C14M_c)); - RAout_6_ \RAout[6]_I ( .IOLDO(\RAout_c[6] ), .RAout6(RAout[6])); - RAout_6__MGIOL \RAout[6]_MGIOL ( .IOLDO(\RAout_c[6] ), .OPOS(\RA[6] ), - .CLK(C14M_c)); - RAout_5_ \RAout[5]_I ( .IOLDO(\RAout_c[5] ), .RAout5(RAout[5])); - RAout_5__MGIOL \RAout[5]_MGIOL ( .IOLDO(\RAout_c[5] ), .OPOS(\RA[5] ), - .CLK(C14M_c)); - RAout_4_ \RAout[4]_I ( .IOLDO(\RAout_c[4] ), .RAout4(RAout[4])); - RAout_4__MGIOL \RAout[4]_MGIOL ( .IOLDO(\RAout_c[4] ), .OPOS(\RA[4] ), - .CLK(C14M_c)); - RAout_3_ \RAout[3]_I ( .IOLDO(\RAout_c[3] ), .RAout3(RAout[3])); - RAout_3__MGIOL \RAout[3]_MGIOL ( .IOLDO(\RAout_c[3] ), .OPOS(\RA[3] ), - .CLK(C14M_c)); - RAout_2_ \RAout[2]_I ( .IOLDO(\RAout_c[2] ), .RAout2(RAout[2])); - RAout_2__MGIOL \RAout[2]_MGIOL ( .IOLDO(\RAout_c[2] ), .OPOS(\RA[2] ), - .CLK(C14M_c)); - RAout_1_ \RAout[1]_I ( .IOLDO(\RAout_c[1] ), .RAout1(RAout[1])); - RAout_1__MGIOL \RAout[1]_MGIOL ( .IOLDO(\RAout_c[1] ), .OPOS(\RA[1] ), - .CLK(C14M_c)); - RAout_0_ \RAout[0]_I ( .IOLDO(\RAout_c[0] ), .RAout0(RAout[0])); - RAout_0__MGIOL \RAout[0]_MGIOL ( .IOLDO(\RAout_c[0] ), .OPOS(\RA[0] ), - .CLK(C14M_c)); - BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1])); - BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), .CE(N_225_i), - .LSR(BA_0_sqmuxa), .CLK(C14M_c)); - BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0])); - BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), .CE(N_225_i), - .LSR(BA_0_sqmuxa), .CLK(C14M_c)); - nRWEout nRWEout_I( .IOLDO(nRWEout_c), .nRWEout(nRWEout)); - nRWEout_MGIOL nRWEout_MGIOL( .IOLDO(nRWEout_c), .OPOS(nRWE), .CLK(C14M_c)); - nCASout nCASout_I( .IOLDO(nCASout_c), .nCASout(nCASout)); - nCASout_MGIOL nCASout_MGIOL( .IOLDO(nCASout_c), .OPOS(nCAS), .CLK(C14M_c)); - nRASout nRASout_I( .IOLDO(nRASout_c), .nRASout(nRASout)); - nRASout_MGIOL nRASout_MGIOL( .IOLDO(nRASout_c), .OPOS(nRAS), .CLK(C14M_c)); - nCSout nCSout_I( .PADDO(GND), .nCSout(nCSout)); - CKEout CKEout_I( .IOLDO(CKEout_c), .CKEout(CKEout)); - CKEout_MGIOL CKEout_MGIOL( .IOLDO(CKEout_c), .OPOS(CKE), .CLK(C14M_c)); - nVOE nVOE_I( .PADDO(nVOE_c), .nVOE(nVOE)); - Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7])); - Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_6_ \Vout[6]_I ( .IOLDO(\Vout_c[6] ), .Vout6(Vout[6])); - Vout_6__MGIOL \Vout[6]_MGIOL ( .IOLDO(\Vout_c[6] ), .OPOS(\RD_in[6] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_5_ \Vout[5]_I ( .IOLDO(\Vout_c[5] ), .Vout5(Vout[5])); - Vout_5__MGIOL \Vout[5]_MGIOL ( .IOLDO(\Vout_c[5] ), .OPOS(\RD_in[5] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_4_ \Vout[4]_I ( .IOLDO(\Vout_c[4] ), .Vout4(Vout[4])); - Vout_4__MGIOL \Vout[4]_MGIOL ( .IOLDO(\Vout_c[4] ), .OPOS(\RD_in[4] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_3_ \Vout[3]_I ( .IOLDO(\Vout_c[3] ), .Vout3(Vout[3])); - Vout_3__MGIOL \Vout[3]_MGIOL ( .IOLDO(\Vout_c[3] ), .OPOS(\RD_in[3] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_2_ \Vout[2]_I ( .IOLDO(\Vout_c[2] ), .Vout2(Vout[2])); - Vout_2__MGIOL \Vout[2]_MGIOL ( .IOLDO(\Vout_c[2] ), .OPOS(\RD_in[2] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_1_ \Vout[1]_I ( .IOLDO(\Vout_c[1] ), .Vout1(Vout[1])); - Vout_1__MGIOL \Vout[1]_MGIOL ( .IOLDO(\Vout_c[1] ), .OPOS(\RD_in[1] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_0_ \Vout[0]_I ( .IOLDO(\Vout_c[0] ), .Vout0(Vout[0])); - Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), - .CE(Vout3), .CLK(C14M_c)); - nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE)); - Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7])); - Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6])); - Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5])); - Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4])); - Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3])); - Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2])); - Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1])); - Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0])); - Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7])); - Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6])); - Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5])); - Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4])); - Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3])); - Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2])); - Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1])); - Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0])); - Ain_7_ \Ain[7]_I ( .PADDI(\Ain_c[7] ), .Ain7(Ain[7])); - Ain_6_ \Ain[6]_I ( .PADDI(\Ain_c[6] ), .Ain6(Ain[6])); - Ain_5_ \Ain[5]_I ( .PADDI(\Ain_c[5] ), .Ain5(Ain[5])); - Ain_4_ \Ain[4]_I ( .PADDI(\Ain_c[4] ), .Ain4(Ain[4])); - Ain_3_ \Ain[3]_I ( .PADDI(\Ain_c[3] ), .Ain3(Ain[3])); - Ain_2_ \Ain[2]_I ( .PADDI(\Ain_c[2] ), .Ain2(Ain[2])); - Ain_1_ \Ain[1]_I ( .PADDI(\Ain_c[1] ), .Ain1(Ain[1])); - Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0])); - nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X)); - nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80)); - nWE nWE_I( .PADDI(nWE_c), .nWE(nWE)); - PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1)); - PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1r)); - ram2e_ufm_ufmefb_EFBInst_0 \ram2e_ufm/ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), - .WBRSTI(\ram2e_ufm/wb_rst ), .WBCYCI(\ram2e_ufm/wb_cyc_stb ), - .WBSTBI(\ram2e_ufm/wb_cyc_stb ), .WBWEI(\ram2e_ufm/wb_we ), - .WBADRI0(\ram2e_ufm/wb_adr[0] ), .WBADRI1(\ram2e_ufm/wb_adr[1] ), - .WBADRI2(\ram2e_ufm/wb_adr[2] ), .WBADRI3(\ram2e_ufm/wb_adr[3] ), - .WBADRI4(\ram2e_ufm/wb_adr[4] ), .WBADRI5(\ram2e_ufm/wb_adr[5] ), - .WBADRI6(\ram2e_ufm/wb_adr[6] ), .WBADRI7(\ram2e_ufm/wb_adr[7] ), - .WBDATI0(\ram2e_ufm/wb_dati[0] ), .WBDATI1(\ram2e_ufm/wb_dati[1] ), - .WBDATI2(\ram2e_ufm/wb_dati[2] ), .WBDATI3(\ram2e_ufm/wb_dati[3] ), - .WBDATI4(\ram2e_ufm/wb_dati[4] ), .WBDATI5(\ram2e_ufm/wb_dati[5] ), - .WBDATI6(\ram2e_ufm/wb_dati[6] ), .WBDATI7(\ram2e_ufm/wb_dati[7] ), - .WBDATO0(\ram2e_ufm/wb_dato[0] ), .WBDATO1(\ram2e_ufm/wb_dato[1] ), - .WBDATO2(\ram2e_ufm/wb_dato[2] ), .WBDATO3(\ram2e_ufm/wb_dato[3] ), - .WBDATO4(\ram2e_ufm/wb_dato[4] ), .WBDATO5(\ram2e_ufm/wb_dato[5] ), - .WBDATO6(\ram2e_ufm/wb_dato[6] ), .WBDATO7(\ram2e_ufm/wb_dato[7] ), - .WBACKO(\ram2e_ufm/wb_ack )); - VHI VHI_INST( .Z(VCCI)); - PUR PUR_INST( .PUR(VCCI)); - GSR GSR_INST( .GSR(VCCI)); -endmodule - -module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly; - - vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module vcc ( output PWR1 ); - - VHI INST1( .Z(PWR1)); -endmodule - -module gnd ( output PWR0 ); - - VLO INST1( .Z(PWR0)); -endmodule - -module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h000A; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - ccu20001 \FS_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); - - specify - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h5002; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h300A; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut4 \ram2e_ufm/wb_req_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40003 \ram2e_ufm/CKE_7_RNIS77M1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 CKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut4 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40003 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCCD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_10 ( input B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40005 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40006 \ram2e_ufm/CmdTout_3_0_a3_0_a3[0] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40005 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40006 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_11 ( input D1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40007 \ram2e_ufm/RC_3_0_0_a3_1[1] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40008 \ram2e_ufm/N_360_i ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - vmuxregsre \RC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40007 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40008 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_12 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - - lut40009 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNI6S1P8 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40010 \ram2e_ufm/S_r_i_0_o2_RNIVM0LF[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0011 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0011 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40009 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40010 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0D0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0011 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_13 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output - F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40012 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40013 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0011 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40012 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40013 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAA1A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_14 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40014 \ram2e_ufm/CmdLEDGet_3_0_a3_0 ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40015 \ram2e_ufm/CmdLEDGet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40014 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40015 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_15 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ( .A(A1), .B(B1), .C(GNDI), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40017 \ram2e_ufm/CmdLEDSet_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40016 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40017 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_16 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40018 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40019 \ram2e_ufm/CmdRWMaskSet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40018 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40019 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_17 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40020 \ram2e_ufm/CmdRWMaskSet_3_0_a3_0 ( .A(GNDI), .B(B1), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 \ram2e_ufm/CmdSetRWBankFFLED_4_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40020 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40021 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_18 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40022 \ram2e_ufm/N_369_i ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40023 \ram2e_ufm/N_368_i ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CmdTout[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40022 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h006A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40023 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0066) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_19 ( input C1, B1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, M0_dly, CLK_dly, LSR_dly; - - lut40024 \ram2e_ufm/SUM0_i_o2 ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40025 \ram2e_ufm/RA_35_i_i_0_a3_0[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0011 DOEEN( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40024 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40025 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \ram2e_ufm/RA_35_i_i_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40027 \ram2e_ufm/RA_35_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40026 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40027 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_21 ( input D1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40028 \ram2e_ufm/RA_35_0_0[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 \ram2e_ufm/RA_35_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40028 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40029 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_22 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \ram2e_ufm/RA_35_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40030 \ram2e_ufm/RA_35_0_0[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40030 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40031 \ram2e_ufm/RA_35_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40031 \ram2e_ufm/RA_35_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre \RA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40031 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_24 ( input D1, C1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40032 \ram2e_ufm/RA_35_0_0[9] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40033 \ram2e_ufm/un2_S_2_i_0_0_o3_RNIHFHN3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \RA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40032 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40033 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_25 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40034 \ram2e_ufm/RA_35_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40035 \ram2e_ufm/RA_35_2_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40034 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40035 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_26 ( input D1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40036 \ram2e_ufm/RC_3_0_0[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40037 \ram2e_ufm/RC_3_0_0[1] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - vmuxregsre \RC[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RC[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40036 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6622) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40037 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2266) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_27 ( input D1, C1, B1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \ram2e_ufm/RWBank_3_0[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 \ram2e_ufm/RWBank_3_0_0[0] ( .A(GNDI), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40038 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_28 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40039 \ram2e_ufm/RWBank_3_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40040 \ram2e_ufm/RWBank_3_0[2] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40039 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40040 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_29 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40041 \ram2e_ufm/RWBank_3_0[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \ram2e_ufm/RWBank_3_0_0[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40041 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40042 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_30 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40043 \ram2e_ufm/RWBank_3_0[7] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40044 \ram2e_ufm/RWBank_3_0[6] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40043 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40044 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40045 \ram2e_ufm/RA_35_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40046 \ram2e_ufm/RWSel_2_0_a3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40045 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40046 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_32 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; - - lut40047 \ram2e_ufm/Ready3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40048 Ready_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40047 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40048 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40049 \ram2e_ufm/S_r_i_0_o2_0_RNI36E21[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40050 \ram2e_ufm/S_s_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40049 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00A2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40050 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40051 \ram2e_ufm/S_r_i_0_o2_RNIFNP81_0[2] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40052 \ram2e_ufm/S_r_i_0_o2_RNIFNP81[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \S[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40051 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00AE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40052 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2321) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_35 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40053 \ram2e_ufm/CKE_7_m1_0_0_o2_RNICM8E1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40054 \ram2e_ufm/CKE_7_m1_0_0_o2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0011 VOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40053 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40054 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40055 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40056 \ram2e_ufm/nCAS_s_i_0_a3_RNIO1UQ3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 nCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40055 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40056 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40057 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40058 \ram2e_ufm/nRAS_s_i_0_0_RNI0PC64 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 nRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40057 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40058 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_38 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40059 \ram2e_ufm/nRAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40060 \ram2e_ufm/nRAS_s_i_0_a3_0_RNIIR094 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0004 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40059 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40060 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0103) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_39 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40061 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40062 \ram2e_ufm/CmdBitbangMXO2_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/CmdBitbangMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40061 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40062 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_40 ( input D1, C1, B1, A1, C0, B0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40063 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40064 \ram2e_ufm/CmdExecMXO2_3_0_a3 ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/CmdExecMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40063 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40064 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40065 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40066 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/CmdSetRWBankFFChip ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40065 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40066 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_42 ( input D1, C1, A1, D0, C0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40067 \ram2e_ufm/SUM1_0_o3_0 ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40068 \ram2e_ufm/LEDEN_RNO ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/LEDEN ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40067 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40068 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_43 ( input D1, C1, B1, D0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40069 \ram2e_ufm/RWMask_RNO[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40070 \ram2e_ufm/RWMask_RNO[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40069 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0FCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40070 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h55CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_44 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40070 \ram2e_ufm/RWMask_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40071 \ram2e_ufm/RWMask_RNO[2] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40071 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h55F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_45 ( input D1, C1, B1, D0, C0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40072 \ram2e_ufm/RWMask_RNO[5] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40071 \ram2e_ufm/RWMask_RNO[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40072 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h33F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_46 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40068 \ram2e_ufm/RWMask_RNO[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40071 \ram2e_ufm/RWMask_RNO[6] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40073 \ram2e_ufm/wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40074 \ram2e_ufm/wb_adr_7_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40073 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40074 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_48 ( input D1, B1, D0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40075 \ram2e_ufm/wb_adr_RNO[3] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40076 \ram2e_ufm/wb_adr_RNO[2] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40075 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40076 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_49 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40077 \ram2e_ufm/wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40077 \ram2e_ufm/wb_adr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40077 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8D8D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_50 ( input B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40025 \ram2e_ufm/wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40078 \ram2e_ufm/wb_adr_RNO[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40078 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_51 ( input D1, C1, B1, A1, D0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40079 \ram2e_ufm/wb_cyc_stb_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40080 \ram2e_ufm/wb_cyc_stb_RNO ( .A(A0), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_cyc_stb ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40079 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40080 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40081 \ram2e_ufm/wb_dati_7_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40082 \ram2e_ufm/wb_dati_7_0_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40081 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40082 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40083 \ram2e_ufm/wb_dati_7_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40084 \ram2e_ufm/wb_dati_7_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40083 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40084 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40085 \ram2e_ufm/wb_dati_7_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40035 \ram2e_ufm/wb_dati_7_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40085 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40035 \ram2e_ufm/wb_dati_7_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40086 \ram2e_ufm/wb_dati_7_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40086 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40087 \ram2e_ufm/wb_reqc_1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40088 \ram2e_ufm/wb_req_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0011 \ram2e_ufm/wb_req ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40087 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40088 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_57 ( input D1, C1, B1, A1, C0, A0, DI0, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40089 \ram2e_ufm/Ready3_0_a3_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40090 \ram2e_ufm/wb_rst8_0_a3_0_a3 ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0011 \ram2e_ufm/wb_rst ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40089 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40090 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40091 \ram2e_ufm/wb_we_RNO_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40092 \ram2e_ufm/wb_we_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_we ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40091 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40092 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SUM0_i_m3_0_SLICE_59 ( input D1, C1, B1, D0, C0, B0, M0, - output OFX0 ); - wire GNDI, - \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 , - \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ; - - lut40093 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1 ( .A(GNDI), .B(B1), .C(C1), - .D(D1), - .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40094 \ram2e_ufm/SUM0_i_m3_0/GATE ( .A(GNDI), .B(B0), .C(C0), .D(D0), - .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 )); - selmux2 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K0K1MUX ( - .D0(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ), - .D1(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ), - .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40093 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF3FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40094 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module selmux2 ( input D0, D1, SD, output Z ); - - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 ( input D1, C1, B1, A1, C0, B0, - A0, M0, output OFX0 ); - wire - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 - , GNDI, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 - ; - - lut40095 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1 ( .A(A1), .B(B1), - .C(C1), .D(D1), - .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 ) - ); - lut40096 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - selmux2 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K0K1MUX ( - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 ) - , - .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40095 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40096 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_CKE_7_SLICE_61 ( input D1, C1, A1, D0, B0, A0, M0, output - OFX0 ); - wire GNDI, \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 , - \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ; - - lut40097 \ram2e_ufm/CKE_7/SLICE_61_K1 ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40098 \ram2e_ufm/CKE_7/GATE ( .A(A0), .B(B0), .C(GNDI), .D(D0), - .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 )); - selmux2 \ram2e_ufm/CKE_7/SLICE_61_K0K1MUX ( - .D0(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ), - .D1(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ), .SD(M0), - .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40097 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5F0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40098 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40099 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIAJ811 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40100 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIPG3P2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40099 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40100 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40101 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40102 \ram2e_ufm/S_r_i_0_o2_RNI3VQTC[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40101 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40102 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFCFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_64 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40103 \ram2e_ufm/wb_adr_7_i_i_a3_6[0] ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40104 \ram2e_ufm/wb_adr_7_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40103 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40104 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40105 \ram2e_ufm/SUM0_i_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40106 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40105 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40106 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF1F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40107 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40108 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40107 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40108 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDDDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_67 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40109 \ram2e_ufm/nRAS_s_i_0_m3 ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40110 \ram2e_ufm/nRAS_s_i_0_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40109 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDD11) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40110 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFDE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40111 \ram2e_ufm/wb_adr_7_i_i_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40112 \ram2e_ufm/wb_adr_7_i_i_3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40111 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40112 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0819) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40113 \ram2e_ufm/nCAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40114 \ram2e_ufm/wb_rst16_i_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40113 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40114 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_70 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40115 \ram2e_ufm/wb_dati_7_0_0_a3_12[7] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40116 \ram2e_ufm/wb_dati_7_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40115 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40116 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_71 ( input C1, B1, A1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40117 \ram2e_ufm/RA_35_0_0_a3_4[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40118 \ram2e_ufm/nRAS_s_i_0_a3_4 ( .A(A0), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40117 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40118 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_72 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40119 \ram2e_ufm/BA_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40120 \ram2e_ufm/un1_RC12_i_0_o3 ( .A(A0), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40119 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0C4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40120 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40121 \ram2e_ufm/wb_dati_7_0_0_o3_0[2] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40122 \ram2e_ufm/wb_dati_7_0_0_a3_3[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40121 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40122 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40123 \ram2e_ufm/RA_35_2_0_0[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40124 \ram2e_ufm/RA_35_2_0_a3_5[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40123 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40124 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_75 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40125 \ram2e_ufm/wb_dati_7_0_0_a3_15[7] ( .A(A1), .B(B1), .C(GNDI), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40126 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40125 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40126 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_76 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40127 \ram2e_ufm/wb_dati_7_0_0_a3_13[7] ( .A(GNDI), .B(GNDI), .C(C1), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40128 \ram2e_ufm/wb_dati_7_0_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40127 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0F00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40128 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40129 \ram2e_ufm/SUM2_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40130 \ram2e_ufm/N_314_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40129 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40130 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_78 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40131 \ram2e_ufm/S_r_i_0_o2[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40132 \ram2e_ufm/S_r_i_0_o2_RNIP4KI1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40131 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40132 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_79 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40133 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40134 \ram2e_ufm/S_r_i_0_o2_RNIOGTF1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40133 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8F88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40134 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40135 \ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40136 \ram2e_ufm/CmdBitbangMXO2_RNINSM62 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40135 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40136 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40137 \ram2e_ufm/wb_dati_7_0_0_a3_14[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40138 \ram2e_ufm/wb_dati_7_0_0_a3_13_RNI81UL[7] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40137 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40138 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40139 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40140 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40139 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40140 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_83 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40141 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ( .A(A1), .B(B1), .C(GNDI), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40142 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40141 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40142 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40143 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40144 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40143 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40144 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0F04) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40145 \ram2e_ufm/wb_dati_7_0_0_a3_10[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40146 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40145 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40146 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_86 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40147 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_1 ( .A(A1), .B(GNDI), .C(GNDI), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40148 \ram2e_ufm/wb_adr_7_i_i_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40147 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40148 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_87 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40149 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40150 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_m3 ( .A(GNDI), .B(B0), .C(C0), - .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40149 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40150 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_88 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40151 \ram2e_ufm/wb_dati_7_0_0_a3_4_1_0[7] ( .A(GNDI), .B(B1), .C(GNDI), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40152 \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40151 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40152 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_89 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40153 \ram2e_ufm/wb_dati_7_0_0_a3_7[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40154 \ram2e_ufm/wb_dati_7_0_0_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40153 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40154 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40155 \ram2e_ufm/wb_dati_7_0_0_a3_1_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40156 \ram2e_ufm/wb_dati_7_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40155 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0021) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40156 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40157 \ram2e_ufm/nRAS_s_i_0_a3_8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40158 \ram2e_ufm/nRAS_s_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40157 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40158 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3230) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40159 \ram2e_ufm/CKE_7s2_0_0_o3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40160 \ram2e_ufm/nCAS_s_i_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40159 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40160 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_93 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40161 \ram2e_ufm/wb_dati_7_0_0_o2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40162 \ram2e_ufm/wb_dati_7_0_0_a3[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40161 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40162 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_94 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40163 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ( .A(GNDI), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40164 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40163 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF3F3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40164 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40165 \ram2e_ufm/RA_35_0_0_o2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40166 \ram2e_ufm/RA_35_0_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40165 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEEC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40166 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40167 \ram2e_ufm/RA_35_0_0_o2_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40168 \ram2e_ufm/RA_35_0_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40167 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0236) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40168 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_97 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40169 \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ( .A(GNDI), .B(B1), .C(C1), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40170 \ram2e_ufm/wb_dati_7_0_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40169 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40170 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_98 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40171 \ram2e_ufm/wb_dati_7_0_0_a3_9[7] ( .A(GNDI), .B(GNDI), .C(C1), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40172 \ram2e_ufm/wb_dati_7_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40171 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40172 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_99 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40173 \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ( .A(A1), .B(GNDI), .C(C1), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40174 \ram2e_ufm/wb_adr_7_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40173 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40174 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA2A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40175 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40176 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40175 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40176 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE4FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_101 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40177 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3 ( .A(GNDI), .B(B1), - .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40178 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40177 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40178 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC5C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_102 ( input C1, B1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40179 \ram2e_ufm/CKE_7s2_0_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40180 \ram2e_ufm/CKE_7s2_0_0 ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40179 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40180 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_103 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40181 \ram2e_ufm/wb_dati_7_0_0_0_o2[7] ( .A(GNDI), .B(GNDI), .C(C1), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40182 \ram2e_ufm/wb_adr_RNO_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40181 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40182 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_104 ( input D1, C1, B1, A1, C0, A0, output F0, F1 ); - wire GNDI; - - lut40183 \ram2e_ufm/wb_dati_7_0_0_o2_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40184 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ( .A(A0), .B(GNDI), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40183 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h60A4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40184 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_105 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); - wire GNDI; - - lut40185 \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40186 \ram2e_ufm/N_285_i ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40185 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40186 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0F05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_106 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40024 \ram2e_ufm/S_r_i_0_o2[2] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40187 \ram2e_ufm/RA_35_2_0_a3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40187 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_107 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40188 \ram2e_ufm/CKE_7_m1_0_0_o2_RNIGC501 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40189 \ram2e_ufm/RA_35_i_i_0_a3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40188 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40189 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_108 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40190 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40191 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ( .A(GNDI), - .B(B0), .C(C0), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40190 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40191 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0F03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_109 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40192 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_6 ( .A(GNDI), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40193 \ram2e_ufm/wb_we_RNO_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40192 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40193 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAEAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_110 ( input D1, C1, B1, A1, C0, B0, output F0, F1 ); - wire GNDI; - - lut40194 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_7 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40195 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ( .A(GNDI), .B(B0), - .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40194 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40195 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_111 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40196 \ram2e_ufm/wb_dati_7_0_0_a3_2[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40197 \ram2e_ufm/wb_dati_7_0_0_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40196 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40197 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_112 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40198 \ram2e_ufm/nRAS_s_i_0_a3_6 ( .A(GNDI), .B(B1), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40199 \ram2e_ufm/nRAS_s_i_0_a3_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40198 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40199 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_113 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40200 \ram2e_ufm/nRAS_s_i_0_a3_5 ( .A(GNDI), .B(B1), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40201 \ram2e_ufm/RA_35_2_0_a3_3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40200 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40201 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_114 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40202 \ram2e_ufm/wb_adr_RNO_2[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40203 \ram2e_ufm/wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40202 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC03F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40203 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_115 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40131 \ram2e_ufm/un2_S_2_i_0_0_o3 ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40204 \ram2e_ufm/CKE_7s2_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40204 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_116 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40066 \ram2e_ufm/CmdExecMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40205 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ( .A(A0), .B(B0), - .C(GNDI), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40205 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_117 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40206 \ram2e_ufm/S_s_0_0_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40207 \ram2e_ufm/N_225_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40206 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0F0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40207 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0015) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_118 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40208 \ram2e_ufm/CKE_7_m1_0_0_o2_RNI7FOA1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40209 \ram2e_ufm/N_201_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40208 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40209 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_119 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40210 \ram2e_ufm/S_r_i_0_o2_RNIBAU51[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40211 \ram2e_ufm/un1_CKE75_0_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40210 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40211 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB5CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_120 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40212 \ram2e_ufm/DQMH_4_iv_0_0_i_i_a3_0_a3 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40213 \ram2e_ufm/N_507_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40212 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7707) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40213 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h888F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_121 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40214 \ram2e_ufm/Vout3_0_a3_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40215 \ram2e_ufm/RA_35_0_0_o2[11] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40214 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40215 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_122 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40216 \ram2e_ufm/nRWE_s_i_0_63_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40217 \ram2e_ufm/nCAS_s_i_0_m2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40216 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5EDE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40217 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3F7A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_123 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40218 \ram2e_ufm/wb_adr_RNO_3[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40062 \ram2e_ufm/wb_dati_7_0_0_a3_8[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40218 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_124 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40219 \ram2e_ufm/RA_35_0_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40220 \ram2e_ufm/RA_35_0_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40219 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40220 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_125 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40221 \ram2e_ufm/wb_adr_7_i_i_o2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40061 \ram2e_ufm/wb_dati_7_0_0_a3_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40221 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F4C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_126 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40222 \ram2e_ufm/wb_we_RNO_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40223 \ram2e_ufm/wb_adr_7_i_i_a3_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40222 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h70F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40223 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_127 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40224 \ram2e_ufm/un9_VOEEN_0_a2_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40225 \ram2e_ufm/RA_35_2_30_a3_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40224 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40225 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_128 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); - wire GNDI; - - lut40226 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40227 \ram2e_ufm/wb_adr_RNO_4[1] ( .A(A0), .B(GNDI), .C(C0), .D(D0), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40226 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40227 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40228 \ram2e_ufm/BA_4[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40140 \ram2e_ufm/RA_35_2_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40228 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAB00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_130 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40229 \ram2e_ufm/N_187_i ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40230 \ram2e_ufm/wb_we_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40229 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40230 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_131 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40231 \ram2e_ufm/Ready3_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40232 \ram2e_ufm/wb_dati_7_0_0_0_a3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40231 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40232 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_132 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40233 \ram2e_ufm/RA_35_0_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40234 \ram2e_ufm/RA_35_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40233 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40234 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_133 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40235 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40236 \ram2e_ufm/SUM0_i_o2_2 ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40235 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40236 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_134 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40190 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40237 \ram2e_ufm/RA_35_0_0_a3[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40237 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_135 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40238 \ram2e_ufm/S_r_i_0_o2_0[1] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40239 \ram2e_ufm/RA_35_2_0_a3_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40238 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40239 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h002A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_136 ( input C1, B1, A1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40240 \ram2e_ufm/nRAS_s_i_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40241 \ram2e_ufm/un1_nDOE_i ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40240 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3737) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40241 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBBFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_137 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40242 \ram2e_ufm/RDOE_i ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40243 \ram2e_ufm/LEDEN_RNI6G6M ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40242 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40243 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBFBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_138 ( input D1, B1, A1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40244 VOEEN_RNO( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40245 DOEEN_RNO( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40244 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1133) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40245 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1155) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_139 ( input B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40246 nVOE_pad_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40247 S_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40246 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40247 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_140 ( input B1, A1, C0, A0, output F0, F1 ); - wire GNDI; - - lut40025 \ram2e_ufm/RA_35_0_0_a3_0[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40248 \ram2e_ufm/RA_35_0_0_a3[5] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40248 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_141 ( input D1, B1, D0, A0, output F0, F1 ); - wire GNDI; - - lut40075 \ram2e_ufm/RDout_i_0_i_a3[0] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40076 \ram2e_ufm/N_263_i ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_142 ( input D1, C1, A1, D0, C0, output F0, F1 ); - wire GNDI; - - lut40227 \ram2e_ufm/CmdLEDGet_3_0_a3_1 ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40249 \ram2e_ufm/RDout_i_i_a3[4] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40249 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_143 ( input D1, C1, D0, B0, output F0, F1 ); - wire GNDI; - - lut40250 \ram2e_ufm/RDout_i_0_i_a3[1] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40075 \ram2e_ufm/RDout_i_0_i_a3[7] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40250 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_144 ( input C1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40251 \ram2e_ufm/RDout_i_0_i_a3[2] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40252 \ram2e_ufm/RDout_i_0_i_a3[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40251 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40252 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_145 ( input D1, C1, B1, A1, D0, A0, output F0, F1 ); - wire GNDI; - - lut40253 \ram2e_ufm/wb_dati_7_0_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40254 \ram2e_ufm/wb_dati_7_0_0_o2_0[7] ( .A(A0), .B(GNDI), .C(GNDI), - .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40253 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40254 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_146 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40255 \ram2e_ufm/RA_35_0_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40256 \ram2e_ufm/Ready3_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40255 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40256 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_147 ( input D1, C1, B1, A1, C0, B0, output F0, F1 ); - wire GNDI; - - lut40257 \ram2e_ufm/RWBank_3_0_0_o3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40195 \ram2e_ufm/RDout_i_0_i_a3[5] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40257 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); - - xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); - - specify - (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD0) = (0:0:0,0:0:0); - (RD0 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD0, 0:0:0); - $width (negedge RD0, 0:0:0); - endspecify - -endmodule - -module xo2iobuf ( input I, T, output Z, PAD, input PADI ); - - IB INST1( .I(PADI), .O(Z)); - OBW INST2( .I(I), .T(T), .O(PAD)); -endmodule - -module LED ( input PADDO, output LED ); - - xo2iobuf0258 LED_pad( .I(PADDO), .PAD(LED)); - - specify - (PADDO => LED) = (0:0:0,0:0:0); - endspecify - -endmodule - -module xo2iobuf0258 ( input I, output PAD ); - - OB INST5( .I(I), .O(PAD)); -endmodule - -module C14M ( output PADDI, input C14M ); - - xo2iobuf0259 C14M_pad( .Z(PADDI), .PAD(C14M)); - - specify - (C14M => PADDI) = (0:0:0,0:0:0); - $width (posedge C14M, 0:0:0); - $width (negedge C14M, 0:0:0); - endspecify - -endmodule - -module xo2iobuf0259 ( output Z, input PAD ); - - IB INST1( .I(PAD), .O(Z)); -endmodule - -module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); - - xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7)); - - specify - (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD7) = (0:0:0,0:0:0); - (RD7 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD7, 0:0:0); - $width (negedge RD7, 0:0:0); - endspecify - -endmodule - -module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); - - xo2iobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6)); - - specify - (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD6) = (0:0:0,0:0:0); - (RD6 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD6, 0:0:0); - $width (negedge RD6, 0:0:0); - endspecify - -endmodule - -module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); - - xo2iobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5)); - - specify - (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD5) = (0:0:0,0:0:0); - (RD5 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD5, 0:0:0); - $width (negedge RD5, 0:0:0); - endspecify - -endmodule - -module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); - - xo2iobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4)); - - specify - (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD4) = (0:0:0,0:0:0); - (RD4 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD4, 0:0:0); - $width (negedge RD4, 0:0:0); - endspecify - -endmodule - -module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); - - xo2iobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3)); - - specify - (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD3) = (0:0:0,0:0:0); - (RD3 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD3, 0:0:0); - $width (negedge RD3, 0:0:0); - endspecify - -endmodule - -module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); - - xo2iobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2)); - - specify - (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD2) = (0:0:0,0:0:0); - (RD2 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD2, 0:0:0); - $width (negedge RD2, 0:0:0); - endspecify - -endmodule - -module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); - - xo2iobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1)); - - specify - (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD1) = (0:0:0,0:0:0); - (RD1 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD1, 0:0:0); - $width (negedge RD1, 0:0:0); - endspecify - -endmodule - -module DQMH ( input IOLDO, output DQMH ); - - xo2iobuf0258 DQMH_pad( .I(IOLDO), .PAD(DQMH)); - - specify - (IOLDO => DQMH) = (0:0:0,0:0:0); - endspecify - -endmodule - -module DQMH_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre DQMH_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module mfflsre ( input D0, SP, CK, LSR, output Q ); - - FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module DQML ( input IOLDO, output DQML ); - - xo2iobuf0258 DQML_pad( .I(IOLDO), .PAD(DQML)); - - specify - (IOLDO => DQML) = (0:0:0,0:0:0); - endspecify - -endmodule - -module DQML_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre DQML_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module RAout_11_ ( input IOLDO, output RAout11 ); - - xo2iobuf0258 \RAout_pad[11] ( .I(IOLDO), .PAD(RAout11)); - - specify - (IOLDO => RAout11) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_11__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module mfflsre0260 ( input D0, SP, CK, LSR, output Q ); - - FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module inverter ( input I, output Z ); - - INV INST1( .A(I), .Z(Z)); -endmodule - -module RAout_10_ ( input IOLDO, output RAout10 ); - - xo2iobuf0258 \RAout_pad[10] ( .I(IOLDO), .PAD(RAout10)); - - specify - (IOLDO => RAout10) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_10__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_9_ ( input IOLDO, output RAout9 ); - - xo2iobuf0258 \RAout_pad[9] ( .I(IOLDO), .PAD(RAout9)); - - specify - (IOLDO => RAout9) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_9__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_8_ ( input IOLDO, output RAout8 ); - - xo2iobuf0258 \RAout_pad[8] ( .I(IOLDO), .PAD(RAout8)); - - specify - (IOLDO => RAout8) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_8__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_7_ ( input IOLDO, output RAout7 ); - - xo2iobuf0258 \RAout_pad[7] ( .I(IOLDO), .PAD(RAout7)); - - specify - (IOLDO => RAout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_7__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_6_ ( input IOLDO, output RAout6 ); - - xo2iobuf0258 \RAout_pad[6] ( .I(IOLDO), .PAD(RAout6)); - - specify - (IOLDO => RAout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_6__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_5_ ( input IOLDO, output RAout5 ); - - xo2iobuf0258 \RAout_pad[5] ( .I(IOLDO), .PAD(RAout5)); - - specify - (IOLDO => RAout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_5__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_4_ ( input IOLDO, output RAout4 ); - - xo2iobuf0258 \RAout_pad[4] ( .I(IOLDO), .PAD(RAout4)); - - specify - (IOLDO => RAout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_4__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_3_ ( input IOLDO, output RAout3 ); - - xo2iobuf0258 \RAout_pad[3] ( .I(IOLDO), .PAD(RAout3)); - - specify - (IOLDO => RAout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_3__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_2_ ( input IOLDO, output RAout2 ); - - xo2iobuf0258 \RAout_pad[2] ( .I(IOLDO), .PAD(RAout2)); - - specify - (IOLDO => RAout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_2__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_1_ ( input IOLDO, output RAout1 ); - - xo2iobuf0258 \RAout_pad[1] ( .I(IOLDO), .PAD(RAout1)); - - specify - (IOLDO => RAout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_1__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_0_ ( input IOLDO, output RAout0 ); - - xo2iobuf0258 \RAout_pad[0] ( .I(IOLDO), .PAD(RAout0)); - - specify - (IOLDO => RAout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_0__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 \RAout_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module BA_1_ ( input IOLDO, output BA1 ); - - xo2iobuf0258 \BA_pad[1] ( .I(IOLDO), .PAD(BA1)); - - specify - (IOLDO => BA1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module BA_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0261 \BA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module mfflsre0261 ( input D0, SP, CK, LSR, output Q ); - - FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module BA_0_ ( input IOLDO, output BA0 ); - - xo2iobuf0258 \BA_pad[0] ( .I(IOLDO), .PAD(BA0)); - - specify - (IOLDO => BA0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module BA_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0261 \BA_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module nRWEout ( input IOLDO, output nRWEout ); - - xo2iobuf0258 nRWEout_pad( .I(IOLDO), .PAD(nRWEout)); - - specify - (IOLDO => nRWEout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRWEout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nRWEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nCASout ( input IOLDO, output nCASout ); - - xo2iobuf0258 nCASout_pad( .I(IOLDO), .PAD(nCASout)); - - specify - (IOLDO => nCASout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nCASout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nCASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nRASout ( input IOLDO, output nRASout ); - - xo2iobuf0258 nRASout_pad( .I(IOLDO), .PAD(nRASout)); - - specify - (IOLDO => nRASout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRASout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nRASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nCSout ( input PADDO, output nCSout ); - - xo2iobuf0258 nCSout_pad( .I(PADDO), .PAD(nCSout)); - - specify - (PADDO => nCSout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CKEout ( input IOLDO, output CKEout ); - - xo2iobuf0258 CKEout_pad( .I(IOLDO), .PAD(CKEout)); - - specify - (IOLDO => CKEout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CKEout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0260 CKEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nVOE ( input PADDO, output nVOE ); - - xo2iobuf0258 nVOE_pad( .I(PADDO), .PAD(nVOE)); - - specify - (PADDO => nVOE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_7_ ( input IOLDO, output Vout7 ); - - xo2iobuf0258 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7)); - - specify - (IOLDO => Vout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0260 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_6_ ( input IOLDO, output Vout6 ); - - xo2iobuf0258 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6)); - - specify - (IOLDO => Vout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0260 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_5_ ( input IOLDO, output Vout5 ); - - xo2iobuf0258 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5)); - - specify - (IOLDO => Vout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0260 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_4_ ( input IOLDO, output Vout4 ); - - xo2iobuf0258 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4)); - - specify - (IOLDO => Vout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0260 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_3_ ( input IOLDO, output Vout3 ); - - xo2iobuf0258 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3)); - - specify - (IOLDO => Vout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0260 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_2_ ( input IOLDO, output Vout2 ); - - xo2iobuf0258 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2)); - - specify - (IOLDO => Vout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0260 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_1_ ( input IOLDO, output Vout1 ); - - xo2iobuf0258 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1)); - - specify - (IOLDO => Vout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0260 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_0_ ( input IOLDO, output Vout0 ); - - xo2iobuf0258 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0)); - - specify - (IOLDO => Vout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0260 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module nDOE ( input PADDO, output nDOE ); - - xo2iobuf0258 nDOE_pad( .I(PADDO), .PAD(nDOE)); - - specify - (PADDO => nDOE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_7_ ( input PADDO, output Dout7 ); - - xo2iobuf0258 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); - - specify - (PADDO => Dout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_6_ ( input PADDO, output Dout6 ); - - xo2iobuf0258 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); - - specify - (PADDO => Dout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_5_ ( input PADDO, output Dout5 ); - - xo2iobuf0258 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); - - specify - (PADDO => Dout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_4_ ( input PADDO, output Dout4 ); - - xo2iobuf0258 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); - - specify - (PADDO => Dout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_3_ ( input PADDO, output Dout3 ); - - xo2iobuf0258 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); - - specify - (PADDO => Dout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_2_ ( input PADDO, output Dout2 ); - - xo2iobuf0258 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); - - specify - (PADDO => Dout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_1_ ( input PADDO, output Dout1 ); - - xo2iobuf0258 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); - - specify - (PADDO => Dout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_0_ ( input PADDO, output Dout0 ); - - xo2iobuf0258 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); - - specify - (PADDO => Dout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Din_7_ ( output PADDI, input Din7 ); - - xo2iobuf0259 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); - - specify - (Din7 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din7, 0:0:0); - $width (negedge Din7, 0:0:0); - endspecify - -endmodule - -module Din_6_ ( output PADDI, input Din6 ); - - xo2iobuf0259 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); - - specify - (Din6 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din6, 0:0:0); - $width (negedge Din6, 0:0:0); - endspecify - -endmodule - -module Din_5_ ( output PADDI, input Din5 ); - - xo2iobuf0259 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); - - specify - (Din5 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din5, 0:0:0); - $width (negedge Din5, 0:0:0); - endspecify - -endmodule - -module Din_4_ ( output PADDI, input Din4 ); - - xo2iobuf0259 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); - - specify - (Din4 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din4, 0:0:0); - $width (negedge Din4, 0:0:0); - endspecify - -endmodule - -module Din_3_ ( output PADDI, input Din3 ); - - xo2iobuf0259 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); - - specify - (Din3 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din3, 0:0:0); - $width (negedge Din3, 0:0:0); - endspecify - -endmodule - -module Din_2_ ( output PADDI, input Din2 ); - - xo2iobuf0259 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); - - specify - (Din2 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din2, 0:0:0); - $width (negedge Din2, 0:0:0); - endspecify - -endmodule - -module Din_1_ ( output PADDI, input Din1 ); - - xo2iobuf0259 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); - - specify - (Din1 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din1, 0:0:0); - $width (negedge Din1, 0:0:0); - endspecify - -endmodule - -module Din_0_ ( output PADDI, input Din0 ); - - xo2iobuf0259 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); - - specify - (Din0 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din0, 0:0:0); - $width (negedge Din0, 0:0:0); - endspecify - -endmodule - -module Ain_7_ ( output PADDI, input Ain7 ); - - xo2iobuf0259 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7)); - - specify - (Ain7 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain7, 0:0:0); - $width (negedge Ain7, 0:0:0); - endspecify - -endmodule - -module Ain_6_ ( output PADDI, input Ain6 ); - - xo2iobuf0259 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6)); - - specify - (Ain6 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain6, 0:0:0); - $width (negedge Ain6, 0:0:0); - endspecify - -endmodule - -module Ain_5_ ( output PADDI, input Ain5 ); - - xo2iobuf0259 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5)); - - specify - (Ain5 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain5, 0:0:0); - $width (negedge Ain5, 0:0:0); - endspecify - -endmodule - -module Ain_4_ ( output PADDI, input Ain4 ); - - xo2iobuf0259 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4)); - - specify - (Ain4 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain4, 0:0:0); - $width (negedge Ain4, 0:0:0); - endspecify - -endmodule - -module Ain_3_ ( output PADDI, input Ain3 ); - - xo2iobuf0259 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3)); - - specify - (Ain3 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain3, 0:0:0); - $width (negedge Ain3, 0:0:0); - endspecify - -endmodule - -module Ain_2_ ( output PADDI, input Ain2 ); - - xo2iobuf0259 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2)); - - specify - (Ain2 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain2, 0:0:0); - $width (negedge Ain2, 0:0:0); - endspecify - -endmodule - -module Ain_1_ ( output PADDI, input Ain1 ); - - xo2iobuf0259 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1)); - - specify - (Ain1 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain1, 0:0:0); - $width (negedge Ain1, 0:0:0); - endspecify - -endmodule - -module Ain_0_ ( output PADDI, input Ain0 ); - - xo2iobuf0259 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0)); - - specify - (Ain0 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain0, 0:0:0); - $width (negedge Ain0, 0:0:0); - endspecify - -endmodule - -module nC07X ( output PADDI, input nC07X ); - - xo2iobuf0259 nC07X_pad( .Z(PADDI), .PAD(nC07X)); - - specify - (nC07X => PADDI) = (0:0:0,0:0:0); - $width (posedge nC07X, 0:0:0); - $width (negedge nC07X, 0:0:0); - endspecify - -endmodule - -module nEN80 ( output PADDI, input nEN80 ); - - xo2iobuf0259 nEN80_pad( .Z(PADDI), .PAD(nEN80)); - - specify - (nEN80 => PADDI) = (0:0:0,0:0:0); - $width (posedge nEN80, 0:0:0); - $width (negedge nEN80, 0:0:0); - endspecify - -endmodule - -module nWE ( output PADDI, input nWE ); - - xo2iobuf0259 nWE_pad( .Z(PADDI), .PAD(nWE)); - - specify - (nWE => PADDI) = (0:0:0,0:0:0); - $width (posedge nWE, 0:0:0); - $width (negedge nWE, 0:0:0); - endspecify - -endmodule - -module PHI1 ( output PADDI, input PHI1 ); - - xo2iobuf0259 PHI1_pad( .Z(PADDI), .PAD(PHI1)); - - specify - (PHI1 => PADDI) = (0:0:0,0:0:0); - $width (posedge PHI1, 0:0:0); - $width (negedge PHI1, 0:0:0); - endspecify - -endmodule - -module PHI1_MGIOL ( input DI, CLK, output IN ); - wire VCCI, GNDI, DI_dly, CLK_dly; - - smuxlregsre PHI1r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), - .Q(IN)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IN) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module smuxlregsre ( input D0, SP, CK, LSR, output Q ); - - IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module ram2e_ufm_ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, - WBWEI, WBADRI0, WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, - WBADRI7, WBDATI0, WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, - WBDATI7, output WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, - WBDATO6, WBDATO7, WBACKO ); - wire VCCI, GNDI; - - EFB_B \ram2e_ufm/ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), - .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), - .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), - .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), - .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), - .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), - .WBDATO1(WBDATO1), .WBDATO2(WBDATO2), .WBDATO3(WBDATO3), .WBDATO4(WBDATO4), - .WBDATO5(WBDATO5), .WBDATO6(WBDATO6), .WBDATO7(WBDATO7), .WBACKO(WBACKO), - .WBCUFMIRQ(), .UFMSN(VCCI), .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), - .I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), - .I2C2SCLI(GNDI), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), - .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), - .SPISCKEN(), .SPIMISOI(GNDI), .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), - .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), - .SPIMCSN3(), .SPIMCSN4(), .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), - .SPICSNEN(), .SPISCSN(GNDI), .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), - .TCIC(GNDI), .TCINT(), .TCOC(), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), - .PLL1STBO(), .PLLWEO(), .PLLADRO0(), .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), - .PLLADRO4(), .PLLDATO0(), .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), - .PLLDATO4(), .PLLDATO5(), .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), - .PLL0DATI1(GNDI), .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), - .PLL0DATI5(GNDI), .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), - .PLL1DATI0(GNDI), .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), - .PLL1DATI4(GNDI), .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), - .PLL1ACKI(GNDI)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); -endmodule - -module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, - WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, - WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, - WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, - WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output - I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input - I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, - I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, - input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output - SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, - SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, - input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, - PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, - PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, - PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, - PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, - PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI ); - wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, - WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, - WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, - WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, - WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, - PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, - PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, - PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, - PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, - I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, - SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, - UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, - WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, - PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, - PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, - PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, - PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, - I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, - I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, - I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, - SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, - SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, - SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, - CFGWAKE_buf, CFGSTDBY_buf; - - EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), - .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), - .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), - .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), - .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), - .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), - .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), - .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), - .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), - .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), - .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), - .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), - .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), - .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), - .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), - .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), - .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), - .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), - .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), - .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), - .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), - .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), - .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), - .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), - .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), - .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), - .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), - .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), - .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), - .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), - .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), - .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), - .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), - .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), - .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), - .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), - .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), - .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), - .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), - .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), - .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), - .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf)); - defparam INST10.DEV_DENSITY = "1200L"; - defparam INST10.EFB_I2C1 = "DISABLED"; - defparam INST10.EFB_I2C2 = "DISABLED"; - defparam INST10.EFB_SPI = "DISABLED"; - defparam INST10.EFB_TC = "DISABLED"; - defparam INST10.EFB_TC_PORTMODE = "WB"; - defparam INST10.EFB_UFM = "ENABLED"; - defparam INST10.EFB_WB_CLK_FREQ = "14.4"; - defparam INST10.GSR = "ENABLED"; - defparam INST10.I2C1_ADDRESSING = "7BIT"; - defparam INST10.I2C1_BUS_PERF = "100kHz"; - defparam INST10.I2C1_CLK_DIVIDER = 1; - defparam INST10.I2C1_GEN_CALL = "DISABLED"; - defparam INST10.I2C1_SLAVE_ADDR = "0b1000001"; - defparam INST10.I2C1_WAKEUP = "DISABLED"; - defparam INST10.I2C2_ADDRESSING = "7BIT"; - defparam INST10.I2C2_BUS_PERF = "100kHz"; - defparam INST10.I2C2_CLK_DIVIDER = 1; - defparam INST10.I2C2_GEN_CALL = "DISABLED"; - defparam INST10.I2C2_SLAVE_ADDR = "0b1000010"; - defparam INST10.I2C2_WAKEUP = "DISABLED"; - defparam INST10.SPI_CLK_DIVIDER = 1; - defparam INST10.SPI_CLK_INV = "DISABLED"; - defparam INST10.SPI_INTR_RXOVR = "DISABLED"; - defparam INST10.SPI_INTR_RXRDY = "DISABLED"; - defparam INST10.SPI_INTR_TXOVR = "DISABLED"; - defparam INST10.SPI_INTR_TXRDY = "DISABLED"; - defparam INST10.SPI_LSB_FIRST = "DISABLED"; - defparam INST10.SPI_MODE = "MASTER"; - defparam INST10.SPI_PHASE_ADJ = "DISABLED"; - defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED"; - defparam INST10.SPI_WAKEUP = "DISABLED"; - defparam INST10.TC_CCLK_SEL = 1; - defparam INST10.TC_ICAPTURE = "DISABLED"; - defparam INST10.TC_ICR_INT = "OFF"; - defparam INST10.TC_MODE = "CTCM"; - defparam INST10.TC_OCR_INT = "OFF"; - defparam INST10.TC_OCR_SET = 32767; - defparam INST10.TC_OC_MODE = "TOGGLE"; - defparam INST10.TC_OVERFLOW = "DISABLED"; - defparam INST10.TC_OV_INT = "OFF"; - defparam INST10.TC_RESETN = "ENABLED"; - defparam INST10.TC_SCLK_SEL = "PCLOCK"; - defparam INST10.TC_TOP_SEL = "OFF"; - defparam INST10.TC_TOP_SET = 65535; - defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED"; - defparam INST10.UFM_INIT_FILE_FORMAT = "HEX"; - defparam INST10.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem"; - defparam INST10.UFM_INIT_PAGES = 321; - defparam INST10.UFM_INIT_START_PAGE = 190; - EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), - .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), - .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), - .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), - .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), - .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), - .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), - .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), - .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), - .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), - .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), - .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), - .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), - .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), - .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), - .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), - .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), - .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), - .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), - .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), - .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), - .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), - .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), - .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), - .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), - .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), - .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), - .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), - .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), - .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), - .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), - .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), - .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), - .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), - .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), - .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), - .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), - .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), - .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), - .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), - .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), - .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), - .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), - .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), - .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), - .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), - .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), - .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), - .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), - .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), - .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), - .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), - .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), - .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), - .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), - .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), - .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), - .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), - .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), - .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), - .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), - .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), - .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), - .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), - .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), - .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), - .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), - .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), - .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), - .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), - .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), - .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), - .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), - .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), - .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), - .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), - .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), - .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), - .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), - .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), - .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), - .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), - .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), - .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), - .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), - .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), - .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), - .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), - .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), - .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), - .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), - .CFGSTDBYin(CFGSTDBY_buf)); -endmodule - -module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, - output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, - output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output - WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output - WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output - WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output - WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output - WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output - WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output - WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output - WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output - PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, - output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input - PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, - input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output - PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, - output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input - PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, - input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output - PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, - output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input - I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, - input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, - input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, - input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, - input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input - TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input - WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input - WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input - WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input - WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input - WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input - PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, - input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, - input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, - input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, - input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, - input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, - input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, - input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, - input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output - I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, - output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input - I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, - input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output - I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, - output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, - output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input - SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, - input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output - SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, - output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, - output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, - output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, - output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, - output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, - output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin ); - wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, - WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, - WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, - WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, - WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly; - - BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout)); - BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout)); - BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout)); - BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout)); - BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout)); - BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out)); - BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out)); - BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out)); - BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out)); - BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out)); - BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out)); - BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out)); - BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out)); - BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out)); - BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out)); - BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out)); - BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out)); - BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out)); - BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out)); - BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out)); - BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out)); - BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out)); - BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out)); - BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out)); - BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out)); - BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out)); - BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out)); - BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out)); - BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out)); - BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout)); - BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out)); - BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out)); - BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out)); - BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out)); - BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out)); - BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out)); - BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out)); - BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out)); - BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout)); - BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout)); - BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout)); - BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout)); - BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout)); - BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout)); - BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout)); - BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout)); - BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout)); - BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout)); - BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout)); - BUFBA TCIC_buf( .A(TCICin), .Z(TCICout)); - BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout)); - BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out)); - BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out)); - BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out)); - BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out)); - BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out)); - BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out)); - BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out)); - BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out)); - BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout)); - BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout)); - BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout)); - BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout)); - BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout)); - BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout)); - BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out)); - BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out)); - BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out)); - BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out)); - BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out)); - BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out)); - BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out)); - BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out)); - BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out)); - BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out)); - BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out)); - BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out)); - BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out)); - BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout)); - BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout)); - BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout)); - BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout)); - BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout)); - BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout)); - BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout)); - BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout)); - BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout)); - BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout)); - BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout)); - BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout)); - BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout)); - BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout)); - BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout)); - BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout)); - BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out)); - BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out)); - BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out)); - BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out)); - BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out)); - BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out)); - BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out)); - BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out)); - BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout)); - BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout)); - BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout)); - BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout)); - BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout)); - BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout)); - BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout)); - - specify - (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO2out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO3out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO4out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO5out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO6out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO7out) = (0:0:0,0:0:0); - (WBCLKIin => WBACKOout) = (0:0:0,0:0:0); - $setuphold - (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly); - $setuphold - (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly); - $setuphold - (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly); - $setuphold - (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly); - $setuphold - (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly); - $setuphold - (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly); - $setuphold - (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly); - $setuphold - (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly); - $setuphold - (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly); - $setuphold - (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly); - $setuphold - (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly); - $setuphold - (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly); - $setuphold - (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly); - $setuphold - (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly); - $setuphold - (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly); - $setuphold - (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly); - $setuphold - (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly); - $setuphold - (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly); - $setuphold - (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly); - $setuphold - (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly); - $width (posedge WBCLKIin, 0:0:0); - $width (negedge WBCLKIin, 0:0:0); - endspecify - -endmodule diff --git a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html deleted file mode 100644 index 15f7f6d..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html +++ /dev/null @@ -1,16 +0,0 @@ - 
    Setting log file to '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html'.
-Starting: parse design source files
-(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
-(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v'
-(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v'
-(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v'
-INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E'
-INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-473,10) (VERI-9000) elaborating module 'RAM2E'
-INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-334,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
-INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
-INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
-INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
-INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
-Done: design load finished with (0) errors, and (0) warnings
-
-
    \ No newline at end of file diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior b/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior deleted file mode 100644 index d3d1f69..0000000 --- a/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior +++ /dev/null @@ -1,118 +0,0 @@ -Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 5 -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: 6 -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-1200HC -Package: TQFP100 -Performance: M -Package Status: Final Version 1.44. -Performance Hardware Data Status: Final Version 34.4. -// Design: RAM2E -// Package: TQFP100 -// ncd File: ram2e_lcmxo2_1200hc_impl1.ncd -// Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Dec 28 23:23:48 2023 -// M: Minimum Performance Grade -// iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml - -I/O Timing Report (All units are in ns) - -Worst Case Results across Performance Grades (M, 6, 5, 4): - -// Input Setup and Hold Times - -Port Clock Edge Setup Performance_Grade Hold Performance_Grade ----------------------------------------------------------------------- -Ain[0] C14M R 0.163 4 1.694 4 -Ain[1] C14M R -0.150 M 2.217 4 -Ain[2] C14M R -0.080 M 2.156 4 -Ain[3] C14M R 0.466 4 1.338 4 -Ain[4] C14M R 0.215 4 1.597 4 -Ain[5] C14M R -0.331 M 2.651 4 -Ain[6] C14M R 0.065 M 1.882 4 -Ain[7] C14M R 0.284 4 1.683 4 -Din[0] C14M R 6.887 4 2.257 4 -Din[1] C14M R 8.753 4 2.907 4 -Din[2] C14M R 6.379 4 2.740 4 -Din[3] C14M R 7.129 4 1.402 4 -Din[4] C14M R 6.869 4 2.791 4 -Din[5] C14M R 6.514 4 2.334 4 -Din[6] C14M R 6.735 4 1.914 4 -Din[7] C14M R 8.094 4 1.968 4 -PHI1 C14M R 1.557 4 4.842 4 -RD[0] C14M R -0.266 M 2.342 4 -RD[1] C14M R -0.248 M 2.283 4 -RD[2] C14M R -0.407 M 2.610 4 -RD[3] C14M R -0.243 M 2.193 4 -RD[4] C14M R -0.246 M 2.201 4 -RD[5] C14M R -0.243 M 2.193 4 -RD[6] C14M R -0.087 M 1.756 4 -RD[7] C14M R -0.092 M 1.769 4 -nC07X C14M R -0.320 M 2.703 4 -nEN80 C14M R 4.607 4 1.925 4 -nWE C14M R 4.609 4 2.010 4 - - -// Clock to Output Delay - -Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------- -BA[0] C14M R 10.424 4 3.355 M -BA[1] C14M R 10.424 4 3.355 M -CKEout C14M F 10.424 4 3.355 M -DQMH C14M R 10.404 4 3.362 M -DQML C14M R 10.404 4 3.362 M -LED C14M R 22.936 4 8.890 M -RAout[0] C14M F 10.490 4 3.360 M -RAout[10] C14M F 10.490 4 3.360 M -RAout[11] C14M F 10.424 4 3.355 M -RAout[1] C14M F 10.490 4 3.360 M -RAout[2] C14M F 10.490 4 3.360 M -RAout[3] C14M F 10.490 4 3.360 M -RAout[4] C14M F 10.490 4 3.360 M -RAout[5] C14M F 10.490 4 3.360 M -RAout[6] C14M F 10.490 4 3.360 M -RAout[7] C14M F 10.490 4 3.360 M -RAout[8] C14M F 10.490 4 3.360 M -RAout[9] C14M F 10.490 4 3.360 M -RD[0] C14M R 13.733 4 3.707 M -RD[1] C14M R 13.745 4 3.707 M -RD[2] C14M R 14.285 4 3.790 M -RD[3] C14M R 13.348 4 3.790 M -RD[4] C14M R 14.450 4 3.952 M -RD[5] C14M R 14.480 4 3.952 M -RD[6] C14M R 14.784 4 3.952 M -RD[7] C14M R 14.247 4 3.952 M -Vout[0] C14M R 11.348 4 3.872 M -Vout[1] C14M R 11.434 4 3.871 M -Vout[2] C14M R 11.348 4 3.872 M -Vout[3] C14M R 11.434 4 3.871 M -Vout[4] C14M R 11.348 4 3.872 M -Vout[5] C14M R 11.348 4 3.872 M -Vout[6] C14M R 11.434 4 3.871 M -Vout[7] C14M R 11.434 4 3.871 M -nCASout C14M F 10.424 4 3.355 M -nDOE C14M R 13.929 4 4.309 M -nRASout C14M F 10.424 4 3.355 M -nRWEout C14M F 10.424 4 3.355 M -nVOE C14M R 13.926 4 4.281 M -WARNING: you must also run trce with hold speed: 4 -WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-1200HC/msg_file.log b/CPLD/LCMXO2-1200HC/msg_file.log deleted file mode 100644 index e3ee81e..0000000 --- a/CPLD/LCMXO2-1200HC/msg_file.log +++ /dev/null @@ -1,29 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.12.1.454 -Wed Sep 20 04:45:58 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 - Circuit name : REFB - Module type : efb - Module Version : 1.2 - Ports : - Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] - Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq - I/O buffer : not inserted - EDIF output : REFB.edn - Verilog output : REFB.v - Verilog template : REFB_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : REFB.srp - Estimated Resource Usage: - -END SCUBA Module Synthesis - diff --git a/CPLD/LCMXO2-1200HC/promote.xml b/CPLD/LCMXO2-1200HC/promote.xml deleted file mode 100644 index 5c9d512..0000000 --- a/CPLD/LCMXO2-1200HC/promote.xml +++ /dev/null @@ -1,3 +0,0 @@ - - - diff --git a/CPLD/LCMXO2-1200HC/reportview.xml b/CPLD/LCMXO2-1200HC/reportview.xml deleted file mode 100644 index 7c96405..0000000 --- a/CPLD/LCMXO2-1200HC/reportview.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - - diff --git a/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html deleted file mode 100644 index 0a46512..0000000 --- a/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html +++ /dev/null @@ -1,106 +0,0 @@ - -Lattice TCL Log - - -
    pn231205230924
-#Start recording tcl command: 12/5/2023 14:55:22
-#Project Location: //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
-prj_project open "//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-prj_project save
-prj_project close
-#Stop recording: 12/5/2023 23:09:24
-
-
-
-pn231226232445
-#Start recording tcl command: 12/26/2023 18:23:53
-#Project Location: //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
-prj_project open "//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-prj_run Export -impl impl1 -task IBIS
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-prj_run Export -impl impl1
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1
-prj_run Export -impl impl1 -forceAll
-prj_run Export -impl impl1 -forceAll
-prj_src remove "//Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.v"
-#Stop recording: 12/26/2023 23:24:45
-
-
-
-pn231228232403
-#Start recording tcl command: 12/28/2023 23:23:13
-#Project Location: //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
-prj_project open "//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
-prj_run Export -impl impl1
-#Stop recording: 12/28/2023 23:24:03
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    - - diff --git a/CPLD/LCMXO2-640HC/REFB.edn b/CPLD/LCMXO2-640HC/REFB.edn deleted file mode 100644 index 3040a1d..0000000 --- a/CPLD/LCMXO2-640HC/REFB.edn +++ /dev/null @@ -1,550 +0,0 @@ -(edif REFB - (edifVersion 2 0 0) - (edifLevel 0) - (keywordMap (keywordLevel 0)) - (status - (written - (timestamp 2023 9 20 4 17 14) - (program "SCUBA" (version "Diamond (64-bit) 3.12.1.454")))) - (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 ") - (library ORCLIB - (edifLevel 0) - (technology - (numberDefinition)) - (cell VHI - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port Z - (direction OUTPUT))))) - (cell VLO - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port Z - (direction OUTPUT))))) - (cell EFB - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port WBCLKI - (direction INPUT)) - (port WBRSTI - (direction INPUT)) - (port WBCYCI - (direction INPUT)) - (port WBSTBI - (direction INPUT)) - (port WBWEI - (direction INPUT)) - (port WBADRI7 - (direction INPUT)) - (port WBADRI6 - (direction INPUT)) - (port WBADRI5 - (direction INPUT)) - (port WBADRI4 - (direction INPUT)) - (port WBADRI3 - (direction INPUT)) - (port WBADRI2 - (direction INPUT)) - (port WBADRI1 - (direction INPUT)) - (port WBADRI0 - (direction INPUT)) - (port WBDATI7 - (direction INPUT)) - (port WBDATI6 - (direction INPUT)) - (port WBDATI5 - (direction INPUT)) - (port WBDATI4 - (direction INPUT)) - (port WBDATI3 - (direction INPUT)) - (port WBDATI2 - (direction INPUT)) - (port WBDATI1 - (direction INPUT)) - (port WBDATI0 - (direction INPUT)) - (port PLL0DATI7 - (direction INPUT)) - (port PLL0DATI6 - (direction INPUT)) - (port PLL0DATI5 - (direction INPUT)) - (port PLL0DATI4 - (direction INPUT)) - (port PLL0DATI3 - (direction INPUT)) - (port PLL0DATI2 - (direction INPUT)) - (port PLL0DATI1 - (direction INPUT)) - (port PLL0DATI0 - (direction INPUT)) - (port PLL0ACKI - (direction INPUT)) - (port PLL1DATI7 - (direction INPUT)) - (port PLL1DATI6 - (direction INPUT)) - (port PLL1DATI5 - (direction INPUT)) - (port PLL1DATI4 - (direction INPUT)) - (port PLL1DATI3 - (direction INPUT)) - (port PLL1DATI2 - (direction INPUT)) - (port PLL1DATI1 - (direction INPUT)) - (port PLL1DATI0 - (direction INPUT)) - (port PLL1ACKI - (direction INPUT)) - (port I2C1SCLI - (direction INPUT)) - (port I2C1SDAI - (direction INPUT)) - (port I2C2SCLI - (direction INPUT)) - (port I2C2SDAI - (direction INPUT)) - (port SPISCKI - (direction INPUT)) - (port SPIMISOI - (direction INPUT)) - (port SPIMOSII - (direction INPUT)) - (port SPISCSN - (direction INPUT)) - (port TCCLKI - (direction INPUT)) - (port TCRSTN - (direction INPUT)) - (port TCIC - (direction INPUT)) - (port UFMSN - (direction INPUT)) - (port WBDATO7 - (direction OUTPUT)) - (port WBDATO6 - (direction OUTPUT)) - (port WBDATO5 - (direction OUTPUT)) - (port WBDATO4 - (direction OUTPUT)) - (port WBDATO3 - (direction OUTPUT)) - (port WBDATO2 - (direction OUTPUT)) - (port WBDATO1 - (direction OUTPUT)) - (port WBDATO0 - (direction OUTPUT)) - (port WBACKO - (direction OUTPUT)) - (port PLLCLKO - (direction OUTPUT)) - (port PLLRSTO - (direction OUTPUT)) - (port PLL0STBO - (direction OUTPUT)) - (port PLL1STBO - (direction OUTPUT)) - (port PLLWEO - (direction OUTPUT)) - (port PLLADRO4 - (direction OUTPUT)) - (port PLLADRO3 - (direction OUTPUT)) - (port PLLADRO2 - (direction OUTPUT)) - (port PLLADRO1 - (direction OUTPUT)) - (port PLLADRO0 - (direction OUTPUT)) - (port PLLDATO7 - (direction OUTPUT)) - (port PLLDATO6 - (direction OUTPUT)) - (port PLLDATO5 - (direction OUTPUT)) - (port PLLDATO4 - (direction OUTPUT)) - (port PLLDATO3 - (direction OUTPUT)) - (port PLLDATO2 - (direction OUTPUT)) - (port PLLDATO1 - (direction OUTPUT)) - (port PLLDATO0 - (direction OUTPUT)) - (port I2C1SCLO - (direction OUTPUT)) - (port I2C1SCLOEN - (direction OUTPUT)) - (port I2C1SDAO - (direction OUTPUT)) - (port I2C1SDAOEN - (direction OUTPUT)) - (port I2C2SCLO - (direction OUTPUT)) - (port I2C2SCLOEN - (direction OUTPUT)) - (port I2C2SDAO - (direction OUTPUT)) - (port I2C2SDAOEN - (direction OUTPUT)) - (port I2C1IRQO - (direction OUTPUT)) - (port I2C2IRQO - (direction OUTPUT)) - (port SPISCKO - (direction OUTPUT)) - (port SPISCKEN - (direction OUTPUT)) - (port SPIMISOO - (direction OUTPUT)) - (port SPIMISOEN - (direction OUTPUT)) - (port SPIMOSIO - (direction OUTPUT)) - (port SPIMOSIEN - (direction OUTPUT)) - (port SPIMCSN7 - (direction OUTPUT)) - (port SPIMCSN6 - (direction OUTPUT)) - (port SPIMCSN5 - (direction OUTPUT)) - (port SPIMCSN4 - (direction OUTPUT)) - (port SPIMCSN3 - (direction OUTPUT)) - (port SPIMCSN2 - (direction OUTPUT)) - (port SPIMCSN1 - (direction OUTPUT)) - (port SPIMCSN0 - (direction OUTPUT)) - (port SPICSNEN - (direction OUTPUT)) - (port SPIIRQO - (direction OUTPUT)) - (port TCINT - (direction OUTPUT)) - (port TCOC - (direction OUTPUT)) - (port WBCUFMIRQ - (direction OUTPUT)) - (port CFGWAKE - (direction OUTPUT)) - (port CFGSTDBY - (direction OUTPUT))))) - (cell REFB - (cellType GENERIC) - (view view1 - (viewType NETLIST) - (interface - (port wb_clk_i - (direction INPUT)) - (port wb_rst_i - (direction INPUT)) - (port wb_cyc_i - (direction INPUT)) - (port wb_stb_i - (direction INPUT)) - (port wb_we_i - (direction INPUT)) - (port (array (rename wb_adr_i "wb_adr_i(7:0)") 8) - (direction INPUT)) - (port (array (rename wb_dat_i "wb_dat_i(7:0)") 8) - (direction INPUT)) - (port (array (rename wb_dat_o "wb_dat_o(7:0)") 8) - (direction OUTPUT)) - (port wb_ack_o - (direction OUTPUT)) - (port wbc_ufm_irq - (direction OUTPUT))) - (property NGD_DRC_MASK (integer 1)) - (contents - (instance scuba_vhi_inst - (viewRef view1 - (cellRef VHI))) - (instance scuba_vlo_inst - (viewRef view1 - (cellRef VLO))) - (instance EFBInst_0 - (viewRef view1 - (cellRef EFB)) - (property UFM_INIT_FILE_FORMAT - (string "HEX")) - (property UFM_INIT_FILE_NAME - (string "../RAM2E-LCMXO2.mem")) - (property UFM_INIT_ALL_ZEROS - (string "DISABLED")) - (property UFM_INIT_START_PAGE - (string "190")) - (property UFM_INIT_PAGES - (string "1")) - (property DEV_DENSITY - (string "640L")) - (property EFB_UFM - (string "ENABLED")) - (property TC_ICAPTURE - (string "DISABLED")) - (property TC_OVERFLOW - (string "DISABLED")) - (property TC_ICR_INT - (string "OFF")) - (property TC_OCR_INT - (string "OFF")) - (property TC_OV_INT - (string "OFF")) - (property TC_TOP_SEL - (string "OFF")) - (property TC_RESETN - (string "ENABLED")) - (property TC_OC_MODE - (string "TOGGLE")) - (property TC_OCR_SET - (string "32767")) - (property TC_TOP_SET - (string "65535")) - (property GSR - (string "ENABLED")) - (property TC_CCLK_SEL - (string "1")) - (property TC_MODE - (string "CTCM")) - (property TC_SCLK_SEL - (string "PCLOCK")) - (property EFB_TC_PORTMODE - (string "WB")) - (property EFB_TC - (string "DISABLED")) - (property SPI_WAKEUP - (string "DISABLED")) - (property SPI_INTR_RXOVR - (string "DISABLED")) - (property SPI_INTR_TXOVR - (string "DISABLED")) - (property SPI_INTR_RXRDY - (string "DISABLED")) - (property SPI_INTR_TXRDY - (string "DISABLED")) - (property SPI_SLAVE_HANDSHAKE - (string "DISABLED")) - (property SPI_PHASE_ADJ - (string "DISABLED")) - (property SPI_CLK_INV - (string "DISABLED")) - (property SPI_LSB_FIRST - (string "DISABLED")) - (property SPI_CLK_DIVIDER - (string "1")) - (property SPI_MODE - (string "MASTER")) - (property EFB_SPI - (string "DISABLED")) - (property I2C2_WAKEUP - (string "DISABLED")) - (property I2C2_GEN_CALL - (string "DISABLED")) - (property I2C2_CLK_DIVIDER - (string "1")) - (property I2C2_BUS_PERF - (string "100kHz")) - (property I2C2_SLAVE_ADDR - (string "0b1000010")) - (property I2C2_ADDRESSING - (string "7BIT")) - (property EFB_I2C2 - (string "DISABLED")) - (property I2C1_WAKEUP - (string "DISABLED")) - (property I2C1_GEN_CALL - (string "DISABLED")) - (property I2C1_CLK_DIVIDER - (string "1")) - (property I2C1_BUS_PERF - (string "100kHz")) - (property I2C1_SLAVE_ADDR - (string "0b1000001")) - (property I2C1_ADDRESSING - (string "7BIT")) - (property EFB_I2C1 - (string "DISABLED")) - (property EFB_WB_CLK_FREQ - (string "14.4"))) - (net scuba_vhi - (joined - (portRef Z (instanceRef scuba_vhi_inst)) - (portRef UFMSN (instanceRef EFBInst_0)))) - (net scuba_vlo - (joined - (portRef Z (instanceRef scuba_vlo_inst)) - (portRef PLL1DATI7 (instanceRef EFBInst_0)) - (portRef PLL1DATI6 (instanceRef EFBInst_0)) - (portRef PLL1DATI5 (instanceRef EFBInst_0)) - (portRef PLL1DATI4 (instanceRef EFBInst_0)) - (portRef PLL1DATI3 (instanceRef EFBInst_0)) - (portRef PLL1DATI2 (instanceRef EFBInst_0)) - (portRef PLL1DATI1 (instanceRef EFBInst_0)) - (portRef PLL1DATI0 (instanceRef EFBInst_0)) - (portRef PLL1ACKI (instanceRef EFBInst_0)) - (portRef PLL0DATI7 (instanceRef EFBInst_0)) - (portRef PLL0DATI6 (instanceRef EFBInst_0)) - (portRef PLL0DATI5 (instanceRef EFBInst_0)) - (portRef PLL0DATI4 (instanceRef EFBInst_0)) - (portRef PLL0DATI3 (instanceRef EFBInst_0)) - (portRef PLL0DATI2 (instanceRef EFBInst_0)) - (portRef PLL0DATI1 (instanceRef EFBInst_0)) - (portRef PLL0DATI0 (instanceRef EFBInst_0)) - (portRef PLL0ACKI (instanceRef EFBInst_0)) - (portRef TCIC (instanceRef EFBInst_0)) - (portRef TCRSTN (instanceRef EFBInst_0)) - (portRef TCCLKI (instanceRef EFBInst_0)) - (portRef SPISCSN (instanceRef EFBInst_0)) - (portRef SPIMOSII (instanceRef EFBInst_0)) - (portRef SPIMISOI (instanceRef EFBInst_0)) - (portRef SPISCKI (instanceRef EFBInst_0)) - (portRef I2C2SDAI (instanceRef EFBInst_0)) - (portRef I2C2SCLI (instanceRef EFBInst_0)) - (portRef I2C1SDAI (instanceRef EFBInst_0)) - (portRef I2C1SCLI (instanceRef EFBInst_0)))) - (net wbc_ufm_irq - (joined - (portRef wbc_ufm_irq) - (portRef WBCUFMIRQ (instanceRef EFBInst_0)))) - (net wb_ack_o - (joined - (portRef wb_ack_o) - (portRef WBACKO (instanceRef EFBInst_0)))) - (net wb_dat_o7 - (joined - (portRef (member wb_dat_o 0)) - (portRef WBDATO7 (instanceRef EFBInst_0)))) - (net wb_dat_o6 - (joined - (portRef (member wb_dat_o 1)) - (portRef WBDATO6 (instanceRef EFBInst_0)))) - (net wb_dat_o5 - (joined - (portRef (member wb_dat_o 2)) - (portRef WBDATO5 (instanceRef EFBInst_0)))) - (net wb_dat_o4 - (joined - (portRef (member wb_dat_o 3)) - (portRef WBDATO4 (instanceRef EFBInst_0)))) - (net wb_dat_o3 - (joined - (portRef (member wb_dat_o 4)) - (portRef WBDATO3 (instanceRef EFBInst_0)))) - (net wb_dat_o2 - (joined - (portRef (member wb_dat_o 5)) - (portRef WBDATO2 (instanceRef EFBInst_0)))) - (net wb_dat_o1 - (joined - (portRef (member wb_dat_o 6)) - (portRef WBDATO1 (instanceRef EFBInst_0)))) - (net wb_dat_o0 - (joined - (portRef (member wb_dat_o 7)) - (portRef WBDATO0 (instanceRef EFBInst_0)))) - (net wb_dat_i7 - (joined - (portRef (member wb_dat_i 0)) - (portRef WBDATI7 (instanceRef EFBInst_0)))) - (net wb_dat_i6 - (joined - (portRef (member wb_dat_i 1)) - (portRef WBDATI6 (instanceRef EFBInst_0)))) - (net wb_dat_i5 - (joined - (portRef (member wb_dat_i 2)) - (portRef WBDATI5 (instanceRef EFBInst_0)))) - (net wb_dat_i4 - (joined - (portRef (member wb_dat_i 3)) - (portRef WBDATI4 (instanceRef EFBInst_0)))) - (net wb_dat_i3 - (joined - (portRef (member wb_dat_i 4)) - (portRef WBDATI3 (instanceRef EFBInst_0)))) - (net wb_dat_i2 - (joined - (portRef (member wb_dat_i 5)) - (portRef WBDATI2 (instanceRef EFBInst_0)))) - (net wb_dat_i1 - (joined - (portRef (member wb_dat_i 6)) - (portRef WBDATI1 (instanceRef EFBInst_0)))) - (net wb_dat_i0 - (joined - (portRef (member wb_dat_i 7)) - (portRef WBDATI0 (instanceRef EFBInst_0)))) - (net wb_adr_i7 - (joined - (portRef (member wb_adr_i 0)) - (portRef WBADRI7 (instanceRef EFBInst_0)))) - (net wb_adr_i6 - (joined - (portRef (member wb_adr_i 1)) - (portRef WBADRI6 (instanceRef EFBInst_0)))) - (net wb_adr_i5 - (joined - (portRef (member wb_adr_i 2)) - (portRef WBADRI5 (instanceRef EFBInst_0)))) - (net wb_adr_i4 - (joined - (portRef (member wb_adr_i 3)) - (portRef WBADRI4 (instanceRef EFBInst_0)))) - (net wb_adr_i3 - (joined - (portRef (member wb_adr_i 4)) - (portRef WBADRI3 (instanceRef EFBInst_0)))) - (net wb_adr_i2 - (joined - (portRef (member wb_adr_i 5)) - (portRef WBADRI2 (instanceRef EFBInst_0)))) - (net wb_adr_i1 - (joined - (portRef (member wb_adr_i 6)) - (portRef WBADRI1 (instanceRef EFBInst_0)))) - (net wb_adr_i0 - (joined - (portRef (member wb_adr_i 7)) - (portRef WBADRI0 (instanceRef EFBInst_0)))) - (net wb_we_i - (joined - (portRef wb_we_i) - (portRef WBWEI (instanceRef EFBInst_0)))) - (net wb_stb_i - (joined - (portRef wb_stb_i) - (portRef WBSTBI (instanceRef EFBInst_0)))) - (net wb_cyc_i - (joined - (portRef wb_cyc_i) - (portRef WBCYCI (instanceRef EFBInst_0)))) - (net wb_rst_i - (joined - (portRef wb_rst_i) - (portRef WBRSTI (instanceRef EFBInst_0)))) - (net wb_clk_i - (joined - (portRef wb_clk_i) - (portRef WBCLKI (instanceRef EFBInst_0)))))))) - (design REFB - (cellRef REFB - (libraryRef ORCLIB))) -) diff --git a/CPLD/LCMXO2-640HC/REFB.lpc b/CPLD/LCMXO2-640HC/REFB.lpc deleted file mode 100644 index 6bd84ca..0000000 --- a/CPLD/LCMXO2-640HC/REFB.lpc +++ /dev/null @@ -1,141 +0,0 @@ -[Device] -Family=machxo2 -PartType=LCMXO2-640HC -PartName=LCMXO2-640HC-4TG100C -SpeedGrade=4 -Package=TQFP100 -OperatingCondition=COM -Status=S - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=EFB -CoreRevision=1.2 -ModuleName=REFB -SourceFormat=Verilog HDL -ParameterFileVersion=1.0 -Date=09/20/2023 -Time=04:17:14 - -[Parameters] -Verilog=1 -VHDL=0 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -freq= -i2c1=0 -i2c1config=0 -i2c1_addr=7-Bit Addressing -i2c1_ce=0 -i2c1_freq=100 -i2c1_sa=10000 -i2c1_we=0 -i2c2=0 -i2c2_addr=7-Bit Addressing -i2c2_ce=0 -i2c2_freq=100 -i2c2_sa=10000 -i2c2_we=0 -ufm_addr=7-Bit Addressing -ufm_sa=10000 -pll=0 -pll_cnt=1 -spi=0 -spi_clkinv=0 -spi_cs=1 -spi_en=0 -spi_freq=1 -spi_lsb=0 -spi_mode=Slave -spi_ib=0 -spi_ph=0 -spi_hs=0 -spi_rxo=0 -spi_rxr=0 -spi_txo=0 -spi_txr=0 -spi_we=0 -static_tc=Static -tc=0 -tc_clkinv=Positive -tc_ctr=1 -tc_div=1 -tc_ipcap=0 -tc_mode=CTCM -tc_ocr=32767 -tc_oflow=1 -tc_o=TOGGLE -tc_opcomp=0 -tc_osc=0 -tc_sa_oflow=0 -tc_top=65535 -ufm=1 -ufm0=0 -ufm1=0 -ufm2=0 -ufm3=0 -ufm_cfg0=0 -ufm_cfg1=0 -wb_clk_freq=14.4 -ufm_usage=SHARED_EBR_TAG -ufm_ebr=190 -ufm_remain= -mem_size=1 -ufm_start= -ufm_init=mem -memfile=../RAM2E-LCMXO2.mem -ufm_dt=hex -ufm0_ebr= -mem_size0=1 -ufm0_init=0 -memfile0= -ufm0_dt=hex -ufm1_ebr= -mem_size1=1 -ufm1_init=0 -memfile1= -ufm1_dt=hex -ufm2_ebr= -mem_size2=1 -ufm2_init=0 -memfile2= -ufm2_dt=hex -ufm3_ebr= -mem_size3=1 -ufm3_init=0 -memfile3= -ufm3_dt=hex -ufm_cfg0_ebr= -mem_size_cfg0=1 -ufm_cfg0_init=0 -memfile_cfg0= -ufm_cfg0_dt=hex -ufm_cfg1_ebr= -mem_size_cfg1=1 -ufm_cfg1_init=0 -memfile_cfg1= -ufm_cfg1_dt=hex -wb=1 -boot_option=Internal -efb_ufm=0 -boot_option_internal=Single Boot -internal_ufm0=0 -internal_ufm1=0 -efb_ufm_boot= -tamperdr=0 -t_pwd=0 -t_lockflash=0 -t_manmode=0 -t_jtagport=0 -t_sspiport=0 -t_sic2port=0 -t_wbport=0 -t_portlock=0 - -[Command] -cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 diff --git a/CPLD/LCMXO2-640HC/REFB.naf b/CPLD/LCMXO2-640HC/REFB.naf deleted file mode 100644 index 5c239f5..0000000 --- a/CPLD/LCMXO2-640HC/REFB.naf +++ /dev/null @@ -1,31 +0,0 @@ -wb_clk_i i -wb_rst_i i -wb_cyc_i i -wb_stb_i i -wb_we_i i -wb_adr_i[7] i -wb_adr_i[6] i -wb_adr_i[5] i -wb_adr_i[4] i -wb_adr_i[3] i -wb_adr_i[2] i -wb_adr_i[1] i -wb_adr_i[0] i -wb_dat_i[7] i -wb_dat_i[6] i -wb_dat_i[5] i -wb_dat_i[4] i -wb_dat_i[3] i -wb_dat_i[2] i -wb_dat_i[1] i -wb_dat_i[0] i -wb_dat_o[7] o -wb_dat_o[6] o -wb_dat_o[5] o -wb_dat_o[4] o -wb_dat_o[3] o -wb_dat_o[2] o -wb_dat_o[1] o -wb_dat_o[0] o -wb_ack_o o -wbc_ufm_irq o diff --git a/CPLD/LCMXO2-640HC/REFB.sort b/CPLD/LCMXO2-640HC/REFB.sort deleted file mode 100644 index 96fe0d5..0000000 --- a/CPLD/LCMXO2-640HC/REFB.sort +++ /dev/null @@ -1 +0,0 @@ -REFB.v diff --git a/CPLD/LCMXO2-640HC/REFB.srp b/CPLD/LCMXO2-640HC/REFB.srp deleted file mode 100644 index 95501ab..0000000 --- a/CPLD/LCMXO2-640HC/REFB.srp +++ /dev/null @@ -1,26 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.12.1.454 -Wed Sep 20 04:17:14 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - - Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 - Circuit name : REFB - Module type : efb - Module Version : 1.2 - Ports : - Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] - Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq - I/O buffer : not inserted - EDIF output : REFB.edn - Verilog output : REFB.v - Verilog template : REFB_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : REFB.srp - Element Usage : - EFB : 1 - Estimated Resource Usage: diff --git a/CPLD/LCMXO2-640HC/REFB.sym b/CPLD/LCMXO2-640HC/REFB.sym deleted file mode 100644 index 6588d30..0000000 Binary files a/CPLD/LCMXO2-640HC/REFB.sym and /dev/null differ diff --git a/CPLD/LCMXO2-640HC/REFB_generate.log b/CPLD/LCMXO2-640HC/REFB_generate.log deleted file mode 100644 index 3c32a89..0000000 --- a/CPLD/LCMXO2-640HC/REFB_generate.log +++ /dev/null @@ -1,44 +0,0 @@ -Starting process: Module - -Starting process: - -SCUBA, Version Diamond (64-bit) 3.12.1.454 -Wed Sep 20 04:17:14 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 - Circuit name : REFB - Module type : efb - Module Version : 1.2 - Ports : - Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] - Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq - I/O buffer : not inserted - EDIF output : REFB.edn - Verilog output : REFB.v - Verilog template : REFB_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : REFB.srp - Estimated Resource Usage: - -END SCUBA Module Synthesis - -File: REFB.lpc created. - - -End process: completed successfully. - - -Total Warnings: 0 - -Total Errors: 0 - - diff --git a/CPLD/LCMXO2-640HC/REFB_tmpl.v b/CPLD/LCMXO2-640HC/REFB_tmpl.v deleted file mode 100644 index 4f87825..0000000 --- a/CPLD/LCMXO2-640HC/REFB_tmpl.v +++ /dev/null @@ -1,8 +0,0 @@ -/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */ -/* Module Version: 1.2 */ -/* Wed Sep 20 04:17:14 2023 */ - -/* parameterized module instance */ -REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), - .wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ), - .wbc_ufm_irq( )); diff --git a/CPLD/LCMXO2-640HC/_math_real.vhd b/CPLD/LCMXO2-640HC/_math_real.vhd deleted file mode 100644 index e1215d8..0000000 --- a/CPLD/LCMXO2-640HC/_math_real.vhd +++ /dev/null @@ -1,2574 +0,0 @@ - - ------------------------------------------------------------------------- --- --- Copyright 1996 by IEEE. All rights reserved. --- --- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard --- VHDL Mathematical Packages. This source file may not be copied, sold, or --- included with software that is sold without written permission from the IEEE --- Standards Department. This source file may be used to implement this standard --- and may be distributed in compiled form in any manner so long as the --- compiled form does not allow direct decompilation of the original source file. --- This source file may be copied for individual use between licensed users. --- This source file is provided on an AS IS basis. The IEEE disclaims ANY --- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY --- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source --- file shall indemnify and hold IEEE harmless from any damages or liability --- arising out of the use thereof. --- --- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, --- MATH_REAL) --- --- Library: This package shall be compiled into a library --- symbolically named IEEE. --- --- Developers: IEEE DASC VHDL Mathematical Packages Working Group --- --- Purpose: This package defines a standard for designers to use in --- describing VHDL models that make use of common REAL constants --- and common REAL elementary mathematical functions. --- --- Limitation: The values generated by the functions in this package may --- vary from platform to platform, and the precision of results --- is only guaranteed to be the minimum required by IEEE Std 1076- --- 1993. --- --- Notes: --- No declarations or definitions shall be included in, or --- excluded from, this package. --- The "package declaration" defines the types, subtypes, and --- declarations of MATH_REAL. --- The standard mathematical definition and conventional meaning --- of the mathematical functions that are part of this standard --- represent the formal semantics of the implementation of the --- MATH_REAL package declaration. The purpose of the MATH_REAL --- package body is to provide a guideline for implementations to --- verify their implementation of MATH_REAL. Tool developers may --- choose to implement the package body in the most efficient --- manner available to them. --- --- ----------------------------------------------------------------------------- --- Version : 1.5 --- Date : 24 July 1996 --- ----------------------------------------------------------------------------- - -package MATH_REAL is - constant CopyRightNotice: STRING - := "Copyright 1996 IEEE. All rights reserved."; - - -- - -- Constant Definitions - -- - constant MATH_E : REAL := 2.71828_18284_59045_23536; - -- Value of e - constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; - -- Value of 1/e - constant MATH_PI : REAL := 3.14159_26535_89793_23846; - -- Value of pi - constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; - -- Value of 2*pi - constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; - -- Value of 1/pi - constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; - -- Value of pi/2 - constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; - -- Value of pi/3 - constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; - -- Value of pi/4 - constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; - -- Value 3*pi/2 - constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; - -- Natural log of 2 - constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; - -- Natural log of 10 - constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; - -- Log base 2 of e - constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; - -- Log base 10 of e - constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; - -- square root of 2 - constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; - -- square root of 1/2 - constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; - -- square root of pi - constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; - -- Conversion factor from degree to radian - constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; - -- Conversion factor from radian to degree - - -- - -- Function Declarations - -- - function SIGN (X: in REAL ) return REAL; - -- Purpose: - -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 - -- Special values: - -- None - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(SIGN(X)) <= 1.0 - -- Notes: - -- None - - function CEIL (X : in REAL ) return REAL; - -- Purpose: - -- Returns smallest INTEGER value (as REAL) not less than X - -- Special values: - -- None - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- CEIL(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function FLOOR (X : in REAL ) return REAL; - -- Purpose: - -- Returns largest INTEGER value (as REAL) not greater than X - -- Special values: - -- FLOOR(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- FLOOR(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function ROUND (X : in REAL ) return REAL; - -- Purpose: - -- Rounds X to the nearest integer value (as real). If X is - -- halfway between two integers, rounding is away from 0.0 - -- Special values: - -- ROUND(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ROUND(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function TRUNC (X : in REAL ) return REAL; - -- Purpose: - -- Truncates X towards 0.0 and returns truncated value - -- Special values: - -- TRUNC(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- TRUNC(X) is mathematically unbounded - -- Notes: - -- a) Implementations have to support at least the domain - -- ABS(X) < REAL(INTEGER'HIGH) - - function "MOD" (X, Y: in REAL ) return REAL; - -- Purpose: - -- Returns floating point modulus of X/Y, with the same sign as - -- Y, and absolute value less than the absolute value of Y, and - -- for some INTEGER value N the result satisfies the relation - -- X = Y*N + MOD(X,Y) - -- Special values: - -- None - -- Domain: - -- X in REAL; Y in REAL and Y /= 0.0 - -- Error conditions: - -- Error if Y = 0.0 - -- Range: - -- ABS(MOD(X,Y)) < ABS(Y) - -- Notes: - -- None - - function REALMAX (X, Y : in REAL ) return REAL; - -- Purpose: - -- Returns the algebraically larger of X and Y - -- Special values: - -- REALMAX(X,Y) = X when X = Y - -- Domain: - -- X in REAL; Y in REAL - -- Error conditions: - -- None - -- Range: - -- REALMAX(X,Y) is mathematically unbounded - -- Notes: - -- None - - function REALMIN (X, Y : in REAL ) return REAL; - -- Purpose: - -- Returns the algebraically smaller of X and Y - -- Special values: - -- REALMIN(X,Y) = X when X = Y - -- Domain: - -- X in REAL; Y in REAL - -- Error conditions: - -- None - -- Range: - -- REALMIN(X,Y) is mathematically unbounded - -- Notes: - -- None - - procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); - -- Purpose: - -- Returns, in X, a pseudo-random number with uniform - -- distribution in the open interval (0.0, 1.0). - -- Special values: - -- None - -- Domain: - -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 - -- Error conditions: - -- Error if SEED1 or SEED2 outside of valid domain - -- Range: - -- 0.0 < X < 1.0 - -- Notes: - -- a) The semantics for this function are described by the - -- algorithm published by Pierre L'Ecuyer in "Communications - -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. - -- The algorithm is based on the combination of two - -- multiplicative linear congruential generators for 32-bit - -- platforms. - -- - -- b) Before the first call to UNIFORM, the seed values - -- (SEED1, SEED2) have to be initialized to values in the range - -- [1, 2147483562] and [1, 2147483398] respectively. The - -- seed values are modified after each call to UNIFORM. - -- - -- c) This random number generator is portable for 32-bit - -- computers, and it has a period of ~2.30584*(10**18) for each - -- set of seed values. - -- - -- d) For information on spectral tests for the algorithm, refer - -- to the L'Ecuyer article. - - function SQRT (X : in REAL ) return REAL; - -- Purpose: - -- Returns square root of X - -- Special values: - -- SQRT(0.0) = 0.0 - -- SQRT(1.0) = 1.0 - -- Domain: - -- X >= 0.0 - -- Error conditions: - -- Error if X < 0.0 - -- Range: - -- SQRT(X) >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range of SQRT is - -- approximately given by: - -- SQRT(X) <= SQRT(REAL'HIGH) - - function CBRT (X : in REAL ) return REAL; - -- Purpose: - -- Returns cube root of X - -- Special values: - -- CBRT(0.0) = 0.0 - -- CBRT(1.0) = 1.0 - -- CBRT(-1.0) = -1.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- CBRT(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of CBRT is approximately given by: - -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) - - function "**" (X : in INTEGER; Y : in REAL) return REAL; - -- Purpose: - -- Returns Y power of X ==> X**Y - -- Special values: - -- X**0.0 = 1.0; X /= 0 - -- 0**Y = 0.0; Y > 0.0 - -- X**1.0 = REAL(X); X >= 0 - -- 1**Y = 1.0 - -- Domain: - -- X > 0 - -- X = 0 for Y > 0.0 - -- X < 0 for Y = 0.0 - -- Error conditions: - -- Error if X < 0 and Y /= 0.0 - -- Error if X = 0 and Y <= 0.0 - -- Range: - -- X**Y >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range for "**" is - -- approximately given by: - -- X**Y <= REAL'HIGH - - function "**" (X : in REAL; Y : in REAL) return REAL; - -- Purpose: - -- Returns Y power of X ==> X**Y - -- Special values: - -- X**0.0 = 1.0; X /= 0.0 - -- 0.0**Y = 0.0; Y > 0.0 - -- X**1.0 = X; X >= 0.0 - -- 1.0**Y = 1.0 - -- Domain: - -- X > 0.0 - -- X = 0.0 for Y > 0.0 - -- X < 0.0 for Y = 0.0 - -- Error conditions: - -- Error if X < 0.0 and Y /= 0.0 - -- Error if X = 0.0 and Y <= 0.0 - -- Range: - -- X**Y >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range for "**" is - -- approximately given by: - -- X**Y <= REAL'HIGH - - function EXP (X : in REAL ) return REAL; - -- Purpose: - -- Returns e**X; where e = MATH_E - -- Special values: - -- EXP(0.0) = 1.0 - -- EXP(1.0) = MATH_E - -- EXP(-1.0) = MATH_1_OVER_E - -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) - -- Domain: - -- X in REAL such that EXP(X) <= REAL'HIGH - -- Error conditions: - -- Error if X > LOG(REAL'HIGH) - -- Range: - -- EXP(X) >= 0.0 - -- Notes: - -- a) The usable domain of EXP is approximately given by: - -- X <= LOG(REAL'HIGH) - - function LOG (X : in REAL ) return REAL; - -- Purpose: - -- Returns natural logarithm of X - -- Special values: - -- LOG(1.0) = 0.0 - -- LOG(MATH_E) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG is approximately given by: - -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) - - function LOG2 (X : in REAL ) return REAL; - -- Purpose: - -- Returns logarithm base 2 of X - -- Special values: - -- LOG2(1.0) = 0.0 - -- LOG2(2.0) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG2(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG2 is approximately given by: - -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) - - function LOG10 (X : in REAL ) return REAL; - -- Purpose: - -- Returns logarithm base 10 of X - -- Special values: - -- LOG10(1.0) = 0.0 - -- LOG10(10.0) = 1.0 - -- Domain: - -- X > 0.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Range: - -- LOG10(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of LOG10 is approximately given by: - -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) - - function LOG (X: in REAL; BASE: in REAL) return REAL; - -- Purpose: - -- Returns logarithm base BASE of X - -- Special values: - -- LOG(1.0, BASE) = 0.0 - -- LOG(BASE, BASE) = 1.0 - -- Domain: - -- X > 0.0 - -- BASE > 0.0 - -- BASE /= 1.0 - -- Error conditions: - -- Error if X <= 0.0 - -- Error if BASE <= 0.0 - -- Error if BASE = 1.0 - -- Range: - -- LOG(X, BASE) is mathematically unbounded - -- Notes: - -- a) When BASE > 1.0, the reachable range of LOG is - -- approximately given by: - -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) - -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is - -- approximately given by: - -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) - - function SIN (X : in REAL ) return REAL; - -- Purpose: - -- Returns sine of X; X in radians - -- Special values: - -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER - -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(SIN(X)) <= 1.0 - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function COS ( X : in REAL ) return REAL; - -- Purpose: - -- Returns cosine of X; X in radians - -- Special values: - -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an - -- INTEGER - -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER - -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(COS(X)) <= 1.0 - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function TAN (X : in REAL ) return REAL; - -- Purpose: - -- Returns tangent of X; X in radians - -- Special values: - -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER - -- Domain: - -- X in REAL and - -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER - -- Error conditions: - -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an - -- INTEGER - -- Range: - -- TAN(X) is mathematically unbounded - -- Notes: - -- a) For larger values of ABS(X), degraded accuracy is allowed. - - function ARCSIN (X : in REAL ) return REAL; - -- Purpose: - -- Returns inverse sine of X - -- Special values: - -- ARCSIN(0.0) = 0.0 - -- ARCSIN(1.0) = MATH_PI_OVER_2 - -- ARCSIN(-1.0) = -MATH_PI_OVER_2 - -- Domain: - -- ABS(X) <= 1.0 - -- Error conditions: - -- Error if ABS(X) > 1.0 - -- Range: - -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 - -- Notes: - -- None - - function ARCCOS (X : in REAL ) return REAL; - -- Purpose: - -- Returns inverse cosine of X - -- Special values: - -- ARCCOS(1.0) = 0.0 - -- ARCCOS(0.0) = MATH_PI_OVER_2 - -- ARCCOS(-1.0) = MATH_PI - -- Domain: - -- ABS(X) <= 1.0 - -- Error conditions: - -- Error if ABS(X) > 1.0 - -- Range: - -- 0.0 <= ARCCOS(X) <= MATH_PI - -- Notes: - -- None - - function ARCTAN (Y : in REAL) return REAL; - -- Purpose: - -- Returns the value of the angle in radians of the point - -- (1.0, Y), which is in rectangular coordinates - -- Special values: - -- ARCTAN(0.0) = 0.0 - -- Domain: - -- Y in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 - -- Notes: - -- None - - function ARCTAN (Y : in REAL; X : in REAL) return REAL; - -- Purpose: - -- Returns the principal value of the angle in radians of - -- the point (X, Y), which is in rectangular coordinates - -- Special values: - -- ARCTAN(0.0, X) = 0.0 if X > 0.0 - -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 - -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 - -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 - -- Domain: - -- Y in REAL - -- X in REAL, X /= 0.0 when Y = 0.0 - -- Error conditions: - -- Error if X = 0.0 and Y = 0.0 - -- Range: - -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI - -- Notes: - -- None - - function SINH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic sine of X - -- Special values: - -- SINH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- SINH(X) is mathematically unbounded - -- Notes: - -- a) The usable domain of SINH is approximately given by: - -- ABS(X) <= LOG(REAL'HIGH) - - - function COSH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic cosine of X - -- Special values: - -- COSH(0.0) = 1.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- COSH(X) >= 1.0 - -- Notes: - -- a) The usable domain of COSH is approximately given by: - -- ABS(X) <= LOG(REAL'HIGH) - - function TANH (X : in REAL) return REAL; - -- Purpose: - -- Returns hyperbolic tangent of X - -- Special values: - -- TANH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ABS(TANH(X)) <= 1.0 - -- Notes: - -- None - - function ARCSINH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic sine of X - -- Special values: - -- ARCSINH(0.0) = 0.0 - -- Domain: - -- X in REAL - -- Error conditions: - -- None - -- Range: - -- ARCSINH(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of ARCSINH is approximately given by: - -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) - - function ARCCOSH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic cosine of X - -- Special values: - -- ARCCOSH(1.0) = 0.0 - -- Domain: - -- X >= 1.0 - -- Error conditions: - -- Error if X < 1.0 - -- Range: - -- ARCCOSH(X) >= 0.0 - -- Notes: - -- a) The upper bound of the reachable range of ARCCOSH is - -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) - - function ARCTANH (X : in REAL) return REAL; - -- Purpose: - -- Returns inverse hyperbolic tangent of X - -- Special values: - -- ARCTANH(0.0) = 0.0 - -- Domain: - -- ABS(X) < 1.0 - -- Error conditions: - -- Error if ABS(X) >= 1.0 - -- Range: - -- ARCTANH(X) is mathematically unbounded - -- Notes: - -- a) The reachable range of ARCTANH is approximately given by: - -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) - -end MATH_REAL; - - - ------------------------------------------------------------------------- --- --- Copyright 1996 by IEEE. All rights reserved. - --- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard --- VHDL Mathematical Packages. This source file may not be copied, sold, or --- included with software that is sold without written permission from the IEEE --- Standards Department. This source file may be used to implement this standard --- and may be distributed in compiled form in any manner so long as the --- compiled form does not allow direct decompilation of the original source file. --- This source file may be copied for individual use between licensed users. --- This source file is provided on an AS IS basis. The IEEE disclaims ANY --- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY --- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source --- file shall indemnify and hold IEEE harmless from any damages or liability --- arising out of the use thereof. - --- --- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, --- MATH_REAL) --- --- Library: This package shall be compiled into a library --- symbolically named IEEE. --- --- Developers: IEEE DASC VHDL Mathematical Packages Working Group --- --- Purpose: This package body is a nonnormative implementation of the --- functionality defined in the MATH_REAL package declaration. --- --- Limitation: The values generated by the functions in this package may --- vary from platform to platform, and the precision of results --- is only guaranteed to be the minimum required by IEEE Std 1076 --- -1993. --- --- Notes: --- The "package declaration" defines the types, subtypes, and --- declarations of MATH_REAL. --- The standard mathematical definition and conventional meaning --- of the mathematical functions that are part of this standard --- represent the formal semantics of the implementation of the --- MATH_REAL package declaration. The purpose of the MATH_REAL --- package body is to clarify such semantics and provide a --- guideline for implementations to verify their implementation --- of MATH_REAL. Tool developers may choose to implement --- the package body in the most efficient manner available to them. --- --- ----------------------------------------------------------------------------- --- Version : 1.5 --- Date : 24 July 1996 --- ----------------------------------------------------------------------------- - -package body MATH_REAL is - - -- - -- Local Constants for Use in the Package Body Only - -- - constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 - constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 - constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi - constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic - constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries - constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria - constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic - - -- - -- Local Type Declarations for Cordic Operations - -- - type REAL_VECTOR is array (NATURAL range <>) of REAL; - type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; - subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); - subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); - subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); - subtype QUADRANT is INTEGER range 0 to 3; - type CORDIC_MODE_TYPE is (ROTATION, VECTORING); - - -- - -- Auxiliary Functions for Cordic Algorithms - -- - function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; - NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is - -- Description: - -- Returns power of two for a vector of values - -- Notes: - -- None - -- - variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); - variable TEMP : REAL := INITIAL_VALUE; - variable FLAG : BOOLEAN := TRUE; - begin - for I in 0 to NUMBER_OF_VALUES loop - V(I) := TEMP; - for P in D'RANGE loop - if I = D(P) then - FLAG := FALSE; - exit; - end if; - end loop; - if FLAG then - TEMP := TEMP/2.0; - end if; - FLAG := TRUE; - end loop; - return V; - end POWER_OF_2_SERIES; - - - constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( - NATURAL_VECTOR'(100, 90),1.0, - MAX_ITER); - - constant EPSILON : REAL_VECTOR_N := ( - 7.8539816339744827e-01, - 4.6364760900080606e-01, - 2.4497866312686413e-01, - 1.2435499454676144e-01, - 6.2418809995957351e-02, - 3.1239833430268277e-02, - 1.5623728620476830e-02, - 7.8123410601011116e-03, - 3.9062301319669717e-03, - 1.9531225164788189e-03, - 9.7656218955931937e-04, - 4.8828121119489829e-04, - 2.4414062014936175e-04, - 1.2207031189367021e-04, - 6.1035156174208768e-05, - 3.0517578115526093e-05, - 1.5258789061315760e-05, - 7.6293945311019699e-06, - 3.8146972656064960e-06, - 1.9073486328101870e-06, - 9.5367431640596080e-07, - 4.7683715820308876e-07, - 2.3841857910155801e-07, - 1.1920928955078067e-07, - 5.9604644775390553e-08, - 2.9802322387695303e-08, - 1.4901161193847654e-08, - 7.4505805969238281e-09 - ); - - function CORDIC ( X0 : in REAL; - Y0 : in REAL; - Z0 : in REAL; - N : in NATURAL; -- Precision factor - CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) - -- or vectoring (Y -> 0) - ) return REAL_ARR_3 is - -- Description: - -- Compute cordic values - -- Notes: - -- None - variable X : REAL := X0; - variable Y : REAL := Y0; - variable Z : REAL := Z0; - variable X_TEMP : REAL; - begin - if CORDIC_MODE = ROTATION then - for K in 0 to N loop - X_TEMP := X; - if ( Z >= 0.0) then - X := X - Y * TWO_AT_MINUS(K); - Y := Y + X_TEMP * TWO_AT_MINUS(K); - Z := Z - EPSILON(K); - else - X := X + Y * TWO_AT_MINUS(K); - Y := Y - X_TEMP * TWO_AT_MINUS(K); - Z := Z + EPSILON(K); - end if; - end loop; - else - for K in 0 to N loop - X_TEMP := X; - if ( Y < 0.0) then - X := X - Y * TWO_AT_MINUS(K); - Y := Y + X_TEMP * TWO_AT_MINUS(K); - Z := Z - EPSILON(K); - else - X := X + Y * TWO_AT_MINUS(K); - Y := Y - X_TEMP * TWO_AT_MINUS(K); - Z := Z + EPSILON(K); - end if; - end loop; - end if; - return REAL_ARR_3'(X, Y, Z); - end CORDIC; - - -- - -- Bodies for Global Mathematical Functions Start Here - -- - function SIGN (X: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- None - begin - if ( X > 0.0 ) then - return 1.0; - elsif ( X < 0.0 ) then - return -1.0; - else - return 0.0; - end if; - end SIGN; - - function CEIL (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) No conversion to an INTEGER type is expected, so truncate - -- cannot overflow for large arguments - -- b) The domain supported by this function is X <= LARGE - -- c) Returns X if ABS(X) >= LARGE - - constant LARGE: REAL := REAL(INTEGER'HIGH); - variable RD: REAL; - - begin - if ABS(X) >= LARGE then - return X; - end if; - - RD := REAL ( INTEGER(X)); - if RD = X then - return X; - end if; - - if X > 0.0 then - if RD >= X then - return RD; - else - return RD + 1.0; - end if; - elsif X = 0.0 then - return 0.0; - else - if RD <= X then - return RD + 1.0; - else - return RD; - end if; - end if; - end CEIL; - - function FLOOR (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) No conversion to an INTEGER type is expected, so truncate - -- cannot overflow for large arguments - -- b) The domain supported by this function is ABS(X) <= LARGE - -- c) Returns X if ABS(X) >= LARGE - - constant LARGE: REAL := REAL(INTEGER'HIGH); - variable RD: REAL; - - begin - if ABS( X ) >= LARGE then - return X; - end if; - - RD := REAL ( INTEGER(X)); - if RD = X then - return X; - end if; - - if X > 0.0 then - if RD <= X then - return RD; - else - return RD - 1.0; - end if; - elsif X = 0.0 then - return 0.0; - else - if RD >= X then - return RD - 1.0; - else - return RD; - end if; - end if; - end FLOOR; - - function ROUND (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 if X = 0.0 - -- b) Returns FLOOR(X + 0.5) if X > 0 - -- c) Returns CEIL(X - 0.5) if X < 0 - - begin - if X > 0.0 then - return FLOOR(X + 0.5); - elsif X < 0.0 then - return CEIL( X - 0.5); - else - return 0.0; - end if; - end ROUND; - - function TRUNC (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 if X = 0.0 - -- b) Returns FLOOR(X) if X > 0 - -- c) Returns CEIL(X) if X < 0 - - begin - if X > 0.0 then - return FLOOR(X); - elsif X < 0.0 then - return CEIL( X); - else - return 0.0; - end if; - end TRUNC; - - - - - function "MOD" (X, Y: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable XNEGATIVE : BOOLEAN := X < 0.0; - variable YNEGATIVE : BOOLEAN := Y < 0.0; - variable VALUE : REAL; - begin - -- Check validity of input arguments - if (Y = 0.0) then - assert FALSE - report "MOD(X, 0.0) is undefined" - severity ERROR; - return 0.0; - end if; - - -- Compute value - if ( XNEGATIVE ) then - if ( YNEGATIVE ) then - VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - end if; - else - if ( YNEGATIVE ) then - VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - end if; - end if; - - return VALUE; - end "MOD"; - - - function REALMAX (X, Y : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) REALMAX(X,Y) = X when X = Y - -- - begin - if X >= Y then - return X; - else - return Y; - end if; - end REALMAX; - - function REALMIN (X, Y : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) REALMIN(X,Y) = X when X = Y - -- - begin - if X <= Y then - return X; - else - return Y; - end if; - end REALMIN; - - - procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) - is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - -- - variable Z, K: INTEGER; - variable TSEED1 : INTEGER := INTEGER'(SEED1); - variable TSEED2 : INTEGER := INTEGER'(SEED2); - begin - -- Check validity of arguments - if SEED1 > 2147483562 then - assert FALSE - report "SEED1 > 2147483562 in UNIFORM" - severity ERROR; - X := 0.0; - return; - end if; - - if SEED2 > 2147483398 then - assert FALSE - report "SEED2 > 2147483398 in UNIFORM" - severity ERROR; - X := 0.0; - return; - end if; - - -- Compute new seed values and pseudo-random number - K := TSEED1/53668; - TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; - - if TSEED1 < 0 then - TSEED1 := TSEED1 + 2147483563; - end if; - - K := TSEED2/52774; - TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; - - if TSEED2 < 0 then - TSEED2 := TSEED2 + 2147483399; - end if; - - Z := TSEED1 - TSEED2; - if Z < 1 then - Z := Z + 2147483562; - end if; - - -- Get output values - SEED1 := POSITIVE'(TSEED1); - SEED2 := POSITIVE'(TSEED2); - X := REAL(Z)*4.656613e-10; - end UNIFORM; - - - - function SQRT (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Uses the Newton-Raphson approximation: - -- F(n+1) = 0.5*[F(n) + x/F(n)] - -- b) Returns 0.0 on error - -- - - constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor - - variable INIVAL: REAL; - variable OLDVAL : REAL ; - variable NEWVAL : REAL ; - variable COUNT : INTEGER := 1; - - begin - -- Check validity of argument - if ( X < 0.0 ) then - assert FALSE - report "X < 0.0 in SQRT(X)" - severity ERROR; - return 0.0; - end if; - - -- Get the square root for special cases - if X = 0.0 then - return 0.0; - else - if ( X = 1.0 ) then - return 1.0; - end if; - end if; - - -- Get the square root for general cases - INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise - OLDVAL := INIVAL; - NEWVAL := (X/OLDVAL + OLDVAL)*0.5; - - -- Check for relative and absolute error and max count - while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR - (ABS(NEWVAL - OLDVAL) > EPS) ) AND - (COUNT < MAX_COUNT) ) loop - OLDVAL := NEWVAL; - NEWVAL := (X/OLDVAL + OLDVAL)*0.5; - COUNT := COUNT + 1; - end loop; - return NEWVAL; - end SQRT; - - function CBRT (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Uses the Newton-Raphson approximation: - -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; - -- - constant EPS : REAL := BASE_EPS*BASE_EPS; - - variable INIVAL: REAL; - variable XLOCAL : REAL := X; - variable NEGATIVE : BOOLEAN := X < 0.0; - variable OLDVAL : REAL ; - variable NEWVAL : REAL ; - variable COUNT : INTEGER := 1; - - begin - - -- Compute root for special cases - if X = 0.0 then - return 0.0; - elsif ( X = 1.0 ) then - return 1.0; - else - if X = -1.0 then - return -1.0; - end if; - end if; - - -- Compute root for general cases - if NEGATIVE then - XLOCAL := -X; - end if; - - INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but - -- imprecise - OLDVAL := INIVAL; - NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; - - -- Check for relative and absolute errors and max count - while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR - (ABS(NEWVAL - OLDVAL) > EPS ) ) AND - ( COUNT < MAX_COUNT ) ) loop - OLDVAL := NEWVAL; - NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; - COUNT := COUNT + 1; - end loop; - - if NEGATIVE then - NEWVAL := -NEWVAL; - end if; - - return NEWVAL; - end CBRT; - - function "**" (X : in INTEGER; Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error condition - - begin - -- Check validity of argument - if ( ( X < 0 ) and ( Y /= 0.0 ) ) then - assert FALSE - report "X < 0 and Y /= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - if ( ( X = 0 ) and ( Y <= 0.0 ) ) then - assert FALSE - report "X = 0 and Y <= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - -- Get value for special cases - if ( X = 0 and Y > 0.0 ) then - return 0.0; - end if; - - if ( X = 1 ) then - return 1.0; - end if; - - if ( Y = 0.0 and X /= 0 ) then - return 1.0; - end if; - - if ( Y = 1.0) then - return (REAL(X)); - end if; - - -- Get value for general case - return EXP (Y * LOG (REAL(X))); - end "**"; - - function "**" (X : in REAL; Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error condition - - begin - -- Check validity of argument - if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then - assert FALSE - report "X < 0.0 and Y /= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then - assert FALSE - report "X = 0.0 and Y <= 0.0 in X**Y" - severity ERROR; - return 0.0; - end if; - - -- Get value for special cases - if ( X = 0.0 and Y > 0.0 ) then - return 0.0; - end if; - - if ( X = 1.0 ) then - return 1.0; - end if; - - if ( Y = 0.0 and X /= 0.0 ) then - return 1.0; - end if; - - if ( Y = 1.0) then - return (X); - end if; - - -- Get value for general case - return EXP (Y * LOG (X)); - end "**"; - - function EXP (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) This function computes the exponential using the following - -- series: - -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 - -- and reduces argument X to take advantage of exp(x+y) = - -- exp(x)*exp(y) - -- - -- b) This implementation limits X to be less than LOG(REAL'HIGH) - -- to avoid overflow. Returns REAL'HIGH when X reaches that - -- limit - -- - constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria - - variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument - variable XLOCAL : REAL := ABS(X); -- Use positive value - variable OLDVAL: REAL ; - variable COUNT: INTEGER ; - variable NEWVAL: REAL ; - variable LAST_TERM: REAL ; - variable FACTOR : REAL := 1.0; - - begin - -- Compute value for special cases - if X = 0.0 then - return 1.0; - end if; - - if XLOCAL = 1.0 then - if RECIPROCAL then - return MATH_1_OVER_E; - else - return MATH_E; - end if; - end if; - - if XLOCAL = 2.0 then - if RECIPROCAL then - return 1.0/MATH_E_P2; - else - return MATH_E_P2; - end if; - end if; - - if XLOCAL = 10.0 then - if RECIPROCAL then - return 1.0/MATH_E_P10; - else - return MATH_E_P10; - end if; - end if; - - if XLOCAL > LOG(REAL'HIGH) then - if RECIPROCAL then - return 0.0; - else - assert FALSE - report "X > LOG(REAL'HIGH) in EXP(X)" - severity NOTE; - return REAL'HIGH; - end if; - end if; - - -- Reduce argument to ABS(X) < 1.0 - while XLOCAL > 10.0 loop - XLOCAL := XLOCAL - 10.0; - FACTOR := FACTOR*MATH_E_P10; - end loop; - - while XLOCAL > 1.0 loop - XLOCAL := XLOCAL - 1.0; - FACTOR := FACTOR*MATH_E; - end loop; - - -- Compute value for case 0 < XLOCAL < 1 - OLDVAL := 1.0; - LAST_TERM := XLOCAL; - NEWVAL:= OLDVAL + LAST_TERM; - COUNT := 2; - - -- Check for relative and absolute errors and max count - while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR - (ABS(NEWVAL - OLDVAL) > EPS) ) AND - (COUNT < MAX_COUNT ) ) loop - OLDVAL := NEWVAL; - LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); - NEWVAL := OLDVAL + LAST_TERM; - COUNT := COUNT + 1; - end loop; - - -- Compute final value using exp(x+y) = exp(x)*exp(y) - NEWVAL := NEWVAL*FACTOR; - - if RECIPROCAL then - NEWVAL := 1.0/NEWVAL; - end if; - - return NEWVAL; - end EXP; - - - -- - -- Auxiliary Functions to Compute LOG - -- - function ILOGB(X: in REAL) return INTEGER IS - -- Description: - -- Returns n such that -1 <= ABS(X)/2^n < 2 - -- Notes: - -- None - - variable N: INTEGER := 0; - variable Y: REAL := ABS(X); - - begin - if(Y = 1.0 or Y = 0.0) then - return 0; - end if; - - if( Y > 1.0) then - while Y >= 2.0 loop - Y := Y/2.0; - N := N+1; - end loop; - return N; - end if; - - -- O < Y < 1 - while Y < 1.0 loop - Y := Y*2.0; - N := N -1; - end loop; - return N; - end ILOGB; - - function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS - -- Description: - -- Returns X*2^n - -- Notes: - -- None - begin - return X*(2.0 ** N); - end LDEXP; - - function LOG (X : in REAL ) return REAL IS - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- - -- Notes: - -- a) Returns REAL'LOW on error - -- - -- Copyright (c) 1992 Regents of the University of California. - -- All rights reserved. - -- - -- Redistribution and use in source and binary forms, with or without - -- modification, are permitted provided that the following conditions - -- are met: - -- 1. Redistributions of source code must retain the above copyright - -- notice, this list of conditions and the following disclaimer. - -- 2. Redistributions in binary form must reproduce the above copyright - -- notice, this list of conditions and the following disclaimer in the - -- documentation and/or other materials provided with the distribution. - -- 3. All advertising materials mentioning features or use of this - -- software must display the following acknowledgement: - -- This product includes software developed by the University of - -- California, Berkeley and its contributors. - -- 4. Neither the name of the University nor the names of its - -- contributors may be used to endorse or promote products derived - -- from this software without specific prior written permission. - -- - -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' - -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A - -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR - -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR - -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY - -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE - -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH - -- DAMAGE. - -- - -- NOTE: This VHDL version was generated using the C version of the - -- original function by the IEEE VHDL Mathematical Package - -- Working Group (CS/JT) - - constant N: INTEGER := 128; - - -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. - -- Used for generation of extend precision logarithms. - -- The constant 35184372088832 is 2^45, so the divide is exact. - -- It ensures correct reading of logF_head, even for inaccurate - -- decimal-to-binary conversion routines. (Everybody gets the - -- right answer for INTEGERs less than 2^53.) - -- Values for LOG(F) were generated using error < 10^-57 absolute - -- with the bc -l package. - - type REAL_VECTOR is array (NATURAL range <>) of REAL; - - constant A1:REAL := 0.08333333333333178827; - constant A2:REAL := 0.01250000000377174923; - constant A3:REAL := 0.002232139987919447809; - constant A4:REAL := 0.0004348877777076145742; - - constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( - 0.0, - 0.007782140442060381246, - 0.015504186535963526694, - 0.023167059281547608406, - 0.030771658666765233647, - 0.038318864302141264488, - 0.045809536031242714670, - 0.053244514518837604555, - 0.060624621816486978786, - 0.067950661908525944454, - 0.075223421237524235039, - 0.082443669210988446138, - 0.089612158689760690322, - 0.096729626458454731618, - 0.103796793681567578460, - 0.110814366340264314203, - 0.117783035656430001836, - 0.124703478501032805070, - 0.131576357788617315236, - 0.138402322859292326029, - 0.145182009844575077295, - 0.151916042025732167530, - 0.158605030176659056451, - 0.165249572895390883786, - 0.171850256926518341060, - 0.178407657472689606947, - 0.184922338493834104156, - 0.191394852999565046047, - 0.197825743329758552135, - 0.204215541428766300668, - 0.210564769107350002741, - 0.216873938300523150246, - 0.223143551314024080056, - 0.229374101064877322642, - 0.235566071312860003672, - 0.241719936886966024758, - 0.247836163904594286577, - 0.253915209980732470285, - 0.259957524436686071567, - 0.265963548496984003577, - 0.271933715484010463114, - 0.277868451003087102435, - 0.283768173130738432519, - 0.289633292582948342896, - 0.295464212893421063199, - 0.301261330578199704177, - 0.307025035294827830512, - 0.312755710004239517729, - 0.318453731118097493890, - 0.324119468654316733591, - 0.329753286372579168528, - 0.335355541920762334484, - 0.340926586970454081892, - 0.346466767346100823488, - 0.351976423156884266063, - 0.357455888922231679316, - 0.362905493689140712376, - 0.368325561158599157352, - 0.373716409793814818840, - 0.379078352934811846353, - 0.384411698910298582632, - 0.389716751140440464951, - 0.394993808240542421117, - 0.400243164127459749579, - 0.405465108107819105498, - 0.410659924985338875558, - 0.415827895143593195825, - 0.420969294644237379543, - 0.426084395310681429691, - 0.431173464818130014464, - 0.436236766774527495726, - 0.441274560805140936281, - 0.446287102628048160113, - 0.451274644139630254358, - 0.456237433481874177232, - 0.461175715122408291790, - 0.466089729924533457960, - 0.470979715219073113985, - 0.475845904869856894947, - 0.480688529345570714212, - 0.485507815781602403149, - 0.490303988045525329653, - 0.495077266798034543171, - 0.499827869556611403822, - 0.504556010751912253908, - 0.509261901790523552335, - 0.513945751101346104405, - 0.518607764208354637958, - 0.523248143765158602036, - 0.527867089620485785417, - 0.532464798869114019908, - 0.537041465897345915436, - 0.541597282432121573947, - 0.546132437597407260909, - 0.550647117952394182793, - 0.555141507540611200965, - 0.559615787935399566777, - 0.564070138285387656651, - 0.568504735352689749561, - 0.572919753562018740922, - 0.577315365035246941260, - 0.581691739635061821900, - 0.586049045003164792433, - 0.590387446602107957005, - 0.594707107746216934174, - 0.599008189645246602594, - 0.603290851438941899687, - 0.607555250224322662688, - 0.611801541106615331955, - 0.616029877215623855590, - 0.620240409751204424537, - 0.624433288012369303032, - 0.628608659422752680256, - 0.632766669570628437213, - 0.636907462236194987781, - 0.641031179420679109171, - 0.645137961373620782978, - 0.649227946625615004450, - 0.653301272011958644725, - 0.657358072709030238911, - 0.661398482245203922502, - 0.665422632544505177065, - 0.669430653942981734871, - 0.673422675212350441142, - 0.677398823590920073911, - 0.681359224807238206267, - 0.685304003098281100392, - 0.689233281238557538017, - 0.693147180560117703862); - - constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( - 0.0, - -0.00000000000000543229938420049, - 0.00000000000000172745674997061, - -0.00000000000001323017818229233, - -0.00000000000001154527628289872, - -0.00000000000000466529469958300, - 0.00000000000005148849572685810, - -0.00000000000002532168943117445, - -0.00000000000005213620639136504, - -0.00000000000001819506003016881, - 0.00000000000006329065958724544, - 0.00000000000008614512936087814, - -0.00000000000007355770219435028, - 0.00000000000009638067658552277, - 0.00000000000007598636597194141, - 0.00000000000002579999128306990, - -0.00000000000004654729747598444, - -0.00000000000007556920687451336, - 0.00000000000010195735223708472, - -0.00000000000017319034406422306, - -0.00000000000007718001336828098, - 0.00000000000010980754099855238, - -0.00000000000002047235780046195, - -0.00000000000008372091099235912, - 0.00000000000014088127937111135, - 0.00000000000012869017157588257, - 0.00000000000017788850778198106, - 0.00000000000006440856150696891, - 0.00000000000016132822667240822, - -0.00000000000007540916511956188, - -0.00000000000000036507188831790, - 0.00000000000009120937249914984, - 0.00000000000018567570959796010, - -0.00000000000003149265065191483, - -0.00000000000009309459495196889, - 0.00000000000017914338601329117, - -0.00000000000001302979717330866, - 0.00000000000023097385217586939, - 0.00000000000023999540484211737, - 0.00000000000015393776174455408, - -0.00000000000036870428315837678, - 0.00000000000036920375082080089, - -0.00000000000009383417223663699, - 0.00000000000009433398189512690, - 0.00000000000041481318704258568, - -0.00000000000003792316480209314, - 0.00000000000008403156304792424, - -0.00000000000034262934348285429, - 0.00000000000043712191957429145, - -0.00000000000010475750058776541, - -0.00000000000011118671389559323, - 0.00000000000037549577257259853, - 0.00000000000013912841212197565, - 0.00000000000010775743037572640, - 0.00000000000029391859187648000, - -0.00000000000042790509060060774, - 0.00000000000022774076114039555, - 0.00000000000010849569622967912, - -0.00000000000023073801945705758, - 0.00000000000015761203773969435, - 0.00000000000003345710269544082, - -0.00000000000041525158063436123, - 0.00000000000032655698896907146, - -0.00000000000044704265010452446, - 0.00000000000034527647952039772, - -0.00000000000007048962392109746, - 0.00000000000011776978751369214, - -0.00000000000010774341461609578, - 0.00000000000021863343293215910, - 0.00000000000024132639491333131, - 0.00000000000039057462209830700, - -0.00000000000026570679203560751, - 0.00000000000037135141919592021, - -0.00000000000017166921336082431, - -0.00000000000028658285157914353, - -0.00000000000023812542263446809, - 0.00000000000006576659768580062, - -0.00000000000028210143846181267, - 0.00000000000010701931762114254, - 0.00000000000018119346366441110, - 0.00000000000009840465278232627, - -0.00000000000033149150282752542, - -0.00000000000018302857356041668, - -0.00000000000016207400156744949, - 0.00000000000048303314949553201, - -0.00000000000071560553172382115, - 0.00000000000088821239518571855, - -0.00000000000030900580513238244, - -0.00000000000061076551972851496, - 0.00000000000035659969663347830, - 0.00000000000035782396591276383, - -0.00000000000046226087001544578, - 0.00000000000062279762917225156, - 0.00000000000072838947272065741, - 0.00000000000026809646615211673, - -0.00000000000010960825046059278, - 0.00000000000002311949383800537, - -0.00000000000058469058005299247, - -0.00000000000002103748251144494, - -0.00000000000023323182945587408, - -0.00000000000042333694288141916, - -0.00000000000043933937969737844, - 0.00000000000041341647073835565, - 0.00000000000006841763641591466, - 0.00000000000047585534004430641, - 0.00000000000083679678674757695, - -0.00000000000085763734646658640, - 0.00000000000021913281229340092, - -0.00000000000062242842536431148, - -0.00000000000010983594325438430, - 0.00000000000065310431377633651, - -0.00000000000047580199021710769, - -0.00000000000037854251265457040, - 0.00000000000040939233218678664, - 0.00000000000087424383914858291, - 0.00000000000025218188456842882, - -0.00000000000003608131360422557, - -0.00000000000050518555924280902, - 0.00000000000078699403323355317, - -0.00000000000067020876961949060, - 0.00000000000016108575753932458, - 0.00000000000058527188436251509, - -0.00000000000035246757297904791, - -0.00000000000018372084495629058, - 0.00000000000088606689813494916, - 0.00000000000066486268071468700, - 0.00000000000063831615170646519, - 0.00000000000025144230728376072, - -0.00000000000017239444525614834); - - variable M, J:INTEGER; - variable F1, F2, G, Q, U, U2, V: REAL; - variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs - variable ONE: REAL := 1.0; --Made variable so no constant folding occurs - - -- double logb(), ldexp(); - - variable U1:REAL; - - begin - - -- Check validity of argument - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = MATH_E ) then - return 1.0; - end if; - - -- Argument reduction: 1 <= g < 2; x/2^m = g; - -- y = F*(1 + f/F) for |f| <= 2^-8 - - M := ILOGB(X); - G := LDEXP(X, -M); - J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding - F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] - F2 := G - F1; - - -- Approximate expansion for log(1+f2/F1) ~= u + q - G := 1.0/(2.0*F1+F2); - U := 2.0*F2*G; - V := U*U; - Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); - - -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, - -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. - -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. - -- - if ( J /= 0 or M /= 0) then - U1 := U + 513.0; - U1 := U1 - 513.0; - - -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero - -- u1 = u to 24 bits. - -- - else - U1 := U; - --TRUNC(U1); --In c this is u1 = (double) (float) (u1) - end if; - - U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; - -- u1 + u2 = 2f/(2F+f) to extra precision. - - -- log(x) = log(2^m*F1*(1+f2/F1)) = - -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); - -- (exact) + (tiny) - - U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact - U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny - U2 := U2 + LOGF_TAIL(N)*REAL(M); - return (U1 + U2); - end LOG; - - - function LOG2 (X: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG2(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = 2.0 ) then - return 1.0; - end if; - - -- Compute value for general case - return ( MATH_LOG2_OF_E*LOG(X) ); - end LOG2; - - - function LOG10 (X: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG10(X)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = 10.0 ) then - return 1.0; - end if; - - -- Compute value for general case - return ( MATH_LOG10_OF_E*LOG(X) ); - end LOG10; - - - function LOG (X: in REAL; BASE: in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns REAL'LOW on error - begin - -- Check validity of arguments - if ( X <= 0.0 ) then - assert FALSE - report "X <= 0.0 in LOG(X, BASE)" - severity ERROR; - return(REAL'LOW); - end if; - - if ( BASE <= 0.0 or BASE = 1.0 ) then - assert FALSE - report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" - severity ERROR; - return(REAL'LOW); - end if; - - -- Compute value for special cases - if ( X = 1.0 ) then - return 0.0; - end if; - - if ( X = BASE ) then - return 1.0; - end if; - - -- Compute value for general case - return ( LOG(X)/LOG(BASE)); - end LOG; - - - function SIN (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) SIN(-X) = -SIN(X) - -- b) SIN(X) = X if ABS(X) < EPS - -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS - -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) - -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS - -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if - -- EPS< ABS(X) MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in SIN(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then - return 0.0; - end if; - - if XLOCAL = MATH_PI_OVER_2 then - if NEGATIVE then - return -1.0; - else - return 1.0; - end if; - end if; - - if XLOCAL = MATH_3_PI_OVER_2 then - if NEGATIVE then - return 1.0; - else - return -1.0; - end if; - end if; - - if XLOCAL < EPS then - if NEGATIVE then - return -XLOCAL; - else - return XLOCAL; - end if; - else - if XLOCAL < BASE_EPS then - TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := MATH_PI - XLOCAL; - if ABS(TEMP) < EPS then - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - else - if ABS(TEMP) < BASE_EPS then - TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := MATH_2_PI - XLOCAL; - if ABS(TEMP) < EPS then - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - else - if ABS(TEMP) < BASE_EPS then - TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - end if; - end if; - - TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); - if TEMP < EPS then - TEMP := 1.0 - TEMP*TEMP*0.5; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - else - if TEMP < BASE_EPS then - TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; - if NEGATIVE then - return -TEMP; - else - return TEMP; - end if; - end if; - end if; - - TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); - if TEMP < EPS then - TEMP := 1.0 - TEMP*TEMP*0.5; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - else - if TEMP < BASE_EPS then - TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; - if NEGATIVE then - return TEMP; - else - return -TEMP; - end if; - end if; - end if; - - -- Compute value for general cases - if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then - VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); - end if; - - N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); - case QUADRANT( N mod 4) is - when 0 => - VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); - when 1 => - VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, - ROTATION)(0); - when 2 => - VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); - when 3 => - VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, - ROTATION)(0); - end case; - - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end SIN; - - - function COS (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) COS(-X) = COS(X) - -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) - -- c) COS(MATH_PI + X) = -COS(X) - -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS - -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if - -- EPS< ABS(X) MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in COS(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then - return 1.0; - end if; - - if XLOCAL = MATH_PI then - return -1.0; - end if; - - if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then - return 0.0; - end if; - - TEMP := ABS(XLOCAL); - if ( TEMP < EPS) then - return (1.0 - 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - TEMP := ABS(XLOCAL -MATH_2_PI); - if ( TEMP < EPS) then - return (1.0 - 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - TEMP := ABS (XLOCAL - MATH_PI); - if TEMP < EPS then - return (-1.0 + 0.5*TEMP*TEMP); - else - if (TEMP < BASE_EPS) then - return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); - end if; - end if; - - -- Compute value for general cases - return SIN(MATH_PI_OVER_2 - XLOCAL); - end COS; - - function TAN (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) TAN(0.0) = 0.0 - -- b) TAN(-X) = -TAN(X) - -- c) Returns REAL'LOW on error if X < 0.0 - -- d) Returns REAL'HIGH on error if X > 0.0 - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X) ; - variable VALUE: REAL; - variable TEMP : REAL; - - begin - -- Make 0.0 <= XLOCAL <= MATH_2_PI - if XLOCAL > MATH_2_PI then - TEMP := FLOOR(XLOCAL/MATH_2_PI); - XLOCAL := XLOCAL - TEMP*MATH_2_PI; - end if; - - if XLOCAL < 0.0 then - assert FALSE - report "XLOCAL <= 0.0 after reduction in TAN(X)" - severity ERROR; - XLOCAL := -XLOCAL; - end if; - - -- Check validity of argument - if XLOCAL = MATH_PI_OVER_2 then - assert FALSE - report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" - severity ERROR; - if NEGATIVE then - return(REAL'LOW); - else - return(REAL'HIGH); - end if; - end if; - - if XLOCAL = MATH_3_PI_OVER_2 then - assert FALSE - report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" - severity ERROR; - if NEGATIVE then - return(REAL'HIGH); - else - return(REAL'LOW); - end if; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 or XLOCAL = MATH_PI then - return 0.0; - end if; - - -- Compute value for general cases - VALUE := SIN(XLOCAL)/COS(XLOCAL); - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end TAN; - - function ARCSIN (X : in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCSIN(-X) = -ARCSIN(X) - -- b) Returns X on error - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable VALUE : REAL; - - begin - -- Check validity of arguments - if XLOCAL > 1.0 then - assert FALSE - report "ABS(X) > 1.0 in ARCSIN(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - elsif XLOCAL = 1.0 then - if NEGATIVE then - return -MATH_PI_OVER_2; - else - return MATH_PI_OVER_2; - end if; - end if; - - -- Compute value for general cases - if XLOCAL < 0.9 then - VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); - else - VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); - end if; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCSIN; - - function ARCCOS (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) - -- b) Returns X on error - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable VALUE : REAL; - - begin - -- Check validity of argument - if XLOCAL > 1.0 then - assert FALSE - report "ABS(X) > 1.0 in ARCCOS(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 1.0 then - return 0.0; - elsif X = 0.0 then - return MATH_PI_OVER_2; - elsif X = -1.0 then - return MATH_PI; - end if; - - -- Compute value for general cases - if XLOCAL > 0.9 then - VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); - else - VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); - end if; - - - if NEGATIVE then - VALUE := MATH_PI - VALUE; - end if; - - return VALUE; - end ARCCOS; - - - function ARCTAN (Y : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) ARCTAN(-Y) = -ARCTAN(Y) - -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 - -- c) ARCTAN(Y) = Y for |Y| < EPS - - constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; - - variable NEGATIVE : BOOLEAN := Y < 0.0; - variable RECIPROCAL : BOOLEAN; - variable YLOCAL : REAL := ABS(Y); - variable VALUE : REAL; - - begin - -- Make argument |Y| <=1.0 - if YLOCAL > 1.0 then - YLOCAL := 1.0/YLOCAL; - RECIPROCAL := TRUE; - else - RECIPROCAL := FALSE; - end if; - - -- Compute value for special cases - if YLOCAL = 0.0 then - if RECIPROCAL then - if NEGATIVE then - return (-MATH_PI_OVER_2); - else - return (MATH_PI_OVER_2); - end if; - else - return 0.0; - end if; - end if; - - if YLOCAL < EPS then - if NEGATIVE then - if RECIPROCAL then - return (-MATH_PI_OVER_2 + YLOCAL); - else - return -YLOCAL; - end if; - else - if RECIPROCAL then - return (MATH_PI_OVER_2 - YLOCAL); - else - return YLOCAL; - end if; - end if; - end if; - - -- Compute value for general cases - VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); - - if RECIPROCAL then - VALUE := MATH_PI_OVER_2 - VALUE; - end if; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCTAN; - - - function ARCTAN (Y : in REAL; X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable YLOCAL : REAL; - variable VALUE : REAL; - begin - - -- Check validity of arguments - if (Y = 0.0 and X = 0.0 ) then - assert FALSE report - "ARCTAN(0.0, 0.0) is undetermined" - severity ERROR; - return 0.0; - end if; - - -- Compute value for special cases - if Y = 0.0 then - if X > 0.0 then - return 0.0; - else - return MATH_PI; - end if; - end if; - - if X = 0.0 then - if Y > 0.0 then - return MATH_PI_OVER_2; - else - return -MATH_PI_OVER_2; - end if; - end if; - - - -- Compute value for general cases - YLOCAL := ABS(Y/X); - - VALUE := ARCTAN(YLOCAL); - - if X < 0.0 then - VALUE := MATH_PI - VALUE; - end if; - - if Y < 0.0 then - VALUE := -VALUE; - end if; - - return VALUE; - end ARCTAN; - - - function SINH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) - EXP(-X))/2.0 - -- b) SINH(-X) = SINH(X) - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP - 1.0/TEMP)*0.5; - - if NEGATIVE then - VALUE := -VALUE; - end if; - - return VALUE; - end SINH; - - function COSH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) + EXP(-X))/2.0 - -- b) COSH(-X) = COSH(X) - - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 1.0; - end if; - - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP + 1.0/TEMP)*0.5; - - return VALUE; - end COSH; - - function TANH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) - -- b) TANH(-X) = -TANH(X) - - variable NEGATIVE : BOOLEAN := X < 0.0; - variable XLOCAL : REAL := ABS(X); - variable TEMP : REAL; - variable VALUE : REAL; - - begin - -- Compute value for special cases - if XLOCAL = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - TEMP := EXP(XLOCAL); - VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); - - if NEGATIVE then - return -VALUE; - else - return VALUE; - end if; - end TANH; - - function ARCSINH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns LOG( X + SQRT( X*X + 1.0)) - - begin - -- Compute value for special cases - if X = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - return ( LOG( X + SQRT( X*X + 1.0)) ); - end ARCSINH; - - - - function ARCCOSH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 - -- b) Returns X on error - - begin - -- Check validity of arguments - if X < 1.0 then - assert FALSE - report "X < 1.0 in ARCCOSH(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 1.0 then - return 0.0; - end if; - - -- Compute value for general cases - return ( LOG( X + SQRT( X*X - 1.0))); - end ARCCOSH; - - function ARCTANH (X : in REAL) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 - -- b) Returns X on error - begin - -- Check validity of arguments - if ABS(X) >= 1.0 then - assert FALSE - report "ABS(X) >= 1.0 in ARCTANH(X)" - severity ERROR; - return X; - end if; - - -- Compute value for special cases - if X = 0.0 then - return 0.0; - end if; - - -- Compute value for general cases - return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); - end ARCTANH; - -end MATH_REAL; diff --git a/CPLD/LCMXO2-640HC/generate_core.tcl b/CPLD/LCMXO2-640HC/generate_core.tcl deleted file mode 100644 index 47f429b..0000000 --- a/CPLD/LCMXO2-640HC/generate_core.tcl +++ /dev/null @@ -1,100 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -proc GetCmdLine {lpcfile} { - global Para - - if [catch {open $lpcfile r} fileid] { - puts "Cannot open $para_file file!" - exit -1 - } - - seek $fileid 0 start - set default_match 0 - while {[gets $fileid line] >= 0} { - if {[string first "\[Command\]" $line] == 0} { - set default_match 1 - continue - } - if {[string first "\[" $line] == 0} { - set default_match 0 - } - if {$default_match == 1} { - if [regexp {([^=]*)=(.*)} $line match parameter value] { - if [regexp {([ |\t]*;)} $parameter match] {continue} - if [regexp {(.*)[ |\t]*;} $value match temp] { - set Para($parameter) $temp - } else { - set Para($parameter) $value - } - } - } - } - set default_match 0 - close $fileid - - return $Para(cmd_line) -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" - -set scuba "$Para(FPGAPath)/scuba" -set modulename "REFB" -set lang "verilog" -set lpcfile "$Para(sbp_path)/$modulename.lpc" -set arch "xo2c00" -set cmd_line [GetCmdLine $lpcfile] -set fdcfile "$Para(sbp_path)/$modulename.fdc" -if {[file exists $fdcfile] == 0} { - append scuba " " $cmd_line -} else { - append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" -} -set Para(result) [catch {eval exec "$scuba"} msg] -#puts $msg diff --git a/CPLD/LCMXO2-640HC/generate_ngd.tcl b/CPLD/LCMXO2-640HC/generate_ngd.tcl deleted file mode 100644 index d6ce2af..0000000 --- a/CPLD/LCMXO2-640HC/generate_ngd.tcl +++ /dev/null @@ -1,74 +0,0 @@ -#!/usr/local/bin/wish - -proc GetPlatform {} { - global tcl_platform - - set cpu $tcl_platform(machine) - - switch $cpu { - intel - - i*86* { - set cpu ix86 - } - x86_64 { - if {$tcl_platform(wordSize) == 4} { - set cpu ix86 - } - } - } - - switch $tcl_platform(platform) { - windows { - if {$cpu == "amd64"} { - # Do not check wordSize, win32-x64 is an IL32P64 platform. - set cpu x86_64 - } - if {$cpu == "x86_64"} { - return "nt64" - } else { - return "nt" - } - } - unix { - if {$tcl_platform(os) == "Linux"} { - if {$cpu == "x86_64"} { - return "lin64" - } else { - return "lin" - } - } else { - return "sol" - } - } - } - return "nt" -} - -set platformpath [GetPlatform] -set Para(sbp_path) [file dirname [info script]] -set Para(install_dir) $env(TOOLRTF) -set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" -set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" - -set Para(ModuleName) "REFB" -set Para(Module) "EFB" -set Para(libname) machxo2 -set Para(arch_name) xo2c00 -set Para(PartType) "LCMXO2-640HC" - -set Para(tech_syn) machxo2 -set Para(tech_cae) machxo2 -set Para(Package) "TQFP100" -set Para(SpeedGrade) "4" -set Para(FMax) "100" -set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" - -#edif2ngd -set edif2ngd "$Para(FPGAPath)/edif2ngd" -set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] -#puts $msg - -#ngdbuild -set ngdbuild "$Para(FPGAPath)/ngdbuild" -set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] -#puts $msg diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt deleted file mode 100644 index a2966b6..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt +++ /dev/null @@ -1,77 +0,0 @@ -NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * -NOTE All Rights Reserved * -NOTE DATE CREATED: Thu Dec 28 23:23:58 2023 * -NOTE DESIGN NAME: RAM2E * -NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 * -NOTE PIN ASSIGNMENTS * -NOTE PINS RD[0] : 36 : inout * -NOTE PINS LED : 35 : out * -NOTE PINS C14M : 62 : in * -NOTE PINS RD[7] : 43 : inout * -NOTE PINS RD[6] : 42 : inout * -NOTE PINS RD[5] : 41 : inout * -NOTE PINS RD[4] : 40 : inout * -NOTE PINS RD[3] : 39 : inout * -NOTE PINS RD[2] : 38 : inout * -NOTE PINS RD[1] : 37 : inout * -NOTE PINS DQMH : 49 : out * -NOTE PINS DQML : 48 : out * -NOTE PINS RAout[11] : 59 : out * -NOTE PINS RAout[10] : 64 : out * -NOTE PINS RAout[9] : 63 : out * -NOTE PINS RAout[8] : 65 : out * -NOTE PINS RAout[7] : 67 : out * -NOTE PINS RAout[6] : 69 : out * -NOTE PINS RAout[5] : 71 : out * -NOTE PINS RAout[4] : 75 : out * -NOTE PINS RAout[3] : 74 : out * -NOTE PINS RAout[2] : 70 : out * -NOTE PINS RAout[1] : 68 : out * -NOTE PINS RAout[0] : 66 : out * -NOTE PINS BA[1] : 60 : out * -NOTE PINS BA[0] : 58 : out * -NOTE PINS nRWEout : 51 : out * -NOTE PINS nCASout : 52 : out * -NOTE PINS nRASout : 54 : out * -NOTE PINS nCSout : 57 : out * -NOTE PINS CKEout : 53 : out * -NOTE PINS nVOE : 10 : out * -NOTE PINS Vout[7] : 12 : out * -NOTE PINS Vout[6] : 14 : out * -NOTE PINS Vout[5] : 16 : out * -NOTE PINS Vout[4] : 19 : out * -NOTE PINS Vout[3] : 13 : out * -NOTE PINS Vout[2] : 17 : out * -NOTE PINS Vout[1] : 15 : out * -NOTE PINS Vout[0] : 18 : out * -NOTE PINS nDOE : 20 : out * -NOTE PINS Dout[7] : 32 : out * -NOTE PINS Dout[6] : 31 : out * -NOTE PINS Dout[5] : 21 : out * -NOTE PINS Dout[4] : 24 : out * -NOTE PINS Dout[3] : 28 : out * -NOTE PINS Dout[2] : 25 : out * -NOTE PINS Dout[1] : 27 : out * -NOTE PINS Dout[0] : 30 : out * -NOTE PINS Din[7] : 87 : in * -NOTE PINS Din[6] : 88 : in * -NOTE PINS Din[5] : 99 : in * -NOTE PINS Din[4] : 1 : in * -NOTE PINS Din[3] : 9 : in * -NOTE PINS Din[2] : 98 : in * -NOTE PINS Din[1] : 97 : in * -NOTE PINS Din[0] : 96 : in * -NOTE PINS Ain[7] : 8 : in * -NOTE PINS Ain[6] : 86 : in * -NOTE PINS Ain[5] : 84 : in * -NOTE PINS Ain[4] : 78 : in * -NOTE PINS Ain[3] : 4 : in * -NOTE PINS Ain[2] : 7 : in * -NOTE PINS Ain[1] : 2 : in * -NOTE PINS Ain[0] : 3 : in * -NOTE PINS nC07X : 34 : in * -NOTE PINS nEN80 : 82 : in * -NOTE PINS nWE : 29 : in * -NOTE PINS PHI1 : 85 : in * -NOTE CONFIGURATION MODE: NONE * -NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.areasrr b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.areasrr deleted file mode 100644 index 545fb4f..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.areasrr +++ /dev/null @@ -1,61 +0,0 @@ ----------------------------------------------------------------------- -Report for cell RAM2E.verilog - -Register bits: 122 of 640 (19%) -PIC Latch: 0 -I/O cells: 69 - Cell usage: - cell count Res Usage(%) - BB 8 100.0 - CCU2D 9 100.0 - EFB 1 100.0 - FD1P3AX 61 100.0 - FD1P3IX 1 100.0 - FD1S3AX 21 100.0 - FD1S3AY 4 100.0 - FD1S3IX 6 100.0 - GSR 1 100.0 - IB 21 100.0 - IFS1P3DX 1 100.0 - INV 1 100.0 - OB 40 100.0 - OFS1P3BX 5 100.0 - OFS1P3DX 21 100.0 - OFS1P3IX 2 100.0 - ORCALUT4 277 100.0 - PFUMX 3 100.0 - PUR 1 100.0 - VHI 3 100.0 - VLO 3 100.0 -SUB MODULES - RAM2E_UFM 1 100.0 - REFB 1 100.0 - - TOTAL 492 ----------------------------------------------------------------------- -Report for cell RAM2E_UFM.netlist - Instance path: ram2e_ufm - Cell usage: - cell count Res Usage(%) - EFB 1 100.0 - FD1P3AX 30 49.2 - FD1P3IX 1 100.0 - FD1S3IX 1 16.7 - ORCALUT4 272 98.2 - PFUMX 3 100.0 - VHI 2 66.7 - VLO 2 66.7 -SUB MODULES - REFB 1 100.0 - - TOTAL 313 ----------------------------------------------------------------------- -Report for cell REFB.netlist - Instance path: ram2e_ufm.ufmefb - Cell usage: - cell count Res Usage(%) - EFB 1 100.0 - VHI 1 33.3 - VLO 1 33.3 - - TOTAL 3 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn deleted file mode 100644 index 2878fee..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn +++ /dev/null @@ -1,86 +0,0 @@ -BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Dec 28 23:23:55 2023 - - -Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf - -Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. - -Running DRC. -DRC detected 0 errors and 0 warnings. -Reading Preference File from RAM2E_LCMXO2_640HC_impl1.prf. - -Preference Summary: -+---------------------------------+---------------------------------+ -| Preference | Current Setting | -+---------------------------------+---------------------------------+ -| RamCfg | Reset** | -+---------------------------------+---------------------------------+ -| MCCLK_FREQ | 2.08** | -+---------------------------------+---------------------------------+ -| CONFIG_SECURE | OFF** | -+---------------------------------+---------------------------------+ -| INBUF | ON** | -+---------------------------------+---------------------------------+ -| JTAG_PORT | ENABLE** | -+---------------------------------+---------------------------------+ -| SDM_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| SLAVE_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MASTER_SPI_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| I2C_PORT | DISABLE** | -+---------------------------------+---------------------------------+ -| MUX_CONFIGURATION_PORTS | DISABLE** | -+---------------------------------+---------------------------------+ -| CONFIGURATION | CFG** | -+---------------------------------+---------------------------------+ -| COMPRESS_CONFIG | ON** | -+---------------------------------+---------------------------------+ -| MY_ASSP | OFF** | -+---------------------------------+---------------------------------+ -| ONE_TIME_PROGRAM | OFF** | -+---------------------------------+---------------------------------+ -| ENABLE_TRANSFR | DISABLE** | -+---------------------------------+---------------------------------+ -| SHAREDEBRINIT | DISABLE** | -+---------------------------------+---------------------------------+ -| BACKGROUND_RECONFIG | OFF** | -+---------------------------------+---------------------------------+ - * Default setting. - ** The specified setting matches the default setting. - - -Creating bit map... - -Bitstream Status: Final Version 1.95. - -Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.jed". - -=========== -UFM Summary. -=========== -UFM Size: 191 Pages (128*191 Bits). -UFM Utilization: General Purpose Flash Memory. - -Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). -Initialized UFM Pages: 1 Page (Page 190). - -Total CPU Time: 3 secs -Total REAL Time: 3 secs -Peak Memory Usage: 267 MB diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bit b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bit deleted file mode 100644 index ae990d6..0000000 Binary files a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bit and /dev/null differ diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.edi b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.edi deleted file mode 100644 index c8dad6c..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.edi +++ /dev/null @@ -1,5874 +0,0 @@ -(edif RAM2E - (edifVersion 2 0 0) - (edifLevel 0) - (keywordMap (keywordLevel 0)) - (status - (written - (timeStamp 2023 12 28 23 23 25) - (author "Synopsys, Inc.") - (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R")) - ) - ) - (library LUCENT - (edifLevel 0) - (technology (numberDefinition )) - (cell CCU2D (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A0 (direction INPUT)) - (port B0 (direction INPUT)) - (port C0 (direction INPUT)) - (port D0 (direction INPUT)) - (port A1 (direction INPUT)) - (port B1 (direction INPUT)) - (port C1 (direction INPUT)) - (port D1 (direction INPUT)) - (port CIN (direction INPUT)) - (port COUT (direction OUTPUT)) - (port S0 (direction OUTPUT)) - (port S1 (direction OUTPUT)) - ) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0000")) - (property INIT0 (string "0000")) - ) - ) - (cell BB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port B (direction INOUT)) - (port I (direction INPUT)) - (port T (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell OB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port I (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell IB (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port I (direction INPUT)) - (port O (direction OUTPUT)) - ) - ) - ) - (cell FD1S3IX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1S3AY (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1S3AX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port CK (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1P3IX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port CK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell OFS1P3IX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell OFS1P3DX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell IFS1P3DX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port CD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell OFS1P3BX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port SCLK (direction INPUT)) - (port PD (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell FD1P3AX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port D (direction INPUT)) - (port SP (direction INPUT)) - (port CK (direction INPUT)) - (port Q (direction OUTPUT)) - ) - ) - ) - (cell ORCALUT4 (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A (direction INPUT)) - (port B (direction INPUT)) - (port C (direction INPUT)) - (port D (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell PFUMX (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port ALUT (direction INPUT)) - (port BLUT (direction INPUT)) - (port C0 (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell GSR (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port GSR (direction INPUT)) - ) - ) - ) - (cell INV (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port A (direction INPUT)) - (port Z (direction OUTPUT)) - ) - ) - ) - (cell VHI (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port Z (direction OUTPUT)) - ) - ) - ) - (cell VLO (cellType GENERIC) - (view PRIM (viewType NETLIST) - (interface - (port Z (direction OUTPUT)) - ) - ) - ) - ) - (library work - (edifLevel 0) - (technology (numberDefinition )) - (cell EFB (cellType GENERIC) - (view verilog (viewType NETLIST) - (interface - (port WBCLKI (direction INPUT)) - (port WBRSTI (direction INPUT)) - (port WBCYCI (direction INPUT)) - (port WBSTBI (direction INPUT)) - (port WBWEI (direction INPUT)) - (port WBADRI7 (direction INPUT)) - (port WBADRI6 (direction INPUT)) - (port WBADRI5 (direction INPUT)) - (port WBADRI4 (direction INPUT)) - (port WBADRI3 (direction INPUT)) - (port WBADRI2 (direction INPUT)) - (port WBADRI1 (direction INPUT)) - (port WBADRI0 (direction INPUT)) - (port WBDATI7 (direction INPUT)) - (port WBDATI6 (direction INPUT)) - (port WBDATI5 (direction INPUT)) - (port WBDATI4 (direction INPUT)) - (port WBDATI3 (direction INPUT)) - (port WBDATI2 (direction INPUT)) - (port WBDATI1 (direction INPUT)) - (port WBDATI0 (direction INPUT)) - (port PLL0DATI7 (direction INPUT)) - (port PLL0DATI6 (direction INPUT)) - (port PLL0DATI5 (direction INPUT)) - (port PLL0DATI4 (direction INPUT)) - (port PLL0DATI3 (direction INPUT)) - (port PLL0DATI2 (direction INPUT)) - (port PLL0DATI1 (direction INPUT)) - (port PLL0DATI0 (direction INPUT)) - (port PLL0ACKI (direction INPUT)) - (port PLL1DATI7 (direction INPUT)) - (port PLL1DATI6 (direction INPUT)) - (port PLL1DATI5 (direction INPUT)) - (port PLL1DATI4 (direction INPUT)) - (port PLL1DATI3 (direction INPUT)) - (port PLL1DATI2 (direction INPUT)) - (port PLL1DATI1 (direction INPUT)) - (port PLL1DATI0 (direction INPUT)) - (port PLL1ACKI (direction INPUT)) - (port I2C1SCLI (direction INPUT)) - (port I2C1SDAI (direction INPUT)) - (port I2C2SCLI (direction INPUT)) - (port I2C2SDAI (direction INPUT)) - (port SPISCKI (direction INPUT)) - (port SPIMISOI (direction INPUT)) - (port SPIMOSII (direction INPUT)) - (port SPISCSN (direction INPUT)) - (port TCCLKI (direction INPUT)) - (port TCRSTN (direction INPUT)) - (port TCIC (direction INPUT)) - (port UFMSN (direction INPUT)) - (port WBDATO7 (direction OUTPUT)) - (port WBDATO6 (direction OUTPUT)) - (port WBDATO5 (direction OUTPUT)) - (port WBDATO4 (direction OUTPUT)) - (port WBDATO3 (direction OUTPUT)) - (port WBDATO2 (direction OUTPUT)) - (port WBDATO1 (direction OUTPUT)) - (port WBDATO0 (direction OUTPUT)) - (port WBACKO (direction OUTPUT)) - (port PLLCLKO (direction OUTPUT)) - (port PLLRSTO (direction OUTPUT)) - (port PLL0STBO (direction OUTPUT)) - (port PLL1STBO (direction OUTPUT)) - (port PLLWEO (direction OUTPUT)) - (port PLLADRO4 (direction OUTPUT)) - (port PLLADRO3 (direction OUTPUT)) - (port PLLADRO2 (direction OUTPUT)) - (port PLLADRO1 (direction OUTPUT)) - (port PLLADRO0 (direction OUTPUT)) - (port PLLDATO7 (direction OUTPUT)) - (port PLLDATO6 (direction OUTPUT)) - (port PLLDATO5 (direction OUTPUT)) - (port PLLDATO4 (direction OUTPUT)) - (port PLLDATO3 (direction OUTPUT)) - (port PLLDATO2 (direction OUTPUT)) - (port PLLDATO1 (direction OUTPUT)) - (port PLLDATO0 (direction OUTPUT)) - (port I2C1SCLO (direction OUTPUT)) - (port I2C1SCLOEN (direction OUTPUT)) - (port I2C1SDAO (direction OUTPUT)) - (port I2C1SDAOEN (direction OUTPUT)) - (port I2C2SCLO (direction OUTPUT)) - (port I2C2SCLOEN (direction OUTPUT)) - (port I2C2SDAO (direction OUTPUT)) - (port I2C2SDAOEN (direction OUTPUT)) - (port I2C1IRQO (direction OUTPUT)) - (port I2C2IRQO (direction OUTPUT)) - (port SPISCKO (direction OUTPUT)) - (port SPISCKEN (direction OUTPUT)) - (port SPIMISOO (direction OUTPUT)) - (port SPIMISOEN (direction OUTPUT)) - (port SPIMOSIO (direction OUTPUT)) - (port SPIMOSIEN (direction OUTPUT)) - (port SPIMCSN0 (direction OUTPUT)) - (port SPIMCSN1 (direction OUTPUT)) - (port SPIMCSN2 (direction OUTPUT)) - (port SPIMCSN3 (direction OUTPUT)) - (port SPIMCSN4 (direction OUTPUT)) - (port SPIMCSN5 (direction OUTPUT)) - (port SPIMCSN6 (direction OUTPUT)) - (port SPIMCSN7 (direction OUTPUT)) - (port SPICSNEN (direction OUTPUT)) - (port SPIIRQO (direction OUTPUT)) - (port TCINT (direction OUTPUT)) - (port TCOC (direction OUTPUT)) - (port WBCUFMIRQ (direction OUTPUT)) - (port CFGWAKE (direction OUTPUT)) - (port CFGSTDBY (direction OUTPUT)) - ) - (property TC_ICAPTURE (string "DISABLED")) - (property TC_OVERFLOW (string "DISABLED")) - (property TC_ICR_INT (string "OFF")) - (property TC_OCR_INT (string "OFF")) - (property TC_OV_INT (string "OFF")) - (property TC_TOP_SEL (string "OFF")) - (property TC_RESETN (string "ENABLED")) - (property TC_OC_MODE (string "TOGGLE")) - (property TC_OCR_SET (integer 32767)) - (property TC_TOP_SET (integer 65535)) - (property GSR (string "ENABLED")) - (property TC_CCLK_SEL (integer 1)) - (property TC_SCLK_SEL (string "PCLOCK")) - (property TC_MODE (string "CTCM")) - (property SPI_WAKEUP (string "DISABLED")) - (property SPI_INTR_RXOVR (string "DISABLED")) - (property SPI_INTR_TXOVR (string "DISABLED")) - (property SPI_INTR_RXRDY (string "DISABLED")) - (property SPI_INTR_TXRDY (string "DISABLED")) - (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) - (property SPI_PHASE_ADJ (string "DISABLED")) - (property SPI_CLK_INV (string "DISABLED")) - (property SPI_LSB_FIRST (string "DISABLED")) - (property SPI_CLK_DIVIDER (integer 1)) - (property SPI_MODE (string "MASTER")) - (property I2C2_WAKEUP (string "DISABLED")) - (property I2C1_WAKEUP (string "DISABLED")) - (property I2C2_GEN_CALL (string "DISABLED")) - (property I2C1_GEN_CALL (string "DISABLED")) - (property I2C2_CLK_DIVIDER (integer 1)) - (property I2C1_CLK_DIVIDER (integer 1)) - (property I2C2_BUS_PERF (string "100kHz")) - (property I2C1_BUS_PERF (string "100kHz")) - (property I2C2_SLAVE_ADDR (string "0b1000010")) - (property I2C1_SLAVE_ADDR (string "0b1000001")) - (property I2C2_ADDRESSING (string "7BIT")) - (property I2C1_ADDRESSING (string "7BIT")) - (property UFM_INIT_FILE_FORMAT (string "HEX")) - (property UFM_INIT_FILE_NAME (string "../RAM2E-LCMXO2.mem")) - (property UFM_INIT_ALL_ZEROS (string "DISABLED")) - (property UFM_INIT_START_PAGE (integer 190)) - (property UFM_INIT_PAGES (integer 1)) - (property DEV_DENSITY (string "640L")) - (property EFB_WB_CLK_FREQ (string "14.4")) - (property EFB_UFM (string "ENABLED")) - (property EFB_TC_PORTMODE (string "WB")) - (property EFB_TC (string "DISABLED")) - (property EFB_SPI (string "DISABLED")) - (property EFB_I2C2 (string "DISABLED")) - (property EFB_I2C1 (string "DISABLED")) - (property orig_inst_of (string "EFB")) - ) - ) - (cell REFB (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename wb_dato "wb_dato[7:0]") 8) (direction OUTPUT)) - (port (array (rename wb_dati "wb_dati[7:0]") 8) (direction INPUT)) - (port (array (rename wb_adr "wb_adr[7:0]") 8) (direction INPUT)) - (port wb_ack (direction OUTPUT)) - (port wb_we (direction INPUT)) - (port wb_cyc_stb (direction INPUT)) - (port wb_rst (direction INPUT)) - (port C14M_c (direction INPUT)) - ) - (contents - (instance EFBInst_0 (viewRef verilog (cellRef EFB)) - (property UFM_INIT_FILE_FORMAT (string "HEX")) - (property UFM_INIT_FILE_NAME (string "../RAM2E-LCMXO2.mem")) - (property UFM_INIT_ALL_ZEROS (string "DISABLED")) - (property UFM_INIT_START_PAGE (integer 190)) - (property UFM_INIT_PAGES (integer 1)) - (property DEV_DENSITY (string "640L")) - (property EFB_UFM (string "ENABLED")) - (property TC_ICAPTURE (string "DISABLED")) - (property TC_OVERFLOW (string "DISABLED")) - (property TC_ICR_INT (string "OFF")) - (property TC_OCR_INT (string "OFF")) - (property TC_OV_INT (string "OFF")) - (property TC_TOP_SEL (string "OFF")) - (property TC_RESETN (string "ENABLED")) - (property TC_OC_MODE (string "TOGGLE")) - (property TC_OCR_SET (integer 32767)) - (property TC_TOP_SET (integer 65535)) - (property GSR (string "ENABLED")) - (property TC_CCLK_SEL (integer 1)) - (property TC_MODE (string "CTCM")) - (property TC_SCLK_SEL (string "PCLOCK")) - (property EFB_TC_PORTMODE (string "WB")) - (property EFB_TC (string "DISABLED")) - (property SPI_WAKEUP (string "DISABLED")) - (property SPI_INTR_RXOVR (string "DISABLED")) - (property SPI_INTR_TXOVR (string "DISABLED")) - (property SPI_INTR_RXRDY (string "DISABLED")) - (property SPI_INTR_TXRDY (string "DISABLED")) - (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) - (property SPI_PHASE_ADJ (string "DISABLED")) - (property SPI_CLK_INV (string "DISABLED")) - (property SPI_LSB_FIRST (string "DISABLED")) - (property SPI_CLK_DIVIDER (integer 1)) - (property SPI_MODE (string "MASTER")) - (property EFB_SPI (string "DISABLED")) - (property I2C2_WAKEUP (string "DISABLED")) - (property I2C2_GEN_CALL (string "DISABLED")) - (property I2C2_CLK_DIVIDER (integer 1)) - (property I2C2_BUS_PERF (string "100kHz")) - (property I2C2_SLAVE_ADDR (string "0b1000010")) - (property I2C2_ADDRESSING (string "7BIT")) - (property EFB_I2C2 (string "DISABLED")) - (property I2C1_WAKEUP (string "DISABLED")) - (property I2C1_GEN_CALL (string "DISABLED")) - (property I2C1_CLK_DIVIDER (integer 1)) - (property I2C1_BUS_PERF (string "100kHz")) - (property I2C1_SLAVE_ADDR (string "0b1000001")) - (property I2C1_ADDRESSING (string "7BIT")) - (property EFB_I2C1 (string "DISABLED")) - (property EFB_WB_CLK_FREQ (string "14.4")) - ) - (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) - (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) - (net C14M_c (joined - (portRef C14M_c) - (portRef WBCLKI (instanceRef EFBInst_0)) - )) - (net wb_rst (joined - (portRef wb_rst) - (portRef WBRSTI (instanceRef EFBInst_0)) - )) - (net wb_cyc_stb (joined - (portRef wb_cyc_stb) - (portRef WBSTBI (instanceRef EFBInst_0)) - (portRef WBCYCI (instanceRef EFBInst_0)) - )) - (net wb_we (joined - (portRef wb_we) - (portRef WBWEI (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_7 "wb_adr[7]") (joined - (portRef (member wb_adr 0)) - (portRef WBADRI7 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_6 "wb_adr[6]") (joined - (portRef (member wb_adr 1)) - (portRef WBADRI6 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_5 "wb_adr[5]") (joined - (portRef (member wb_adr 2)) - (portRef WBADRI5 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_4 "wb_adr[4]") (joined - (portRef (member wb_adr 3)) - (portRef WBADRI4 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_3 "wb_adr[3]") (joined - (portRef (member wb_adr 4)) - (portRef WBADRI3 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_2 "wb_adr[2]") (joined - (portRef (member wb_adr 5)) - (portRef WBADRI2 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_1 "wb_adr[1]") (joined - (portRef (member wb_adr 6)) - (portRef WBADRI1 (instanceRef EFBInst_0)) - )) - (net (rename wb_adr_0 "wb_adr[0]") (joined - (portRef (member wb_adr 7)) - (portRef WBADRI0 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_7 "wb_dati[7]") (joined - (portRef (member wb_dati 0)) - (portRef WBDATI7 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_6 "wb_dati[6]") (joined - (portRef (member wb_dati 1)) - (portRef WBDATI6 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_5 "wb_dati[5]") (joined - (portRef (member wb_dati 2)) - (portRef WBDATI5 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_4 "wb_dati[4]") (joined - (portRef (member wb_dati 3)) - (portRef WBDATI4 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_3 "wb_dati[3]") (joined - (portRef (member wb_dati 4)) - (portRef WBDATI3 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_2 "wb_dati[2]") (joined - (portRef (member wb_dati 5)) - (portRef WBDATI2 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_1 "wb_dati[1]") (joined - (portRef (member wb_dati 6)) - (portRef WBDATI1 (instanceRef EFBInst_0)) - )) - (net (rename wb_dati_0 "wb_dati[0]") (joined - (portRef (member wb_dati 7)) - (portRef WBDATI0 (instanceRef EFBInst_0)) - )) - (net GND (joined - (portRef Z (instanceRef GND)) - (portRef TCIC (instanceRef EFBInst_0)) - (portRef TCRSTN (instanceRef EFBInst_0)) - (portRef TCCLKI (instanceRef EFBInst_0)) - (portRef SPISCSN (instanceRef EFBInst_0)) - (portRef SPIMOSII (instanceRef EFBInst_0)) - (portRef SPIMISOI (instanceRef EFBInst_0)) - (portRef SPISCKI (instanceRef EFBInst_0)) - (portRef I2C2SDAI (instanceRef EFBInst_0)) - (portRef I2C2SCLI (instanceRef EFBInst_0)) - (portRef I2C1SDAI (instanceRef EFBInst_0)) - (portRef I2C1SCLI (instanceRef EFBInst_0)) - (portRef PLL1ACKI (instanceRef EFBInst_0)) - (portRef PLL1DATI0 (instanceRef EFBInst_0)) - (portRef PLL1DATI1 (instanceRef EFBInst_0)) - (portRef PLL1DATI2 (instanceRef EFBInst_0)) - (portRef PLL1DATI3 (instanceRef EFBInst_0)) - (portRef PLL1DATI4 (instanceRef EFBInst_0)) - (portRef PLL1DATI5 (instanceRef EFBInst_0)) - (portRef PLL1DATI6 (instanceRef EFBInst_0)) - (portRef PLL1DATI7 (instanceRef EFBInst_0)) - (portRef PLL0ACKI (instanceRef EFBInst_0)) - (portRef PLL0DATI0 (instanceRef EFBInst_0)) - (portRef PLL0DATI1 (instanceRef EFBInst_0)) - (portRef PLL0DATI2 (instanceRef EFBInst_0)) - (portRef PLL0DATI3 (instanceRef EFBInst_0)) - (portRef PLL0DATI4 (instanceRef EFBInst_0)) - (portRef PLL0DATI5 (instanceRef EFBInst_0)) - (portRef PLL0DATI6 (instanceRef EFBInst_0)) - (portRef PLL0DATI7 (instanceRef EFBInst_0)) - )) - (net VCC (joined - (portRef Z (instanceRef VCC)) - (portRef UFMSN (instanceRef EFBInst_0)) - )) - (net (rename wb_dato_7 "wb_dato[7]") (joined - (portRef WBDATO7 (instanceRef EFBInst_0)) - (portRef (member wb_dato 0)) - )) - (net (rename wb_dato_6 "wb_dato[6]") (joined - (portRef WBDATO6 (instanceRef EFBInst_0)) - (portRef (member wb_dato 1)) - )) - (net (rename wb_dato_5 "wb_dato[5]") (joined - (portRef WBDATO5 (instanceRef EFBInst_0)) - (portRef (member wb_dato 2)) - )) - (net (rename wb_dato_4 "wb_dato[4]") (joined - (portRef WBDATO4 (instanceRef EFBInst_0)) - (portRef (member wb_dato 3)) - )) - (net (rename wb_dato_3 "wb_dato[3]") (joined - (portRef WBDATO3 (instanceRef EFBInst_0)) - (portRef (member wb_dato 4)) - )) - (net (rename wb_dato_2 "wb_dato[2]") (joined - (portRef WBDATO2 (instanceRef EFBInst_0)) - (portRef (member wb_dato 5)) - )) - (net (rename wb_dato_1 "wb_dato[1]") (joined - (portRef WBDATO1 (instanceRef EFBInst_0)) - (portRef (member wb_dato 6)) - )) - (net (rename wb_dato_0 "wb_dato[0]") (joined - (portRef WBDATO0 (instanceRef EFBInst_0)) - (portRef (member wb_dato 7)) - )) - (net wb_ack (joined - (portRef WBACKO (instanceRef EFBInst_0)) - (portRef wb_ack) - )) - (net PLLCLKO (joined - (portRef PLLCLKO (instanceRef EFBInst_0)) - )) - (net PLLRSTO (joined - (portRef PLLRSTO (instanceRef EFBInst_0)) - )) - (net PLL0STBO (joined - (portRef PLL0STBO (instanceRef EFBInst_0)) - )) - (net PLL1STBO (joined - (portRef PLL1STBO (instanceRef EFBInst_0)) - )) - (net PLLWEO (joined - (portRef PLLWEO (instanceRef EFBInst_0)) - )) - (net PLLADRO4 (joined - (portRef PLLADRO4 (instanceRef EFBInst_0)) - )) - (net PLLADRO3 (joined - (portRef PLLADRO3 (instanceRef EFBInst_0)) - )) - (net PLLADRO2 (joined - (portRef PLLADRO2 (instanceRef EFBInst_0)) - )) - (net PLLADRO1 (joined - (portRef PLLADRO1 (instanceRef EFBInst_0)) - )) - (net PLLADRO0 (joined - (portRef PLLADRO0 (instanceRef EFBInst_0)) - )) - (net PLLDATO7 (joined - (portRef PLLDATO7 (instanceRef EFBInst_0)) - )) - (net PLLDATO6 (joined - (portRef PLLDATO6 (instanceRef EFBInst_0)) - )) - (net PLLDATO5 (joined - (portRef PLLDATO5 (instanceRef EFBInst_0)) - )) - (net PLLDATO4 (joined - (portRef PLLDATO4 (instanceRef EFBInst_0)) - )) - (net PLLDATO3 (joined - (portRef PLLDATO3 (instanceRef EFBInst_0)) - )) - (net PLLDATO2 (joined - (portRef PLLDATO2 (instanceRef EFBInst_0)) - )) - (net PLLDATO1 (joined - (portRef PLLDATO1 (instanceRef EFBInst_0)) - )) - (net PLLDATO0 (joined - (portRef PLLDATO0 (instanceRef EFBInst_0)) - )) - (net I2C1SCLO (joined - (portRef I2C1SCLO (instanceRef EFBInst_0)) - )) - (net I2C1SCLOEN (joined - (portRef I2C1SCLOEN (instanceRef EFBInst_0)) - )) - (net I2C1SDAO (joined - (portRef I2C1SDAO (instanceRef EFBInst_0)) - )) - (net I2C1SDAOEN (joined - (portRef I2C1SDAOEN (instanceRef EFBInst_0)) - )) - (net I2C2SCLO (joined - (portRef I2C2SCLO (instanceRef EFBInst_0)) - )) - (net I2C2SCLOEN (joined - (portRef I2C2SCLOEN (instanceRef EFBInst_0)) - )) - (net I2C2SDAO (joined - (portRef I2C2SDAO (instanceRef EFBInst_0)) - )) - (net I2C2SDAOEN (joined - (portRef I2C2SDAOEN (instanceRef EFBInst_0)) - )) - (net I2C1IRQO (joined - (portRef I2C1IRQO (instanceRef EFBInst_0)) - )) - (net I2C2IRQO (joined - (portRef I2C2IRQO (instanceRef EFBInst_0)) - )) - (net SPISCKO (joined - (portRef SPISCKO (instanceRef EFBInst_0)) - )) - (net SPISCKEN (joined - (portRef SPISCKEN (instanceRef EFBInst_0)) - )) - (net SPIMISOO (joined - (portRef SPIMISOO (instanceRef EFBInst_0)) - )) - (net SPIMISOEN (joined - (portRef SPIMISOEN (instanceRef EFBInst_0)) - )) - (net SPIMOSIO (joined - (portRef SPIMOSIO (instanceRef EFBInst_0)) - )) - (net SPIMOSIEN (joined - (portRef SPIMOSIEN (instanceRef EFBInst_0)) - )) - (net SPIMCSN0 (joined - (portRef SPIMCSN0 (instanceRef EFBInst_0)) - )) - (net SPIMCSN1 (joined - (portRef SPIMCSN1 (instanceRef EFBInst_0)) - )) - (net SPIMCSN2 (joined - (portRef SPIMCSN2 (instanceRef EFBInst_0)) - )) - (net SPIMCSN3 (joined - (portRef SPIMCSN3 (instanceRef EFBInst_0)) - )) - (net SPIMCSN4 (joined - (portRef SPIMCSN4 (instanceRef EFBInst_0)) - )) - (net SPIMCSN5 (joined - (portRef SPIMCSN5 (instanceRef EFBInst_0)) - )) - (net SPIMCSN6 (joined - (portRef SPIMCSN6 (instanceRef EFBInst_0)) - )) - (net SPIMCSN7 (joined - (portRef SPIMCSN7 (instanceRef EFBInst_0)) - )) - (net SPICSNEN (joined - (portRef SPICSNEN (instanceRef EFBInst_0)) - )) - (net SPIIRQO (joined - (portRef SPIIRQO (instanceRef EFBInst_0)) - )) - (net TCINT (joined - (portRef TCINT (instanceRef EFBInst_0)) - )) - (net TCOC (joined - (portRef TCOC (instanceRef EFBInst_0)) - )) - (net wbc_ufm_irq (joined - (portRef WBCUFMIRQ (instanceRef EFBInst_0)) - )) - (net CFGWAKE (joined - (portRef CFGWAKE (instanceRef EFBInst_0)) - )) - (net CFGSTDBY (joined - (portRef CFGSTDBY (instanceRef EFBInst_0)) - )) - ) - (property NGD_DRC_MASK (integer 1)) - (property orig_inst_of (string "REFB")) - ) - ) - (cell RAM2E_UFM (cellType GENERIC) - (view netlist (viewType NETLIST) - (interface - (port (array (rename ra_35 "RA_35[11:0]") 12) (direction OUTPUT)) - (port (array (rename ain_c "Ain_c[7:0]") 8) (direction INPUT)) - (port CmdTout_3_0 (direction OUTPUT)) - (port (array (rename rwbank "RWBank[7:0]") 8) (direction INPUT)) - (port (array (rename fs "FS[15:0]") 16) (direction INPUT)) - (port (array (rename ra "RA[11:0]") 12) (direction INPUT)) - (port (array (rename rc_3 "RC_3[2:1]") 2) (direction OUTPUT)) - (port (array (rename rwbank_3 "RWBank_3[7:0]") 8) (direction OUTPUT)) - (port (array (rename din_c "Din_c[7:0]") 8) (direction INPUT)) - (port S_s_0_0_0 (direction OUTPUT)) - (port (array (rename ba_4 "BA_4[1:0]") 2) (direction OUTPUT)) - (port (array (rename cs "CS[2:0]") 3) (direction INPUT)) - (port (array (rename cmdtout "CmdTout[2:1]") 2) (direction INPUT)) - (port (array (rename rc "RC[2:1]") 2) (direction INPUT)) - (port (array (rename s "S[3:0]") 4) (direction INPUT)) - (port N_359_i (direction OUTPUT)) - (port CmdRWMaskSet_3 (direction OUTPUT)) - (port CmdLEDSet_3 (direction OUTPUT)) - (port N_667 (direction OUTPUT)) - (port N_666 (direction OUTPUT)) - (port N_665 (direction OUTPUT)) - (port N_664 (direction OUTPUT)) - (port N_663 (direction OUTPUT)) - (port N_662 (direction OUTPUT)) - (port N_648 (direction OUTPUT)) - (port CmdSetRWBankFFLED (direction INPUT)) - (port CmdLEDGet (direction INPUT)) - (port Vout3 (direction OUTPUT)) - (port un9_VOEEN_0_a2_0_a3_0_a3_1z (direction OUTPUT)) - (port N_263_i_1z (direction OUTPUT)) - (port N_508 (direction OUTPUT)) - (port RWSel_2 (direction OUTPUT)) - (port nC07X_c (direction INPUT)) - (port RDOE_i_1z (direction OUTPUT)) - (port LED_c (direction OUTPUT)) - (port Ready (direction INPUT)) - (port nDOE_c (direction OUTPUT)) - (port DOEEN (direction INPUT)) - (port nEN80_c (direction INPUT)) - (port N_360_i_1z (direction OUTPUT)) - (port N_368_i_1z (direction OUTPUT)) - (port N_507_i_1z (direction OUTPUT)) - (port un2_S_2_i_0_0_o3_RNIHFHN3_1z (direction OUTPUT)) - (port CmdLEDGet_3 (direction OUTPUT)) - (port N_126 (direction OUTPUT)) - (port N_362_i (direction OUTPUT)) - (port N_369_i_1z (direction OUTPUT)) - (port Ready3 (direction OUTPUT)) - (port CmdSetRWBankFFLED_4 (direction OUTPUT)) - (port N_361_i (direction OUTPUT)) - (port N_223 (direction OUTPUT)) - (port CmdLEDSet (direction INPUT)) - (port CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_1z (direction OUTPUT)) - (port CmdRWMaskSet (direction INPUT)) - (port CmdExecMXO2_3_0_a3_0_RNI6S1P8_1z (direction OUTPUT)) - (port N_370_i (direction OUTPUT)) - (port nWE_c (direction INPUT)) - (port N_358_i (direction OUTPUT)) - (port un1_CS_0_sqmuxa_i (direction OUTPUT)) - (port N_547_i (direction OUTPUT)) - (port C14M_c (direction INPUT)) - (port CO0_0 (direction INPUT)) - (port N_187_i_1z (direction OUTPUT)) - (port N_185_i (direction OUTPUT)) - (port CKE_7_RNIS77M1_1z (direction OUTPUT)) - (port N_372_i (direction OUTPUT)) - (port S_1 (direction INPUT)) - (port RWSel (direction INPUT)) - (port N_201_i_1z (direction OUTPUT)) - (port N_225_i_1z (direction OUTPUT)) - (port BA_0_sqmuxa (direction OUTPUT)) - (port CO0_1 (direction INPUT)) - (port RC12 (direction OUTPUT)) - (port N_551 (direction OUTPUT)) - ) - (contents - (instance wb_rst16_i_i_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) - ) - (instance (rename wb_dati_7_0_0_0_RNO_7 "wb_dati_7_0_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A))+D (B A))")) - ) - (instance nRAS_s_i_0_a3_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B !A))")) - ) - (instance un1_RC12_i_0_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B+A))")) - ) - (instance (rename wb_dati_7_0_0_a3_3_4 "wb_dati_7_0_0_a3_3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (!C (!B !A)))")) - ) - (instance (rename RA_35_2_0_a3_5_10 "RA_35_2_0_a3_5[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A)))")) - ) - (instance (rename un1_LEDEN_0_sqmuxa_1_i_0_0_RNO_0 "un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (B A)))")) - ) - (instance (rename wb_dati_7_0_0_0_0_RNO_7 "wb_dati_7_0_0_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B !A)))")) - ) - (instance (rename S_s_0_0_RNO_0 "S_s_0_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B !A)+C !A)")) - ) - (instance CKE_7_m1_0_0_o2_RNI7FOA1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance CKE_7_m1_0_0_o2_RNIGC501 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A))")) - ) - (instance (rename RC_3_0_0_1 "RC_3_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (!B A+B !A)+C (B !A))")) - ) - (instance N_314_i_i_o3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(!B+!A)))")) - ) - (instance nRAS_s_i_0_a3_5_RNIH7J73 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (B A)))")) - ) - (instance (rename wb_dati_7_0_0_a3_8_3 "wb_dati_7_0_0_a3_8[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B 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(viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (B A)))")) - ) - (instance (rename RA_35_2_0_RNO_10 "RA_35_2_0_RNO[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance (rename S_r_i_0_o2_RNIFNP81_0_2 "S_r_i_0_o2_RNIFNP81_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C A)+D (!C (!B+A)))")) - ) - (instance wb_req_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) - ) - (instance CmdBitbangMXO2_RNINSM62 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B+C (B+A))+D B)")) - ) - (instance wb_we_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C B+C (B+A))+D B)")) - ) - (instance (rename wb_dati_7_0_0_a3_13_RNI81UL_7 "wb_dati_7_0_0_a3_13_RNI81UL[7]") (viewRef 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PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_2 "RWMask[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_3 "RWMask[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_4 "RWMask[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_5 "RWMask[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_6 "RWMask[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWMask_7 "RWMask[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdSetRWBankFFChip (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdExecMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdBitbangMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename S_r_i_0_o2_RNIVM0LF_1 "S_r_i_0_o2_RNIVM0LF[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B+A))")) - ) - (instance un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance (rename S_r_i_0_o2_RNI3VQTC_1 "S_r_i_0_o2_RNI3VQTC[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B !A)))")) - ) - (instance (rename wb_adr_7_i_i_0 "wb_adr_7_i_i[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B A)))")) - ) - (instance un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C (!B A))+D (C A))")) - ) - (instance nRAS_s_i_0_0_RNI0PC64 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A)))")) - ) - (instance nCAS_s_i_0_a3_RNIO1UQ3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B !A))+D (!B !A))")) - ) - (instance (rename wb_dati_7_0_0_5 "wb_dati_7_0_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_2 "wb_dati_7_0_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_0_7 "wb_dati_7_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) - ) - (instance CmdExecMXO2_3_0_a3_0_RNI6S1P8 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C (B !A)+C !A))")) - ) - (instance (rename wb_dati_7_0_0_6 "wb_dati_7_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_4 "wb_dati_7_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) - ) - (instance un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C !B)+D (!C (!B !A)+C !B))")) - ) - (instance un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C (!B !A)))")) - ) - (instance (rename un1_RWMask_0_sqmuxa_1_i_0_0_0 "un1_RWMask_0_sqmuxa_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B A)+D (C+(!B A)))")) - ) - (instance (rename wb_dati_7_0_0_0_0 "wb_dati_7_0_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_1 "wb_dati_7_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!C (!B A+B !A)+C B)+D (!C (B !A)+C B))")) - ) - (instance (rename wb_dati_7_0_0_0_3 "wb_dati_7_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C A+C (B+A)))")) - ) - (instance (rename wb_adr_7_i_i_4_0 "wb_adr_7_i_i_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C+(B+A)))")) - ) - (instance (rename wb_adr_7_i_i_5_0 "wb_adr_7_i_i_5[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D C+D (C+(B !A)))")) - ) - (instance un1_CS_0_sqmuxa_0_0_m3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B+!A)+C (B A))")) - ) - (instance un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(C (!B !A)))")) - ) - (instance (rename un1_LEDEN_0_sqmuxa_1_i_0_0_0 "un1_LEDEN_0_sqmuxa_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (!B A)+D (C+(!B A)))")) - ) - (instance (rename un1_CmdSetRWBankFFChip13_1_i_0_0_0 "un1_CmdSetRWBankFFChip13_1_i_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C+(B !A))+D (C+!A))")) - ) - (instance (rename wb_dati_7_0_0_RNO_0_7 "wb_dati_7_0_0_RNO_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D (!C (B A)+C B))")) - ) - (instance (rename wb_dati_7_0_0_0_a3_7 "wb_dati_7_0_0_0_a3[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B !A+B A)))")) - ) - (instance (rename wb_adr_7_i_i_a3_6_0 "wb_adr_7_i_i_a3_6[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B A))")) - ) - (instance (rename RA_35_0_0_0_7 "RA_35_0_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B A))")) - ) - (instance (rename RA_35_0_0_0_6 "RA_35_0_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B A))")) - ) - (instance (rename RA_35_0_0_4 "RA_35_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B A))")) - ) - (instance (rename RA_35_0_0_3 "RA_35_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C+(B A))")) - ) - (instance (rename wb_dati_7_0_0_a3_2_4 "wb_dati_7_0_0_a3_2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D (C (!B !A)))")) - ) - (instance CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C A)+D (!C (!B A)+C A))")) - ) - (instance (rename wb_dati_7_0_0_0_0_3 "wb_dati_7_0_0_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_0_6 "wb_dati_7_0_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) - ) - (instance (rename wb_dati_7_0_0_0_4 "wb_dati_7_0_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!D (B A)+D (C+(B A)))")) - ) - (instance CKE_7_am (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C (B A))")) - ) - (instance CKE_7 (viewRef PRIM (cellRef PFUMX (libraryRef LUCENT))) ) - (instance wb_cyc_stb_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!C A+C (B+A))")) - ) - (instance CmdExecMXO2_3_0_a3_0_RNIPG3P2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(D+(!C 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(instance (rename RWBank_6 "RWBank[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RWBank_7 "RWBank[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RC_0 "RC[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RC_1 "RC[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RC_2 "RC[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_0 "RA[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_1 "RA[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_2 "RA[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_3 "RA[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_4 "RA[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_5 "RA[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_6 "RA[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_7 "RA[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_8 "RA[8]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_9 "RA[9]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_10 "RA[10]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename RA_11 "RA[11]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) - ) - (instance DOEEN (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename CmdTout_0 "CmdTout[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename CmdTout_1 "CmdTout[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename CmdTout_2 "CmdTout[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdSetRWBankFFLED (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdRWMaskSet (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdLEDSet (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance CmdLEDGet (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) - ) - (instance (rename CS_0 "CS[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename CS_1 "CS[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance (rename CS_2 "CS[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) - ) - (instance CKE (viewRef PRIM (cellRef FD1S3AY (libraryRef LUCENT))) - ) - (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) - (instance DQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance DQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_11 "RAout_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_10 "RAout_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_9 "RAout_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_8 "RAout_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_7 "RAout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_6 "RAout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_5 "RAout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_4 "RAout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_3 "RAout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_2 "RAout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_1 "RAout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename RAout_pad_0 "RAout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename BA_pad_1 "BA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename BA_pad_0 "BA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance nRWEout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance nCASout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance nRASout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance nCSout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance CKEout_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance nVOE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_7 "Vout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_6 "Vout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_5 "Vout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_4 "Vout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_3 "Vout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_2 "Vout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_1 "Vout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Vout_pad_0 "Vout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance nDOE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Ain_pad_7 "Ain_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Ain_pad_6 "Ain_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Ain_pad_5 "Ain_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Ain_pad_4 "Ain_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Ain_pad_3 "Ain_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Ain_pad_2 "Ain_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Ain_pad_1 "Ain_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance (rename Ain_pad_0 "Ain_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance nC07X_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance nEN80_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance nWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) - (instance PHI1_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) - ) - (instance C14M_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) - (instance nVOE_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(!B+A)")) - ) - (instance (rename SZ0Z_1 "S_1") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) - (property lut_function (string "(C (!B A))")) - ) - (instance (rename FS_s_0_15 "FS_s_0[15]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x5002")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_13 "FS_cry_0[13]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_11 "FS_cry_0[11]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_9 "FS_cry_0[9]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_7 "FS_cry_0[7]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_5 "FS_cry_0[5]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_3 "FS_cry_0[3]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_1 "FS_cry_0[1]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) - (property INIT0 (string "0x300A")) - (property INJECT1_1 (string "NO")) - (property INJECT1_0 (string "NO")) - (property INIT1 (string "0x300A")) - ) - (instance ram2e_ufm (viewRef netlist (cellRef RAM2E_UFM)) - ) - (net un9_VOEEN_0_a2_0_a3_0_a3 (joined - (portRef un9_VOEEN_0_a2_0_a3_0_a3_1z (instanceRef ram2e_ufm)) - (portRef SP (instanceRef RWSel)) - )) - (net (rename S_0 "S[0]") (joined - (portRef Q (instanceRef S_0)) - (portRef (member s 3) (instanceRef ram2e_ufm)) - (portRef C (instanceRef VOEEN_RNO)) - (portRef C (instanceRef DOEEN_RNO)) - )) - (net (rename S_1 "S[1]") (joined - (portRef Q (instanceRef S_1)) - (portRef (member s 2) (instanceRef ram2e_ufm)) - (portRef B (instanceRef VOEEN_RNO)) - (portRef B (instanceRef DOEEN_RNO)) - )) - (net (rename S_2 "S[2]") (joined - (portRef Q (instanceRef S_2)) - (portRef (member s 1) (instanceRef ram2e_ufm)) - (portRef A (instanceRef DOEEN_RNO)) - )) - (net (rename S_3 "S[3]") (joined - (portRef Q (instanceRef S_3)) - (portRef (member s 0) (instanceRef ram2e_ufm)) - (portRef D (instanceRef DOEEN)) - (portRef A (instanceRef VOEEN_RNO)) - )) - (net (rename FS_0 "FS[0]") (joined - (portRef Q (instanceRef FS_0)) - (portRef (member fs 15) (instanceRef ram2e_ufm)) - (portRef A1 (instanceRef FS_cry_0_0)) - )) - (net (rename FS_1 "FS[1]") (joined - (portRef Q (instanceRef FS_1)) - (portRef (member fs 14) (instanceRef ram2e_ufm)) - (portRef A0 (instanceRef FS_cry_0_1)) - )) - (net (rename FS_2 "FS[2]") (joined - (portRef Q (instanceRef FS_2)) - (portRef (member fs 13) (instanceRef ram2e_ufm)) - (portRef A1 (instanceRef FS_cry_0_1)) - )) - (net (rename FS_3 "FS[3]") (joined - (portRef Q (instanceRef FS_3)) - (portRef (member fs 12) (instanceRef ram2e_ufm)) - (portRef A0 (instanceRef FS_cry_0_3)) - )) - (net (rename FS_4 "FS[4]") (joined - (portRef Q (instanceRef FS_4)) - (portRef (member fs 11) (instanceRef ram2e_ufm)) - (portRef A1 (instanceRef FS_cry_0_3)) - )) - (net (rename FS_5 "FS[5]") (joined - (portRef Q (instanceRef FS_5)) - (portRef (member fs 10) (instanceRef ram2e_ufm)) - (portRef A0 (instanceRef FS_cry_0_5)) - )) - (net (rename FS_6 "FS[6]") (joined - (portRef Q (instanceRef FS_6)) - (portRef (member fs 9) (instanceRef ram2e_ufm)) - (portRef A1 (instanceRef FS_cry_0_5)) - )) - (net (rename FS_7 "FS[7]") (joined - (portRef Q (instanceRef FS_7)) - (portRef (member fs 8) (instanceRef ram2e_ufm)) - (portRef A0 (instanceRef FS_cry_0_7)) - )) - (net (rename FS_8 "FS[8]") (joined - (portRef Q (instanceRef FS_8)) - (portRef (member fs 7) (instanceRef ram2e_ufm)) - (portRef A1 (instanceRef FS_cry_0_7)) - )) - (net (rename FS_9 "FS[9]") (joined - (portRef Q (instanceRef FS_9)) - (portRef (member fs 6) (instanceRef ram2e_ufm)) - (portRef A0 (instanceRef FS_cry_0_9)) - )) - (net (rename FS_10 "FS[10]") (joined - (portRef Q (instanceRef FS_10)) - (portRef (member fs 5) (instanceRef ram2e_ufm)) - (portRef A1 (instanceRef FS_cry_0_9)) - )) - (net (rename FS_11 "FS[11]") (joined - (portRef Q (instanceRef FS_11)) - (portRef (member fs 4) (instanceRef ram2e_ufm)) - (portRef A0 (instanceRef FS_cry_0_11)) - )) - (net (rename FS_12 "FS[12]") (joined - (portRef Q (instanceRef FS_12)) - (portRef (member fs 3) (instanceRef ram2e_ufm)) - (portRef A1 (instanceRef FS_cry_0_11)) - )) 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index f497a02..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.mrp +++ /dev/null @@ -1,468 +0,0 @@ - - Lattice Mapping Report File for Design Module 'RAM2E' - - -Design Information ------------------- - -Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial - RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr - RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC - loud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify. - lpf -lpf //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset - //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml -Target Vendor: LATTICE -Target Device: LCMXO2-640HCTQFP100 -Target Performance: 4 -Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 -Mapped on: 12/28/23 23:23:28 - -Design Summary --------------- - - Number of registers: 122 out of 877 (14%) - PFU registers: 93 out of 640 (15%) - PIO registers: 29 out of 237 (12%) - Number of SLICEs: 148 out of 320 (46%) - SLICEs as Logic/ROM: 148 out of 320 (46%) - SLICEs as RAM: 0 out of 240 (0%) - SLICEs as Carry: 9 out of 320 (3%) - Number of LUT4s: 296 out of 640 (46%) - Number used as logic LUTs: 278 - Number used as distributed RAM: 0 - Number used as ripple logic: 18 - Number used as shift registers: 0 - Number of PIO sites used: 69 + 4(JTAG) out of 79 (92%) - Number of block RAMs: 0 out of 2 (0%) - Number of GSRs: 0 out of 1 (0%) - EFB used : Yes - JTAG used : No - Readback used : No - Oscillator used : No - Startup used : No - POR : On - Bandgap : On - Number of Power Controller: 0 out of 1 (0%) - Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) - Number of DCCA: 0 out of 8 (0%) - Number of DCMA: 0 out of 2 (0%) - Notes:- - 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of - distributed RAMs) + 2*(Number of ripple logic) - 2. Number of logic LUT4s does not include count of distributed RAM and - ripple logic. - Number of clocks: 1 - Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M ) - Number of Clock Enables: 14 - Net N_225_i: 2 loads, 0 LSLICEs - Net N_201_i: 2 loads, 0 LSLICEs - Net N_187_i: 11 loads, 11 LSLICEs - Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs - Net RC12: 2 loads, 2 LSLICEs - Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs - - Page 1 - - - - -Design: RAM2E Date: 12/28/23 23:23:28 - -Design Summary (cont) ---------------------- - Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs - Net N_185_i: 2 loads, 2 LSLICEs - Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs - Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs - Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs - Net N_126: 6 loads, 6 LSLICEs - Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs - Net Vout3: 8 loads, 0 LSLICEs - Number of LSRs: 7 - Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs - Net BA_0_sqmuxa: 2 loads, 0 LSLICEs - Net S[2]: 1 loads, 1 LSLICEs - Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs - Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs - Net N_1080_0: 1 loads, 1 LSLICEs - Net N_1078_0: 1 loads, 1 LSLICEs - Number of nets driven by tri-state buffers: 0 - Top 10 highest fanout non-clock nets: - Net S[2]: 50 loads - Net S[3]: 45 loads - Net S[0]: 37 loads - Net S[1]: 34 loads - Net FS[12]: 24 loads - Net FS[11]: 22 loads - Net FS[10]: 19 loads - Net FS[13]: 19 loads - Net FS[9]: 19 loads - Net FS[8]: 18 loads - - - - - Number of warnings: 3 - Number of errors: 0 - - -Design Errors/Warnings ----------------------- - -WARNING - map: //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf(93): Semantic - error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port - "nWE80" does not exist in the design. This preference has been disabled. -WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will - temporarily disable certain features of the device including Power - Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port. - Functionality is restored after the Flash Memory (UFM/Configuration) - Interface is disabled using Disable Configuration Interface command 0x26 - followed by Bypass command 0xFF. -WARNING - map: IO buffer missing for top level port nWE80...logic will be - discarded. - -IO (PIO) Attributes -------------------- - -+---------------------+-----------+-----------+------------+ -| IO Name | Direction | Levelmode | IO | - - Page 2 - - - - -Design: RAM2E Date: 12/28/23 23:23:28 - -IO (PIO) Attributes (cont) --------------------------- -| | | IO_TYPE | Register | -+---------------------+-----------+-----------+------------+ -| RD[0] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| LED | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| C14M | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[7] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[6] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[5] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[4] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[3] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[2] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| RD[1] | BIDIR | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| DQMH | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| DQML | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[11] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[10] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[9] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[8] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[7] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[6] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[5] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[4] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[3] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[2] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[1] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| RAout[0] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| BA[1] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| BA[0] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nRWEout | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ - - Page 3 - - - - -Design: RAM2E Date: 12/28/23 23:23:28 - -IO (PIO) Attributes (cont) --------------------------- -| nCASout | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nRASout | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nCSout | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| CKEout | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nVOE | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Vout[7] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[6] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[5] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[4] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[3] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[2] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[1] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| Vout[0] | OUTPUT | LVCMOS33 | OUT | -+---------------------+-----------+-----------+------------+ -| nDOE | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[7] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[6] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[5] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[4] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[3] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[2] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[1] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Dout[0] | OUTPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[7] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[6] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[5] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[4] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[3] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[2] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ - - Page 4 - - - - -Design: RAM2E Date: 12/28/23 23:23:28 - -IO (PIO) Attributes (cont) --------------------------- -| Din[1] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Din[0] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[7] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[6] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[5] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[4] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[3] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[2] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[1] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| Ain[0] | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| nC07X | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| nEN80 | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| nWE | INPUT | LVCMOS33 | | -+---------------------+-----------+-----------+------------+ -| PHI1 | INPUT | LVCMOS33 | IN | -+---------------------+-----------+-----------+------------+ - -Removed logic -------------- - -Block GSR_INST undriven or does not drive anything - clipped. -Block ram2e_ufm/VCC undriven or does not drive anything - clipped. -Block ram2e_ufm/GND undriven or does not drive anything - clipped. -Signal CKEout.CN was merged into signal C14M_c -Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped. -Signal FS_s_0_S1[15] undriven or does not drive anything - clipped. -Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything - - clipped. -Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped. - - Page 5 - - - - -Design: RAM2E Date: 12/28/23 23:23:28 - -Removed logic (cont) --------------------- -Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped. - -Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped. - -Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything - - clipped. -Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything - - clipped. -Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything - - clipped. -Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything - - clipped. -Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped. -Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped. -Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped. -Signal N_1 undriven or does not drive anything - clipped. -Block nCASout.CN was optimized away. -Block ram2e_ufm/ufmefb/VCC was optimized away. -Block ram2e_ufm/ufmefb/GND was optimized away. - - - -Embedded Functional Block Connection Summary --------------------------------------------- - - Desired WISHBONE clock frequency: 14.4 MHz - Clock source: C14M_c - Reset source: ram2e_ufm/wb_rst - Functions mode: - I2C #1 (Primary) Function: DISABLED - - Page 6 - - - - -Design: RAM2E Date: 12/28/23 23:23:28 - -Embedded Functional Block Connection Summary (cont) ---------------------------------------------------- - I2C #2 (Secondary) Function: DISABLED - SPI Function: DISABLED - Timer/Counter Function: DISABLED - Timer/Counter Mode: WB - UFM Connection: ENABLED - PLL0 Connection: DISABLED - PLL1 Connection: DISABLED - I2C Function Summary: - -------------------- - None - SPI Function Summary: - -------------------- - None - Timer/Counter Function Summary: - ------------------------------ - None - UFM Function Summary: - -------------------- - UFM Utilization: General Purpose Flash Memory - Initialized UFM Pages: 1 Pages (1*128 Bits) - Available General - Purpose Flash Memory: 191 Pages (191*128 Bits) - - EBR Blocks with Unique - Initialization Data: 0 - - WID EBR Instance - --- ------------ - - -ASIC Components ---------------- - -Instance Name: ram2e_ufm/ufmefb/EFBInst_0 - Type: EFB - -Run Time and Memory Usage -------------------------- - - Total CPU Time: 0 secs - Total REAL Time: 0 secs - Peak Memory Usage: 59 MB - - - - - - - - - - - - - - - - Page 7 - - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. - Copyright (c) 1995 AT&T Corp. All rights reserved. - Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. - Copyright (c) 2001 Agere Systems All rights reserved. - Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights - reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad deleted file mode 100644 index 5b02157..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad +++ /dev/null @@ -1,285 +0,0 @@ -PAD Specification File -*************************** - -PART TYPE: LCMXO2-640HC -Performance Grade: 4 -PACKAGE: TQFP100 -Package Status: Final Version 1.39 - -Thu Dec 28 23:23:38 2023 - -Pinout by Port Name: -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ -| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ -| Ain[0] | 3/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[1] | 2/3 | LVCMOS33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[2] | 7/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[3] | 4/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[4] | 78/0 | LVCMOS33_IN | PT11A | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[5] | 84/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[6] | 86/0 | LVCMOS33_IN | PT9C | | | CLAMP:ON HYSTERESIS:SMALL | -| Ain[7] | 8/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL | -| BA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW | -| BA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW | -| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL | -| CKEout | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW | -| DQMH | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW | -| DQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW | -| Din[0] | 96/0 | LVCMOS33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[1] | 97/0 | LVCMOS33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[2] | 98/0 | LVCMOS33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[3] | 9/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[4] | 1/3 | LVCMOS33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[5] | 99/0 | LVCMOS33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[6] | 88/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL | -| Din[7] | 87/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL | -| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:SLOW | -| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:SLOW | -| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:SLOW | -| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:SLOW | -| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:SLOW | -| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:SLOW | -| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:SLOW | -| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:SLOW | -| LED | 35/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW | -| PHI1 | 85/0 | LVCMOS33_IN | PT9D | | | CLAMP:ON HYSTERESIS:SMALL | -| RAout[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW | -| RAout[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW | -| RAout[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW | -| RAout[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW | -| RAout[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW | -| RAout[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW | -| RAout[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW | -| RAout[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW | -| RAout[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW | -| RAout[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW | -| RAout[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW | -| RAout[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW | -| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | -| Vout[0] | 18/3 | LVCMOS33_OUT | PL6C | | | DRIVE:4mA SLEW:SLOW | -| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW | -| Vout[2] | 17/3 | LVCMOS33_OUT | PL6B | | | DRIVE:4mA SLEW:SLOW | -| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW | -| Vout[4] | 19/3 | LVCMOS33_OUT | PL6D | | | DRIVE:4mA SLEW:SLOW | -| Vout[5] | 16/3 | LVCMOS33_OUT | PL6A | | | DRIVE:4mA SLEW:SLOW | -| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW | -| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW | -| nC07X | 34/2 | LVCMOS33_IN | PB6C | | | CLAMP:ON HYSTERESIS:SMALL | -| nCASout | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW | -| nCSout | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW | -| nDOE | 20/3 | LVCMOS33_OUT | PL7A | | | DRIVE:4mA SLEW:SLOW | -| nEN80 | 82/0 | LVCMOS33_IN | PT10C | | | CLAMP:ON HYSTERESIS:SMALL | -| nRASout | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW | -| nRWEout | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW | -| nVOE | 10/3 | LVCMOS33_OUT | PL3D | | | DRIVE:4mA SLEW:SLOW | -| nWE | 29/2 | LVCMOS33_IN | PB4C | | | CLAMP:ON HYSTERESIS:SMALL | -+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ - -Vccio by Bank: -+------+-------+ -| Bank | Vccio | -+------+-------+ -| 0 | 3.3V | -| 1 | 3.3V | -| 2 | 3.3V | -| 3 | 3.3V | -+------+-------+ - -Vref by Bank: -+------+-----+-----------------+---------+ -| Vref | Pin | Bank # / Vref # | Load(s) | -+------+-----+-----------------+---------+ -+------+-----+-----------------+---------+ - -Pinout by Pin Number: -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ -| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2A | | | | -| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2B | | | | -| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | | -| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL2D | PCLKC3_2 | | | -| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3A | | | | -| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3B | | | | -| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL3C | | | | -| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL3D | | | | -| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | | -| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | | -| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | | -| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | | -| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL6A | | | | -| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL6B | | | | -| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL6C | | | | -| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL6D | | | | -| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL7A | PCLKT3_0 | | | -| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL7B | PCLKC3_0 | | | -| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL7C | | | | -| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL7D | | | | -| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4A | CSSPIN | | | -| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4B | | | | -| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB4C | | | | -| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB4D | | | | -| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6A | MCLK/CCLK | | | -| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6B | SO/SPISO | | | -| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB6C | PCLKT2_0 | | | -| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB6D | PCLKC2_0 | | | -| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | | -| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | | -| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | | -| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | | -| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | | -| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | | -| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | | -| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | | -| 45/2 | unused, PULL:DOWN | | | PB14A | | | | -| 47/2 | unused, PULL:DOWN | | | PB14B | | | | -| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | | -| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | | -| 51/1 | nRWEout | LOCATED | LVCMOS33_OUT | PR7D | | | | -| 52/1 | nCASout | LOCATED | LVCMOS33_OUT | PR7C | | | | -| 53/1 | CKEout | LOCATED | LVCMOS33_OUT | PR7B | | | | -| 54/1 | nRASout | LOCATED | LVCMOS33_OUT | PR7A | | | | -| 57/1 | nCSout | LOCATED | LVCMOS33_OUT | PR6D | | | | -| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | | -| 59/1 | RAout[11] | LOCATED | LVCMOS33_OUT | PR6B | | | | -| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | | -| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | | -| 63/1 | RAout[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | | -| 64/1 | RAout[10] | LOCATED | LVCMOS33_OUT | PR5B | | | | -| 65/1 | RAout[8] | LOCATED | LVCMOS33_OUT | PR5A | | | | -| 66/1 | RAout[0] | LOCATED | LVCMOS33_OUT | PR3D | | | | -| 67/1 | RAout[7] | LOCATED | LVCMOS33_OUT | PR3C | | | | -| 68/1 | RAout[1] | LOCATED | LVCMOS33_OUT | PR3B | | | | -| 69/1 | RAout[6] | LOCATED | LVCMOS33_OUT | PR3A | | | | -| 70/1 | RAout[2] | LOCATED | LVCMOS33_OUT | PR2D | | | | -| 71/1 | RAout[5] | LOCATED | LVCMOS33_OUT | PR2C | | | | -| 74/1 | RAout[3] | LOCATED | LVCMOS33_OUT | PR2B | | | | -| 75/1 | RAout[4] | LOCATED | LVCMOS33_OUT | PR2A | | | | -| 76/0 | unused, PULL:DOWN | | | PT11D | DONE | | | -| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | | -| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT11A | | | | -| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | -| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT10C | JTAGENB | | | -| 83/0 | unused, PULL:DOWN | | | PT10B | | | | -| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT10A | | | | -| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT9D | SDA/PCLKC0_0 | | | -| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT9C | SCL/PCLKT0_0 | | | -| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT9B | PCLKC0_1 | | | -| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | | -| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | -| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | -| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | -| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | -| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT6D | | | | -| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6C | | | | -| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT6B | | | | -| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6A | | | | -| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | -+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ - -sysCONFIG Pins: -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | -+----------+--------------------+--------------------+----------+-------------+-------------------+ -| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | -| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | -| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | -| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | -+----------+--------------------+--------------------+----------+-------------+-------------------+ - -Dedicated sysCONFIG Pins: - - -List of All Pins' Locate Preferences Based on Final Placement After PAR -to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): - -LOCATE COMP "Ain[0]" SITE "3"; -LOCATE COMP "Ain[1]" SITE "2"; -LOCATE COMP "Ain[2]" SITE "7"; -LOCATE COMP "Ain[3]" SITE "4"; -LOCATE COMP "Ain[4]" SITE "78"; -LOCATE COMP "Ain[5]" SITE "84"; -LOCATE COMP "Ain[6]" SITE "86"; -LOCATE COMP "Ain[7]" SITE "8"; -LOCATE COMP "BA[0]" SITE "58"; -LOCATE COMP "BA[1]" SITE "60"; -LOCATE COMP "C14M" SITE "62"; -LOCATE COMP "CKEout" SITE "53"; -LOCATE COMP "DQMH" SITE "49"; -LOCATE COMP "DQML" SITE "48"; -LOCATE COMP "Din[0]" SITE "96"; -LOCATE COMP "Din[1]" SITE "97"; -LOCATE COMP "Din[2]" SITE "98"; -LOCATE COMP "Din[3]" SITE "9"; -LOCATE COMP "Din[4]" SITE "1"; -LOCATE COMP "Din[5]" SITE "99"; -LOCATE COMP "Din[6]" SITE "88"; -LOCATE COMP "Din[7]" SITE "87"; -LOCATE COMP "Dout[0]" SITE "30"; -LOCATE COMP "Dout[1]" SITE "27"; -LOCATE COMP "Dout[2]" SITE "25"; -LOCATE COMP "Dout[3]" SITE "28"; -LOCATE COMP "Dout[4]" SITE "24"; -LOCATE COMP "Dout[5]" SITE "21"; -LOCATE COMP "Dout[6]" SITE "31"; -LOCATE COMP "Dout[7]" SITE "32"; -LOCATE COMP "LED" SITE "35"; -LOCATE COMP "PHI1" SITE "85"; -LOCATE COMP "RAout[0]" SITE "66"; -LOCATE COMP "RAout[10]" SITE "64"; -LOCATE COMP "RAout[11]" SITE "59"; -LOCATE COMP "RAout[1]" SITE "68"; -LOCATE COMP "RAout[2]" SITE "70"; -LOCATE COMP "RAout[3]" SITE "74"; -LOCATE COMP "RAout[4]" SITE "75"; -LOCATE COMP "RAout[5]" SITE "71"; -LOCATE COMP "RAout[6]" SITE "69"; -LOCATE COMP "RAout[7]" SITE "67"; -LOCATE COMP "RAout[8]" SITE "65"; -LOCATE COMP "RAout[9]" SITE "63"; -LOCATE COMP "RD[0]" SITE "36"; -LOCATE COMP "RD[1]" SITE "37"; -LOCATE COMP "RD[2]" SITE "38"; -LOCATE COMP "RD[3]" SITE "39"; -LOCATE COMP "RD[4]" SITE "40"; -LOCATE COMP "RD[5]" SITE "41"; -LOCATE COMP "RD[6]" SITE "42"; -LOCATE COMP "RD[7]" SITE "43"; -LOCATE COMP "Vout[0]" SITE "18"; -LOCATE COMP "Vout[1]" SITE "15"; -LOCATE COMP "Vout[2]" SITE "17"; -LOCATE COMP "Vout[3]" SITE "13"; -LOCATE COMP "Vout[4]" SITE "19"; -LOCATE COMP "Vout[5]" SITE "16"; -LOCATE COMP "Vout[6]" SITE "14"; -LOCATE COMP "Vout[7]" SITE "12"; -LOCATE COMP "nC07X" SITE "34"; -LOCATE COMP "nCASout" SITE "52"; -LOCATE COMP "nCSout" SITE "57"; -LOCATE COMP "nDOE" SITE "20"; -LOCATE COMP "nEN80" SITE "82"; -LOCATE COMP "nRASout" SITE "54"; -LOCATE COMP "nRWEout" SITE "51"; -LOCATE COMP "nVOE" SITE "10"; -LOCATE COMP "nWE" SITE "29"; - - - - - -PAR: Place And Route Diamond (64-bit) 3.12.1.454. -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Dec 28 23:23:41 2023 - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf deleted file mode 100644 index 1c72043..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf +++ /dev/null @@ -1,126 +0,0 @@ -SCHEMATIC START ; -# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Dec 28 23:23:28 2023 - -SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; -LOCATE COMP "RD[0]" SITE "36" ; -LOCATE COMP "LED" SITE "35" ; -LOCATE COMP "C14M" SITE "62" ; -LOCATE COMP "RD[7]" SITE "43" ; -LOCATE COMP "RD[6]" SITE "42" ; -LOCATE COMP "RD[5]" SITE "41" ; -LOCATE COMP "RD[4]" SITE "40" ; -LOCATE COMP "RD[3]" SITE "39" ; -LOCATE COMP "RD[2]" SITE "38" ; -LOCATE COMP "RD[1]" SITE "37" ; -LOCATE COMP "DQMH" SITE "49" ; -LOCATE COMP "DQML" SITE "48" ; -LOCATE COMP "RAout[11]" SITE "59" ; -LOCATE COMP "RAout[10]" SITE "64" ; -LOCATE COMP "RAout[9]" SITE "63" ; -LOCATE COMP "RAout[8]" SITE "65" ; -LOCATE COMP "RAout[7]" SITE "67" ; -LOCATE COMP "RAout[6]" SITE "69" ; -LOCATE COMP "RAout[5]" SITE "71" ; -LOCATE COMP "RAout[4]" SITE "75" ; -LOCATE COMP "RAout[3]" SITE "74" ; -LOCATE COMP "RAout[2]" SITE "70" ; -LOCATE COMP "RAout[1]" SITE "68" ; -LOCATE COMP "RAout[0]" SITE "66" ; -LOCATE COMP "BA[1]" SITE "60" ; -LOCATE COMP "BA[0]" SITE "58" ; -LOCATE COMP "nRWEout" SITE "51" ; -LOCATE COMP "nCASout" SITE "52" ; -LOCATE COMP "nRASout" SITE "54" ; -LOCATE COMP "nCSout" SITE "57" ; -LOCATE COMP "CKEout" SITE "53" ; -LOCATE COMP "nVOE" SITE "10" ; -LOCATE COMP "Vout[7]" SITE "12" ; -LOCATE COMP "Vout[6]" SITE "14" ; -LOCATE COMP "Vout[5]" SITE "16" ; -LOCATE COMP "Vout[4]" SITE "19" ; -LOCATE COMP "Vout[3]" SITE "13" ; -LOCATE COMP "Vout[2]" SITE "17" ; -LOCATE COMP "Vout[1]" SITE "15" ; -LOCATE COMP "Vout[0]" SITE "18" ; -LOCATE COMP "nDOE" SITE "20" ; -LOCATE COMP "Dout[7]" SITE "32" ; -LOCATE COMP "Dout[6]" SITE "31" ; -LOCATE COMP "Dout[5]" SITE "21" ; -LOCATE COMP "Dout[4]" SITE "24" ; -LOCATE COMP "Dout[3]" SITE "28" ; -LOCATE COMP "Dout[2]" SITE "25" ; -LOCATE COMP "Dout[1]" SITE "27" ; -LOCATE COMP "Dout[0]" SITE "30" ; -LOCATE COMP "Din[7]" SITE "87" ; -LOCATE COMP "Din[6]" SITE "88" ; -LOCATE COMP "Din[5]" SITE "99" ; -LOCATE COMP "Din[4]" SITE "1" ; -LOCATE COMP "Din[3]" SITE "9" ; -LOCATE COMP "Din[2]" SITE "98" ; -LOCATE COMP "Din[1]" SITE "97" ; -LOCATE COMP "Din[0]" SITE "96" ; -LOCATE COMP "Ain[7]" SITE "8" ; -LOCATE COMP "Ain[6]" SITE "86" ; -LOCATE COMP "Ain[5]" SITE "84" ; -LOCATE COMP "Ain[4]" SITE "78" ; -LOCATE COMP "Ain[3]" SITE "4" ; -LOCATE COMP "Ain[2]" SITE "7" ; -LOCATE COMP "Ain[1]" SITE "2" ; -LOCATE COMP "Ain[0]" SITE "3" ; -LOCATE COMP "nC07X" SITE "34" ; -LOCATE COMP "nEN80" SITE "82" ; -LOCATE COMP "nWE" SITE "29" ; -LOCATE COMP "PHI1" SITE "85" ; -FREQUENCY PORT "C14M" 14.300000 MHz ; -SCHEMATIC END ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -OUTPUT PORT "LED" LOAD 100.000000 pF ; -OUTPUT PORT "BA[1]" LOAD 5.000000 pF ; -OUTPUT PORT "BA[0]" LOAD 5.000000 pF ; -OUTPUT PORT "CKEout" LOAD 5.000000 pF ; -OUTPUT PORT "DQMH" LOAD 5.000000 pF ; -OUTPUT PORT "DQML" LOAD 5.000000 pF ; -OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ; -OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ; -OUTPUT PORT "RAout[0]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[1]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[2]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[3]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[4]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[5]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[6]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[7]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[8]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[9]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[10]" LOAD 5.000000 pF ; -OUTPUT PORT "RAout[11]" LOAD 5.000000 pF ; -OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[3]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ; -OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ; -OUTPUT PORT "nCASout" LOAD 5.000000 pF ; -OUTPUT PORT "nCSout" LOAD 5.000000 pF ; -OUTPUT PORT "nDOE" LOAD 10.000000 pF ; -OUTPUT PORT "nRASout" LOAD 5.000000 pF ; -OUTPUT PORT "nRWEout" LOAD 5.000000 pF ; -OUTPUT PORT "nVOE" LOAD 10.000000 pF ; -OUTPUT PORT "RD[0]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[1]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[2]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[3]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[4]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[5]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[6]" LOAD 9.000000 pF ; -OUTPUT PORT "RD[7]" LOAD 9.000000 pF ; -COMMERCIAL ; diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr deleted file mode 100644 index 3418fc0..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr +++ /dev/null @@ -1,696 +0,0 @@ -#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 -#install: C:\lscc\diamond\3.12\synpbase -#OS: Windows 8 6.2 -#Hostname: ZANEMACWIN11 - -# Thu Dec 28 23:23:17 2023 - -#Implementation: impl1 - - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ - -@N|Running in 64-bit mode -###########################################################[ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ - -@N|Running in 64-bit mode -@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) -@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) -@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) -@I::"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v" (library work) -@I::"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v" (library work) -@I::"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v" (library work) -Verilog syntax check successful! -File \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v changed - recompiling -File \\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v changed - recompiling -Selecting top level module RAM2E -@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. -Running optimization stage 1 on VHI ....... -Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) -@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. -Running optimization stage 1 on VLO ....... -Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) -@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. -Running optimization stage 1 on EFB ....... -Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) -@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work. -Running optimization stage 1 on REFB ....... -Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) -@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work. -Running optimization stage 1 on RAM2E_UFM ....... -Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) -@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work. -Running optimization stage 1 on RAM2E ....... -Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) -Running optimization stage 2 on RAM2E ....... -@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused. -Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -Running optimization stage 2 on RAM2E_UFM ....... -@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused. -Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -Running optimization stage 2 on REFB ....... -Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -Running optimization stage 2 on EFB ....... -Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -Running optimization stage 2 on VLO ....... -Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -Running optimization stage 2 on VHI ....... -Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) - -At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Thu Dec 28 23:23:18 2023 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ - -@N|Running in 64-bit mode -File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\layer0.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Thu Dec 28 23:23:18 2023 - -###########################################################] - -For a summary of runtime and memory usage for all design units, please see file: -========================================================== -@L: A:\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv - -@END - -At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 31MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Thu Dec 28 23:23:18 2023 - -###########################################################] -###########################################################[ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ - -@N|Running in 64-bit mode -File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling - -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime - -Process completed successfully. -# Thu Dec 28 23:23:19 2023 - -###########################################################] -# Thu Dec 28 23:23:19 2023 - - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) - - -Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB) - -Reading constraint file: \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc -@L: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt -See clock summary report "\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt" -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB) - -@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2. -@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. -@N: FX493 |Applying initial value "0" on instance CmdExecMXO2. -@N: FX493 |Applying initial value "0" on instance PHI1r. -@N: FX493 |Applying initial value "0" on instance RWSel. -@N: FX493 |Applying initial value "0" on instance Ready. -@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0]. -@N: FX493 |Applying initial value "0" on instance CmdLEDGet. -@N: FX493 |Applying initial value "0" on instance CmdLEDSet. -@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet. -@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED. -@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP. -@N: FX493 |Applying initial value "1" on instance DQMH. -@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP. -@N: FX493 |Applying initial value "1" on instance DQML. -@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP. -@N: FX493 |Applying initial value "0000" on instance S[3:0]. -@N: FX493 |Applying initial value "1" on instance CKE. -@N: FX493 |Applying initial value "1" on instance nRWE. -@N: FX493 |Applying initial value "1" on instance nRWEout. -@N: FX493 |Applying initial value "1" on instance nCAS. -@N: FX493 |Applying initial value "1" on instance nCASout. -@N: FX493 |Applying initial value "1" on instance nRAS. -@N: FX493 |Applying initial value "1" on instance nRASout. - -Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) - - -Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) - - -Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) - - -Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) - -@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E - -Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) - - - -Clock Summary -****************** - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------- -0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122 - -0 - System 100.0 MHz 10.000 system system_clkgroup 0 -======================================================================================== - - - -Clock Load Summary -*********************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example ----------------------------------------------------------------------------------------- -C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv) - -System 0 - - - - -======================================================================================== - -ICG Latch Removal Summary: -Number of ICG latches removed: 0 -Number of ICG latches not removed: 0 -For details review file gcc_ICG_report.rpt - - -@S |Clock Optimization Summary - - - -#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ - -1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s) -0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) -0 instances converted, 0 sequential instances remain driven by gated/generated clocks - -=========================== Non-Gated/Non-Generated Clocks ============================ -Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------- -@KP:ckid0_0 C14M port 122 nRAS -======================================================================================= - - -##### END OF CLOCK OPTIMIZATION REPORT ###### - -@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. -Finished Pre Mapping Phase. - -Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) - - -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) - - -Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB) - -Pre-mapping successful! - -At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB) - -Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Dec 28 23:23:21 2023 - -###########################################################] -# Thu Dec 28 23:23:21 2023 - - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 -Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ - - -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) - -@N: MF916 |Option synthesis_strategy=base is enabled. -@N: MF248 |Running in 64-bit mode. -@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) - -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB) - - -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB) - - -Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) - - -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) - - - -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB) - - -Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) - -@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0] -@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. - -Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB) - - -Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) - - -Available hyper_sources - for debug and ip models - None Found - - -Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) - - -Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) - - -Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) - - -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) - - -Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB) - - -Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB) - -Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------- - 1 0h:00m:02s 33.71ns 284 / 122 - -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB) - -@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. -@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. -@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. - -Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB) - - -Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB) - -Writing Analyst data base \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm - -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB) - -Writing EDIF Netlist and constraint files -@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi -@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF - -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) - - -Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) - - -Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB) - -@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) -@N: MT615 |Found clock C14M with period 69.84ns - - -##### START OF TIMING REPORT #####[ -# Timing report written on Thu Dec 28 23:23:25 2023 -# - - -Top view: RAM2E -Requested Frequency: 14.3 MHz -Wire load mode: top -Paths requested: 5 -Constraint File(s): \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc - -@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. - -@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. - - - -Performance Summary -******************* - - -Worst slack in design: 33.707 - - Requested Estimated Requested Estimated Clock Clock -Starting Clock Frequency Frequency Period Period Slack Type Group -------------------------------------------------------------------------------------------------------------------- -C14M 14.3 MHz 128.0 MHz 69.841 7.813 33.707 declared default_clkgroup -System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup -=================================================================================================================== -Estimated period and frequency reported as NA means no slack depends directly on the clock waveform - - - - - -Clock Relationships -******************* - -Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------- -Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------- -System C14M | 69.841 67.088 | No paths - | No paths - | No paths - -C14M System | 69.841 68.797 | No paths - | No paths - | No paths - -C14M C14M | 69.841 62.028 | No paths - | 34.920 33.707 | No paths - -========================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - - -Interface Information -********************* - -No IO constraint found - - - -==================================== -Detailed Report for Clock: C14M -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------- -RA[0] C14M FD1P3AX Q RA[0] 1.108 33.707 -RA[3] C14M FD1P3AX Q RA[3] 1.108 33.707 -RA[1] C14M FD1P3AX Q RA[1] 1.044 33.771 -RA[2] C14M FD1P3AX Q RA[2] 1.044 33.771 -RA[4] C14M FD1P3AX Q RA[4] 1.044 33.771 -RA[5] C14M FD1P3AX Q RA[5] 1.044 33.771 -RA[6] C14M FD1P3AX Q RA[6] 1.044 33.771 -RA[7] C14M FD1P3AX Q RA[7] 1.044 33.771 -RA[8] C14M FD1P3AX Q RA[8] 1.044 33.771 -RA[9] C14M FD1P3AX Q RA[9] 1.044 33.771 -=========================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------- -RAout_0io[0] C14M OFS1P3DX D RA[0] 34.815 33.707 -RAout_0io[3] C14M OFS1P3DX D RA[3] 34.815 33.707 -RAout_0io[1] C14M OFS1P3DX D RA[1] 34.815 33.771 -RAout_0io[2] C14M OFS1P3DX D RA[2] 34.815 33.771 -RAout_0io[4] C14M OFS1P3DX D RA[4] 34.815 33.771 -RAout_0io[5] C14M OFS1P3DX D RA[5] 34.815 33.771 -RAout_0io[6] C14M OFS1P3DX D RA[6] 34.815 33.771 -RAout_0io[7] C14M OFS1P3DX D RA[7] 34.815 33.771 -RAout_0io[8] C14M OFS1P3DX D RA[8] 34.815 33.771 -RAout_0io[9] C14M OFS1P3DX D RA[9] 34.815 33.771 -================================================================================= - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 34.920 - - Setup time: 0.106 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 34.815 - - - Propagation time: 1.108 - - Clock delay at starting point: 0.000 (ideal) - = Slack (critical) : 33.707 - - Number of logic level(s): 0 - Starting point: RA[0] / Q - Ending point: RAout_0io[0] / D - The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK - The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------- -RA[0] FD1P3AX Q Out 1.108 1.108 r - -RA[0] Net - - - - 3 -RAout_0io[0] OFS1P3DX D In 0.000 1.108 r - -================================================================================= - - - - -==================================== -Detailed Report for Clock: System -==================================== - - - -Starting Points with Worst Slack -******************************** - - Starting Arrival -Instance Reference Type Pin Net Time Slack - Clock ---------------------------------------------------------------------------------------------------- -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313 -ram2e_ufm.ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313 -=================================================================================================== - - -Ending Points with Worst Slack -****************************** - - Starting Required -Instance Reference Type Pin Net Time Slack - Clock ----------------------------------------------------------------------------------------------------------------------- -ram2e_ufm.RWMask[0] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[1] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[2] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[3] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[4] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[5] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[6] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.RWMask[7] System FD1P3AX SP un1_RWMask_0_sqmuxa_1_i_0_0[0] 69.369 67.088 -ram2e_ufm.LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0_0[0] 69.369 67.736 -ram2e_ufm.wb_cyc_stb System FD1P3AX SP un1_CmdSetRWBankFFChip13_1_i_0_0[0] 69.369 67.736 -====================================================================================================================== - - - -Worst Path Information -*********************** - - -Path information for path number 1: - Requested Period: 69.841 - - Setup time: 0.472 - + Clock delay at ending point: 0.000 (ideal) - = Required time: 69.369 - - - Propagation time: 2.282 - - Clock delay at starting point: 0.000 (ideal) - - Estimated clock delay at start point: -0.000 - = Slack (non-critical) : 67.088 - - Number of logic level(s): 2 - Starting point: ram2e_ufm.ufmefb.EFBInst_0 / WBACKO - Ending point: ram2e_ufm.RWMask[0] / SP - The start point is clocked by System [rising] - The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK - -Instance / Net Pin Pin Arrival No. of -Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- -ram2e_ufm.ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r - -wb_ack Net - - - - 5 -ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 B In 0.000 0.000 r - -ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ORCALUT4 Z Out 1.017 1.017 r - -un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] Net - - - - 1 -ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 D In 0.000 1.017 r - -ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0] ORCALUT4 Z Out 1.265 2.282 r - -un1_RWMask_0_sqmuxa_1_i_0_0[0] Net - - - - 8 -ram2e_ufm.RWMask[0] FD1P3AX SP In 0.000 2.282 r - -================================================================================================================== - - - -##### END OF TIMING REPORT #####] - -Timing exceptions that could not be applied - -Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB) - - -Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB) - ---------------------------------------- -Resource Usage Report -Part: lcmxo2_640hc-4 - -Register bits: 122 of 640 (19%) -PIC Latch: 0 -I/O cells: 69 - - -Details: -BB: 8 -CCU2D: 9 -EFB: 1 -FD1P3AX: 61 -FD1P3IX: 1 -FD1S3AX: 21 -FD1S3AY: 4 -FD1S3IX: 6 -GSR: 1 -IB: 21 -IFS1P3DX: 1 -INV: 1 -OB: 40 -OFS1P3BX: 5 -OFS1P3DX: 21 -OFS1P3IX: 2 -ORCALUT4: 277 -PFUMX: 3 -PUR: 1 -VHI: 3 -VLO: 3 -Mapper successful! - -At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 217MB) - -Process took 0h:00m:04s realtime, 0h:00m:04s cputime -# Thu Dec 28 23:23:25 2023 - -###########################################################] diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.tw1 deleted file mode 100644 index 301cc7e..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.tw1 +++ /dev/null @@ -1,215 +0,0 @@ - -Loading design for application trce from file ram2e_lcmxo2_640hc_impl1_map.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:23:29 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf -Design file: ram2e_lcmxo2_640hc_impl1_map.ncd -Preference file: ram2e_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,4 -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; - 1611 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 58.937ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[2] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 10.827ns (31.6% logic, 68.4% route), 7 logic levels. - - Constraint Details: - - 10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 SLICE_34.CLK to SLICE_34.Q0 SLICE_34 (from C14M_c) -ROUTE 50 e 1.234 SLICE_34.Q0 to SLICE_35.A0 S[2] -CTOF_DEL --- 0.495 SLICE_35.A0 to SLICE_35.F0 SLICE_35 -ROUTE 7 e 1.234 SLICE_35.F0 to *m/SLICE_80.D1 N_551 -CTOF_DEL --- 0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80 -ROUTE 8 e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98 -ROUTE 5 e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781 -CTOF_DEL --- 0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99 -ROUTE 1 e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0] -CTOF_DEL --- 0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86 -ROUTE 1 e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47 -ROUTE 1 e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 10.827 (31.6% logic, 68.4% route), 7 logic levels. - -Report: 90.967MHz is the maximum frequency for this preference. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 90.967 MHz| 7 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 1 clocks: - -Clock Domain: C14M_c Source: C14M.PAD Loads: 89 - Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; - - -Timing summary (Setup): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:23:29 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf -Design file: ram2e_lcmxo2_640hc_impl1_map.ncd -Preference file: ram2e_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,M -Report level: verbose report, limited to 1 item per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; - 1611 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.447ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[0] (from C14M_c +) - Destination: FF Data in FS[0] (to C14M_c +) - - Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. - - Constraint Details: - - 0.434ns physical path delay SLICE_0 to SLICE_0 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns - - Physical Path Details: - - Data path SLICE_0 to SLICE_0: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c) -ROUTE 6 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0] -CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0 -ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c) - -------- - 0.434 (53.9% logic, 46.1% route), 2 logic levels. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 1 clocks: - -Clock Domain: C14M_c Source: C14M.PAD Loads: 89 - Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 0 (setup), 0 (hold) -Score: 0 (setup), 0 (hold) -Cumulative negative slack: 0 (0+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr deleted file mode 100644 index 20a9bf6..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr +++ /dev/null @@ -1,1139 +0,0 @@ - -Loading design for application trce from file ram2e_lcmxo2_640hc_impl1.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 4 -Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Setup and Hold Report - --------------------------------------------------------------------------------- -Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:23:44 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -Design file: ram2e_lcmxo2_640hc_impl1.ncd -Preference file: ram2e_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,4 -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; - 1611 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 57.938ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[0] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 11.826ns (24.8% logic, 75.2% route), 6 logic levels. - - Constraint Details: - - 11.826ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 57.938ns - - Physical Path Details: - - Data path SLICE_33 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C10C.CLK to R6C10C.Q0 SLICE_33 (from C14M_c) -ROUTE 37 2.491 R6C10C.Q0 to R6C9B.D1 S[0] -CTOF_DEL --- 0.495 R6C9B.D1 to R6C9B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.866 R6C9B.F1 to R3C5B.B1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 ram2e_ufm/SLICE_89 -ROUTE 6 1.040 R3C5B.F1 to R4C5C.B1 ram2e_ufm/N_783 -CTOF_DEL --- 0.495 R4C5C.B1 to R4C5C.F1 ram2e_ufm/SLICE_68 -ROUTE 1 0.967 R4C5C.F1 to R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0] -CTOF_DEL --- 0.495 R4C5A.A0 to R4C5A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 11.826 (24.8% logic, 75.2% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R6C10C.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 57.944ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[3] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 11.820ns (29.0% logic, 71.0% route), 7 logic levels. - - Constraint Details: - - 11.820ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 57.944ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C10D.CLK to R6C10D.Q1 SLICE_34 (from C14M_c) -ROUTE 45 1.001 R6C10D.Q1 to R6C10A.A0 S[3] -CTOF_DEL --- 0.495 R6C10A.A0 to R6C10A.F0 SLICE_35 -ROUTE 7 0.989 R6C10A.F0 to R6C9B.A1 N_551 -CTOF_DEL --- 0.495 R6C9B.A1 to R6C9B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.866 R6C9B.F1 to R3C5B.B1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 ram2e_ufm/SLICE_89 -ROUTE 6 1.040 R3C5B.F1 to R4C5C.B1 ram2e_ufm/N_783 -CTOF_DEL --- 0.495 R4C5C.B1 to R4C5C.F1 ram2e_ufm/SLICE_68 -ROUTE 1 0.967 R4C5C.F1 to R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0] -CTOF_DEL --- 0.495 R4C5A.A0 to R4C5A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 11.820 (29.0% logic, 71.0% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R6C10D.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.190ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[15] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 11.574ns (25.3% logic, 74.7% route), 6 logic levels. - - Constraint Details: - - 11.574ns physical path delay SLICE_1 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.190ns - - Physical Path Details: - - Data path SLICE_1 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R2C11A.CLK to R2C11A.Q0 SLICE_1 (from C14M_c) -ROUTE 9 2.239 R2C11A.Q0 to R6C9B.C1 FS[15] -CTOF_DEL --- 0.495 R6C9B.C1 to R6C9B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.866 R6C9B.F1 to R3C5B.B1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 ram2e_ufm/SLICE_89 -ROUTE 6 1.040 R3C5B.F1 to R4C5C.B1 ram2e_ufm/N_783 -CTOF_DEL --- 0.495 R4C5C.B1 to R4C5C.F1 ram2e_ufm/SLICE_68 -ROUTE 1 0.967 R4C5C.F1 to R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0] -CTOF_DEL --- 0.495 R4C5A.A0 to R4C5A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 11.574 (25.3% logic, 74.7% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R2C11A.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.271ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[2] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 11.493ns (29.8% logic, 70.2% route), 7 logic levels. - - Constraint Details: - - 11.493ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.271ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C10D.CLK to R6C10D.Q0 SLICE_34 (from C14M_c) -ROUTE 50 0.674 R6C10D.Q0 to R6C10A.D0 S[2] -CTOF_DEL --- 0.495 R6C10A.D0 to R6C10A.F0 SLICE_35 -ROUTE 7 0.989 R6C10A.F0 to R6C9B.A1 N_551 -CTOF_DEL --- 0.495 R6C9B.A1 to R6C9B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.866 R6C9B.F1 to R3C5B.B1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R3C5B.B1 to R3C5B.F1 ram2e_ufm/SLICE_89 -ROUTE 6 1.040 R3C5B.F1 to R4C5C.B1 ram2e_ufm/N_783 -CTOF_DEL --- 0.495 R4C5C.B1 to R4C5C.F1 ram2e_ufm/SLICE_68 -ROUTE 1 0.967 R4C5C.F1 to R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0] -CTOF_DEL --- 0.495 R4C5A.A0 to R4C5A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 11.493 (29.8% logic, 70.2% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R6C10D.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.733ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[0] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_dati[2] (to C14M_c +) - - Delay: 11.031ns (26.5% logic, 73.5% route), 6 logic levels. - - Constraint Details: - - 11.031ns physical path delay SLICE_33 to ram2e_ufm/SLICE_53 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.733ns - - Physical Path Details: - - Data path SLICE_33 to ram2e_ufm/SLICE_53: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C10C.CLK to R6C10C.Q0 SLICE_33 (from C14M_c) -ROUTE 37 2.491 R6C10C.Q0 to R6C9B.D1 S[0] -CTOF_DEL --- 0.495 R6C9B.D1 to R6C9B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 1.621 R6C9B.F1 to R2C7D.D1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 ram2e_ufm/SLICE_70 -ROUTE 3 0.981 R2C7D.F1 to R2C6D.A1 ram2e_ufm/N_807 -CTOF_DEL --- 0.495 R2C6D.A1 to R2C6D.F1 ram2e_ufm/SLICE_111 -ROUTE 3 2.253 R2C6D.F1 to R3C4C.A1 ram2e_ufm/N_611 -CTOF_DEL --- 0.495 R3C4C.A1 to R3C4C.F1 ram2e_ufm/SLICE_73 -ROUTE 2 0.758 R3C4C.F1 to R2C4B.C0 ram2e_ufm/wb_dati_7_0_0_o3_0[2] -CTOF_DEL --- 0.495 R2C4B.C0 to R2C4B.F0 ram2e_ufm/SLICE_53 -ROUTE 1 0.000 R2C4B.F0 to R2C4B.DI0 ram2e_ufm/wb_dati_7[2] (to C14M_c) - -------- - 11.031 (26.5% logic, 73.5% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R6C10C.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_53: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R2C4B.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.733ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[0] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_dati[5] (to C14M_c +) - - Delay: 11.031ns (26.5% logic, 73.5% route), 6 logic levels. - - Constraint Details: - - 11.031ns physical path delay SLICE_33 to ram2e_ufm/SLICE_54 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.733ns - - Physical Path Details: - - Data path SLICE_33 to ram2e_ufm/SLICE_54: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C10C.CLK to R6C10C.Q0 SLICE_33 (from C14M_c) -ROUTE 37 2.491 R6C10C.Q0 to R6C9B.D1 S[0] -CTOF_DEL --- 0.495 R6C9B.D1 to R6C9B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 1.621 R6C9B.F1 to R2C7D.D1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 ram2e_ufm/SLICE_70 -ROUTE 3 0.981 R2C7D.F1 to R2C6D.A1 ram2e_ufm/N_807 -CTOF_DEL --- 0.495 R2C6D.A1 to R2C6D.F1 ram2e_ufm/SLICE_111 -ROUTE 3 2.253 R2C6D.F1 to R3C4C.A1 ram2e_ufm/N_611 -CTOF_DEL --- 0.495 R3C4C.A1 to R3C4C.F1 ram2e_ufm/SLICE_73 -ROUTE 2 0.758 R3C4C.F1 to R2C4D.C1 ram2e_ufm/wb_dati_7_0_0_o3_0[2] -CTOF_DEL --- 0.495 R2C4D.C1 to R2C4D.F1 ram2e_ufm/SLICE_54 -ROUTE 1 0.000 R2C4D.F1 to R2C4D.DI1 ram2e_ufm/wb_dati_7[5] (to C14M_c) - -------- - 11.031 (26.5% logic, 73.5% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R6C10C.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_54: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R2C4D.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.739ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[3] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_dati[5] (to C14M_c +) - - Delay: 11.025ns (31.0% logic, 69.0% route), 7 logic levels. - - Constraint Details: - - 11.025ns physical path delay SLICE_34 to ram2e_ufm/SLICE_54 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.739ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_54: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C10D.CLK to R6C10D.Q1 SLICE_34 (from C14M_c) -ROUTE 45 1.001 R6C10D.Q1 to R6C10A.A0 S[3] -CTOF_DEL --- 0.495 R6C10A.A0 to R6C10A.F0 SLICE_35 -ROUTE 7 0.989 R6C10A.F0 to R6C9B.A1 N_551 -CTOF_DEL --- 0.495 R6C9B.A1 to R6C9B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 1.621 R6C9B.F1 to R2C7D.D1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 ram2e_ufm/SLICE_70 -ROUTE 3 0.981 R2C7D.F1 to R2C6D.A1 ram2e_ufm/N_807 -CTOF_DEL --- 0.495 R2C6D.A1 to R2C6D.F1 ram2e_ufm/SLICE_111 -ROUTE 3 2.253 R2C6D.F1 to R3C4C.A1 ram2e_ufm/N_611 -CTOF_DEL --- 0.495 R3C4C.A1 to R3C4C.F1 ram2e_ufm/SLICE_73 -ROUTE 2 0.758 R3C4C.F1 to R2C4D.C1 ram2e_ufm/wb_dati_7_0_0_o3_0[2] -CTOF_DEL --- 0.495 R2C4D.C1 to R2C4D.F1 ram2e_ufm/SLICE_54 -ROUTE 1 0.000 R2C4D.F1 to R2C4D.DI1 ram2e_ufm/wb_dati_7[5] (to C14M_c) - -------- - 11.025 (31.0% logic, 69.0% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R6C10D.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_54: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R2C4D.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.739ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[3] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_dati[2] (to C14M_c +) - - Delay: 11.025ns (31.0% logic, 69.0% route), 7 logic levels. - - Constraint Details: - - 11.025ns physical path delay SLICE_34 to ram2e_ufm/SLICE_53 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.739ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_53: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C10D.CLK to R6C10D.Q1 SLICE_34 (from C14M_c) -ROUTE 45 1.001 R6C10D.Q1 to R6C10A.A0 S[3] -CTOF_DEL --- 0.495 R6C10A.A0 to R6C10A.F0 SLICE_35 -ROUTE 7 0.989 R6C10A.F0 to R6C9B.A1 N_551 -CTOF_DEL --- 0.495 R6C9B.A1 to R6C9B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 1.621 R6C9B.F1 to R2C7D.D1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R2C7D.D1 to R2C7D.F1 ram2e_ufm/SLICE_70 -ROUTE 3 0.981 R2C7D.F1 to R2C6D.A1 ram2e_ufm/N_807 -CTOF_DEL --- 0.495 R2C6D.A1 to R2C6D.F1 ram2e_ufm/SLICE_111 -ROUTE 3 2.253 R2C6D.F1 to R3C4C.A1 ram2e_ufm/N_611 -CTOF_DEL --- 0.495 R3C4C.A1 to R3C4C.F1 ram2e_ufm/SLICE_73 -ROUTE 2 0.758 R3C4C.F1 to R2C4B.C0 ram2e_ufm/wb_dati_7_0_0_o3_0[2] -CTOF_DEL --- 0.495 R2C4B.C0 to R2C4B.F0 ram2e_ufm/SLICE_53 -ROUTE 1 0.000 R2C4B.F0 to R2C4B.DI0 ram2e_ufm/wb_dati_7[2] (to C14M_c) - -------- - 11.025 (31.0% logic, 69.0% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R6C10D.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_53: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R2C4B.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.780ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[0] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 10.984ns (26.6% logic, 73.4% route), 6 logic levels. - - Constraint Details: - - 10.984ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.780ns - - Physical Path Details: - - Data path SLICE_33 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C10C.CLK to R6C10C.Q0 SLICE_33 (from C14M_c) -ROUTE 37 2.491 R6C10C.Q0 to R6C9B.D1 S[0] -CTOF_DEL --- 0.495 R6C9B.D1 to R6C9B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.182 R6C9B.F1 to R2C5A.C1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R2C5A.C1 to R2C5A.F1 ram2e_ufm/SLICE_98 -ROUTE 5 1.413 R2C5A.F1 to R4C5B.D0 ram2e_ufm/N_781 -CTOF_DEL --- 0.495 R4C5B.D0 to R4C5B.F0 ram2e_ufm/SLICE_126 -ROUTE 1 0.436 R4C5B.F0 to R4C5A.C0 ram2e_ufm/N_753 -CTOF_DEL --- 0.495 R4C5A.C0 to R4C5A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 10.984 (26.6% logic, 73.4% route), 6 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_33: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R6C10C.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 58.786ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q S[3] (from C14M_c +) - Destination: FF Data in ram2e_ufm/wb_adr[0] (to C14M_c +) - - Delay: 10.978ns (31.2% logic, 68.8% route), 7 logic levels. - - Constraint Details: - - 10.978ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets - 69.930ns delay constraint less - 0.000ns skew and - 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.786ns - - Physical Path Details: - - Data path SLICE_34 to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.452 R6C10D.CLK to R6C10D.Q1 SLICE_34 (from C14M_c) -ROUTE 45 1.001 R6C10D.Q1 to R6C10A.A0 S[3] -CTOF_DEL --- 0.495 R6C10A.A0 to R6C10A.F0 SLICE_35 -ROUTE 7 0.989 R6C10A.F0 to R6C9B.A1 N_551 -CTOF_DEL --- 0.495 R6C9B.A1 to R6C9B.F1 ram2e_ufm/SLICE_80 -ROUTE 8 2.182 R6C9B.F1 to R2C5A.C1 ram2e_ufm/N_777 -CTOF_DEL --- 0.495 R2C5A.C1 to R2C5A.F1 ram2e_ufm/SLICE_98 -ROUTE 5 1.413 R2C5A.F1 to R4C5B.D0 ram2e_ufm/N_781 -CTOF_DEL --- 0.495 R4C5B.D0 to R4C5B.F0 ram2e_ufm/SLICE_126 -ROUTE 1 0.436 R4C5B.F0 to R4C5A.C0 ram2e_ufm/N_753 -CTOF_DEL --- 0.495 R4C5A.C0 to R4C5A.F0 ram2e_ufm/SLICE_86 -ROUTE 1 1.535 R4C5A.F0 to R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0] -CTOF_DEL --- 0.495 R3C6C.B0 to R3C6C.F0 ram2e_ufm/SLICE_47 -ROUTE 1 0.000 R3C6C.F0 to R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c) - -------- - 10.978 (31.2% logic, 68.8% route), 7 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_34: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R6C10D.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to ram2e_ufm/SLICE_47: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 3.070 62.PADDI to R3C6C.CLK C14M_c - -------- - 3.070 (0.0% logic, 100.0% route), 0 logic levels. - -Report: 83.389MHz is the maximum frequency for this preference. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 83.389 MHz| 6 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 1 clocks: - -Clock Domain: C14M_c Source: C14M.PAD Loads: 89 - Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; - - -Timing summary (Setup): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) - --------------------------------------------------------------------------------- -Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:23:44 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -Report Information ------------------- -Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -Design file: ram2e_lcmxo2_640hc_impl1.ncd -Preference file: ram2e_lcmxo2_640hc_impl1.prf -Device,speed: LCMXO2-640HC,m -Report level: verbose report, limited to 10 items per preference --------------------------------------------------------------------------------- - -BLOCK ASYNCPATHS -BLOCK RESETPATHS --------------------------------------------------------------------------------- - - - -================================================================================ -Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; - 1611 items scored, 0 timing errors detected. --------------------------------------------------------------------------------- - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[15] (from C14M_c +) - Destination: FF Data in FS[15] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_1 to SLICE_1 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_1 to SLICE_1: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C11A.CLK to R2C11A.Q0 SLICE_1 (from C14M_c) -ROUTE 9 0.132 R2C11A.Q0 to R2C11A.A0 FS[15] -CTOF_DEL --- 0.101 R2C11A.A0 to R2C11A.F0 SLICE_1 -ROUTE 1 0.000 R2C11A.F0 to R2C11A.DI0 FS_s[15] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C11A.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_1: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C11A.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdTout[2] (from C14M_c +) - Destination: FF Data in CmdTout[2] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_18 to SLICE_18 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_18 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9B.CLK to R5C9B.Q1 SLICE_18 (from C14M_c) -ROUTE 2 0.132 R5C9B.Q1 to R5C9B.A1 CmdTout[2] -CTOF_DEL --- 0.101 R5C9B.A1 to R5C9B.F1 SLICE_18 -ROUTE 1 0.000 R5C9B.F1 to R5C9B.DI1 N_369_i (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R5C9B.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R5C9B.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q CmdTout[1] (from C14M_c +) - Destination: FF Data in CmdTout[1] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_18 to SLICE_18 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_18 to SLICE_18: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C9B.CLK to R5C9B.Q0 SLICE_18 (from C14M_c) -ROUTE 3 0.132 R5C9B.Q0 to R5C9B.A0 CmdTout[1] -CTOF_DEL --- 0.101 R5C9B.A0 to R5C9B.F0 SLICE_18 -ROUTE 1 0.000 R5C9B.F0 to R5C9B.DI0 N_368_i (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R5C9B.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_18: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R5C9B.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[13] (from C14M_c +) - Destination: FF Data in FS[13] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_2 to SLICE_2 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_2 to SLICE_2: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C10D.CLK to R2C10D.Q0 SLICE_2 (from C14M_c) -ROUTE 19 0.132 R2C10D.Q0 to R2C10D.A0 FS[13] -CTOF_DEL --- 0.101 R2C10D.A0 to R2C10D.F0 SLICE_2 -ROUTE 1 0.000 R2C10D.F0 to R2C10D.DI0 FS_s[13] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C10D.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_2: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C10D.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA[9] (from C14M_c +) - Destination: FF Data in RA[9] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_24 to SLICE_24 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_24 to SLICE_24: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C11A.CLK to R5C11A.Q1 SLICE_24 (from C14M_c) -ROUTE 2 0.132 R5C11A.Q1 to R5C11A.A1 RA[9] -CTOF_DEL --- 0.101 R5C11A.A1 to R5C11A.F1 SLICE_24 -ROUTE 1 0.000 R5C11A.F1 to R5C11A.DI1 RA_35[9] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R5C11A.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_24: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R5C11A.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q RA[11] (from C14M_c +) - Destination: FF Data in RA[11] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_25 to SLICE_25 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_25 to SLICE_25: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R5C10B.CLK to R5C10B.Q1 SLICE_25 (from C14M_c) -ROUTE 2 0.132 R5C10B.Q1 to R5C10B.A1 RA[11] -CTOF_DEL --- 0.101 R5C10B.A1 to R5C10B.F1 SLICE_25 -ROUTE 1 0.000 R5C10B.F1 to R5C10B.DI1 RA_35[11] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_25: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R5C10B.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_25: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R5C10B.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[12] (from C14M_c +) - Destination: FF Data in FS[12] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_3 to SLICE_3 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_3 to SLICE_3: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C10C.CLK to R2C10C.Q1 SLICE_3 (from C14M_c) -ROUTE 24 0.132 R2C10C.Q1 to R2C10C.A1 FS[12] -CTOF_DEL --- 0.101 R2C10C.A1 to R2C10C.F1 SLICE_3 -ROUTE 1 0.000 R2C10C.F1 to R2C10C.DI1 FS_s[12] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C10C.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_3: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C10C.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[10] (from C14M_c +) - Destination: FF Data in FS[10] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_4 to SLICE_4 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_4 to SLICE_4: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C10B.CLK to R2C10B.Q1 SLICE_4 (from C14M_c) -ROUTE 19 0.132 R2C10B.Q1 to R2C10B.A1 FS[10] -CTOF_DEL --- 0.101 R2C10B.A1 to R2C10B.F1 SLICE_4 -ROUTE 1 0.000 R2C10B.F1 to R2C10B.DI1 FS_s[10] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C10B.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_4: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C10B.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[7] (from C14M_c +) - Destination: FF Data in FS[7] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_5 to SLICE_5 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_5 to SLICE_5: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C10A.CLK to R2C10A.Q0 SLICE_5 (from C14M_c) -ROUTE 4 0.132 R2C10A.Q0 to R2C10A.A0 FS[7] -CTOF_DEL --- 0.101 R2C10A.A0 to R2C10A.F0 SLICE_5 -ROUTE 1 0.000 R2C10A.F0 to R2C10A.DI0 FS_s[7] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C10A.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_5: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C10A.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - -Passed: The following path meets requirements by 0.379ns - - Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) - - Source: FF Q FS[6] (from C14M_c +) - Destination: FF Data in FS[6] (to C14M_c +) - - Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. - - Constraint Details: - - 0.366ns physical path delay SLICE_6 to SLICE_6 meets - -0.013ns DIN_HLD and - 0.000ns delay constraint less - 0.000ns skew requirement (totaling -0.013ns) by 0.379ns - - Physical Path Details: - - Data path SLICE_6 to SLICE_6: - - Name Fanout Delay (ns) Site Resource -REG_DEL --- 0.133 R2C9D.CLK to R2C9D.Q1 SLICE_6 (from C14M_c) -ROUTE 4 0.132 R2C9D.Q1 to R2C9D.A1 FS[6] -CTOF_DEL --- 0.101 R2C9D.A1 to R2C9D.F1 SLICE_6 -ROUTE 1 0.000 R2C9D.F1 to R2C9D.DI1 FS_s[6] (to C14M_c) - -------- - 0.366 (63.9% logic, 36.1% route), 2 logic levels. - - Clock Skew Details: - - Source Clock Path C14M to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C9D.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - - Destination Clock Path C14M to SLICE_6: - - Name Fanout Delay (ns) Site Resource -ROUTE 89 1.059 62.PADDI to R2C9D.CLK C14M_c - -------- - 1.059 (0.0% logic, 100.0% route), 0 logic levels. - -Report Summary --------------- ----------------------------------------------------------------------------- -Preference(MIN Delays) | Constraint| Actual|Levels ----------------------------------------------------------------------------- - | | | -FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2 - | | | ----------------------------------------------------------------------------- - - -All preferences were met. - - -Clock Domains Analysis ------------------------- - -Found 1 clocks: - -Clock Domain: C14M_c Source: C14M.PAD Loads: 89 - Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; - - -Timing summary (Hold): ---------------- - -Timing errors: 0 Score: 0 -Cumulative negative slack: 0 - -Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) - - - -Timing summary (Setup and Hold): ---------------- - -Timing errors: 0 (setup), 0 (hold) -Score: 0 (setup), 0 (hold) -Cumulative negative slack: 0 (0+0) --------------------------------------------------------------------------------- - --------------------------------------------------------------------------------- - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html deleted file mode 100644 index bc51171..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html +++ /dev/null @@ -1,152 +0,0 @@ - -Bitgen Report - - -
    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Dec 28 23:23:55 2023
-
-
-Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
-
-Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-
-Running DRC.
-DRC detected 0 errors and 0 warnings.
-Reading Preference File from RAM2E_LCMXO2_640HC_impl1.prf.
-
-
-Preference Summary:
-
-+---------------------------------+---------------------------------+
-|  Preference                     |  Current Setting                |
-+---------------------------------+---------------------------------+
-|                         RamCfg  |                        Reset**  |
-+---------------------------------+---------------------------------+
-|                     MCCLK_FREQ  |                         2.08**  |
-+---------------------------------+---------------------------------+
-|                  CONFIG_SECURE  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                          INBUF  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                      JTAG_PORT  |                       ENABLE**  |
-+---------------------------------+---------------------------------+
-|                       SDM_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                 SLAVE_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                MASTER_SPI_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                       I2C_PORT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                  CONFIGURATION  |                          CFG**  |
-+---------------------------------+---------------------------------+
-|                COMPRESS_CONFIG  |                           ON**  |
-+---------------------------------+---------------------------------+
-|                        MY_ASSP  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|               ONE_TIME_PROGRAM  |                          OFF**  |
-+---------------------------------+---------------------------------+
-|                 ENABLE_TRANSFR  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|                  SHAREDEBRINIT  |                      DISABLE**  |
-+---------------------------------+---------------------------------+
-|            BACKGROUND_RECONFIG  |                          OFF**  |
-+---------------------------------+---------------------------------+
- *  Default setting.
- ** The specified setting matches the default setting.
-
-
-Creating bit map...
- 
-Bitstream Status: Final           Version 1.95.
- 
-Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.jed".
- 
-===========
-UFM Summary.
-===========
-UFM Size:        191 Pages (128*191 Bits).
-UFM Utilization: General Purpose Flash Memory.
- 
-Available General Purpose Flash Memory:  191 Pages (Page 0 to Page 190).
-Initialized UFM Pages:                     1 Page (Page 190).
- 
-Total CPU Time: 3 secs 
-Total REAL Time: 3 secs 
-Peak Memory Usage: 267 MB
-
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    - - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt deleted file mode 100644 index e904e24..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt +++ /dev/null @@ -1,152 +0,0 @@ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 - -# Written on Thu Dec 28 23:23:21 2023 - -##### DESIGN INFO ####################################################### - -Top View: "RAM2E" -Constraint File(s): "\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc" - - - - -##### SUMMARY ############################################################ - -Found 0 issues in 0 out of 1 constraints - - -##### DETAILS ############################################################ - - - -Clock Relationships -******************* - -Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------ -System C14M | 69.841 | No paths | No paths | No paths -C14M System | 69.841 | No paths | No paths | No paths -C14M C14M | 69.841 | No paths | 34.920 | No paths -=================================================================================================================================== - Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. - 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. - - -Unconstrained Start/End Points -****************************** - -p:Ain[0] -p:Ain[1] -p:Ain[2] -p:Ain[3] -p:Ain[4] -p:Ain[5] -p:Ain[6] -p:Ain[7] -p:BA[0] -p:BA[1] -p:CKEout -p:DQMH -p:DQML -p:Din[0] -p:Din[1] -p:Din[2] -p:Din[3] -p:Din[4] -p:Din[5] -p:Din[6] -p:Din[7] -p:Dout[0] -p:Dout[1] -p:Dout[2] -p:Dout[3] -p:Dout[4] -p:Dout[5] -p:Dout[6] -p:Dout[7] -p:LED -p:PHI1 -p:RAout[0] -p:RAout[1] -p:RAout[2] -p:RAout[3] -p:RAout[4] -p:RAout[5] -p:RAout[6] -p:RAout[7] -p:RAout[8] -p:RAout[9] -p:RAout[10] -p:RAout[11] -p:RD[0] (bidir end point) -p:RD[0] (bidir start point) -p:RD[1] (bidir end point) -p:RD[1] (bidir start point) -p:RD[2] (bidir end point) -p:RD[2] (bidir start point) -p:RD[3] (bidir end point) -p:RD[3] (bidir start point) -p:RD[4] (bidir end point) -p:RD[4] (bidir start point) -p:RD[5] (bidir end point) -p:RD[5] (bidir start point) -p:RD[6] (bidir end point) -p:RD[6] (bidir start point) -p:RD[7] (bidir end point) -p:RD[7] (bidir start point) -p:Vout[0] -p:Vout[1] -p:Vout[2] -p:Vout[3] -p:Vout[4] -p:Vout[5] -p:Vout[6] -p:Vout[7] -p:nC07X -p:nCASout -p:nCSout -p:nDOE -p:nEN80 -p:nRASout -p:nRWEout -p:nVOE -p:nWE -p:nWE80 - - -Inapplicable constraints -************************ - -(none) - - -Applicable constraints with issues -********************************** - -(none) - - -Constraints with matching wildcard expressions -********************************************** - -(none) - - -Library Report -************** - - -# End of Constraint Checker Report diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_iotiming.html deleted file mode 100644 index 4f1de8c..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_iotiming.html +++ /dev/null @@ -1,184 +0,0 @@ - -I/O Timing Report - - -
    I/O Timing Report
-Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 5
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 6
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: M
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-// Design: RAM2E
-// Package: TQFP100
-// ncd File: ram2e_lcmxo2_640hc_impl1.ncd
-// Version: Diamond (64-bit) 3.12.1.454
-// Written on Thu Dec 28 23:23:47 2023
-// M: Minimum Performance Grade
-// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml
-
-I/O Timing Report (All units are in ns)
-
-Worst Case Results across Performance Grades (M, 6, 5, 4):
-
-// Input Setup and Hold Times
-
-Port   Clock Edge  Setup Performance_Grade  Hold Performance_Grade
-----------------------------------------------------------------------
-Ain[0] C14M  R     2.463      4      -0.066     M
-Ain[1] C14M  R     1.330      4       0.135     6
-Ain[2] C14M  R     1.221      4       0.223     4
-Ain[3] C14M  R     2.776      4      -0.165     M
-Ain[4] C14M  R     1.603      4       0.140     M
-Ain[5] C14M  R     0.021      6       1.287     4
-Ain[6] C14M  R     1.444      4       0.205     M
-Ain[7] C14M  R     1.816      4       0.114     M
-Din[0] C14M  R     8.919      4       0.723     4
-Din[1] C14M  R     8.410      4       1.156     4
-Din[2] C14M  R     8.503      4       1.181     4
-Din[3] C14M  R     8.783      4       0.110     M
-Din[4] C14M  R    10.420      4       1.022     4
-Din[5] C14M  R     8.001      4       0.566     4
-Din[6] C14M  R     9.731      4       1.050     4
-Din[7] C14M  R    10.052      4       0.862     4
-PHI1   C14M  R     2.579      4       3.047     4
-RD[0]  C14M  R     0.267      4       0.866     4
-RD[1]  C14M  R     0.173      4       0.937     4
-RD[2]  C14M  R     0.100      4       1.018     4
-RD[3]  C14M  R     0.267      4       0.866     4
-RD[4]  C14M  R     0.172      4       0.936     4
-RD[5]  C14M  R     0.267      4       0.866     4
-RD[6]  C14M  R     0.766      4       0.420     4
-RD[7]  C14M  R     0.267      4       0.866     4
-nC07X  C14M  R     0.998      4       0.405     6
-nEN80  C14M  R     6.107      4       0.114     M
-nWE    C14M  R     6.726      4       0.069     M
-
-
-// Clock to Output Delay
-
-Port      Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
-------------------------------------------------------------------------
-BA[0]     C14M  R     8.629         4        2.885          M
-BA[1]     C14M  R     8.629         4        2.885          M
-CKEout    C14M  F     8.629         4        2.885          M
-DQMH      C14M  R     8.609         4        2.892          M
-DQML      C14M  R     8.609         4        2.892          M
-LED       C14M  R    19.935         4        8.161          M
-RAout[0]  C14M  F     8.695         4        2.890          M
-RAout[10] C14M  F     8.629         4        2.885          M
-RAout[11] C14M  F     8.629         4        2.885          M
-RAout[1]  C14M  F     8.695         4        2.890          M
-RAout[2]  C14M  F     8.695         4        2.890          M
-RAout[3]  C14M  F     8.695         4        2.890          M
-RAout[4]  C14M  F     8.695         4        2.890          M
-RAout[5]  C14M  F     8.695         4        2.890          M
-RAout[6]  C14M  F     8.695         4        2.890          M
-RAout[7]  C14M  F     8.695         4        2.890          M
-RAout[8]  C14M  F     8.629         4        2.885          M
-RAout[9]  C14M  F     8.629         4        2.885          M
-RD[0]     C14M  R    11.414         4        3.265          M
-RD[1]     C14M  R    11.811         4        3.265          M
-RD[2]     C14M  R    11.925         4        3.265          M
-RD[3]     C14M  R    11.384         4        3.265          M
-RD[4]     C14M  R    12.301         4        3.371          M
-RD[5]     C14M  R    12.767         4        3.371          M
-RD[6]     C14M  R    12.010         4        3.371          M
-RD[7]     C14M  R    12.313         4        3.371          M
-Vout[0]   C14M  R     9.553         4        3.402          M
-Vout[1]   C14M  R     9.553         4        3.402          M
-Vout[2]   C14M  R     9.553         4        3.402          M
-Vout[3]   C14M  R     9.553         4        3.402          M
-Vout[4]   C14M  R     9.553         4        3.402          M
-Vout[5]   C14M  R     9.553         4        3.402          M
-Vout[6]   C14M  R     9.553         4        3.402          M
-Vout[7]   C14M  R     9.553         4        3.402          M
-nCASout   C14M  F     8.629         4        2.885          M
-nDOE      C14M  R    12.048         4        3.811          M
-nRASout   C14M  F     8.629         4        2.885          M
-nRWEout   C14M  F     8.629         4        2.885          M
-nVOE      C14M  R    12.164         4        3.783          M
-WARNING: you must also run trce with hold speed: 4
-WARNING: you must also run trce with setup speed: 6
-WARNING: you must also run trce with hold speed: 6
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    - - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf deleted file mode 100644 index 7753439..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf +++ /dev/null @@ -1,5500 +0,0 @@ -(DELAYFILE - (SDFVERSION "3.0") - (DESIGN "RAM2E") - (DATE "Thu Dec 28 23:23:31 2023") - (VENDOR "Lattice") - (PROGRAM "ldbanno") - (VERSION "Diamond (64-bit) 3.12.1.454") - (DIVIDER /) - (VOLTAGE 1.26:1.20:1.14) - (PROCESS "default") - (TEMPERATURE -40:25:85) - (TIMESCALE 1ps) - (CELL - (CELLTYPE "SLICE_0") - (INSTANCE SLICE_0) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 FCO (718:803:889)(718:803:889)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_1") - (INSTANCE SLICE_1) - (DELAY - (ABSOLUTE - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH FCI F0 (473:529:585)(473:529:585)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_2") - (INSTANCE SLICE_2) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 FCO (718:803:889)(718:803:889)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F1 (718:803:889)(718:803:889)) - (IOPATH A0 FCO (827:925:1023)(827:925:1023)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - (IOPATH FCI F0 (473:529:585)(473:529:585)) - (IOPATH FCI F1 (519:581:643)(519:581:643)) - (IOPATH FCI FCO (130:146:162)(130:146:162)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - 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(CELLTYPE "ram2e_ufm_SLICE_58") - (INSTANCE ram2e_ufm\/SLICE_58) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SUM0_i_m3_0_SLICE_59") - (INSTANCE ram2e_ufm\/SUM0_i_m3_0\/SLICE_59) - (DELAY - (ABSOLUTE - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH B1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60") - (INSTANCE ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH B1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_CKE_7_SLICE_61") - (INSTANCE ram2e_ufm\/CKE_7\/SLICE_61) - (DELAY - (ABSOLUTE - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH B1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_62") - (INSTANCE ram2e_ufm\/SLICE_62) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_63") - (INSTANCE ram2e_ufm\/SLICE_63) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_64") - (INSTANCE ram2e_ufm\/SLICE_64) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_65") - (INSTANCE ram2e_ufm\/SLICE_65) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_66") - (INSTANCE ram2e_ufm\/SLICE_66) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_67") - (INSTANCE ram2e_ufm\/SLICE_67) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_68") - (INSTANCE ram2e_ufm\/SLICE_68) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_69") - (INSTANCE ram2e_ufm\/SLICE_69) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_70") - (INSTANCE ram2e_ufm\/SLICE_70) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_71") - (INSTANCE ram2e_ufm\/SLICE_71) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_72") - (INSTANCE ram2e_ufm\/SLICE_72) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_73") - (INSTANCE ram2e_ufm\/SLICE_73) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_74") - (INSTANCE ram2e_ufm\/SLICE_74) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_75") - (INSTANCE ram2e_ufm\/SLICE_75) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_76") - (INSTANCE ram2e_ufm\/SLICE_76) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_77") - (INSTANCE ram2e_ufm\/SLICE_77) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_78") - (INSTANCE ram2e_ufm\/SLICE_78) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_79") - (INSTANCE ram2e_ufm\/SLICE_79) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_80") - (INSTANCE ram2e_ufm\/SLICE_80) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_81") - (INSTANCE ram2e_ufm\/SLICE_81) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_82") - (INSTANCE ram2e_ufm\/SLICE_82) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_83") - (INSTANCE ram2e_ufm\/SLICE_83) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_84") - (INSTANCE ram2e_ufm\/SLICE_84) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_85") - (INSTANCE ram2e_ufm\/SLICE_85) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_86") - (INSTANCE ram2e_ufm\/SLICE_86) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_87") - (INSTANCE ram2e_ufm\/SLICE_87) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_88") - (INSTANCE ram2e_ufm\/SLICE_88) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_89") - (INSTANCE ram2e_ufm\/SLICE_89) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_90") - (INSTANCE ram2e_ufm\/SLICE_90) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_91") - (INSTANCE ram2e_ufm\/SLICE_91) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_92") - (INSTANCE ram2e_ufm\/SLICE_92) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_93") - (INSTANCE ram2e_ufm\/SLICE_93) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_94") - (INSTANCE ram2e_ufm\/SLICE_94) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_95") - (INSTANCE ram2e_ufm\/SLICE_95) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_96") - (INSTANCE ram2e_ufm\/SLICE_96) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_97") - (INSTANCE ram2e_ufm\/SLICE_97) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_98") - (INSTANCE ram2e_ufm\/SLICE_98) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_99") - (INSTANCE ram2e_ufm\/SLICE_99) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_100") - (INSTANCE ram2e_ufm\/SLICE_100) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_101") - (INSTANCE ram2e_ufm\/SLICE_101) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_102") - (INSTANCE ram2e_ufm\/SLICE_102) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_103") - (INSTANCE ram2e_ufm\/SLICE_103) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_104") - (INSTANCE ram2e_ufm\/SLICE_104) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_105") - (INSTANCE ram2e_ufm\/SLICE_105) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_106") - (INSTANCE ram2e_ufm\/SLICE_106) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_107") - (INSTANCE ram2e_ufm\/SLICE_107) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_108") - (INSTANCE ram2e_ufm\/SLICE_108) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_109") - (INSTANCE ram2e_ufm\/SLICE_109) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_110") - (INSTANCE ram2e_ufm\/SLICE_110) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_111") - (INSTANCE ram2e_ufm\/SLICE_111) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_112") - (INSTANCE ram2e_ufm\/SLICE_112) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_113") - (INSTANCE ram2e_ufm\/SLICE_113) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_114") - (INSTANCE ram2e_ufm\/SLICE_114) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_115") - (INSTANCE ram2e_ufm\/SLICE_115) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_116") - (INSTANCE ram2e_ufm\/SLICE_116) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_117") - (INSTANCE ram2e_ufm\/SLICE_117) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_118") - (INSTANCE ram2e_ufm\/SLICE_118) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_119") - (INSTANCE ram2e_ufm\/SLICE_119) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_120") - (INSTANCE ram2e_ufm\/SLICE_120) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_121") - (INSTANCE ram2e_ufm\/SLICE_121) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_122") - (INSTANCE ram2e_ufm\/SLICE_122) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_123") - (INSTANCE ram2e_ufm\/SLICE_123) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_124") - (INSTANCE ram2e_ufm\/SLICE_124) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_125") - (INSTANCE ram2e_ufm\/SLICE_125) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_126") - (INSTANCE ram2e_ufm\/SLICE_126) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_127") - (INSTANCE ram2e_ufm\/SLICE_127) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_128") - (INSTANCE ram2e_ufm\/SLICE_128) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - 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(INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQMH_MGIOL/CE (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQML_MGIOL/CE (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_120/F0 DQML_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_120/F1 DQMH_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[7\]_MGIOL/CE (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[6\]_MGIOL/CE (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[5\]_MGIOL/CE (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[4\]_MGIOL/CE (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[3\]_MGIOL/CE (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[2\]_MGIOL/CE (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[1\]_MGIOL/CE (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[0\]_MGIOL/CE (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_129/F1 BA\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT Ain\[0\]_I/PADDI ram2e_ufm\/SLICE_132/A1 (0:0:0)(0:0:0)) - (INTERCONNECT Ain\[7\]_I/PADDI ram2e_ufm\/SLICE_132/A0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_136/F0 nDOE_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F0 LED_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) - (INTERCONNECT PHI1_I/PADDI SLICE_139/A1 (0:0:0)(0:0:0)) - (INTERCONNECT PHI1_I/PADDI SLICE_139/A0 (0:0:0)(0:0:0)) - (INTERCONNECT PHI1_I/PADDI PHI1_MGIOL/DI (0:0:0)(0:0:0)) - (INTERCONNECT PHI1_MGIOL/IN SLICE_139/B0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_139/F1 nVOE_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_141/F0 RD\[3\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_141/F1 RD\[0\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_142/F0 RD\[4\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_143/F0 RD\[7\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_143/F1 RD\[1\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_144/F0 RD\[6\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_144/F1 RD\[2\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F0 RD\[5\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[0\]_I/PADDI Vout\[0\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) - (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (0:0:0)(0:0:0)) - (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[11\]_MGIOL/IOLDO RAout\[11\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[10\]_MGIOL/IOLDO RAout\[10\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[9\]_MGIOL/IOLDO RAout\[9\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[8\]_MGIOL/IOLDO RAout\[8\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[7\]_MGIOL/IOLDO RAout\[7\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[6\]_MGIOL/IOLDO RAout\[6\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[5\]_MGIOL/IOLDO RAout\[5\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[4\]_MGIOL/IOLDO RAout\[4\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[3\]_MGIOL/IOLDO RAout\[3\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[2\]_MGIOL/IOLDO RAout\[2\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[1\]_MGIOL/IOLDO RAout\[1\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT RAout\[0\]_MGIOL/IOLDO RAout\[0\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT nRWEout_MGIOL/IOLDO nRWEout_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT nCASout_MGIOL/IOLDO nCASout_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT nRASout_MGIOL/IOLDO nRASout_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT CKEout_MGIOL/IOLDO CKEout_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[4\]_MGIOL/IOLDO Vout\[4\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[3\]_MGIOL/IOLDO Vout\[3\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (0:0:0)(0:0:0)) - (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (0:0:0)(0:0:0)) - ) - ) - ) -) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo deleted file mode 100644 index e3950a9..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo +++ /dev/null @@ -1,7135 +0,0 @@ - -// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 - -// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd -// Netlist created on Thu Dec 28 23:23:28 2023 -// Netlist written on Thu Dec 28 23:23:31 2023 -// Design is for device LCMXO2-640HC -// Design is for package TQFP100 -// Design is for performance grade 4 - -`timescale 1 ns / 1 ps - -module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, - Vout, nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout, BA, - RAout, DQML, DQMH, RD ); - input C14M, PHI1, nWE, nWE80, nEN80, nC07X; - input [7:0] Ain; - input [7:0] Din; - output LED; - output [7:0] Dout; - output nDOE; - output [7:0] Vout; - output nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout; - output [1:0] BA; - output [11:0] RAout; - output DQML, DQMH; - inout [7:0] RD; - wire \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , - \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , - \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , - \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , - \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , - \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , - \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , N_551, - \S[1] , \S[0] , \ram2e_ufm/CKE_7 , CKE_7_RNIS77M1, CKE, - \ram2e_ufm/wb_adr_0_sqmuxa_1_i , RWSel, CO0_0, \CmdTout_3[0] , - N_185_i, GND, \RC[2] , CO0_1, \RC[1] , N_360_i, RC12, - \ram2e_ufm/N_821 , \ram2e_ufm/SUM1_0_0 , \ram2e_ufm/SUM0_i_a3_4_0 , - \ram2e_ufm/N_886 , \ram2e_ufm/N_215 , \ram2e_ufm/SUM0_i_4 , \CS[2] , - \CS[1] , CmdExecMXO2_3_0_a3_0_RNI6S1P8, N_547_i, un1_CS_0_sqmuxa_i, - \CS[0] , \ram2e_ufm/N_234 , CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514, - \ram2e_ufm/N_800 , \Din_c[5] , \Din_c[3] , - \ram2e_ufm/CmdLEDGet_3_0_a3_1 , \ram2e_ufm/N_847 , \Din_c[2] , - \Din_c[1] , CmdLEDGet_3, N_187_i, CmdLEDGet, \Din_c[7] , \Din_c[4] , - \ram2e_ufm/N_883 , CmdLEDSet_3, CmdLEDSet, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 , CmdRWMaskSet_3, CmdRWMaskSet, - \ram2e_ufm/N_850 , \Din_c[0] , CmdSetRWBankFFLED_4, CmdSetRWBankFFLED, - \CmdTout[2] , \CmdTout[1] , N_369_i, N_368_i, \RA[1] , - \ram2e_ufm/N_186 , \S[3] , N_1080_0, \ram2e_ufm/N_660 , DOEEN, - \ram2e_ufm/N_193 , \ram2e_ufm/N_659 , \ram2e_ufm/N_182 , \Ain_c[1] , - \ram2e_ufm/RA_35_0_0_1[0] , \ram2e_ufm/N_801 , \ram2e_ufm/N_684 , - N_223, \RA_35[0] , N_126, \RA[0] , \ram2e_ufm/RA_35_0_0_0[3] , - \ram2e_ufm/N_680 , \ram2e_ufm/N_679 , \Ain_c[2] , \RA_35[3] , - \RA_35[2] , \RA[2] , \RA[3] , \ram2e_ufm/RA_35_0_0_0[5] , - \ram2e_ufm/N_621 , \Ain_c[5] , \ram2e_ufm/RA_35_0_0_0[4] , \RA_35[5] , - \RA_35[4] , \RA[4] , \RA[5] , \ram2e_ufm/RA_35_0_0_0_0[7] , - \ram2e_ufm/RA_35_0_0_0_0[6] , \RA_35[7] , \RA_35[6] , \RA[6] , - \RA[7] , \ram2e_ufm/RA_35_0_0_0[9] , \RA[9] , \ram2e_ufm/N_242 , - \RA[8] , \ram2e_ufm/N_699 , \ram2e_ufm/N_698 , \ram2e_ufm/N_221 , - \RA_35[9] , un2_S_2_i_0_0_o3_RNIHFHN3, \RWBank[4] , \RA[11] , - \ram2e_ufm/N_845 , \ram2e_ufm/RA_35_2_0_0[10] , \ram2e_ufm/N_628 , - \ram2e_ufm/N_627 , \ram2e_ufm/N_624 , \RA_35[11] , \RA_35[10] , - \RA[10] , \RC_3[2] , \RC_3[1] , \ram2e_ufm/RWMask[1] , - \ram2e_ufm/N_188 , \ram2e_ufm/RWMask[0] , \RWBank_3[1] , - \RWBank_3[0] , \RWBank[0] , \RWBank[1] , \ram2e_ufm/RWMask[3] , - \ram2e_ufm/RWMask[2] , \RWBank_3[3] , \RWBank_3[2] , \RWBank[2] , - \RWBank[3] , \ram2e_ufm/RWMask[5] , \ram2e_ufm/RWMask[4] , - \RWBank_3[5] , \RWBank_3[4] , \RWBank[5] , \ram2e_ufm/RWMask[7] , - \ram2e_ufm/RWMask[6] , \Din_c[6] , \RWBank_3[7] , \RWBank_3[6] , - \RWBank[6] , \RWBank[7] , \Ain_c[3] , nWE_c, nC07X_c, RWSel_2, - un9_VOEEN_0_a2_0_a3_0_a3, \ram2e_ufm/Ready3_0_a3_5 , - \ram2e_ufm/Ready3_0_a3_4 , \ram2e_ufm/Ready3_0_a3_3 , - \ram2e_ufm/N_885 , Ready, Ready3, N_1026_0, \ram2e_ufm/S_r_i_0_o2[1] , - \ram2e_ufm/N_271 , \ram2e_ufm/N_194 , S_1, \ram2e_ufm/N_643 , N_362_i, - \S_s_0_0[0] , \S[2] , N_372_i, N_361_i, N_1078_0, VOEEN, BA_0_sqmuxa, - \ram2e_ufm/N_285_i , \ram2e_ufm/N_804 , \ram2e_ufm/N_872 , - \ram2e_ufm/N_641 , \ram2e_ufm/N_640 , N_370_i, nCAS, - \ram2e_ufm/nRAS_s_i_0_0 , \ram2e_ufm/N_617 , \ram2e_ufm/N_616 , - \ram2e_ufm/N_615 , N_358_i, nRAS, \ram2e_ufm/N_226 , - \ram2e_ufm/N_866 , \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] , N_359_i, nRWE, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 , - \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 , \ram2e_ufm/CmdBitbangMXO2_3 , - \ram2e_ufm/CmdBitbangMXO2 , \ram2e_ufm/N_851 , - \ram2e_ufm/CmdExecMXO2_3 , \ram2e_ufm/CmdExecMXO2 , - \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 , \ram2e_ufm/N_190 , - \ram2e_ufm/CmdSetRWBankFFChip_3 , \ram2e_ufm/CmdSetRWBankFFChip , - \ram2e_ufm/wb_dato[0] , \ram2e_ufm/N_295 , - \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] , \ram2e_ufm/LEDEN , - \ram2e_ufm/N_212 , \ram2e_ufm/wb_dato[1] , \ram2e_ufm/N_307_i , - \ram2e_ufm/N_309_i , \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] , - \ram2e_ufm/wb_dato[3] , \ram2e_ufm/wb_dato[2] , \ram2e_ufm/N_302_i , - \ram2e_ufm/N_304_i , \ram2e_ufm/wb_dato[5] , \ram2e_ufm/wb_dato[4] , - \ram2e_ufm/N_301_i , \ram2e_ufm/N_310_i , \ram2e_ufm/wb_dato[7] , - \ram2e_ufm/wb_dato[6] , \ram2e_ufm/N_296 , \ram2e_ufm/N_300_i , - \ram2e_ufm/wb_adr_7_5_41_0_1 , \ram2e_ufm/N_768 , - \ram2e_ufm/wb_adr_7_i_i_5[0] , \ram2e_ufm/wb_adr_7_i_i_4[0] , - \ram2e_ufm/N_793 , \ram2e_ufm/wb_adr_RNO[1] , - \ram2e_ufm/wb_adr_7_i_i[0] , \ram2e_ufm/CmdBitbangMXO2_RNINSM62 , - \ram2e_ufm/wb_adr[0] , \ram2e_ufm/wb_adr[1] , \ram2e_ufm/N_268_i , - \ram2e_ufm/N_80_i , \ram2e_ufm/wb_adr[2] , \ram2e_ufm/wb_adr[3] , - \ram2e_ufm/N_290 , \ram2e_ufm/N_294 , \ram2e_ufm/wb_adr[4] , - \ram2e_ufm/wb_adr[5] , \ram2e_ufm/N_267_i , \ram2e_ufm/N_284 , - \ram2e_ufm/wb_adr[6] , \ram2e_ufm/wb_adr[7] , \ram2e_ufm/wb_ack , - \ram2e_ufm/N_336 , \ram2e_ufm/N_687 , \ram2e_ufm/wb_cyc_stb_RNO , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] , - \ram2e_ufm/wb_cyc_stb , \ram2e_ufm/wb_dati_7_0_0_0[1] , - \ram2e_ufm/N_849 , \ram2e_ufm/N_611 , - \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] , \ram2e_ufm/N_856 , - \ram2e_ufm/wb_dati_7[1] , \ram2e_ufm/wb_dati_7[0] , - \ram2e_ufm/wb_dati[0] , \ram2e_ufm/wb_dati[1] , - \ram2e_ufm/wb_dati_7_0_0_0_0[3] , \ram2e_ufm/N_783 , - \ram2e_ufm/wb_dati_7_0_0_o3_0[2] , \ram2e_ufm/N_760 , - \ram2e_ufm/wb_dati_7[3] , \ram2e_ufm/wb_dati_7[2] , - \ram2e_ufm/wb_dati[2] , \ram2e_ufm/wb_dati[3] , - \ram2e_ufm/wb_dati_7_0_0_0[4] , \ram2e_ufm/N_763 , \ram2e_ufm/N_757 , - \ram2e_ufm/wb_dati_7[5] , \ram2e_ufm/wb_dati_7[4] , - \ram2e_ufm/wb_dati[4] , \ram2e_ufm/wb_dati[5] , - \ram2e_ufm/wb_dati_7_0_0_0_0[7] , \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] , - \ram2e_ufm/N_604 , \ram2e_ufm/N_602 , \ram2e_ufm/wb_dati_7_0_0_0[6] , - \ram2e_ufm/wb_dati_7[7] , \ram2e_ufm/wb_dati_7[6] , - \ram2e_ufm/wb_dati[6] , \ram2e_ufm/wb_dati[7] , \ram2e_ufm/wb_reqc_1 , - \ram2e_ufm/wb_reqc_i , \ram2e_ufm/wb_req , \ram2e_ufm/wb_rst8 , - \ram2e_ufm/wb_rst16_i , \ram2e_ufm/wb_rst , - \ram2e_ufm/wb_we_7_iv_0_0_3_0_0 , \ram2e_ufm/N_799 , - \ram2e_ufm/wb_we_7_iv_0_0_3_0_1 , \ram2e_ufm/N_208 , - \ram2e_ufm/wb_we_RNO , \ram2e_ufm/wb_we_RNO_0 , \ram2e_ufm/wb_we , - \ram2e_ufm/N_338 , \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 , \ram2e_ufm/N_817 , - \ram2e_ufm/CKE_7_sm0 , \ram2e_ufm/N_720_tz , \ram2e_ufm/SUM0_i_0 , - \ram2e_ufm/N_350 , \ram2e_ufm/SUM0_i_3 , \ram2e_ufm/SUM0_i_1 , - \ram2e_ufm/N_187 , \ram2e_ufm/N_755 , \ram2e_ufm/N_735 , - \ram2e_ufm/N_345 , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] , - \ram2e_ufm/N_777 , \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] , - \ram2e_ufm/N_250 , \ram2e_ufm/N_256 , \ram2e_ufm/wb_adr_7_i_i_3_1[0] , - \ram2e_ufm/wb_adr_7_i_i_3[0] , \ram2e_ufm/N_254 , \ram2e_ufm/N_807 , - \ram2e_ufm/N_876 , \ram2e_ufm/N_784 , \ram2e_ufm/N_560 , \BA_4[0] , - \ram2e_ufm/N_873 , \ram2e_ufm/N_781 , \ram2e_ufm/N_184 , - \ram2e_ufm/N_625 , \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] , - \ram2e_ufm/N_811 , \ram2e_ufm/N_206 , - \ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] , \ram2e_ufm/N_185 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S , \ram2e_ufm/N_637 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 , \ram2e_ufm/N_592 , - \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] , - \ram2e_ufm/wb_adr_7_i_i_1[0] , \ram2e_ufm/N_753 , \ram2e_ufm/N_634 , - \ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] , - \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] , - \ram2e_ufm/wb_dati_7_0_0_a3_1[6] , \ram2e_ufm/N_890 , - \ram2e_ufm/N_220 , \ram2e_ufm/N_196 , \ram2e_ufm/N_243 , \Ain_c[4] , - \Ain_c[6] , \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] , - \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] , \ram2e_ufm/N_565 , - \ram2e_ufm/CKE_7s2_0_0_0 , \ram2e_ufm/wb_adr_7_5_41_a3_3_0 , - \ram2e_ufm/N_204 , \ram2e_ufm/N_595 , \ram2e_ufm/nRWE_s_i_0_63_1 , - \ram2e_ufm/N_792 , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] , - \ram2e_ufm/N_553 , nEN80_c, \ram2e_ufm/N_241_i , \ram2e_ufm/N_814 , - N_225_i, N_201_i, N_507_i, N_508, Vout3, \BA_4[1] , \Ain_c[0] , - \Ain_c[7] , nDOE_c, LED_c, RDOE_i, PHI1_c, PHI1r, nVOE_c, N_263_i, - N_667, N_648, N_662, N_666, N_663, N_665, N_664, \RD_in[0] , - \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , - \RD_in[2] , \RD_in[1] , DQMH_c, DQML_c, \RAout_c[11] , \RAout_c[10] , - \RAout_c[9] , \RAout_c[8] , \RAout_c[7] , \RAout_c[6] , \RAout_c[5] , - \RAout_c[4] , \RAout_c[3] , \RAout_c[2] , \RAout_c[1] , \RAout_c[0] , - \BA_c[1] , \BA_c[0] , nRWEout_c, nCASout_c, nRASout_c, CKEout_c, - \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] , - \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , VCCI; - - SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), - .Q1(\FS[0] ), .FCO(\FS_cry[0] )); - SLICE_1 SLICE_1( .A0(\FS[15] ), .DI0(\FS_s[15] ), .CLK(C14M_c), - .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), .Q0(\FS[15] )); - SLICE_2 SLICE_2( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), - .DI0(\FS_s[13] ), .CLK(C14M_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), - .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] )); - SLICE_3 SLICE_3( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), - .DI0(\FS_s[11] ), .CLK(C14M_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), - .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] )); - SLICE_4 SLICE_4( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), - .DI0(\FS_s[9] ), .CLK(C14M_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), - .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] )); - SLICE_5 SLICE_5( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), - .DI0(\FS_s[7] ), .CLK(C14M_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), - .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] )); - SLICE_6 SLICE_6( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), - .DI0(\FS_s[5] ), .CLK(C14M_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), - .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] )); - SLICE_7 SLICE_7( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), - .DI0(\FS_s[3] ), .CLK(C14M_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), - .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] )); - SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), - .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), - .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); - SLICE_9 SLICE_9( .D1(N_551), .C1(\S[1] ), .B1(\S[0] ), .A1(\FS[15] ), - .D0(N_551), .C0(\S[1] ), .B0(\S[0] ), .A0(\ram2e_ufm/CKE_7 ), - .DI0(CKE_7_RNIS77M1), .CLK(C14M_c), .F0(CKE_7_RNIS77M1), .Q0(CKE), - .F1(\ram2e_ufm/wb_adr_0_sqmuxa_1_i )); - SLICE_10 SLICE_10( .B0(RWSel), .A0(CO0_0), .DI0(\CmdTout_3[0] ), - .CE(N_185_i), .CLK(C14M_c), .F0(\CmdTout_3[0] ), .Q0(CO0_0), .F1(GND)); - SLICE_11 SLICE_11( .B1(\RC[2] ), .A1(CO0_1), .C0(\RC[2] ), .B0(\RC[1] ), - .A0(CO0_1), .DI0(N_360_i), .CE(RC12), .CLK(C14M_c), .F0(N_360_i), - .Q0(CO0_1), .F1(\ram2e_ufm/N_821 )); - SLICE_12 SLICE_12( .D1(\ram2e_ufm/SUM1_0_0 ), .C1(\ram2e_ufm/SUM0_i_a3_4_0 ), - .B1(\ram2e_ufm/N_886 ), .A1(\ram2e_ufm/N_215 ), .D0(\ram2e_ufm/SUM0_i_4 ), - .C0(\ram2e_ufm/N_215 ), .B0(\CS[2] ), .A0(\CS[1] ), - .DI1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .DI0(N_547_i), - .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_547_i), .Q0(\CS[0] ), - .F1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .Q1(\CS[1] )); - SLICE_13 SLICE_13( .D1(\ram2e_ufm/N_234 ), .C1(\ram2e_ufm/N_215 ), - .B1(\CS[2] ), .A1(\CS[1] ), .D0(\ram2e_ufm/N_234 ), .C0(\ram2e_ufm/N_215 ), - .B0(\CS[2] ), .A0(\CS[1] ), .DI0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), - .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), - .F0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), .Q0(\CS[2] ), - .F1(\ram2e_ufm/SUM1_0_0 )); - SLICE_14 SLICE_14( .C1(\ram2e_ufm/N_800 ), .B1(\Din_c[5] ), .A1(\Din_c[3] ), - .D0(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ), .C0(\ram2e_ufm/N_847 ), - .B0(\Din_c[2] ), .A0(\Din_c[1] ), .DI0(CmdLEDGet_3), .CE(N_187_i), - .CLK(C14M_c), .F0(CmdLEDGet_3), .Q0(CmdLEDGet), .F1(\ram2e_ufm/N_847 )); - SLICE_15 SLICE_15( .C1(\Din_c[7] ), .B1(\Din_c[1] ), .A1(\CS[2] ), - .D0(\Din_c[4] ), .C0(\Din_c[7] ), .B0(\Din_c[1] ), .A0(\ram2e_ufm/N_883 ), - .DI0(CmdLEDSet_3), .CE(N_187_i), .CLK(C14M_c), .F0(CmdLEDSet_3), - .Q0(CmdLEDSet), .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 )); - SLICE_16 SLICE_16( .D1(\Din_c[7] ), .C1(\Din_c[5] ), .B1(\Din_c[3] ), - .A1(\Din_c[1] ), .D0(\Din_c[4] ), .C0(\Din_c[7] ), .B0(\Din_c[1] ), - .A0(\ram2e_ufm/N_883 ), .DI0(CmdRWMaskSet_3), .CE(N_187_i), .CLK(C14M_c), - .F0(CmdRWMaskSet_3), .Q0(CmdRWMaskSet), .F1(\ram2e_ufm/N_850 )); - SLICE_17 SLICE_17( .C1(\ram2e_ufm/N_847 ), .B1(\Din_c[2] ), .A1(\Din_c[0] ), - .D0(\ram2e_ufm/N_883 ), .C0(\Din_c[7] ), .B0(\Din_c[4] ), .A0(\Din_c[1] ), - .DI0(CmdSetRWBankFFLED_4), .CE(N_187_i), .CLK(C14M_c), - .F0(CmdSetRWBankFFLED_4), .Q0(CmdSetRWBankFFLED), .F1(\ram2e_ufm/N_883 )); - SLICE_18 SLICE_18( .D1(RWSel), .C1(\CmdTout[2] ), .B1(\CmdTout[1] ), - .A1(CO0_0), .C0(RWSel), .B0(\CmdTout[1] ), .A0(CO0_0), .DI1(N_369_i), - .DI0(N_368_i), .CE(N_185_i), .CLK(C14M_c), .F0(N_368_i), .Q0(\CmdTout[1] ), - .F1(N_369_i), .Q1(\CmdTout[2] )); - SLICE_19 SLICE_19( .B1(\CS[2] ), .A1(\CS[1] ), .B0(\RA[1] ), - .A0(\ram2e_ufm/N_186 ), .M0(\S[3] ), .LSR(N_1080_0), .CLK(C14M_c), - .F0(\ram2e_ufm/N_660 ), .Q0(DOEEN), .F1(\ram2e_ufm/N_193 )); - SLICE_20 SLICE_20( .D1(\ram2e_ufm/N_660 ), .C1(\ram2e_ufm/N_659 ), - .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[1] ), .D0(\ram2e_ufm/RA_35_0_0_1[0] ), - .C0(\ram2e_ufm/N_801 ), .B0(\ram2e_ufm/N_684 ), .A0(\FS[7] ), .DI1(N_223), - .DI0(\RA_35[0] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[0] ), .Q0(\RA[0] ), - .F1(N_223), .Q1(\RA[1] )); - SLICE_21 SLICE_21( .C1(\ram2e_ufm/RA_35_0_0_0[3] ), .B1(\ram2e_ufm/N_801 ), - .A1(\FS[10] ), .D0(\ram2e_ufm/N_680 ), .C0(\ram2e_ufm/N_679 ), - .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[2] ), .DI1(\RA_35[3] ), - .DI0(\RA_35[2] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[2] ), .Q0(\RA[2] ), - .F1(\RA_35[3] ), .Q1(\RA[3] )); - SLICE_22 SLICE_22( .D1(\ram2e_ufm/RA_35_0_0_0[5] ), .C1(\ram2e_ufm/N_621 ), - .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[5] ), .C0(\ram2e_ufm/RA_35_0_0_0[4] ), - .B0(\ram2e_ufm/N_801 ), .A0(\FS[11] ), .DI1(\RA_35[5] ), .DI0(\RA_35[4] ), - .CE(N_126), .CLK(C14M_c), .F0(\RA_35[4] ), .Q0(\RA[4] ), .F1(\RA_35[5] ), - .Q1(\RA[5] )); - SLICE_23 SLICE_23( .C1(\ram2e_ufm/RA_35_0_0_0_0[7] ), .B1(\ram2e_ufm/N_801 ), - .A1(\FS[14] ), .C0(\ram2e_ufm/RA_35_0_0_0_0[6] ), .B0(\ram2e_ufm/N_801 ), - .A0(\FS[13] ), .DI1(\RA_35[7] ), .DI0(\RA_35[6] ), .CE(N_126), - .CLK(C14M_c), .F0(\RA_35[6] ), .Q0(\RA[6] ), .F1(\RA_35[7] ), .Q1(\RA[7] )); - SLICE_24 SLICE_24( .C1(\ram2e_ufm/RA_35_0_0_0[9] ), .B1(\RA[9] ), - .A1(\ram2e_ufm/N_242 ), .D0(\RA[8] ), .C0(\ram2e_ufm/N_699 ), - .B0(\ram2e_ufm/N_698 ), .A0(\ram2e_ufm/N_221 ), .DI1(\RA_35[9] ), - .DI0(un2_S_2_i_0_0_o3_RNIHFHN3), .CE(N_126), .CLK(C14M_c), - .F0(un2_S_2_i_0_0_o3_RNIHFHN3), .Q0(\RA[8] ), .F1(\RA_35[9] ), - .Q1(\RA[9] )); - SLICE_25 SLICE_25( .D1(\RWBank[4] ), .C1(\RA[11] ), .B1(\ram2e_ufm/N_845 ), - .A1(\ram2e_ufm/N_242 ), .D0(\ram2e_ufm/RA_35_2_0_0[10] ), - .C0(\ram2e_ufm/N_628 ), .B0(\ram2e_ufm/N_627 ), .A0(\ram2e_ufm/N_624 ), - .DI1(\RA_35[11] ), .DI0(\RA_35[10] ), .CE(N_126), .CLK(C14M_c), - .F0(\RA_35[10] ), .Q0(\RA[10] ), .F1(\RA_35[11] ), .Q1(\RA[11] )); - SLICE_26 SLICE_26( .C1(\RC[2] ), .B1(\RC[1] ), .A1(CO0_1), .C0(\RC[2] ), - .B0(CO0_1), .A0(\RC[1] ), .DI1(\RC_3[2] ), .DI0(\RC_3[1] ), .CE(RC12), - .CLK(C14M_c), .F0(\RC_3[1] ), .Q0(\RC[1] ), .F1(\RC_3[2] ), .Q1(\RC[2] )); - SLICE_27 SLICE_27( .C1(\ram2e_ufm/RWMask[1] ), .B1(\ram2e_ufm/N_188 ), - .A1(\Din_c[1] ), .C0(\ram2e_ufm/RWMask[0] ), .B0(\ram2e_ufm/N_188 ), - .A0(\Din_c[0] ), .DI1(\RWBank_3[1] ), .DI0(\RWBank_3[0] ), .CE(N_187_i), - .CLK(C14M_c), .F0(\RWBank_3[0] ), .Q0(\RWBank[0] ), .F1(\RWBank_3[1] ), - .Q1(\RWBank[1] )); - SLICE_28 SLICE_28( .C1(\ram2e_ufm/RWMask[3] ), .B1(\ram2e_ufm/N_188 ), - .A1(\Din_c[3] ), .C0(\ram2e_ufm/RWMask[2] ), .B0(\ram2e_ufm/N_188 ), - .A0(\Din_c[2] ), .DI1(\RWBank_3[3] ), .DI0(\RWBank_3[2] ), .CE(N_187_i), - .CLK(C14M_c), .F0(\RWBank_3[2] ), .Q0(\RWBank[2] ), .F1(\RWBank_3[3] ), - .Q1(\RWBank[3] )); - SLICE_29 SLICE_29( .C1(\ram2e_ufm/RWMask[5] ), .B1(\ram2e_ufm/N_188 ), - .A1(\Din_c[5] ), .C0(\ram2e_ufm/RWMask[4] ), .B0(\ram2e_ufm/N_188 ), - .A0(\Din_c[4] ), .DI1(\RWBank_3[5] ), .DI0(\RWBank_3[4] ), .CE(N_187_i), - .CLK(C14M_c), .F0(\RWBank_3[4] ), .Q0(\RWBank[4] ), .F1(\RWBank_3[5] ), - .Q1(\RWBank[5] )); - SLICE_30 SLICE_30( .C1(\ram2e_ufm/RWMask[7] ), .B1(\ram2e_ufm/N_188 ), - .A1(\Din_c[7] ), .C0(\ram2e_ufm/RWMask[6] ), .B0(\ram2e_ufm/N_188 ), - .A0(\Din_c[6] ), .DI1(\RWBank_3[7] ), .DI0(\RWBank_3[6] ), .CE(N_187_i), - .CLK(C14M_c), .F0(\RWBank_3[6] ), .Q0(\RWBank[6] ), .F1(\RWBank_3[7] ), - .Q1(\RWBank[7] )); - SLICE_31 SLICE_31( .D1(\RA[3] ), .C1(\ram2e_ufm/N_186 ), - .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[3] ), .D0(nWE_c), .C0(nC07X_c), - .B0(\RA[3] ), .A0(\RA[0] ), .DI0(RWSel_2), .CE(un9_VOEEN_0_a2_0_a3_0_a3), - .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(\ram2e_ufm/RA_35_0_0_0[3] )); - SLICE_32 SLICE_32( .D1(\ram2e_ufm/Ready3_0_a3_5 ), - .C1(\ram2e_ufm/Ready3_0_a3_4 ), .B1(\ram2e_ufm/Ready3_0_a3_3 ), - .A1(\ram2e_ufm/N_885 ), .B0(Ready), .A0(Ready3), .DI0(N_1026_0), - .CLK(C14M_c), .F0(N_1026_0), .Q0(Ready), .F1(Ready3)); - SLICE_33 SLICE_33( .D1(\ram2e_ufm/S_r_i_0_o2[1] ), .C1(\ram2e_ufm/N_271 ), - .B1(\ram2e_ufm/N_194 ), .A1(S_1), .D0(\S[1] ), .C0(\ram2e_ufm/N_643 ), - .B0(\ram2e_ufm/N_271 ), .A0(S_1), .DI1(N_362_i), .DI0(\S_s_0_0[0] ), - .CLK(C14M_c), .F0(\S_s_0_0[0] ), .Q0(\S[0] ), .F1(N_362_i), .Q1(\S[1] )); - SLICE_34 SLICE_34( .D1(\S[2] ), .C1(S_1), .B1(\ram2e_ufm/N_194 ), - .A1(\S[3] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\ram2e_ufm/N_194 ), .A0(S_1), - .DI1(N_372_i), .DI0(N_361_i), .CLK(C14M_c), .F0(N_361_i), .Q0(\S[2] ), - .F1(N_372_i), .Q1(\S[3] )); - SLICE_35 SLICE_35( .D1(N_551), .C1(\S[1] ), .B1(\S[0] ), .A1(\FS[4] ), - .B0(\S[3] ), .A0(\S[2] ), .DI0(N_551), .LSR(N_1078_0), .CLK(C14M_c), - .F0(N_551), .Q0(VOEEN), .F1(BA_0_sqmuxa)); - SLICE_36 SLICE_36( .D1(\ram2e_ufm/N_285_i ), .C1(\S[0] ), .B1(\S[1] ), - .A1(\ram2e_ufm/N_804 ), .D0(nWE_c), .C0(\ram2e_ufm/N_872 ), - .B0(\ram2e_ufm/N_641 ), .A0(\ram2e_ufm/N_640 ), .DI0(N_370_i), - .CLK(C14M_c), .F0(N_370_i), .Q0(nCAS), .F1(\ram2e_ufm/N_872 )); - SLICE_37 SLICE_37( .D1(\S[0] ), .C1(\S[1] ), .B1(\ram2e_ufm/N_285_i ), - .A1(\ram2e_ufm/N_804 ), .D0(\ram2e_ufm/nRAS_s_i_0_0 ), - .C0(\ram2e_ufm/N_617 ), .B0(\ram2e_ufm/N_616 ), .A0(\ram2e_ufm/N_615 ), - .DI0(N_358_i), .CLK(C14M_c), .F0(N_358_i), .Q0(nRAS), - .F1(\ram2e_ufm/N_617 )); - SLICE_38 SLICE_38( .D1(\S[2] ), .C1(\ram2e_ufm/S_r_i_0_o2[1] ), - .B1(\ram2e_ufm/N_226 ), .A1(\ram2e_ufm/N_285_i ), .D0(\ram2e_ufm/N_804 ), - .C0(\ram2e_ufm/N_866 ), .B0(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ), - .A0(\ram2e_ufm/N_615 ), .DI0(N_359_i), .CLK(C14M_c), .F0(N_359_i), - .Q0(nRWE), .F1(\ram2e_ufm/N_615 )); - ram2e_ufm_SLICE_39 \ram2e_ufm/SLICE_39 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ), - .B1(\Din_c[0] ), .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), - .D0(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ), .C0(\ram2e_ufm/N_800 ), - .B0(\Din_c[2] ), .A0(\Din_c[1] ), .DI0(\ram2e_ufm/CmdBitbangMXO2_3 ), - .CE(N_187_i), .CLK(C14M_c), .F0(\ram2e_ufm/CmdBitbangMXO2_3 ), - .Q0(\ram2e_ufm/CmdBitbangMXO2 ), .F1(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 )); - ram2e_ufm_SLICE_40 \ram2e_ufm/SLICE_40 ( .D1(\CS[1] ), .C1(\CS[2] ), - .B1(\CS[0] ), .A1(\Din_c[6] ), .B0(\ram2e_ufm/N_851 ), - .A0(\ram2e_ufm/N_800 ), .DI0(\ram2e_ufm/CmdExecMXO2_3 ), .CE(N_187_i), - .CLK(C14M_c), .F0(\ram2e_ufm/CmdExecMXO2_3 ), .Q0(\ram2e_ufm/CmdExecMXO2 ), - .F1(\ram2e_ufm/N_800 )); - ram2e_ufm_SLICE_41 \ram2e_ufm/SLICE_41 ( .D1(\Din_c[0] ), .C1(\Din_c[1] ), - .B1(\Din_c[2] ), .A1(\Din_c[4] ), - .D0(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ), .C0(\ram2e_ufm/N_800 ), - .B0(\ram2e_ufm/N_190 ), .A0(\Din_c[7] ), - .DI0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .CE(N_187_i), .CLK(C14M_c), - .F0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), .Q0(\ram2e_ufm/CmdSetRWBankFFChip ), - .F1(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 )); - ram2e_ufm_SLICE_42 \ram2e_ufm/SLICE_42 ( .C1(\Din_c[6] ), .B1(\Din_c[2] ), - .A1(\Din_c[0] ), .C0(\ram2e_ufm/wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), - .DI0(\ram2e_ufm/N_295 ), .CE(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_295 ), .Q0(\ram2e_ufm/LEDEN ), - .F1(\ram2e_ufm/N_212 )); - ram2e_ufm_SLICE_43 \ram2e_ufm/SLICE_43 ( .C1(\ram2e_ufm/wb_dato[1] ), - .B1(\S[3] ), .A1(\Din_c[1] ), .C0(\ram2e_ufm/wb_dato[0] ), .B0(\S[3] ), - .A0(\Din_c[0] ), .DI1(\ram2e_ufm/N_307_i ), .DI0(\ram2e_ufm/N_309_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_309_i ), .Q0(\ram2e_ufm/RWMask[0] ), - .F1(\ram2e_ufm/N_307_i ), .Q1(\ram2e_ufm/RWMask[1] )); - ram2e_ufm_SLICE_44 \ram2e_ufm/SLICE_44 ( .C1(\ram2e_ufm/wb_dato[3] ), - .B1(\S[3] ), .A1(\Din_c[3] ), .C0(\ram2e_ufm/wb_dato[2] ), .B0(\S[3] ), - .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_302_i ), .DI0(\ram2e_ufm/N_304_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_304_i ), .Q0(\ram2e_ufm/RWMask[2] ), - .F1(\ram2e_ufm/N_302_i ), .Q1(\ram2e_ufm/RWMask[3] )); - ram2e_ufm_SLICE_45 \ram2e_ufm/SLICE_45 ( .C1(\ram2e_ufm/wb_dato[5] ), - .B1(\S[3] ), .A1(\Din_c[5] ), .C0(\ram2e_ufm/wb_dato[4] ), .B0(\S[3] ), - .A0(\Din_c[4] ), .DI1(\ram2e_ufm/N_301_i ), .DI0(\ram2e_ufm/N_310_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_310_i ), .Q0(\ram2e_ufm/RWMask[4] ), - .F1(\ram2e_ufm/N_301_i ), .Q1(\ram2e_ufm/RWMask[5] )); - ram2e_ufm_SLICE_46 \ram2e_ufm/SLICE_46 ( .C1(\ram2e_ufm/wb_dato[7] ), - .B1(\S[3] ), .A1(\Din_c[7] ), .C0(\ram2e_ufm/wb_dato[6] ), .B0(\S[3] ), - .A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_296 ), .DI0(\ram2e_ufm/N_300_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_300_i ), .Q0(\ram2e_ufm/RWMask[6] ), - .F1(\ram2e_ufm/N_296 ), .Q1(\ram2e_ufm/RWMask[7] )); - ram2e_ufm_SLICE_47 \ram2e_ufm/SLICE_47 ( .D1(\ram2e_ufm/wb_adr_7_5_41_0_1 ), - .C1(\S[2] ), .B1(\ram2e_ufm/N_768 ), .A1(\Din_c[1] ), - .D0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), - .B0(\ram2e_ufm/N_793 ), .A0(\FS[10] ), .DI1(\ram2e_ufm/wb_adr_RNO[1] ), - .DI0(\ram2e_ufm/wb_adr_7_i_i[0] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_adr_7_i_i[0] ), .Q0(\ram2e_ufm/wb_adr[0] ), - .F1(\ram2e_ufm/wb_adr_RNO[1] ), .Q1(\ram2e_ufm/wb_adr[1] )); - ram2e_ufm_SLICE_48 \ram2e_ufm/SLICE_48 ( .B1(\S[2] ), .A1(\Din_c[3] ), - .B0(\S[2] ), .A0(\Din_c[2] ), .DI1(\ram2e_ufm/N_268_i ), - .DI0(\ram2e_ufm/N_80_i ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_80_i ), .Q0(\ram2e_ufm/wb_adr[2] ), - .F1(\ram2e_ufm/N_268_i ), .Q1(\ram2e_ufm/wb_adr[3] )); - ram2e_ufm_SLICE_49 \ram2e_ufm/SLICE_49 ( .C1(\S[2] ), .B1(\FS[14] ), - .A1(\Din_c[5] ), .C0(\S[2] ), .B0(\FS[14] ), .A0(\Din_c[4] ), - .DI1(\ram2e_ufm/N_290 ), .DI0(\ram2e_ufm/N_294 ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_294 ), .Q0(\ram2e_ufm/wb_adr[4] ), .F1(\ram2e_ufm/N_290 ), - .Q1(\ram2e_ufm/wb_adr[5] )); - ram2e_ufm_SLICE_50 \ram2e_ufm/SLICE_50 ( .B1(\S[2] ), .A1(\Din_c[7] ), - .C0(\S[2] ), .B0(\FS[14] ), .A0(\Din_c[6] ), .DI1(\ram2e_ufm/N_267_i ), - .DI0(\ram2e_ufm/N_284 ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_284 ), .Q0(\ram2e_ufm/wb_adr[6] ), - .F1(\ram2e_ufm/N_267_i ), .Q1(\ram2e_ufm/wb_adr[7] )); - ram2e_ufm_SLICE_51 \ram2e_ufm/SLICE_51 ( .D1(\ram2e_ufm/wb_ack ), - .C1(\ram2e_ufm/N_336 ), .B1(\FS[14] ), .A1(\FS[0] ), - .C0(\ram2e_ufm/CmdExecMXO2 ), .B0(\S[3] ), .A0(\ram2e_ufm/N_687 ), - .DI0(\ram2e_ufm/wb_cyc_stb_RNO ), - .CE(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_cyc_stb_RNO ), .Q0(\ram2e_ufm/wb_cyc_stb ), - .F1(\ram2e_ufm/N_687 )); - ram2e_ufm_SLICE_52 \ram2e_ufm/SLICE_52 ( .D1(\ram2e_ufm/wb_dati_7_0_0_0[1] ), - .C1(\ram2e_ufm/N_849 ), .B1(\ram2e_ufm/N_793 ), .A1(\ram2e_ufm/N_611 ), - .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ), .C0(\ram2e_ufm/wb_adr[0] ), - .B0(\S[2] ), .A0(\ram2e_ufm/N_856 ), .DI1(\ram2e_ufm/wb_dati_7[1] ), - .DI0(\ram2e_ufm/wb_dati_7[0] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[0] ), .Q0(\ram2e_ufm/wb_dati[0] ), - .F1(\ram2e_ufm/wb_dati_7[1] ), .Q1(\ram2e_ufm/wb_dati[1] )); - ram2e_ufm_SLICE_53 \ram2e_ufm/SLICE_53 ( - .D1(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .C1(\ram2e_ufm/N_849 ), - .B1(\ram2e_ufm/N_783 ), .A1(\ram2e_ufm/N_611 ), - .D0(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C0(\ram2e_ufm/wb_adr[2] ), - .B0(\S[2] ), .A0(\ram2e_ufm/N_760 ), .DI1(\ram2e_ufm/wb_dati_7[3] ), - .DI0(\ram2e_ufm/wb_dati_7[2] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[2] ), .Q0(\ram2e_ufm/wb_dati[2] ), - .F1(\ram2e_ufm/wb_dati_7[3] ), .Q1(\ram2e_ufm/wb_dati[3] )); - ram2e_ufm_SLICE_54 \ram2e_ufm/SLICE_54 ( - .D1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .C1(\ram2e_ufm/wb_adr[5] ), - .B1(\S[2] ), .A1(\ram2e_ufm/N_760 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0[4] ), - .C0(\ram2e_ufm/N_763 ), .B0(\ram2e_ufm/N_760 ), .A0(\ram2e_ufm/N_757 ), - .DI1(\ram2e_ufm/wb_dati_7[5] ), .DI0(\ram2e_ufm/wb_dati_7[4] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_dati_7[4] ), .Q0(\ram2e_ufm/wb_dati[4] ), - .F1(\ram2e_ufm/wb_dati_7[5] ), .Q1(\ram2e_ufm/wb_dati[5] )); - ram2e_ufm_SLICE_55 \ram2e_ufm/SLICE_55 ( - .D1(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), - .C1(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), .B1(\ram2e_ufm/N_604 ), - .A1(\ram2e_ufm/N_602 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), - .C0(\ram2e_ufm/N_849 ), .B0(\ram2e_ufm/N_793 ), .A0(\ram2e_ufm/N_757 ), - .DI1(\ram2e_ufm/wb_dati_7[7] ), .DI0(\ram2e_ufm/wb_dati_7[6] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_dati_7[6] ), .Q0(\ram2e_ufm/wb_dati[6] ), - .F1(\ram2e_ufm/wb_dati_7[7] ), .Q1(\ram2e_ufm/wb_dati[7] )); - ram2e_ufm_SLICE_56 \ram2e_ufm/SLICE_56 ( .D1(\S[3] ), .C1(\S[1] ), - .B1(\S[0] ), .A1(\FS[14] ), .D0(\ram2e_ufm/wb_reqc_1 ), .C0(\FS[13] ), - .B0(\FS[12] ), .A0(\FS[11] ), .DI0(\ram2e_ufm/wb_reqc_i ), - .CE(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ), .LSR(\S[2] ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_reqc_i ), .Q0(\ram2e_ufm/wb_req ), - .F1(\ram2e_ufm/wb_reqc_1 )); - ram2e_ufm_SLICE_57 \ram2e_ufm/SLICE_57 ( .D1(\FS[15] ), .C1(\FS[14] ), - .B1(\FS[4] ), .A1(\FS[2] ), .B0(\FS[15] ), .A0(\FS[14] ), - .DI0(\ram2e_ufm/wb_rst8 ), .LSR(\ram2e_ufm/wb_rst16_i ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_rst8 ), .Q0(\ram2e_ufm/wb_rst ), - .F1(\ram2e_ufm/Ready3_0_a3_4 )); - ram2e_ufm_SLICE_58 \ram2e_ufm/SLICE_58 ( - .D1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), .C1(\ram2e_ufm/N_885 ), - .B1(\ram2e_ufm/N_799 ), .A1(\FS[12] ), - .D0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ), .C0(\ram2e_ufm/N_799 ), - .B0(\ram2e_ufm/N_208 ), .A0(\FS[13] ), .DI0(\ram2e_ufm/wb_we_RNO ), - .CE(\ram2e_ufm/wb_we_RNO_0 ), .CLK(C14M_c), .F0(\ram2e_ufm/wb_we_RNO ), - .Q0(\ram2e_ufm/wb_we ), .F1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 )); - ram2e_ufm_SUM0_i_m3_0_SLICE_59 \ram2e_ufm/SUM0_i_m3_0/SLICE_59 ( - .C1(\CS[1] ), .B1(\Din_c[5] ), .A1(\Din_c[3] ), .C0(\Din_c[7] ), - .B0(\Din_c[5] ), .A0(\Din_c[3] ), .M0(\Din_c[1] ), - .OFX0(\ram2e_ufm/N_338 )); - ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60 ( .D1(\CS[0] ), .C1(\Din_c[6] ), - .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), .A1(\ram2e_ufm/N_193 ), - .C0(CO0_0), .B0(\CmdTout[1] ), .A0(\CmdTout[2] ), .M0(RWSel), - .OFX0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 )); - ram2e_ufm_CKE_7_SLICE_61 \ram2e_ufm/CKE_7/SLICE_61 ( .C1(\RC[1] ), - .B1(\ram2e_ufm/N_821 ), .A1(\ram2e_ufm/N_817 ), .C0(nWE_c), .B0(\S[1] ), - .A0(\ram2e_ufm/N_804 ), .M0(\ram2e_ufm/CKE_7_sm0 ), - .OFX0(\ram2e_ufm/CKE_7 )); - ram2e_ufm_SLICE_62 \ram2e_ufm/SLICE_62 ( .D1(\ram2e_ufm/N_851 ), - .C1(\Din_c[6] ), .B1(\CS[2] ), .A1(\CS[1] ), - .D0(\ram2e_ufm/SUM0_i_a3_4_0 ), .C0(\ram2e_ufm/N_234 ), .B0(\CS[2] ), - .A0(\CS[1] ), .F0(\ram2e_ufm/N_720_tz ), .F1(\ram2e_ufm/SUM0_i_a3_4_0 )); - ram2e_ufm_SLICE_63 \ram2e_ufm/SLICE_63 ( .D1(\ram2e_ufm/SUM0_i_0 ), - .C1(\ram2e_ufm/N_350 ), .B1(\CS[2] ), .A1(\CS[0] ), - .D0(\ram2e_ufm/SUM0_i_3 ), .C0(\ram2e_ufm/SUM0_i_1 ), - .B0(\ram2e_ufm/N_187 ), .A0(\CS[0] ), .F0(\ram2e_ufm/SUM0_i_4 ), - .F1(\ram2e_ufm/SUM0_i_1 )); - ram2e_ufm_SLICE_64 \ram2e_ufm/SLICE_64 ( .C1(\ram2e_ufm/N_793 ), - .B1(\FS[11] ), .A1(\FS[9] ), .D0(\ram2e_ufm/N_856 ), - .C0(\ram2e_ufm/N_755 ), .B0(\FS[13] ), .A0(\FS[11] ), - .F0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .F1(\ram2e_ufm/N_755 )); - ram2e_ufm_SLICE_65 \ram2e_ufm/SLICE_65 ( .D1(\ram2e_ufm/N_193 ), - .C1(\Din_c[6] ), .B1(\Din_c[0] ), .A1(\CS[0] ), .D0(\ram2e_ufm/N_735 ), - .C0(\ram2e_ufm/N_345 ), .B0(\CS[1] ), .A0(\CS[0] ), - .F0(\ram2e_ufm/SUM0_i_0 ), .F1(\ram2e_ufm/N_735 )); - ram2e_ufm_SLICE_66 \ram2e_ufm/SLICE_66 ( .D1(\ram2e_ufm/wb_ack ), - .C1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), - .B1(\ram2e_ufm/N_777 ), .A1(\FS[14] ), .D0(\ram2e_ufm/wb_ack ), - .C0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ), - .B0(\ram2e_ufm/CmdExecMXO2 ), .A0(\ram2e_ufm/N_187 ), - .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), - .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] )); - ram2e_ufm_SLICE_67 \ram2e_ufm/SLICE_67 ( .C1(\FS[3] ), .B1(\FS[2] ), - .A1(\FS[1] ), .D0(\S[1] ), .C0(\ram2e_ufm/N_250 ), .B0(\FS[4] ), - .A0(\FS[3] ), .F0(\ram2e_ufm/N_256 ), .F1(\ram2e_ufm/N_250 )); - ram2e_ufm_SLICE_68 \ram2e_ufm/SLICE_68 ( - .D1(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .C1(\ram2e_ufm/N_783 ), .B1(\FS[9] ), - .A1(\FS[8] ), .D0(\FS[12] ), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[8] ), - .F0(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .F1(\ram2e_ufm/wb_adr_7_i_i_3[0] )); - ram2e_ufm_SLICE_69 \ram2e_ufm/SLICE_69 ( .D1(\ram2e_ufm/N_254 ), - .C1(\ram2e_ufm/wb_rst16_i ), .B1(\FS[15] ), .A1(\FS[0] ), .D0(\S[2] ), - .C0(\S[3] ), .B0(\S[1] ), .A0(\S[0] ), .F0(\ram2e_ufm/wb_rst16_i ), - .F1(\ram2e_ufm/N_641 )); - ram2e_ufm_SLICE_70 \ram2e_ufm/SLICE_70 ( .C1(\FS[14] ), - .B1(\ram2e_ufm/N_777 ), .A1(\FS[8] ), .D0(\FS[12] ), .C0(\FS[13] ), - .B0(\ram2e_ufm/N_807 ), .A0(\ram2e_ufm/N_876 ), .F0(\ram2e_ufm/N_604 ), - .F1(\ram2e_ufm/N_807 )); - ram2e_ufm_SLICE_71 \ram2e_ufm/SLICE_71 ( .C1(\FS[4] ), - .B1(\ram2e_ufm/N_784 ), .A1(\FS[3] ), .C0(\S[2] ), .B0(\S[3] ), - .A0(\S[0] ), .F0(\ram2e_ufm/N_784 ), .F1(\ram2e_ufm/N_801 )); - ram2e_ufm_SLICE_72 \ram2e_ufm/SLICE_72 ( .D1(\S[0] ), .C1(\RWBank[5] ), - .B1(\ram2e_ufm/N_560 ), .A1(\FS[4] ), .C0(\S[2] ), .B0(\S[3] ), - .A0(\S[1] ), .F0(\ram2e_ufm/N_560 ), .F1(\BA_4[0] )); - ram2e_ufm_SLICE_73 \ram2e_ufm/SLICE_73 ( .D1(\ram2e_ufm/N_873 ), - .C1(\ram2e_ufm/N_781 ), .B1(\ram2e_ufm/N_611 ), .A1(\ram2e_ufm/N_184 ), - .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), - .F0(\ram2e_ufm/N_873 ), .F1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] )); - ram2e_ufm_SLICE_74 \ram2e_ufm/SLICE_74 ( .C1(\RWBank[3] ), - .B1(\ram2e_ufm/N_845 ), .A1(\ram2e_ufm/N_625 ), .D0(\S[0] ), .C0(\S[1] ), - .B0(\S[2] ), .A0(\S[3] ), .F0(\ram2e_ufm/N_845 ), - .F1(\ram2e_ufm/RA_35_2_0_0[10] )); - ram2e_ufm_SLICE_75 \ram2e_ufm/SLICE_75 ( .C1(\FS[11] ), .B1(\FS[10] ), - .A1(\FS[9] ), .D0(\FS[12] ), .C0(\FS[13] ), .B0(\ram2e_ufm/N_876 ), - .A0(\ram2e_ufm/wb_ack ), - .F0(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), - .F1(\ram2e_ufm/N_876 )); - ram2e_ufm_SLICE_76 \ram2e_ufm/SLICE_76 ( .B1(\FS[11] ), .A1(\FS[10] ), - .D0(\FS[12] ), .C0(\FS[13] ), .B0(\ram2e_ufm/N_811 ), - .A0(\ram2e_ufm/N_206 ), .F0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), - .F1(\ram2e_ufm/N_811 )); - ram2e_ufm_SLICE_77 \ram2e_ufm/SLICE_77 ( .C1(\ram2e_ufm/N_185 ), .B1(RWSel), - .A1(\CS[0] ), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), - .F0(\ram2e_ufm/N_185 ), .F1(\ram2e_ufm/N_215 )); - ram2e_ufm_SLICE_78 \ram2e_ufm/SLICE_78 ( .B1(\S[1] ), .A1(\S[0] ), - .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\RWBank[1] ), - .F0(\ram2e_ufm/N_699 ), .F1(\ram2e_ufm/S_r_i_0_o2[1] )); - ram2e_ufm_SLICE_79 \ram2e_ufm/SLICE_79 ( - .D1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), - .C1(\ram2e_ufm/N_807 ), .B1(\ram2e_ufm/N_187 ), .A1(CmdLEDSet), - .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(RWSel), - .F0(\ram2e_ufm/N_187 ), .F1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] )); - ram2e_ufm_SLICE_80 \ram2e_ufm/SLICE_80 ( .D1(N_551), .C1(\S[1] ), - .B1(\S[0] ), .A1(\FS[15] ), .D0(\ram2e_ufm/N_185 ), .C0(RWSel), - .B0(\ram2e_ufm/N_777 ), .A0(\ram2e_ufm/CmdBitbangMXO2 ), - .F0(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .F1(\ram2e_ufm/N_777 )); - ram2e_ufm_SLICE_81 \ram2e_ufm/SLICE_81 ( .D1(\FS[8] ), - .C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), .A1(\FS[9] ), .D0(\FS[12] ), - .C0(\FS[13] ), .B0(\ram2e_ufm/N_811 ), .A0(\ram2e_ufm/N_856 ), - .F0(\ram2e_ufm/N_757 ), .F1(\ram2e_ufm/N_856 )); - ram2e_ufm_SLICE_82 \ram2e_ufm/SLICE_82 ( - .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ), - .C1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .B1(\Din_c[6] ), .A1(\CS[0] ), - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ), - .C0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), - .B0(\ram2e_ufm/N_637 ), .A0(\ram2e_ufm/N_185 ), .F0(un1_CS_0_sqmuxa_i), - .F1(\ram2e_ufm/N_637 )); - ram2e_ufm_SLICE_83 \ram2e_ufm/SLICE_83 ( .C1(\ram2e_ufm/N_851 ), - .B1(\Din_c[6] ), .A1(\CS[2] ), .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ), - .C0(RWSel), .B0(\ram2e_ufm/N_592 ), .A0(\CS[0] ), - .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 )); - ram2e_ufm_SLICE_84 \ram2e_ufm/SLICE_84 ( .D1(\ram2e_ufm/N_850 ), - .C1(\ram2e_ufm/N_212 ), .B1(\Din_c[4] ), .A1(\CS[2] ), - .D0(\ram2e_ufm/N_886 ), .C0(\ram2e_ufm/N_720_tz ), .B0(\ram2e_ufm/N_187 ), - .A0(\CS[1] ), .F0(\ram2e_ufm/SUM0_i_3 ), .F1(\ram2e_ufm/N_886 )); - ram2e_ufm_SLICE_85 \ram2e_ufm/SLICE_85 ( .D1(\FS[13] ), - .C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), .A1(\FS[12] ), - .D0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), - .C0(\ram2e_ufm/N_793 ), .B0(\ram2e_ufm/N_187 ), .A0(CmdRWMaskSet), - .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .F1(\ram2e_ufm/N_793 )); - ram2e_ufm_SLICE_86 \ram2e_ufm/SLICE_86 ( .B1(\S[2] ), .A1(\Din_c[0] ), - .D0(\ram2e_ufm/wb_adr_7_i_i_3[0] ), .C0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), - .B0(\ram2e_ufm/N_753 ), .A0(\ram2e_ufm/N_634 ), - .F0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), .F1(\ram2e_ufm/N_634 )); - ram2e_ufm_SLICE_87 \ram2e_ufm/SLICE_87 ( - .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C1(\ram2e_ufm/N_212 ), - .B1(\ram2e_ufm/N_190 ), .A1(\Din_c[1] ), .C0(\ram2e_ufm/N_886 ), - .B0(\ram2e_ufm/N_234 ), .A0(\CS[1] ), .F0(\ram2e_ufm/N_592 ), - .F1(\ram2e_ufm/N_234 )); - ram2e_ufm_SLICE_88 \ram2e_ufm/SLICE_88 ( .B1(\FS[11] ), .A1(\FS[10] ), - .D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\ram2e_ufm/N_876 ), - .B0(\ram2e_ufm/N_793 ), .A0(\ram2e_ufm/N_206 ), - .F0(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] )); - ram2e_ufm_SLICE_89 \ram2e_ufm/SLICE_89 ( .C1(\FS[14] ), - .B1(\ram2e_ufm/N_777 ), .A1(\FS[13] ), - .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .C0(\ram2e_ufm/wb_adr[3] ), - .B0(\S[2] ), .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), - .F1(\ram2e_ufm/N_783 )); - ram2e_ufm_SLICE_90 \ram2e_ufm/SLICE_90 ( .D1(\ram2e_ufm/N_206 ), - .C1(\FS[12] ), .B1(\FS[11] ), .A1(\FS[10] ), - .D0(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ), .C0(\ram2e_ufm/wb_adr[6] ), - .B0(\S[2] ), .A0(\ram2e_ufm/N_783 ), .F0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] )); - ram2e_ufm_SLICE_91 \ram2e_ufm/SLICE_91 ( .D1(CO0_1), .C1(\RC[2] ), - .B1(\ram2e_ufm/N_817 ), .A1(\RC[1] ), .D0(\ram2e_ufm/N_890 ), - .C0(\ram2e_ufm/N_784 ), .B0(\ram2e_ufm/N_256 ), .A0(\ram2e_ufm/N_285_i ), - .F0(\ram2e_ufm/nRAS_s_i_0_0 ), .F1(\ram2e_ufm/N_890 )); - ram2e_ufm_SLICE_92 \ram2e_ufm/SLICE_92 ( .D1(nWE_c), .C1(\S[1] ), - .B1(\ram2e_ufm/N_804 ), .A1(N_551), .D0(\S[0] ), .C0(\ram2e_ufm/N_890 ), - .B0(\ram2e_ufm/N_220 ), .A0(\ram2e_ufm/N_285_i ), .F0(\ram2e_ufm/N_640 ), - .F1(\ram2e_ufm/N_220 )); - ram2e_ufm_SLICE_93 \ram2e_ufm/SLICE_93 ( .D1(\FS[11] ), .C1(\FS[10] ), - .B1(\FS[9] ), .A1(\FS[8] ), .C0(\ram2e_ufm/N_783 ), .B0(\ram2e_ufm/N_196 ), - .A0(\FS[12] ), .F0(\ram2e_ufm/N_760 ), .F1(\ram2e_ufm/N_196 )); - ram2e_ufm_SLICE_94 \ram2e_ufm/SLICE_94 ( .B1(\Din_c[7] ), .A1(\Din_c[4] ), - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C0(\ram2e_ufm/N_243 ), - .B0(\Din_c[0] ), .A0(\CS[2] ), .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 )); - ram2e_ufm_SLICE_95 \ram2e_ufm/SLICE_95 ( .D1(\S[3] ), .C1(\S[2] ), - .B1(\S[1] ), .A1(\S[0] ), .D0(\RA[4] ), .C0(\ram2e_ufm/N_186 ), - .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[4] ), .F0(\ram2e_ufm/RA_35_0_0_0[4] ), - .F1(\ram2e_ufm/N_182 )); - ram2e_ufm_SLICE_96 \ram2e_ufm/SLICE_96 ( .D1(\S[3] ), .C1(\S[2] ), - .B1(\S[1] ), .A1(\S[0] ), .D0(\RA[6] ), .C0(\ram2e_ufm/N_186 ), - .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[6] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[6] ), - .F1(\ram2e_ufm/N_186 )); - ram2e_ufm_SLICE_97 \ram2e_ufm/SLICE_97 ( .C1(\ram2e_ufm/N_873 ), - .B1(\FS[13] ), .A1(\FS[12] ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ), - .C0(\ram2e_ufm/wb_adr[1] ), .B0(\S[2] ), .A0(\ram2e_ufm/N_781 ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0[1] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] )); - ram2e_ufm_SLICE_98 \ram2e_ufm/SLICE_98 ( .B1(\ram2e_ufm/N_777 ), - .A1(\FS[14] ), .D0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), - .C0(\ram2e_ufm/wb_adr[7] ), .B0(\S[2] ), .A0(\ram2e_ufm/N_781 ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), .F1(\ram2e_ufm/N_781 )); - ram2e_ufm_SLICE_99 \ram2e_ufm/SLICE_99 ( .C1(\FS[11] ), .B1(\FS[10] ), - .A1(\FS[8] ), .D0(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ), - .C0(\ram2e_ufm/N_781 ), .B0(\ram2e_ufm/N_565 ), .A0(\FS[12] ), - .F0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), - .F1(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] )); - ram2e_ufm_SLICE_100 \ram2e_ufm/SLICE_100 ( .D1(\Din_c[5] ), .C1(\Din_c[3] ), - .B1(\Din_c[2] ), .A1(\Din_c[1] ), .D0(\ram2e_ufm/N_243 ), .C0(\Din_c[7] ), - .B0(\Din_c[4] ), .A0(\CS[2] ), .F0(\ram2e_ufm/N_345 ), - .F1(\ram2e_ufm/N_243 )); - ram2e_ufm_SLICE_101 \ram2e_ufm/SLICE_101 ( .B1(\Din_c[5] ), .A1(\Din_c[3] ), - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ), .C0(\ram2e_ufm/N_850 ), - .B0(\ram2e_ufm/N_190 ), .A0(\CS[1] ), - .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .F1(\ram2e_ufm/N_190 )); - ram2e_ufm_SLICE_102 \ram2e_ufm/SLICE_102 ( .C1(\S[3] ), .B1(\S[2] ), - .A1(\S[1] ), .C0(\ram2e_ufm/CKE_7s2_0_0_0 ), .B0(\ram2e_ufm/N_817 ), - .A0(\ram2e_ufm/N_220 ), .F0(\ram2e_ufm/CKE_7_sm0 ), .F1(\ram2e_ufm/N_817 )); - ram2e_ufm_SLICE_103 \ram2e_ufm/SLICE_103 ( .B1(\FS[13] ), .A1(\FS[12] ), - .D0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), .C0(\ram2e_ufm/N_799 ), - .B0(\ram2e_ufm/N_204 ), .A0(\ram2e_ufm/N_184 ), - .F0(\ram2e_ufm/wb_adr_7_5_41_0_1 ), .F1(\ram2e_ufm/N_184 )); - ram2e_ufm_SLICE_104 \ram2e_ufm/SLICE_104 ( .D1(\FS[11] ), .C1(\FS[10] ), - .B1(\FS[9] ), .A1(\FS[8] ), .B0(\ram2e_ufm/N_595 ), .A0(\FS[12] ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .F1(\ram2e_ufm/N_595 )); - ram2e_ufm_SLICE_105 \ram2e_ufm/SLICE_105 ( .D1(\ram2e_ufm/nRWE_s_i_0_63_1 ), - .C1(\S[3] ), .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\ram2e_ufm/N_285_i ), - .C0(\ram2e_ufm/wb_rst16_i ), .B0(\FS[15] ), .A0(\FS[0] ), - .F0(\ram2e_ufm/N_285_i ), .F1(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] )); - ram2e_ufm_SLICE_106 \ram2e_ufm/SLICE_106 ( .B1(\S[1] ), .A1(\S[0] ), - .D0(\S[2] ), .C0(\RA[10] ), .B0(\ram2e_ufm/S_r_i_0_o2[1] ), - .A0(\ram2e_ufm/N_194 ), .F0(\ram2e_ufm/N_624 ), .F1(\ram2e_ufm/N_194 )); - ram2e_ufm_SLICE_107 \ram2e_ufm/SLICE_107 ( .D1(\S[0] ), .C1(\FS[4] ), - .B1(\S[3] ), .A1(\S[2] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[8] ), - .B0(\FS[5] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_659 ), .F1(\ram2e_ufm/N_792 )); - ram2e_ufm_SLICE_108 \ram2e_ufm/SLICE_108 ( - .D1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ), .C1(\FS[7] ), - .B1(\FS[5] ), .A1(\FS[4] ), .C0(\ram2e_ufm/wb_req ), - .B0(\ram2e_ufm/N_336 ), .A0(\FS[0] ), - .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), - .F1(\ram2e_ufm/N_336 )); - ram2e_ufm_SLICE_109 \ram2e_ufm/SLICE_109 ( .B1(\S[2] ), .A1(\FS[14] ), - .D0(\ram2e_ufm/N_799 ), .C0(\ram2e_ufm/N_634 ), .B0(\ram2e_ufm/N_184 ), - .A0(\FS[11] ), .F0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), - .F1(\ram2e_ufm/N_799 )); - ram2e_ufm_SLICE_110 \ram2e_ufm/SLICE_110 ( .D1(\FS[8] ), .C1(\FS[9] ), - .B1(\FS[11] ), .A1(\FS[10] ), .B0(\ram2e_ufm/wb_ack ), - .A0(\ram2e_ufm/N_885 ), - .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), - .F1(\ram2e_ufm/N_885 )); - ram2e_ufm_SLICE_111 \ram2e_ufm/SLICE_111 ( .C1(\ram2e_ufm/N_807 ), - .B1(\ram2e_ufm/N_553 ), .A1(\FS[12] ), - .D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\ram2e_ufm/N_811 ), - .B0(\FS[13] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_553 ), - .F1(\ram2e_ufm/N_611 )); - ram2e_ufm_SLICE_112 \ram2e_ufm/SLICE_112 ( .C1(\S[1] ), .B1(\S[0] ), - .A1(\ram2e_ufm/N_285_i ), .D0(nWE_c), .C0(nEN80_c), .B0(\S[2] ), - .A0(\ram2e_ufm/N_866 ), .F0(\ram2e_ufm/N_616 ), .F1(\ram2e_ufm/N_866 )); - ram2e_ufm_SLICE_113 \ram2e_ufm/SLICE_113 ( .C1(nEN80_c), .B1(\S[3] ), - .A1(\S[2] ), .D0(nWE_c), .C0(\S[1] ), .B0(\S[0] ), .A0(\ram2e_ufm/N_804 ), - .F0(\ram2e_ufm/N_628 ), .F1(\ram2e_ufm/N_804 )); - ram2e_ufm_SLICE_114 \ram2e_ufm/SLICE_114 ( .C1(\FS[10] ), .B1(\FS[9] ), - .A1(\FS[8] ), .D0(\ram2e_ufm/N_799 ), .C0(\ram2e_ufm/N_241_i ), - .B0(\FS[12] ), .A0(\FS[11] ), .F0(\ram2e_ufm/N_768 ), - .F1(\ram2e_ufm/N_241_i )); - ram2e_ufm_SLICE_115 \ram2e_ufm/SLICE_115 ( .B1(\S[2] ), .A1(\S[1] ), - .D0(nEN80_c), .C0(\S[3] ), .B0(\S[0] ), .A0(\ram2e_ufm/N_221 ), - .F0(\ram2e_ufm/CKE_7s2_0_0_0 ), .F1(\ram2e_ufm/N_221 )); - ram2e_ufm_SLICE_116 \ram2e_ufm/SLICE_116 ( .D1(\Din_c[3] ), .C1(\Din_c[5] ), - .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .A1(\ram2e_ufm/N_814 ), - .C0(\Din_c[2] ), .B0(\Din_c[1] ), .A0(\Din_c[0] ), .F0(\ram2e_ufm/N_814 ), - .F1(\ram2e_ufm/N_851 )); - ram2e_ufm_SLICE_117 \ram2e_ufm/SLICE_117 ( .D1(\S[1] ), .C1(\S[0] ), - .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[0] ), - .A0(\S[3] ), .F0(N_225_i), .F1(\ram2e_ufm/N_643 )); - ram2e_ufm_SLICE_118 \ram2e_ufm/SLICE_118 ( .D1(\S[1] ), .C1(\S[0] ), - .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[0] ), - .A0(\S[3] ), .F0(N_201_i), .F1(RC12)); - ram2e_ufm_SLICE_119 \ram2e_ufm/SLICE_119 ( .D1(\S[2] ), .C1(\S[3] ), - .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), - .A0(\S[0] ), .F0(N_126), .F1(N_185_i)); - ram2e_ufm_SLICE_120 \ram2e_ufm/SLICE_120 ( .D1(\S[3] ), .C1(\S[0] ), - .B1(\RWBank[0] ), .A1(\FS[15] ), .D0(\S[3] ), .C0(\S[0] ), - .B0(\RWBank[0] ), .A0(\FS[15] ), .F0(N_507_i), .F1(N_508)); - ram2e_ufm_SLICE_121 \ram2e_ufm/SLICE_121 ( .D1(\S[3] ), .C1(\S[2] ), - .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), - .A0(\S[0] ), .F0(\ram2e_ufm/N_242 ), .F1(Vout3)); - ram2e_ufm_SLICE_122 \ram2e_ufm/SLICE_122 ( .D1(\FS[4] ), .C1(\FS[3] ), - .B1(\FS[2] ), .A1(\FS[1] ), .D0(\FS[4] ), .C0(\FS[3] ), .B0(\FS[2] ), - .A0(\FS[1] ), .F0(\ram2e_ufm/N_254 ), .F1(\ram2e_ufm/nRWE_s_i_0_63_1 )); - ram2e_ufm_SLICE_123 \ram2e_ufm/SLICE_123 ( .C1(\FS[11] ), .B1(\FS[9] ), - .A1(\FS[8] ), .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[11] ), .A0(\FS[10] ), - .F0(\ram2e_ufm/N_849 ), .F1(\ram2e_ufm/N_204 )); - ram2e_ufm_SLICE_124 \ram2e_ufm/SLICE_124 ( .D1(\ram2e_ufm/N_784 ), - .C1(\FS[12] ), .B1(\FS[4] ), .A1(\FS[3] ), .D0(\FS[4] ), - .C0(\ram2e_ufm/N_784 ), .B0(\FS[1] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_684 ), - .F1(\ram2e_ufm/RA_35_0_0_0[5] )); - ram2e_ufm_SLICE_125 \ram2e_ufm/SLICE_125 ( .D1(\FS[13] ), .C1(\FS[11] ), - .B1(\FS[9] ), .A1(\FS[8] ), .D0(\ram2e_ufm/N_793 ), .C0(\FS[11] ), - .B0(\FS[9] ), .A0(\FS[8] ), .F0(\ram2e_ufm/N_763 ), .F1(\ram2e_ufm/N_565 )); - ram2e_ufm_SLICE_126 \ram2e_ufm/SLICE_126 ( .D1(\FS[12] ), .C1(\FS[10] ), - .B1(\FS[9] ), .A1(\FS[8] ), .D0(\ram2e_ufm/N_781 ), .C0(\FS[12] ), - .B0(\FS[10] ), .A0(\FS[9] ), .F0(\ram2e_ufm/N_753 ), - .F1(\ram2e_ufm/N_208 )); - ram2e_ufm_SLICE_127 \ram2e_ufm/SLICE_127 ( .D1(\S[3] ), .C1(\S[2] ), - .B1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\S[2] ), .B0(\S[0] ), - .A0(\RWBank[7] ), .F0(\ram2e_ufm/N_698 ), .F1(un9_VOEEN_0_a2_0_a3_0_a3)); - ram2e_ufm_SLICE_128 \ram2e_ufm/SLICE_128 ( .D1(\FS[13] ), .C1(\FS[12] ), - .B1(\FS[11] ), .A1(\FS[10] ), .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ), - .F0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), - .F1(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] )); - ram2e_ufm_SLICE_129 \ram2e_ufm/SLICE_129 ( .D1(\S[0] ), .C1(\RWBank[6] ), - .B1(\ram2e_ufm/N_560 ), .A1(\FS[4] ), .D0(N_551), .C0(\S[0] ), - .B0(\FS[1] ), .A0(\FS[4] ), .F0(\ram2e_ufm/N_627 ), .F1(\BA_4[1] )); - ram2e_ufm_SLICE_130 \ram2e_ufm/SLICE_130 ( .B1(\ram2e_ufm/N_185 ), - .A1(RWSel), .D0(\ram2e_ufm/N_185 ), .C0(RWSel), .B0(\ram2e_ufm/N_777 ), - .A0(\ram2e_ufm/CmdExecMXO2 ), .F0(\ram2e_ufm/wb_we_RNO_0 ), .F1(N_187_i)); - ram2e_ufm_SLICE_131 \ram2e_ufm/SLICE_131 ( .D1(\FS[13] ), .C1(\FS[12] ), - .B1(\FS[3] ), .A1(\FS[1] ), .D0(\ram2e_ufm/N_856 ), .C0(\ram2e_ufm/N_811 ), - .B0(\FS[13] ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_602 ), - .F1(\ram2e_ufm/Ready3_0_a3_5 )); - ram2e_ufm_SLICE_132 \ram2e_ufm/SLICE_132 ( .D1(\RA[0] ), - .C1(\ram2e_ufm/N_186 ), .B1(\ram2e_ufm/N_182 ), .A1(\Ain_c[0] ), - .D0(\RA[7] ), .C0(\ram2e_ufm/N_186 ), .B0(\ram2e_ufm/N_182 ), - .A0(\Ain_c[7] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[7] ), - .F1(\ram2e_ufm/RA_35_0_0_1[0] )); - ram2e_ufm_SLICE_133 \ram2e_ufm/SLICE_133 ( .D1(RWSel), .C1(\Din_c[4] ), - .B1(\Din_c[2] ), .A1(\Din_c[0] ), .C0(\ram2e_ufm/N_338 ), .B0(\Din_c[4] ), - .A0(\Din_c[2] ), .F0(\ram2e_ufm/N_350 ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 )); - ram2e_ufm_SLICE_134 \ram2e_ufm/SLICE_134 ( .D1(\FS[6] ), .C1(\FS[3] ), - .B1(\FS[2] ), .A1(\FS[1] ), .D0(\ram2e_ufm/N_792 ), .C0(\FS[9] ), - .B0(\FS[6] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_679 ), - .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] )); - ram2e_ufm_SLICE_135 \ram2e_ufm/SLICE_135 ( .B1(\S[3] ), .A1(\S[2] ), - .D0(nEN80_c), .C0(\S[3] ), .B0(\S[2] ), .A0(\ram2e_ufm/S_r_i_0_o2[1] ), - .F0(\ram2e_ufm/N_625 ), .F1(\ram2e_ufm/N_271 )); - ram2e_ufm_SLICE_136 \ram2e_ufm/SLICE_136 ( .C1(nWE_c), .B1(nEN80_c), - .A1(\S[3] ), .C0(nWE_c), .B0(nEN80_c), .A0(DOEEN), .F0(nDOE_c), - .F1(\ram2e_ufm/N_226 )); - ram2e_ufm_SLICE_137 \ram2e_ufm/SLICE_137 ( .C1(nWE_c), .B1(nEN80_c), - .A1(Ready), .C0(nEN80_c), .B0(Ready), .A0(\ram2e_ufm/LEDEN ), .F0(LED_c), - .F1(RDOE_i)); - SLICE_138 SLICE_138( .C1(\S[0] ), .B1(\S[1] ), .A1(\S[3] ), .C0(\S[0] ), - .B0(\S[1] ), .A0(\S[2] ), .F0(N_1080_0), .F1(N_1078_0)); - SLICE_139 SLICE_139( .B1(VOEEN), .A1(PHI1_c), .C0(Ready), .B0(PHI1r), - .A0(PHI1_c), .F0(S_1), .F1(nVOE_c)); - ram2e_ufm_SLICE_140 \ram2e_ufm/SLICE_140 ( .B1(\RA[2] ), - .A1(\ram2e_ufm/N_186 ), .B0(\RA[5] ), .A0(\ram2e_ufm/N_186 ), - .F0(\ram2e_ufm/N_621 ), .F1(\ram2e_ufm/N_680 )); - ram2e_ufm_SLICE_141 \ram2e_ufm/SLICE_141 ( .B1(Ready), .A1(\Din_c[0] ), - .B0(Ready), .A0(\Din_c[3] ), .F0(N_263_i), .F1(N_667)); - ram2e_ufm_SLICE_142 \ram2e_ufm/SLICE_142 ( .C1(\Din_c[4] ), .B1(\Din_c[7] ), - .A1(\Din_c[0] ), .B0(Ready), .A0(\Din_c[4] ), .F0(N_648), - .F1(\ram2e_ufm/CmdLEDGet_3_0_a3_1 )); - ram2e_ufm_SLICE_143 \ram2e_ufm/SLICE_143 ( .B1(Ready), .A1(\Din_c[1] ), - .B0(Ready), .A0(\Din_c[7] ), .F0(N_662), .F1(N_666)); - ram2e_ufm_SLICE_144 \ram2e_ufm/SLICE_144 ( .B1(Ready), .A1(\Din_c[2] ), - .B0(Ready), .A0(\Din_c[6] ), .F0(N_663), .F1(N_665)); - ram2e_ufm_SLICE_145 \ram2e_ufm/SLICE_145 ( .D1(\ram2e_ufm/wb_adr[4] ), - .C1(\S[2] ), .B1(\ram2e_ufm/N_873 ), .A1(\ram2e_ufm/N_783 ), .B0(\FS[9] ), - .A0(\FS[8] ), .F0(\ram2e_ufm/N_206 ), .F1(\ram2e_ufm/wb_dati_7_0_0_0[4] )); - ram2e_ufm_SLICE_146 \ram2e_ufm/SLICE_146 ( .D1(\RWBank[2] ), - .C1(\ram2e_ufm/N_845 ), .B1(\ram2e_ufm/N_784 ), .A1(\FS[4] ), .D0(\FS[7] ), - .C0(\FS[6] ), .B0(\FS[5] ), .A0(\FS[0] ), .F0(\ram2e_ufm/Ready3_0_a3_3 ), - .F1(\ram2e_ufm/RA_35_0_0_0[9] )); - ram2e_ufm_SLICE_147 \ram2e_ufm/SLICE_147 ( .D1(\ram2e_ufm/LEDEN ), - .C1(CmdSetRWBankFFLED), .B1(\ram2e_ufm/CmdSetRWBankFFChip ), - .A1(CmdLEDGet), .B0(Ready), .A0(\Din_c[5] ), .F0(N_664), - .F1(\ram2e_ufm/N_188 )); - RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(N_667), - .RD0(RD[0])); - LED LED_I( .PADDO(LED_c), .LED(LED)); - C14M C14M_I( .PADDI(C14M_c), .C14M(C14M)); - RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(N_662), - .RD7(RD[7])); - RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(N_663), - .RD6(RD[6])); - RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(N_664), - .RD5(RD[5])); - RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(N_648), - .RD4(RD[4])); - RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(N_263_i), - .RD3(RD[3])); - RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(N_665), - .RD2(RD[2])); - RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(N_666), - .RD1(RD[1])); - DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH)); - DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_508), .CE(N_201_i), - .CLK(C14M_c)); - DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML)); - DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_507_i), .CE(N_201_i), - .CLK(C14M_c)); - RAout_11_ \RAout[11]_I ( .IOLDO(\RAout_c[11] ), .RAout11(RAout[11])); - RAout_11__MGIOL \RAout[11]_MGIOL ( .IOLDO(\RAout_c[11] ), .OPOS(\RA[11] ), - .CLK(C14M_c)); - RAout_10_ \RAout[10]_I ( .IOLDO(\RAout_c[10] ), .RAout10(RAout[10])); - RAout_10__MGIOL \RAout[10]_MGIOL ( .IOLDO(\RAout_c[10] ), .OPOS(\RA[10] ), - .CLK(C14M_c)); - RAout_9_ \RAout[9]_I ( .IOLDO(\RAout_c[9] ), .RAout9(RAout[9])); - RAout_9__MGIOL \RAout[9]_MGIOL ( .IOLDO(\RAout_c[9] ), .OPOS(\RA[9] ), - .CLK(C14M_c)); - RAout_8_ \RAout[8]_I ( .IOLDO(\RAout_c[8] ), .RAout8(RAout[8])); - RAout_8__MGIOL \RAout[8]_MGIOL ( .IOLDO(\RAout_c[8] ), .OPOS(\RA[8] ), - .CLK(C14M_c)); - RAout_7_ \RAout[7]_I ( .IOLDO(\RAout_c[7] ), .RAout7(RAout[7])); - RAout_7__MGIOL \RAout[7]_MGIOL ( .IOLDO(\RAout_c[7] ), .OPOS(\RA[7] ), - .CLK(C14M_c)); - RAout_6_ \RAout[6]_I ( .IOLDO(\RAout_c[6] ), .RAout6(RAout[6])); - RAout_6__MGIOL \RAout[6]_MGIOL ( .IOLDO(\RAout_c[6] ), .OPOS(\RA[6] ), - .CLK(C14M_c)); - RAout_5_ \RAout[5]_I ( .IOLDO(\RAout_c[5] ), .RAout5(RAout[5])); - RAout_5__MGIOL \RAout[5]_MGIOL ( .IOLDO(\RAout_c[5] ), .OPOS(\RA[5] ), - .CLK(C14M_c)); - RAout_4_ \RAout[4]_I ( .IOLDO(\RAout_c[4] ), .RAout4(RAout[4])); - RAout_4__MGIOL \RAout[4]_MGIOL ( .IOLDO(\RAout_c[4] ), .OPOS(\RA[4] ), - .CLK(C14M_c)); - RAout_3_ \RAout[3]_I ( .IOLDO(\RAout_c[3] ), .RAout3(RAout[3])); - RAout_3__MGIOL \RAout[3]_MGIOL ( .IOLDO(\RAout_c[3] ), .OPOS(\RA[3] ), - .CLK(C14M_c)); - RAout_2_ \RAout[2]_I ( .IOLDO(\RAout_c[2] ), .RAout2(RAout[2])); - RAout_2__MGIOL \RAout[2]_MGIOL ( .IOLDO(\RAout_c[2] ), .OPOS(\RA[2] ), - .CLK(C14M_c)); - RAout_1_ \RAout[1]_I ( .IOLDO(\RAout_c[1] ), .RAout1(RAout[1])); - RAout_1__MGIOL \RAout[1]_MGIOL ( .IOLDO(\RAout_c[1] ), .OPOS(\RA[1] ), - .CLK(C14M_c)); - RAout_0_ \RAout[0]_I ( .IOLDO(\RAout_c[0] ), .RAout0(RAout[0])); - RAout_0__MGIOL \RAout[0]_MGIOL ( .IOLDO(\RAout_c[0] ), .OPOS(\RA[0] ), - .CLK(C14M_c)); - BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1])); - BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), .CE(N_225_i), - .LSR(BA_0_sqmuxa), .CLK(C14M_c)); - BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0])); - BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), .CE(N_225_i), - .LSR(BA_0_sqmuxa), .CLK(C14M_c)); - nRWEout nRWEout_I( .IOLDO(nRWEout_c), .nRWEout(nRWEout)); - nRWEout_MGIOL nRWEout_MGIOL( .IOLDO(nRWEout_c), .OPOS(nRWE), .CLK(C14M_c)); - nCASout nCASout_I( .IOLDO(nCASout_c), .nCASout(nCASout)); - nCASout_MGIOL nCASout_MGIOL( .IOLDO(nCASout_c), .OPOS(nCAS), .CLK(C14M_c)); - nRASout nRASout_I( .IOLDO(nRASout_c), .nRASout(nRASout)); - nRASout_MGIOL nRASout_MGIOL( .IOLDO(nRASout_c), .OPOS(nRAS), .CLK(C14M_c)); - nCSout nCSout_I( .PADDO(GND), .nCSout(nCSout)); - CKEout CKEout_I( .IOLDO(CKEout_c), .CKEout(CKEout)); - CKEout_MGIOL CKEout_MGIOL( .IOLDO(CKEout_c), .OPOS(CKE), .CLK(C14M_c)); - nVOE nVOE_I( .PADDO(nVOE_c), .nVOE(nVOE)); - Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7])); - Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_6_ \Vout[6]_I ( .IOLDO(\Vout_c[6] ), .Vout6(Vout[6])); - Vout_6__MGIOL \Vout[6]_MGIOL ( .IOLDO(\Vout_c[6] ), .OPOS(\RD_in[6] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_5_ \Vout[5]_I ( .IOLDO(\Vout_c[5] ), .Vout5(Vout[5])); - Vout_5__MGIOL \Vout[5]_MGIOL ( .IOLDO(\Vout_c[5] ), .OPOS(\RD_in[5] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_4_ \Vout[4]_I ( .IOLDO(\Vout_c[4] ), .Vout4(Vout[4])); - Vout_4__MGIOL \Vout[4]_MGIOL ( .IOLDO(\Vout_c[4] ), .OPOS(\RD_in[4] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_3_ \Vout[3]_I ( .IOLDO(\Vout_c[3] ), .Vout3(Vout[3])); - Vout_3__MGIOL \Vout[3]_MGIOL ( .IOLDO(\Vout_c[3] ), .OPOS(\RD_in[3] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_2_ \Vout[2]_I ( .IOLDO(\Vout_c[2] ), .Vout2(Vout[2])); - Vout_2__MGIOL \Vout[2]_MGIOL ( .IOLDO(\Vout_c[2] ), .OPOS(\RD_in[2] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_1_ \Vout[1]_I ( .IOLDO(\Vout_c[1] ), .Vout1(Vout[1])); - Vout_1__MGIOL \Vout[1]_MGIOL ( .IOLDO(\Vout_c[1] ), .OPOS(\RD_in[1] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_0_ \Vout[0]_I ( .IOLDO(\Vout_c[0] ), .Vout0(Vout[0])); - Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), - .CE(Vout3), .CLK(C14M_c)); - nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE)); - Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7])); - Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6])); - Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5])); - Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4])); - Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3])); - Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2])); - Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1])); - Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0])); - Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7])); - Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6])); - Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5])); - Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4])); - Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3])); - Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2])); - Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1])); - Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0])); - Ain_7_ \Ain[7]_I ( .PADDI(\Ain_c[7] ), .Ain7(Ain[7])); - Ain_6_ \Ain[6]_I ( .PADDI(\Ain_c[6] ), .Ain6(Ain[6])); - Ain_5_ \Ain[5]_I ( .PADDI(\Ain_c[5] ), .Ain5(Ain[5])); - Ain_4_ \Ain[4]_I ( .PADDI(\Ain_c[4] ), .Ain4(Ain[4])); - Ain_3_ \Ain[3]_I ( .PADDI(\Ain_c[3] ), .Ain3(Ain[3])); - Ain_2_ \Ain[2]_I ( .PADDI(\Ain_c[2] ), .Ain2(Ain[2])); - Ain_1_ \Ain[1]_I ( .PADDI(\Ain_c[1] ), .Ain1(Ain[1])); - Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0])); - nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X)); - nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80)); - nWE nWE_I( .PADDI(nWE_c), .nWE(nWE)); - PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1)); - PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1r)); - ram2e_ufm_ufmefb_EFBInst_0 \ram2e_ufm/ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), - .WBRSTI(\ram2e_ufm/wb_rst ), .WBCYCI(\ram2e_ufm/wb_cyc_stb ), - .WBSTBI(\ram2e_ufm/wb_cyc_stb ), .WBWEI(\ram2e_ufm/wb_we ), - .WBADRI0(\ram2e_ufm/wb_adr[0] ), .WBADRI1(\ram2e_ufm/wb_adr[1] ), - .WBADRI2(\ram2e_ufm/wb_adr[2] ), .WBADRI3(\ram2e_ufm/wb_adr[3] ), - .WBADRI4(\ram2e_ufm/wb_adr[4] ), .WBADRI5(\ram2e_ufm/wb_adr[5] ), - .WBADRI6(\ram2e_ufm/wb_adr[6] ), .WBADRI7(\ram2e_ufm/wb_adr[7] ), - .WBDATI0(\ram2e_ufm/wb_dati[0] ), .WBDATI1(\ram2e_ufm/wb_dati[1] ), - .WBDATI2(\ram2e_ufm/wb_dati[2] ), .WBDATI3(\ram2e_ufm/wb_dati[3] ), - .WBDATI4(\ram2e_ufm/wb_dati[4] ), .WBDATI5(\ram2e_ufm/wb_dati[5] ), - .WBDATI6(\ram2e_ufm/wb_dati[6] ), .WBDATI7(\ram2e_ufm/wb_dati[7] ), - .WBDATO0(\ram2e_ufm/wb_dato[0] ), .WBDATO1(\ram2e_ufm/wb_dato[1] ), - .WBDATO2(\ram2e_ufm/wb_dato[2] ), .WBDATO3(\ram2e_ufm/wb_dato[3] ), - .WBDATO4(\ram2e_ufm/wb_dato[4] ), .WBDATO5(\ram2e_ufm/wb_dato[5] ), - .WBDATO6(\ram2e_ufm/wb_dato[6] ), .WBDATO7(\ram2e_ufm/wb_dato[7] ), - .WBACKO(\ram2e_ufm/wb_ack )); - VHI VHI_INST( .Z(VCCI)); - PUR PUR_INST( .PUR(VCCI)); - GSR GSR_INST( .GSR(VCCI)); -endmodule - -module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly; - - vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module vcc ( output PWR1 ); - - VHI INST1( .Z(PWR1)); -endmodule - -module gnd ( output PWR0 ); - - VLO INST1( .Z(PWR0)); -endmodule - -module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h000A; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - ccu20001 \FS_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); - - specify - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h5002; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h300A; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut4 \ram2e_ufm/wb_req_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40003 \ram2e_ufm/CKE_7_RNIS77M1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 CKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut4 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40003 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_10 ( input B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40005 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40006 \ram2e_ufm/CmdTout_3_0_a3_0_a3[0] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40005 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40006 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_11 ( input B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40006 \ram2e_ufm/RC_3_0_0_a3_1[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40007 \ram2e_ufm/N_360_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \RC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40007 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_12 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - - lut40008 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNI6S1P8 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40009 \ram2e_ufm/S_r_i_0_o2_RNIVM0LF[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0010 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0010 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40008 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40009 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0010 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_13 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output - F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40011 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40012 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0010 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40011 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA2A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40012 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC4C6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40013 \ram2e_ufm/CmdLEDGet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40014 \ram2e_ufm/CmdLEDGet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40013 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40014 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_15 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40013 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40015 \ram2e_ufm/CmdLEDSet_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40015 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_16 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40017 \ram2e_ufm/CmdRWMaskSet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40016 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40017 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_17 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40018 \ram2e_ufm/CmdRWMaskSet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40019 \ram2e_ufm/CmdSetRWBankFFLED_4_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40018 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40019 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_18 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40020 \ram2e_ufm/N_369_i ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40021 \ram2e_ufm/N_368_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CmdTout[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40020 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0078) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40021 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0606) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_19 ( input B1, A1, B0, A0, M0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, M0_dly, CLK_dly, LSR_dly; - - lut40022 \ram2e_ufm/SUM0_i_o2 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/RA_35_i_i_0_a3_0[1] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre0010 DOEEN( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40022 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40023 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40024 \ram2e_ufm/RA_35_i_i_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40025 \ram2e_ufm/RA_35_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40024 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40025 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \ram2e_ufm/RA_35_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40024 \ram2e_ufm/RA_35_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40026 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_22 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40024 \ram2e_ufm/RA_35_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40026 \ram2e_ufm/RA_35_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \ram2e_ufm/RA_35_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40026 \ram2e_ufm/RA_35_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre \RA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_24 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \ram2e_ufm/RA_35_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40027 \ram2e_ufm/un2_S_2_i_0_0_o3_RNIHFHN3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \RA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40027 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_25 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40028 \ram2e_ufm/RA_35_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut4 \ram2e_ufm/RA_35_2_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40028 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_26 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40029 \ram2e_ufm/RC_3_0_0[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40030 \ram2e_ufm/RC_3_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \RC[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RC[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40029 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3838) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40030 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4646) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_27 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40031 \ram2e_ufm/RWBank_3_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40031 \ram2e_ufm/RWBank_3_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40031 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_28 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40031 \ram2e_ufm/RWBank_3_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40031 \ram2e_ufm/RWBank_3_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40031 \ram2e_ufm/RWBank_3_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40031 \ram2e_ufm/RWBank_3_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40032 \ram2e_ufm/RWBank_3_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40031 \ram2e_ufm/RWBank_3_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40032 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40033 \ram2e_ufm/RA_35_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40034 \ram2e_ufm/RWSel_2_0_a3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40033 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40034 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; - - lut40035 \ram2e_ufm/Ready3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40036 Ready_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40035 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40036 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40037 \ram2e_ufm/S_r_i_0_o2_0_RNI36E21[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40038 \ram2e_ufm/S_s_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40037 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40038 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFBFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40039 \ram2e_ufm/S_r_i_0_o2_RNIFNP81_0[2] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40040 \ram2e_ufm/S_r_i_0_o2_RNIFNP81[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \S[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40039 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0B0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40040 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_35 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40016 \ram2e_ufm/CKE_7_m1_0_0_o2_RNICM8E1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40036 \ram2e_ufm/CKE_7_m1_0_0_o2 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0010 VOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40041 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40042 \ram2e_ufm/nCAS_s_i_0_a3_RNIO1UQ3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 nCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40041 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40042 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40034 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40016 \ram2e_ufm/nRAS_s_i_0_0_RNI0PC64 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 nRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_38 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40043 \ram2e_ufm/nRAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40044 \ram2e_ufm/nRAS_s_i_0_a3_0_RNIIR094 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0004 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40043 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40044 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_39 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40045 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40019 \ram2e_ufm/CmdBitbangMXO2_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/CmdBitbangMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40045 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_40 ( input D1, C1, B1, A1, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40014 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40023 \ram2e_ufm/CmdExecMXO2_3_0_a3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/CmdExecMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40046 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40014 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/CmdSetRWBankFFChip ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40046 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_42 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40047 \ram2e_ufm/SUM1_0_o3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40048 \ram2e_ufm/LEDEN_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/LEDEN ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40047 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40048 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_43 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40049 \ram2e_ufm/RWMask_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 \ram2e_ufm/RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40049 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7474) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_44 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40049 \ram2e_ufm/RWMask_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 \ram2e_ufm/RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_45 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40049 \ram2e_ufm/RWMask_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 \ram2e_ufm/RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_46 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40048 \ram2e_ufm/RWMask_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40049 \ram2e_ufm/RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40050 \ram2e_ufm/wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40024 \ram2e_ufm/wb_adr_7_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40050 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_48 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40023 \ram2e_ufm/wb_adr_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/wb_adr_RNO[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_49 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40051 \ram2e_ufm/wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40051 \ram2e_ufm/wb_adr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40051 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_50 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40023 \ram2e_ufm/wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40051 \ram2e_ufm/wb_adr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_51 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40052 \ram2e_ufm/wb_cyc_stb_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40053 \ram2e_ufm/wb_cyc_stb_RNO ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_cyc_stb ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40052 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0032) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40053 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40054 \ram2e_ufm/wb_dati_7_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40055 \ram2e_ufm/wb_dati_7_0_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40054 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40055 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40054 \ram2e_ufm/wb_dati_7_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40054 \ram2e_ufm/wb_dati_7_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40054 \ram2e_ufm/wb_dati_7_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut4 \ram2e_ufm/wb_dati_7_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut4 \ram2e_ufm/wb_dati_7_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40054 \ram2e_ufm/wb_dati_7_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut4 \ram2e_ufm/wb_reqc_1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40056 \ram2e_ufm/wb_req_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0010 \ram2e_ufm/wb_req ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40056 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_57 ( input D1, C1, B1, A1, B0, A0, DI0, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40035 \ram2e_ufm/Ready3_0_a3_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40006 \ram2e_ufm/wb_rst8_0_a3_0_a3 ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0010 \ram2e_ufm/wb_rst ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40057 \ram2e_ufm/wb_we_RNO_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40057 \ram2e_ufm/wb_we_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_we ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40057 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SUM0_i_m3_0_SLICE_59 ( input C1, B1, A1, C0, B0, A0, M0, - output OFX0 ); - wire GNDI, - \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 , - \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ; - - lut40058 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), - .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40059 \ram2e_ufm/SUM0_i_m3_0/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 )); - selmux2 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K0K1MUX ( - .D0(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ), - .D1(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ), - .SD(M0), .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40058 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40059 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module selmux2 ( input D0, D1, SD, output Z ); - - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 ( input D1, C1, B1, A1, C0, B0, - A0, M0, output OFX0 ); - wire - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 - , GNDI, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 - ; - - lut40060 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1 ( .A(A1), .B(B1), - .C(C1), .D(D1), - .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 ) - ); - lut40061 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - selmux2 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K0K1MUX ( - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 ) - , - .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40060 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h55D5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40061 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_CKE_7_SLICE_61 ( input C1, B1, A1, C0, B0, A0, M0, output - OFX0 ); - wire GNDI, \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 , - \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ; - - lut40062 \ram2e_ufm/CKE_7/SLICE_61_K1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40063 \ram2e_ufm/CKE_7/GATE ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 )); - selmux2 \ram2e_ufm/CKE_7/SLICE_61_K0K1MUX ( - .D0(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ), - .D1(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ), .SD(M0), - .Z(OFX0)); - - specify - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40062 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5D5D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40063 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40043 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIAJ811 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40064 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIPG3P2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40064 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40065 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40066 \ram2e_ufm/S_r_i_0_o2_RNI3VQTC[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40065 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40066 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40067 \ram2e_ufm/wb_adr_7_i_i_a3_6[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40068 \ram2e_ufm/wb_adr_7_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40067 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40068 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40069 \ram2e_ufm/SUM0_i_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40065 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40069 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40070 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40071 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40070 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40071 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF5F4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40072 \ram2e_ufm/nRAS_s_i_0_m3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40073 \ram2e_ufm/nRAS_s_i_0_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40072 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8B8B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40073 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40074 \ram2e_ufm/wb_adr_7_i_i_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40075 \ram2e_ufm/wb_adr_7_i_i_3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40074 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0090) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40075 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h01A1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40076 \ram2e_ufm/nCAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut4 \ram2e_ufm/wb_rst16_i_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40076 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_70 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40077 \ram2e_ufm/wb_dati_7_0_0_a3_12[7] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40078 \ram2e_ufm/wb_dati_7_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40077 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0404) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40078 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_71 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40013 \ram2e_ufm/RA_35_0_0_a3_4[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40079 \ram2e_ufm/nRAS_s_i_0_a3_4 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40079 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_72 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40080 \ram2e_ufm/BA_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40047 \ram2e_ufm/un1_RC12_i_0_o3 ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40080 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40081 \ram2e_ufm/wb_dati_7_0_0_o3_0[2] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40082 \ram2e_ufm/wb_dati_7_0_0_a3_3[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40081 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40082 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40053 \ram2e_ufm/RA_35_2_0_0[10] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40034 \ram2e_ufm/RA_35_2_0_a3_5[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40079 \ram2e_ufm/wb_dati_7_0_0_a3_15[7] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40015 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40083 \ram2e_ufm/wb_dati_7_0_0_a3_13[7] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40019 \ram2e_ufm/wb_dati_7_0_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40083 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40084 \ram2e_ufm/SUM2_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40085 \ram2e_ufm/N_314_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40084 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40085 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40036 \ram2e_ufm/S_r_i_0_o2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \ram2e_ufm/S_r_i_0_o2_RNIP4KI1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_79 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40086 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40087 \ram2e_ufm/S_r_i_0_o2_RNIOGTF1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40086 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40087 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40034 \ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40088 \ram2e_ufm/CmdBitbangMXO2_RNINSM62 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40088 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40017 \ram2e_ufm/wb_dati_7_0_0_a3_14[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40035 \ram2e_ufm/wb_dati_7_0_0_a3_13_RNI81UL[7] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40019 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_83 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40067 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40089 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40089 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40082 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40090 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40090 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3130) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40017 \ram2e_ufm/wb_dati_7_0_0_a3_10[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40086 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_86 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40023 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_1 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut4 \ram2e_ufm/wb_adr_7_i_i_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40091 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40092 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_m3 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40091 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40092 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8D8D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40093 \ram2e_ufm/wb_dati_7_0_0_a3_4_1_0[7] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40094 \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40093 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40094 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC8C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_89 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40077 \ram2e_ufm/wb_dati_7_0_0_a3_7[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40055 \ram2e_ufm/wb_dati_7_0_0_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40095 \ram2e_ufm/wb_dati_7_0_0_a3_1_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40055 \ram2e_ufm/wb_dati_7_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40095 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0021) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40096 \ram2e_ufm/nRAS_s_i_0_a3_8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40097 \ram2e_ufm/nRAS_s_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40096 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40097 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5540) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40098 \ram2e_ufm/CKE_7s2_0_0_o3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40099 \ram2e_ufm/nCAS_s_i_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40098 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5C50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40099 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_93 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40100 \ram2e_ufm/wb_dati_7_0_0_o2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40013 \ram2e_ufm/wb_dati_7_0_0_a3[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40100 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_94 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40101 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40041 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40101 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40102 \ram2e_ufm/RA_35_0_0_o2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40033 \ram2e_ufm/RA_35_0_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40102 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAE8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40103 \ram2e_ufm/RA_35_0_0_o2_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40033 \ram2e_ufm/RA_35_0_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40103 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1512) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_97 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40104 \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40055 \ram2e_ufm/wb_dati_7_0_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40104 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_98 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40093 \ram2e_ufm/wb_dati_7_0_0_a3_9[7] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40055 \ram2e_ufm/wb_dati_7_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_99 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40105 \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40106 \ram2e_ufm/wb_adr_7_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40105 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40106 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut4 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40107 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40107 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBF8F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_101 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40022 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3 ( .A(A1), .B(B1), - .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40108 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40108 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB1A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_102 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40077 \ram2e_ufm/CKE_7s2_0_0_a2_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40047 \ram2e_ufm/CKE_7s2_0_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_103 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40101 \ram2e_ufm/wb_dati_7_0_0_0_o2[7] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40109 \ram2e_ufm/wb_adr_RNO_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40109 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_104 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40110 \ram2e_ufm/wb_dati_7_0_0_o2_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40093 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40110 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7084) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_105 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40016 \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40111 \ram2e_ufm/N_285_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40111 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0B0B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_106 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40022 \ram2e_ufm/S_r_i_0_o2[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40112 \ram2e_ufm/RA_35_2_0_a3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40112 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_107 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40113 \ram2e_ufm/CKE_7_m1_0_0_o2_RNIGC501 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40114 \ram2e_ufm/RA_35_i_i_0_a3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40113 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40114 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_108 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut4 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40115 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ( .A(A0), - .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40115 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3131) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_109 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40006 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_6 ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40068 \ram2e_ufm/wb_we_RNO_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_110 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40035 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_7 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40023 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ( .A(A0), .B(B0), - .C(GNDI), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_111 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40104 \ram2e_ufm/wb_dati_7_0_0_a3_2[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40116 \ram2e_ufm/wb_dati_7_0_0_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40116 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h9180) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_112 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40018 \ram2e_ufm/nRAS_s_i_0_a3_6 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40117 \ram2e_ufm/nRAS_s_i_0_a3_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40117 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_113 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40077 \ram2e_ufm/nRAS_s_i_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40014 \ram2e_ufm/RA_35_2_0_a3_3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_114 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40118 \ram2e_ufm/wb_adr_RNO_2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40117 \ram2e_ufm/wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40118 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8787) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40036 \ram2e_ufm/un2_S_2_i_0_0_o3 ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40119 \ram2e_ufm/CKE_7s2_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40119 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0C4C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_116 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40014 \ram2e_ufm/CmdExecMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40067 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ( .A(A0), .B(B0), - .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_117 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40120 \ram2e_ufm/S_s_0_0_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40121 \ram2e_ufm/N_225_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40120 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0F0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40121 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_118 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40113 \ram2e_ufm/CKE_7_m1_0_0_o2_RNI7FOA1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40122 \ram2e_ufm/N_201_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40122 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_119 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40123 \ram2e_ufm/S_r_i_0_o2_RNIBAU51[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40124 \ram2e_ufm/un1_CKE75_0_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40123 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40124 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hD79B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_120 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40125 \ram2e_ufm/DQMH_4_iv_0_0_i_i_a3_0_a3 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40126 \ram2e_ufm/N_507_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40125 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h31F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40126 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCD05) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_121 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40127 \ram2e_ufm/Vout3_0_a3_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40128 \ram2e_ufm/RA_35_0_0_o2[11] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40127 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40128 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFCF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_122 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40129 \ram2e_ufm/nRWE_s_i_0_63_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40130 \ram2e_ufm/nCAS_s_i_0_m2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40129 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4FFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40130 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h37FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_123 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40131 \ram2e_ufm/wb_adr_RNO_3[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40019 \ram2e_ufm/wb_dati_7_0_0_a3_8[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40131 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_124 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40132 \ram2e_ufm/RA_35_0_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40035 \ram2e_ufm/RA_35_0_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40132 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_125 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40133 \ram2e_ufm/wb_adr_7_i_i_o2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40045 \ram2e_ufm/wb_dati_7_0_0_a3_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40133 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F70) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_126 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40134 \ram2e_ufm/wb_we_RNO_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40117 \ram2e_ufm/wb_adr_7_i_i_a3_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40134 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F07) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_127 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40117 \ram2e_ufm/un9_VOEEN_0_a2_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40046 \ram2e_ufm/RA_35_2_30_a3_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_128 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40135 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40136 \ram2e_ufm/wb_adr_RNO_4[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40135 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40136 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40080 \ram2e_ufm/BA_4[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40016 \ram2e_ufm/RA_35_2_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_130 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40083 \ram2e_ufm/N_187_i ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40088 \ram2e_ufm/wb_we_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_131 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40035 \ram2e_ufm/Ready3_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40137 \ram2e_ufm/wb_dati_7_0_0_0_a3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40137 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_132 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40138 \ram2e_ufm/RA_35_0_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40033 \ram2e_ufm/RA_35_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40138 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_133 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40035 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40084 \ram2e_ufm/SUM0_i_o2_2 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_134 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut4 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40114 \ram2e_ufm/RA_35_0_0_a3[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_135 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40022 \ram2e_ufm/S_r_i_0_o2_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40139 \ram2e_ufm/RA_35_2_0_a3_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40139 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_136 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40140 \ram2e_ufm/nRAS_s_i_0_o2 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40141 \ram2e_ufm/un1_nDOE_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40140 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5757) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40141 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_137 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40142 \ram2e_ufm/RDOE_i ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40084 \ram2e_ufm/LEDEN_RNI6G6M ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40142 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_138 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40007 VOEEN_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40007 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module SLICE_139 ( input B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40101 nVOE_pad_RNO( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40067 S_1( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_140 ( input B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40023 \ram2e_ufm/RA_35_0_0_a3_0[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/RA_35_0_0_a3[5] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_141 ( input B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40023 \ram2e_ufm/RDout_i_0_i_a3[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/N_263_i ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_142 ( input C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40136 \ram2e_ufm/CmdLEDGet_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/RDout_i_i_a3[4] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_143 ( input B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40023 \ram2e_ufm/RDout_i_0_i_a3[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/RDout_i_0_i_a3[7] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_144 ( input B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40023 \ram2e_ufm/RDout_i_0_i_a3[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40023 \ram2e_ufm/RDout_i_0_i_a3[6] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_145 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40033 \ram2e_ufm/wb_dati_7_0_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40143 \ram2e_ufm/wb_dati_7_0_0_o2_0[7] ( .A(A0), .B(B0), .C(GNDI), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40143 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_146 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40144 \ram2e_ufm/RA_35_0_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40035 \ram2e_ufm/Ready3_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40144 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_147 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); - wire GNDI; - - lut40027 \ram2e_ufm/RWBank_3_0_0_o3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40023 \ram2e_ufm/RDout_i_0_i_a3[5] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); - - xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); - - specify - (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD0) = (0:0:0,0:0:0); - (RD0 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD0, 0:0:0); - $width (negedge RD0, 0:0:0); - endspecify - -endmodule - -module xo2iobuf ( input I, T, output Z, PAD, input PADI ); - - IB INST1( .I(PADI), .O(Z)); - OBW INST2( .I(I), .T(T), .O(PAD)); -endmodule - -module LED ( input PADDO, output LED ); - - xo2iobuf0145 LED_pad( .I(PADDO), .PAD(LED)); - - specify - (PADDO => LED) = (0:0:0,0:0:0); - endspecify - -endmodule - -module xo2iobuf0145 ( input I, output PAD ); - - OB INST5( .I(I), .O(PAD)); -endmodule - -module C14M ( output PADDI, input C14M ); - - xo2iobuf0146 C14M_pad( .Z(PADDI), .PAD(C14M)); - - specify - (C14M => PADDI) = (0:0:0,0:0:0); - $width (posedge C14M, 0:0:0); - $width (negedge C14M, 0:0:0); - endspecify - -endmodule - -module xo2iobuf0146 ( output Z, input PAD ); - - IB INST1( .I(PAD), .O(Z)); -endmodule - -module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); - - xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7)); - - specify - (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD7) = (0:0:0,0:0:0); - (RD7 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD7, 0:0:0); - $width (negedge RD7, 0:0:0); - endspecify - -endmodule - -module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); - - xo2iobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6)); - - specify - (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD6) = (0:0:0,0:0:0); - (RD6 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD6, 0:0:0); - $width (negedge RD6, 0:0:0); - endspecify - -endmodule - -module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); - - xo2iobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5)); - - specify - (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD5) = (0:0:0,0:0:0); - (RD5 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD5, 0:0:0); - $width (negedge RD5, 0:0:0); - endspecify - -endmodule - -module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); - - xo2iobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4)); - - specify - (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD4) = (0:0:0,0:0:0); - (RD4 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD4, 0:0:0); - $width (negedge RD4, 0:0:0); - endspecify - -endmodule - -module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); - - xo2iobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3)); - - specify - (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD3) = (0:0:0,0:0:0); - (RD3 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD3, 0:0:0); - $width (negedge RD3, 0:0:0); - endspecify - -endmodule - -module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); - - xo2iobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2)); - - specify - (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD2) = (0:0:0,0:0:0); - (RD2 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD2, 0:0:0); - $width (negedge RD2, 0:0:0); - endspecify - -endmodule - -module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); - - xo2iobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1)); - - specify - (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD1) = (0:0:0,0:0:0); - (RD1 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD1, 0:0:0); - $width (negedge RD1, 0:0:0); - endspecify - -endmodule - -module DQMH ( input IOLDO, output DQMH ); - - xo2iobuf0145 DQMH_pad( .I(IOLDO), .PAD(DQMH)); - - specify - (IOLDO => DQMH) = (0:0:0,0:0:0); - endspecify - -endmodule - -module DQMH_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre DQMH_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module mfflsre ( input D0, SP, CK, LSR, output Q ); - - FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module DQML ( input IOLDO, output DQML ); - - xo2iobuf0145 DQML_pad( .I(IOLDO), .PAD(DQML)); - - specify - (IOLDO => DQML) = (0:0:0,0:0:0); - endspecify - -endmodule - -module DQML_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre DQML_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module RAout_11_ ( input IOLDO, output RAout11 ); - - xo2iobuf0145 \RAout_pad[11] ( .I(IOLDO), .PAD(RAout11)); - - specify - (IOLDO => RAout11) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_11__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module mfflsre0147 ( input D0, SP, CK, LSR, output Q ); - - FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module inverter ( input I, output Z ); - - INV INST1( .A(I), .Z(Z)); -endmodule - -module RAout_10_ ( input IOLDO, output RAout10 ); - - xo2iobuf0145 \RAout_pad[10] ( .I(IOLDO), .PAD(RAout10)); - - specify - (IOLDO => RAout10) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_10__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_9_ ( input IOLDO, output RAout9 ); - - xo2iobuf0145 \RAout_pad[9] ( .I(IOLDO), .PAD(RAout9)); - - specify - (IOLDO => RAout9) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_9__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_8_ ( input IOLDO, output RAout8 ); - - xo2iobuf0145 \RAout_pad[8] ( .I(IOLDO), .PAD(RAout8)); - - specify - (IOLDO => RAout8) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_8__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_7_ ( input IOLDO, output RAout7 ); - - xo2iobuf0145 \RAout_pad[7] ( .I(IOLDO), .PAD(RAout7)); - - specify - (IOLDO => RAout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_7__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_6_ ( input IOLDO, output RAout6 ); - - xo2iobuf0145 \RAout_pad[6] ( .I(IOLDO), .PAD(RAout6)); - - specify - (IOLDO => RAout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_6__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_5_ ( input IOLDO, output RAout5 ); - - xo2iobuf0145 \RAout_pad[5] ( .I(IOLDO), .PAD(RAout5)); - - specify - (IOLDO => RAout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_5__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_4_ ( input IOLDO, output RAout4 ); - - xo2iobuf0145 \RAout_pad[4] ( .I(IOLDO), .PAD(RAout4)); - - specify - (IOLDO => RAout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_4__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_3_ ( input IOLDO, output RAout3 ); - - xo2iobuf0145 \RAout_pad[3] ( .I(IOLDO), .PAD(RAout3)); - - specify - (IOLDO => RAout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_3__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_2_ ( input IOLDO, output RAout2 ); - - xo2iobuf0145 \RAout_pad[2] ( .I(IOLDO), .PAD(RAout2)); - - specify - (IOLDO => RAout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_2__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_1_ ( input IOLDO, output RAout1 ); - - xo2iobuf0145 \RAout_pad[1] ( .I(IOLDO), .PAD(RAout1)); - - specify - (IOLDO => RAout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_1__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_0_ ( input IOLDO, output RAout0 ); - - xo2iobuf0145 \RAout_pad[0] ( .I(IOLDO), .PAD(RAout0)); - - specify - (IOLDO => RAout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_0__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 \RAout_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module BA_1_ ( input IOLDO, output BA1 ); - - xo2iobuf0145 \BA_pad[1] ( .I(IOLDO), .PAD(BA1)); - - specify - (IOLDO => BA1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module BA_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0148 \BA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module mfflsre0148 ( input D0, SP, CK, LSR, output Q ); - - FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module BA_0_ ( input IOLDO, output BA0 ); - - xo2iobuf0145 \BA_pad[0] ( .I(IOLDO), .PAD(BA0)); - - specify - (IOLDO => BA0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module BA_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0148 \BA_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module nRWEout ( input IOLDO, output nRWEout ); - - xo2iobuf0145 nRWEout_pad( .I(IOLDO), .PAD(nRWEout)); - - specify - (IOLDO => nRWEout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRWEout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nRWEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nCASout ( input IOLDO, output nCASout ); - - xo2iobuf0145 nCASout_pad( .I(IOLDO), .PAD(nCASout)); - - specify - (IOLDO => nCASout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nCASout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nCASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nRASout ( input IOLDO, output nRASout ); - - xo2iobuf0145 nRASout_pad( .I(IOLDO), .PAD(nRASout)); - - specify - (IOLDO => nRASout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRASout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nRASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nCSout ( input PADDO, output nCSout ); - - xo2iobuf0145 nCSout_pad( .I(PADDO), .PAD(nCSout)); - - specify - (PADDO => nCSout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CKEout ( input IOLDO, output CKEout ); - - xo2iobuf0145 CKEout_pad( .I(IOLDO), .PAD(CKEout)); - - specify - (IOLDO => CKEout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CKEout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0147 CKEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nVOE ( input PADDO, output nVOE ); - - xo2iobuf0145 nVOE_pad( .I(PADDO), .PAD(nVOE)); - - specify - (PADDO => nVOE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_7_ ( input IOLDO, output Vout7 ); - - xo2iobuf0145 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7)); - - specify - (IOLDO => Vout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_6_ ( input IOLDO, output Vout6 ); - - xo2iobuf0145 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6)); - - specify - (IOLDO => Vout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_5_ ( input IOLDO, output Vout5 ); - - xo2iobuf0145 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5)); - - specify - (IOLDO => Vout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_4_ ( input IOLDO, output Vout4 ); - - xo2iobuf0145 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4)); - - specify - (IOLDO => Vout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_3_ ( input IOLDO, output Vout3 ); - - xo2iobuf0145 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3)); - - specify - (IOLDO => Vout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_2_ ( input IOLDO, output Vout2 ); - - xo2iobuf0145 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2)); - - specify - (IOLDO => Vout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_1_ ( input IOLDO, output Vout1 ); - - xo2iobuf0145 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1)); - - specify - (IOLDO => Vout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_0_ ( input IOLDO, output Vout0 ); - - xo2iobuf0145 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0)); - - specify - (IOLDO => Vout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0147 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module nDOE ( input PADDO, output nDOE ); - - xo2iobuf0145 nDOE_pad( .I(PADDO), .PAD(nDOE)); - - specify - (PADDO => nDOE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_7_ ( input PADDO, output Dout7 ); - - xo2iobuf0145 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); - - specify - (PADDO => Dout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_6_ ( input PADDO, output Dout6 ); - - xo2iobuf0145 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); - - specify - (PADDO => Dout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_5_ ( input PADDO, output Dout5 ); - - xo2iobuf0145 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); - - specify - (PADDO => Dout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_4_ ( input PADDO, output Dout4 ); - - xo2iobuf0145 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); - - specify - (PADDO => Dout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_3_ ( input PADDO, output Dout3 ); - - xo2iobuf0145 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); - - specify - (PADDO => Dout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_2_ ( input PADDO, output Dout2 ); - - xo2iobuf0145 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); - - specify - (PADDO => Dout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_1_ ( input PADDO, output Dout1 ); - - xo2iobuf0145 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); - - specify - (PADDO => Dout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_0_ ( input PADDO, output Dout0 ); - - xo2iobuf0145 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); - - specify - (PADDO => Dout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Din_7_ ( output PADDI, input Din7 ); - - xo2iobuf0146 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); - - specify - (Din7 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din7, 0:0:0); - $width (negedge Din7, 0:0:0); - endspecify - -endmodule - -module Din_6_ ( output PADDI, input Din6 ); - - xo2iobuf0146 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); - - specify - (Din6 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din6, 0:0:0); - $width (negedge Din6, 0:0:0); - endspecify - -endmodule - -module Din_5_ ( output PADDI, input Din5 ); - - xo2iobuf0146 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); - - specify - (Din5 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din5, 0:0:0); - $width (negedge Din5, 0:0:0); - endspecify - -endmodule - -module Din_4_ ( output PADDI, input Din4 ); - - xo2iobuf0146 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); - - specify - (Din4 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din4, 0:0:0); - $width (negedge Din4, 0:0:0); - endspecify - -endmodule - -module Din_3_ ( output PADDI, input Din3 ); - - xo2iobuf0146 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); - - specify - (Din3 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din3, 0:0:0); - $width (negedge Din3, 0:0:0); - endspecify - -endmodule - -module Din_2_ ( output PADDI, input Din2 ); - - xo2iobuf0146 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); - - specify - (Din2 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din2, 0:0:0); - $width (negedge Din2, 0:0:0); - endspecify - -endmodule - -module Din_1_ ( output PADDI, input Din1 ); - - xo2iobuf0146 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); - - specify - (Din1 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din1, 0:0:0); - $width (negedge Din1, 0:0:0); - endspecify - -endmodule - -module Din_0_ ( output PADDI, input Din0 ); - - xo2iobuf0146 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); - - specify - (Din0 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din0, 0:0:0); - $width (negedge Din0, 0:0:0); - endspecify - -endmodule - -module Ain_7_ ( output PADDI, input Ain7 ); - - xo2iobuf0146 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7)); - - specify - (Ain7 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain7, 0:0:0); - $width (negedge Ain7, 0:0:0); - endspecify - -endmodule - -module Ain_6_ ( output PADDI, input Ain6 ); - - xo2iobuf0146 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6)); - - specify - (Ain6 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain6, 0:0:0); - $width (negedge Ain6, 0:0:0); - endspecify - -endmodule - -module Ain_5_ ( output PADDI, input Ain5 ); - - xo2iobuf0146 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5)); - - specify - (Ain5 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain5, 0:0:0); - $width (negedge Ain5, 0:0:0); - endspecify - -endmodule - -module Ain_4_ ( output PADDI, input Ain4 ); - - xo2iobuf0146 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4)); - - specify - (Ain4 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain4, 0:0:0); - $width (negedge Ain4, 0:0:0); - endspecify - -endmodule - -module Ain_3_ ( output PADDI, input Ain3 ); - - xo2iobuf0146 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3)); - - specify - (Ain3 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain3, 0:0:0); - $width (negedge Ain3, 0:0:0); - endspecify - -endmodule - -module Ain_2_ ( output PADDI, input Ain2 ); - - xo2iobuf0146 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2)); - - specify - (Ain2 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain2, 0:0:0); - $width (negedge Ain2, 0:0:0); - endspecify - -endmodule - -module Ain_1_ ( output PADDI, input Ain1 ); - - xo2iobuf0146 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1)); - - specify - (Ain1 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain1, 0:0:0); - $width (negedge Ain1, 0:0:0); - endspecify - -endmodule - -module Ain_0_ ( output PADDI, input Ain0 ); - - xo2iobuf0146 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0)); - - specify - (Ain0 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain0, 0:0:0); - $width (negedge Ain0, 0:0:0); - endspecify - -endmodule - -module nC07X ( output PADDI, input nC07X ); - - xo2iobuf0146 nC07X_pad( .Z(PADDI), .PAD(nC07X)); - - specify - (nC07X => PADDI) = (0:0:0,0:0:0); - $width (posedge nC07X, 0:0:0); - $width (negedge nC07X, 0:0:0); - endspecify - -endmodule - -module nEN80 ( output PADDI, input nEN80 ); - - xo2iobuf0146 nEN80_pad( .Z(PADDI), .PAD(nEN80)); - - specify - (nEN80 => PADDI) = (0:0:0,0:0:0); - $width (posedge nEN80, 0:0:0); - $width (negedge nEN80, 0:0:0); - endspecify - -endmodule - -module nWE ( output PADDI, input nWE ); - - xo2iobuf0146 nWE_pad( .Z(PADDI), .PAD(nWE)); - - specify - (nWE => PADDI) = (0:0:0,0:0:0); - $width (posedge nWE, 0:0:0); - $width (negedge nWE, 0:0:0); - endspecify - -endmodule - -module PHI1 ( output PADDI, input PHI1 ); - - xo2iobuf0146 PHI1_pad( .Z(PADDI), .PAD(PHI1)); - - specify - (PHI1 => PADDI) = (0:0:0,0:0:0); - $width (posedge PHI1, 0:0:0); - $width (negedge PHI1, 0:0:0); - endspecify - -endmodule - -module PHI1_MGIOL ( input DI, CLK, output IN ); - wire VCCI, GNDI, DI_dly, CLK_dly; - - smuxlregsre PHI1r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), - .Q(IN)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IN) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module smuxlregsre ( input D0, SP, CK, LSR, output Q ); - - IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module ram2e_ufm_ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, - WBWEI, WBADRI0, WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, - WBADRI7, WBDATI0, WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, - WBDATI7, output WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, - WBDATO6, WBDATO7, WBACKO ); - wire VCCI, GNDI; - - EFB_B \ram2e_ufm/ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), - .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), - .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), - .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), - .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), - .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), - .WBDATO1(WBDATO1), .WBDATO2(WBDATO2), .WBDATO3(WBDATO3), .WBDATO4(WBDATO4), - .WBDATO5(WBDATO5), .WBDATO6(WBDATO6), .WBDATO7(WBDATO7), .WBACKO(WBACKO), - .WBCUFMIRQ(), .UFMSN(VCCI), .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), - .I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), - .I2C2SCLI(GNDI), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), - .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), - .SPISCKEN(), .SPIMISOI(GNDI), .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), - .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), - .SPIMCSN3(), .SPIMCSN4(), .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), - .SPICSNEN(), .SPISCSN(GNDI), .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), - .TCIC(GNDI), .TCINT(), .TCOC(), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), - .PLL1STBO(), .PLLWEO(), .PLLADRO0(), .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), - .PLLADRO4(), .PLLDATO0(), .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), - .PLLDATO4(), .PLLDATO5(), .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), - .PLL0DATI1(GNDI), .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), - .PLL0DATI5(GNDI), .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), - .PLL1DATI0(GNDI), .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), - .PLL1DATI4(GNDI), .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), - .PLL1ACKI(GNDI)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); -endmodule - -module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, - WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, - WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, - WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, - WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output - I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input - I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, - I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, - input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output - SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, - SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, - input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, - PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, - PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, - PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, - PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, - PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI ); - wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, - WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, - WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, - WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, - WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, - PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, - PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, - PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, - PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, - I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, - SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, - UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, - WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, - PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, - PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, - PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, - PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, - I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, - I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, - I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, - SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, - SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, - SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, - CFGWAKE_buf, CFGSTDBY_buf; - - EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), - .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), - .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), - .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), - .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), - .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), - .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), - .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), - .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), - .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), - .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), - .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), - .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), - .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), - .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), - .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), - .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), - .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), - .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), - .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), - .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), - .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), - .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), - .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), - .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), - .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), - .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), - .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), - .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), - .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), - .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), - .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), - .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), - .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), - .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), - .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), - .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), - .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), - .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), - .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), - .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), - .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf)); - defparam INST10.DEV_DENSITY = "640L"; - defparam INST10.EFB_I2C1 = "DISABLED"; - defparam INST10.EFB_I2C2 = "DISABLED"; - defparam INST10.EFB_SPI = "DISABLED"; - defparam INST10.EFB_TC = "DISABLED"; - defparam INST10.EFB_TC_PORTMODE = "WB"; - defparam INST10.EFB_UFM = "ENABLED"; - defparam INST10.EFB_WB_CLK_FREQ = "14.4"; - defparam INST10.GSR = "ENABLED"; - defparam INST10.I2C1_ADDRESSING = "7BIT"; - defparam INST10.I2C1_BUS_PERF = "100kHz"; - defparam INST10.I2C1_CLK_DIVIDER = 1; - defparam INST10.I2C1_GEN_CALL = "DISABLED"; - defparam INST10.I2C1_SLAVE_ADDR = "0b1000001"; - defparam INST10.I2C1_WAKEUP = "DISABLED"; - defparam INST10.I2C2_ADDRESSING = "7BIT"; - defparam INST10.I2C2_BUS_PERF = "100kHz"; - defparam INST10.I2C2_CLK_DIVIDER = 1; - defparam INST10.I2C2_GEN_CALL = "DISABLED"; - defparam INST10.I2C2_SLAVE_ADDR = "0b1000010"; - defparam INST10.I2C2_WAKEUP = "DISABLED"; - defparam INST10.SPI_CLK_DIVIDER = 1; - defparam INST10.SPI_CLK_INV = "DISABLED"; - defparam INST10.SPI_INTR_RXOVR = "DISABLED"; - defparam INST10.SPI_INTR_RXRDY = "DISABLED"; - defparam INST10.SPI_INTR_TXOVR = "DISABLED"; - defparam INST10.SPI_INTR_TXRDY = "DISABLED"; - defparam INST10.SPI_LSB_FIRST = "DISABLED"; - defparam INST10.SPI_MODE = "MASTER"; - defparam INST10.SPI_PHASE_ADJ = "DISABLED"; - defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED"; - defparam INST10.SPI_WAKEUP = "DISABLED"; - defparam INST10.TC_CCLK_SEL = 1; - defparam INST10.TC_ICAPTURE = "DISABLED"; - defparam INST10.TC_ICR_INT = "OFF"; - defparam INST10.TC_MODE = "CTCM"; - defparam INST10.TC_OCR_INT = "OFF"; - defparam INST10.TC_OCR_SET = 32767; - defparam INST10.TC_OC_MODE = "TOGGLE"; - defparam INST10.TC_OVERFLOW = "DISABLED"; - defparam INST10.TC_OV_INT = "OFF"; - defparam INST10.TC_RESETN = "ENABLED"; - defparam INST10.TC_SCLK_SEL = "PCLOCK"; - defparam INST10.TC_TOP_SEL = "OFF"; - defparam INST10.TC_TOP_SET = 65535; - defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED"; - defparam INST10.UFM_INIT_FILE_FORMAT = "HEX"; - defparam INST10.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem"; - defparam INST10.UFM_INIT_PAGES = 1; - defparam INST10.UFM_INIT_START_PAGE = 190; - EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), - .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), - .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), - .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), - .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), - .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), - .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), - .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), - .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), - .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), - .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), - .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), - .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), - .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), - .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), - .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), - .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), - .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), - .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), - .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), - .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), - .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), - .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), - .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), - .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), - .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), - .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), - .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), - .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), - .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), - .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), - .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), - .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), - .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), - .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), - .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), - .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), - .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), - .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), - .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), - .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), - .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), - .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), - .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), - .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), - .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), - .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), - .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), - .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), - .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), - .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), - .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), - .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), - .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), - .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), - .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), - .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), - .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), - .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), - .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), - .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), - .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), - .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), - .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), - .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), - .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), - .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), - .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), - .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), - .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), - .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), - .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), - .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), - .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), - .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), - .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), - .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), - .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), - .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), - .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), - .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), - .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), - .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), - .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), - .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), - .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), - .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), - .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), - .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), - .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), - .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), - .CFGSTDBYin(CFGSTDBY_buf)); -endmodule - -module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, - output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, - output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output - WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output - WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output - WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output - WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output - WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output - WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output - WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output - WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output - PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, - output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input - PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, - input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output - PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, - output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input - PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, - input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output - PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, - output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input - I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, - input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, - input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, - input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, - input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input - TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input - WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input - WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input - WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input - WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input - WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input - PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, - input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, - input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, - input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, - input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, - input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, - input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, - input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, - input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output - I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, - output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input - I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, - input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output - I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, - output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, - output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input - SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, - input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output - SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, - output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, - output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, - output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, - output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, - output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, - output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin ); - wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, - WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, - WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, - WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, - WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly; - - BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout)); - BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout)); - BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout)); - BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout)); - BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout)); - BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out)); - BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out)); - BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out)); - BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out)); - BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out)); - BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out)); - BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out)); - BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out)); - BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out)); - BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out)); - BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out)); - BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out)); - BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out)); - BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out)); - BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out)); - BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out)); - BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out)); - BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out)); - BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out)); - BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out)); - BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out)); - BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out)); - BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out)); - BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out)); - BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout)); - BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out)); - BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out)); - BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out)); - BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out)); - BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out)); - BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out)); - BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out)); - BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out)); - BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout)); - BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout)); - BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout)); - BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout)); - BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout)); - BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout)); - BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout)); - BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout)); - BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout)); - BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout)); - BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout)); - BUFBA TCIC_buf( .A(TCICin), .Z(TCICout)); - BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout)); - BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out)); - BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out)); - BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out)); - BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out)); - BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out)); - BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out)); - BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out)); - BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out)); - BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout)); - BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout)); - BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout)); - BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout)); - BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout)); - BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout)); - BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out)); - BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out)); - BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out)); - BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out)); - BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out)); - BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out)); - BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out)); - BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out)); - BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out)); - BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out)); - BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out)); - BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out)); - BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out)); - BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout)); - BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout)); - BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout)); - BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout)); - BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout)); - BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout)); - BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout)); - BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout)); - BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout)); - BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout)); - BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout)); - BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout)); - BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout)); - BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout)); - BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout)); - BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout)); - BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out)); - BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out)); - BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out)); - BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out)); - BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out)); - BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out)); - BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out)); - BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out)); - BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout)); - BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout)); - BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout)); - BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout)); - BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout)); - BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout)); - BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout)); - - specify - (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO2out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO3out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO4out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO5out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO6out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO7out) = (0:0:0,0:0:0); - (WBCLKIin => WBACKOout) = (0:0:0,0:0:0); - $setuphold - (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly); - $setuphold - (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly); - $setuphold - (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly); - $setuphold - (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly); - $setuphold - (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly); - $setuphold - (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly); - $setuphold - (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly); - $setuphold - (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly); - $setuphold - (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly); - $setuphold - (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly); - $setuphold - (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly); - $setuphold - (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly); - $setuphold - (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly); - $setuphold - (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly); - $setuphold - (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly); - $setuphold - (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly); - $setuphold - (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly); - $setuphold - (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly); - $setuphold - (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly); - $setuphold - (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly); - $width (posedge WBCLKIin, 0:0:0); - $width (negedge WBCLKIin, 0:0:0); - endspecify - -endmodule diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html deleted file mode 100644 index 40b807f..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html +++ /dev/null @@ -1,485 +0,0 @@ - -Project Summary - - -
    
-            Lattice Mapping Report File for Design Module 'RAM2E'
-
-
-
-Design Information
-
-Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
-     RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
-     RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
-     loud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
-     lpf -lpf //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
-     //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml 
-Target Vendor:  LATTICE
-Target Device:  LCMXO2-640HCTQFP100
-Target Performance:   4
-Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
-Mapped on:  12/28/23  23:23:28
-
-
-Design Summary
-   Number of registers:    122 out of   877 (14%)
-      PFU registers:           93 out of   640 (15%)
-      PIO registers:           29 out of   237 (12%)
-   Number of SLICEs:       148 out of   320 (46%)
-      SLICEs as Logic/ROM:    148 out of   320 (46%)
-      SLICEs as RAM:            0 out of   240 (0%)
-      SLICEs as Carry:          9 out of   320 (3%)
-   Number of LUT4s:        296 out of   640 (46%)
-      Number used as logic LUTs:        278
-      Number used as distributed RAM:     0
-      Number used as ripple logic:       18
-      Number used as shift registers:     0
-   Number of PIO sites used: 69 + 4(JTAG) out of 79 (92%)
-   Number of block RAMs:  0 out of 2 (0%)
-   Number of GSRs:        0 out of 1 (0%)
-   EFB used :        Yes
-   JTAG used :       No
-   Readback used :   No
-   Oscillator used : No
-   Startup used :    No
-   POR :             On
-   Bandgap :         On
-   Number of Power Controller:  0 out of 1 (0%)
-   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
-   Number of DCCA:  0 out of 8 (0%)
-   Number of DCMA:  0 out of 2 (0%)
-   Notes:-
-      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
-     distributed RAMs) + 2*(Number of ripple logic)
-      2. Number of logic LUT4s does not include count of distributed RAM and
-     ripple logic.
-   Number of clocks:  1
-     Net C14M_c: 89 loads, 73 rising, 16 falling (Driver: PIO C14M )
-   Number of Clock Enables:  14
-     Net N_225_i: 2 loads, 0 LSLICEs
-     Net N_201_i: 2 loads, 0 LSLICEs
-     Net N_187_i: 11 loads, 11 LSLICEs
-     Net ram2e_ufm/wb_adr_0_sqmuxa_1_i: 1 loads, 1 LSLICEs
-     Net RC12: 2 loads, 2 LSLICEs
-     Net ram2e_ufm/CmdBitbangMXO2_RNINSM62: 8 loads, 8 LSLICEs
-
-     Net ram2e_ufm/wb_we_RNO_0: 1 loads, 1 LSLICEs
-     Net N_185_i: 2 loads, 2 LSLICEs
-     Net ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0]: 1 loads, 1 LSLICEs
-     Net ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0]: 4 loads, 4 LSLICEs
-     Net ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0]: 1 loads, 1 LSLICEs
-     Net N_126: 6 loads, 6 LSLICEs
-     Net un9_VOEEN_0_a2_0_a3_0_a3: 1 loads, 1 LSLICEs
-     Net Vout3: 8 loads, 0 LSLICEs
-   Number of LSRs:  7
-     Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
-     Net BA_0_sqmuxa: 2 loads, 0 LSLICEs
-     Net S[2]: 1 loads, 1 LSLICEs
-     Net ram2e_ufm/wb_rst: 1 loads, 0 LSLICEs
-     Net ram2e_ufm/wb_rst16_i: 1 loads, 1 LSLICEs
-     Net N_1080_0: 1 loads, 1 LSLICEs
-     Net N_1078_0: 1 loads, 1 LSLICEs
-   Number of nets driven by tri-state buffers:  0
-   Top 10 highest fanout non-clock nets:
-     Net S[2]: 50 loads
-     Net S[3]: 45 loads
-     Net S[0]: 37 loads
-     Net S[1]: 34 loads
-     Net FS[12]: 24 loads
-     Net FS[11]: 22 loads
-     Net FS[10]: 19 loads
-     Net FS[13]: 19 loads
-     Net FS[9]: 19 loads
-     Net FS[8]: 18 loads
-
-
-
-
-   Number of warnings:  3
-   Number of errors:    0
-     
-
-
-
-
-Design Errors/Warnings
-
-WARNING - map: //Mac/iCloud/Repos/ram2e/CPLD/RAM2E-LCMXO2.lpf(93): Semantic
-     error in "IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ;": Port
-     "nWE80" does not exist in the design. This preference has been disabled.
-WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
-     temporarily disable certain features of the device including Power
-     Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
-     Functionality is restored after the Flash Memory (UFM/Configuration)
-     Interface is disabled using Disable Configuration Interface command 0x26
-     followed by Bypass command 0xFF. 
-WARNING - map: IO buffer missing for top level port nWE80...logic will be
-     discarded.
-
-
-
-IO (PIO) Attributes
-
-+---------------------+-----------+-----------+------------+
-| IO Name             | Direction | Levelmode | IO         |
-
-|                     |           |  IO_TYPE  | Register   |
-+---------------------+-----------+-----------+------------+
-| RD[0]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| LED                 | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| C14M                | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[7]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[6]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[5]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[4]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[3]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[2]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| RD[1]               | BIDIR     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| DQML                | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[11]           | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[10]           | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[9]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[8]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[7]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[6]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[5]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[4]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[3]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[2]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[1]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| RAout[0]            | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| BA[1]               | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| BA[0]               | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nRWEout             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-
-| nCASout             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nRASout             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nCSout              | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| CKEout              | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nVOE                | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Vout[7]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[6]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[5]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[4]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[3]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[2]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[1]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| Vout[0]             | OUTPUT    | LVCMOS33  | OUT        |
-+---------------------+-----------+-----------+------------+
-| nDOE                | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[7]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[6]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[5]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[4]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[3]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[2]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[1]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Dout[0]             | OUTPUT    | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[7]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[6]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[5]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[4]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[3]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[2]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-
-| Din[1]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Din[0]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[7]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[6]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[5]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[4]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[3]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[2]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[1]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| Ain[0]              | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| nC07X               | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| nEN80               | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| nWE                 | INPUT     | LVCMOS33  |            |
-+---------------------+-----------+-----------+------------+
-| PHI1                | INPUT     | LVCMOS33  | IN         |
-+---------------------+-----------+-----------+------------+
-
-
-
-Removed logic
-
-Block GSR_INST undriven or does not drive anything - clipped.
-Block ram2e_ufm/VCC undriven or does not drive anything - clipped.
-Block ram2e_ufm/GND undriven or does not drive anything - clipped.
-Signal CKEout.CN was merged into signal C14M_c
-Signal ram2e_ufm/ufmefb/VCC undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/GND undriven or does not drive anything - clipped.
-Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
-Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/CFGWAKE undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/wbc_ufm_irq undriven or does not drive anything -
-     clipped.
-Signal ram2e_ufm/ufmefb/TCOC undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/TCINT undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIIRQO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPICSNEN undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
-
-Signal ram2e_ufm/ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
-     
-Signal ram2e_ufm/ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
-     
-Signal ram2e_ufm/ufmefb/SPIMISOO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPISCKEN undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/SPISCKO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C2SDAOEN undriven or does not drive anything -
-     clipped.
-Signal ram2e_ufm/ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C2SCLOEN undriven or does not drive anything -
-     clipped.
-Signal ram2e_ufm/ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C1SDAOEN undriven or does not drive anything -
-     clipped.
-Signal ram2e_ufm/ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/I2C1SCLOEN undriven or does not drive anything -
-     clipped.
-Signal ram2e_ufm/ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLWEO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLL1STBO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLL0STBO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLRSTO undriven or does not drive anything - clipped.
-Signal ram2e_ufm/ufmefb/PLLCLKO undriven or does not drive anything - clipped.
-Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
-Signal N_1 undriven or does not drive anything - clipped.
-Block nCASout.CN was optimized away.
-Block ram2e_ufm/ufmefb/VCC was optimized away.
-Block ram2e_ufm/ufmefb/GND was optimized away.
-
-     
-
-
-
-Embedded Functional Block Connection Summary
-
-   Desired WISHBONE clock frequency: 14.4 MHz
-   Clock source:                     C14M_c
-   Reset source:                     ram2e_ufm/wb_rst
-   Functions mode:
-      I2C #1 (Primary) Function:     DISABLED
-
-      I2C #2 (Secondary) Function:   DISABLED
-      SPI Function:                  DISABLED
-      Timer/Counter Function:        DISABLED
-      Timer/Counter Mode:            WB
-      UFM Connection:                ENABLED
-      PLL0 Connection:               DISABLED
-      PLL1 Connection:               DISABLED
-   I2C Function Summary:
-   --------------------
-      None
-   SPI Function Summary:
-   --------------------
-      None
-   Timer/Counter Function Summary:
-   ------------------------------
-      None
-   UFM Function Summary:
-   --------------------
-      UFM Utilization:        General Purpose Flash Memory
-      Initialized UFM Pages:  1 Pages (1*128 Bits)
-      Available General
-      Purpose Flash Memory:   191 Pages (191*128 Bits)
-
-           EBR Blocks with Unique
-      Initialization Data:    0
-
-           WID		EBR Instance
-      ---		------------
-
-
-
-
-ASIC Components
----------------
-
-Instance Name: ram2e_ufm/ufmefb/EFBInst_0
-         Type: EFB
-
-
-
-Run Time and Memory Usage
--------------------------
-
-   Total CPU Time: 0 secs  
-   Total REAL Time: 0 secs  
-   Peak Memory Usage: 59 MB
-        
-
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-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-     Copyright (c) 1995 AT&T Corp.   All rights reserved.
-     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-     Copyright (c) 2001 Agere Systems   All rights reserved.
-     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
-     reserved.
-
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    - - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html deleted file mode 100644 index 8d4838a..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html +++ /dev/null @@ -1,350 +0,0 @@ - -PAD Specification File - - -
    PAD Specification File
-***************************
-
-PART TYPE:        LCMXO2-640HC
-Performance Grade:      4
-PACKAGE:          TQFP100
-Package Status:                     Final          Version 1.39
-
-Thu Dec 28 23:23:38 2023
-
-Pinout by Port Name:
-+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
-| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                                 |
-+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
-| Ain[0]    | 3/3      | LVCMOS33_IN   | PL2C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[1]    | 2/3      | LVCMOS33_IN   | PL2B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[2]    | 7/3      | LVCMOS33_IN   | PL3A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[3]    | 4/3      | LVCMOS33_IN   | PL2D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[4]    | 78/0     | LVCMOS33_IN   | PT11A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[5]    | 84/0     | LVCMOS33_IN   | PT10A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[6]    | 86/0     | LVCMOS33_IN   | PT9C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Ain[7]    | 8/3      | LVCMOS33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| BA[0]     | 58/1     | LVCMOS33_OUT  | PR6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| BA[1]     | 60/1     | LVCMOS33_OUT  | PR6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| C14M      | 62/1     | LVCMOS33_IN   | PR5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| CKEout    | 53/1     | LVCMOS33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| DQMH      | 49/2     | LVCMOS33_OUT  | PB14D |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| DQML      | 48/2     | LVCMOS33_OUT  | PB14C |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Din[0]    | 96/0     | LVCMOS33_IN   | PT6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[1]    | 97/0     | LVCMOS33_IN   | PT6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[2]    | 98/0     | LVCMOS33_IN   | PT6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[3]    | 9/3      | LVCMOS33_IN   | PL3C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[4]    | 1/3      | LVCMOS33_IN   | PL2A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[5]    | 99/0     | LVCMOS33_IN   | PT6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[6]    | 88/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Din[7]    | 87/0     | LVCMOS33_IN   | PT9B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| LED       | 35/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| PHI1      | 85/0     | LVCMOS33_IN   | PT9D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| RAout[0]  | 66/1     | LVCMOS33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[10] | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[11] | 59/1     | LVCMOS33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[1]  | 68/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[2]  | 70/1     | LVCMOS33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[3]  | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[4]  | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[5]  | 71/1     | LVCMOS33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[6]  | 69/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[7]  | 67/1     | LVCMOS33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[8]  | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RAout[9]  | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| RD[0]     | 36/2     | LVCMOS33_BIDI | PB10A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[1]     | 37/2     | LVCMOS33_BIDI | PB10B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[2]     | 38/2     | LVCMOS33_BIDI | PB10C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[3]     | 39/2     | LVCMOS33_BIDI | PB10D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[4]     | 40/2     | LVCMOS33_BIDI | PB12A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[5]     | 41/2     | LVCMOS33_BIDI | PB12B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[6]     | 42/2     | LVCMOS33_BIDI | PB12C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| RD[7]     | 43/2     | LVCMOS33_BIDI | PB12D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
-| Vout[0]   | 18/3     | LVCMOS33_OUT  | PL6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[1]   | 15/3     | LVCMOS33_OUT  | PL5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[2]   | 17/3     | LVCMOS33_OUT  | PL6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[3]   | 13/3     | LVCMOS33_OUT  | PL5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[4]   | 19/3     | LVCMOS33_OUT  | PL6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[5]   | 16/3     | LVCMOS33_OUT  | PL6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[6]   | 14/3     | LVCMOS33_OUT  | PL5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| Vout[7]   | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nC07X     | 34/2     | LVCMOS33_IN   | PB6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nCASout   | 52/1     | LVCMOS33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nCSout    | 57/1     | LVCMOS33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nDOE      | 20/3     | LVCMOS33_OUT  | PL7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nEN80     | 82/0     | LVCMOS33_IN   | PT10C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-| nRASout   | 54/1     | LVCMOS33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nRWEout   | 51/1     | LVCMOS33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nVOE      | 10/3     | LVCMOS33_OUT  | PL3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
-| nWE       | 29/2     | LVCMOS33_IN   | PB4C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
-+-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
-
-Vccio by Bank:
-+------+-------+
-| Bank | Vccio |
-+------+-------+
-| 0    | 3.3V  |
-| 1    | 3.3V  |
-| 2    | 3.3V  |
-| 3    | 3.3V  |
-+------+-------+
-
-
-Vref by Bank:
-+------+-----+-----------------+---------+
-| Vref | Pin | Bank # / Vref # | Load(s) |
-+------+-----+-----------------+---------+
-+------+-----+-----------------+---------+
-
-Pinout by Pin Number:
-+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
-| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
-+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
-| 1/3      | Din[4]                | LOCATED    | LVCMOS33_IN   | PL2A  |               |           |           |
-| 2/3      | Ain[1]                | LOCATED    | LVCMOS33_IN   | PL2B  |               |           |           |
-| 3/3      | Ain[0]                | LOCATED    | LVCMOS33_IN   | PL2C  | PCLKT3_2      |           |           |
-| 4/3      | Ain[3]                | LOCATED    | LVCMOS33_IN   | PL2D  | PCLKC3_2      |           |           |
-| 7/3      | Ain[2]                | LOCATED    | LVCMOS33_IN   | PL3A  |               |           |           |
-| 8/3      | Ain[7]                | LOCATED    | LVCMOS33_IN   | PL3B  |               |           |           |
-| 9/3      | Din[3]                | LOCATED    | LVCMOS33_IN   | PL3C  |               |           |           |
-| 10/3     | nVOE                  | LOCATED    | LVCMOS33_OUT  | PL3D  |               |           |           |
-| 12/3     | Vout[7]               | LOCATED    | LVCMOS33_OUT  | PL5A  | PCLKT3_1      |           |           |
-| 13/3     | Vout[3]               | LOCATED    | LVCMOS33_OUT  | PL5B  | PCLKC3_1      |           |           |
-| 14/3     | Vout[6]               | LOCATED    | LVCMOS33_OUT  | PL5C  |               |           |           |
-| 15/3     | Vout[1]               | LOCATED    | LVCMOS33_OUT  | PL5D  |               |           |           |
-| 16/3     | Vout[5]               | LOCATED    | LVCMOS33_OUT  | PL6A  |               |           |           |
-| 17/3     | Vout[2]               | LOCATED    | LVCMOS33_OUT  | PL6B  |               |           |           |
-| 18/3     | Vout[0]               | LOCATED    | LVCMOS33_OUT  | PL6C  |               |           |           |
-| 19/3     | Vout[4]               | LOCATED    | LVCMOS33_OUT  | PL6D  |               |           |           |
-| 20/3     | nDOE                  | LOCATED    | LVCMOS33_OUT  | PL7A  | PCLKT3_0      |           |           |
-| 21/3     | Dout[5]               | LOCATED    | LVCMOS33_OUT  | PL7B  | PCLKC3_0      |           |           |
-| 24/3     | Dout[4]               | LOCATED    | LVCMOS33_OUT  | PL7C  |               |           |           |
-| 25/3     | Dout[2]               | LOCATED    | LVCMOS33_OUT  | PL7D  |               |           |           |
-| 27/2     | Dout[1]               | LOCATED    | LVCMOS33_OUT  | PB4A  | CSSPIN        |           |           |
-| 28/2     | Dout[3]               | LOCATED    | LVCMOS33_OUT  | PB4B  |               |           |           |
-| 29/2     | nWE                   | LOCATED    | LVCMOS33_IN   | PB4C  |               |           |           |
-| 30/2     | Dout[0]               | LOCATED    | LVCMOS33_OUT  | PB4D  |               |           |           |
-| 31/2     | Dout[6]               | LOCATED    | LVCMOS33_OUT  | PB6A  | MCLK/CCLK     |           |           |
-| 32/2     | Dout[7]               | LOCATED    | LVCMOS33_OUT  | PB6B  | SO/SPISO      |           |           |
-| 34/2     | nC07X                 | LOCATED    | LVCMOS33_IN   | PB6C  | PCLKT2_0      |           |           |
-| 35/2     | LED                   | LOCATED    | LVCMOS33_OUT  | PB6D  | PCLKC2_0      |           |           |
-| 36/2     | RD[0]                 | LOCATED    | LVCMOS33_BIDI | PB10A |               |           |           |
-| 37/2     | RD[1]                 | LOCATED    | LVCMOS33_BIDI | PB10B |               |           |           |
-| 38/2     | RD[2]                 | LOCATED    | LVCMOS33_BIDI | PB10C | PCLKT2_1      |           |           |
-| 39/2     | RD[3]                 | LOCATED    | LVCMOS33_BIDI | PB10D | PCLKC2_1      |           |           |
-| 40/2     | RD[4]                 | LOCATED    | LVCMOS33_BIDI | PB12A |               |           |           |
-| 41/2     | RD[5]                 | LOCATED    | LVCMOS33_BIDI | PB12B |               |           |           |
-| 42/2     | RD[6]                 | LOCATED    | LVCMOS33_BIDI | PB12C |               |           |           |
-| 43/2     | RD[7]                 | LOCATED    | LVCMOS33_BIDI | PB12D |               |           |           |
-| 45/2     |     unused, PULL:DOWN |            |               | PB14A |               |           |           |
-| 47/2     |     unused, PULL:DOWN |            |               | PB14B |               |           |           |
-| 48/2     | DQML                  | LOCATED    | LVCMOS33_OUT  | PB14C | SN            |           |           |
-| 49/2     | DQMH                  | LOCATED    | LVCMOS33_OUT  | PB14D | SI/SISPI      |           |           |
-| 51/1     | nRWEout               | LOCATED    | LVCMOS33_OUT  | PR7D  |               |           |           |
-| 52/1     | nCASout               | LOCATED    | LVCMOS33_OUT  | PR7C  |               |           |           |
-| 53/1     | CKEout                | LOCATED    | LVCMOS33_OUT  | PR7B  |               |           |           |
-| 54/1     | nRASout               | LOCATED    | LVCMOS33_OUT  | PR7A  |               |           |           |
-| 57/1     | nCSout                | LOCATED    | LVCMOS33_OUT  | PR6D  |               |           |           |
-| 58/1     | BA[0]                 | LOCATED    | LVCMOS33_OUT  | PR6C  |               |           |           |
-| 59/1     | RAout[11]             | LOCATED    | LVCMOS33_OUT  | PR6B  |               |           |           |
-| 60/1     | BA[1]                 | LOCATED    | LVCMOS33_OUT  | PR6A  |               |           |           |
-| 62/1     | C14M                  | LOCATED    | LVCMOS33_IN   | PR5D  | PCLKC1_0      |           |           |
-| 63/1     | RAout[9]              | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0      |           |           |
-| 64/1     | RAout[10]             | LOCATED    | LVCMOS33_OUT  | PR5B  |               |           |           |
-| 65/1     | RAout[8]              | LOCATED    | LVCMOS33_OUT  | PR5A  |               |           |           |
-| 66/1     | RAout[0]              | LOCATED    | LVCMOS33_OUT  | PR3D  |               |           |           |
-| 67/1     | RAout[7]              | LOCATED    | LVCMOS33_OUT  | PR3C  |               |           |           |
-| 68/1     | RAout[1]              | LOCATED    | LVCMOS33_OUT  | PR3B  |               |           |           |
-| 69/1     | RAout[6]              | LOCATED    | LVCMOS33_OUT  | PR3A  |               |           |           |
-| 70/1     | RAout[2]              | LOCATED    | LVCMOS33_OUT  | PR2D  |               |           |           |
-| 71/1     | RAout[5]              | LOCATED    | LVCMOS33_OUT  | PR2C  |               |           |           |
-| 74/1     | RAout[3]              | LOCATED    | LVCMOS33_OUT  | PR2B  |               |           |           |
-| 75/1     | RAout[4]              | LOCATED    | LVCMOS33_OUT  | PR2A  |               |           |           |
-| 76/0     |     unused, PULL:DOWN |            |               | PT11D | DONE          |           |           |
-| 77/0     |     unused, PULL:DOWN |            |               | PT11C | INITN         |           |           |
-| 78/0     | Ain[4]                | LOCATED    | LVCMOS33_IN   | PT11A |               |           |           |
-| 81/0     |     unused, PULL:DOWN |            |               | PT10D | PROGRAMN      |           |           |
-| 82/0     | nEN80                 | LOCATED    | LVCMOS33_IN   | PT10C | JTAGENB       |           |           |
-| 83/0     |     unused, PULL:DOWN |            |               | PT10B |               |           |           |
-| 84/0     | Ain[5]                | LOCATED    | LVCMOS33_IN   | PT10A |               |           |           |
-| 85/0     | PHI1                  | LOCATED    | LVCMOS33_IN   | PT9D  | SDA/PCLKC0_0  |           |           |
-| 86/0     | Ain[6]                | LOCATED    | LVCMOS33_IN   | PT9C  | SCL/PCLKT0_0  |           |           |
-| 87/0     | Din[7]                | LOCATED    | LVCMOS33_IN   | PT9B  | PCLKC0_1      |           |           |
-| 88/0     | Din[6]                | LOCATED    | LVCMOS33_IN   | PT9A  | PCLKT0_1      |           |           |
-| 90/0     | Reserved: sysCONFIG   |            |               | PT7D  | TMS           |           |           |
-| 91/0     | Reserved: sysCONFIG   |            |               | PT7C  | TCK           |           |           |
-| 94/0     | Reserved: sysCONFIG   |            |               | PT7B  | TDI           |           |           |
-| 95/0     | Reserved: sysCONFIG   |            |               | PT7A  | TDO           |           |           |
-| 96/0     | Din[0]                | LOCATED    | LVCMOS33_IN   | PT6D  |               |           |           |
-| 97/0     | Din[1]                | LOCATED    | LVCMOS33_IN   | PT6C  |               |           |           |
-| 98/0     | Din[2]                | LOCATED    | LVCMOS33_IN   | PT6B  |               |           |           |
-| 99/0     | Din[5]                | LOCATED    | LVCMOS33_IN   | PT6A  |               |           |           |
-| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
-+----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
-
-sysCONFIG Pins:
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-| PT7D     | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
-| PT7C     | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
-| PT7B     | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
-| PT7A     | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
-+----------+--------------------+--------------------+----------+-------------+-------------------+
-
-Dedicated sysCONFIG Pins:
-
-
-List of All Pins' Locate Preferences Based on Final Placement After PAR 
-to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
-
-LOCATE  COMP  "Ain[0]"  SITE  "3";
-LOCATE  COMP  "Ain[1]"  SITE  "2";
-LOCATE  COMP  "Ain[2]"  SITE  "7";
-LOCATE  COMP  "Ain[3]"  SITE  "4";
-LOCATE  COMP  "Ain[4]"  SITE  "78";
-LOCATE  COMP  "Ain[5]"  SITE  "84";
-LOCATE  COMP  "Ain[6]"  SITE  "86";
-LOCATE  COMP  "Ain[7]"  SITE  "8";
-LOCATE  COMP  "BA[0]"  SITE  "58";
-LOCATE  COMP  "BA[1]"  SITE  "60";
-LOCATE  COMP  "C14M"  SITE  "62";
-LOCATE  COMP  "CKEout"  SITE  "53";
-LOCATE  COMP  "DQMH"  SITE  "49";
-LOCATE  COMP  "DQML"  SITE  "48";
-LOCATE  COMP  "Din[0]"  SITE  "96";
-LOCATE  COMP  "Din[1]"  SITE  "97";
-LOCATE  COMP  "Din[2]"  SITE  "98";
-LOCATE  COMP  "Din[3]"  SITE  "9";
-LOCATE  COMP  "Din[4]"  SITE  "1";
-LOCATE  COMP  "Din[5]"  SITE  "99";
-LOCATE  COMP  "Din[6]"  SITE  "88";
-LOCATE  COMP  "Din[7]"  SITE  "87";
-LOCATE  COMP  "Dout[0]"  SITE  "30";
-LOCATE  COMP  "Dout[1]"  SITE  "27";
-LOCATE  COMP  "Dout[2]"  SITE  "25";
-LOCATE  COMP  "Dout[3]"  SITE  "28";
-LOCATE  COMP  "Dout[4]"  SITE  "24";
-LOCATE  COMP  "Dout[5]"  SITE  "21";
-LOCATE  COMP  "Dout[6]"  SITE  "31";
-LOCATE  COMP  "Dout[7]"  SITE  "32";
-LOCATE  COMP  "LED"  SITE  "35";
-LOCATE  COMP  "PHI1"  SITE  "85";
-LOCATE  COMP  "RAout[0]"  SITE  "66";
-LOCATE  COMP  "RAout[10]"  SITE  "64";
-LOCATE  COMP  "RAout[11]"  SITE  "59";
-LOCATE  COMP  "RAout[1]"  SITE  "68";
-LOCATE  COMP  "RAout[2]"  SITE  "70";
-LOCATE  COMP  "RAout[3]"  SITE  "74";
-LOCATE  COMP  "RAout[4]"  SITE  "75";
-LOCATE  COMP  "RAout[5]"  SITE  "71";
-LOCATE  COMP  "RAout[6]"  SITE  "69";
-LOCATE  COMP  "RAout[7]"  SITE  "67";
-LOCATE  COMP  "RAout[8]"  SITE  "65";
-LOCATE  COMP  "RAout[9]"  SITE  "63";
-LOCATE  COMP  "RD[0]"  SITE  "36";
-LOCATE  COMP  "RD[1]"  SITE  "37";
-LOCATE  COMP  "RD[2]"  SITE  "38";
-LOCATE  COMP  "RD[3]"  SITE  "39";
-LOCATE  COMP  "RD[4]"  SITE  "40";
-LOCATE  COMP  "RD[5]"  SITE  "41";
-LOCATE  COMP  "RD[6]"  SITE  "42";
-LOCATE  COMP  "RD[7]"  SITE  "43";
-LOCATE  COMP  "Vout[0]"  SITE  "18";
-LOCATE  COMP  "Vout[1]"  SITE  "15";
-LOCATE  COMP  "Vout[2]"  SITE  "17";
-LOCATE  COMP  "Vout[3]"  SITE  "13";
-LOCATE  COMP  "Vout[4]"  SITE  "19";
-LOCATE  COMP  "Vout[5]"  SITE  "16";
-LOCATE  COMP  "Vout[6]"  SITE  "14";
-LOCATE  COMP  "Vout[7]"  SITE  "12";
-LOCATE  COMP  "nC07X"  SITE  "34";
-LOCATE  COMP  "nCASout"  SITE  "52";
-LOCATE  COMP  "nCSout"  SITE  "57";
-LOCATE  COMP  "nDOE"  SITE  "20";
-LOCATE  COMP  "nEN80"  SITE  "82";
-LOCATE  COMP  "nRASout"  SITE  "54";
-LOCATE  COMP  "nRWEout"  SITE  "51";
-LOCATE  COMP  "nVOE"  SITE  "10";
-LOCATE  COMP  "nWE"  SITE  "29";
-
-
-
-
-
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Dec 28 23:23:41 2023
-
-
-
-
-
    
-
    
-
    
-
    
-
    
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-
    
-
    
-
    
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-
    
-
    
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-
    
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-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
-
    
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-
    - - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html deleted file mode 100644 index b47cccb..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html +++ /dev/null @@ -1,298 +0,0 @@ - -Place & Route Report - - -
    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-Thu Dec 28 23:23:31 2023
-
-C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
-RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
-RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset
-//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml
-
-
-Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
-
-Cost Table Summary
-Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
-Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
-----------   --------     -----        ------       -----------  -----------  ----         ------
-5_1   *      0            57.938       0            0.379        0            13           Completed
-* : Design saved.
-
-Total (real) run time for 1-seed: 13 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Lattice Place and Route Report for Design "RAM2E_LCMXO2_640HC_impl1_map.ncd"
-Thu Dec 28 23:23:31 2023
-
-
-Best Par Run
-PAR: Place And Route Diamond (64-bit) 3.12.1.454.
-Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
-Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
-Placement level-cost: 5-1.
-Routing Iterations: 6
-
-Loading design for application par from file RAM2E_LCMXO2_640HC_impl1_map.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-License checked out.
-
-
-Ignore Preference Error(s):  True
-
-Device utilization summary:
-
-   PIO (prelim)   69+4(JTAG)/80      91% used
-                  69+4(JTAG)/79      92% bonded
-   IOLOGIC           29/80           36% used
-
-   SLICE            148/320          46% used
-
-   EFB                1/1           100% used
-
-
-Number of Signals: 459
-Number of Connections: 1330
-
-Pin Constraint Summary:
-   69 out of 69 pins locked (100% locked).
-
-The following 1 signal is selected to use the primary clock routing resources:
-    C14M_c (driver: C14M, clk load #: 89)
-
-WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
-
-The following 1 signal is selected to use the secondary clock routing resources:
-    N_187_i (driver: ram2e_ufm/SLICE_130, clk load #: 0, sr load #: 0, ce load #: 11)
-
-No signal is selected as Global Set/Reset.
-Starting Placer Phase 0.
-...........
-Finished Placer Phase 0.  REAL time: 0 secs 
-
-Starting Placer Phase 1.
-....................
-Placer score = 69810.
-Finished Placer Phase 1.  REAL time: 7 secs 
-
-Starting Placer Phase 2.
-.
-Placer score =  69262
-Finished Placer Phase 2.  REAL time: 7 secs 
-
-
-
-Clock Report
-
-Global Clock Resources:
-  CLK_PIN    : 0 out of 8 (0%)
-  General PIO: 1 out of 80 (1%)
-  DCM        : 0 out of 2 (0%)
-  DCC        : 0 out of 8 (0%)
-
-Global Clocks:
-  PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 89
-  SECONDARY "N_187_i" from F1 on comp "ram2e_ufm/SLICE_130" on site "R6C8B", clk load = 0, ce load = 11, sr load = 0
-
-  PRIMARY  : 1 out of 8 (12%)
-  SECONDARY: 1 out of 8 (12%)
-
-
-
-
-I/O Usage Summary (final):
-   69 + 4(JTAG) out of 80 (91.3%) PIO sites used.
-   69 + 4(JTAG) out of 79 (92.4%) bonded PIO sites used.
-   Number of PIO comps: 69; differential: 0.
-   Number of Vref pins used: 0.
-
-I/O Bank Usage Summary:
-+----------+----------------+------------+-----------+
-| I/O Bank | Usage          | Bank Vccio | Bank Vref |
-+----------+----------------+------------+-----------+
-| 0        | 11 / 19 ( 57%) | 3.3V       | -         |
-| 1        | 20 / 20 (100%) | 3.3V       | -         |
-| 2        | 18 / 20 ( 90%) | 3.3V       | -         |
-| 3        | 20 / 20 (100%) | 3.3V       | -         |
-+----------+----------------+------------+-----------+
-
-Total placer CPU time: 6 secs 
-
-Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
-
-0 connections routed; 1330 unrouted.
-Starting router resource preassignment
-WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
-
-Completed router resource preassignment. Real time: 11 secs 
-
-Start NBR router at 23:23:42 12/28/23
-
-*****************************************************************
-Info: NBR allows conflicts(one node used by more than one signal)
-      in the earlier iterations. In each iteration, it tries to  
-      solve the conflicts while keeping the critical connections 
-      routed as short as possible. The routing process is said to
-      be completed when no conflicts exist and all connections   
-      are routed.                                                
-Note: NBR uses a different method to calculate timing slacks. The
-      worst slack and total negative slack may not be the same as
-      that in TRCE report. You should always run TRCE to verify  
-      your design.                                               
-*****************************************************************
-
-Start NBR special constraint process at 23:23:42 12/28/23
-
-Start NBR section for initial routing at 23:23:42 12/28/23
-Level 4, iteration 1
-19(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 58.137ns/0.000ns; real time: 11 secs 
-
-Info: Initial congestion level at 75% usage is 0
-Info: Initial congestion area  at 75% usage is 0 (0.00%)
-
-Start NBR section for normal routing at 23:23:42 12/28/23
-Level 4, iteration 1
-8(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 11 secs 
-Level 4, iteration 2
-1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 11 secs 
-Level 4, iteration 3
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 12 secs 
-
-Start NBR section for setup/hold timing optimization with effort level 3 at 23:23:43 12/28/23
-
-Start NBR section for re-routing at 23:23:43 12/28/23
-Level 4, iteration 1
-0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
-Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 12 secs 
-
-Start NBR section for post-routing at 23:23:43 12/28/23
-
-End NBR router with 0 unrouted connection
-
-NBR Summary
------------
-  Number of unrouted connections : 0 (0.00%)
-  Number of connections with timing violations : 0 (0.00%)
-  Estimated worst slack<setup> : 57.938ns
-  Timing score<setup> : 0
------------
-Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
-
-
-
-Total CPU time 12 secs 
-Total REAL time: 12 secs 
-Completely routed.
-End of route.  1330 routed (100.00%); 0 unrouted.
-
-Hold time timing score: 0, hold timing errors: 0
-
-Timing score: 0 
-
-Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
-
-
-All signals are completely routed.
-
-
-PAR_SUMMARY::Run status = Completed
-PAR_SUMMARY::Number of unrouted conns = 0
-PAR_SUMMARY::Worst  slack<setup/<ns>> = 57.938
-PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
-PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.379
-PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
-PAR_SUMMARY::Number of errors = 0
-
-Total CPU  time to completion: 12 secs 
-Total REAL time to completion: 13 secs 
-
-par done!
-
-Note: user must run 'Trace' for timing closure signoff.
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
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    - - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt deleted file mode 100644 index c2df067..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt +++ /dev/null @@ -1,51 +0,0 @@ - -Copyright (C) 1994-2021 Synopsys, Inc. -This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. -and may only be used pursuant to the terms and conditions of a written license agreement -with Synopsys, Inc. All other use, reproduction, modification, or distribution of the -Synopsys software or the associated documentation is strictly prohibited. -Tool: Synplify Pro (R) -Build: R-2021.03L-SP1 -Install: C:\lscc\diamond\3.12\synpbase -OS: Windows 6.2 - -Hostname: ZANEMACWIN11 - -Implementation : impl1 - -# Written on Thu Dec 28 23:23:20 2023 - -##### FILES SYNTAX CHECKED ############################################## -Constraint File(s): "\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc" - -#Run constraint checker to find more issues with constraints. -######################################################################### - - - -No issues found in constraint syntax. - - - -Clock Summary -************* - - Start Requested Requested Clock Clock Clock -Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------- -0 - C14M 14.3 MHz 69.841 declared default_clkgroup 122 - -0 - System 100.0 MHz 10.000 system system_clkgroup 0 -======================================================================================== - - -Clock Load Summary -****************** - - Clock Source Clock Pin Non-clock Pin Non-clock Pin -Clock Load Pin Seq Example Seq Example Comb Example ----------------------------------------------------------------------------------------- -C14M 122 C14M(port) DOEEN.C - un1_C14M.I[0](inv) - -System 0 - - - - -======================================================================================== diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html deleted file mode 100644 index ab3cea2..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html +++ /dev/null @@ -1,83 +0,0 @@ - -Project Summary - - -
    
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    RAM2E_LCMXO2_640HC project summary
    Module Name:RAM2E_LCMXO2_640HCSynthesis:SynplifyPro
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:State:
    Target Device:LCMXO2-640HC-4TG100CDevice Family:MachXO2
    Device Type:LCMXO2-640HCPackage Type:TQFP100
    Performance grade:4Operating conditions:COM
    Logic preference file:RAM2E-LCMXO2.lpf
    Physical Preference file:impl1/RAM2E_LCMXO2_640HC_impl1.prf
    Product Version:3.12.1.454Patch Version:
    Updated:2024/01/05 06:01:02
    Implementation Location://Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1
    Project File://Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf
    
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-
    - - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html deleted file mode 100644 index d8ae1c6..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html +++ /dev/null @@ -1,761 +0,0 @@ - -Synthesis Report - - -
    Synthesis Report
-#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
-#install: C:\lscc\diamond\3.12\synpbase
-#OS: Windows 8 6.2
-#Hostname: ZANEMACWIN11
-
-# Thu Dec 28 23:23:17 2023
-
-#Implementation: impl1
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
-@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
-@I::"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v" (library work)
-@I::"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v" (library work)
-@I::"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v" (library work)
-Verilog syntax check successful!
-File \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v changed - recompiling
-File \\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v changed - recompiling
-Selecting top level module RAM2E
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
-Running optimization stage 1 on VHI .......
-Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
-Running optimization stage 1 on VLO .......
-Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
-@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
-Running optimization stage 1 on EFB .......
-Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
-Running optimization stage 1 on REFB .......
-Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
-@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work.
-Running optimization stage 1 on RAM2E_UFM .......
-Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB)
-@N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":1:7:1:11|Synthesizing module RAM2E in library work.
-Running optimization stage 1 on RAM2E .......
-Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
-Running optimization stage 2 on RAM2E .......
-@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused.
-Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-Running optimization stage 2 on RAM2E_UFM .......
-@N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused.
-Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-Running optimization stage 2 on REFB .......
-Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-Running optimization stage 2 on EFB .......
-Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-Running optimization stage 2 on VLO .......
-Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-Running optimization stage 2 on VHI .......
-Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB)
-
-At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Dec 28 23:23:18 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\layer0.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Dec 28 23:23:18 2023
-
-###########################################################]
-
-For a summary of runtime and memory usage for all design units, please see file:
-==========================================================
-@L: A:\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
-
-@END
-
-At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 31MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Dec 28 23:23:18 2023
-
-###########################################################]
-###########################################################[
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
-
-@N|Running in 64-bit mode
-File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
-
-At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-
-Process completed successfully.
-# Thu Dec 28 23:23:19 2023
-
-###########################################################]
-# Thu Dec 28 23:23:19 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
-
-
-Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB)
-
-Reading constraint file: \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc
-@L: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt 
-See clock summary report "\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
-
-@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
-@N: FX493 |Applying initial value "0" on instance PHI1r.
-@N: FX493 |Applying initial value "0" on instance RWSel.
-@N: FX493 |Applying initial value "0" on instance Ready.
-@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
-@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
-@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
-@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
-@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQMH is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "1" on instance DQMH.
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Initial value on register DQML is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "1" on instance DQML.
-@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":21:4:21:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
-@N: FX493 |Applying initial value "0000" on instance S[3:0].
-@N: FX493 |Applying initial value "1" on instance CKE.
-@N: FX493 |Applying initial value "1" on instance nRWE.
-@N: FX493 |Applying initial value "1" on instance nRWEout.
-@N: FX493 |Applying initial value "1" on instance nCAS.
-@N: FX493 |Applying initial value "1" on instance nCASout.
-@N: FX493 |Applying initial value "1" on instance nRAS.
-@N: FX493 |Applying initial value "1" on instance nRASout.
-
-Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
-
-
-Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
-
-
-Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
-
-
-Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
-
-@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E 
-
-Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
-
-
-
-Clock Summary
-******************
-
-          Start      Requested     Requested     Clock        Clock                Clock
-Level     Clock      Frequency     Period        Type         Group                Load 
-----------------------------------------------------------------------------------------
-0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     122  
-                                                                                        
-0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
-========================================================================================
-
-
-
-Clock Load Summary
-***********************
-
-           Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin     
-Clock      Load      Pin            Seq Example     Seq Example       Comb Example      
-----------------------------------------------------------------------------------------
-C14M       122       C14M(port)     DOEEN.C         -                 un1_C14M.I[0](inv)
-                                                                                        
-System     0         -              -               -                 -                 
-========================================================================================
-
-ICG Latch Removal Summary:
-Number of ICG latches removed: 0
-Number of ICG latches not removed:	0
-For details review file gcc_ICG_report.rpt
-
-
-@S |Clock Optimization Summary
-
-
-
-#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
-
-1 non-gated/non-generated clock tree(s) driving 122 clock pin(s) of sequential element(s)
-0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
-0 instances converted, 0 sequential instances remain driven by gated/generated clocks
-
-=========================== Non-Gated/Non-Generated Clocks ============================
-Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
----------------------------------------------------------------------------------------
-@KP:ckid0_0       C14M                port                   122        nRAS           
-=======================================================================================
-
-
-##### END OF CLOCK OPTIMIZATION REPORT ######
-
-@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
-Finished Pre Mapping Phase.
-
-Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
-
-
-Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
-
-
-Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB)
-
-Pre-mapping successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
-
-Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu Dec 28 23:23:21 2023
-
-###########################################################]
-# Thu Dec 28 23:23:21 2023
-
-
-Copyright (C) 1994-2021 Synopsys, Inc.
-This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
-and may only be used pursuant to the terms and conditions of a written license agreement
-with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
-Synopsys software or the associated documentation is strictly prohibited.
-Tool: Synplify Pro (R)
-Build: R-2021.03L-SP1
-Install: C:\lscc\diamond\3.12\synpbase
-OS: Windows 6.2
-
-Hostname: ZANEMACWIN11
-
-Implementation : impl1
-Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
-
-
-Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB)
-
-@N: MF916 |Option synthesis_strategy=base is enabled. 
-@N: MF248 |Running in 64-bit mode.
-@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
-
-Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
-
-
-Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB)
-
-
-Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
-
-
-Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)
-
-
-
-Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB)
-
-
-Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB)
-
-@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
-@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
-
-Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB)
-
-
-Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
-
-
-Available hyper_sources - for debug and ip models
-	None Found
-
-
-Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
-
-
-Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
-
-
-Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB)
-
-
-Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB)
-
-
-Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB)
-
-
-Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
-
-Pass		 CPU time		Worst Slack		Luts / Registers
-------------------------------------------------------------
-   1		0h:00m:02s		    33.71ns		 284 /       122
-
-Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB)
-
-@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
-@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-@A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_0_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. 
-
-Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
-
-
-Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB)
-
-Writing Analyst data base \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
-
-Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB)
-
-Writing EDIF Netlist and constraint files
-@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
-@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
-
-Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
-
-
-Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB)
-
-
-Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB)
-
-@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
-@N: MT615 |Found clock C14M with period 69.84ns 
-
-
-##### START OF TIMING REPORT #####[
-# Timing report written on Thu Dec 28 23:23:25 2023
-#
-
-
-Top view:               RAM2E
-Requested Frequency:    14.3 MHz
-Wire load mode:         top
-Paths requested:        5
-Constraint File(s):    \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc
-                       
-@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
-
-@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
-
-
-
-Performance Summary
-*******************
-
-
-Worst slack in design: 33.707
-
-                   Requested     Estimated     Requested     Estimated                Clock        Clock           
-Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
--------------------------------------------------------------------------------------------------------------------
-C14M               14.3 MHz      128.0 MHz     69.841        7.813         33.707     declared     default_clkgroup
-System             100.0 MHz     NA            10.000        NA            67.088     system       system_clkgroup 
-===================================================================================================================
-Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
-
-
-
-
-
-Clock Relationships
-*******************
-
-Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------
-Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack
-----------------------------------------------------------------------------------------------------------
-System    C14M    |  69.841      67.088  |  No paths    -      |  No paths    -       |  No paths    -    
-C14M      System  |  69.841      68.797  |  No paths    -      |  No paths    -       |  No paths    -    
-C14M      C14M    |  69.841      62.028  |  No paths    -      |  34.920      33.707  |  No paths    -    
-==========================================================================================================
- Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
-       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
-
-
-
-Interface Information 
-*********************
-
-No IO constraint found
-
-
-
-====================================
-Detailed Report for Clock: C14M
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-             Starting                                    Arrival           
-Instance     Reference     Type        Pin     Net       Time        Slack 
-             Clock                                                         
----------------------------------------------------------------------------
-RA[0]        C14M          FD1P3AX     Q       RA[0]     1.108       33.707
-RA[3]        C14M          FD1P3AX     Q       RA[3]     1.108       33.707
-RA[1]        C14M          FD1P3AX     Q       RA[1]     1.044       33.771
-RA[2]        C14M          FD1P3AX     Q       RA[2]     1.044       33.771
-RA[4]        C14M          FD1P3AX     Q       RA[4]     1.044       33.771
-RA[5]        C14M          FD1P3AX     Q       RA[5]     1.044       33.771
-RA[6]        C14M          FD1P3AX     Q       RA[6]     1.044       33.771
-RA[7]        C14M          FD1P3AX     Q       RA[7]     1.044       33.771
-RA[8]        C14M          FD1P3AX     Q       RA[8]     1.044       33.771
-RA[9]        C14M          FD1P3AX     Q       RA[9]     1.044       33.771
-===========================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                 Starting                                     Required           
-Instance         Reference     Type         Pin     Net       Time         Slack 
-                 Clock                                                           
----------------------------------------------------------------------------------
-RAout_0io[0]     C14M          OFS1P3DX     D       RA[0]     34.815       33.707
-RAout_0io[3]     C14M          OFS1P3DX     D       RA[3]     34.815       33.707
-RAout_0io[1]     C14M          OFS1P3DX     D       RA[1]     34.815       33.771
-RAout_0io[2]     C14M          OFS1P3DX     D       RA[2]     34.815       33.771
-RAout_0io[4]     C14M          OFS1P3DX     D       RA[4]     34.815       33.771
-RAout_0io[5]     C14M          OFS1P3DX     D       RA[5]     34.815       33.771
-RAout_0io[6]     C14M          OFS1P3DX     D       RA[6]     34.815       33.771
-RAout_0io[7]     C14M          OFS1P3DX     D       RA[7]     34.815       33.771
-RAout_0io[8]     C14M          OFS1P3DX     D       RA[8]     34.815       33.771
-RAout_0io[9]     C14M          OFS1P3DX     D       RA[9]     34.815       33.771
-=================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      34.920
-    - Setup time:                            0.106
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         34.815
-
-    - Propagation time:                      1.108
-    - Clock delay at starting point:         0.000 (ideal)
-    = Slack (critical) :                     33.707
-
-    Number of logic level(s):                0
-    Starting point:                          RA[0] / Q
-    Ending point:                            RAout_0io[0] / D
-    The start point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
-    The end   point is clocked by            C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
-
-Instance / Net                  Pin      Pin               Arrival     No. of    
-Name               Type         Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------
-RA[0]              FD1P3AX      Q        Out     1.108     1.108 r     -         
-RA[0]              Net          -        -       -         -           3         
-RAout_0io[0]       OFS1P3DX     D        In      0.000     1.108 r     -         
-=================================================================================
-
-
-
-
-====================================
-Detailed Report for Clock: System
-====================================
-
-
-
-Starting Points with Worst Slack
-********************************
-
-                               Starting                                          Arrival           
-Instance                       Reference     Type     Pin         Net            Time        Slack 
-                               Clock                                                               
----------------------------------------------------------------------------------------------------
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
-ram2e_ufm.ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
-===================================================================================================
-
-
-Ending Points with Worst Slack
-******************************
-
-                         Starting                                                                  Required           
-Instance                 Reference     Type        Pin     Net                                     Time         Slack 
-                         Clock                                                                                        
-----------------------------------------------------------------------------------------------------------------------
-ram2e_ufm.RWMask[0]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[1]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[2]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[3]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[4]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[5]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[6]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.RWMask[7]      System        FD1P3AX     SP      un1_RWMask_0_sqmuxa_1_i_0_0[0]          69.369       67.088
-ram2e_ufm.LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0_0[0]           69.369       67.736
-ram2e_ufm.wb_cyc_stb     System        FD1P3AX     SP      un1_CmdSetRWBankFFChip13_1_i_0_0[0]     69.369       67.736
-======================================================================================================================
-
-
-
-Worst Path Information
-***********************
-
-
-Path information for path number 1: 
-      Requested Period:                      69.841
-    - Setup time:                            0.472
-    + Clock delay at ending point:           0.000 (ideal)
-    = Required time:                         69.369
-
-    - Propagation time:                      2.282
-    - Clock delay at starting point:         0.000 (ideal)
-    - Estimated clock delay at start point:  -0.000
-    = Slack (non-critical) :                 67.088
-
-    Number of logic level(s):                2
-    Starting point:                          ram2e_ufm.ufmefb.EFBInst_0 / WBACKO
-    Ending point:                            ram2e_ufm.RWMask[0] / SP
-    The start point is clocked by            System [rising]
-    The end   point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
-
-Instance / Net                                                 Pin        Pin               Arrival     No. of    
-Name                                              Type         Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------
-ram2e_ufm.ufmefb.EFBInst_0                        EFB          WBACKO     Out     0.000     0.000 r     -         
-wb_ack                                            Net          -          -       -         -           5         
-ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     B          In      0.000     0.000 r     -         
-ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]     ORCALUT4     Z          Out     1.017     1.017 r     -         
-un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0]               Net          -          -       -         -           1         
-ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
-ram2e_ufm.un1_RWMask_0_sqmuxa_1_i_0_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
-un1_RWMask_0_sqmuxa_1_i_0_0[0]                    Net          -          -       -         -           8         
-ram2e_ufm.RWMask[0]                               FD1P3AX      SP         In      0.000     2.282 r     -         
-==================================================================================================================
-
-
-
-##### END OF TIMING REPORT #####]
-
-Timing exceptions that could not be applied
-
-Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
-
-
-Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB)
-
----------------------------------------
-Resource Usage Report
-Part: lcmxo2_640hc-4
-
-Register bits: 122 of 640 (19%)
-PIC Latch:       0
-I/O cells:       69
-
-
-Details:
-BB:             8
-CCU2D:          9
-EFB:            1
-FD1P3AX:        61
-FD1P3IX:        1
-FD1S3AX:        21
-FD1S3AY:        4
-FD1S3IX:        6
-GSR:            1
-IB:             21
-IFS1P3DX:       1
-INV:            1
-OB:             40
-OFS1P3BX:       5
-OFS1P3DX:       21
-OFS1P3IX:       2
-ORCALUT4:       277
-PFUMX:          3
-PUR:            1
-VHI:            3
-VLO:            3
-Mapper successful!
-
-At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 217MB)
-
-Process took 0h:00m:04s realtime, 0h:00m:04s cputime
-# Thu Dec 28 23:23:25 2023
-
-###########################################################]
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    - - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html deleted file mode 100644 index 1027e13..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html +++ /dev/null @@ -1,289 +0,0 @@ - -Lattice Map TRACE Report - - -
    Map TRACE Report
-
-Loading design for application trce from file ram2e_lcmxo2_640hc_impl1_map.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Dec 28 23:23:29 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
-Design file:     ram2e_lcmxo2_640hc_impl1_map.ncd
-Preference file: ram2e_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,4
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1611 items scored, 0 timing errors detected.
-Report:   90.967MHz is the maximum frequency for this preference.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1611 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 58.937ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[2]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              10.827ns  (31.6% logic, 68.4% route), 7 logic levels.
-
- Constraint Details:
-
-     10.827ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.937ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452   SLICE_34.CLK to    SLICE_34.Q0 SLICE_34 (from C14M_c)
-ROUTE        50   e 1.234    SLICE_34.Q0 to    SLICE_35.A0 S[2]
-CTOF_DEL    ---     0.495    SLICE_35.A0 to    SLICE_35.F0 SLICE_35
-ROUTE         7   e 1.234    SLICE_35.F0 to *m/SLICE_80.D1 N_551
-CTOF_DEL    ---     0.495 *m/SLICE_80.D1 to *m/SLICE_80.F1 ram2e_ufm/SLICE_80
-ROUTE         8   e 1.234 *m/SLICE_80.F1 to *m/SLICE_98.B1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495 *m/SLICE_98.B1 to *m/SLICE_98.F1 ram2e_ufm/SLICE_98
-ROUTE         5   e 1.234 *m/SLICE_98.F1 to *m/SLICE_99.C0 ram2e_ufm/N_781
-CTOF_DEL    ---     0.495 *m/SLICE_99.C0 to *m/SLICE_99.F0 ram2e_ufm/SLICE_99
-ROUTE         1   e 1.234 *m/SLICE_99.F0 to *m/SLICE_86.C0 ram2e_ufm/wb_adr_7_i_i_1[0]
-CTOF_DEL    ---     0.495 *m/SLICE_86.C0 to *m/SLICE_86.F0 ram2e_ufm/SLICE_86
-ROUTE         1   e 1.234 *m/SLICE_86.F0 to *m/SLICE_47.C0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495 *m/SLICE_47.C0 to *m/SLICE_47.F0 ram2e_ufm/SLICE_47
-ROUTE         1   e 0.001 *m/SLICE_47.F0 to */SLICE_47.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   10.827   (31.6% logic, 68.4% route), 7 logic levels.
-
-Report:   90.967MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   90.967 MHz|   7  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 1 clocks:
-
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
-   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Dec 28 23:23:29 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
-Design file:     ram2e_lcmxo2_640hc_impl1_map.ncd
-Preference file: ram2e_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,M
-Report level:    verbose report, limited to 1 item per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1611 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1611 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.447ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[0]  (from C14M_c +)
-   Destination:    FF         Data in        FS[0]  (to C14M_c +)
-
-   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.434ns physical path delay SLICE_0 to SLICE_0 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
-
- Physical Path Details:
-
-      Data path SLICE_0 to SLICE_0:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133    SLICE_0.CLK to     SLICE_0.Q1 SLICE_0 (from C14M_c)
-ROUTE         6   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
-CTOF_DEL    ---     0.101     SLICE_0.A1 to     SLICE_0.F1 SLICE_0
-ROUTE         1   e 0.001     SLICE_0.F1 to    SLICE_0.DI1 FS_s[0] (to C14M_c)
-                  --------
-                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   2  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 1 clocks:
-
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
-   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
-
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    - - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html deleted file mode 100644 index 32b00c0..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html +++ /dev/null @@ -1,1213 +0,0 @@ - -Lattice TRACE Report - - -
    Place & Route TRACE Report
-
-Loading design for application trce from file ram2e_lcmxo2_640hc_impl1.ncd.
-Design name: RAM2E
-NCD version: 3.3
-Vendor:      LATTICE
-Device:      LCMXO2-640HC
-Package:     TQFP100
-Performance: 4
-Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
-Package Status:                     Final          Version 1.39.
-Performance Hardware Data Status:   Final          Version 34.4.
-Setup and Hold Report
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
-Thu Dec 28 23:23:44 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
-Design file:     ram2e_lcmxo2_640hc_impl1.ncd
-Preference file: ram2e_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,4
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1611 items scored, 0 timing errors detected.
-Report:   83.389MHz is the maximum frequency for this preference.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1611 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 57.938ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.826ns  (24.8% logic, 75.2% route), 6 logic levels.
-
- Constraint Details:
-
-     11.826ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.938ns
-
- Physical Path Details:
-
-      Data path SLICE_33 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
-ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
-CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
-ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
-CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
-ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
-CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   11.826   (24.8% logic, 75.2% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 57.944ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[3]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.820ns  (29.0% logic, 71.0% route), 7 logic levels.
-
- Constraint Details:
-
-     11.820ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.944ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
-ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
-CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
-ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
-CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
-ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
-CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
-ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
-CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   11.820   (29.0% logic, 71.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.190ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[15]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.574ns  (25.3% logic, 74.7% route), 6 logic levels.
-
- Constraint Details:
-
-     11.574ns physical path delay SLICE_1 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.190ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R2C11A.CLK to      R2C11A.Q0 SLICE_1 (from C14M_c)
-ROUTE         9     2.239      R2C11A.Q0 to       R6C9B.C1 FS[15]
-CTOF_DEL    ---     0.495       R6C9B.C1 to       R6C9B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
-ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
-CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
-ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
-CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   11.574   (25.3% logic, 74.7% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to     R2C11A.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.271ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[2]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              11.493ns  (29.8% logic, 70.2% route), 7 logic levels.
-
- Constraint Details:
-
-     11.493ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.271ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q0 SLICE_34 (from C14M_c)
-ROUTE        50     0.674      R6C10D.Q0 to      R6C10A.D0 S[2]
-CTOF_DEL    ---     0.495      R6C10A.D0 to      R6C10A.F0 SLICE_35
-ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
-CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.866       R6C9B.F1 to       R3C5B.B1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R3C5B.B1 to       R3C5B.F1 ram2e_ufm/SLICE_89
-ROUTE         6     1.040       R3C5B.F1 to       R4C5C.B1 ram2e_ufm/N_783
-CTOF_DEL    ---     0.495       R4C5C.B1 to       R4C5C.F1 ram2e_ufm/SLICE_68
-ROUTE         1     0.967       R4C5C.F1 to       R4C5A.A0 ram2e_ufm/wb_adr_7_i_i_3[0]
-CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   11.493   (29.8% logic, 70.2% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.733ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_dati[2]  (to C14M_c +)
-
-   Delay:              11.031ns  (26.5% logic, 73.5% route), 6 logic levels.
-
- Constraint Details:
-
-     11.031ns physical path delay SLICE_33 to ram2e_ufm/SLICE_53 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.733ns
-
- Physical Path Details:
-
-      Data path SLICE_33 to ram2e_ufm/SLICE_53:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
-ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
-CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
-ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
-CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
-ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
-CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
-ROUTE         2     0.758       R3C4C.F1 to       R2C4B.C0 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
-CTOF_DEL    ---     0.495       R2C4B.C0 to       R2C4B.F0 ram2e_ufm/SLICE_53
-ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 ram2e_ufm/wb_dati_7[2] (to C14M_c)
-                  --------
-                   11.031   (26.5% logic, 73.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_53:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to      R2C4B.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.733ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_dati[5]  (to C14M_c +)
-
-   Delay:              11.031ns  (26.5% logic, 73.5% route), 6 logic levels.
-
- Constraint Details:
-
-     11.031ns physical path delay SLICE_33 to ram2e_ufm/SLICE_54 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.733ns
-
- Physical Path Details:
-
-      Data path SLICE_33 to ram2e_ufm/SLICE_54:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
-ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
-CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
-ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
-CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
-ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
-CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
-ROUTE         2     0.758       R3C4C.F1 to       R2C4D.C1 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
-CTOF_DEL    ---     0.495       R2C4D.C1 to       R2C4D.F1 ram2e_ufm/SLICE_54
-ROUTE         1     0.000       R2C4D.F1 to      R2C4D.DI1 ram2e_ufm/wb_dati_7[5] (to C14M_c)
-                  --------
-                   11.031   (26.5% logic, 73.5% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_54:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to      R2C4D.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.739ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[3]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_dati[5]  (to C14M_c +)
-
-   Delay:              11.025ns  (31.0% logic, 69.0% route), 7 logic levels.
-
- Constraint Details:
-
-     11.025ns physical path delay SLICE_34 to ram2e_ufm/SLICE_54 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.739ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_54:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
-ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
-CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
-ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
-CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
-ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
-CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
-ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
-CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
-ROUTE         2     0.758       R3C4C.F1 to       R2C4D.C1 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
-CTOF_DEL    ---     0.495       R2C4D.C1 to       R2C4D.F1 ram2e_ufm/SLICE_54
-ROUTE         1     0.000       R2C4D.F1 to      R2C4D.DI1 ram2e_ufm/wb_dati_7[5] (to C14M_c)
-                  --------
-                   11.025   (31.0% logic, 69.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_54:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to      R2C4D.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.739ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[3]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_dati[2]  (to C14M_c +)
-
-   Delay:              11.025ns  (31.0% logic, 69.0% route), 7 logic levels.
-
- Constraint Details:
-
-     11.025ns physical path delay SLICE_34 to ram2e_ufm/SLICE_53 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.739ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_53:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
-ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
-CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
-ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
-CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     1.621       R6C9B.F1 to       R2C7D.D1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R2C7D.D1 to       R2C7D.F1 ram2e_ufm/SLICE_70
-ROUTE         3     0.981       R2C7D.F1 to       R2C6D.A1 ram2e_ufm/N_807
-CTOF_DEL    ---     0.495       R2C6D.A1 to       R2C6D.F1 ram2e_ufm/SLICE_111
-ROUTE         3     2.253       R2C6D.F1 to       R3C4C.A1 ram2e_ufm/N_611
-CTOF_DEL    ---     0.495       R3C4C.A1 to       R3C4C.F1 ram2e_ufm/SLICE_73
-ROUTE         2     0.758       R3C4C.F1 to       R2C4B.C0 ram2e_ufm/wb_dati_7_0_0_o3_0[2]
-CTOF_DEL    ---     0.495       R2C4B.C0 to       R2C4B.F0 ram2e_ufm/SLICE_53
-ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 ram2e_ufm/wb_dati_7[2] (to C14M_c)
-                  --------
-                   11.025   (31.0% logic, 69.0% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_53:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to      R2C4B.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.780ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[0]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              10.984ns  (26.6% logic, 73.4% route), 6 logic levels.
-
- Constraint Details:
-
-     10.984ns physical path delay SLICE_33 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.780ns
-
- Physical Path Details:
-
-      Data path SLICE_33 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R6C10C.CLK to      R6C10C.Q0 SLICE_33 (from C14M_c)
-ROUTE        37     2.491      R6C10C.Q0 to       R6C9B.D1 S[0]
-CTOF_DEL    ---     0.495       R6C9B.D1 to       R6C9B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.182       R6C9B.F1 to       R2C5A.C1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R2C5A.C1 to       R2C5A.F1 ram2e_ufm/SLICE_98
-ROUTE         5     1.413       R2C5A.F1 to       R4C5B.D0 ram2e_ufm/N_781
-CTOF_DEL    ---     0.495       R4C5B.D0 to       R4C5B.F0 ram2e_ufm/SLICE_126
-ROUTE         1     0.436       R4C5B.F0 to       R4C5A.C0 ram2e_ufm/N_753
-CTOF_DEL    ---     0.495       R4C5A.C0 to       R4C5A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   10.984   (26.6% logic, 73.4% route), 6 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_33:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to     R6C10C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 58.786ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              S[3]  (from C14M_c +)
-   Destination:    FF         Data in        ram2e_ufm/wb_adr[0]  (to C14M_c +)
-
-   Delay:              10.978ns  (31.2% logic, 68.8% route), 7 logic levels.
-
- Constraint Details:
-
-     10.978ns physical path delay SLICE_34 to ram2e_ufm/SLICE_47 meets
-     69.930ns delay constraint less
-      0.000ns skew and
-      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.786ns
-
- Physical Path Details:
-
-      Data path SLICE_34 to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.452     R6C10D.CLK to      R6C10D.Q1 SLICE_34 (from C14M_c)
-ROUTE        45     1.001      R6C10D.Q1 to      R6C10A.A0 S[3]
-CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_35
-ROUTE         7     0.989      R6C10A.F0 to       R6C9B.A1 N_551
-CTOF_DEL    ---     0.495       R6C9B.A1 to       R6C9B.F1 ram2e_ufm/SLICE_80
-ROUTE         8     2.182       R6C9B.F1 to       R2C5A.C1 ram2e_ufm/N_777
-CTOF_DEL    ---     0.495       R2C5A.C1 to       R2C5A.F1 ram2e_ufm/SLICE_98
-ROUTE         5     1.413       R2C5A.F1 to       R4C5B.D0 ram2e_ufm/N_781
-CTOF_DEL    ---     0.495       R4C5B.D0 to       R4C5B.F0 ram2e_ufm/SLICE_126
-ROUTE         1     0.436       R4C5B.F0 to       R4C5A.C0 ram2e_ufm/N_753
-CTOF_DEL    ---     0.495       R4C5A.C0 to       R4C5A.F0 ram2e_ufm/SLICE_86
-ROUTE         1     1.535       R4C5A.F0 to       R3C6C.B0 ram2e_ufm/wb_adr_7_i_i_4[0]
-CTOF_DEL    ---     0.495       R3C6C.B0 to       R3C6C.F0 ram2e_ufm/SLICE_47
-ROUTE         1     0.000       R3C6C.F0 to      R3C6C.DI0 ram2e_ufm/wb_adr_7_i_i[0] (to C14M_c)
-                  --------
-                   10.978   (31.2% logic, 68.8% route), 7 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_34:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to     R6C10D.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to ram2e_ufm/SLICE_47:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     3.070       62.PADDI to      R3C6C.CLK C14M_c
-                  --------
-                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report:   83.389MHz is the maximum frequency for this preference.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference                              |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   83.389 MHz|   6  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 1 clocks:
-
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
-   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
-
-
-Timing summary (Setup):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
-
---------------------------------------------------------------------------------
-Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
-Thu Dec 28 23:23:44 2023
-
-Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
-Copyright (c) 1995 AT&T Corp.   All rights reserved.
-Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
-Copyright (c) 2001 Agere Systems   All rights reserved.
-Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
-
-Report Information
-------------------
-Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
-Design file:     ram2e_lcmxo2_640hc_impl1.ncd
-Preference file: ram2e_lcmxo2_640hc_impl1.prf
-Device,speed:    LCMXO2-640HC,m
-Report level:    verbose report, limited to 10 items per preference
---------------------------------------------------------------------------------
-
-Preference Summary
-
-
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1611 items scored, 0 timing errors detected.
-
-BLOCK ASYNCPATHS
-BLOCK RESETPATHS
---------------------------------------------------------------------------------
-
-
-
-================================================================================
-Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
-            1611 items scored, 0 timing errors detected.
---------------------------------------------------------------------------------
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[15]  (from C14M_c +)
-   Destination:    FF         Data in        FS[15]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_1 to SLICE_1 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_1 to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R2C11A.CLK to      R2C11A.Q0 SLICE_1 (from C14M_c)
-ROUTE         9     0.132      R2C11A.Q0 to      R2C11A.A0 FS[15]
-CTOF_DEL    ---     0.101      R2C11A.A0 to      R2C11A.F0 SLICE_1
-ROUTE         1     0.000      R2C11A.F0 to     R2C11A.DI0 FS_s[15] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R2C11A.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_1:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R2C11A.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdTout[2]  (from C14M_c +)
-   Destination:    FF         Data in        CmdTout[2]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_18 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C9B.CLK to       R5C9B.Q1 SLICE_18 (from C14M_c)
-ROUTE         2     0.132       R5C9B.Q1 to       R5C9B.A1 CmdTout[2]
-CTOF_DEL    ---     0.101       R5C9B.A1 to       R5C9B.F1 SLICE_18
-ROUTE         1     0.000       R5C9B.F1 to      R5C9B.DI1 N_369_i (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              CmdTout[1]  (from C14M_c +)
-   Destination:    FF         Data in        CmdTout[1]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_18 to SLICE_18 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_18 to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R5C9B.CLK to       R5C9B.Q0 SLICE_18 (from C14M_c)
-ROUTE         3     0.132       R5C9B.Q0 to       R5C9B.A0 CmdTout[1]
-CTOF_DEL    ---     0.101       R5C9B.A0 to       R5C9B.F0 SLICE_18
-ROUTE         1     0.000       R5C9B.F0 to      R5C9B.DI0 N_368_i (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_18:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to      R5C9B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[13]  (from C14M_c +)
-   Destination:    FF         Data in        FS[13]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_2 to SLICE_2 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_2 to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R2C10D.CLK to      R2C10D.Q0 SLICE_2 (from C14M_c)
-ROUTE        19     0.132      R2C10D.Q0 to      R2C10D.A0 FS[13]
-CTOF_DEL    ---     0.101      R2C10D.A0 to      R2C10D.F0 SLICE_2
-ROUTE         1     0.000      R2C10D.F0 to     R2C10D.DI0 FS_s[13] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R2C10D.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_2:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R2C10D.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA[9]  (from C14M_c +)
-   Destination:    FF         Data in        RA[9]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_24 to SLICE_24 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_24 to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C11A.CLK to      R5C11A.Q1 SLICE_24 (from C14M_c)
-ROUTE         2     0.132      R5C11A.Q1 to      R5C11A.A1 RA[9]
-CTOF_DEL    ---     0.101      R5C11A.A1 to      R5C11A.F1 SLICE_24
-ROUTE         1     0.000      R5C11A.F1 to     R5C11A.DI1 RA_35[9] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R5C11A.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_24:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R5C11A.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              RA[11]  (from C14M_c +)
-   Destination:    FF         Data in        RA[11]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_25 to SLICE_25 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_25 to SLICE_25:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R5C10B.CLK to      R5C10B.Q1 SLICE_25 (from C14M_c)
-ROUTE         2     0.132      R5C10B.Q1 to      R5C10B.A1 RA[11]
-CTOF_DEL    ---     0.101      R5C10B.A1 to      R5C10B.F1 SLICE_25
-ROUTE         1     0.000      R5C10B.F1 to     R5C10B.DI1 RA_35[11] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_25:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R5C10B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_25:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R5C10B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[12]  (from C14M_c +)
-   Destination:    FF         Data in        FS[12]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_3 to SLICE_3 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_3 to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R2C10C.CLK to      R2C10C.Q1 SLICE_3 (from C14M_c)
-ROUTE        24     0.132      R2C10C.Q1 to      R2C10C.A1 FS[12]
-CTOF_DEL    ---     0.101      R2C10C.A1 to      R2C10C.F1 SLICE_3
-ROUTE         1     0.000      R2C10C.F1 to     R2C10C.DI1 FS_s[12] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R2C10C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_3:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R2C10C.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[10]  (from C14M_c +)
-   Destination:    FF         Data in        FS[10]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_4 to SLICE_4 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_4 to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R2C10B.CLK to      R2C10B.Q1 SLICE_4 (from C14M_c)
-ROUTE        19     0.132      R2C10B.Q1 to      R2C10B.A1 FS[10]
-CTOF_DEL    ---     0.101      R2C10B.A1 to      R2C10B.F1 SLICE_4
-ROUTE         1     0.000      R2C10B.F1 to     R2C10B.DI1 FS_s[10] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R2C10B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_4:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R2C10B.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[7]  (from C14M_c +)
-   Destination:    FF         Data in        FS[7]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_5 to SLICE_5 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_5 to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133     R2C10A.CLK to      R2C10A.Q0 SLICE_5 (from C14M_c)
-ROUTE         4     0.132      R2C10A.Q0 to      R2C10A.A0 FS[7]
-CTOF_DEL    ---     0.101      R2C10A.A0 to      R2C10A.F0 SLICE_5
-ROUTE         1     0.000      R2C10A.F0 to     R2C10A.DI0 FS_s[7] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R2C10A.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_5:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to     R2C10A.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-
-Passed: The following path meets requirements by 0.379ns
-
- Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
-
-   Source:         FF         Q              FS[6]  (from C14M_c +)
-   Destination:    FF         Data in        FS[6]  (to C14M_c +)
-
-   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
-
- Constraint Details:
-
-      0.366ns physical path delay SLICE_6 to SLICE_6 meets
-     -0.013ns DIN_HLD and
-      0.000ns delay constraint less
-      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
-
- Physical Path Details:
-
-      Data path SLICE_6 to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-REG_DEL     ---     0.133      R2C9D.CLK to       R2C9D.Q1 SLICE_6 (from C14M_c)
-ROUTE         4     0.132       R2C9D.Q1 to       R2C9D.A1 FS[6]
-CTOF_DEL    ---     0.101       R2C9D.A1 to       R2C9D.F1 SLICE_6
-ROUTE         1     0.000       R2C9D.F1 to      R2C9D.DI1 FS_s[6] (to C14M_c)
-                  --------
-                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
-
- Clock Skew Details: 
-
-      Source Clock Path C14M to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to      R2C9D.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-      Destination Clock Path C14M to SLICE_6:
-
-   Name    Fanout   Delay (ns)          Site               Resource
-ROUTE        89     1.059       62.PADDI to      R2C9D.CLK C14M_c
-                  --------
-                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
-
-Report Summary
---------------
-----------------------------------------------------------------------------
-Preference(MIN Delays)                  |   Constraint|       Actual|Levels
-----------------------------------------------------------------------------
-                                        |             |             |
-FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   2  
-                                        |             |             |
-----------------------------------------------------------------------------
-
-
-All preferences were met.
-
-
-Clock Domains Analysis
-------------------------
-
-Found 1 clocks:
-
-Clock Domain: C14M_c   Source: C14M.PAD   Loads: 89
-   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
-
-
-Timing summary (Hold):
----------------
-
-Timing errors: 0  Score: 0
-Cumulative negative slack: 0
-
-Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage)
-
-
-
-Timing summary (Setup and Hold):
----------------
-
-Timing errors: 0 (setup), 0 (hold)
-Score: 0 (setup), 0 (hold)
-Cumulative negative slack: 0 (0+0)
---------------------------------------------------------------------------------
-
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    - - diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf deleted file mode 100644 index 3712166..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf +++ /dev/null @@ -1,5988 +0,0 @@ -(DELAYFILE - (SDFVERSION "3.0") - (DESIGN "RAM2E") - (DATE "Thu Dec 28 23:23:51 2023") - (VENDOR "Lattice") - (PROGRAM "ldbanno") - (VERSION "Diamond (64-bit) 3.12.1.454") - (DIVIDER /) - (VOLTAGE 1.26:1.20:1.14) - (PROCESS "default") - (TEMPERATURE -40:25:85) - (TIMESCALE 1ps) - (CELL - (CELLTYPE "SLICE_0") - (INSTANCE SLICE_0) - (DELAY - (ABSOLUTE - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 FCO (718:803:889)(718:803:889)) - (IOPATH CLK Q1 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "SLICE_1") - (INSTANCE SLICE_1) - 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(CELLTYPE "ram2e_ufm_SLICE_58") - (INSTANCE ram2e_ufm\/SLICE_58) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - (IOPATH CLK Q0 (392:422:452)(392:422:452)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) - (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1250:1250:1250)) - (WIDTH (negedge CLK) (1250:1250:1250)) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SUM0_i_m3_0_SLICE_59") - (INSTANCE ram2e_ufm\/SUM0_i_m3_0\/SLICE_59) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (457:589:721)(457:589:721)) - (IOPATH B1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH D0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60") - (INSTANCE ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH B1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_CKE_7_SLICE_61") - (INSTANCE ram2e_ufm\/CKE_7\/SLICE_61) - (DELAY - (ABSOLUTE - (IOPATH D1 OFX0 (457:589:721)(457:589:721)) - (IOPATH C1 OFX0 (457:589:721)(457:589:721)) - (IOPATH A1 OFX0 (457:589:721)(457:589:721)) - (IOPATH D0 OFX0 (457:589:721)(457:589:721)) - (IOPATH B0 OFX0 (457:589:721)(457:589:721)) - (IOPATH A0 OFX0 (457:589:721)(457:589:721)) - (IOPATH M0 OFX0 (322:349:376)(322:349:376)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_62") - (INSTANCE ram2e_ufm\/SLICE_62) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_63") - (INSTANCE ram2e_ufm\/SLICE_63) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_64") - (INSTANCE ram2e_ufm\/SLICE_64) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_65") - (INSTANCE ram2e_ufm\/SLICE_65) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_66") - (INSTANCE ram2e_ufm\/SLICE_66) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_67") - (INSTANCE ram2e_ufm\/SLICE_67) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_68") - (INSTANCE ram2e_ufm\/SLICE_68) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_69") - (INSTANCE ram2e_ufm\/SLICE_69) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_70") - (INSTANCE ram2e_ufm\/SLICE_70) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_71") - (INSTANCE ram2e_ufm\/SLICE_71) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_72") - (INSTANCE ram2e_ufm\/SLICE_72) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_73") - (INSTANCE ram2e_ufm\/SLICE_73) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_74") - (INSTANCE ram2e_ufm\/SLICE_74) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_75") - (INSTANCE ram2e_ufm\/SLICE_75) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_76") - (INSTANCE ram2e_ufm\/SLICE_76) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_77") - (INSTANCE ram2e_ufm\/SLICE_77) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_78") - (INSTANCE ram2e_ufm\/SLICE_78) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_79") - (INSTANCE ram2e_ufm\/SLICE_79) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_80") - (INSTANCE ram2e_ufm\/SLICE_80) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_81") - (INSTANCE ram2e_ufm\/SLICE_81) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_82") - (INSTANCE ram2e_ufm\/SLICE_82) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_83") - (INSTANCE ram2e_ufm\/SLICE_83) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_84") - (INSTANCE ram2e_ufm\/SLICE_84) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_85") - (INSTANCE ram2e_ufm\/SLICE_85) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_86") - (INSTANCE ram2e_ufm\/SLICE_86) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_87") - (INSTANCE ram2e_ufm\/SLICE_87) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_88") - (INSTANCE ram2e_ufm\/SLICE_88) - (DELAY - (ABSOLUTE - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_89") - (INSTANCE ram2e_ufm\/SLICE_89) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_90") - (INSTANCE ram2e_ufm\/SLICE_90) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_91") - (INSTANCE ram2e_ufm\/SLICE_91) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_92") - (INSTANCE ram2e_ufm\/SLICE_92) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_93") - (INSTANCE ram2e_ufm\/SLICE_93) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_94") - (INSTANCE ram2e_ufm\/SLICE_94) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_95") - (INSTANCE ram2e_ufm\/SLICE_95) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_96") - (INSTANCE ram2e_ufm\/SLICE_96) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_97") - (INSTANCE ram2e_ufm\/SLICE_97) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_98") - (INSTANCE ram2e_ufm\/SLICE_98) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_99") - (INSTANCE ram2e_ufm\/SLICE_99) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_100") - (INSTANCE ram2e_ufm\/SLICE_100) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_101") - (INSTANCE ram2e_ufm\/SLICE_101) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_102") - (INSTANCE ram2e_ufm\/SLICE_102) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_103") - (INSTANCE ram2e_ufm\/SLICE_103) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_104") - (INSTANCE ram2e_ufm\/SLICE_104) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_105") - (INSTANCE ram2e_ufm\/SLICE_105) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_106") - (INSTANCE ram2e_ufm\/SLICE_106) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_107") - (INSTANCE ram2e_ufm\/SLICE_107) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_108") - (INSTANCE ram2e_ufm\/SLICE_108) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_109") - (INSTANCE ram2e_ufm\/SLICE_109) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_110") - (INSTANCE ram2e_ufm\/SLICE_110) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_111") - (INSTANCE ram2e_ufm\/SLICE_111) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_112") - (INSTANCE ram2e_ufm\/SLICE_112) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_113") - (INSTANCE ram2e_ufm\/SLICE_113) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_114") - (INSTANCE ram2e_ufm\/SLICE_114) - (DELAY - (ABSOLUTE - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_115") - (INSTANCE ram2e_ufm\/SLICE_115) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_116") - (INSTANCE ram2e_ufm\/SLICE_116) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_117") - (INSTANCE ram2e_ufm\/SLICE_117) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_118") - (INSTANCE ram2e_ufm\/SLICE_118) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_119") - (INSTANCE ram2e_ufm\/SLICE_119) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_120") - (INSTANCE ram2e_ufm\/SLICE_120) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_121") - (INSTANCE ram2e_ufm\/SLICE_121) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_122") - (INSTANCE ram2e_ufm\/SLICE_122) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_123") - (INSTANCE ram2e_ufm\/SLICE_123) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_124") - (INSTANCE ram2e_ufm\/SLICE_124) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_125") - (INSTANCE ram2e_ufm\/SLICE_125) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_126") - (INSTANCE ram2e_ufm\/SLICE_126) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_127") - (INSTANCE ram2e_ufm\/SLICE_127) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - (IOPATH A1 F1 (367:431:495)(367:431:495)) - (IOPATH D0 F0 (367:431:495)(367:431:495)) - (IOPATH C0 F0 (367:431:495)(367:431:495)) - (IOPATH B0 F0 (367:431:495)(367:431:495)) - (IOPATH A0 F0 (367:431:495)(367:431:495)) - ) - ) - ) - (CELL - (CELLTYPE "ram2e_ufm_SLICE_128") - (INSTANCE ram2e_ufm\/SLICE_128) - (DELAY - (ABSOLUTE - (IOPATH D1 F1 (367:431:495)(367:431:495)) - (IOPATH C1 F1 (367:431:495)(367:431:495)) - (IOPATH B1 F1 (367:431:495)(367:431:495)) - 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(WIDTH (posedge Din0) (3330:3330:3330)) - (WIDTH (negedge Din0) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_7_") - (INSTANCE Ain\[7\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain7 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain7) (3330:3330:3330)) - (WIDTH (negedge Ain7) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_6_") - (INSTANCE Ain\[6\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain6 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain6) (3330:3330:3330)) - (WIDTH (negedge Ain6) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_5_") - (INSTANCE Ain\[5\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain5 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain5) (3330:3330:3330)) - (WIDTH (negedge Ain5) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_4_") - (INSTANCE Ain\[4\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain4 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain4) (3330:3330:3330)) - (WIDTH (negedge Ain4) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_3_") - (INSTANCE Ain\[3\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain3 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain3) (3330:3330:3330)) - (WIDTH (negedge Ain3) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_2_") - (INSTANCE Ain\[2\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain2 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain2) (3330:3330:3330)) - (WIDTH (negedge Ain2) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_1_") - (INSTANCE Ain\[1\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain1 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain1) (3330:3330:3330)) - (WIDTH (negedge Ain1) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "Ain_0_") - (INSTANCE Ain\[0\]_I) - (DELAY - (ABSOLUTE - (IOPATH Ain0 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge Ain0) (3330:3330:3330)) - (WIDTH (negedge Ain0) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "nC07X") - (INSTANCE nC07X_I) - (DELAY - (ABSOLUTE - (IOPATH nC07X PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge nC07X) (3330:3330:3330)) - (WIDTH (negedge nC07X) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "nEN80") - (INSTANCE nEN80_I) - (DELAY - (ABSOLUTE - (IOPATH nEN80 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge nEN80) (3330:3330:3330)) - (WIDTH (negedge nEN80) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "nWE") - (INSTANCE nWE_I) - (DELAY - (ABSOLUTE - (IOPATH nWE PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge nWE) (3330:3330:3330)) - (WIDTH (negedge nWE) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "PHI1") - (INSTANCE PHI1_I) - (DELAY - (ABSOLUTE - (IOPATH PHI1 PADDI (1007:1069:1132)(1007:1069:1132)) - ) - ) - (TIMINGCHECK - (WIDTH (posedge PHI1) (3330:3330:3330)) - (WIDTH (negedge PHI1) (3330:3330:3330)) - ) - ) - (CELL - (CELLTYPE "PHI1_MGIOL") - (INSTANCE PHI1_MGIOL) - (DELAY - (ABSOLUTE - (IOPATH CLK IN (577:577:577)(577:577:577)) - ) - ) - (TIMINGCHECK - (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) - ) - (TIMINGCHECK - (WIDTH (posedge CLK) (1855:1855:1855)) - (WIDTH (negedge CLK) (1855:1855:1855)) - ) - ) - (CELL - (CELLTYPE "EFB_Buffer_Block") - (INSTANCE ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20) - (DELAY - (ABSOLUTE - (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278)) - (IOPATH WBCLKIin WBDATO1out (947:3204:5461)(947:3204:5461)) - (IOPATH WBCLKIin WBDATO2out (955:3211:5468)(955:3211:5468)) - (IOPATH WBCLKIin WBDATO3out (910:3173:5436)(910:3173:5436)) - (IOPATH WBCLKIin WBDATO4out (944:3217:5491)(944:3217:5491)) - (IOPATH WBCLKIin WBDATO5out (917:3672:6428)(917:3672:6428)) - (IOPATH WBCLKIin WBDATO6out (926:3191:5457)(926:3191:5457)) - (IOPATH WBCLKIin WBDATO7out (939:3201:5464)(939:3201:5464)) - (IOPATH WBCLKIin WBACKOout (903:1623:2343)(903:1623:2343)) - ) - ) - (TIMINGCHECK - (SETUPHOLD WBRSTIin (posedge WBCLKIin) (3138:3170:3203)(-3138:-1966:-794)) - (SETUPHOLD WBCYCIin (posedge WBCLKIin) (2616:2649:2682)(-2616:-1558:-501)) - (SETUPHOLD WBSTBIin (posedge WBCLKIin) (2605:2637:2670)(-2605:-1494:-384)) - (SETUPHOLD WBWEIin (posedge WBCLKIin) (1409:1442:1475)(-1409:-837:-266)) - (SETUPHOLD WBADRI0in (posedge WBCLKIin) (2058:2123:2188)(-2058:-1191:-324)) - (SETUPHOLD WBADRI1in (posedge WBCLKIin) (2068:2104:2140)(-2068:-1234:-401)) - (SETUPHOLD WBADRI2in (posedge WBCLKIin) (1928:1993:2058)(-1928:-1110:-292)) - (SETUPHOLD WBADRI3in (posedge WBCLKIin) (2167:2196:2226)(-2167:-1264:-361)) - (SETUPHOLD WBADRI4in (posedge WBCLKIin) (2072:2101:2130)(-2072:-1198:-324)) - (SETUPHOLD WBADRI5in (posedge WBCLKIin) (1611:1640:1670)(-1611:-950:-289)) - (SETUPHOLD WBADRI6in (posedge WBCLKIin) (2532:2564:2597)(-2532:-1380:-229)) - (SETUPHOLD WBADRI7in (posedge WBCLKIin) (2519:2551:2584)(-2519:-1377:-235)) - (SETUPHOLD WBDATI0in (posedge WBCLKIin) (1057:1262:1467)(-1037:-712:-388)) - (SETUPHOLD WBDATI1in (posedge WBCLKIin) (1114:1338:1563)(-1108:-785:-462)) - (SETUPHOLD WBDATI2in (posedge WBCLKIin) (916:1076:1237)(-912:-636:-360)) - (SETUPHOLD WBDATI3in (posedge WBCLKIin) (1145:1359:1573)(-1115:-782:-449)) - (SETUPHOLD WBDATI4in (posedge WBCLKIin) (1192:1400:1609)(-1176:-820:-464)) - (SETUPHOLD WBDATI5in (posedge WBCLKIin) (1027:1222:1418)(-1000:-706:-413)) - (SETUPHOLD WBDATI6in (posedge WBCLKIin) (1034:1248:1463)(-1034:-756:-479)) - (SETUPHOLD WBDATI7in (posedge WBCLKIin) (528:614:701)(-528:-398:-268)) - ) - (TIMINGCHECK - (WIDTH (posedge WBCLKIin) (4887:4887:4887)) - (WIDTH (negedge WBCLKIin) (4887:4887:4887)) - ) - ) - (CELL - (CELLTYPE "RAM2E") - (INSTANCE ) - (DELAY - (ABSOLUTE - (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_51/B1 (1363:1554:1746)(1363:1554:1746)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_69/C1 (1291:1472:1653)(1291:1472:1653)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_105/B0 (1522:1716:1910)(1522:1716:1910)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_108/B0 (788:918:1049)(788:918:1049)) - (INTERCONNECT SLICE_0/Q1 ram2e_ufm\/SLICE_146/D0 (546:608:671)(546:608:671)) - (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT C14M_I/PADDI SLICE_0/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_1/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_2/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_2/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_3/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_3/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_4/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_4/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_5/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_5/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_6/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_6/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_7/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_7/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_9/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_11/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_13/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_14/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_15/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_16/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_17/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_23/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_23/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_24/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_24/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_25/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_25/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_26/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_26/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_27/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_27/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_28/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_28/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_29/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_29/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_30/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_30/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_31/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_32/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_33/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_33/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (2666:2868:3070)(2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_39/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_40/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_41/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_42/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_43/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_43/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_44/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_44/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_45/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_45/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_46/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_46/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_47/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_47/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_48/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_48/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_49/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_49/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_50/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_50/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_51/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_52/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_52/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_53/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_53/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_54/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_54/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_55/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_55/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_56/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_57/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI ram2e_ufm\/SLICE_58/CLK (2666:2868:3070) - (2666:2868:3070)) - (INTERCONNECT C14M_I/PADDI DQMH_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI DQML_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[11\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[10\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[9\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[8\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[7\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[6\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[5\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[4\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[3\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[2\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI RAout\[0\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI BA\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI BA\[0\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI nRWEout_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI nCASout_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI nRASout_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI CKEout_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI Vout\[7\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI Vout\[6\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI Vout\[5\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI Vout\[4\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI Vout\[3\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI Vout\[2\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI Vout\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI Vout\[0\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI PHI1_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT C14M_I/PADDI - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin - (2813:3028:3243)(2813:3028:3243)) - (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_1/Q0 SLICE_9/B1 (1593:1795:1997)(1593:1795:1997)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/B1 (1675:1872:2069)(1675:1872:2069)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_57/B0 (1675:1872:2069)(1675:1872:2069)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_69/D1 (982:1084:1186)(982:1084:1186)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_80/C1 (1808:2023:2239)(1808:2023:2239)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_105/C0 (993:1150:1307)(993:1150:1307)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/B1 (1593:1795:1997)(1593:1795:1997)) - (INTERCONNECT SLICE_1/Q0 ram2e_ufm\/SLICE_120/B0 (1593:1795:1997)(1593:1795:1997)) - (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_2/Q1 SLICE_23/B1 (793:924:1055)(793:924:1055)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/D1 (995:1098:1201)(995:1098:1201)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_49/D0 (995:1098:1201)(995:1098:1201)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_50/B0 (1607:1810:2013)(1607:1810:2013)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_51/D1 (921:1016:1111)(921:1016:1111)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_56/C1 (889:1042:1195)(889:1042:1195)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/D1 (926:1021:1117)(926:1021:1117)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_57/D0 (926:1021:1117)(926:1021:1117)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_66/B1 (1490:1688:1886)(1490:1688:1886)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_70/B1 (1607:1810:2013)(1607:1810:2013)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_81/D1 (995:1098:1201)(995:1098:1201)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_85/D1 (1290:1417:1544)(1290:1417:1544)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_89/A1 (1575:1775:1976)(1575:1775:1976)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_98/D1 (995:1098:1201)(995:1098:1201)) - (INTERCONNECT SLICE_2/Q1 ram2e_ufm\/SLICE_109/C1 (1376:1566:1756)(1376:1566:1756)) - (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_2/Q0 SLICE_23/B0 (786:914:1043)(786:914:1043)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_56/B0 (786:914:1043)(786:914:1043)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_58/D0 (1283:1407:1532)(1283:1407:1532)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_64/D0 (2000:2193:2387)(2000:2193:2387)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_70/D0 (2053:2244:2436)(2053:2244:2436)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_75/D0 (2053:2244:2436)(2053:2244:2436)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_76/D0 (1673:1831:1990)(1673:1831:1990)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_81/C0 (2011:2259:2508)(2011:2259:2508)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_85/B1 (1852:2079:2307)(1852:2079:2307)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_89/D1 (2063:2255:2448)(2063:2255:2448)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_97/D1 (2063:2255:2448)(2063:2255:2448)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_103/D1 (2063:2255:2448)(2063:2255:2448)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_111/C0 (1684:1897:2111)(1684:1897:2111)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_125/B1 (2669:2961:3253)(2669:2961:3253)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_128/D1 (2063:2255:2448)(2063:2255:2448)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_128/D0 (2063:2255:2448)(2063:2255:2448)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_131/C1 (2391:2672:2954)(2391:2672:2954)) - (INTERCONNECT SLICE_2/Q0 ram2e_ufm\/SLICE_131/D0 (2053:2244:2436)(2053:2244:2436)) - (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_56/D0 (803:890:978)(803:890:978)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_58/C1 (2000:2253:2506)(2000:2253:2506)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_68/D0 (2316:2549:2782)(2316:2549:2782)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_70/B0 (2226:2491:2757)(2226:2491:2757)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_75/A0 (2194:2457:2720)(2194:2457:2720)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_76/A0 (2579:2875:3172)(2579:2875:3172)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_81/D0 (2696:2962:3228)(2696:2962:3228)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_85/C1 (1947:2202:2457)(1947:2202:2457)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_90/B1 (2933:3266:3600)(2933:3266:3600)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_93/B0 (3391:3765:4140)(3391:3765:4140)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_97/A1 (3739:4144:4549)(3739:4144:4549)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_99/A0 (3739:4144:4549)(3739:4144:4549)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_103/A1 (2912:3245:3578)(2912:3245:3578)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_104/B0 (2944:3279:3615)(2944:3279:3615)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_111/D1 (2369:2600:2831)(2369:2600:2831)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_114/B0 (2611:2910:3209)(2611:2910:3209)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_124/C1 (814:956:1099)(814:956:1099)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_126/A1 (2189:2451:2714)(2189:2451:2714)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_126/A0 (2189:2451:2714)(2189:2451:2714)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_128/A1 (4066:4506:4946)(4066:4506:4946)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_128/C0 (3540:3934:4329)(3540:3934:4329)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_131/B1 (2923:3255:3588)(2923:3255:3588)) - (INTERCONNECT SLICE_3/Q1 ram2e_ufm\/SLICE_131/A0 (2564:2859:3154)(2564:2859:3154)) - (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_3/Q0 SLICE_22/B0 (770:892:1014)(770:892:1014)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_56/A0 (751:878:1006)(751:878:1006)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_64/C1 (1633:1850:2068)(1633:1850:2068)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_64/A0 (1505:1698:1891)(1505:1698:1891)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_68/A0 (2270:2529:2789)(2270:2529:2789)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_73/C0 (1701:1918:2135)(1701:1918:2135)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_75/A1 (1875:2100:2325)(1875:2100:2325)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_76/A1 (2255:2513:2771)(2255:2513:2771)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_88/A1 (2255:2513:2771)(2255:2513:2771)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_90/A1 (2255:2513:2771)(2255:2513:2771)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_93/A1 (2619:2908:3198)(2619:2908:3198)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_99/D1 (2065:2259:2454)(2065:2259:2454)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_104/C1 (1701:1918:2135)(1701:1918:2135)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_109/D0 (2060:2254:2448)(2060:2254:2448)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_110/B1 (1901:2128:2355)(1901:2128:2355)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_114/A0 (1505:1698:1891)(1505:1698:1891)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_123/C1 (1701:1918:2135)(1701:1918:2135)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_123/C0 (1701:1918:2135)(1701:1918:2135)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_125/C1 (2076:2325:2575)(2076:2325:2575)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_125/C0 (2076:2325:2575)(2076:2325:2575)) - (INTERCONNECT SLICE_3/Q0 ram2e_ufm\/SLICE_128/C1 (1701:1918:2135)(1701:1918:2135)) - (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_4/Q1 SLICE_21/A1 (738:861:985)(738:861:985)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_47/D0 (1944:2145:2347)(1944:2145:2347)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_68/B0 (1510:1714:1919)(1510:1714:1919)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_73/B0 (1885:2122:2359)(1885:2122:2359)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_75/B1 (1495:1698:1901)(1495:1698:1901)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_76/B1 (1495:1698:1901)(1495:1698:1901)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_88/B1 (1495:1698:1901)(1495:1698:1901)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_90/D1 (1612:1778:1944)(1612:1778:1944)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_93/B1 (1484:1686:1888)(1484:1686:1888)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_99/B1 (1874:2110:2346)(1874:2110:2346)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_104/A1 (1822:2053:2285)(1822:2053:2285)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_110/D1 (1981:2179:2377)(1981:2179:2377)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_114/C1 (1628:1849:2071)(1628:1849:2071)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_123/D0 (1268:1404:1541)(1268:1404:1541)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_126/C1 (1279:1470:1662)(1279:1470:1662)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_126/C0 (1279:1470:1662)(1279:1470:1662)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_128/B1 (1885:2122:2359)(1885:2122:2359)) - (INTERCONNECT SLICE_4/Q1 ram2e_ufm\/SLICE_128/B0 (1885:2122:2359)(1885:2122:2359)) - (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_64/B1 (1617:1822:2027)(1617:1822:2027)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_68/C1 (1703:1929:2155)(1703:1929:2155)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_73/D0 (1750:1919:2089)(1750:1919:2089)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_75/C1 (805:948:1092)(805:948:1092)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_81/B1 (1222:1392:1563)(1222:1392:1563)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_93/D1 (2452:2690:2928)(2452:2690:2928)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_104/B1 (1617:1822:2027)(1617:1822:2027)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_110/C1 (1703:1929:2155)(1703:1929:2155)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_111/B0 (1222:1392:1563)(1222:1392:1563)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_114/B1 (1617:1822:2027)(1617:1822:2027)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_123/B1 (1617:1822:2027)(1617:1822:2027)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_123/B0 (1617:1822:2027)(1617:1822:2027)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_125/D1 (2447:2683:2920)(2447:2683:2920)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_125/B0 (2362:2631:2901)(2362:2631:2901)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_126/B1 (1607:1811:2015)(1607:1811:2015)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_126/B0 (1607:1811:2015)(1607:1811:2015)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_134/B0 (1591:1793:1996)(1591:1793:1996)) - (INTERCONNECT SLICE_4/Q0 ram2e_ufm\/SLICE_145/B0 (2694:3000:3306)(2694:3000:3306)) - (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_68/D1 (1879:2074:2269)(1879:2074:2269)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_68/C0 (1366:1555:1744)(1366:1555:1744)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_70/A1 (1012:1172:1333)(1012:1172:1333)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_73/A0 (1195:1362:1530)(1195:1362:1530)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_81/A1 (1387:1580:1773)(1387:1580:1773)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_93/C1 (1890:2141:2392)(1890:2141:2392)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_99/A1 (1533:1737:1942)(1533:1737:1942)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_104/D1 (1698:1869:2041)(1698:1869:2041)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_107/B0 (1038:1200:1363)(1038:1200:1363)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_110/A1 (1892:2126:2361)(1892:2126:2361)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_114/A1 (1897:2132:2367)(1897:2132:2367)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_123/D1 (1698:1869:2041)(1698:1869:2041)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_123/A0 (1897:2132:2367)(1897:2132:2367)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_125/A1 (2126:2383:2640)(2126:2383:2640)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_125/D0 (1323:1462:1601)(1323:1462:1601)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_126/D1 (1552:1712:1872)(1552:1712:1872)) - (INTERCONNECT SLICE_5/Q1 ram2e_ufm\/SLICE_145/C0 (1890:2141:2392)(1890:2141:2392)) - (INTERCONNECT SLICE_5/Q0 SLICE_5/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_5/Q0 SLICE_20/B0 (781:909:1037)(781:909:1037)) - (INTERCONNECT SLICE_5/Q0 ram2e_ufm\/SLICE_108/C1 (920:1067:1214)(920:1067:1214)) - (INTERCONNECT SLICE_5/Q0 ram2e_ufm\/SLICE_146/A0 (1446:1638:1831)(1446:1638:1831)) - (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_5/F0 SLICE_5/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_6/Q1 ram2e_ufm\/SLICE_134/D1 (544:604:665)(544:604:665)) - (INTERCONNECT SLICE_6/Q1 ram2e_ufm\/SLICE_134/D0 (544:604:665)(544:604:665)) - (INTERCONNECT SLICE_6/Q1 ram2e_ufm\/SLICE_146/C0 (555:670:786)(555:670:786)) - (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_6/Q0 ram2e_ufm\/SLICE_107/D0 (528:582:636)(528:582:636)) - (INTERCONNECT SLICE_6/Q0 ram2e_ufm\/SLICE_108/A1 (1184:1351:1519)(1184:1351:1519)) - (INTERCONNECT SLICE_6/Q0 ram2e_ufm\/SLICE_146/B0 (1216:1386:1556)(1216:1386:1556)) - (INTERCONNECT SLICE_6/F1 SLICE_6/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_6/F0 SLICE_6/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_7/FCO SLICE_6/FCI (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_7/Q1 SLICE_7/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_7/Q1 SLICE_35/B1 (2395:2672:2950)(2395:2672:2950)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_57/A1 (1183:1347:1512)(1183:1347:1512)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_67/D0 (1783:1960:2138)(1783:1960:2138)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_71/A1 (2363:2638:2913)(2363:2638:2913)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_72/B1 (2389:2666:2943)(2389:2666:2943)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_107/D1 (2528:2770:3012)(2528:2770:3012)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_108/B1 (3097:3442:3787)(3097:3442:3787)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_122/A1 (2331:2611:2891)(2331:2611:2891)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_122/A0 (2331:2611:2891)(2331:2611:2891)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_124/D1 (1783:1960:2138)(1783:1960:2138)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_124/D0 (1783:1960:2138)(1783:1960:2138)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_129/B1 (3097:3443:3789)(3097:3443:3789)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_129/B0 (3097:3443:3789)(3097:3443:3789)) - (INTERCONNECT SLICE_7/Q1 ram2e_ufm\/SLICE_146/D1 (2528:2770:3012)(2528:2770:3012)) - (INTERCONNECT SLICE_7/Q0 SLICE_7/A0 (483:579:675)(483:579:675)) - (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_67/B1 (1164:1329:1494)(1164:1329:1494)) - (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_67/B0 (1164:1329:1494)(1164:1329:1494)) - (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_71/D1 (922:1019:1116)(922:1019:1116)) - (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_107/A0 (758:888:1018)(758:888:1018)) - (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_122/D1 (1260:1394:1528)(1260:1394:1528)) - (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_122/D0 (1260:1394:1528)(1260:1394:1528)) - (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_124/A1 (1502:1696:1891)(1502:1696:1891)) - (INTERCONNECT SLICE_7/Q0 ram2e_ufm\/SLICE_124/A0 (1502:1696:1891)(1502:1696:1891)) - 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(INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_122/B1 (1165:1330:1495)(1165:1330:1495)) - (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_122/B0 (1165:1330:1495)(1165:1330:1495)) - (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_124/C0 (918:1068:1219)(918:1068:1219)) - (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_129/A0 (1497:1691:1885)(1497:1691:1885)) - (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_131/D1 (530:586:642)(530:586:642)) - (INTERCONNECT SLICE_8/Q0 ram2e_ufm\/SLICE_134/B1 (779:910:1042)(779:910:1042)) - (INTERCONNECT SLICE_8/F1 SLICE_8/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_8/F0 SLICE_8/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_33/Q1 SLICE_9/D1 (885:985:1086)(885:985:1086)) - (INTERCONNECT SLICE_33/Q1 SLICE_9/B0 (1127:1295:1464)(1127:1295:1464)) - (INTERCONNECT SLICE_33/Q1 SLICE_33/D0 (538:599:660)(538:599:660)) - (INTERCONNECT SLICE_33/Q1 SLICE_35/D1 (538:599:660)(538:599:660)) - (INTERCONNECT SLICE_33/Q1 SLICE_36/D1 (1276:1411:1547)(1276:1411:1547)) - (INTERCONNECT SLICE_33/Q1 SLICE_37/A1 (2975:3305:3635)(2975:3305:3635)) - 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(INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_121/C0 (1282:1472:1662)(1282:1472:1662)) - (INTERCONNECT SLICE_33/Q1 ram2e_ufm\/SLICE_127/A1 (2273:2534:2796)(2273:2534:2796)) - (INTERCONNECT SLICE_33/Q1 SLICE_138/A1 (753:882:1012)(753:882:1012)) - (INTERCONNECT SLICE_33/Q1 SLICE_138/B0 (1123:1292:1461)(1123:1292:1461)) - (INTERCONNECT SLICE_35/F0 SLICE_9/C1 (559:681:804)(559:681:804)) - (INTERCONNECT SLICE_35/F0 SLICE_9/C0 (559:681:804)(559:681:804)) - (INTERCONNECT SLICE_35/F0 SLICE_35/A1 (483:582:681)(483:582:681)) - (INTERCONNECT SLICE_35/F0 SLICE_35/DI0 (7:16:25)(7:16:25)) - (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_80/A1 (740:864:989)(740:864:989)) - (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_92/C1 (929:1083:1238)(929:1083:1238)) - (INTERCONNECT SLICE_35/F0 ram2e_ufm\/SLICE_129/C0 (1293:1479:1665)(1293:1479:1665)) - (INTERCONNECT SLICE_33/Q0 SLICE_9/A1 (786:917:1048)(786:917:1048)) - (INTERCONNECT SLICE_33/Q0 SLICE_9/A0 (786:917:1048)(786:917:1048)) - (INTERCONNECT SLICE_33/Q0 SLICE_35/C1 (536:648:760)(536:648:760)) - (INTERCONNECT SLICE_33/Q0 SLICE_36/B1 (1198:1364:1531)(1198:1364:1531)) - (INTERCONNECT SLICE_33/Q0 SLICE_37/D1 (956:1054:1153)(956:1054:1153)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_56/D1 (825:916:1008)(825:916:1008)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_69/B0 (1442:1634:1826)(1442:1634:1826)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_71/C0 (1581:1792:2003)(1581:1792:2003)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_72/A1 (786:917:1048)(786:917:1048)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_74/A0 (1551:1748:1946)(1551:1748:1946)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_77/A0 (1931:2161:2392)(1931:2161:2392)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_78/A1 (1035:1192:1349)(1035:1192:1349)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_80/D1 (2096:2293:2491)(2096:2293:2491)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_92/A0 (1166:1330:1494)(1166:1330:1494)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_95/B1 (2160:2423:2686)(2160:2423:2686)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_96/B1 (1067:1226:1386)(1067:1226:1386)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_106/A1 (1551:1748:1946)(1551:1748:1946)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_107/B1 (1431:1622:1813)(1431:1622:1813)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_112/B1 (1442:1634:1826)(1442:1634:1826)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_113/A0 (1551:1748:1946)(1551:1748:1946)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_115/D0 (1689:1860:2031)(1689:1860:2031)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_117/A1 (786:917:1048)(786:917:1048)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_117/A0 (786:917:1048)(786:917:1048)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_118/B1 (1156:1326:1497)(1156:1326:1497)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_118/B0 (1156:1326:1497)(1156:1326:1497)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_119/B1 (1067:1226:1386)(1067:1226:1386)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_119/B0 (1067:1226:1386)(1067:1226:1386)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_120/A1 (786:917:1048)(786:917:1048)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_120/A0 (786:917:1048)(786:917:1048)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_121/A1 (1931:2161:2392)(1931:2161:2392)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_121/A0 (1931:2161:2392)(1931:2161:2392)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_127/C1 (1929:2179:2429)(1929:2179:2429)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_127/C0 (1929:2179:2429)(1929:2179:2429)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_129/D1 (1689:1860:2031)(1689:1860:2031)) - (INTERCONNECT SLICE_33/Q0 ram2e_ufm\/SLICE_129/D0 (1689:1860:2031)(1689:1860:2031)) - (INTERCONNECT SLICE_33/Q0 SLICE_138/C1 (2107:2359:2612)(2107:2359:2612)) - (INTERCONNECT SLICE_33/Q0 SLICE_138/C0 (2107:2359:2612)(2107:2359:2612)) - (INTERCONNECT ram2e_ufm\/CKE_7\/SLICE_61/OFX0 SLICE_9/D0 (857:949:1042) - (857:949:1042)) - (INTERCONNECT SLICE_9/F0 SLICE_9/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_9/Q0 CKEout_MGIOL/OPOS (1081:1188:1296)(1081:1188:1296)) - (INTERCONNECT SLICE_9/F1 ram2e_ufm\/SLICE_56/CE (1172:1292:1412)(1172:1292:1412)) - (INTERCONNECT SLICE_31/Q0 SLICE_10/D0 (795:880:965)(795:880:965)) - (INTERCONNECT SLICE_31/Q0 SLICE_18/B1 (1437:1625:1813)(1437:1625:1813)) - (INTERCONNECT SLICE_31/Q0 SLICE_18/B0 (1437:1625:1813)(1437:1625:1813)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/M0 - (1487:1630:1774)(1487:1630:1774)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_77/B1 (1437:1625:1813)(1437:1625:1813)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_79/C0 (2267:2540:2814)(2267:2540:2814)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_80/D0 (1886:2072:2259)(1886:2072:2259)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_83/B0 (1437:1625:1813)(1437:1625:1813)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_130/C1 (1576:1783:1990)(1576:1783:1990)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_130/C0 (1576:1783:1990)(1576:1783:1990)) - (INTERCONNECT SLICE_31/Q0 ram2e_ufm\/SLICE_133/A1 (2139:2388:2637)(2139:2388:2637)) - (INTERCONNECT SLICE_10/Q0 SLICE_10/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_10/Q0 SLICE_18/C1 (552:669:786)(552:669:786)) - (INTERCONNECT SLICE_10/Q0 SLICE_18/D0 (528:582:636)(528:582:636)) - (INTERCONNECT SLICE_10/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/C0 - (552:669:786)(552:669:786)) - (INTERCONNECT SLICE_10/F0 SLICE_10/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_10/CE (882:979:1076)(882:979:1076)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_18/CE (1647:1803:1960)(1647:1803:1960)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F1 SLICE_18/CE (1647:1803:1960)(1647:1803:1960)) - (INTERCONNECT SLICE_10/F1 nCSout_I/PADDO (1694:1892:2090)(1694:1892:2090)) - (INTERCONNECT SLICE_11/Q0 SLICE_11/B1 (796:925:1054)(796:925:1054)) - (INTERCONNECT SLICE_11/Q0 SLICE_11/B0 (796:925:1054)(796:925:1054)) - (INTERCONNECT SLICE_11/Q0 SLICE_26/D1 (554:615:676)(554:615:676)) - (INTERCONNECT SLICE_11/Q0 SLICE_26/D0 (554:615:676)(554:615:676)) - (INTERCONNECT SLICE_11/Q0 ram2e_ufm\/SLICE_91/D1 (533:592:652)(533:592:652)) - (INTERCONNECT SLICE_26/Q1 SLICE_11/A1 (756:882:1009)(756:882:1009)) - (INTERCONNECT SLICE_26/Q1 SLICE_11/A0 (756:882:1009)(756:882:1009)) - (INTERCONNECT SLICE_26/Q1 SLICE_26/A1 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_26/Q1 SLICE_26/A0 (756:882:1009)(756:882:1009)) - (INTERCONNECT SLICE_26/Q1 ram2e_ufm\/SLICE_91/B1 (777:906:1036)(777:906:1036)) - (INTERCONNECT SLICE_26/Q0 SLICE_11/D0 (525:582:639)(525:582:639)) - (INTERCONNECT SLICE_26/Q0 SLICE_26/B1 (778:905:1032)(778:905:1032)) - (INTERCONNECT SLICE_26/Q0 SLICE_26/B0 (778:905:1032)(778:905:1032)) - (INTERCONNECT SLICE_26/Q0 ram2e_ufm\/CKE_7\/SLICE_61/A1 (751:878:1006) - (751:878:1006)) - (INTERCONNECT SLICE_26/Q0 ram2e_ufm\/SLICE_91/C1 (879:1031:1183)(879:1031:1183)) - (INTERCONNECT SLICE_11/F0 SLICE_11/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_11/CE (1245:1369:1494)(1245:1369:1494)) - (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_26/CE (1245:1369:1494)(1245:1369:1494)) - (INTERCONNECT ram2e_ufm\/SLICE_118/F1 SLICE_26/CE (1245:1369:1494)(1245:1369:1494)) - (INTERCONNECT SLICE_11/F1 ram2e_ufm\/CKE_7\/SLICE_61/C1 (541:653:766)(541:653:766)) - (INTERCONNECT SLICE_13/F1 SLICE_12/D1 (520:573:626)(520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_62/F1 SLICE_12/C1 (534:645:756)(534:645:756)) - (INTERCONNECT ram2e_ufm\/SLICE_62/F1 ram2e_ufm\/SLICE_62/D0 (523:579:635) - (523:579:635)) - (INTERCONNECT ram2e_ufm\/SLICE_84/F1 SLICE_12/B1 (781:910:1039)(781:910:1039)) - (INTERCONNECT ram2e_ufm\/SLICE_84/F1 ram2e_ufm\/SLICE_84/C0 (280:362:445) - (280:362:445)) - (INTERCONNECT ram2e_ufm\/SLICE_84/F1 ram2e_ufm\/SLICE_87/B0 (1108:1272:1436) - (1108:1272:1436)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_12/A1 (751:875:999)(751:875:999)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_12/B0 (1110:1271:1433)(1110:1271:1433)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_13/C1 (890:1040:1191)(890:1040:1191)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F1 SLICE_13/C0 (890:1040:1191)(890:1040:1191)) - (INTERCONNECT SLICE_12/Q1 SLICE_12/D0 (550:615:680)(550:615:680)) - (INTERCONNECT SLICE_12/Q1 SLICE_13/B1 (792:925:1058)(792:925:1058)) - (INTERCONNECT SLICE_12/Q1 SLICE_13/B0 (792:925:1058)(792:925:1058)) - (INTERCONNECT SLICE_12/Q1 SLICE_19/C1 (817:971:1125)(817:971:1125)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_40/D1 (532:590:648)(532:590:648)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/D1 (534:598:662) - (534:598:662)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_62/C1 (561:681:801)(561:681:801)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_62/C0 (561:681:801)(561:681:801)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_65/B0 (1375:1577:1779)(1375:1577:1779)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_84/B0 (776:908:1040)(776:908:1040)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_87/A0 (760:890:1021)(760:890:1021)) - (INTERCONNECT SLICE_12/Q1 ram2e_ufm\/SLICE_101/B0 (776:908:1040)(776:908:1040)) - (INTERCONNECT ram2e_ufm\/SLICE_63/F0 SLICE_12/C0 (541:653:766)(541:653:766)) - (INTERCONNECT SLICE_13/Q0 SLICE_12/A0 (766:894:1023)(766:894:1023)) - (INTERCONNECT SLICE_13/Q0 SLICE_13/A1 (766:894:1023)(766:894:1023)) - (INTERCONNECT SLICE_13/Q0 SLICE_13/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_13/Q0 SLICE_15/B1 (1042:1199:1356)(1042:1199:1356)) - (INTERCONNECT SLICE_13/Q0 SLICE_19/A1 (1754:1973:2192)(1754:1973:2192)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_40/B1 (1797:2019:2242)(1797:2019:2242)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_62/A1 (766:894:1023)(766:894:1023)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_62/A0 (766:894:1023)(766:894:1023)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_63/B1 (1760:1987:2214)(1760:1987:2214)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_83/D1 (1555:1709:1864)(1555:1709:1864)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_84/B1 (1760:1987:2214)(1760:1987:2214)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_94/C0 (1566:1775:1985)(1566:1775:1985)) - (INTERCONNECT SLICE_13/Q0 ram2e_ufm\/SLICE_100/C0 (1191:1368:1545)(1191:1368:1545)) - (INTERCONNECT SLICE_12/F1 SLICE_12/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_12/F0 SLICE_12/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_12/LSR (887:985:1084)(887:985:1084)) - (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_12/LSR (887:985:1084)(887:985:1084)) - (INTERCONNECT ram2e_ufm\/SLICE_82/F0 SLICE_13/LSR (887:985:1084)(887:985:1084)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_40/C1 (570:687:804)(570:687:804)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/C1 - (570:687:804)(570:687:804)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_63/D1 (1625:1786:1947)(1625:1786:1947)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_63/A0 (736:853:971)(736:853:971)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_65/D1 (934:1028:1123)(934:1028:1123)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_65/D0 (934:1028:1123)(934:1028:1123)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_77/D1 (886:983:1080)(886:983:1080)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_82/C1 (570:687:804)(570:687:804)) - (INTERCONNECT SLICE_12/Q0 ram2e_ufm\/SLICE_83/C0 (570:687:804)(570:687:804)) - (INTERCONNECT ram2e_ufm\/SLICE_87/F1 SLICE_13/D1 (273:306:340)(273:306:340)) - (INTERCONNECT ram2e_ufm\/SLICE_87/F1 SLICE_13/D0 (527:589:651)(527:589:651)) - (INTERCONNECT ram2e_ufm\/SLICE_87/F1 ram2e_ufm\/SLICE_62/B0 (769:899:1029) - (769:899:1029)) - (INTERCONNECT ram2e_ufm\/SLICE_87/F1 ram2e_ufm\/SLICE_87/C0 (284:372:461) - (284:372:461)) - (INTERCONNECT SLICE_13/F0 SLICE_13/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_40/F1 SLICE_14/C1 (811:957:1103)(811:957:1103)) - (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_39/B0 (777:908:1040) - (777:908:1040)) - (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_40/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_40/F1 ram2e_ufm\/SLICE_41/D0 (800:891:982) - (800:891:982)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_14/B1 (1956:2151:2346)(1956:2151:2346)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_16/A1 (1929:2122:2315)(1929:2122:2315)) - (INTERCONNECT Din\[5\]_I/PADDI SLICE_29/A1 (2251:2478:2706)(2251:2478:2706)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_39/B1 (1956:2151:2346) - (1956:2151:2346)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_45/B1 (2326:2553:2780) - (2326:2553:2780)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_49/B1 (2690:2948:3207) - (2690:2948:3207)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/A1 - (2267:2497:2727)(2267:2497:2727)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/D0 - (1719:1846:1974)(1719:1846:1974)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_100/B1 (2320:2546:2773) - (2320:2546:2773)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_101/B1 (2299:2531:2764) - (2299:2531:2764)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_116/B1 (1961:2156:2352) - (1961:2156:2352)) - (INTERCONNECT Din\[5\]_I/PADDI ram2e_ufm\/SLICE_147/C0 (2052:2269:2486) - (2052:2269:2486)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_14/A1 (2246:2470:2695)(2246:2470:2695)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_16/B1 (3038:3331:3624)(3038:3331:3624)) - (INTERCONNECT Din\[3\]_I/PADDI SLICE_28/B1 (3408:3733:4058)(3408:3733:4058)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_39/D1 (2733:2959:3185) - (2733:2959:3185)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_44/B1 (3408:3733:4058) - (3408:3733:4058)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_48/A1 (3006:3296:3587) - (3006:3296:3587)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/B1 - (2663:2923:3184)(2663:2923:3184)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/B0 - (2663:2923:3184)(2663:2923:3184)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_100/C1 (2036:2249:2462) - (2036:2249:2462)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_101/C1 (2759:3041:3324) - (2759:3041:3324)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_116/A1 (2958:3251:3544) - (2958:3251:3544)) - (INTERCONNECT Din\[3\]_I/PADDI ram2e_ufm\/SLICE_141/B0 (2648:2907:3166) - (2648:2907:3166)) - (INTERCONNECT ram2e_ufm\/SLICE_142/F1 SLICE_14/D0 (266:290:315)(266:290:315)) - (INTERCONNECT SLICE_14/F1 SLICE_14/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_14/F1 SLICE_17/C1 (537:645:753)(537:645:753)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_14/B0 (2210:2433:2656)(2210:2433:2656)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_15/A1 (1871:2055:2240)(1871:2055:2240)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_15/A0 (1871:2055:2240)(1871:2055:2240)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_16/D1 (1661:1780:1899)(1661:1780:1899)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_16/D0 (1661:1780:1899)(1661:1780:1899)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_17/D0 (2031:2182:2333)(2031:2182:2333)) - (INTERCONNECT Din\[1\]_I/PADDI SLICE_27/A1 (2173:2393:2613)(2173:2393:2613)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_39/D0 (2401:2584:2767) - (2401:2584:2767)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_41/A1 (2505:2760:3016) - (2505:2760:3016)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_43/B1 (1872:2056:2240) - (1872:2056:2240)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_47/A1 (2162:2380:2598) - (2162:2380:2598)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/M0 - (1626:1733:1841)(1626:1733:1841)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_87/B1 (2537:2795:3053) - (2537:2795:3053)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_100/D1 (2290:2479:2669) - (2290:2479:2669)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_116/A0 (1871:2055:2240) - (1871:2055:2240)) - (INTERCONNECT Din\[1\]_I/PADDI ram2e_ufm\/SLICE_143/D1 (2765:2979:3194) - (2765:2979:3194)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_14/A0 (2284:2506:2729)(2284:2506:2729)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_17/A1 (1915:2105:2296)(1915:2105:2296)) - (INTERCONNECT Din\[2\]_I/PADDI SLICE_28/D0 (1636:1752:1869)(1636:1752:1869)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_39/A0 (2981:3270:3560) - (2981:3270:3560)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_41/B1 (2316:2541:2766) - (2316:2541:2766)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_42/D1 (1641:1758:1875) - (1641:1758:1875)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_44/B0 (3037:3330:3623) - (3037:3330:3623)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_48/C0 (2016:2219:2423) - (2016:2219:2423)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_100/A1 (2210:2423:2637) - (2210:2423:2637)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_116/B0 (1947:2140:2333) - (1947:2140:2333)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_133/D1 (2016:2165:2315) - (2016:2165:2315)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_133/D0 (2016:2165:2315) - (2016:2165:2315)) - (INTERCONNECT Din\[2\]_I/PADDI ram2e_ufm\/SLICE_144/A1 (2981:3270:3560) - (2981:3270:3560)) - (INTERCONNECT SLICE_14/F0 SLICE_14/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_14/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_15/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_16/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_17/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_27/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_27/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_28/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_28/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_29/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_29/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_30/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 SLICE_30/CE (1815:2020:2225)(1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_39/CE (1815:2020:2225) - (1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_40/CE (1815:2020:2225) - (1815:2020:2225)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F1 ram2e_ufm\/SLICE_41/CE (1815:2020:2225) - (1815:2020:2225)) - (INTERCONNECT SLICE_14/Q0 ram2e_ufm\/SLICE_147/D1 (520:573:626)(520:573:626)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_15/C1 (2190:2401:2613)(2190:2401:2613)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_15/C0 (2190:2401:2613)(2190:2401:2613)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_16/C1 (2517:2763:3010)(2517:2763:3010)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_16/B0 (2421:2645:2870)(2421:2645:2870)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_17/B0 (2785:3041:3297)(2785:3041:3297)) - (INTERCONNECT Din\[7\]_I/PADDI SLICE_30/B1 (2406:2629:2852)(2406:2629:2852)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_41/B0 (1955:2151:2347) - (1955:2151:2347)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_46/B1 (2776:3031:3286) - (2776:3031:3286)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_50/B1 (3140:3426:3713) - (3140:3426:3713)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/A0 - (2389:2611:2833)(2389:2611:2833)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_94/D1 (2534:2721:2908) - (2534:2721:2908)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_100/B0 (2776:3031:3286) - (2776:3031:3286)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_142/B1 (1955:2151:2347) - (1955:2151:2347)) - (INTERCONNECT Din\[7\]_I/PADDI ram2e_ufm\/SLICE_143/D0 (2071:2230:2389) - (2071:2230:2389)) - (INTERCONNECT SLICE_17/F1 SLICE_15/D0 (539:600:661)(539:600:661)) - (INTERCONNECT SLICE_17/F1 SLICE_16/C0 (550:666:782)(550:666:782)) - (INTERCONNECT SLICE_17/F1 SLICE_17/C0 (280:362:445)(280:362:445)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_15/B0 (1827:2026:2225)(1827:2026:2225)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_16/A0 (1795:1991:2188)(1795:1991:2188)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_17/A0 (2165:2393:2622)(2165:2393:2622)) - (INTERCONNECT Din\[4\]_I/PADDI SLICE_29/A0 (3295:3621:3948)(3295:3621:3948)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_41/D1 (2678:2912:3147) - (2678:2912:3147)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_45/C0 (3423:3774:4125) - (3423:3774:4125)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_49/C0 (3460:3807:4155) - (3460:3807:4155)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_84/D1 (2710:2938:3167) - (2710:2938:3167)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_94/C1 (2711:2993:3276) - (2711:2993:3276)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_100/A0 (2910:3203:3496) - (2910:3203:3496)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_133/B1 (2952:3248:3545) - (2952:3248:3545)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_133/B0 (2952:3248:3545) - (2952:3248:3545)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_142/D1 (2678:2912:3147) - (2678:2912:3147)) - (INTERCONNECT Din\[4\]_I/PADDI ram2e_ufm\/SLICE_142/D0 (2678:2912:3147) - (2678:2912:3147)) - (INTERCONNECT SLICE_15/F0 SLICE_15/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_15/Q0 ram2e_ufm\/SLICE_79/D1 (1116:1235:1355)(1116:1235:1355)) - (INTERCONNECT SLICE_15/F1 ram2e_ufm\/SLICE_101/C0 (868:1015:1163)(868:1015:1163)) - (INTERCONNECT SLICE_16/F0 SLICE_16/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_16/Q0 ram2e_ufm\/SLICE_85/A0 (740:863:986)(740:863:986)) - (INTERCONNECT SLICE_16/F1 ram2e_ufm\/SLICE_84/A1 (736:854:973)(736:854:973)) - (INTERCONNECT SLICE_16/F1 ram2e_ufm\/SLICE_101/A0 (1070:1231:1392)(1070:1231:1392)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_17/B1 (1956:2151:2346)(1956:2151:2346)) - (INTERCONNECT Din\[0\]_I/PADDI SLICE_27/A0 (2256:2484:2712)(2256:2484:2712)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_39/C1 (2438:2689:2941) - (2438:2689:2941)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_41/C1 (2438:2689:2941) - (2438:2689:2941)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_42/A1 (2631:2891:3152) - (2631:2891:3152)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_42/D0 (2094:2254:2414) - (2094:2254:2414)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_43/D0 (2785:3011:3238) - (2785:3011:3238)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_65/C1 (1730:1912:2095) - (1730:1912:2095)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_86/C1 (1714:1895:2076) - (1714:1895:2076)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_94/D0 (2453:2644:2835) - (2453:2644:2835)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_116/C0 (1725:1907:2089) - (1725:1907:2089)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_133/C1 (1730:1912:2095) - (1730:1912:2095)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_141/C1 (2438:2689:2941) - (2438:2689:2941)) - (INTERCONNECT Din\[0\]_I/PADDI ram2e_ufm\/SLICE_142/C1 (2438:2689:2941) - (2438:2689:2941)) - (INTERCONNECT SLICE_17/F0 SLICE_17/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_17/Q0 ram2e_ufm\/SLICE_147/B1 (765:883:1001)(765:883:1001)) - (INTERCONNECT SLICE_18/Q0 SLICE_18/D1 (534:591:648)(534:591:648)) - (INTERCONNECT SLICE_18/Q0 SLICE_18/A0 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_18/Q0 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/A0 - (744:866:989)(744:866:989)) - (INTERCONNECT SLICE_18/Q1 SLICE_18/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_18/Q1 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/B0 - (765:888:1011)(765:888:1011)) - (INTERCONNECT SLICE_18/F1 SLICE_18/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_18/F0 SLICE_18/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 SLICE_19/C0 (809:960:1112)(809:960:1112)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 SLICE_31/C1 (546:675:804)(546:675:804)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_95/C0 (546:675:804) - (546:675:804)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_96/C0 (286:377:469) - (286:377:469)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_132/B1 (517:621:726) - (517:621:726)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_132/A0 (485:587:689) - (485:587:689)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_140/C1 (818:982:1146) - (818:982:1146)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F1 ram2e_ufm\/SLICE_140/C0 (818:982:1146) - (818:982:1146)) - (INTERCONNECT SLICE_20/Q1 SLICE_19/A0 (1002:1154:1306)(1002:1154:1306)) - (INTERCONNECT SLICE_20/Q1 RAout\[1\]_MGIOL/OPOS (1411:1555:1700)(1411:1555:1700)) - (INTERCONNECT SLICE_34/Q1 SLICE_19/M0 (1132:1257:1382)(1132:1257:1382)) - (INTERCONNECT SLICE_34/Q1 SLICE_34/A1 (483:579:675)(483:579:675)) - (INTERCONNECT SLICE_34/Q1 SLICE_34/A0 (748:874:1001)(748:874:1001)) - (INTERCONNECT SLICE_34/Q1 SLICE_35/A0 (748:874:1001)(748:874:1001)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_42/A0 (2182:2464:2746)(2182:2464:2746)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_43/A1 (1799:2030:2261)(1799:2030:2261)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_43/A0 (1799:2030:2261)(1799:2030:2261)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_44/A1 (2182:2464:2746)(2182:2464:2746)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_44/D0 (1624:1801:1979)(1624:1801:1979)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_45/A1 (1799:2030:2261)(1799:2030:2261)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_45/A0 (1799:2030:2261)(1799:2030:2261)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_46/A1 (1799:2030:2261)(1799:2030:2261)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_46/A0 (1799:2030:2261)(1799:2030:2261)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_51/D0 (1624:1801:1979)(1624:1801:1979)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_56/A1 (1439:1639:1839)(1439:1639:1839)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_69/A0 (1439:1639:1839)(1439:1639:1839)) - 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(INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_115/A0 (2199:2465:2731)(2199:2465:2731)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_117/B1 (2621:2923:3226)(2621:2923:3226)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_117/B0 (2621:2923:3226)(2621:2923:3226)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_118/A1 (2589:2889:3189)(2589:2889:3189)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_118/A0 (2589:2889:3189)(2589:2889:3189)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_119/A1 (1439:1639:1839)(1439:1639:1839)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_119/A0 (1439:1639:1839)(1439:1639:1839)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_120/D1 (2379:2613:2848)(2379:2613:2848)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_120/D0 (2379:2613:2848)(2379:2613:2848)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_121/B1 (1071:1238:1406)(1071:1238:1406)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_121/B0 (1071:1238:1406)(1071:1238:1406)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_127/B1 (1851:2086:2322)(1851:2086:2322)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_127/B0 (1851:2086:2322)(1851:2086:2322)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_135/D1 (1609:1776:1944)(1609:1776:1944)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_135/D0 (1609:1776:1944)(1609:1776:1944)) - (INTERCONNECT SLICE_34/Q1 ram2e_ufm\/SLICE_136/C1 (1178:1369:1561)(1178:1369:1561)) - (INTERCONNECT SLICE_34/Q1 SLICE_138/B1 (774:904:1034)(774:904:1034)) - (INTERCONNECT SLICE_138/F0 SLICE_19/LSR (1135:1258:1382)(1135:1258:1382)) - (INTERCONNECT SLICE_19/F0 SLICE_20/C1 (800:939:1079)(800:939:1079)) - (INTERCONNECT SLICE_19/Q0 ram2e_ufm\/SLICE_136/A0 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_19/F1 ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/B1 - (775:903:1032)(775:903:1032)) - (INTERCONNECT SLICE_19/F1 ram2e_ufm\/SLICE_65/A1 (736:854:973)(736:854:973)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_20/D1 (897:1007:1118)(897:1007:1118)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_21/B0 (774:904:1034)(774:904:1034)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_22/A1 (749:884:1019)(749:884:1019)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 SLICE_31/A1 (485:587:689)(485:587:689)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_95/B0 (517:621:726) - (517:621:726)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_96/D0 (897:1007:1118) - (897:1007:1118)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_132/D1 (897:1007:1118) - (897:1007:1118)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F1 ram2e_ufm\/SLICE_132/D0 (897:1007:1118) - (897:1007:1118)) - (INTERCONNECT Ain\[1\]_I/PADDI SLICE_20/B1 (2708:2959:3210)(2708:2959:3210)) - (INTERCONNECT ram2e_ufm\/SLICE_107/F0 SLICE_20/A1 (733:848:964)(733:848:964)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_20/D0 (528:584:640)(528:584:640)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_21/C1 (541:658:775)(541:658:775)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_22/A0 (740:867:995)(740:867:995)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_23/A1 (1083:1249:1415)(1083:1249:1415)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F1 SLICE_23/A0 (1083:1249:1415)(1083:1249:1415)) - (INTERCONNECT ram2e_ufm\/SLICE_124/F0 SLICE_20/C0 (534:639:744)(534:639:744)) - (INTERCONNECT ram2e_ufm\/SLICE_132/F1 SLICE_20/A0 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_20/F1 SLICE_20/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_20/F0 SLICE_20/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_20/CE (901:1003:1106)(901:1003:1106)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_20/CE (901:1003:1106)(901:1003:1106)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_21/CE (1265:1399:1533)(1265:1399:1533)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_21/CE (1265:1399:1533)(1265:1399:1533)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_22/CE (1265:1399:1533)(1265:1399:1533)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_22/CE (1265:1399:1533)(1265:1399:1533)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_23/CE (901:1003:1106)(901:1003:1106)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_23/CE (901:1003:1106)(901:1003:1106)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_24/CE (1618:1781:1945)(1618:1781:1945)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_24/CE (1618:1781:1945)(1618:1781:1945)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_25/CE (1242:1369:1496)(1242:1369:1496)) - (INTERCONNECT ram2e_ufm\/SLICE_119/F0 SLICE_25/CE (1242:1369:1496)(1242:1369:1496)) - (INTERCONNECT SLICE_20/Q0 SLICE_31/B0 (770:896:1022)(770:896:1022)) - (INTERCONNECT SLICE_20/Q0 ram2e_ufm\/SLICE_132/A1 (733:853:974)(733:853:974)) - (INTERCONNECT SLICE_20/Q0 RAout\[0\]_MGIOL/OPOS (1342:1481:1620)(1342:1481:1620)) - (INTERCONNECT SLICE_31/F1 SLICE_21/B1 (772:897:1023)(772:897:1023)) - (INTERCONNECT ram2e_ufm\/SLICE_140/F1 SLICE_21/D0 (266:290:315)(266:290:315)) - (INTERCONNECT ram2e_ufm\/SLICE_134/F0 SLICE_21/C0 (800:939:1079)(800:939:1079)) - (INTERCONNECT Ain\[2\]_I/PADDI SLICE_21/A0 (2594:2847:3101)(2594:2847:3101)) - (INTERCONNECT SLICE_21/F1 SLICE_21/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_21/F0 SLICE_21/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_21/Q0 ram2e_ufm\/SLICE_140/A1 (733:853:974)(733:853:974)) - (INTERCONNECT SLICE_21/Q0 RAout\[2\]_MGIOL/OPOS (1340:1473:1606)(1340:1473:1606)) - (INTERCONNECT SLICE_21/Q1 SLICE_31/D1 (539:599:659)(539:599:659)) - (INTERCONNECT SLICE_21/Q1 SLICE_31/D0 (539:599:659)(539:599:659)) - (INTERCONNECT SLICE_21/Q1 RAout\[3\]_MGIOL/OPOS (1084:1193:1303)(1084:1193:1303)) - (INTERCONNECT ram2e_ufm\/SLICE_140/F0 SLICE_22/D1 (520:573:626)(520:573:626)) - (INTERCONNECT Ain\[5\]_I/PADDI SLICE_22/C1 (1530:1696:1862)(1530:1696:1862)) - (INTERCONNECT ram2e_ufm\/SLICE_124/F1 SLICE_22/B1 (1136:1293:1450)(1136:1293:1450)) - (INTERCONNECT ram2e_ufm\/SLICE_95/F0 SLICE_22/C0 (868:1015:1163)(868:1015:1163)) - (INTERCONNECT SLICE_22/F1 SLICE_22/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_22/F0 SLICE_22/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_22/Q0 ram2e_ufm\/SLICE_95/A0 (1177:1341:1505)(1177:1341:1505)) - (INTERCONNECT SLICE_22/Q0 RAout\[4\]_MGIOL/OPOS (1667:1835:2003)(1667:1835:2003)) - (INTERCONNECT SLICE_22/Q1 ram2e_ufm\/SLICE_140/D0 (523:578:633)(523:578:633)) - (INTERCONNECT SLICE_22/Q1 RAout\[5\]_MGIOL/OPOS (1084:1193:1303)(1084:1193:1303)) - (INTERCONNECT ram2e_ufm\/SLICE_132/F0 SLICE_23/C1 (531:639:747)(531:639:747)) - (INTERCONNECT ram2e_ufm\/SLICE_96/F0 SLICE_23/C0 (531:639:747)(531:639:747)) - (INTERCONNECT SLICE_23/F1 SLICE_23/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_23/F0 SLICE_23/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_23/Q0 ram2e_ufm\/SLICE_96/B0 (765:888:1011)(765:888:1011)) - (INTERCONNECT SLICE_23/Q0 RAout\[6\]_MGIOL/OPOS (1786:1945:2105)(1786:1945:2105)) - (INTERCONNECT SLICE_23/Q1 ram2e_ufm\/SLICE_132/B0 (765:888:1011)(765:888:1011)) - (INTERCONNECT SLICE_23/Q1 RAout\[7\]_MGIOL/OPOS (1411:1555:1700)(1411:1555:1700)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F0 SLICE_24/D1 (536:594:652)(536:594:652)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F0 SLICE_25/D1 (536:594:652)(536:594:652)) - (INTERCONNECT ram2e_ufm\/SLICE_146/F1 SLICE_24/B1 (1136:1293:1450)(1136:1293:1450)) - (INTERCONNECT SLICE_24/Q1 SLICE_24/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_24/Q1 RAout\[9\]_MGIOL/OPOS (1340:1473:1606)(1340:1473:1606)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F0 SLICE_24/D0 (964:1060:1157)(964:1060:1157)) - (INTERCONNECT SLICE_24/Q0 SLICE_24/C0 (534:644:754)(534:644:754)) - (INTERCONNECT SLICE_24/Q0 RAout\[8\]_MGIOL/OPOS (1411:1555:1700)(1411:1555:1700)) - (INTERCONNECT ram2e_ufm\/SLICE_127/F0 SLICE_24/B0 (772:897:1023)(772:897:1023)) - (INTERCONNECT ram2e_ufm\/SLICE_115/F1 SLICE_24/A0 (733:854:976)(733:854:976)) - (INTERCONNECT ram2e_ufm\/SLICE_115/F1 ram2e_ufm\/SLICE_115/C0 (280:362:445) - (280:362:445)) - (INTERCONNECT SLICE_24/F1 SLICE_24/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_24/F0 SLICE_24/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_29/Q0 SLICE_25/C1 (1269:1444:1620)(1269:1444:1620)) - (INTERCONNECT ram2e_ufm\/SLICE_74/F0 SLICE_25/B1 (513:611:710)(513:611:710)) - (INTERCONNECT ram2e_ufm\/SLICE_74/F0 ram2e_ufm\/SLICE_74/C1 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_74/F0 ram2e_ufm\/SLICE_146/A1 (1331:1522:1713) - (1331:1522:1713)) - (INTERCONNECT SLICE_25/Q1 SLICE_25/A1 (479:571:663)(479:571:663)) - (INTERCONNECT SLICE_25/Q1 RAout\[11\]_MGIOL/OPOS (1775:1951:2127)(1775:1951:2127)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F0 SLICE_25/D0 (523:573:623)(523:573:623)) - (INTERCONNECT ram2e_ufm\/SLICE_74/F1 SLICE_25/C0 (531:639:747)(531:639:747)) - (INTERCONNECT ram2e_ufm\/SLICE_106/F0 SLICE_25/B0 (762:883:1004)(762:883:1004)) - (INTERCONNECT ram2e_ufm\/SLICE_129/F0 SLICE_25/A0 (733:848:964)(733:848:964)) - (INTERCONNECT SLICE_25/F1 SLICE_25/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_25/F0 SLICE_25/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_25/Q0 ram2e_ufm\/SLICE_106/B0 (765:888:1011)(765:888:1011)) - (INTERCONNECT SLICE_25/Q0 RAout\[10\]_MGIOL/OPOS (1756:1937:2118)(1756:1937:2118)) - (INTERCONNECT SLICE_26/F1 SLICE_26/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_26/F0 SLICE_26/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_43/Q1 SLICE_27/D1 (964:1060:1157)(964:1060:1157)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_27/B1 (1042:1195:1349)(1042:1195:1349)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_27/B0 (1042:1195:1349)(1042:1195:1349)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/A1 (1395:1579:1764)(1395:1579:1764)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_28/A0 (1395:1579:1764)(1395:1579:1764)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_29/B1 (1797:2016:2235)(1797:2016:2235)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_29/B0 (1797:2016:2235)(1797:2016:2235)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/D1 (1185:1304:1423)(1185:1304:1423)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F1 SLICE_30/D0 (1185:1304:1423)(1185:1304:1423)) - (INTERCONNECT ram2e_ufm\/SLICE_43/Q0 SLICE_27/C0 (541:653:766)(541:653:766)) - (INTERCONNECT SLICE_27/F1 SLICE_27/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_27/F0 SLICE_27/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/C1 (1345:1528:1712)(1345:1528:1712)) - (INTERCONNECT SLICE_27/Q0 ram2e_ufm\/SLICE_120/C0 (1345:1528:1712)(1345:1528:1712)) - (INTERCONNECT SLICE_27/Q1 ram2e_ufm\/SLICE_78/B0 (1031:1183:1336)(1031:1183:1336)) - (INTERCONNECT ram2e_ufm\/SLICE_44/Q1 SLICE_28/C1 (541:653:766)(541:653:766)) - (INTERCONNECT ram2e_ufm\/SLICE_44/Q0 SLICE_28/C0 (541:653:766)(541:653:766)) - (INTERCONNECT SLICE_28/F1 SLICE_28/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_28/F0 SLICE_28/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_28/Q0 ram2e_ufm\/SLICE_146/C1 (868:1015:1163)(868:1015:1163)) - (INTERCONNECT SLICE_28/Q1 ram2e_ufm\/SLICE_74/D1 (894:983:1072)(894:983:1072)) - (INTERCONNECT ram2e_ufm\/SLICE_45/Q1 SLICE_29/C1 (975:1126:1278)(975:1126:1278)) - (INTERCONNECT ram2e_ufm\/SLICE_45/Q0 SLICE_29/C0 (541:653:766)(541:653:766)) - (INTERCONNECT SLICE_29/F1 SLICE_29/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_29/F0 SLICE_29/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_29/Q1 ram2e_ufm\/SLICE_72/D1 (1410:1533:1656)(1410:1533:1656)) - (INTERCONNECT ram2e_ufm\/SLICE_46/Q1 SLICE_30/A1 (740:863:986)(740:863:986)) - (INTERCONNECT Din\[6\]_I/PADDI SLICE_30/B0 (1767:1946:2126)(1767:1946:2126)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_40/A1 (2544:2801:3059) - (2544:2801:3059)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_42/B1 (3316:3640:3964) - (3316:3640:3964)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_46/B0 (2946:3238:3530) - (2946:3238:3530)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_50/C0 (3449:3791:4134) - (3449:3791:4134)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/D1 - (3010:3267:3524)(3010:3267:3524)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_62/D1 (2698:2921:3145) - (2698:2921:3145)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_65/B1 (2561:2819:3078) - (2561:2819:3078)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_82/D1 (2334:2526:2718) - (2334:2526:2718)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_83/C1 (2345:2592:2839) - (2345:2592:2839)) - (INTERCONNECT Din\[6\]_I/PADDI ram2e_ufm\/SLICE_144/D0 (2313:2503:2693) - (2313:2503:2693)) - (INTERCONNECT ram2e_ufm\/SLICE_46/Q0 SLICE_30/A0 (740:863:986)(740:863:986)) - (INTERCONNECT SLICE_30/F1 SLICE_30/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_30/F0 SLICE_30/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_30/Q0 ram2e_ufm\/SLICE_129/A1 (1174:1336:1498)(1174:1336:1498)) - (INTERCONNECT SLICE_30/Q1 ram2e_ufm\/SLICE_127/A0 (999:1149:1299)(999:1149:1299)) - (INTERCONNECT Ain\[3\]_I/PADDI SLICE_31/B1 (2626:2882:3138)(2626:2882:3138)) - (INTERCONNECT nC07X_I/PADDI SLICE_31/C0 (2424:2651:2878)(2424:2651:2878)) - (INTERCONNECT nWE_I/PADDI SLICE_31/A0 (2889:3153:3417)(2889:3153:3417)) - (INTERCONNECT nWE_I/PADDI SLICE_36/A0 (3270:3567:3864)(3270:3567:3864)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/CKE_7\/SLICE_61/D0 (3398:3666:3935) - (3398:3666:3935)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_92/D1 (3398:3666:3935)(3398:3666:3935)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_112/B0 (3780:4129:4479)(3780:4129:4479)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_113/B0 (3629:3963:4298)(3629:3963:4298)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_136/B1 (4416:4832:5248)(4416:4832:5248)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_136/B0 (4416:4832:5248)(4416:4832:5248)) - (INTERCONNECT nWE_I/PADDI ram2e_ufm\/SLICE_137/D1 (1782:1926:2070)(1782:1926:2070)) - (INTERCONNECT SLICE_31/F0 SLICE_31/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_127/F1 SLICE_31/CE (539:596:653)(539:596:653)) - (INTERCONNECT ram2e_ufm\/SLICE_110/F1 SLICE_32/D1 (535:598:662)(535:598:662)) - (INTERCONNECT ram2e_ufm\/SLICE_110/F1 ram2e_ufm\/SLICE_58/B1 (767:894:1021) - (767:894:1021)) - (INTERCONNECT ram2e_ufm\/SLICE_110/F1 ram2e_ufm\/SLICE_110/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_57/F1 SLICE_32/C1 (541:653:766)(541:653:766)) - (INTERCONNECT ram2e_ufm\/SLICE_131/F1 SLICE_32/B1 (1099:1259:1420)(1099:1259:1420)) - (INTERCONNECT ram2e_ufm\/SLICE_146/F0 SLICE_32/A1 (999:1149:1299)(999:1149:1299)) - (INTERCONNECT SLICE_32/F1 SLICE_32/C0 (277:356:436)(277:356:436)) - (INTERCONNECT SLICE_32/Q0 SLICE_32/A0 (481:575:669)(481:575:669)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_137/A1 (771:900:1030)(771:900:1030)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_137/A0 (771:900:1030)(771:900:1030)) - (INTERCONNECT SLICE_32/Q0 SLICE_139/D0 (528:582:636)(528:582:636)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_141/D1 (561:625:689)(561:625:689)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_141/D0 (561:625:689)(561:625:689)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_142/B0 (1173:1337:1501)(1173:1337:1501)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_143/B1 (1183:1348:1513)(1183:1348:1513)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_143/B0 (1183:1348:1513)(1183:1348:1513)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_144/B1 (1183:1348:1513)(1183:1348:1513)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_144/B0 (1183:1348:1513)(1183:1348:1513)) - (INTERCONNECT SLICE_32/Q0 ram2e_ufm\/SLICE_147/B0 (1173:1337:1501)(1173:1337:1501)) - (INTERCONNECT SLICE_32/F0 SLICE_32/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 SLICE_33/D1 (548:615:683)(548:615:683)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 SLICE_38/B1 (1038:1199:1361)(1038:1199:1361)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_78/D0 (527:589:651) - (527:589:651)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_79/B0 (1471:1674:1877) - (1471:1674:1877)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_105/B1 (1471:1674:1877) - (1471:1674:1877)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_106/D0 (548:615:683) - (548:615:683)) - (INTERCONNECT ram2e_ufm\/SLICE_78/F1 ram2e_ufm\/SLICE_135/A0 (758:891:1024) - (758:891:1024)) - (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_33/C1 (550:666:782)(550:666:782)) - (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_34/C1 (888:1041:1194)(888:1041:1194)) - (INTERCONNECT ram2e_ufm\/SLICE_106/F1 SLICE_34/C0 (888:1041:1194)(888:1041:1194)) - (INTERCONNECT ram2e_ufm\/SLICE_106/F1 ram2e_ufm\/SLICE_106/C0 (280:362:445) - (280:362:445)) - (INTERCONNECT ram2e_ufm\/SLICE_135/F1 SLICE_33/B1 (765:889:1013)(765:889:1013)) - (INTERCONNECT ram2e_ufm\/SLICE_135/F1 SLICE_33/C0 (280:362:445)(280:362:445)) - (INTERCONNECT SLICE_139/F0 SLICE_33/A1 (1010:1161:1312)(1010:1161:1312)) - (INTERCONNECT SLICE_139/F0 SLICE_33/A0 (1010:1161:1312)(1010:1161:1312)) - (INTERCONNECT SLICE_139/F0 SLICE_34/B1 (1380:1570:1761)(1380:1570:1761)) - (INTERCONNECT SLICE_139/F0 SLICE_34/B0 (1380:1570:1761)(1380:1570:1761)) - (INTERCONNECT ram2e_ufm\/SLICE_117/F1 SLICE_33/B0 (1099:1259:1420)(1099:1259:1420)) - (INTERCONNECT SLICE_33/F1 SLICE_33/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_33/F0 SLICE_33/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_34/Q0 SLICE_34/D1 (548:611:674)(548:611:674)) - (INTERCONNECT SLICE_34/Q0 SLICE_34/D0 (548:611:674)(548:611:674)) - (INTERCONNECT SLICE_34/Q0 SLICE_35/D0 (548:611:674)(548:611:674)) - (INTERCONNECT SLICE_34/Q0 SLICE_38/C1 (954:1108:1262)(954:1108:1262)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_47/C1 (2210:2470:2730)(2210:2470:2730)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_48/B1 (2441:2714:2987)(2441:2714:2987)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_48/B0 (2441:2714:2987)(2441:2714:2987)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_49/A1 (2809:3114:3420)(2809:3114:3420)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_49/A0 (2809:3114:3420)(2809:3114:3420)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_50/A1 (2784:3087:3390)(2784:3087:3390)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_50/A0 (2784:3087:3390)(2784:3087:3390)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_52/A0 (3179:3516:3854)(3179:3516:3854)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_53/A0 (2809:3114:3420)(2809:3114:3420)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_54/A1 (2809:3114:3420)(2809:3114:3420)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_56/LSR (845:960:1075)(845:960:1075)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_69/D0 (1196:1339:1482)(1196:1339:1482)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_71/A0 (1948:2190:2433)(1948:2190:2433)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_72/D0 (563:629:695)(563:629:695)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_74/C0 (545:674:803)(545:674:803)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_77/D0 (816:926:1036)(816:926:1036)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_78/C0 (837:1003:1169)(837:1003:1169)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_79/D0 (2938:3207:3476)(2938:3207:3476)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_86/A1 (3549:3918:4288)(3549:3918:4288)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_89/A0 (2779:3081:3384)(2779:3081:3384)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_90/A0 (2809:3114:3420)(2809:3114:3420)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_95/D1 (2086:2302:2518)(2086:2302:2518)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_96/D1 (826:937:1048)(826:937:1048)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_97/A0 (2779:3081:3384)(2779:3081:3384)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_98/A0 (2809:3114:3420)(2809:3114:3420)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_102/D1 (943:1042:1141)(943:1042:1141)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_106/A0 (744:883:1023)(744:883:1023)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_107/C1 (2113:2376:2640)(2113:2376:2640)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_109/A1 (3549:3918:4288)(3549:3918:4288)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_112/D0 (1196:1339:1482)(1196:1339:1482)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_113/D1 (1313:1444:1575)(1313:1444:1575)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_115/D1 (1313:1444:1575)(1313:1444:1575)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_117/D1 (563:629:695)(563:629:695)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_117/D0 (563:629:695)(563:629:695)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_118/D1 (563:629:695)(563:629:695)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_118/D0 (563:629:695)(563:629:695)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_119/D1 (826:937:1048)(826:937:1048)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_119/D0 (826:937:1048)(826:937:1048)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_121/D1 (816:926:1036)(816:926:1036)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_121/D0 (816:926:1036)(816:926:1036)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_127/D1 (2086:2302:2518)(2086:2302:2518)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_127/D0 (2086:2302:2518)(2086:2302:2518)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_135/C1 (549:665:781)(549:665:781)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_135/C0 (549:665:781)(549:665:781)) - (INTERCONNECT SLICE_34/Q0 SLICE_138/D0 (1180:1321:1463)(1180:1321:1463)) - (INTERCONNECT SLICE_34/Q0 ram2e_ufm\/SLICE_145/A1 (2809:3114:3420)(2809:3114:3420)) - (INTERCONNECT SLICE_34/F1 SLICE_34/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_34/F0 SLICE_34/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_138/F1 SLICE_35/LSR (876:972:1069)(876:972:1069)) - (INTERCONNECT SLICE_35/Q0 SLICE_139/C1 (905:1049:1193)(905:1049:1193)) - (INTERCONNECT SLICE_35/F1 BA\[1\]_MGIOL/LSR (1438:1586:1735)(1438:1586:1735)) - (INTERCONNECT SLICE_35/F1 BA\[0\]_MGIOL/LSR (1438:1586:1735)(1438:1586:1735)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_36/C1 (986:1144:1302)(986:1144:1302)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_37/B1 (783:915:1047)(783:915:1047)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 SLICE_38/A1 (1099:1267:1436)(1099:1267:1436)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_91/A0 (1099:1267:1436) - (1099:1267:1436)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_92/C0 (986:1144:1302) - (986:1144:1302)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_105/C1 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F0 ram2e_ufm\/SLICE_112/A1 (1099:1267:1436) - (1099:1267:1436)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_36/A1 (741:874:1008)(741:874:1008)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_37/C1 (814:972:1130)(814:972:1130)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 SLICE_38/A0 (1013:1181:1350)(1013:1181:1350)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/CKE_7\/SLICE_61/A0 (741:874:1008) - (741:874:1008)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/SLICE_92/B1 (777:908:1040) - (777:908:1040)) - (INTERCONNECT ram2e_ufm\/SLICE_113/F1 ram2e_ufm\/SLICE_113/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_69/F1 SLICE_36/D0 (789:873:958)(789:873:958)) - (INTERCONNECT ram2e_ufm\/SLICE_92/F0 SLICE_36/C0 (531:639:747)(531:639:747)) - (INTERCONNECT SLICE_36/F1 SLICE_36/B0 (762:883:1004)(762:883:1004)) - (INTERCONNECT SLICE_36/F0 SLICE_36/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_36/Q0 nCASout_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795)) - (INTERCONNECT ram2e_ufm\/SLICE_112/F0 SLICE_37/D0 (266:290:315)(266:290:315)) - (INTERCONNECT SLICE_38/F1 SLICE_37/C0 (534:645:756)(534:645:756)) - (INTERCONNECT SLICE_38/F1 SLICE_38/B0 (765:889:1013)(765:889:1013)) - (INTERCONNECT SLICE_37/F1 SLICE_37/B0 (762:883:1004)(762:883:1004)) - (INTERCONNECT ram2e_ufm\/SLICE_91/F0 SLICE_37/A0 (730:848:967)(730:848:967)) - (INTERCONNECT SLICE_37/F0 SLICE_37/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_37/Q0 nRASout_MGIOL/OPOS (1445:1584:1723)(1445:1584:1723)) - (INTERCONNECT ram2e_ufm\/SLICE_136/F1 SLICE_38/D1 (1116:1235:1355)(1116:1235:1355)) - (INTERCONNECT ram2e_ufm\/SLICE_105/F1 SLICE_38/D0 (523:573:623)(523:573:623)) - (INTERCONNECT ram2e_ufm\/SLICE_112/F1 SLICE_38/C0 (534:645:756)(534:645:756)) - (INTERCONNECT ram2e_ufm\/SLICE_112/F1 ram2e_ufm\/SLICE_112/C0 (280:362:445) - (280:362:445)) - (INTERCONNECT SLICE_38/F0 SLICE_38/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT SLICE_38/Q0 nRWEout_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795)) - (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_39/A1 (747:879:1011) - (747:879:1011)) - (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_87/A1 (740:864:989) - (740:864:989)) - (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_94/B0 (515:616:718) - (515:616:718)) - (INTERCONNECT ram2e_ufm\/SLICE_94/F1 ram2e_ufm\/SLICE_116/D1 (1160:1285:1410) - (1160:1285:1410)) - (INTERCONNECT ram2e_ufm\/SLICE_39/F1 ram2e_ufm\/SLICE_39/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_39/F0 ram2e_ufm\/SLICE_39/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_39/Q0 ram2e_ufm\/SLICE_80/B0 (1395:1579:1763) - (1395:1579:1763)) - (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_40/B0 (783:909:1036) - (783:909:1036)) - (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_62/B1 (783:909:1036) - (783:909:1036)) - (INTERCONNECT ram2e_ufm\/SLICE_116/F1 ram2e_ufm\/SLICE_83/B1 (783:909:1036) - (783:909:1036)) - (INTERCONNECT ram2e_ufm\/SLICE_40/F0 ram2e_ufm\/SLICE_40/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_51/A0 (1008:1160:1313) - (1008:1160:1313)) - (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_66/D0 (798:885:972) - (798:885:972)) - (INTERCONNECT ram2e_ufm\/SLICE_40/Q0 ram2e_ufm\/SLICE_130/B0 (1209:1375:1542) - (1209:1375:1542)) - (INTERCONNECT ram2e_ufm\/SLICE_41/F1 ram2e_ufm\/SLICE_41/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_41/A0 (1109:1269:1430) - (1109:1269:1430)) - (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_87/D1 (528:584:640) - (528:584:640)) - (INTERCONNECT ram2e_ufm\/SLICE_101/F1 ram2e_ufm\/SLICE_101/D0 (525:584:643) - (525:584:643)) - (INTERCONNECT ram2e_ufm\/SLICE_41/F0 ram2e_ufm\/SLICE_41/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_41/Q0 ram2e_ufm\/SLICE_147/A1 (730:848:967) - (730:848:967)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO0 ram2e_ufm\/SLICE_42/C0 - (1531:1730:1930)(1531:1730:1930)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO0 ram2e_ufm\/SLICE_43/C0 - (1895:2126:2357)(1895:2126:2357)) - (INTERCONNECT ram2e_ufm\/SLICE_42/F0 ram2e_ufm\/SLICE_42/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F1 ram2e_ufm\/SLICE_42/CE (539:596:653) - (539:596:653)) - (INTERCONNECT ram2e_ufm\/SLICE_42/Q0 ram2e_ufm\/SLICE_137/D0 (969:1067:1165) - (969:1067:1165)) - (INTERCONNECT ram2e_ufm\/SLICE_42/Q0 ram2e_ufm\/SLICE_147/C1 (1344:1528:1713) - (1344:1528:1713)) - (INTERCONNECT ram2e_ufm\/SLICE_42/F1 ram2e_ufm\/SLICE_84/C1 (547:660:773) - (547:660:773)) - (INTERCONNECT ram2e_ufm\/SLICE_42/F1 ram2e_ufm\/SLICE_87/C1 (874:1022:1170) - (874:1022:1170)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO1 ram2e_ufm\/SLICE_43/D1 - (1495:1644:1793)(1495:1644:1793)) - (INTERCONNECT ram2e_ufm\/SLICE_43/F1 ram2e_ufm\/SLICE_43/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_43/F0 ram2e_ufm\/SLICE_43/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_43/CE (1157:1283:1410) - (1157:1283:1410)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_43/CE (1157:1283:1410) - (1157:1283:1410)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_44/CE (1510:1666:1822) - (1510:1666:1822)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_44/CE (1510:1666:1822) - (1510:1666:1822)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_45/CE (1510:1666:1822) - (1510:1666:1822)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_45/CE (1510:1666:1822) - (1510:1666:1822)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_46/CE (1157:1283:1410) - (1157:1283:1410)) - (INTERCONNECT ram2e_ufm\/SLICE_85/F0 ram2e_ufm\/SLICE_46/CE (1157:1283:1410) - (1157:1283:1410)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO3 ram2e_ufm\/SLICE_44/D1 - (1596:1735:1874)(1596:1735:1874)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO2 ram2e_ufm\/SLICE_44/C0 - (1607:1801:1995)(1607:1801:1995)) - (INTERCONNECT ram2e_ufm\/SLICE_44/F1 ram2e_ufm\/SLICE_44/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_44/F0 ram2e_ufm\/SLICE_44/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/ufmefb\/EFBInst_0/WBDATO5 ram2e_ufm\/SLICE_45/D1 - (1514:1658:1802)(1514:1658:1802)) - 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(INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_54/CE (2560:2785:3010) - (2560:2785:3010)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_54/CE (2560:2785:3010) - (2560:2785:3010)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_55/CE (2190:2383:2576) - (2190:2383:2576)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F0 ram2e_ufm\/SLICE_55/CE (2190:2383:2576) - (2190:2383:2576)) - (INTERCONNECT ram2e_ufm\/SLICE_47/Q0 ram2e_ufm\/SLICE_52/B0 (1364:1552:1740) - (1364:1552:1740)) - (INTERCONNECT ram2e_ufm\/SLICE_47/Q0 - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI0in - (1967:2161:2355)(1967:2161:2355)) - (INTERCONNECT ram2e_ufm\/SLICE_47/Q1 ram2e_ufm\/SLICE_97/D0 (1225:1346:1468) - (1225:1346:1468)) - (INTERCONNECT ram2e_ufm\/SLICE_47/Q1 - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBADRI1in - (1669:1836:2004)(1669:1836:2004)) - (INTERCONNECT ram2e_ufm\/SLICE_48/F1 ram2e_ufm\/SLICE_48/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_48/F0 ram2e_ufm\/SLICE_48/DI0 (0:0:0)(0:0:0)) - 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(906:1001:1097)(906:1001:1097)) - (INTERCONNECT ram2e_ufm\/SLICE_70/F0 ram2e_ufm\/SLICE_55/D1 (530:587:645) - (530:587:645)) - (INTERCONNECT ram2e_ufm\/SLICE_98/F0 ram2e_ufm\/SLICE_55/C1 (531:639:747) - (531:639:747)) - (INTERCONNECT ram2e_ufm\/SLICE_131/F0 ram2e_ufm\/SLICE_55/B1 (1358:1545:1733) - (1358:1545:1733)) - (INTERCONNECT ram2e_ufm\/SLICE_88/F0 ram2e_ufm\/SLICE_55/A1 (733:848:964) - (733:848:964)) - (INTERCONNECT ram2e_ufm\/SLICE_90/F0 ram2e_ufm\/SLICE_55/D0 (520:573:626) - (520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_55/F1 ram2e_ufm\/SLICE_55/DI1 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_55/F0 ram2e_ufm\/SLICE_55/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_55/Q0 - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI6in - (1233:1363:1494)(1233:1363:1494)) - (INTERCONNECT ram2e_ufm\/SLICE_55/Q1 - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBDATI7in - (906:1001:1097)(906:1001:1097)) - (INTERCONNECT ram2e_ufm\/SLICE_56/F1 ram2e_ufm\/SLICE_56/C0 (531:639:747) - (531:639:747)) - (INTERCONNECT ram2e_ufm\/SLICE_56/F0 ram2e_ufm\/SLICE_56/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_56/Q0 ram2e_ufm\/SLICE_108/D0 (1116:1235:1355) - (1116:1235:1355)) - (INTERCONNECT ram2e_ufm\/SLICE_57/F0 ram2e_ufm\/SLICE_57/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_69/F0 ram2e_ufm\/SLICE_57/LSR (881:983:1086) - (881:983:1086)) - (INTERCONNECT ram2e_ufm\/SLICE_69/F0 ram2e_ufm\/SLICE_69/A1 (481:577:673) - (481:577:673)) - (INTERCONNECT ram2e_ufm\/SLICE_69/F0 ram2e_ufm\/SLICE_105/D0 (271:301:332) - (271:301:332)) - (INTERCONNECT ram2e_ufm\/SLICE_57/Q0 - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBRSTIin - (1938:2122:2306)(1938:2122:2306)) - (INTERCONNECT ram2e_ufm\/SLICE_109/F0 ram2e_ufm\/SLICE_58/D1 (266:290:315) - (266:290:315)) - (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_58/A1 (1074:1241:1408) - (1074:1241:1408)) - (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_58/A0 (483:582:681) - (483:582:681)) - (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_103/B0 (774:907:1040) - (774:907:1040)) - (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_109/B0 (769:899:1029) - (769:899:1029)) - (INTERCONNECT ram2e_ufm\/SLICE_109/F1 ram2e_ufm\/SLICE_114/C0 (809:963:1118) - (809:963:1118)) - (INTERCONNECT ram2e_ufm\/SLICE_126/F1 ram2e_ufm\/SLICE_58/C0 (534:639:744) - (534:639:744)) - (INTERCONNECT ram2e_ufm\/SLICE_58/F1 ram2e_ufm\/SLICE_58/B0 (508:600:693) - (508:600:693)) - (INTERCONNECT ram2e_ufm\/SLICE_58/F0 ram2e_ufm\/SLICE_58/DI0 (0:0:0)(0:0:0)) - (INTERCONNECT ram2e_ufm\/SLICE_130/F0 ram2e_ufm\/SLICE_58/CE (1240:1368:1496) - (1240:1368:1496)) - (INTERCONNECT ram2e_ufm\/SLICE_58/Q0 - ram2e_ufm\/ufmefb\/EFBInst_0/ram2e_ufm\/ufmefb\/EFBInst_0_EFB/INST20/WBWEIin - (1527:1661:1795)(1527:1661:1795)) - (INTERCONNECT ram2e_ufm\/SUM0_i_m3_0\/SLICE_59/OFX0 ram2e_ufm\/SLICE_133/C0 - (800:939:1079)(800:939:1079)) - (INTERCONNECT ram2e_ufm\/SLICE_94/F0 - ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/A1 (1067:1225:1383)(1067:1225:1383)) - (INTERCONNECT ram2e_ufm\/un1_CS_0_sqmuxa_0_0_0\/SLICE_60/OFX0 - ram2e_ufm\/SLICE_82/A0 (1067:1225:1383)(1067:1225:1383)) - (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/CKE_7\/SLICE_61/D1 (271:301:332) - (271:301:332)) - (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/SLICE_91/A1 (738:859:981) - (738:859:981)) - (INTERCONNECT ram2e_ufm\/SLICE_102/F1 ram2e_ufm\/SLICE_102/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_102/F0 ram2e_ufm\/CKE_7\/SLICE_61/M0 (485:526:568) - (485:526:568)) - (INTERCONNECT ram2e_ufm\/SLICE_62/F0 ram2e_ufm\/SLICE_84/D0 (1220:1340:1460) - (1220:1340:1460)) - (INTERCONNECT ram2e_ufm\/SLICE_65/F0 ram2e_ufm\/SLICE_63/C1 (534:639:744) - (534:639:744)) - (INTERCONNECT ram2e_ufm\/SLICE_133/F0 ram2e_ufm\/SLICE_63/A1 (730:848:967) - (730:848:967)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_63/D0 (546:610:675) - (546:610:675)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_66/B0 (770:894:1018) - (770:894:1018)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_79/C1 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_84/A0 (756:886:1016) - (756:886:1016)) - (INTERCONNECT ram2e_ufm\/SLICE_79/F0 ram2e_ufm\/SLICE_85/D0 (873:972:1072) - (873:972:1072)) - (INTERCONNECT ram2e_ufm\/SLICE_84/F0 ram2e_ufm\/SLICE_63/C0 (531:639:747) - (531:639:747)) - (INTERCONNECT ram2e_ufm\/SLICE_63/F1 ram2e_ufm\/SLICE_63/B0 (508:600:693) - (508:600:693)) - (INTERCONNECT ram2e_ufm\/SLICE_64/F1 ram2e_ufm\/SLICE_64/B0 (508:600:693) - (508:600:693)) - (INTERCONNECT ram2e_ufm\/SLICE_65/F1 ram2e_ufm\/SLICE_65/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_100/F0 ram2e_ufm\/SLICE_65/A0 (730:848:967) - (730:848:967)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_66/C1 (991:1149:1308) - (991:1149:1308)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_70/D1 (1350:1485:1621) - (1350:1485:1621)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_80/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_81/C1 (1736:1959:2182) - (1736:1959:2182)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_85/A1 (1554:1754:1955) - (1554:1754:1955)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_89/B1 (2331:2598:2866) - (2331:2598:2866)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_98/C1 (1736:1959:2182) - (1736:1959:2182)) - (INTERCONNECT ram2e_ufm\/SLICE_80/F1 ram2e_ufm\/SLICE_130/D0 (528:584:640) - (528:584:640)) - (INTERCONNECT ram2e_ufm\/SLICE_108/F0 ram2e_ufm\/SLICE_66/A1 (1067:1225:1383) - (1067:1225:1383)) - (INTERCONNECT ram2e_ufm\/SLICE_66/F1 ram2e_ufm\/SLICE_66/A0 (730:848:967) - (730:848:967)) - (INTERCONNECT ram2e_ufm\/SLICE_67/F1 ram2e_ufm\/SLICE_67/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_67/F0 ram2e_ufm\/SLICE_91/D0 (530:587:645) - (530:587:645)) - (INTERCONNECT ram2e_ufm\/SLICE_68/F0 ram2e_ufm\/SLICE_68/A1 (1430:1615:1801) - (1430:1615:1801)) - (INTERCONNECT ram2e_ufm\/SLICE_68/F1 ram2e_ufm\/SLICE_86/A0 (730:848:967) - (730:848:967)) - (INTERCONNECT ram2e_ufm\/SLICE_122/F0 ram2e_ufm\/SLICE_69/B1 (762:883:1004) - (762:883:1004)) - (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_70/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_79/A1 (745:874:1003) - (745:874:1003)) - (INTERCONNECT ram2e_ufm\/SLICE_70/F1 ram2e_ufm\/SLICE_111/A1 (738:859:981) - (738:859:981)) - (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_70/A0 (735:859:984) - (735:859:984)) - (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_75/B0 (513:611:710) - (513:611:710)) - (INTERCONNECT ram2e_ufm\/SLICE_75/F1 ram2e_ufm\/SLICE_88/D0 (528:584:640) - (528:584:640)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_71/C1 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_91/C0 (811:957:1103) - (811:957:1103)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_124/B1 (1744:1971:2199) - (1744:1971:2199)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_124/B0 (1744:1971:2199) - (1744:1971:2199)) - (INTERCONNECT ram2e_ufm\/SLICE_71/F0 ram2e_ufm\/SLICE_146/B1 (777:908:1040) - (777:908:1040)) - (INTERCONNECT ram2e_ufm\/SLICE_72/F0 ram2e_ufm\/SLICE_72/C1 (534:645:756) - (534:645:756)) - (INTERCONNECT ram2e_ufm\/SLICE_72/F0 ram2e_ufm\/SLICE_129/C1 (537:645:753) - (537:645:753)) - (INTERCONNECT ram2e_ufm\/SLICE_72/F1 BA\[0\]_MGIOL/OPOS (1337:1468:1599) - (1337:1468:1599)) - (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_73/D1 (808:897:986) - (808:897:986)) - (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_97/C0 (819:963:1107) - (819:963:1107)) - (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_98/B0 (511:606:702) - (511:606:702)) - (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_99/C0 (819:963:1107) - (819:963:1107)) - (INTERCONNECT ram2e_ufm\/SLICE_98/F1 ram2e_ufm\/SLICE_126/D0 (1172:1292:1413) - (1172:1292:1413)) - (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_73/C1 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_97/C1 (536:650:764) - (536:650:764)) - (INTERCONNECT ram2e_ufm\/SLICE_73/F0 ram2e_ufm\/SLICE_145/D1 (528:584:640) - (528:584:640)) - (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_73/B1 (770:894:1018) - (770:894:1018)) - (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_103/C0 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_103/F1 ram2e_ufm\/SLICE_109/C0 (546:664:783) - (546:664:783)) - (INTERCONNECT ram2e_ufm\/SLICE_135/F0 ram2e_ufm\/SLICE_74/A1 (740:863:986) - (740:863:986)) - (INTERCONNECT ram2e_ufm\/SLICE_75/F0 ram2e_ufm\/SLICE_79/B1 (772:897:1023) - (772:897:1023)) - (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_76/C0 (284:372:461) - (284:372:461)) - (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_81/A0 (737:864:992) - (737:864:992)) - (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_111/A0 (483:582:681) - (483:582:681)) - (INTERCONNECT ram2e_ufm\/SLICE_76/F1 ram2e_ufm\/SLICE_131/B0 (1038:1199:1361) - (1038:1199:1361)) - (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_76/B0 (1116:1279:1442) - (1116:1279:1442)) - (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_88/B0 (1116:1279:1442) - (1116:1279:1442)) - (INTERCONNECT ram2e_ufm\/SLICE_145/F0 ram2e_ufm\/SLICE_90/C1 (874:1022:1170) - (874:1022:1170)) - (INTERCONNECT ram2e_ufm\/SLICE_76/F0 ram2e_ufm\/SLICE_98/C0 (1164:1335:1506) - (1164:1335:1506)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_77/C1 (282:367:453) - (282:367:453)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_80/A0 (1179:1347:1515) - (1179:1347:1515)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_82/B0 (772:902:1032) - (772:902:1032)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_130/A1 (1012:1174:1337) - (1012:1174:1337)) - (INTERCONNECT ram2e_ufm\/SLICE_77/F0 ram2e_ufm\/SLICE_130/A0 (1012:1174:1337) - (1012:1174:1337)) - (INTERCONNECT ram2e_ufm\/SLICE_133/F1 ram2e_ufm\/SLICE_82/B1 (1206:1370:1535) - (1206:1370:1535)) - (INTERCONNECT ram2e_ufm\/SLICE_101/F0 ram2e_ufm\/SLICE_82/A1 (740:863:986) - (740:863:986)) - (INTERCONNECT ram2e_ufm\/SLICE_83/F0 ram2e_ufm\/SLICE_82/D0 (266:290:315) - (266:290:315)) - (INTERCONNECT ram2e_ufm\/SLICE_82/F1 ram2e_ufm\/SLICE_82/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_83/F1 ram2e_ufm\/SLICE_83/D0 (520:573:626) - (520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_87/F0 ram2e_ufm\/SLICE_83/A0 (733:848:964) - (733:848:964)) - (INTERCONNECT ram2e_ufm\/SLICE_110/F0 ram2e_ufm\/SLICE_85/B0 (765:883:1001) - (765:883:1001)) - (INTERCONNECT ram2e_ufm\/SLICE_86/F1 ram2e_ufm\/SLICE_86/D0 (531:586:641) - (531:586:641)) - (INTERCONNECT ram2e_ufm\/SLICE_86/F1 ram2e_ufm\/SLICE_109/A0 (741:861:982) - (741:861:982)) - (INTERCONNECT ram2e_ufm\/SLICE_126/F0 ram2e_ufm\/SLICE_86/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_99/F0 ram2e_ufm\/SLICE_86/B0 (508:600:693) - (508:600:693)) - (INTERCONNECT ram2e_ufm\/SLICE_88/F1 ram2e_ufm\/SLICE_88/C0 (280:362:445) - (280:362:445)) - (INTERCONNECT ram2e_ufm\/SLICE_88/F1 ram2e_ufm\/SLICE_111/D0 (269:296:324) - (269:296:324)) - (INTERCONNECT ram2e_ufm\/SLICE_104/F0 ram2e_ufm\/SLICE_89/D0 (266:290:315) - (266:290:315)) - (INTERCONNECT ram2e_ufm\/SLICE_90/F1 ram2e_ufm\/SLICE_90/B0 (762:883:1004) - (762:883:1004)) - (INTERCONNECT ram2e_ufm\/SLICE_91/F1 ram2e_ufm\/SLICE_91/B0 (511:606:702) - (511:606:702)) - (INTERCONNECT ram2e_ufm\/SLICE_91/F1 ram2e_ufm\/SLICE_92/D0 (860:955:1051) - (860:955:1051)) - (INTERCONNECT ram2e_ufm\/SLICE_92/F1 ram2e_ufm\/SLICE_92/B0 (511:606:702) - (511:606:702)) - (INTERCONNECT ram2e_ufm\/SLICE_92/F1 ram2e_ufm\/SLICE_102/B0 (511:606:702) - (511:606:702)) - (INTERCONNECT ram2e_ufm\/SLICE_93/F1 ram2e_ufm\/SLICE_93/A0 (730:848:967) - (730:848:967)) - (INTERCONNECT ram2e_ufm\/SLICE_100/F1 ram2e_ufm\/SLICE_94/A0 (743:869:995) - (743:869:995)) - (INTERCONNECT ram2e_ufm\/SLICE_100/F1 ram2e_ufm\/SLICE_100/D0 (523:579:635) - (523:579:635)) - (INTERCONNECT Ain\[4\]_I/PADDI ram2e_ufm\/SLICE_95/D0 (1587:1706:1825) - (1587:1706:1825)) - (INTERCONNECT Ain\[6\]_I/PADDI ram2e_ufm\/SLICE_96/A0 (1729:1905:2082) - (1729:1905:2082)) - (INTERCONNECT ram2e_ufm\/SLICE_97/F1 ram2e_ufm\/SLICE_97/B0 (762:883:1004) - (762:883:1004)) - (INTERCONNECT ram2e_ufm\/SLICE_99/F1 ram2e_ufm\/SLICE_99/D0 (520:573:626) - (520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_125/F1 ram2e_ufm\/SLICE_99/B0 (762:883:1004) - (762:883:1004)) - (INTERCONNECT ram2e_ufm\/SLICE_115/F0 ram2e_ufm\/SLICE_102/A0 (740:863:986) - (740:863:986)) - (INTERCONNECT ram2e_ufm\/SLICE_123/F1 ram2e_ufm\/SLICE_103/D0 (520:573:626) - (520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_128/F0 ram2e_ufm\/SLICE_103/A0 (733:848:964) - (733:848:964)) - (INTERCONNECT ram2e_ufm\/SLICE_104/F1 ram2e_ufm\/SLICE_104/C0 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_122/F1 ram2e_ufm\/SLICE_105/D1 (266:290:315) - (266:290:315)) - (INTERCONNECT ram2e_ufm\/SLICE_107/F1 ram2e_ufm\/SLICE_107/C0 (542:652:762) - (542:652:762)) - (INTERCONNECT ram2e_ufm\/SLICE_107/F1 ram2e_ufm\/SLICE_134/A0 (741:861:982) - (741:861:982)) - (INTERCONNECT ram2e_ufm\/SLICE_134/F1 ram2e_ufm\/SLICE_108/D1 (266:290:315) - (266:290:315)) - (INTERCONNECT ram2e_ufm\/SLICE_111/F0 ram2e_ufm\/SLICE_111/C1 (277:356:436) - (277:356:436)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_112/A0 (2246:2473:2700) - (2246:2473:2700)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_113/B1 (2321:2547:2774) - (2321:2547:2774)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_115/B0 (2648:2909:3171) - (2648:2909:3171)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_135/B0 (1951:2145:2340) - (1951:2145:2340)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_136/D1 (2036:2197:2359) - (2036:2197:2359)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_136/C0 (1720:1901:2083) - (1720:1901:2083)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_137/C1 (2090:2303:2517) - (2090:2303:2517)) - (INTERCONNECT nEN80_I/PADDI ram2e_ufm\/SLICE_137/C0 (2090:2303:2517) - (2090:2303:2517)) - (INTERCONNECT ram2e_ufm\/SLICE_114/F1 ram2e_ufm\/SLICE_114/D0 (520:573:626) - (520:573:626)) - (INTERCONNECT ram2e_ufm\/SLICE_116/F0 ram2e_ufm\/SLICE_116/C1 (277:356:436) - (277:356:436)) - (INTERCONNECT ram2e_ufm\/SLICE_117/F0 BA\[1\]_MGIOL/CE (1759:1942:2125) - (1759:1942:2125)) - (INTERCONNECT ram2e_ufm\/SLICE_117/F0 BA\[0\]_MGIOL/CE (1759:1942:2125) - (1759:1942:2125)) - (INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQMH_MGIOL/CE (1433:1585:1737) - (1433:1585:1737)) - (INTERCONNECT ram2e_ufm\/SLICE_118/F0 DQML_MGIOL/CE (1433:1585:1737) - (1433:1585:1737)) - (INTERCONNECT ram2e_ufm\/SLICE_120/F0 DQML_MGIOL/OPOS (1338:1473:1608) - (1338:1473:1608)) - (INTERCONNECT ram2e_ufm\/SLICE_120/F1 DQMH_MGIOL/OPOS (1338:1473:1608) - (1338:1473:1608)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[7\]_MGIOL/CE (1529:1693:1857) - (1529:1693:1857)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[6\]_MGIOL/CE (1529:1693:1857) - (1529:1693:1857)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[5\]_MGIOL/CE (1893:2088:2284) - (1893:2088:2284)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[4\]_MGIOL/CE (1893:2088:2284) - (1893:2088:2284)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[3\]_MGIOL/CE (1529:1693:1857) - (1529:1693:1857)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[2\]_MGIOL/CE (1893:2088:2284) - (1893:2088:2284)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[1\]_MGIOL/CE (1529:1693:1857) - (1529:1693:1857)) - (INTERCONNECT ram2e_ufm\/SLICE_121/F1 Vout\[0\]_MGIOL/CE (1893:2088:2284) - (1893:2088:2284)) - (INTERCONNECT ram2e_ufm\/SLICE_129/F1 BA\[1\]_MGIOL/OPOS (1445:1584:1723) - (1445:1584:1723)) - (INTERCONNECT Ain\[0\]_I/PADDI ram2e_ufm\/SLICE_132/C1 (2395:2638:2881) - (2395:2638:2881)) - (INTERCONNECT Ain\[7\]_I/PADDI ram2e_ufm\/SLICE_132/C0 (2031:2242:2454) - (2031:2242:2454)) - (INTERCONNECT ram2e_ufm\/SLICE_136/F0 nDOE_I/PADDO (1538:1682:1827) - (1538:1682:1827)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F0 LED_I/PADDO (1041:1147:1254)(1041:1147:1254)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[0\]_I/PADDT (1300:1443:1587) - (1300:1443:1587)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[7\]_I/PADDT (1664:1839:2014) - (1664:1839:2014)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[6\]_I/PADDT (1664:1839:2014) - (1664:1839:2014)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[5\]_I/PADDT (1664:1839:2014) - (1664:1839:2014)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[4\]_I/PADDT (1664:1839:2014) - (1664:1839:2014)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[3\]_I/PADDT (1300:1443:1587) - (1300:1443:1587)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[2\]_I/PADDT (1300:1443:1587) - (1300:1443:1587)) - (INTERCONNECT ram2e_ufm\/SLICE_137/F1 RD\[1\]_I/PADDT (1300:1443:1587) - (1300:1443:1587)) - (INTERCONNECT PHI1_I/PADDI SLICE_139/A1 (1840:2021:2203)(1840:2021:2203)) - (INTERCONNECT PHI1_I/PADDI SLICE_139/A0 (1840:2021:2203)(1840:2021:2203)) - (INTERCONNECT PHI1_I/PADDI PHI1_MGIOL/DI (544:554:565)(544:554:565)) - (INTERCONNECT PHI1_MGIOL/IN SLICE_139/B0 (1392:1572:1753)(1392:1572:1753)) - (INTERCONNECT SLICE_139/F1 nVOE_I/PADDO (1344:1530:1717)(1344:1530:1717)) - (INTERCONNECT ram2e_ufm\/SLICE_141/F0 RD\[3\]_I/PADDO (1263:1400:1537) - (1263:1400:1537)) - (INTERCONNECT ram2e_ufm\/SLICE_141/F1 RD\[0\]_I/PADDO (1300:1433:1567) - (1300:1433:1567)) - (INTERCONNECT ram2e_ufm\/SLICE_142/F0 RD\[4\]_I/PADDO (1367:1504:1642) - (1367:1504:1642)) - (INTERCONNECT ram2e_ufm\/SLICE_143/F0 RD\[7\]_I/PADDO (1367:1504:1642) - (1367:1504:1642)) - (INTERCONNECT ram2e_ufm\/SLICE_143/F1 RD\[1\]_I/PADDO (936:1038:1140) - (936:1038:1140)) - (INTERCONNECT ram2e_ufm\/SLICE_144/F0 RD\[6\]_I/PADDO (1111:1225:1339) - (1111:1225:1339)) - (INTERCONNECT ram2e_ufm\/SLICE_144/F1 RD\[2\]_I/PADDO (1041:1147:1254) - (1041:1147:1254)) - (INTERCONNECT ram2e_ufm\/SLICE_147/F0 RD\[5\]_I/PADDO (1769:1938:2108) - (1769:1938:2108)) - (INTERCONNECT RD\[0\]_I/PADDI Vout\[0\]_MGIOL/OPOS (2416:2609:2802) - (2416:2609:2802)) - (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_I/PADDO (2446:2645:2845)(2446:2645:2845)) - (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (2416:2609:2802) - (2416:2609:2802)) - (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_I/PADDO (2000:2173:2346)(2000:2173:2346)) - (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (2862:3081:3301) - (2862:3081:3301)) - (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_I/PADDO (2446:2645:2845)(2446:2645:2845)) - (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (2416:2609:2802) - (2416:2609:2802)) - (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_I/PADDO (2427:2630:2834)(2427:2630:2834)) - (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (2346:2526:2707) - (2346:2526:2707)) - (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_I/PADDO (3085:3339:3593)(3085:3339:3593)) - (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (2416:2609:2802) - (2416:2609:2802)) - (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_I/PADDO (2446:2645:2845)(2446:2645:2845)) - (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (2264:2449:2635) - (2264:2449:2635)) - (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_I/PADDO (3003:3262:3521)(3003:3262:3521)) - (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (2345:2526:2708) - (2345:2526:2708)) - (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_I/PADDO (1929:2090:2252)(1929:2090:2252)) - (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (30:36:43)(30:36:43)) - (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (30:36:43)(30:36:43)) - (INTERCONNECT RAout\[11\]_MGIOL/IOLDO RAout\[11\]_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT RAout\[10\]_MGIOL/IOLDO RAout\[10\]_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT RAout\[9\]_MGIOL/IOLDO RAout\[9\]_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT RAout\[8\]_MGIOL/IOLDO RAout\[8\]_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT RAout\[7\]_MGIOL/IOLDO RAout\[7\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[6\]_MGIOL/IOLDO RAout\[6\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[5\]_MGIOL/IOLDO RAout\[5\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[4\]_MGIOL/IOLDO RAout\[4\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[3\]_MGIOL/IOLDO RAout\[3\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[2\]_MGIOL/IOLDO RAout\[2\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[1\]_MGIOL/IOLDO RAout\[1\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT RAout\[0\]_MGIOL/IOLDO RAout\[0\]_I/IOLDO (25:77:129)(25:77:129)) - (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT nRWEout_MGIOL/IOLDO nRWEout_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT nCASout_MGIOL/IOLDO nCASout_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT nRASout_MGIOL/IOLDO nRASout_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT CKEout_MGIOL/IOLDO CKEout_I/IOLDO (9:36:63)(9:36:63)) - (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (11:21:32)(11:21:32)) - (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (11:21:32)(11:21:32)) - (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (11:21:32)(11:21:32)) - (INTERCONNECT Vout\[4\]_MGIOL/IOLDO Vout\[4\]_I/IOLDO (11:21:32)(11:21:32)) - (INTERCONNECT Vout\[3\]_MGIOL/IOLDO Vout\[3\]_I/IOLDO (11:21:32)(11:21:32)) - (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (11:21:32)(11:21:32)) - (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (11:21:32)(11:21:32)) - (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (11:21:32)(11:21:32)) - ) - ) - ) -) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo deleted file mode 100644 index 8976b2c..0000000 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo +++ /dev/null @@ -1,7686 +0,0 @@ - -// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 - -// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd -// Netlist created on Thu Dec 28 23:23:28 2023 -// Netlist written on Thu Dec 28 23:23:51 2023 -// Design is for device LCMXO2-640HC -// Design is for package TQFP100 -// Design is for performance grade 4 - -`timescale 1 ns / 1 ps - -module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, - Vout, nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout, BA, - RAout, DQML, DQMH, RD ); - input C14M, PHI1, nWE, nWE80, nEN80, nC07X; - input [7:0] Ain; - input [7:0] Din; - output LED; - output [7:0] Dout; - output nDOE; - output [7:0] Vout; - output nVOE, CKEout, nCSout, nRASout, nCASout, nRWEout; - output [1:0] BA; - output [11:0] RAout; - output DQML, DQMH; - inout [7:0] RD; - wire \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , - \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , - \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , - \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , - \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , - \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , - \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , - \S[1] , N_551, \S[0] , \ram2e_ufm/CKE_7 , CKE_7_RNIS77M1, CKE, - \ram2e_ufm/wb_adr_0_sqmuxa_1_i , RWSel, CO0_0, \CmdTout_3[0] , - N_185_i, GND, CO0_1, \RC[2] , \RC[1] , N_360_i, RC12, - \ram2e_ufm/N_821 , \ram2e_ufm/SUM1_0_0 , \ram2e_ufm/SUM0_i_a3_4_0 , - \ram2e_ufm/N_886 , \ram2e_ufm/N_215 , \CS[1] , \ram2e_ufm/SUM0_i_4 , - \CS[2] , CmdExecMXO2_3_0_a3_0_RNI6S1P8, N_547_i, un1_CS_0_sqmuxa_i, - \CS[0] , \ram2e_ufm/N_234 , CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514, - \ram2e_ufm/N_800 , \Din_c[5] , \Din_c[3] , - \ram2e_ufm/CmdLEDGet_3_0_a3_1 , \ram2e_ufm/N_847 , \Din_c[1] , - \Din_c[2] , CmdLEDGet_3, N_187_i, CmdLEDGet, \Din_c[7] , - \ram2e_ufm/N_883 , \Din_c[4] , CmdLEDSet_3, CmdLEDSet, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 , CmdRWMaskSet_3, CmdRWMaskSet, - \ram2e_ufm/N_850 , \Din_c[0] , CmdSetRWBankFFLED_4, CmdSetRWBankFFLED, - \CmdTout[1] , \CmdTout[2] , N_369_i, N_368_i, \ram2e_ufm/N_186 , - \RA[1] , \S[3] , N_1080_0, \ram2e_ufm/N_660 , DOEEN, - \ram2e_ufm/N_193 , \ram2e_ufm/N_182 , \Ain_c[1] , \ram2e_ufm/N_659 , - \ram2e_ufm/N_801 , \ram2e_ufm/N_684 , \ram2e_ufm/RA_35_0_0_1[0] , - N_223, \RA_35[0] , N_126, \RA[0] , \ram2e_ufm/RA_35_0_0_0[3] , - \ram2e_ufm/N_680 , \ram2e_ufm/N_679 , \Ain_c[2] , \RA_35[3] , - \RA_35[2] , \RA[2] , \RA[3] , \ram2e_ufm/N_621 , \Ain_c[5] , - \ram2e_ufm/RA_35_0_0_0[5] , \ram2e_ufm/RA_35_0_0_0[4] , \RA_35[5] , - \RA_35[4] , \RA[4] , \RA[5] , \ram2e_ufm/RA_35_0_0_0_0[7] , - \ram2e_ufm/RA_35_0_0_0_0[6] , \RA_35[7] , \RA_35[6] , \RA[6] , - \RA[7] , \ram2e_ufm/N_242 , \ram2e_ufm/RA_35_0_0_0[9] , \RA[9] , - \ram2e_ufm/N_699 , \RA[8] , \ram2e_ufm/N_698 , \ram2e_ufm/N_221 , - \RA_35[9] , un2_S_2_i_0_0_o3_RNIHFHN3, \RWBank[4] , \ram2e_ufm/N_845 , - \RA[11] , \ram2e_ufm/N_628 , \ram2e_ufm/RA_35_2_0_0[10] , - \ram2e_ufm/N_624 , \ram2e_ufm/N_627 , \RA_35[11] , \RA_35[10] , - \RA[10] , \RC_3[2] , \RC_3[1] , \ram2e_ufm/RWMask[1] , - \ram2e_ufm/N_188 , \ram2e_ufm/RWMask[0] , \RWBank_3[1] , - \RWBank_3[0] , \RWBank[0] , \RWBank[1] , \ram2e_ufm/RWMask[3] , - \ram2e_ufm/RWMask[2] , \RWBank_3[3] , \RWBank_3[2] , \RWBank[2] , - \RWBank[3] , \ram2e_ufm/RWMask[5] , \ram2e_ufm/RWMask[4] , - \RWBank_3[5] , \RWBank_3[4] , \RWBank[5] , \ram2e_ufm/RWMask[7] , - \Din_c[6] , \ram2e_ufm/RWMask[6] , \RWBank_3[7] , \RWBank_3[6] , - \RWBank[6] , \RWBank[7] , \Ain_c[3] , nC07X_c, nWE_c, RWSel_2, - un9_VOEEN_0_a2_0_a3_0_a3, \ram2e_ufm/N_885 , - \ram2e_ufm/Ready3_0_a3_4 , \ram2e_ufm/Ready3_0_a3_5 , - \ram2e_ufm/Ready3_0_a3_3 , Ready3, Ready, N_1026_0, - \ram2e_ufm/S_r_i_0_o2[1] , \ram2e_ufm/N_194 , \ram2e_ufm/N_271 , S_1, - \ram2e_ufm/N_643 , N_362_i, \S_s_0_0[0] , \S[2] , N_372_i, N_361_i, - N_1078_0, VOEEN, BA_0_sqmuxa, \ram2e_ufm/N_285_i , \ram2e_ufm/N_804 , - \ram2e_ufm/N_641 , \ram2e_ufm/N_640 , \ram2e_ufm/N_872 , N_370_i, - nCAS, \ram2e_ufm/N_616 , \ram2e_ufm/N_615 , \ram2e_ufm/N_617 , - \ram2e_ufm/nRAS_s_i_0_0 , N_358_i, nRAS, \ram2e_ufm/N_226 , - \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] , \ram2e_ufm/N_866 , N_359_i, nRWE, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 , - \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 , \ram2e_ufm/CmdBitbangMXO2_3 , - \ram2e_ufm/CmdBitbangMXO2 , \ram2e_ufm/N_851 , - \ram2e_ufm/CmdExecMXO2_3 , \ram2e_ufm/CmdExecMXO2 , - \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 , \ram2e_ufm/N_190 , - \ram2e_ufm/CmdSetRWBankFFChip_3 , \ram2e_ufm/CmdSetRWBankFFChip , - \ram2e_ufm/wb_dato[0] , \ram2e_ufm/N_295 , - \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] , \ram2e_ufm/LEDEN , - \ram2e_ufm/N_212 , \ram2e_ufm/wb_dato[1] , \ram2e_ufm/N_307_i , - \ram2e_ufm/N_309_i , \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] , - \ram2e_ufm/wb_dato[3] , \ram2e_ufm/wb_dato[2] , \ram2e_ufm/N_302_i , - \ram2e_ufm/N_304_i , \ram2e_ufm/wb_dato[5] , \ram2e_ufm/wb_dato[4] , - \ram2e_ufm/N_301_i , \ram2e_ufm/N_310_i , \ram2e_ufm/wb_dato[7] , - \ram2e_ufm/wb_dato[6] , \ram2e_ufm/N_296 , \ram2e_ufm/N_300_i , - \ram2e_ufm/wb_adr_7_5_41_0_1 , \ram2e_ufm/N_768 , \ram2e_ufm/N_793 , - \ram2e_ufm/wb_adr_7_i_i_4[0] , \ram2e_ufm/wb_adr_7_i_i_5[0] , - \ram2e_ufm/wb_adr_RNO[1] , \ram2e_ufm/wb_adr_7_i_i[0] , - \ram2e_ufm/CmdBitbangMXO2_RNINSM62 , \ram2e_ufm/wb_adr[0] , - \ram2e_ufm/wb_adr[1] , \ram2e_ufm/N_268_i , \ram2e_ufm/N_80_i , - \ram2e_ufm/wb_adr[2] , \ram2e_ufm/wb_adr[3] , \ram2e_ufm/N_290 , - \ram2e_ufm/N_294 , \ram2e_ufm/wb_adr[4] , \ram2e_ufm/wb_adr[5] , - \ram2e_ufm/N_267_i , \ram2e_ufm/N_284 , \ram2e_ufm/wb_adr[6] , - \ram2e_ufm/wb_adr[7] , \ram2e_ufm/wb_ack , \ram2e_ufm/N_336 , - \ram2e_ufm/N_687 , \ram2e_ufm/wb_cyc_stb_RNO , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] , - \ram2e_ufm/wb_cyc_stb , \ram2e_ufm/N_849 , - \ram2e_ufm/wb_dati_7_0_0_0[1] , \ram2e_ufm/N_611 , - \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] , \ram2e_ufm/N_856 , - \ram2e_ufm/wb_dati_7[1] , \ram2e_ufm/wb_dati_7[0] , - \ram2e_ufm/wb_dati[0] , \ram2e_ufm/wb_dati[1] , - \ram2e_ufm/wb_dati_7_0_0_0_0[3] , \ram2e_ufm/N_783 , - \ram2e_ufm/N_760 , \ram2e_ufm/wb_dati_7_0_0_o3_0[2] , - \ram2e_ufm/wb_dati_7[3] , \ram2e_ufm/wb_dati_7[2] , - \ram2e_ufm/wb_dati[2] , \ram2e_ufm/wb_dati[3] , \ram2e_ufm/N_757 , - \ram2e_ufm/N_763 , \ram2e_ufm/wb_dati_7_0_0_0[4] , - \ram2e_ufm/wb_dati_7[5] , \ram2e_ufm/wb_dati_7[4] , - \ram2e_ufm/wb_dati[4] , \ram2e_ufm/wb_dati[5] , \ram2e_ufm/N_604 , - \ram2e_ufm/wb_dati_7_0_0_0_0[7] , \ram2e_ufm/N_602 , - \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] , \ram2e_ufm/wb_dati_7_0_0_0[6] , - \ram2e_ufm/wb_dati_7[7] , \ram2e_ufm/wb_dati_7[6] , - \ram2e_ufm/wb_dati[6] , \ram2e_ufm/wb_dati[7] , \ram2e_ufm/wb_reqc_1 , - \ram2e_ufm/wb_reqc_i , \ram2e_ufm/wb_req , \ram2e_ufm/wb_rst8 , - \ram2e_ufm/wb_rst16_i , \ram2e_ufm/wb_rst , - \ram2e_ufm/wb_we_7_iv_0_0_3_0_0 , \ram2e_ufm/N_799 , - \ram2e_ufm/N_208 , \ram2e_ufm/wb_we_7_iv_0_0_3_0_1 , - \ram2e_ufm/wb_we_RNO , \ram2e_ufm/wb_we_RNO_0 , \ram2e_ufm/wb_we , - \ram2e_ufm/N_338 , \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 , \ram2e_ufm/N_817 , - \ram2e_ufm/CKE_7_sm0 , \ram2e_ufm/N_720_tz , \ram2e_ufm/SUM0_i_0 , - \ram2e_ufm/N_350 , \ram2e_ufm/N_187 , \ram2e_ufm/SUM0_i_3 , - \ram2e_ufm/SUM0_i_1 , \ram2e_ufm/N_755 , \ram2e_ufm/N_735 , - \ram2e_ufm/N_345 , \ram2e_ufm/N_777 , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] , \ram2e_ufm/N_250 , - \ram2e_ufm/N_256 , \ram2e_ufm/wb_adr_7_i_i_3_1[0] , - \ram2e_ufm/wb_adr_7_i_i_3[0] , \ram2e_ufm/N_254 , \ram2e_ufm/N_807 , - \ram2e_ufm/N_876 , \ram2e_ufm/N_784 , \ram2e_ufm/N_560 , \BA_4[0] , - \ram2e_ufm/N_781 , \ram2e_ufm/N_873 , \ram2e_ufm/N_184 , - \ram2e_ufm/N_625 , \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] , - \ram2e_ufm/N_811 , \ram2e_ufm/N_206 , - \ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] , \ram2e_ufm/N_185 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S , \ram2e_ufm/N_637 , - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 , \ram2e_ufm/N_592 , - \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] , \ram2e_ufm/N_634 , - \ram2e_ufm/N_753 , \ram2e_ufm/wb_adr_7_i_i_1[0] , - \ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] , - \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] , - \ram2e_ufm/wb_dati_7_0_0_a3_1[6] , \ram2e_ufm/N_890 , - \ram2e_ufm/N_220 , \ram2e_ufm/N_196 , \ram2e_ufm/N_243 , \Ain_c[4] , - \Ain_c[6] , \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] , - \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] , \ram2e_ufm/N_565 , - \ram2e_ufm/CKE_7s2_0_0_0 , \ram2e_ufm/N_204 , - \ram2e_ufm/wb_adr_7_5_41_a3_3_0 , \ram2e_ufm/N_595 , - \ram2e_ufm/nRWE_s_i_0_63_1 , \ram2e_ufm/N_792 , - \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] , - \ram2e_ufm/N_553 , nEN80_c, \ram2e_ufm/N_241_i , \ram2e_ufm/N_814 , - N_225_i, N_201_i, N_507_i, N_508, Vout3, \BA_4[1] , \Ain_c[0] , - \Ain_c[7] , nDOE_c, LED_c, RDOE_i, PHI1_c, PHI1r, nVOE_c, N_263_i, - N_667, N_648, N_662, N_666, N_663, N_665, N_664, \RD_in[0] , - \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , \RD_in[3] , - \RD_in[2] , \RD_in[1] , DQMH_c, DQML_c, \RAout_c[11] , \RAout_c[10] , - \RAout_c[9] , \RAout_c[8] , \RAout_c[7] , \RAout_c[6] , \RAout_c[5] , - \RAout_c[4] , \RAout_c[3] , \RAout_c[2] , \RAout_c[1] , \RAout_c[0] , - \BA_c[1] , \BA_c[0] , nRWEout_c, nCASout_c, nRASout_c, CKEout_c, - \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] , - \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , VCCI; - - SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), - .Q1(\FS[0] ), .FCO(\FS_cry[0] )); - SLICE_1 SLICE_1( .A0(\FS[15] ), .DI0(\FS_s[15] ), .CLK(C14M_c), - .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), .Q0(\FS[15] )); - SLICE_2 SLICE_2( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), - .DI0(\FS_s[13] ), .CLK(C14M_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), - .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] )); - SLICE_3 SLICE_3( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), - .DI0(\FS_s[11] ), .CLK(C14M_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), - .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] )); - SLICE_4 SLICE_4( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), - .DI0(\FS_s[9] ), .CLK(C14M_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), - .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] )); - SLICE_5 SLICE_5( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), - .DI0(\FS_s[7] ), .CLK(C14M_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), - .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] )); - SLICE_6 SLICE_6( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), - .DI0(\FS_s[5] ), .CLK(C14M_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), - .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] )); - SLICE_7 SLICE_7( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), - .DI0(\FS_s[3] ), .CLK(C14M_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), - .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] )); - SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), - .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), - .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); - SLICE_9 SLICE_9( .D1(\S[1] ), .C1(N_551), .B1(\FS[15] ), .A1(\S[0] ), - .D0(\ram2e_ufm/CKE_7 ), .C0(N_551), .B0(\S[1] ), .A0(\S[0] ), - .DI0(CKE_7_RNIS77M1), .CLK(C14M_c), .F0(CKE_7_RNIS77M1), .Q0(CKE), - .F1(\ram2e_ufm/wb_adr_0_sqmuxa_1_i )); - SLICE_10 SLICE_10( .D0(RWSel), .A0(CO0_0), .DI0(\CmdTout_3[0] ), - .CE(N_185_i), .CLK(C14M_c), .F0(\CmdTout_3[0] ), .Q0(CO0_0), .F1(GND)); - SLICE_11 SLICE_11( .B1(CO0_1), .A1(\RC[2] ), .D0(\RC[1] ), .B0(CO0_1), - .A0(\RC[2] ), .DI0(N_360_i), .CE(RC12), .CLK(C14M_c), .F0(N_360_i), - .Q0(CO0_1), .F1(\ram2e_ufm/N_821 )); - SLICE_12 SLICE_12( .D1(\ram2e_ufm/SUM1_0_0 ), .C1(\ram2e_ufm/SUM0_i_a3_4_0 ), - .B1(\ram2e_ufm/N_886 ), .A1(\ram2e_ufm/N_215 ), .D0(\CS[1] ), - .C0(\ram2e_ufm/SUM0_i_4 ), .B0(\ram2e_ufm/N_215 ), .A0(\CS[2] ), - .DI1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .DI0(N_547_i), - .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_547_i), .Q0(\CS[0] ), - .F1(CmdExecMXO2_3_0_a3_0_RNI6S1P8), .Q1(\CS[1] )); - SLICE_13 SLICE_13( .D1(\ram2e_ufm/N_234 ), .C1(\ram2e_ufm/N_215 ), - .B1(\CS[1] ), .A1(\CS[2] ), .D0(\ram2e_ufm/N_234 ), .C0(\ram2e_ufm/N_215 ), - .B0(\CS[1] ), .A0(\CS[2] ), .DI0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), - .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), - .F0(CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514), .Q0(\CS[2] ), - .F1(\ram2e_ufm/SUM1_0_0 )); - SLICE_14 SLICE_14( .C1(\ram2e_ufm/N_800 ), .B1(\Din_c[5] ), .A1(\Din_c[3] ), - .D0(\ram2e_ufm/CmdLEDGet_3_0_a3_1 ), .C0(\ram2e_ufm/N_847 ), - .B0(\Din_c[1] ), .A0(\Din_c[2] ), .DI0(CmdLEDGet_3), .CE(N_187_i), - .CLK(C14M_c), .F0(CmdLEDGet_3), .Q0(CmdLEDGet), .F1(\ram2e_ufm/N_847 )); - SLICE_15 SLICE_15( .C1(\Din_c[7] ), .B1(\CS[2] ), .A1(\Din_c[1] ), - .D0(\ram2e_ufm/N_883 ), .C0(\Din_c[7] ), .B0(\Din_c[4] ), .A0(\Din_c[1] ), - .DI0(CmdLEDSet_3), .CE(N_187_i), .CLK(C14M_c), .F0(CmdLEDSet_3), - .Q0(CmdLEDSet), .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 )); - SLICE_16 SLICE_16( .D1(\Din_c[1] ), .C1(\Din_c[7] ), .B1(\Din_c[3] ), - .A1(\Din_c[5] ), .D0(\Din_c[1] ), .C0(\ram2e_ufm/N_883 ), .B0(\Din_c[7] ), - .A0(\Din_c[4] ), .DI0(CmdRWMaskSet_3), .CE(N_187_i), .CLK(C14M_c), - .F0(CmdRWMaskSet_3), .Q0(CmdRWMaskSet), .F1(\ram2e_ufm/N_850 )); - SLICE_17 SLICE_17( .C1(\ram2e_ufm/N_847 ), .B1(\Din_c[0] ), .A1(\Din_c[2] ), - .D0(\Din_c[1] ), .C0(\ram2e_ufm/N_883 ), .B0(\Din_c[7] ), .A0(\Din_c[4] ), - .DI0(CmdSetRWBankFFLED_4), .CE(N_187_i), .CLK(C14M_c), - .F0(CmdSetRWBankFFLED_4), .Q0(CmdSetRWBankFFLED), .F1(\ram2e_ufm/N_883 )); - SLICE_18 SLICE_18( .D1(\CmdTout[1] ), .C1(CO0_0), .B1(RWSel), - .A1(\CmdTout[2] ), .D0(CO0_0), .B0(RWSel), .A0(\CmdTout[1] ), - .DI1(N_369_i), .DI0(N_368_i), .CE(N_185_i), .CLK(C14M_c), .F0(N_368_i), - .Q0(\CmdTout[1] ), .F1(N_369_i), .Q1(\CmdTout[2] )); - SLICE_19 SLICE_19( .C1(\CS[1] ), .A1(\CS[2] ), .C0(\ram2e_ufm/N_186 ), - .A0(\RA[1] ), .M0(\S[3] ), .LSR(N_1080_0), .CLK(C14M_c), - .F0(\ram2e_ufm/N_660 ), .Q0(DOEEN), .F1(\ram2e_ufm/N_193 )); - SLICE_20 SLICE_20( .D1(\ram2e_ufm/N_182 ), .C1(\ram2e_ufm/N_660 ), - .B1(\Ain_c[1] ), .A1(\ram2e_ufm/N_659 ), .D0(\ram2e_ufm/N_801 ), - .C0(\ram2e_ufm/N_684 ), .B0(\FS[7] ), .A0(\ram2e_ufm/RA_35_0_0_1[0] ), - .DI1(N_223), .DI0(\RA_35[0] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[0] ), - .Q0(\RA[0] ), .F1(N_223), .Q1(\RA[1] )); - SLICE_21 SLICE_21( .C1(\ram2e_ufm/N_801 ), .B1(\ram2e_ufm/RA_35_0_0_0[3] ), - .A1(\FS[10] ), .D0(\ram2e_ufm/N_680 ), .C0(\ram2e_ufm/N_679 ), - .B0(\ram2e_ufm/N_182 ), .A0(\Ain_c[2] ), .DI1(\RA_35[3] ), - .DI0(\RA_35[2] ), .CE(N_126), .CLK(C14M_c), .F0(\RA_35[2] ), .Q0(\RA[2] ), - .F1(\RA_35[3] ), .Q1(\RA[3] )); - SLICE_22 SLICE_22( .D1(\ram2e_ufm/N_621 ), .C1(\Ain_c[5] ), - .B1(\ram2e_ufm/RA_35_0_0_0[5] ), .A1(\ram2e_ufm/N_182 ), - .C0(\ram2e_ufm/RA_35_0_0_0[4] ), .B0(\FS[11] ), .A0(\ram2e_ufm/N_801 ), - .DI1(\RA_35[5] ), .DI0(\RA_35[4] ), .CE(N_126), .CLK(C14M_c), - .F0(\RA_35[4] ), .Q0(\RA[4] ), .F1(\RA_35[5] ), .Q1(\RA[5] )); - SLICE_23 SLICE_23( .C1(\ram2e_ufm/RA_35_0_0_0_0[7] ), .B1(\FS[14] ), - .A1(\ram2e_ufm/N_801 ), .C0(\ram2e_ufm/RA_35_0_0_0_0[6] ), .B0(\FS[13] ), - .A0(\ram2e_ufm/N_801 ), .DI1(\RA_35[7] ), .DI0(\RA_35[6] ), .CE(N_126), - .CLK(C14M_c), .F0(\RA_35[6] ), .Q0(\RA[6] ), .F1(\RA_35[7] ), .Q1(\RA[7] )); - SLICE_24 SLICE_24( .D1(\ram2e_ufm/N_242 ), .B1(\ram2e_ufm/RA_35_0_0_0[9] ), - .A1(\RA[9] ), .D0(\ram2e_ufm/N_699 ), .C0(\RA[8] ), .B0(\ram2e_ufm/N_698 ), - .A0(\ram2e_ufm/N_221 ), .DI1(\RA_35[9] ), .DI0(un2_S_2_i_0_0_o3_RNIHFHN3), - .CE(N_126), .CLK(C14M_c), .F0(un2_S_2_i_0_0_o3_RNIHFHN3), .Q0(\RA[8] ), - .F1(\RA_35[9] ), .Q1(\RA[9] )); - SLICE_25 SLICE_25( .D1(\ram2e_ufm/N_242 ), .C1(\RWBank[4] ), - .B1(\ram2e_ufm/N_845 ), .A1(\RA[11] ), .D0(\ram2e_ufm/N_628 ), - .C0(\ram2e_ufm/RA_35_2_0_0[10] ), .B0(\ram2e_ufm/N_624 ), - .A0(\ram2e_ufm/N_627 ), .DI1(\RA_35[11] ), .DI0(\RA_35[10] ), .CE(N_126), - .CLK(C14M_c), .F0(\RA_35[10] ), .Q0(\RA[10] ), .F1(\RA_35[11] ), - .Q1(\RA[11] )); - SLICE_26 SLICE_26( .D1(CO0_1), .B1(\RC[1] ), .A1(\RC[2] ), .D0(CO0_1), - .B0(\RC[1] ), .A0(\RC[2] ), .DI1(\RC_3[2] ), .DI0(\RC_3[1] ), .CE(RC12), - .CLK(C14M_c), .F0(\RC_3[1] ), .Q0(\RC[1] ), .F1(\RC_3[2] ), .Q1(\RC[2] )); - SLICE_27 SLICE_27( .D1(\ram2e_ufm/RWMask[1] ), .B1(\ram2e_ufm/N_188 ), - .A1(\Din_c[1] ), .C0(\ram2e_ufm/RWMask[0] ), .B0(\ram2e_ufm/N_188 ), - .A0(\Din_c[0] ), .DI1(\RWBank_3[1] ), .DI0(\RWBank_3[0] ), .CE(N_187_i), - .CLK(C14M_c), .F0(\RWBank_3[0] ), .Q0(\RWBank[0] ), .F1(\RWBank_3[1] ), - .Q1(\RWBank[1] )); - SLICE_28 SLICE_28( .C1(\ram2e_ufm/RWMask[3] ), .B1(\Din_c[3] ), - .A1(\ram2e_ufm/N_188 ), .D0(\Din_c[2] ), .C0(\ram2e_ufm/RWMask[2] ), - .A0(\ram2e_ufm/N_188 ), .DI1(\RWBank_3[3] ), .DI0(\RWBank_3[2] ), - .CE(N_187_i), .CLK(C14M_c), .F0(\RWBank_3[2] ), .Q0(\RWBank[2] ), - .F1(\RWBank_3[3] ), .Q1(\RWBank[3] )); - SLICE_29 SLICE_29( .C1(\ram2e_ufm/RWMask[5] ), .B1(\ram2e_ufm/N_188 ), - .A1(\Din_c[5] ), .C0(\ram2e_ufm/RWMask[4] ), .B0(\ram2e_ufm/N_188 ), - .A0(\Din_c[4] ), .DI1(\RWBank_3[5] ), .DI0(\RWBank_3[4] ), .CE(N_187_i), - .CLK(C14M_c), .F0(\RWBank_3[4] ), .Q0(\RWBank[4] ), .F1(\RWBank_3[5] ), - .Q1(\RWBank[5] )); - SLICE_30 SLICE_30( .D1(\ram2e_ufm/N_188 ), .B1(\Din_c[7] ), - .A1(\ram2e_ufm/RWMask[7] ), .D0(\ram2e_ufm/N_188 ), .B0(\Din_c[6] ), - .A0(\ram2e_ufm/RWMask[6] ), .DI1(\RWBank_3[7] ), .DI0(\RWBank_3[6] ), - .CE(N_187_i), .CLK(C14M_c), .F0(\RWBank_3[6] ), .Q0(\RWBank[6] ), - .F1(\RWBank_3[7] ), .Q1(\RWBank[7] )); - SLICE_31 SLICE_31( .D1(\RA[3] ), .C1(\ram2e_ufm/N_186 ), .B1(\Ain_c[3] ), - .A1(\ram2e_ufm/N_182 ), .D0(\RA[3] ), .C0(nC07X_c), .B0(\RA[0] ), - .A0(nWE_c), .DI0(RWSel_2), .CE(un9_VOEEN_0_a2_0_a3_0_a3), .CLK(C14M_c), - .F0(RWSel_2), .Q0(RWSel), .F1(\ram2e_ufm/RA_35_0_0_0[3] )); - SLICE_32 SLICE_32( .D1(\ram2e_ufm/N_885 ), .C1(\ram2e_ufm/Ready3_0_a3_4 ), - .B1(\ram2e_ufm/Ready3_0_a3_5 ), .A1(\ram2e_ufm/Ready3_0_a3_3 ), - .C0(Ready3), .A0(Ready), .DI0(N_1026_0), .CLK(C14M_c), .F0(N_1026_0), - .Q0(Ready), .F1(Ready3)); - SLICE_33 SLICE_33( .D1(\ram2e_ufm/S_r_i_0_o2[1] ), .C1(\ram2e_ufm/N_194 ), - .B1(\ram2e_ufm/N_271 ), .A1(S_1), .D0(\S[1] ), .C0(\ram2e_ufm/N_271 ), - .B0(\ram2e_ufm/N_643 ), .A0(S_1), .DI1(N_362_i), .DI0(\S_s_0_0[0] ), - .CLK(C14M_c), .F0(\S_s_0_0[0] ), .Q0(\S[0] ), .F1(N_362_i), .Q1(\S[1] )); - SLICE_34 SLICE_34( .D1(\S[2] ), .C1(\ram2e_ufm/N_194 ), .B1(S_1), - .A1(\S[3] ), .D0(\S[2] ), .C0(\ram2e_ufm/N_194 ), .B0(S_1), .A0(\S[3] ), - .DI1(N_372_i), .DI0(N_361_i), .CLK(C14M_c), .F0(N_361_i), .Q0(\S[2] ), - .F1(N_372_i), .Q1(\S[3] )); - SLICE_35 SLICE_35( .D1(\S[1] ), .C1(\S[0] ), .B1(\FS[4] ), .A1(N_551), - .D0(\S[2] ), .A0(\S[3] ), .DI0(N_551), .LSR(N_1078_0), .CLK(C14M_c), - .F0(N_551), .Q0(VOEEN), .F1(BA_0_sqmuxa)); - SLICE_36 SLICE_36( .D1(\S[1] ), .C1(\ram2e_ufm/N_285_i ), .B1(\S[0] ), - .A1(\ram2e_ufm/N_804 ), .D0(\ram2e_ufm/N_641 ), .C0(\ram2e_ufm/N_640 ), - .B0(\ram2e_ufm/N_872 ), .A0(nWE_c), .DI0(N_370_i), .CLK(C14M_c), - .F0(N_370_i), .Q0(nCAS), .F1(\ram2e_ufm/N_872 )); - SLICE_37 SLICE_37( .D1(\S[0] ), .C1(\ram2e_ufm/N_804 ), - .B1(\ram2e_ufm/N_285_i ), .A1(\S[1] ), .D0(\ram2e_ufm/N_616 ), - .C0(\ram2e_ufm/N_615 ), .B0(\ram2e_ufm/N_617 ), - .A0(\ram2e_ufm/nRAS_s_i_0_0 ), .DI0(N_358_i), .CLK(C14M_c), .F0(N_358_i), - .Q0(nRAS), .F1(\ram2e_ufm/N_617 )); - SLICE_38 SLICE_38( .D1(\ram2e_ufm/N_226 ), .C1(\S[2] ), - .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\ram2e_ufm/N_285_i ), - .D0(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ), .C0(\ram2e_ufm/N_866 ), - .B0(\ram2e_ufm/N_615 ), .A0(\ram2e_ufm/N_804 ), .DI0(N_359_i), - .CLK(C14M_c), .F0(N_359_i), .Q0(nRWE), .F1(\ram2e_ufm/N_615 )); - ram2e_ufm_SLICE_39 \ram2e_ufm/SLICE_39 ( .D1(\Din_c[3] ), .C1(\Din_c[0] ), - .B1(\Din_c[5] ), .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .D0(\Din_c[1] ), - .C0(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ), .B0(\ram2e_ufm/N_800 ), - .A0(\Din_c[2] ), .DI0(\ram2e_ufm/CmdBitbangMXO2_3 ), .CE(N_187_i), - .CLK(C14M_c), .F0(\ram2e_ufm/CmdBitbangMXO2_3 ), - .Q0(\ram2e_ufm/CmdBitbangMXO2 ), .F1(\ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 )); - ram2e_ufm_SLICE_40 \ram2e_ufm/SLICE_40 ( .D1(\CS[1] ), .C1(\CS[0] ), - .B1(\CS[2] ), .A1(\Din_c[6] ), .C0(\ram2e_ufm/N_800 ), - .B0(\ram2e_ufm/N_851 ), .DI0(\ram2e_ufm/CmdExecMXO2_3 ), .CE(N_187_i), - .CLK(C14M_c), .F0(\ram2e_ufm/CmdExecMXO2_3 ), .Q0(\ram2e_ufm/CmdExecMXO2 ), - .F1(\ram2e_ufm/N_800 )); - ram2e_ufm_SLICE_41 \ram2e_ufm/SLICE_41 ( .D1(\Din_c[4] ), .C1(\Din_c[0] ), - .B1(\Din_c[2] ), .A1(\Din_c[1] ), .D0(\ram2e_ufm/N_800 ), - .C0(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ), .B0(\Din_c[7] ), - .A0(\ram2e_ufm/N_190 ), .DI0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), - .CE(N_187_i), .CLK(C14M_c), .F0(\ram2e_ufm/CmdSetRWBankFFChip_3 ), - .Q0(\ram2e_ufm/CmdSetRWBankFFChip ), - .F1(\ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 )); - ram2e_ufm_SLICE_42 \ram2e_ufm/SLICE_42 ( .D1(\Din_c[2] ), .B1(\Din_c[6] ), - .A1(\Din_c[0] ), .D0(\Din_c[0] ), .C0(\ram2e_ufm/wb_dato[0] ), .A0(\S[3] ), - .DI0(\ram2e_ufm/N_295 ), .CE(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_295 ), .Q0(\ram2e_ufm/LEDEN ), - .F1(\ram2e_ufm/N_212 )); - ram2e_ufm_SLICE_43 \ram2e_ufm/SLICE_43 ( .D1(\ram2e_ufm/wb_dato[1] ), - .B1(\Din_c[1] ), .A1(\S[3] ), .D0(\Din_c[0] ), .C0(\ram2e_ufm/wb_dato[0] ), - .A0(\S[3] ), .DI1(\ram2e_ufm/N_307_i ), .DI0(\ram2e_ufm/N_309_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_309_i ), .Q0(\ram2e_ufm/RWMask[0] ), - .F1(\ram2e_ufm/N_307_i ), .Q1(\ram2e_ufm/RWMask[1] )); - ram2e_ufm_SLICE_44 \ram2e_ufm/SLICE_44 ( .D1(\ram2e_ufm/wb_dato[3] ), - .B1(\Din_c[3] ), .A1(\S[3] ), .D0(\S[3] ), .C0(\ram2e_ufm/wb_dato[2] ), - .B0(\Din_c[2] ), .DI1(\ram2e_ufm/N_302_i ), .DI0(\ram2e_ufm/N_304_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_304_i ), .Q0(\ram2e_ufm/RWMask[2] ), - .F1(\ram2e_ufm/N_302_i ), .Q1(\ram2e_ufm/RWMask[3] )); - ram2e_ufm_SLICE_45 \ram2e_ufm/SLICE_45 ( .D1(\ram2e_ufm/wb_dato[5] ), - .B1(\Din_c[5] ), .A1(\S[3] ), .D0(\ram2e_ufm/wb_dato[4] ), .C0(\Din_c[4] ), - .A0(\S[3] ), .DI1(\ram2e_ufm/N_301_i ), .DI0(\ram2e_ufm/N_310_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_310_i ), .Q0(\ram2e_ufm/RWMask[4] ), - .F1(\ram2e_ufm/N_301_i ), .Q1(\ram2e_ufm/RWMask[5] )); - ram2e_ufm_SLICE_46 \ram2e_ufm/SLICE_46 ( .D1(\ram2e_ufm/wb_dato[7] ), - .B1(\Din_c[7] ), .A1(\S[3] ), .D0(\ram2e_ufm/wb_dato[6] ), .B0(\Din_c[6] ), - .A0(\S[3] ), .DI1(\ram2e_ufm/N_296 ), .DI0(\ram2e_ufm/N_300_i ), - .CE(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_300_i ), .Q0(\ram2e_ufm/RWMask[6] ), - .F1(\ram2e_ufm/N_296 ), .Q1(\ram2e_ufm/RWMask[7] )); - ram2e_ufm_SLICE_47 \ram2e_ufm/SLICE_47 ( .D1(\ram2e_ufm/wb_adr_7_5_41_0_1 ), - .C1(\S[2] ), .B1(\ram2e_ufm/N_768 ), .A1(\Din_c[1] ), .D0(\FS[10] ), - .C0(\ram2e_ufm/N_793 ), .B0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), - .A0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), .DI1(\ram2e_ufm/wb_adr_RNO[1] ), - .DI0(\ram2e_ufm/wb_adr_7_i_i[0] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_adr_7_i_i[0] ), .Q0(\ram2e_ufm/wb_adr[0] ), - .F1(\ram2e_ufm/wb_adr_RNO[1] ), .Q1(\ram2e_ufm/wb_adr[1] )); - ram2e_ufm_SLICE_48 \ram2e_ufm/SLICE_48 ( .B1(\S[2] ), .A1(\Din_c[3] ), - .C0(\Din_c[2] ), .B0(\S[2] ), .DI1(\ram2e_ufm/N_268_i ), - .DI0(\ram2e_ufm/N_80_i ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_80_i ), .Q0(\ram2e_ufm/wb_adr[2] ), - .F1(\ram2e_ufm/N_268_i ), .Q1(\ram2e_ufm/wb_adr[3] )); - ram2e_ufm_SLICE_49 \ram2e_ufm/SLICE_49 ( .D1(\FS[14] ), .B1(\Din_c[5] ), - .A1(\S[2] ), .D0(\FS[14] ), .C0(\Din_c[4] ), .A0(\S[2] ), - .DI1(\ram2e_ufm/N_290 ), .DI0(\ram2e_ufm/N_294 ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/N_294 ), .Q0(\ram2e_ufm/wb_adr[4] ), .F1(\ram2e_ufm/N_290 ), - .Q1(\ram2e_ufm/wb_adr[5] )); - ram2e_ufm_SLICE_50 \ram2e_ufm/SLICE_50 ( .B1(\Din_c[7] ), .A1(\S[2] ), - .C0(\Din_c[6] ), .B0(\FS[14] ), .A0(\S[2] ), .DI1(\ram2e_ufm/N_267_i ), - .DI0(\ram2e_ufm/N_284 ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/N_284 ), .Q0(\ram2e_ufm/wb_adr[6] ), - .F1(\ram2e_ufm/N_267_i ), .Q1(\ram2e_ufm/wb_adr[7] )); - ram2e_ufm_SLICE_51 \ram2e_ufm/SLICE_51 ( .D1(\FS[14] ), - .C1(\ram2e_ufm/wb_ack ), .B1(\FS[0] ), .A1(\ram2e_ufm/N_336 ), .D0(\S[3] ), - .C0(\ram2e_ufm/N_687 ), .A0(\ram2e_ufm/CmdExecMXO2 ), - .DI0(\ram2e_ufm/wb_cyc_stb_RNO ), - .CE(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_cyc_stb_RNO ), .Q0(\ram2e_ufm/wb_cyc_stb ), - .F1(\ram2e_ufm/N_687 )); - ram2e_ufm_SLICE_52 \ram2e_ufm/SLICE_52 ( .D1(\ram2e_ufm/N_849 ), - .C1(\ram2e_ufm/wb_dati_7_0_0_0[1] ), .B1(\ram2e_ufm/N_611 ), - .A1(\ram2e_ufm/N_793 ), .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ), - .C0(\ram2e_ufm/N_856 ), .B0(\ram2e_ufm/wb_adr[0] ), .A0(\S[2] ), - .DI1(\ram2e_ufm/wb_dati_7[1] ), .DI0(\ram2e_ufm/wb_dati_7[0] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_dati_7[0] ), .Q0(\ram2e_ufm/wb_dati[0] ), - .F1(\ram2e_ufm/wb_dati_7[1] ), .Q1(\ram2e_ufm/wb_dati[1] )); - ram2e_ufm_SLICE_53 \ram2e_ufm/SLICE_53 ( .D1(\ram2e_ufm/N_611 ), - .C1(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .B1(\ram2e_ufm/N_783 ), - .A1(\ram2e_ufm/N_849 ), .D0(\ram2e_ufm/N_760 ), - .C0(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .B0(\ram2e_ufm/wb_adr[2] ), - .A0(\S[2] ), .DI1(\ram2e_ufm/wb_dati_7[3] ), - .DI0(\ram2e_ufm/wb_dati_7[2] ), .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), - .CLK(C14M_c), .F0(\ram2e_ufm/wb_dati_7[2] ), .Q0(\ram2e_ufm/wb_dati[2] ), - .F1(\ram2e_ufm/wb_dati_7[3] ), .Q1(\ram2e_ufm/wb_dati[3] )); - ram2e_ufm_SLICE_54 \ram2e_ufm/SLICE_54 ( .D1(\ram2e_ufm/N_760 ), - .C1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] ), .B1(\ram2e_ufm/wb_adr[5] ), - .A1(\S[2] ), .D0(\ram2e_ufm/N_760 ), .C0(\ram2e_ufm/N_757 ), - .B0(\ram2e_ufm/N_763 ), .A0(\ram2e_ufm/wb_dati_7_0_0_0[4] ), - .DI1(\ram2e_ufm/wb_dati_7[5] ), .DI0(\ram2e_ufm/wb_dati_7[4] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_dati_7[4] ), .Q0(\ram2e_ufm/wb_dati[4] ), - .F1(\ram2e_ufm/wb_dati_7[5] ), .Q1(\ram2e_ufm/wb_dati[5] )); - ram2e_ufm_SLICE_55 \ram2e_ufm/SLICE_55 ( .D1(\ram2e_ufm/N_604 ), - .C1(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), .B1(\ram2e_ufm/N_602 ), - .A1(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), - .D0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), .C0(\ram2e_ufm/N_757 ), - .B0(\ram2e_ufm/N_849 ), .A0(\ram2e_ufm/N_793 ), - .DI1(\ram2e_ufm/wb_dati_7[7] ), .DI0(\ram2e_ufm/wb_dati_7[6] ), - .CE(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_dati_7[6] ), .Q0(\ram2e_ufm/wb_dati[6] ), - .F1(\ram2e_ufm/wb_dati_7[7] ), .Q1(\ram2e_ufm/wb_dati[7] )); - ram2e_ufm_SLICE_56 \ram2e_ufm/SLICE_56 ( .D1(\S[0] ), .C1(\FS[14] ), - .B1(\S[1] ), .A1(\S[3] ), .D0(\FS[12] ), .C0(\ram2e_ufm/wb_reqc_1 ), - .B0(\FS[13] ), .A0(\FS[11] ), .DI0(\ram2e_ufm/wb_reqc_i ), - .CE(\ram2e_ufm/wb_adr_0_sqmuxa_1_i ), .LSR(\S[2] ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_reqc_i ), .Q0(\ram2e_ufm/wb_req ), - .F1(\ram2e_ufm/wb_reqc_1 )); - ram2e_ufm_SLICE_57 \ram2e_ufm/SLICE_57 ( .D1(\FS[14] ), .C1(\FS[2] ), - .B1(\FS[15] ), .A1(\FS[4] ), .D0(\FS[14] ), .B0(\FS[15] ), - .DI0(\ram2e_ufm/wb_rst8 ), .LSR(\ram2e_ufm/wb_rst16_i ), .CLK(C14M_c), - .F0(\ram2e_ufm/wb_rst8 ), .Q0(\ram2e_ufm/wb_rst ), - .F1(\ram2e_ufm/Ready3_0_a3_4 )); - ram2e_ufm_SLICE_58 \ram2e_ufm/SLICE_58 ( - .D1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), .C1(\FS[12] ), - .B1(\ram2e_ufm/N_885 ), .A1(\ram2e_ufm/N_799 ), .D0(\FS[13] ), - .C0(\ram2e_ufm/N_208 ), .B0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 ), - .A0(\ram2e_ufm/N_799 ), .DI0(\ram2e_ufm/wb_we_RNO ), - .CE(\ram2e_ufm/wb_we_RNO_0 ), .CLK(C14M_c), .F0(\ram2e_ufm/wb_we_RNO ), - .Q0(\ram2e_ufm/wb_we ), .F1(\ram2e_ufm/wb_we_7_iv_0_0_3_0_1 )); - ram2e_ufm_SUM0_i_m3_0_SLICE_59 \ram2e_ufm/SUM0_i_m3_0/SLICE_59 ( - .D1(\CS[1] ), .B1(\Din_c[3] ), .A1(\Din_c[5] ), .D0(\Din_c[5] ), - .B0(\Din_c[3] ), .A0(\Din_c[7] ), .M0(\Din_c[1] ), - .OFX0(\ram2e_ufm/N_338 )); - ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60 ( .D1(\Din_c[6] ), .C1(\CS[0] ), - .B1(\ram2e_ufm/N_193 ), .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), - .C0(CO0_0), .B0(\CmdTout[2] ), .A0(\CmdTout[1] ), .M0(RWSel), - .OFX0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 )); - ram2e_ufm_CKE_7_SLICE_61 \ram2e_ufm/CKE_7/SLICE_61 ( .D1(\ram2e_ufm/N_817 ), - .C1(\ram2e_ufm/N_821 ), .A1(\RC[1] ), .D0(nWE_c), .B0(\S[1] ), - .A0(\ram2e_ufm/N_804 ), .M0(\ram2e_ufm/CKE_7_sm0 ), - .OFX0(\ram2e_ufm/CKE_7 )); - ram2e_ufm_SLICE_62 \ram2e_ufm/SLICE_62 ( .D1(\Din_c[6] ), .C1(\CS[1] ), - .B1(\ram2e_ufm/N_851 ), .A1(\CS[2] ), .D0(\ram2e_ufm/SUM0_i_a3_4_0 ), - .C0(\CS[1] ), .B0(\ram2e_ufm/N_234 ), .A0(\CS[2] ), - .F0(\ram2e_ufm/N_720_tz ), .F1(\ram2e_ufm/SUM0_i_a3_4_0 )); - ram2e_ufm_SLICE_63 \ram2e_ufm/SLICE_63 ( .D1(\CS[0] ), - .C1(\ram2e_ufm/SUM0_i_0 ), .B1(\CS[2] ), .A1(\ram2e_ufm/N_350 ), - .D0(\ram2e_ufm/N_187 ), .C0(\ram2e_ufm/SUM0_i_3 ), - .B0(\ram2e_ufm/SUM0_i_1 ), .A0(\CS[0] ), .F0(\ram2e_ufm/SUM0_i_4 ), - .F1(\ram2e_ufm/SUM0_i_1 )); - ram2e_ufm_SLICE_64 \ram2e_ufm/SLICE_64 ( .C1(\FS[11] ), .B1(\FS[9] ), - .A1(\ram2e_ufm/N_793 ), .D0(\FS[13] ), .C0(\ram2e_ufm/N_856 ), - .B0(\ram2e_ufm/N_755 ), .A0(\FS[11] ), .F0(\ram2e_ufm/wb_adr_7_i_i_5[0] ), - .F1(\ram2e_ufm/N_755 )); - ram2e_ufm_SLICE_65 \ram2e_ufm/SLICE_65 ( .D1(\CS[0] ), .C1(\Din_c[0] ), - .B1(\Din_c[6] ), .A1(\ram2e_ufm/N_193 ), .D0(\CS[0] ), - .C0(\ram2e_ufm/N_735 ), .B0(\CS[1] ), .A0(\ram2e_ufm/N_345 ), - .F0(\ram2e_ufm/SUM0_i_0 ), .F1(\ram2e_ufm/N_735 )); - ram2e_ufm_SLICE_66 \ram2e_ufm/SLICE_66 ( .D1(\ram2e_ufm/wb_ack ), - .C1(\ram2e_ufm/N_777 ), .B1(\FS[14] ), - .A1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), - .D0(\ram2e_ufm/CmdExecMXO2 ), .C0(\ram2e_ufm/wb_ack ), - .B0(\ram2e_ufm/N_187 ), - .A0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ), - .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ), - .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] )); - ram2e_ufm_SLICE_67 \ram2e_ufm/SLICE_67 ( .C1(\FS[2] ), .B1(\FS[3] ), - .A1(\FS[1] ), .D0(\FS[4] ), .C0(\ram2e_ufm/N_250 ), .B0(\FS[3] ), - .A0(\S[1] ), .F0(\ram2e_ufm/N_256 ), .F1(\ram2e_ufm/N_250 )); - ram2e_ufm_SLICE_68 \ram2e_ufm/SLICE_68 ( .D1(\FS[8] ), .C1(\FS[9] ), - .B1(\ram2e_ufm/N_783 ), .A1(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), - .D0(\FS[12] ), .C0(\FS[8] ), .B0(\FS[10] ), .A0(\FS[11] ), - .F0(\ram2e_ufm/wb_adr_7_i_i_3_1[0] ), .F1(\ram2e_ufm/wb_adr_7_i_i_3[0] )); - ram2e_ufm_SLICE_69 \ram2e_ufm/SLICE_69 ( .D1(\FS[15] ), .C1(\FS[0] ), - .B1(\ram2e_ufm/N_254 ), .A1(\ram2e_ufm/wb_rst16_i ), .D0(\S[2] ), - .C0(\S[1] ), .B0(\S[0] ), .A0(\S[3] ), .F0(\ram2e_ufm/wb_rst16_i ), - .F1(\ram2e_ufm/N_641 )); - ram2e_ufm_SLICE_70 \ram2e_ufm/SLICE_70 ( .D1(\ram2e_ufm/N_777 ), - .B1(\FS[14] ), .A1(\FS[8] ), .D0(\FS[13] ), .C0(\ram2e_ufm/N_807 ), - .B0(\FS[12] ), .A0(\ram2e_ufm/N_876 ), .F0(\ram2e_ufm/N_604 ), - .F1(\ram2e_ufm/N_807 )); - ram2e_ufm_SLICE_71 \ram2e_ufm/SLICE_71 ( .D1(\FS[3] ), - .C1(\ram2e_ufm/N_784 ), .A1(\FS[4] ), .D0(\S[3] ), .C0(\S[0] ), - .A0(\S[2] ), .F0(\ram2e_ufm/N_784 ), .F1(\ram2e_ufm/N_801 )); - ram2e_ufm_SLICE_72 \ram2e_ufm/SLICE_72 ( .D1(\RWBank[5] ), - .C1(\ram2e_ufm/N_560 ), .B1(\FS[4] ), .A1(\S[0] ), .D0(\S[2] ), - .B0(\S[3] ), .A0(\S[1] ), .F0(\ram2e_ufm/N_560 ), .F1(\BA_4[0] )); - ram2e_ufm_SLICE_73 \ram2e_ufm/SLICE_73 ( .D1(\ram2e_ufm/N_781 ), - .C1(\ram2e_ufm/N_873 ), .B1(\ram2e_ufm/N_184 ), .A1(\ram2e_ufm/N_611 ), - .D0(\FS[9] ), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[8] ), - .F0(\ram2e_ufm/N_873 ), .F1(\ram2e_ufm/wb_dati_7_0_0_o3_0[2] )); - ram2e_ufm_SLICE_74 \ram2e_ufm/SLICE_74 ( .D1(\RWBank[3] ), - .C1(\ram2e_ufm/N_845 ), .A1(\ram2e_ufm/N_625 ), .D0(\S[1] ), .C0(\S[2] ), - .B0(\S[3] ), .A0(\S[0] ), .F0(\ram2e_ufm/N_845 ), - .F1(\ram2e_ufm/RA_35_2_0_0[10] )); - ram2e_ufm_SLICE_75 \ram2e_ufm/SLICE_75 ( .C1(\FS[9] ), .B1(\FS[10] ), - .A1(\FS[11] ), .D0(\FS[13] ), .C0(\ram2e_ufm/wb_ack ), - .B0(\ram2e_ufm/N_876 ), .A0(\FS[12] ), - .F0(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), - .F1(\ram2e_ufm/N_876 )); - ram2e_ufm_SLICE_76 \ram2e_ufm/SLICE_76 ( .B1(\FS[10] ), .A1(\FS[11] ), - .D0(\FS[13] ), .C0(\ram2e_ufm/N_811 ), .B0(\ram2e_ufm/N_206 ), - .A0(\FS[12] ), .F0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), - .F1(\ram2e_ufm/N_811 )); - ram2e_ufm_SLICE_77 \ram2e_ufm/SLICE_77 ( .D1(\CS[0] ), - .C1(\ram2e_ufm/N_185 ), .B1(RWSel), .D0(\S[2] ), .C0(\S[3] ), .B0(\S[1] ), - .A0(\S[0] ), .F0(\ram2e_ufm/N_185 ), .F1(\ram2e_ufm/N_215 )); - ram2e_ufm_SLICE_78 \ram2e_ufm/SLICE_78 ( .C1(\S[1] ), .A1(\S[0] ), - .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\S[2] ), .B0(\RWBank[1] ), .A0(\S[3] ), - .F0(\ram2e_ufm/N_699 ), .F1(\ram2e_ufm/S_r_i_0_o2[1] )); - ram2e_ufm_SLICE_79 \ram2e_ufm/SLICE_79 ( .D1(CmdLEDSet), - .C1(\ram2e_ufm/N_187 ), - .B1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_a3_0_1[0] ), - .A1(\ram2e_ufm/N_807 ), .D0(\S[2] ), .C0(RWSel), - .B0(\ram2e_ufm/S_r_i_0_o2[1] ), .A0(\S[3] ), .F0(\ram2e_ufm/N_187 ), - .F1(\ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] )); - ram2e_ufm_SLICE_80 \ram2e_ufm/SLICE_80 ( .D1(\S[0] ), .C1(\FS[15] ), - .B1(\S[1] ), .A1(N_551), .D0(RWSel), .C0(\ram2e_ufm/N_777 ), - .B0(\ram2e_ufm/CmdBitbangMXO2 ), .A0(\ram2e_ufm/N_185 ), - .F0(\ram2e_ufm/CmdBitbangMXO2_RNINSM62 ), .F1(\ram2e_ufm/N_777 )); - ram2e_ufm_SLICE_81 \ram2e_ufm/SLICE_81 ( .D1(\FS[14] ), - .C1(\ram2e_ufm/N_777 ), .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[12] ), - .C0(\FS[13] ), .B0(\ram2e_ufm/N_856 ), .A0(\ram2e_ufm/N_811 ), - .F0(\ram2e_ufm/N_757 ), .F1(\ram2e_ufm/N_856 )); - ram2e_ufm_SLICE_82 \ram2e_ufm/SLICE_82 ( .D1(\Din_c[6] ), .C1(\CS[0] ), - .B1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ), - .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), - .C0(\ram2e_ufm/N_637 ), .B0(\ram2e_ufm/N_185 ), - .A0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0 ), .F0(un1_CS_0_sqmuxa_i), - .F1(\ram2e_ufm/N_637 )); - ram2e_ufm_SLICE_83 \ram2e_ufm/SLICE_83 ( .D1(\CS[2] ), .C1(\Din_c[6] ), - .B1(\ram2e_ufm/N_851 ), .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ), - .C0(\CS[0] ), .B0(RWSel), .A0(\ram2e_ufm/N_592 ), - .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 )); - ram2e_ufm_SLICE_84 \ram2e_ufm/SLICE_84 ( .D1(\Din_c[4] ), - .C1(\ram2e_ufm/N_212 ), .B1(\CS[2] ), .A1(\ram2e_ufm/N_850 ), - .D0(\ram2e_ufm/N_720_tz ), .C0(\ram2e_ufm/N_886 ), .B0(\CS[1] ), - .A0(\ram2e_ufm/N_187 ), .F0(\ram2e_ufm/SUM0_i_3 ), .F1(\ram2e_ufm/N_886 )); - ram2e_ufm_SLICE_85 \ram2e_ufm/SLICE_85 ( .D1(\FS[14] ), .C1(\FS[12] ), - .B1(\FS[13] ), .A1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/N_187 ), - .C0(\ram2e_ufm/N_793 ), - .B0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), .A0(CmdRWMaskSet), - .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ), .F1(\ram2e_ufm/N_793 )); - ram2e_ufm_SLICE_86 \ram2e_ufm/SLICE_86 ( .C1(\Din_c[0] ), .A1(\S[2] ), - .D0(\ram2e_ufm/N_634 ), .C0(\ram2e_ufm/N_753 ), - .B0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), .A0(\ram2e_ufm/wb_adr_7_i_i_3[0] ), - .F0(\ram2e_ufm/wb_adr_7_i_i_4[0] ), .F1(\ram2e_ufm/N_634 )); - ram2e_ufm_SLICE_87 \ram2e_ufm/SLICE_87 ( .D1(\ram2e_ufm/N_190 ), - .C1(\ram2e_ufm/N_212 ), .B1(\Din_c[1] ), - .A1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C0(\ram2e_ufm/N_234 ), - .B0(\ram2e_ufm/N_886 ), .A0(\CS[1] ), .F0(\ram2e_ufm/N_592 ), - .F1(\ram2e_ufm/N_234 )); - ram2e_ufm_SLICE_88 \ram2e_ufm/SLICE_88 ( .B1(\FS[10] ), .A1(\FS[11] ), - .D0(\ram2e_ufm/N_876 ), .C0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), - .B0(\ram2e_ufm/N_206 ), .A0(\ram2e_ufm/N_793 ), - .F0(\ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] )); - ram2e_ufm_SLICE_89 \ram2e_ufm/SLICE_89 ( .D1(\FS[13] ), - .B1(\ram2e_ufm/N_777 ), .A1(\FS[14] ), - .D0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .C0(\ram2e_ufm/N_783 ), - .B0(\ram2e_ufm/wb_adr[3] ), .A0(\S[2] ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[3] ), .F1(\ram2e_ufm/N_783 )); - ram2e_ufm_SLICE_90 \ram2e_ufm/SLICE_90 ( .D1(\FS[10] ), - .C1(\ram2e_ufm/N_206 ), .B1(\FS[12] ), .A1(\FS[11] ), - .D0(\ram2e_ufm/wb_adr[6] ), .C0(\ram2e_ufm/N_783 ), - .B0(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] ), .A0(\S[2] ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0[6] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_1[6] )); - ram2e_ufm_SLICE_91 \ram2e_ufm/SLICE_91 ( .D1(CO0_1), .C1(\RC[1] ), - .B1(\RC[2] ), .A1(\ram2e_ufm/N_817 ), .D0(\ram2e_ufm/N_256 ), - .C0(\ram2e_ufm/N_784 ), .B0(\ram2e_ufm/N_890 ), .A0(\ram2e_ufm/N_285_i ), - .F0(\ram2e_ufm/nRAS_s_i_0_0 ), .F1(\ram2e_ufm/N_890 )); - ram2e_ufm_SLICE_92 \ram2e_ufm/SLICE_92 ( .D1(nWE_c), .C1(N_551), - .B1(\ram2e_ufm/N_804 ), .A1(\S[1] ), .D0(\ram2e_ufm/N_890 ), - .C0(\ram2e_ufm/N_285_i ), .B0(\ram2e_ufm/N_220 ), .A0(\S[0] ), - .F0(\ram2e_ufm/N_640 ), .F1(\ram2e_ufm/N_220 )); - ram2e_ufm_SLICE_93 \ram2e_ufm/SLICE_93 ( .D1(\FS[9] ), .C1(\FS[8] ), - .B1(\FS[10] ), .A1(\FS[11] ), .C0(\ram2e_ufm/N_783 ), .B0(\FS[12] ), - .A0(\ram2e_ufm/N_196 ), .F0(\ram2e_ufm/N_760 ), .F1(\ram2e_ufm/N_196 )); - ram2e_ufm_SLICE_94 \ram2e_ufm/SLICE_94 ( .D1(\Din_c[7] ), .C1(\Din_c[4] ), - .D0(\Din_c[0] ), .C0(\CS[2] ), .B0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), - .A0(\ram2e_ufm/N_243 ), .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 )); - ram2e_ufm_SLICE_95 \ram2e_ufm/SLICE_95 ( .D1(\S[2] ), .C1(\S[1] ), - .B1(\S[0] ), .A1(\S[3] ), .D0(\Ain_c[4] ), .C0(\ram2e_ufm/N_186 ), - .B0(\ram2e_ufm/N_182 ), .A0(\RA[4] ), .F0(\ram2e_ufm/RA_35_0_0_0[4] ), - .F1(\ram2e_ufm/N_182 )); - ram2e_ufm_SLICE_96 \ram2e_ufm/SLICE_96 ( .D1(\S[2] ), .C1(\S[1] ), - .B1(\S[0] ), .A1(\S[3] ), .D0(\ram2e_ufm/N_182 ), .C0(\ram2e_ufm/N_186 ), - .B0(\RA[6] ), .A0(\Ain_c[6] ), .F0(\ram2e_ufm/RA_35_0_0_0_0[6] ), - .F1(\ram2e_ufm/N_186 )); - ram2e_ufm_SLICE_97 \ram2e_ufm/SLICE_97 ( .D1(\FS[13] ), - .C1(\ram2e_ufm/N_873 ), .A1(\FS[12] ), .D0(\ram2e_ufm/wb_adr[1] ), - .C0(\ram2e_ufm/N_781 ), .B0(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ), - .A0(\S[2] ), .F0(\ram2e_ufm/wb_dati_7_0_0_0[1] ), - .F1(\ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] )); - ram2e_ufm_SLICE_98 \ram2e_ufm/SLICE_98 ( .D1(\FS[14] ), - .C1(\ram2e_ufm/N_777 ), .D0(\ram2e_ufm/wb_adr[7] ), - .C0(\ram2e_ufm/wb_dati_7_0_0_a3_8_0[7] ), .B0(\ram2e_ufm/N_781 ), - .A0(\S[2] ), .F0(\ram2e_ufm/wb_dati_7_0_0_0_0[7] ), .F1(\ram2e_ufm/N_781 )); - ram2e_ufm_SLICE_99 \ram2e_ufm/SLICE_99 ( .D1(\FS[11] ), .B1(\FS[10] ), - .A1(\FS[8] ), .D0(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ), - .C0(\ram2e_ufm/N_781 ), .B0(\ram2e_ufm/N_565 ), .A0(\FS[12] ), - .F0(\ram2e_ufm/wb_adr_7_i_i_1[0] ), - .F1(\ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] )); - ram2e_ufm_SLICE_100 \ram2e_ufm/SLICE_100 ( .D1(\Din_c[1] ), .C1(\Din_c[3] ), - .B1(\Din_c[5] ), .A1(\Din_c[2] ), .D0(\ram2e_ufm/N_243 ), .C0(\CS[2] ), - .B0(\Din_c[7] ), .A0(\Din_c[4] ), .F0(\ram2e_ufm/N_345 ), - .F1(\ram2e_ufm/N_243 )); - ram2e_ufm_SLICE_101 \ram2e_ufm/SLICE_101 ( .C1(\Din_c[3] ), .B1(\Din_c[5] ), - .D0(\ram2e_ufm/N_190 ), .C0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ), - .B0(\CS[1] ), .A0(\ram2e_ufm/N_850 ), - .F0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ), .F1(\ram2e_ufm/N_190 )); - ram2e_ufm_SLICE_102 \ram2e_ufm/SLICE_102 ( .D1(\S[2] ), .C1(\S[1] ), - .A1(\S[3] ), .C0(\ram2e_ufm/N_817 ), .B0(\ram2e_ufm/N_220 ), - .A0(\ram2e_ufm/CKE_7s2_0_0_0 ), .F0(\ram2e_ufm/CKE_7_sm0 ), - .F1(\ram2e_ufm/N_817 )); - ram2e_ufm_SLICE_103 \ram2e_ufm/SLICE_103 ( .D1(\FS[13] ), .A1(\FS[12] ), - .D0(\ram2e_ufm/N_204 ), .C0(\ram2e_ufm/N_184 ), .B0(\ram2e_ufm/N_799 ), - .A0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), .F0(\ram2e_ufm/wb_adr_7_5_41_0_1 ), - .F1(\ram2e_ufm/N_184 )); - ram2e_ufm_SLICE_104 \ram2e_ufm/SLICE_104 ( .D1(\FS[8] ), .C1(\FS[11] ), - .B1(\FS[9] ), .A1(\FS[10] ), .C0(\ram2e_ufm/N_595 ), .B0(\FS[12] ), - .F0(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ), .F1(\ram2e_ufm/N_595 )); - ram2e_ufm_SLICE_105 \ram2e_ufm/SLICE_105 ( .D1(\ram2e_ufm/nRWE_s_i_0_63_1 ), - .C1(\ram2e_ufm/N_285_i ), .B1(\ram2e_ufm/S_r_i_0_o2[1] ), .A1(\S[3] ), - .D0(\ram2e_ufm/wb_rst16_i ), .C0(\FS[15] ), .B0(\FS[0] ), - .F0(\ram2e_ufm/N_285_i ), .F1(\ram2e_ufm/S_r_i_0_o2_RNI62C53[1] )); - ram2e_ufm_SLICE_106 \ram2e_ufm/SLICE_106 ( .C1(\S[1] ), .A1(\S[0] ), - .D0(\ram2e_ufm/S_r_i_0_o2[1] ), .C0(\ram2e_ufm/N_194 ), .B0(\RA[10] ), - .A0(\S[2] ), .F0(\ram2e_ufm/N_624 ), .F1(\ram2e_ufm/N_194 )); - ram2e_ufm_SLICE_107 \ram2e_ufm/SLICE_107 ( .D1(\FS[4] ), .C1(\S[2] ), - .B1(\S[0] ), .A1(\S[3] ), .D0(\FS[5] ), .C0(\ram2e_ufm/N_792 ), - .B0(\FS[8] ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_659 ), .F1(\ram2e_ufm/N_792 )); - ram2e_ufm_SLICE_108 \ram2e_ufm/SLICE_108 ( - .D1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ), .C1(\FS[7] ), - .B1(\FS[4] ), .A1(\FS[5] ), .D0(\ram2e_ufm/wb_req ), - .C0(\ram2e_ufm/N_336 ), .B0(\FS[0] ), - .F0(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ), - .F1(\ram2e_ufm/N_336 )); - ram2e_ufm_SLICE_109 \ram2e_ufm/SLICE_109 ( .C1(\FS[14] ), .A1(\S[2] ), - .D0(\FS[11] ), .C0(\ram2e_ufm/N_184 ), .B0(\ram2e_ufm/N_799 ), - .A0(\ram2e_ufm/N_634 ), .F0(\ram2e_ufm/wb_we_7_iv_0_0_3_0_0 ), - .F1(\ram2e_ufm/N_799 )); - ram2e_ufm_SLICE_110 \ram2e_ufm/SLICE_110 ( .D1(\FS[10] ), .C1(\FS[9] ), - .B1(\FS[11] ), .A1(\FS[8] ), .D0(\ram2e_ufm/wb_ack ), - .C0(\ram2e_ufm/N_885 ), - .F0(\ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ), - .F1(\ram2e_ufm/N_885 )); - ram2e_ufm_SLICE_111 \ram2e_ufm/SLICE_111 ( .D1(\FS[12] ), - .C1(\ram2e_ufm/N_553 ), .A1(\ram2e_ufm/N_807 ), - .D0(\ram2e_ufm/wb_dati_7_0_0_a3_6_1[3] ), .C0(\FS[13] ), .B0(\FS[9] ), - .A0(\ram2e_ufm/N_811 ), .F0(\ram2e_ufm/N_553 ), .F1(\ram2e_ufm/N_611 )); - ram2e_ufm_SLICE_112 \ram2e_ufm/SLICE_112 ( .D1(\S[1] ), .B1(\S[0] ), - .A1(\ram2e_ufm/N_285_i ), .D0(\S[2] ), .C0(\ram2e_ufm/N_866 ), .B0(nWE_c), - .A0(nEN80_c), .F0(\ram2e_ufm/N_616 ), .F1(\ram2e_ufm/N_866 )); - ram2e_ufm_SLICE_113 \ram2e_ufm/SLICE_113 ( .D1(\S[2] ), .B1(nEN80_c), - .A1(\S[3] ), .D0(\S[1] ), .C0(\ram2e_ufm/N_804 ), .B0(nWE_c), .A0(\S[0] ), - .F0(\ram2e_ufm/N_628 ), .F1(\ram2e_ufm/N_804 )); - ram2e_ufm_SLICE_114 \ram2e_ufm/SLICE_114 ( .C1(\FS[10] ), .B1(\FS[9] ), - .A1(\FS[8] ), .D0(\ram2e_ufm/N_241_i ), .C0(\ram2e_ufm/N_799 ), - .B0(\FS[12] ), .A0(\FS[11] ), .F0(\ram2e_ufm/N_768 ), - .F1(\ram2e_ufm/N_241_i )); - ram2e_ufm_SLICE_115 \ram2e_ufm/SLICE_115 ( .D1(\S[2] ), .C1(\S[1] ), - .D0(\S[0] ), .C0(\ram2e_ufm/N_221 ), .B0(nEN80_c), .A0(\S[3] ), - .F0(\ram2e_ufm/CKE_7s2_0_0_0 ), .F1(\ram2e_ufm/N_221 )); - ram2e_ufm_SLICE_116 \ram2e_ufm/SLICE_116 ( - .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ), .C1(\ram2e_ufm/N_814 ), - .B1(\Din_c[5] ), .A1(\Din_c[3] ), .C0(\Din_c[0] ), .B0(\Din_c[2] ), - .A0(\Din_c[1] ), .F0(\ram2e_ufm/N_814 ), .F1(\ram2e_ufm/N_851 )); - ram2e_ufm_SLICE_117 \ram2e_ufm/SLICE_117 ( .D1(\S[2] ), .C1(\S[1] ), - .B1(\S[3] ), .A1(\S[0] ), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[3] ), - .A0(\S[0] ), .F0(N_225_i), .F1(\ram2e_ufm/N_643 )); - ram2e_ufm_SLICE_118 \ram2e_ufm/SLICE_118 ( .D1(\S[2] ), .C1(\S[1] ), - .B1(\S[0] ), .A1(\S[3] ), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[0] ), - .A0(\S[3] ), .F0(N_201_i), .F1(RC12)); - ram2e_ufm_SLICE_119 \ram2e_ufm/SLICE_119 ( .D1(\S[2] ), .C1(\S[1] ), - .B1(\S[0] ), .A1(\S[3] ), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[0] ), - .A0(\S[3] ), .F0(N_126), .F1(N_185_i)); - ram2e_ufm_SLICE_120 \ram2e_ufm/SLICE_120 ( .D1(\S[3] ), .C1(\RWBank[0] ), - .B1(\FS[15] ), .A1(\S[0] ), .D0(\S[3] ), .C0(\RWBank[0] ), .B0(\FS[15] ), - .A0(\S[0] ), .F0(N_507_i), .F1(N_508)); - ram2e_ufm_SLICE_121 \ram2e_ufm/SLICE_121 ( .D1(\S[2] ), .C1(\S[1] ), - .B1(\S[3] ), .A1(\S[0] ), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[3] ), - .A0(\S[0] ), .F0(\ram2e_ufm/N_242 ), .F1(Vout3)); - ram2e_ufm_SLICE_122 \ram2e_ufm/SLICE_122 ( .D1(\FS[3] ), .C1(\FS[2] ), - .B1(\FS[1] ), .A1(\FS[4] ), .D0(\FS[3] ), .C0(\FS[2] ), .B0(\FS[1] ), - .A0(\FS[4] ), .F0(\ram2e_ufm/N_254 ), .F1(\ram2e_ufm/nRWE_s_i_0_63_1 )); - ram2e_ufm_SLICE_123 \ram2e_ufm/SLICE_123 ( .D1(\FS[8] ), .C1(\FS[11] ), - .B1(\FS[9] ), .D0(\FS[10] ), .C0(\FS[11] ), .B0(\FS[9] ), .A0(\FS[8] ), - .F0(\ram2e_ufm/N_849 ), .F1(\ram2e_ufm/N_204 )); - ram2e_ufm_SLICE_124 \ram2e_ufm/SLICE_124 ( .D1(\FS[4] ), .C1(\FS[12] ), - .B1(\ram2e_ufm/N_784 ), .A1(\FS[3] ), .D0(\FS[4] ), .C0(\FS[1] ), - .B0(\ram2e_ufm/N_784 ), .A0(\FS[3] ), .F0(\ram2e_ufm/N_684 ), - .F1(\ram2e_ufm/RA_35_0_0_0[5] )); - ram2e_ufm_SLICE_125 \ram2e_ufm/SLICE_125 ( .D1(\FS[9] ), .C1(\FS[11] ), - .B1(\FS[13] ), .A1(\FS[8] ), .D0(\FS[8] ), .C0(\FS[11] ), .B0(\FS[9] ), - .A0(\ram2e_ufm/N_793 ), .F0(\ram2e_ufm/N_763 ), .F1(\ram2e_ufm/N_565 )); - ram2e_ufm_SLICE_126 \ram2e_ufm/SLICE_126 ( .D1(\FS[8] ), .C1(\FS[10] ), - .B1(\FS[9] ), .A1(\FS[12] ), .D0(\ram2e_ufm/N_781 ), .C0(\FS[10] ), - .B0(\FS[9] ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_753 ), - .F1(\ram2e_ufm/N_208 )); - ram2e_ufm_SLICE_127 \ram2e_ufm/SLICE_127 ( .D1(\S[2] ), .C1(\S[0] ), - .B1(\S[3] ), .A1(\S[1] ), .D0(\S[2] ), .C0(\S[0] ), .B0(\S[3] ), - .A0(\RWBank[7] ), .F0(\ram2e_ufm/N_698 ), .F1(un9_VOEEN_0_a2_0_a3_0_a3)); - ram2e_ufm_SLICE_128 \ram2e_ufm/SLICE_128 ( .D1(\FS[13] ), .C1(\FS[11] ), - .B1(\FS[10] ), .A1(\FS[12] ), .D0(\FS[13] ), .C0(\FS[12] ), .B0(\FS[10] ), - .F0(\ram2e_ufm/wb_adr_7_5_41_a3_3_0 ), - .F1(\ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] )); - ram2e_ufm_SLICE_129 \ram2e_ufm/SLICE_129 ( .D1(\S[0] ), - .C1(\ram2e_ufm/N_560 ), .B1(\FS[4] ), .A1(\RWBank[6] ), .D0(\S[0] ), - .C0(N_551), .B0(\FS[4] ), .A0(\FS[1] ), .F0(\ram2e_ufm/N_627 ), - .F1(\BA_4[1] )); - ram2e_ufm_SLICE_130 \ram2e_ufm/SLICE_130 ( .C1(RWSel), - .A1(\ram2e_ufm/N_185 ), .D0(\ram2e_ufm/N_777 ), .C0(RWSel), - .B0(\ram2e_ufm/CmdExecMXO2 ), .A0(\ram2e_ufm/N_185 ), - .F0(\ram2e_ufm/wb_we_RNO_0 ), .F1(N_187_i)); - ram2e_ufm_SLICE_131 \ram2e_ufm/SLICE_131 ( .D1(\FS[1] ), .C1(\FS[13] ), - .B1(\FS[12] ), .A1(\FS[3] ), .D0(\FS[13] ), .C0(\ram2e_ufm/N_856 ), - .B0(\ram2e_ufm/N_811 ), .A0(\FS[12] ), .F0(\ram2e_ufm/N_602 ), - .F1(\ram2e_ufm/Ready3_0_a3_5 )); - ram2e_ufm_SLICE_132 \ram2e_ufm/SLICE_132 ( .D1(\ram2e_ufm/N_182 ), - .C1(\Ain_c[0] ), .B1(\ram2e_ufm/N_186 ), .A1(\RA[0] ), - .D0(\ram2e_ufm/N_182 ), .C0(\Ain_c[7] ), .B0(\RA[7] ), - .A0(\ram2e_ufm/N_186 ), .F0(\ram2e_ufm/RA_35_0_0_0_0[7] ), - .F1(\ram2e_ufm/RA_35_0_0_1[0] )); - ram2e_ufm_SLICE_133 \ram2e_ufm/SLICE_133 ( .D1(\Din_c[2] ), .C1(\Din_c[0] ), - .B1(\Din_c[4] ), .A1(RWSel), .D0(\Din_c[2] ), .C0(\ram2e_ufm/N_338 ), - .B0(\Din_c[4] ), .F0(\ram2e_ufm/N_350 ), - .F1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 )); - ram2e_ufm_SLICE_134 \ram2e_ufm/SLICE_134 ( .D1(\FS[6] ), .C1(\FS[3] ), - .B1(\FS[1] ), .A1(\FS[2] ), .D0(\FS[6] ), .C0(\FS[3] ), .B0(\FS[9] ), - .A0(\ram2e_ufm/N_792 ), .F0(\ram2e_ufm/N_679 ), - .F1(\ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] )); - ram2e_ufm_SLICE_135 \ram2e_ufm/SLICE_135 ( .D1(\S[3] ), .C1(\S[2] ), - .D0(\S[3] ), .C0(\S[2] ), .B0(nEN80_c), .A0(\ram2e_ufm/S_r_i_0_o2[1] ), - .F0(\ram2e_ufm/N_625 ), .F1(\ram2e_ufm/N_271 )); - ram2e_ufm_SLICE_136 \ram2e_ufm/SLICE_136 ( .D1(nEN80_c), .C1(\S[3] ), - .B1(nWE_c), .C0(nEN80_c), .B0(nWE_c), .A0(DOEEN), .F0(nDOE_c), - .F1(\ram2e_ufm/N_226 )); - ram2e_ufm_SLICE_137 \ram2e_ufm/SLICE_137 ( .D1(nWE_c), .C1(nEN80_c), - .A1(Ready), .D0(\ram2e_ufm/LEDEN ), .C0(nEN80_c), .A0(Ready), .F0(LED_c), - .F1(RDOE_i)); - SLICE_138 SLICE_138( .C1(\S[0] ), .B1(\S[3] ), .A1(\S[1] ), .D0(\S[2] ), - .C0(\S[0] ), .B0(\S[1] ), .F0(N_1080_0), .F1(N_1078_0)); - SLICE_139 SLICE_139( .C1(VOEEN), .A1(PHI1_c), .D0(Ready), .B0(PHI1r), - .A0(PHI1_c), .F0(S_1), .F1(nVOE_c)); - ram2e_ufm_SLICE_140 \ram2e_ufm/SLICE_140 ( .C1(\ram2e_ufm/N_186 ), - .A1(\RA[2] ), .D0(\RA[5] ), .C0(\ram2e_ufm/N_186 ), .F0(\ram2e_ufm/N_621 ), - .F1(\ram2e_ufm/N_680 )); - ram2e_ufm_SLICE_141 \ram2e_ufm/SLICE_141 ( .D1(Ready), .C1(\Din_c[0] ), - .D0(Ready), .B0(\Din_c[3] ), .F0(N_263_i), .F1(N_667)); - ram2e_ufm_SLICE_142 \ram2e_ufm/SLICE_142 ( .D1(\Din_c[4] ), .C1(\Din_c[0] ), - .B1(\Din_c[7] ), .D0(\Din_c[4] ), .B0(Ready), .F0(N_648), - .F1(\ram2e_ufm/CmdLEDGet_3_0_a3_1 )); - ram2e_ufm_SLICE_143 \ram2e_ufm/SLICE_143 ( .D1(\Din_c[1] ), .B1(Ready), - .D0(\Din_c[7] ), .B0(Ready), .F0(N_662), .F1(N_666)); - ram2e_ufm_SLICE_144 \ram2e_ufm/SLICE_144 ( .B1(Ready), .A1(\Din_c[2] ), - .D0(\Din_c[6] ), .B0(Ready), .F0(N_663), .F1(N_665)); - ram2e_ufm_SLICE_145 \ram2e_ufm/SLICE_145 ( .D1(\ram2e_ufm/N_873 ), - .C1(\ram2e_ufm/wb_adr[4] ), .B1(\ram2e_ufm/N_783 ), .A1(\S[2] ), - .C0(\FS[8] ), .B0(\FS[9] ), .F0(\ram2e_ufm/N_206 ), - .F1(\ram2e_ufm/wb_dati_7_0_0_0[4] )); - ram2e_ufm_SLICE_146 \ram2e_ufm/SLICE_146 ( .D1(\FS[4] ), .C1(\RWBank[2] ), - .B1(\ram2e_ufm/N_784 ), .A1(\ram2e_ufm/N_845 ), .D0(\FS[0] ), .C0(\FS[6] ), - .B0(\FS[5] ), .A0(\FS[7] ), .F0(\ram2e_ufm/Ready3_0_a3_3 ), - .F1(\ram2e_ufm/RA_35_0_0_0[9] )); - ram2e_ufm_SLICE_147 \ram2e_ufm/SLICE_147 ( .D1(CmdLEDGet), - .C1(\ram2e_ufm/LEDEN ), .B1(CmdSetRWBankFFLED), - .A1(\ram2e_ufm/CmdSetRWBankFFChip ), .C0(\Din_c[5] ), .B0(Ready), - .F0(N_664), .F1(\ram2e_ufm/N_188 )); - RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(N_667), - .RD0(RD[0])); - LED LED_I( .PADDO(LED_c), .LED(LED)); - C14M C14M_I( .PADDI(C14M_c), .C14M(C14M)); - RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(N_662), - .RD7(RD[7])); - RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(N_663), - .RD6(RD[6])); - RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(N_664), - .RD5(RD[5])); - RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(N_648), - .RD4(RD[4])); - RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(N_263_i), - .RD3(RD[3])); - RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(N_665), - .RD2(RD[2])); - RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(N_666), - .RD1(RD[1])); - DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH)); - DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_508), .CE(N_201_i), - .CLK(C14M_c)); - DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML)); - DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_507_i), .CE(N_201_i), - .CLK(C14M_c)); - RAout_11_ \RAout[11]_I ( .IOLDO(\RAout_c[11] ), .RAout11(RAout[11])); - RAout_11__MGIOL \RAout[11]_MGIOL ( .IOLDO(\RAout_c[11] ), .OPOS(\RA[11] ), - .CLK(C14M_c)); - RAout_10_ \RAout[10]_I ( .IOLDO(\RAout_c[10] ), .RAout10(RAout[10])); - RAout_10__MGIOL \RAout[10]_MGIOL ( .IOLDO(\RAout_c[10] ), .OPOS(\RA[10] ), - .CLK(C14M_c)); - RAout_9_ \RAout[9]_I ( .IOLDO(\RAout_c[9] ), .RAout9(RAout[9])); - RAout_9__MGIOL \RAout[9]_MGIOL ( .IOLDO(\RAout_c[9] ), .OPOS(\RA[9] ), - .CLK(C14M_c)); - RAout_8_ \RAout[8]_I ( .IOLDO(\RAout_c[8] ), .RAout8(RAout[8])); - RAout_8__MGIOL \RAout[8]_MGIOL ( .IOLDO(\RAout_c[8] ), .OPOS(\RA[8] ), - .CLK(C14M_c)); - RAout_7_ \RAout[7]_I ( .IOLDO(\RAout_c[7] ), .RAout7(RAout[7])); - RAout_7__MGIOL \RAout[7]_MGIOL ( .IOLDO(\RAout_c[7] ), .OPOS(\RA[7] ), - .CLK(C14M_c)); - RAout_6_ \RAout[6]_I ( .IOLDO(\RAout_c[6] ), .RAout6(RAout[6])); - RAout_6__MGIOL \RAout[6]_MGIOL ( .IOLDO(\RAout_c[6] ), .OPOS(\RA[6] ), - .CLK(C14M_c)); - RAout_5_ \RAout[5]_I ( .IOLDO(\RAout_c[5] ), .RAout5(RAout[5])); - RAout_5__MGIOL \RAout[5]_MGIOL ( .IOLDO(\RAout_c[5] ), .OPOS(\RA[5] ), - .CLK(C14M_c)); - RAout_4_ \RAout[4]_I ( .IOLDO(\RAout_c[4] ), .RAout4(RAout[4])); - RAout_4__MGIOL \RAout[4]_MGIOL ( .IOLDO(\RAout_c[4] ), .OPOS(\RA[4] ), - .CLK(C14M_c)); - RAout_3_ \RAout[3]_I ( .IOLDO(\RAout_c[3] ), .RAout3(RAout[3])); - RAout_3__MGIOL \RAout[3]_MGIOL ( .IOLDO(\RAout_c[3] ), .OPOS(\RA[3] ), - .CLK(C14M_c)); - RAout_2_ \RAout[2]_I ( .IOLDO(\RAout_c[2] ), .RAout2(RAout[2])); - RAout_2__MGIOL \RAout[2]_MGIOL ( .IOLDO(\RAout_c[2] ), .OPOS(\RA[2] ), - .CLK(C14M_c)); - RAout_1_ \RAout[1]_I ( .IOLDO(\RAout_c[1] ), .RAout1(RAout[1])); - RAout_1__MGIOL \RAout[1]_MGIOL ( .IOLDO(\RAout_c[1] ), .OPOS(\RA[1] ), - .CLK(C14M_c)); - RAout_0_ \RAout[0]_I ( .IOLDO(\RAout_c[0] ), .RAout0(RAout[0])); - RAout_0__MGIOL \RAout[0]_MGIOL ( .IOLDO(\RAout_c[0] ), .OPOS(\RA[0] ), - .CLK(C14M_c)); - BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1])); - BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), .CE(N_225_i), - .LSR(BA_0_sqmuxa), .CLK(C14M_c)); - BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0])); - BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), .CE(N_225_i), - .LSR(BA_0_sqmuxa), .CLK(C14M_c)); - nRWEout nRWEout_I( .IOLDO(nRWEout_c), .nRWEout(nRWEout)); - nRWEout_MGIOL nRWEout_MGIOL( .IOLDO(nRWEout_c), .OPOS(nRWE), .CLK(C14M_c)); - nCASout nCASout_I( .IOLDO(nCASout_c), .nCASout(nCASout)); - nCASout_MGIOL nCASout_MGIOL( .IOLDO(nCASout_c), .OPOS(nCAS), .CLK(C14M_c)); - nRASout nRASout_I( .IOLDO(nRASout_c), .nRASout(nRASout)); - nRASout_MGIOL nRASout_MGIOL( .IOLDO(nRASout_c), .OPOS(nRAS), .CLK(C14M_c)); - nCSout nCSout_I( .PADDO(GND), .nCSout(nCSout)); - CKEout CKEout_I( .IOLDO(CKEout_c), .CKEout(CKEout)); - CKEout_MGIOL CKEout_MGIOL( .IOLDO(CKEout_c), .OPOS(CKE), .CLK(C14M_c)); - nVOE nVOE_I( .PADDO(nVOE_c), .nVOE(nVOE)); - Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7])); - Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_6_ \Vout[6]_I ( .IOLDO(\Vout_c[6] ), .Vout6(Vout[6])); - Vout_6__MGIOL \Vout[6]_MGIOL ( .IOLDO(\Vout_c[6] ), .OPOS(\RD_in[6] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_5_ \Vout[5]_I ( .IOLDO(\Vout_c[5] ), .Vout5(Vout[5])); - Vout_5__MGIOL \Vout[5]_MGIOL ( .IOLDO(\Vout_c[5] ), .OPOS(\RD_in[5] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_4_ \Vout[4]_I ( .IOLDO(\Vout_c[4] ), .Vout4(Vout[4])); - Vout_4__MGIOL \Vout[4]_MGIOL ( .IOLDO(\Vout_c[4] ), .OPOS(\RD_in[4] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_3_ \Vout[3]_I ( .IOLDO(\Vout_c[3] ), .Vout3(Vout[3])); - Vout_3__MGIOL \Vout[3]_MGIOL ( .IOLDO(\Vout_c[3] ), .OPOS(\RD_in[3] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_2_ \Vout[2]_I ( .IOLDO(\Vout_c[2] ), .Vout2(Vout[2])); - Vout_2__MGIOL \Vout[2]_MGIOL ( .IOLDO(\Vout_c[2] ), .OPOS(\RD_in[2] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_1_ \Vout[1]_I ( .IOLDO(\Vout_c[1] ), .Vout1(Vout[1])); - Vout_1__MGIOL \Vout[1]_MGIOL ( .IOLDO(\Vout_c[1] ), .OPOS(\RD_in[1] ), - .CE(Vout3), .CLK(C14M_c)); - Vout_0_ \Vout[0]_I ( .IOLDO(\Vout_c[0] ), .Vout0(Vout[0])); - Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), - .CE(Vout3), .CLK(C14M_c)); - nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE)); - Dout_7_ \Dout[7]_I ( .PADDO(\RD_in[7] ), .Dout7(Dout[7])); - Dout_6_ \Dout[6]_I ( .PADDO(\RD_in[6] ), .Dout6(Dout[6])); - Dout_5_ \Dout[5]_I ( .PADDO(\RD_in[5] ), .Dout5(Dout[5])); - Dout_4_ \Dout[4]_I ( .PADDO(\RD_in[4] ), .Dout4(Dout[4])); - Dout_3_ \Dout[3]_I ( .PADDO(\RD_in[3] ), .Dout3(Dout[3])); - Dout_2_ \Dout[2]_I ( .PADDO(\RD_in[2] ), .Dout2(Dout[2])); - Dout_1_ \Dout[1]_I ( .PADDO(\RD_in[1] ), .Dout1(Dout[1])); - Dout_0_ \Dout[0]_I ( .PADDO(\RD_in[0] ), .Dout0(Dout[0])); - Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7])); - Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6])); - Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5])); - Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4])); - Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3])); - Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2])); - Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1])); - Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0])); - Ain_7_ \Ain[7]_I ( .PADDI(\Ain_c[7] ), .Ain7(Ain[7])); - Ain_6_ \Ain[6]_I ( .PADDI(\Ain_c[6] ), .Ain6(Ain[6])); - Ain_5_ \Ain[5]_I ( .PADDI(\Ain_c[5] ), .Ain5(Ain[5])); - Ain_4_ \Ain[4]_I ( .PADDI(\Ain_c[4] ), .Ain4(Ain[4])); - Ain_3_ \Ain[3]_I ( .PADDI(\Ain_c[3] ), .Ain3(Ain[3])); - Ain_2_ \Ain[2]_I ( .PADDI(\Ain_c[2] ), .Ain2(Ain[2])); - Ain_1_ \Ain[1]_I ( .PADDI(\Ain_c[1] ), .Ain1(Ain[1])); - Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0])); - nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X)); - nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80)); - nWE nWE_I( .PADDI(nWE_c), .nWE(nWE)); - PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1)); - PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1r)); - ram2e_ufm_ufmefb_EFBInst_0 \ram2e_ufm/ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), - .WBRSTI(\ram2e_ufm/wb_rst ), .WBCYCI(\ram2e_ufm/wb_cyc_stb ), - .WBSTBI(\ram2e_ufm/wb_cyc_stb ), .WBWEI(\ram2e_ufm/wb_we ), - .WBADRI0(\ram2e_ufm/wb_adr[0] ), .WBADRI1(\ram2e_ufm/wb_adr[1] ), - .WBADRI2(\ram2e_ufm/wb_adr[2] ), .WBADRI3(\ram2e_ufm/wb_adr[3] ), - .WBADRI4(\ram2e_ufm/wb_adr[4] ), .WBADRI5(\ram2e_ufm/wb_adr[5] ), - .WBADRI6(\ram2e_ufm/wb_adr[6] ), .WBADRI7(\ram2e_ufm/wb_adr[7] ), - .WBDATI0(\ram2e_ufm/wb_dati[0] ), .WBDATI1(\ram2e_ufm/wb_dati[1] ), - .WBDATI2(\ram2e_ufm/wb_dati[2] ), .WBDATI3(\ram2e_ufm/wb_dati[3] ), - .WBDATI4(\ram2e_ufm/wb_dati[4] ), .WBDATI5(\ram2e_ufm/wb_dati[5] ), - .WBDATI6(\ram2e_ufm/wb_dati[6] ), .WBDATI7(\ram2e_ufm/wb_dati[7] ), - .WBDATO0(\ram2e_ufm/wb_dato[0] ), .WBDATO1(\ram2e_ufm/wb_dato[1] ), - .WBDATO2(\ram2e_ufm/wb_dato[2] ), .WBDATO3(\ram2e_ufm/wb_dato[3] ), - .WBDATO4(\ram2e_ufm/wb_dato[4] ), .WBDATO5(\ram2e_ufm/wb_dato[5] ), - .WBDATO6(\ram2e_ufm/wb_dato[6] ), .WBDATO7(\ram2e_ufm/wb_dato[7] ), - .WBACKO(\ram2e_ufm/wb_ack )); - VHI VHI_INST( .Z(VCCI)); - PUR PUR_INST( .PUR(VCCI)); - GSR GSR_INST( .GSR(VCCI)); -endmodule - -module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly; - - vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module vcc ( output PWR1 ); - - VHI INST1( .Z(PWR1)); -endmodule - -module gnd ( output PWR0 ); - - VLO INST1( .Z(PWR0)); -endmodule - -module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h000A; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - ccu20001 \FS_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); - - specify - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h5002; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); - - CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), - .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); - defparam inst1.INIT0 = 16'h300A; - defparam inst1.INIT1 = 16'h300A; - defparam inst1.INJECT1_0 = "NO"; - defparam inst1.INJECT1_1 = "NO"; -endmodule - -module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), - .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); - - specify - (A1 => F1) = (0:0:0,0:0:0); - (A1 => FCO) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (A0 => F1) = (0:0:0,0:0:0); - (A0 => FCO) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - (FCI => F0) = (0:0:0,0:0:0); - (FCI => F1) = (0:0:0,0:0:0); - (FCI => FCO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_9 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, Q0, - F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut4 \ram2e_ufm/wb_req_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40003 \ram2e_ufm/CKE_7_RNIS77M1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0004 CKE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut4 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40003 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF01) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0004 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3BX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_10 ( input D0, A0, DI0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40005 GND( .A(GNDI), .B(GNDI), .C(GNDI), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40006 \ram2e_ufm/CmdTout_3_0_a3_0_a3[0] ( .A(A0), .B(GNDI), .C(GNDI), - .D(D0), .Z(F0)); - vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40005 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40006 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_11 ( input B1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40007 \ram2e_ufm/RC_3_0_0_a3_1[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40008 \ram2e_ufm/N_360_i ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - vmuxregsre \RC[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40007 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40008 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1133) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_12 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, LSR, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; - - lut40009 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNI6S1P8 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40010 \ram2e_ufm/S_r_i_0_o2_RNIVM0LF[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0011 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre0011 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40009 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF54) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40010 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0D0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module vmuxregsre0011 ( input D0, D1, SD, SP, CK, LSR, output Q ); - - FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module SLICE_13 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, LSR, CLK, output - F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40012 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514_0 ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40013 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIC4514 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - vmuxregsre0011 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40012 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC4C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40013 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA2A6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_14 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40014 \ram2e_ufm/CmdLEDGet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40015 \ram2e_ufm/CmdLEDGet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40014 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40015 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_15 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40016 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_5_1 ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40017 \ram2e_ufm/CmdLEDSet_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40016 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40017 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_16 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40018 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40019 \ram2e_ufm/CmdRWMaskSet_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40018 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40019 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_17 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, - Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40020 \ram2e_ufm/CmdRWMaskSet_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40021 \ram2e_ufm/CmdSetRWBankFFLED_4_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40020 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40021 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_18 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40022 \ram2e_ufm/N_369_i ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40023 \ram2e_ufm/N_368_i ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \CmdTout[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40022 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40023 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1122) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_19 ( input C1, A1, C0, A0, M0, LSR, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, M0_dly, CLK_dly, LSR_dly; - - lut40024 \ram2e_ufm/SUM0_i_o2 ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40025 \ram2e_ufm/RA_35_i_i_0_a3_0[1] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre0011 DOEEN( .D0(M0_dly), .D1(VCCI), .SD(GNDI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, M0, 0:0:0, 0:0:0,,,, CLK_dly, M0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40024 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40025 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40026 \ram2e_ufm/RA_35_i_i_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40027 \ram2e_ufm/RA_35_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40026 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40027 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFDF5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_21 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40028 \ram2e_ufm/RA_35_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40029 \ram2e_ufm/RA_35_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40028 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40029 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_22 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40030 \ram2e_ufm/RA_35_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40031 \ram2e_ufm/RA_35_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40030 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40031 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40031 \ram2e_ufm/RA_35_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40031 \ram2e_ufm/RA_35_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre \RA[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_24 ( input D1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output - F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40032 \ram2e_ufm/RA_35_0_0[9] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40033 \ram2e_ufm/un2_S_2_i_0_0_o3_RNIHFHN3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \RA[9] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RA[8] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40032 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40033 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_25 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40034 \ram2e_ufm/RA_35_0_0[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut4 \ram2e_ufm/RA_35_2_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RA[11] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \RA[10] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40034 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_26 ( input D1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40035 \ram2e_ufm/RC_3_0_0[2] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40036 \ram2e_ufm/RC_3_0_0[1] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - vmuxregsre \RC[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RC[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40035 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6622) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40036 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3344) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_27 ( input D1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40037 \ram2e_ufm/RWBank_3_0[1] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 \ram2e_ufm/RWBank_3_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40037 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40038 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_28 ( input C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40039 \ram2e_ufm/RWBank_3_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40040 \ram2e_ufm/RWBank_3_0[2] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40039 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40040 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40038 \ram2e_ufm/RWBank_3_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40038 \ram2e_ufm/RWBank_3_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module SLICE_30 ( input D1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40041 \ram2e_ufm/RWBank_3_0[7] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40042 \ram2e_ufm/RWBank_3_0[6] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40041 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40042 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_31 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output - F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40043 \ram2e_ufm/RA_35_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40044 \ram2e_ufm/RWSel_2_0_a3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40043 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40044 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_32 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly; - - lut40045 \ram2e_ufm/Ready3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40046 Ready_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40045 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40046 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40047 \ram2e_ufm/S_r_i_0_o2_0_RNI36E21[1] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40048 \ram2e_ufm/S_s_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40047 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40048 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output - F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; - - lut40049 \ram2e_ufm/S_r_i_0_o2_RNIFNP81_0[2] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40050 \ram2e_ufm/S_r_i_0_o2_RNIFNP81[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \S[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40049 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2322) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40050 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_35 ( input D1, C1, B1, A1, D0, A0, DI0, LSR, CLK, output F0, Q0, - F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40051 \ram2e_ufm/CKE_7_m1_0_0_o2_RNICM8E1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40052 \ram2e_ufm/CKE_7_m1_0_0_o2 ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0011 VOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40051 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40052 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_36 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40053 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40054 \ram2e_ufm/nCAS_s_i_0_a3_RNIO1UQ3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 nCAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40053 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40054 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_37 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40055 \ram2e_ufm/nRAS_s_i_0_a3_5_RNIH7J73_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40056 \ram2e_ufm/nRAS_s_i_0_0_RNI0PC64 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre0004 nRAS( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40055 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40056 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_38 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, - Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly; - - lut40057 \ram2e_ufm/nRAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40058 \ram2e_ufm/nRAS_s_i_0_a3_0_RNIIR094 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre0004 nRWE( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), - .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40057 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40058 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0013) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_39 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40059 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40021 \ram2e_ufm/CmdBitbangMXO2_3_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/CmdBitbangMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40059 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_40 ( input D1, C1, B1, A1, C0, B0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40060 \ram2e_ufm/CmdBitbangMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40061 \ram2e_ufm/CmdExecMXO2_3_0_a3 ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/CmdExecMXO2 ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40060 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40061 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_41 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40062 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0_0 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40063 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/CmdSetRWBankFFChip ( .D0(VCCI), .D1(DI0_dly), - .SD(VCCI), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40062 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40063 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_42 ( input D1, B1, A1, D0, C0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40064 \ram2e_ufm/SUM1_0_o3_0 ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40065 \ram2e_ufm/LEDEN_RNO ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/LEDEN ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40064 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40065 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFA50) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_43 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40066 \ram2e_ufm/RWMask_RNO[1] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40067 \ram2e_ufm/RWMask_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40066 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7722) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40067 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h50FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_44 ( input D1, B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40066 \ram2e_ufm/RWMask_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40068 \ram2e_ufm/RWMask_RNO[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40068 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h33F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_45 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40066 \ram2e_ufm/RWMask_RNO[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40069 \ram2e_ufm/RWMask_RNO[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40069 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5F0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_46 ( input D1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40070 \ram2e_ufm/RWMask_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40066 \ram2e_ufm/RWMask_RNO[6] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40070 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDD88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40071 \ram2e_ufm/wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40072 \ram2e_ufm/wb_adr_7_i_i[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40071 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40072 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_48 ( input B1, A1, C0, B0, DI1, DI0, CE, CLK, output F0, - Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40073 \ram2e_ufm/wb_adr_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40061 \ram2e_ufm/wb_adr_RNO[2] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40073 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_49 ( input D1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40074 \ram2e_ufm/wb_adr_RNO[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40075 \ram2e_ufm/wb_adr_RNO[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40074 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h88DD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40075 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA0F5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_50 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, - output F0, Q0, F1, Q1 ); - wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40076 \ram2e_ufm/wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40077 \ram2e_ufm/wb_adr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - vmuxregsre \ram2e_ufm/wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40076 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40077 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB1B1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_51 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; - - lut40078 \ram2e_ufm/wb_cyc_stb_RNO_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40079 \ram2e_ufm/wb_cyc_stb_RNO ( .A(A0), .B(GNDI), .C(C0), .D(D0), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_cyc_stb ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40078 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40079 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40080 \ram2e_ufm/wb_dati_7_0_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40081 \ram2e_ufm/wb_dati_7_0_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40080 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40081 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40082 \ram2e_ufm/wb_dati_7_0_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40083 \ram2e_ufm/wb_dati_7_0_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40082 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40083 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40083 \ram2e_ufm/wb_dati_7_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40084 \ram2e_ufm/wb_dati_7_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40084 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, - CLK, output F0, Q0, F1, Q1 ); - wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; - - lut40085 \ram2e_ufm/wb_dati_7_0_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40086 \ram2e_ufm/wb_dati_7_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - vmuxregsre \ram2e_ufm/wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre \ram2e_ufm/wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - (CLK => Q1) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40085 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40086 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_56 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, - CLK, output F0, Q0, F1 ); - wire VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; - - lut40084 \ram2e_ufm/wb_reqc_1_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40087 \ram2e_ufm/wb_req_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre0011 \ram2e_ufm/wb_req ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40087 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h070F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_57 ( input D1, C1, B1, A1, D0, B0, DI0, LSR, CLK, - output F0, Q0, F1 ); - wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; - - lut40088 \ram2e_ufm/Ready3_0_a3_4 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40089 \ram2e_ufm/wb_rst8_0_a3_0_a3 ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - vmuxregsre0011 \ram2e_ufm/wb_rst ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(VCCI), .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge LSR, 0:0:0); - $width (negedge LSR, 0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40088 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40089 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, - output F0, Q0, F1 ); - wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; - - lut40090 \ram2e_ufm/wb_we_RNO_2 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40091 \ram2e_ufm/wb_we_RNO ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - vmuxregsre \ram2e_ufm/wb_we ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), - .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - (CLK => Q0) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module lut40090 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40091 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCCEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SUM0_i_m3_0_SLICE_59 ( input D1, B1, A1, D0, B0, A0, M0, - output OFX0 ); - wire GNDI, - \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 , - \ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ; - - lut40092 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1 ( .A(A1), .B(B1), .C(GNDI), - .D(D1), - .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40093 \ram2e_ufm/SUM0_i_m3_0/GATE ( .A(A0), .B(B0), .C(GNDI), .D(D0), - .Z(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 )); - selmux2 \ram2e_ufm/SUM0_i_m3_0/SLICE_59_K0K1MUX ( - .D0(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/GATE_H0 ), - .D1(\ram2e_ufm/SUM0_i_m3_0/SLICE_59/ram2e_ufm/SUM0_i_m3_0/SLICE_59_K1_H1 ), - .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40092 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF77) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40093 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module selmux2 ( input D0, D1, SD, output Z ); - - MUX21 INST1( .D0(D0), .D1(D1), .SD(SD), .Z(Z)); -endmodule - -module ram2e_ufm_un1_CS_0_sqmuxa_0_0_0_SLICE_60 ( input D1, C1, B1, A1, C0, B0, - A0, M0, output OFX0 ); - wire - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 - , GNDI, - \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 - ; - - lut40094 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1 ( .A(A1), .B(B1), - .C(C1), .D(D1), - .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 ) - ); - lut40095 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE ( .A(A0), .B(B0), .C(C0), - .D(GNDI), - .Z(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 ) - ); - gnd DRIVEGND( .PWR0(GNDI)); - selmux2 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K0K1MUX ( - .D0(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/GATE_H0 ) - , - .D1(\ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60/ram2e_ufm/un1_CS_0_sqmuxa_0_0_0/SLICE_60_K1_H1 ) - , .SD(M0), .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (B1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (C0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40094 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3B33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40095 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_CKE_7_SLICE_61 ( input D1, C1, A1, D0, B0, A0, M0, output - OFX0 ); - wire GNDI, \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 , - \ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ; - - lut40096 \ram2e_ufm/CKE_7/SLICE_61_K1 ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 )); - gnd DRIVEGND( .PWR0(GNDI)); - lut40097 \ram2e_ufm/CKE_7/GATE ( .A(A0), .B(B0), .C(GNDI), .D(D0), - .Z(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 )); - selmux2 \ram2e_ufm/CKE_7/SLICE_61_K0K1MUX ( - .D0(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/GATE_H0 ), - .D1(\ram2e_ufm/CKE_7/SLICE_61/ram2e_ufm/CKE_7/SLICE_61_K1_H1 ), .SD(M0), - .Z(OFX0)); - - specify - (D1 => OFX0) = (0:0:0,0:0:0); - (C1 => OFX0) = (0:0:0,0:0:0); - (A1 => OFX0) = (0:0:0,0:0:0); - (D0 => OFX0) = (0:0:0,0:0:0); - (B0 => OFX0) = (0:0:0,0:0:0); - (A0 => OFX0) = (0:0:0,0:0:0); - (M0 => OFX0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40096 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h50FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40097 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40098 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIAJ811 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40099 \ram2e_ufm/CmdExecMXO2_3_0_a3_0_RNIPG3P2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40098 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40099 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF10) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_63 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40100 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIA0N95 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40101 \ram2e_ufm/S_r_i_0_o2_RNI3VQTC[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40100 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40101 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40102 \ram2e_ufm/wb_adr_7_i_i_a3_6[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40103 \ram2e_ufm/wb_adr_7_i_i_5[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40102 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40103 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_65 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40104 \ram2e_ufm/SUM0_i_a3_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40100 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNIN3AF2 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40104 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h002A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_66 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40105 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_0[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40106 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0[0] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40105 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40106 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hBBBA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_67 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40107 \ram2e_ufm/nRAS_s_i_0_m3 ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40108 \ram2e_ufm/nRAS_s_i_0_o2_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40107 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40108 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFBFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40109 \ram2e_ufm/wb_adr_7_i_i_3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40110 \ram2e_ufm/wb_adr_7_i_i_3_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40109 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40110 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h01A1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40111 \ram2e_ufm/nCAS_s_i_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40112 \ram2e_ufm/wb_rst16_i_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40111 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40112 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_70 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40113 \ram2e_ufm/wb_dati_7_0_0_a3_12[7] ( .A(A1), .B(B1), .C(GNDI), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40114 \ram2e_ufm/wb_dati_7_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40113 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40114 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h80A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_71 ( input D1, C1, A1, D0, C0, A0, output F0, F1 ); - wire GNDI; - - lut40115 \ram2e_ufm/RA_35_0_0_a3_4[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40116 \ram2e_ufm/nRAS_s_i_0_a3_4 ( .A(A0), .B(GNDI), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40115 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40116 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0005) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_72 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40117 \ram2e_ufm/BA_4[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40118 \ram2e_ufm/un1_RC12_i_0_o3 ( .A(A0), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40117 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40118 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40119 \ram2e_ufm/wb_dati_7_0_0_o3_0[2] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40120 \ram2e_ufm/wb_dati_7_0_0_a3_3[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40119 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40120 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_74 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40121 \ram2e_ufm/RA_35_2_0_0[10] ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40122 \ram2e_ufm/RA_35_2_0_a3_5[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40121 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40122 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_75 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40123 \ram2e_ufm/wb_dati_7_0_0_a3_15[7] ( .A(A1), .B(B1), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40124 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0_RNO[0] ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40123 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40124 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40125 \ram2e_ufm/wb_dati_7_0_0_a3_13[7] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40126 \ram2e_ufm/wb_dati_7_0_0_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40125 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40126 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_77 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40127 \ram2e_ufm/SUM2_0_o2 ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40128 \ram2e_ufm/N_314_i_i_o3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40127 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF3FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40128 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_78 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40129 \ram2e_ufm/S_r_i_0_o2[1] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40130 \ram2e_ufm/S_r_i_0_o2_RNIP4KI1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40129 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40130 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_79 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40131 \ram2e_ufm/un1_LEDEN_0_sqmuxa_1_i_0_0[0] ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40132 \ram2e_ufm/S_r_i_0_o2_RNIOGTF1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40131 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8F88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40132 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hDFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_80 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40133 \ram2e_ufm/un1_wb_cyc_stb_0_sqmuxa_1_i_0_0_a2[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40134 \ram2e_ufm/CmdBitbangMXO2_RNINSM62 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40133 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40134 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF4F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40135 \ram2e_ufm/wb_dati_7_0_0_a3_14[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40136 \ram2e_ufm/wb_dati_7_0_0_a3_13_RNI81UL[7] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40135 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40136 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40137 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40051 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_0_RNIVQNQ2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40137 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_83 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40138 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0 ( .A(GNDI), .B(B1), .C(C1), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40139 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_1_0_RNIS35S ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40138 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40139 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40140 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNIJT9D1 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40141 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_9_RNI3N8T5 ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40140 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40141 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5510) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40142 \ram2e_ufm/wb_dati_7_0_0_a3_10[7] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40143 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_0[0] ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40142 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40143 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_86 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40025 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_1 ( .A(A1), .B(GNDI), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40144 \ram2e_ufm/wb_adr_7_i_i_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40144 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40145 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3_RNIGCV91 ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40146 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_m3 ( .A(A0), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40145 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40146 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hB1B1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40147 \ram2e_ufm/wb_dati_7_0_0_a3_4_1_0[7] ( .A(A1), .B(B1), .C(GNDI), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40148 \ram2e_ufm/wb_dati_7_0_0_RNO_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40147 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40148 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAA80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_89 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40149 \ram2e_ufm/wb_dati_7_0_0_a3_7[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40081 \ram2e_ufm/wb_dati_7_0_0_0_0[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40149 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_90 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40150 \ram2e_ufm/wb_dati_7_0_0_a3_1_0[6] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40151 \ram2e_ufm/wb_dati_7_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40150 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0401) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40151 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40152 \ram2e_ufm/nRAS_s_i_0_a3_8 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40153 \ram2e_ufm/nRAS_s_i_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40152 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40153 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40154 \ram2e_ufm/CKE_7s2_0_0_o3 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40155 \ram2e_ufm/nCAS_s_i_0_a3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40154 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4E0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40155 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_93 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40156 \ram2e_ufm/wb_dati_7_0_0_o2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40016 \ram2e_ufm/wb_dati_7_0_0_a3[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40156 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h6888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_94 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40157 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3 ( .A(GNDI), .B(GNDI), .C(C1), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40158 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_2_2 ( .A(A0), .B(B0), .C(C0), - .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40157 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF0FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40158 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40159 \ram2e_ufm/RA_35_0_0_o2[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40160 \ram2e_ufm/RA_35_0_0_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40159 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFCC8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40160 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_96 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40161 \ram2e_ufm/RA_35_0_0_o2_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40162 \ram2e_ufm/RA_35_0_0_0_0[6] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40161 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0326) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40162 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_97 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40163 \ram2e_ufm/wb_dati_7_0_0_a3_0_0[1] ( .A(A1), .B(GNDI), .C(C1), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40151 \ram2e_ufm/wb_dati_7_0_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40163 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_98 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40164 \ram2e_ufm/wb_dati_7_0_0_a3_9[7] ( .A(GNDI), .B(GNDI), .C(C1), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40165 \ram2e_ufm/wb_dati_7_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40164 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40165 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_99 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40166 \ram2e_ufm/wb_adr_7_i_i_a3_2_0[0] ( .A(A1), .B(B1), .C(GNDI), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40167 \ram2e_ufm/wb_adr_7_i_i_1[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40166 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40167 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_100 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40168 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40169 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o3_0_RNI9H8R ( .A(A0), .B(B0), - .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40168 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40169 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF7B3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_101 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40170 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_o3 ( .A(GNDI), .B(B1), - .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40171 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_o2 ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40170 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40171 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h88B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_102 ( input D1, C1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40172 \ram2e_ufm/CKE_7s2_0_0_a2_1 ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40173 \ram2e_ufm/CKE_7s2_0_0 ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40172 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40173 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_103 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40174 \ram2e_ufm/wb_dati_7_0_0_0_o2[7] ( .A(A1), .B(GNDI), .C(GNDI), - .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40175 \ram2e_ufm/wb_adr_RNO_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40174 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40175 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0C88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_104 ( input D1, C1, B1, A1, C0, B0, output F0, F1 ); - wire GNDI; - - lut40176 \ram2e_ufm/wb_dati_7_0_0_o2_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40177 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[3] ( .A(GNDI), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40176 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h28A4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40177 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40178 \ram2e_ufm/S_r_i_0_o2_RNI62C53[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40179 \ram2e_ufm/N_285_i ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40178 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40179 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_106 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40180 \ram2e_ufm/S_r_i_0_o2[2] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40181 \ram2e_ufm/RA_35_2_0_a3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40180 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5F5F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40181 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8C0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_107 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40182 \ram2e_ufm/CKE_7_m1_0_0_o2_RNIGC501 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40183 \ram2e_ufm/RA_35_i_i_0_a3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40182 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40183 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_108 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40184 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3[0] ( .A(A1), .B(B1), - .C(C1), .D(D1), .Z(F1)); - lut40185 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_a3_0_0[0] ( .A(GNDI), - .B(B0), .C(C0), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40184 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40185 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0F03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_109 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40186 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_6 ( .A(A1), .B(GNDI), .C(C1), - .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40187 \ram2e_ufm/wb_we_RNO_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40186 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40187 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_110 ( input D1, C1, B1, A1, D0, C0, output F0, F1 ); - wire GNDI; - - lut40188 \ram2e_ufm/wb_we_7_iv_0_0_0_a3_7 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40189 \ram2e_ufm/un1_RWMask_0_sqmuxa_1_i_0_a3_0_0[0] ( .A(GNDI), .B(GNDI), - .C(C0), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40188 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40189 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_111 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40190 \ram2e_ufm/wb_dati_7_0_0_a3_2[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40191 \ram2e_ufm/wb_dati_7_0_0_0_o2[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40190 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40191 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8380) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_112 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40192 \ram2e_ufm/nRAS_s_i_0_a3_6 ( .A(A1), .B(B1), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40193 \ram2e_ufm/nRAS_s_i_0_a3_1 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40192 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40193 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_113 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40194 \ram2e_ufm/nRAS_s_i_0_a3_5 ( .A(A1), .B(B1), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40195 \ram2e_ufm/RA_35_2_0_a3_3[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40194 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40195 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_114 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40196 \ram2e_ufm/wb_adr_RNO_2[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40197 \ram2e_ufm/wb_adr_RNO_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40196 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8787) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40197 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_115 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40198 \ram2e_ufm/un2_S_2_i_0_0_o3 ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40199 \ram2e_ufm/CKE_7s2_0_0_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40198 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40199 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5700) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_116 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40200 \ram2e_ufm/CmdExecMXO2_3_0_a3_0 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40201 \ram2e_ufm/CmdSetRWBankFFChip_3_0_a8_0_a3_0 ( .A(A0), .B(B0), - .C(C0), .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40200 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40201 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_117 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40202 \ram2e_ufm/S_s_0_0_RNO[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40203 \ram2e_ufm/N_225_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40202 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5554) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40203 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_118 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40204 \ram2e_ufm/CKE_7_m1_0_0_o2_RNI7FOA1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40205 \ram2e_ufm/N_201_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40204 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40205 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h000D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_119 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40206 \ram2e_ufm/S_r_i_0_o2_RNIBAU51[1] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40207 \ram2e_ufm/un1_CKE75_0_i_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40206 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40207 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hE36F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_120 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40208 \ram2e_ufm/DQMH_4_iv_0_0_i_i_a3_0_a3 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40209 \ram2e_ufm/N_507_i ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40208 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40209 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_121 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40210 \ram2e_ufm/Vout3_0_a3_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40211 \ram2e_ufm/RA_35_0_0_o2[11] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40210 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40211 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFFE0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_122 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40212 \ram2e_ufm/nRWE_s_i_0_63_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40213 \ram2e_ufm/nCAS_s_i_0_m2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40212 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h75FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40213 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5F6E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_123 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40214 \ram2e_ufm/wb_adr_RNO_3[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40215 \ram2e_ufm/wb_dati_7_0_0_a3_8[3] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40214 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h3FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40215 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_124 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40216 \ram2e_ufm/RA_35_0_0_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40217 \ram2e_ufm/RA_35_0_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40216 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h40CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40217 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_125 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40218 \ram2e_ufm/wb_adr_7_i_i_o2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40219 \ram2e_ufm/wb_dati_7_0_0_a3_2[4] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40218 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5CFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40219 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_126 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40220 \ram2e_ufm/wb_we_RNO_1 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40221 \ram2e_ufm/wb_adr_7_i_i_a3_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40220 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2BAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40221 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_127 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40222 \ram2e_ufm/un9_VOEEN_0_a2_0_a3_0_a3 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40223 \ram2e_ufm/RA_35_2_30_a3_2 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40222 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40223 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_128 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40224 \ram2e_ufm/wb_dati_7_0_0_0_a3_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40225 \ram2e_ufm/wb_adr_RNO_4[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40224 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0880) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40225 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_129 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40226 \ram2e_ufm/BA_4[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40227 \ram2e_ufm/RA_35_2_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40226 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA0A2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40227 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_130 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40228 \ram2e_ufm/N_187_i ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40229 \ram2e_ufm/wb_we_RNO_0 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40228 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h5050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40229 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_131 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40230 \ram2e_ufm/Ready3_0_a3_5 ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40231 \ram2e_ufm/wb_dati_7_0_0_0_a3[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40230 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40231 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_132 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40232 \ram2e_ufm/RA_35_0_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40233 \ram2e_ufm/RA_35_0_0_0_0[7] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40232 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40233 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_133 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40234 \ram2e_ufm/un1_CS_0_sqmuxa_0_0_a3_0_1 ( .A(A1), .B(B1), .C(C1), - .D(D1), .Z(F1)); - lut40127 \ram2e_ufm/SUM0_i_o2_2 ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40234 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_134 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40184 \ram2e_ufm/un1_CmdSetRWBankFFChip13_1_i_0_0_o3_3[0] ( .A(A1), - .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40235 \ram2e_ufm/RA_35_0_0_a3[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40235 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_135 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40236 \ram2e_ufm/S_r_i_0_o2_0[1] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40237 \ram2e_ufm/RA_35_2_0_a3_0[10] ( .A(A0), .B(B0), .C(C0), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40236 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40237 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_136 ( input D1, C1, B1, C0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40238 \ram2e_ufm/nRAS_s_i_0_o2 ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40239 \ram2e_ufm/un1_nDOE_i ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40238 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h0F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40239 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_137 ( input D1, C1, A1, D0, C0, A0, output F0, F1 ); - wire GNDI; - - lut40240 \ram2e_ufm/RDOE_i ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40241 \ram2e_ufm/LEDEN_RNI6G6M ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40240 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAAA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40241 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hF5FF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_138 ( input C1, B1, A1, D0, C0, B0, output F0, F1 ); - wire GNDI; - - lut40242 VOEEN_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40243 DOEEN_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40242 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h1313) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40243 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h003F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module SLICE_139 ( input C1, A1, D0, B0, A0, output F0, F1 ); - wire GNDI; - - lut40244 nVOE_pad_RNO( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40245 S_1( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40244 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hAFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40245 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h2200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_140 ( input C1, A1, D0, C0, output F0, F1 ); - wire GNDI; - - lut40025 \ram2e_ufm/RA_35_0_0_a3_0[2] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40189 \ram2e_ufm/RA_35_0_0_a3[5] ( .A(GNDI), .B(GNDI), .C(C0), .D(D0), - .Z(F0)); - - specify - (C1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_141 ( input D1, C1, D0, B0, output F0, F1 ); - wire GNDI; - - lut40189 \ram2e_ufm/RDout_i_0_i_a3[0] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40246 \ram2e_ufm/N_263_i ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40246 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_142 ( input D1, C1, B1, D0, B0, output F0, F1 ); - wire GNDI; - - lut40247 \ram2e_ufm/CmdLEDGet_3_0_a3_1 ( .A(GNDI), .B(B1), .C(C1), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40248 \ram2e_ufm/RDout_i_i_a3[4] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40247 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40248 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_143 ( input D1, B1, D0, B0, output F0, F1 ); - wire GNDI; - - lut40248 \ram2e_ufm/RDout_i_0_i_a3[1] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40248 \ram2e_ufm/RDout_i_0_i_a3[7] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_144 ( input B1, A1, D0, B0, output F0, F1 ); - wire GNDI; - - lut40073 \ram2e_ufm/RDout_i_0_i_a3[2] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), - .Z(F1)); - gnd DRIVEGND( .PWR0(GNDI)); - lut40248 \ram2e_ufm/RDout_i_0_i_a3[6] ( .A(GNDI), .B(B0), .C(GNDI), .D(D0), - .Z(F0)); - - specify - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module ram2e_ufm_SLICE_145 ( input D1, C1, B1, A1, C0, B0, output F0, F1 ); - wire GNDI; - - lut40249 \ram2e_ufm/wb_dati_7_0_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40250 \ram2e_ufm/wb_dati_7_0_0_o2_0[7] ( .A(GNDI), .B(B0), .C(C0), - .D(GNDI), .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40249 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module lut40250 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hCFCF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_146 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, - F1 ); - - lut40251 \ram2e_ufm/RA_35_0_0_0[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); - lut40188 \ram2e_ufm/Ready3_0_a3_3 ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (D0 => F0) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - (A0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40251 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hA0EC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module ram2e_ufm_SLICE_147 ( input D1, C1, B1, A1, C0, B0, output F0, F1 ); - wire GNDI; - - lut40252 \ram2e_ufm/RWBank_3_0_0_o3[0] ( .A(A1), .B(B1), .C(C1), .D(D1), - .Z(F1)); - lut40061 \ram2e_ufm/RDout_i_0_i_a3[5] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), - .Z(F0)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (D1 => F1) = (0:0:0,0:0:0); - (C1 => F1) = (0:0:0,0:0:0); - (B1 => F1) = (0:0:0,0:0:0); - (A1 => F1) = (0:0:0,0:0:0); - (C0 => F0) = (0:0:0,0:0:0); - (B0 => F0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module lut40252 ( input A, B, C, D, output Z ); - - ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); -endmodule - -module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); - - xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); - - specify - (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD0) = (0:0:0,0:0:0); - (RD0 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD0, 0:0:0); - $width (negedge RD0, 0:0:0); - endspecify - -endmodule - -module xo2iobuf ( input I, T, output Z, PAD, input PADI ); - - IB INST1( .I(PADI), .O(Z)); - OBW INST2( .I(I), .T(T), .O(PAD)); -endmodule - -module LED ( input PADDO, output LED ); - - xo2iobuf0253 LED_pad( .I(PADDO), .PAD(LED)); - - specify - (PADDO => LED) = (0:0:0,0:0:0); - endspecify - -endmodule - -module xo2iobuf0253 ( input I, output PAD ); - - OB INST5( .I(I), .O(PAD)); -endmodule - -module C14M ( output PADDI, input C14M ); - - xo2iobuf0254 C14M_pad( .Z(PADDI), .PAD(C14M)); - - specify - (C14M => PADDI) = (0:0:0,0:0:0); - $width (posedge C14M, 0:0:0); - $width (negedge C14M, 0:0:0); - endspecify - -endmodule - -module xo2iobuf0254 ( output Z, input PAD ); - - IB INST1( .I(PAD), .O(Z)); -endmodule - -module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); - - xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7)); - - specify - (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD7) = (0:0:0,0:0:0); - (RD7 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD7, 0:0:0); - $width (negedge RD7, 0:0:0); - endspecify - -endmodule - -module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); - - xo2iobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6)); - - specify - (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD6) = (0:0:0,0:0:0); - (RD6 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD6, 0:0:0); - $width (negedge RD6, 0:0:0); - endspecify - -endmodule - -module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); - - xo2iobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5)); - - specify - (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD5) = (0:0:0,0:0:0); - (RD5 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD5, 0:0:0); - $width (negedge RD5, 0:0:0); - endspecify - -endmodule - -module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); - - xo2iobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4)); - - specify - (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD4) = (0:0:0,0:0:0); - (RD4 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD4, 0:0:0); - $width (negedge RD4, 0:0:0); - endspecify - -endmodule - -module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); - - xo2iobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3)); - - specify - (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD3) = (0:0:0,0:0:0); - (RD3 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD3, 0:0:0); - $width (negedge RD3, 0:0:0); - endspecify - -endmodule - -module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); - - xo2iobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2)); - - specify - (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD2) = (0:0:0,0:0:0); - (RD2 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD2, 0:0:0); - $width (negedge RD2, 0:0:0); - endspecify - -endmodule - -module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); - - xo2iobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1)); - - specify - (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); - (PADDO => RD1) = (0:0:0,0:0:0); - (RD1 => PADDI) = (0:0:0,0:0:0); - $width (posedge RD1, 0:0:0); - $width (negedge RD1, 0:0:0); - endspecify - -endmodule - -module DQMH ( input IOLDO, output DQMH ); - - xo2iobuf0253 DQMH_pad( .I(IOLDO), .PAD(DQMH)); - - specify - (IOLDO => DQMH) = (0:0:0,0:0:0); - endspecify - -endmodule - -module DQMH_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre DQMH_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module mfflsre ( input D0, SP, CK, LSR, output Q ); - - FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module DQML ( input IOLDO, output DQML ); - - xo2iobuf0253 DQML_pad( .I(IOLDO), .PAD(DQML)); - - specify - (IOLDO => DQML) = (0:0:0,0:0:0); - endspecify - -endmodule - -module DQML_MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre DQML_0io( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), - .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module RAout_11_ ( input IOLDO, output RAout11 ); - - xo2iobuf0253 \RAout_pad[11] ( .I(IOLDO), .PAD(RAout11)); - - specify - (IOLDO => RAout11) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_11__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module mfflsre0255 ( input D0, SP, CK, LSR, output Q ); - - FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module inverter ( input I, output Z ); - - INV INST1( .A(I), .Z(Z)); -endmodule - -module RAout_10_ ( input IOLDO, output RAout10 ); - - xo2iobuf0253 \RAout_pad[10] ( .I(IOLDO), .PAD(RAout10)); - - specify - (IOLDO => RAout10) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_10__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_9_ ( input IOLDO, output RAout9 ); - - xo2iobuf0253 \RAout_pad[9] ( .I(IOLDO), .PAD(RAout9)); - - specify - (IOLDO => RAout9) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_9__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_8_ ( input IOLDO, output RAout8 ); - - xo2iobuf0253 \RAout_pad[8] ( .I(IOLDO), .PAD(RAout8)); - - specify - (IOLDO => RAout8) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_8__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_7_ ( input IOLDO, output RAout7 ); - - xo2iobuf0253 \RAout_pad[7] ( .I(IOLDO), .PAD(RAout7)); - - specify - (IOLDO => RAout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_7__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[7] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_6_ ( input IOLDO, output RAout6 ); - - xo2iobuf0253 \RAout_pad[6] ( .I(IOLDO), .PAD(RAout6)); - - specify - (IOLDO => RAout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_6__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[6] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_5_ ( input IOLDO, output RAout5 ); - - xo2iobuf0253 \RAout_pad[5] ( .I(IOLDO), .PAD(RAout5)); - - specify - (IOLDO => RAout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_5__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[5] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_4_ ( input IOLDO, output RAout4 ); - - xo2iobuf0253 \RAout_pad[4] ( .I(IOLDO), .PAD(RAout4)); - - specify - (IOLDO => RAout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_4__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[4] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_3_ ( input IOLDO, output RAout3 ); - - xo2iobuf0253 \RAout_pad[3] ( .I(IOLDO), .PAD(RAout3)); - - specify - (IOLDO => RAout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_3__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[3] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_2_ ( input IOLDO, output RAout2 ); - - xo2iobuf0253 \RAout_pad[2] ( .I(IOLDO), .PAD(RAout2)); - - specify - (IOLDO => RAout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_2__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[2] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_1_ ( input IOLDO, output RAout1 ); - - xo2iobuf0253 \RAout_pad[1] ( .I(IOLDO), .PAD(RAout1)); - - specify - (IOLDO => RAout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_1__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module RAout_0_ ( input IOLDO, output RAout0 ); - - xo2iobuf0253 \RAout_pad[0] ( .I(IOLDO), .PAD(RAout0)); - - specify - (IOLDO => RAout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module RAout_0__MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 \RAout_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), - .LSR(GNDI), .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module BA_1_ ( input IOLDO, output BA1 ); - - xo2iobuf0253 \BA_pad[1] ( .I(IOLDO), .PAD(BA1)); - - specify - (IOLDO => BA1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module BA_1__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0256 \BA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module mfflsre0256 ( input D0, SP, CK, LSR, output Q ); - - FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module BA_0_ ( input IOLDO, output BA0 ); - - xo2iobuf0253 \BA_pad[0] ( .I(IOLDO), .PAD(BA0)); - - specify - (IOLDO => BA0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module BA_0__MGIOL ( output IOLDO, input OPOS, CE, LSR, CLK ); - wire OPOS_dly, CLK_dly, CE_dly, LSR_dly; - - mfflsre0256 \BA_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(LSR_dly), .Q(IOLDO)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module nRWEout ( input IOLDO, output nRWEout ); - - xo2iobuf0253 nRWEout_pad( .I(IOLDO), .PAD(nRWEout)); - - specify - (IOLDO => nRWEout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRWEout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nRWEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nCASout ( input IOLDO, output nCASout ); - - xo2iobuf0253 nCASout_pad( .I(IOLDO), .PAD(nCASout)); - - specify - (IOLDO => nCASout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nCASout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nCASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nRASout ( input IOLDO, output nRASout ); - - xo2iobuf0253 nRASout_pad( .I(IOLDO), .PAD(nRASout)); - - specify - (IOLDO => nRASout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module nRASout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre nRASout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nCSout ( input PADDO, output nCSout ); - - xo2iobuf0253 nCSout_pad( .I(PADDO), .PAD(nCSout)); - - specify - (PADDO => nCSout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CKEout ( input IOLDO, output CKEout ); - - xo2iobuf0253 CKEout_pad( .I(IOLDO), .PAD(CKEout)); - - specify - (IOLDO => CKEout) = (0:0:0,0:0:0); - endspecify - -endmodule - -module CKEout_MGIOL ( output IOLDO, input OPOS, CLK ); - wire VCCI, CLK_NOTIN, GNDI, OPOS_dly, CLK_dly; - - mfflsre0255 CKEout_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_NOTIN), .LSR(GNDI), - .Q(IOLDO)); - vcc DRIVEVCC( .PWR1(VCCI)); - inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - endspecify - -endmodule - -module nVOE ( input PADDO, output nVOE ); - - xo2iobuf0253 nVOE_pad( .I(PADDO), .PAD(nVOE)); - - specify - (PADDO => nVOE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_7_ ( input IOLDO, output Vout7 ); - - xo2iobuf0253 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7)); - - specify - (IOLDO => Vout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0255 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_6_ ( input IOLDO, output Vout6 ); - - xo2iobuf0253 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6)); - - specify - (IOLDO => Vout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0255 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_5_ ( input IOLDO, output Vout5 ); - - xo2iobuf0253 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5)); - - specify - (IOLDO => Vout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0255 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_4_ ( input IOLDO, output Vout4 ); - - xo2iobuf0253 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4)); - - specify - (IOLDO => Vout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0255 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_3_ ( input IOLDO, output Vout3 ); - - xo2iobuf0253 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3)); - - specify - (IOLDO => Vout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0255 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_2_ ( input IOLDO, output Vout2 ); - - xo2iobuf0253 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2)); - - specify - (IOLDO => Vout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0255 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_1_ ( input IOLDO, output Vout1 ); - - xo2iobuf0253 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1)); - - specify - (IOLDO => Vout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0255 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module Vout_0_ ( input IOLDO, output Vout0 ); - - xo2iobuf0253 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0)); - - specify - (IOLDO => Vout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); - wire GNDI, OPOS_dly, CLK_dly, CE_dly; - - mfflsre0255 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), - .LSR(GNDI), .Q(IOLDO)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IOLDO) = (0:0:0,0:0:0); - $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); - $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module nDOE ( input PADDO, output nDOE ); - - xo2iobuf0253 nDOE_pad( .I(PADDO), .PAD(nDOE)); - - specify - (PADDO => nDOE) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_7_ ( input PADDO, output Dout7 ); - - xo2iobuf0253 \Dout_pad[7] ( .I(PADDO), .PAD(Dout7)); - - specify - (PADDO => Dout7) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_6_ ( input PADDO, output Dout6 ); - - xo2iobuf0253 \Dout_pad[6] ( .I(PADDO), .PAD(Dout6)); - - specify - (PADDO => Dout6) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_5_ ( input PADDO, output Dout5 ); - - xo2iobuf0253 \Dout_pad[5] ( .I(PADDO), .PAD(Dout5)); - - specify - (PADDO => Dout5) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_4_ ( input PADDO, output Dout4 ); - - xo2iobuf0253 \Dout_pad[4] ( .I(PADDO), .PAD(Dout4)); - - specify - (PADDO => Dout4) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_3_ ( input PADDO, output Dout3 ); - - xo2iobuf0253 \Dout_pad[3] ( .I(PADDO), .PAD(Dout3)); - - specify - (PADDO => Dout3) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_2_ ( input PADDO, output Dout2 ); - - xo2iobuf0253 \Dout_pad[2] ( .I(PADDO), .PAD(Dout2)); - - specify - (PADDO => Dout2) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_1_ ( input PADDO, output Dout1 ); - - xo2iobuf0253 \Dout_pad[1] ( .I(PADDO), .PAD(Dout1)); - - specify - (PADDO => Dout1) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Dout_0_ ( input PADDO, output Dout0 ); - - xo2iobuf0253 \Dout_pad[0] ( .I(PADDO), .PAD(Dout0)); - - specify - (PADDO => Dout0) = (0:0:0,0:0:0); - endspecify - -endmodule - -module Din_7_ ( output PADDI, input Din7 ); - - xo2iobuf0254 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); - - specify - (Din7 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din7, 0:0:0); - $width (negedge Din7, 0:0:0); - endspecify - -endmodule - -module Din_6_ ( output PADDI, input Din6 ); - - xo2iobuf0254 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); - - specify - (Din6 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din6, 0:0:0); - $width (negedge Din6, 0:0:0); - endspecify - -endmodule - -module Din_5_ ( output PADDI, input Din5 ); - - xo2iobuf0254 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); - - specify - (Din5 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din5, 0:0:0); - $width (negedge Din5, 0:0:0); - endspecify - -endmodule - -module Din_4_ ( output PADDI, input Din4 ); - - xo2iobuf0254 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); - - specify - (Din4 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din4, 0:0:0); - $width (negedge Din4, 0:0:0); - endspecify - -endmodule - -module Din_3_ ( output PADDI, input Din3 ); - - xo2iobuf0254 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); - - specify - (Din3 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din3, 0:0:0); - $width (negedge Din3, 0:0:0); - endspecify - -endmodule - -module Din_2_ ( output PADDI, input Din2 ); - - xo2iobuf0254 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); - - specify - (Din2 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din2, 0:0:0); - $width (negedge Din2, 0:0:0); - endspecify - -endmodule - -module Din_1_ ( output PADDI, input Din1 ); - - xo2iobuf0254 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); - - specify - (Din1 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din1, 0:0:0); - $width (negedge Din1, 0:0:0); - endspecify - -endmodule - -module Din_0_ ( output PADDI, input Din0 ); - - xo2iobuf0254 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); - - specify - (Din0 => PADDI) = (0:0:0,0:0:0); - $width (posedge Din0, 0:0:0); - $width (negedge Din0, 0:0:0); - endspecify - -endmodule - -module Ain_7_ ( output PADDI, input Ain7 ); - - xo2iobuf0254 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7)); - - specify - (Ain7 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain7, 0:0:0); - $width (negedge Ain7, 0:0:0); - endspecify - -endmodule - -module Ain_6_ ( output PADDI, input Ain6 ); - - xo2iobuf0254 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6)); - - specify - (Ain6 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain6, 0:0:0); - $width (negedge Ain6, 0:0:0); - endspecify - -endmodule - -module Ain_5_ ( output PADDI, input Ain5 ); - - xo2iobuf0254 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5)); - - specify - (Ain5 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain5, 0:0:0); - $width (negedge Ain5, 0:0:0); - endspecify - -endmodule - -module Ain_4_ ( output PADDI, input Ain4 ); - - xo2iobuf0254 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4)); - - specify - (Ain4 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain4, 0:0:0); - $width (negedge Ain4, 0:0:0); - endspecify - -endmodule - -module Ain_3_ ( output PADDI, input Ain3 ); - - xo2iobuf0254 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3)); - - specify - (Ain3 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain3, 0:0:0); - $width (negedge Ain3, 0:0:0); - endspecify - -endmodule - -module Ain_2_ ( output PADDI, input Ain2 ); - - xo2iobuf0254 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2)); - - specify - (Ain2 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain2, 0:0:0); - $width (negedge Ain2, 0:0:0); - endspecify - -endmodule - -module Ain_1_ ( output PADDI, input Ain1 ); - - xo2iobuf0254 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1)); - - specify - (Ain1 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain1, 0:0:0); - $width (negedge Ain1, 0:0:0); - endspecify - -endmodule - -module Ain_0_ ( output PADDI, input Ain0 ); - - xo2iobuf0254 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0)); - - specify - (Ain0 => PADDI) = (0:0:0,0:0:0); - $width (posedge Ain0, 0:0:0); - $width (negedge Ain0, 0:0:0); - endspecify - -endmodule - -module nC07X ( output PADDI, input nC07X ); - - xo2iobuf0254 nC07X_pad( .Z(PADDI), .PAD(nC07X)); - - specify - (nC07X => PADDI) = (0:0:0,0:0:0); - $width (posedge nC07X, 0:0:0); - $width (negedge nC07X, 0:0:0); - endspecify - -endmodule - -module nEN80 ( output PADDI, input nEN80 ); - - xo2iobuf0254 nEN80_pad( .Z(PADDI), .PAD(nEN80)); - - specify - (nEN80 => PADDI) = (0:0:0,0:0:0); - $width (posedge nEN80, 0:0:0); - $width (negedge nEN80, 0:0:0); - endspecify - -endmodule - -module nWE ( output PADDI, input nWE ); - - xo2iobuf0254 nWE_pad( .Z(PADDI), .PAD(nWE)); - - specify - (nWE => PADDI) = (0:0:0,0:0:0); - $width (posedge nWE, 0:0:0); - $width (negedge nWE, 0:0:0); - endspecify - -endmodule - -module PHI1 ( output PADDI, input PHI1 ); - - xo2iobuf0254 PHI1_pad( .Z(PADDI), .PAD(PHI1)); - - specify - (PHI1 => PADDI) = (0:0:0,0:0:0); - $width (posedge PHI1, 0:0:0); - $width (negedge PHI1, 0:0:0); - endspecify - -endmodule - -module PHI1_MGIOL ( input DI, CLK, output IN ); - wire VCCI, GNDI, DI_dly, CLK_dly; - - smuxlregsre PHI1r_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), - .Q(IN)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); - - specify - (CLK => IN) = (0:0:0,0:0:0); - $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); - $width (posedge CLK, 0:0:0); - $width (negedge CLK, 0:0:0); - endspecify - -endmodule - -module smuxlregsre ( input D0, SP, CK, LSR, output Q ); - - IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); - defparam INST01.GSR = "DISABLED"; -endmodule - -module ram2e_ufm_ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, - WBWEI, WBADRI0, WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, - WBADRI7, WBDATI0, WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, - WBDATI7, output WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, - WBDATO6, WBDATO7, WBACKO ); - wire VCCI, GNDI; - - EFB_B \ram2e_ufm/ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), - .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), - .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), - .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), - .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), - .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), - .WBDATO1(WBDATO1), .WBDATO2(WBDATO2), .WBDATO3(WBDATO3), .WBDATO4(WBDATO4), - .WBDATO5(WBDATO5), .WBDATO6(WBDATO6), .WBDATO7(WBDATO7), .WBACKO(WBACKO), - .WBCUFMIRQ(), .UFMSN(VCCI), .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), - .I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), - .I2C2SCLI(GNDI), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), - .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), - .SPISCKEN(), .SPIMISOI(GNDI), .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), - .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), - .SPIMCSN3(), .SPIMCSN4(), .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), - .SPICSNEN(), .SPISCSN(GNDI), .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), - .TCIC(GNDI), .TCINT(), .TCOC(), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), - .PLL1STBO(), .PLLWEO(), .PLLADRO0(), .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), - .PLLADRO4(), .PLLDATO0(), .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), - .PLLDATO4(), .PLLDATO5(), .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), - .PLL0DATI1(GNDI), .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), - .PLL0DATI5(GNDI), .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), - .PLL1DATI0(GNDI), .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), - .PLL1DATI4(GNDI), .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), - .PLL1ACKI(GNDI)); - vcc DRIVEVCC( .PWR1(VCCI)); - gnd DRIVEGND( .PWR0(GNDI)); -endmodule - -module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, - WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, - WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, - WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, - WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output - I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input - I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, - I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, - input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output - SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, - SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, - input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, - PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, - PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, - PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, - PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, - PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI ); - wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, - WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, - WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, - WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, - WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, - PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, - PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, - PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, - PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, - I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, - SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, - UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, - WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, - PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, - PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, - PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, - PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, - I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, - I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, - I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, - SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, - SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, - SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, - CFGWAKE_buf, CFGSTDBY_buf; - - EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), - .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), - .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), - .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), - .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), - .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), - .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), - .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), - .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), - .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), - .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), - .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), - .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), - .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), - .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), - .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), - .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), - .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), - .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), - .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), - .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), - .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), - .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), - .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), - .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), - .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), - .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), - .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), - .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), - .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), - .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), - .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), - .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), - .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), - .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), - .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), - .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), - .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), - .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), - .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), - .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), - .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf)); - defparam INST10.DEV_DENSITY = "640L"; - defparam INST10.EFB_I2C1 = "DISABLED"; - defparam INST10.EFB_I2C2 = "DISABLED"; - defparam INST10.EFB_SPI = "DISABLED"; - defparam INST10.EFB_TC = "DISABLED"; - defparam INST10.EFB_TC_PORTMODE = "WB"; - defparam INST10.EFB_UFM = "ENABLED"; - defparam INST10.EFB_WB_CLK_FREQ = "14.4"; - defparam INST10.GSR = "ENABLED"; - defparam INST10.I2C1_ADDRESSING = "7BIT"; - defparam INST10.I2C1_BUS_PERF = "100kHz"; - defparam INST10.I2C1_CLK_DIVIDER = 1; - defparam INST10.I2C1_GEN_CALL = "DISABLED"; - defparam INST10.I2C1_SLAVE_ADDR = "0b1000001"; - defparam INST10.I2C1_WAKEUP = "DISABLED"; - defparam INST10.I2C2_ADDRESSING = "7BIT"; - defparam INST10.I2C2_BUS_PERF = "100kHz"; - defparam INST10.I2C2_CLK_DIVIDER = 1; - defparam INST10.I2C2_GEN_CALL = "DISABLED"; - defparam INST10.I2C2_SLAVE_ADDR = "0b1000010"; - defparam INST10.I2C2_WAKEUP = "DISABLED"; - defparam INST10.SPI_CLK_DIVIDER = 1; - defparam INST10.SPI_CLK_INV = "DISABLED"; - defparam INST10.SPI_INTR_RXOVR = "DISABLED"; - defparam INST10.SPI_INTR_RXRDY = "DISABLED"; - defparam INST10.SPI_INTR_TXOVR = "DISABLED"; - defparam INST10.SPI_INTR_TXRDY = "DISABLED"; - defparam INST10.SPI_LSB_FIRST = "DISABLED"; - defparam INST10.SPI_MODE = "MASTER"; - defparam INST10.SPI_PHASE_ADJ = "DISABLED"; - defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED"; - defparam INST10.SPI_WAKEUP = "DISABLED"; - defparam INST10.TC_CCLK_SEL = 1; - defparam INST10.TC_ICAPTURE = "DISABLED"; - defparam INST10.TC_ICR_INT = "OFF"; - defparam INST10.TC_MODE = "CTCM"; - defparam INST10.TC_OCR_INT = "OFF"; - defparam INST10.TC_OCR_SET = 32767; - defparam INST10.TC_OC_MODE = "TOGGLE"; - defparam INST10.TC_OVERFLOW = "DISABLED"; - defparam INST10.TC_OV_INT = "OFF"; - defparam INST10.TC_RESETN = "ENABLED"; - defparam INST10.TC_SCLK_SEL = "PCLOCK"; - defparam INST10.TC_TOP_SEL = "OFF"; - defparam INST10.TC_TOP_SET = 65535; - defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED"; - defparam INST10.UFM_INIT_FILE_FORMAT = "HEX"; - defparam INST10.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem"; - defparam INST10.UFM_INIT_PAGES = 1; - defparam INST10.UFM_INIT_START_PAGE = 190; - EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), - .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), - .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), - .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), - .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), - .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), - .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), - .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), - .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), - .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), - .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), - .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), - .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), - .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), - .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), - .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), - .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), - .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), - .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), - .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), - .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), - .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), - .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), - .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), - .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), - .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), - .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), - .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), - .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), - .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), - .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), - .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), - .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), - .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), - .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), - .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), - .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), - .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), - .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), - .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), - .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), - .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), - .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), - .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), - .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), - .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), - .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), - .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), - .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), - .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), - .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), - .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), - .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), - .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), - .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), - .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), - .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), - .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), - .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), - .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), - .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), - .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), - .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), - .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), - .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), - .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), - .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), - .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), - .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), - .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), - .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), - .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), - .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), - .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), - .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), - .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), - .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), - .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), - .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), - .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), - .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), - .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), - .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), - .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), - .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), - .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), - .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), - .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), - .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), - .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), - .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), - .CFGSTDBYin(CFGSTDBY_buf)); -endmodule - -module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, - output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, - output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output - WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output - WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output - WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output - WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output - WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output - WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output - WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output - WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output - PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, - output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input - PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, - input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output - PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, - output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input - PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, - input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output - PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, - output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input - I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, - input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, - input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, - input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, - input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input - TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input - WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input - WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input - WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input - WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input - WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input - PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, - input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, - input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, - input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, - input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, - input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, - input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, - input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, - input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output - I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, - output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input - I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, - input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output - I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, - output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, - output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input - SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, - input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output - SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, - output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, - output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, - output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, - output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, - output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, - output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin ); - wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, - WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, - WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, - WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, - WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly; - - BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout)); - BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout)); - BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout)); - BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout)); - BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout)); - BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out)); - BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out)); - BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out)); - BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out)); - BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out)); - BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out)); - BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out)); - BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out)); - BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out)); - BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out)); - BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out)); - BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out)); - BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out)); - BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out)); - BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out)); - BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out)); - BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out)); - BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out)); - BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out)); - BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out)); - BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out)); - BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out)); - BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out)); - BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out)); - BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout)); - BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out)); - BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out)); - BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out)); - BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out)); - BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out)); - BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out)); - BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out)); - BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out)); - BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout)); - BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout)); - BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout)); - BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout)); - BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout)); - BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout)); - BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout)); - BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout)); - BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout)); - BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout)); - BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout)); - BUFBA TCIC_buf( .A(TCICin), .Z(TCICout)); - BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout)); - BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out)); - BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out)); - BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out)); - BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out)); - BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out)); - BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out)); - BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out)); - BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out)); - BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout)); - BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout)); - BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout)); - BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout)); - BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout)); - BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout)); - BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out)); - BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out)); - BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out)); - BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out)); - BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out)); - BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out)); - BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out)); - BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out)); - BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out)); - BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out)); - BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out)); - BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out)); - BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out)); - BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout)); - BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout)); - BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout)); - BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout)); - BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout)); - BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout)); - BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout)); - BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout)); - BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout)); - BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout)); - BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout)); - BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout)); - BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout)); - BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout)); - BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout)); - BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout)); - BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out)); - BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out)); - BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out)); - BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out)); - BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out)); - BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out)); - BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out)); - BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out)); - BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout)); - BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout)); - BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout)); - BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout)); - BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout)); - BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout)); - BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout)); - - specify - (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO2out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO3out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO4out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO5out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO6out) = (0:0:0,0:0:0); - (WBCLKIin => WBDATO7out) = (0:0:0,0:0:0); - (WBCLKIin => WBACKOout) = (0:0:0,0:0:0); - $setuphold - (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly); - $setuphold - (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly); - $setuphold - (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly); - $setuphold - (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly); - $setuphold - (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly); - $setuphold - (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly); - $setuphold - (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly); - $setuphold - (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly); - $setuphold - (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly); - $setuphold - (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly); - $setuphold - (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly); - $setuphold - (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly); - $setuphold - (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly); - $setuphold - (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly); - $setuphold - (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly); - $setuphold - (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly); - $setuphold - (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly); - $setuphold - (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly); - $setuphold - (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly); - $setuphold - (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly); - $width (posedge WBCLKIin, 0:0:0); - $width (negedge WBCLKIin, 0:0:0); - endspecify - -endmodule diff --git a/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html deleted file mode 100644 index 1142cd1..0000000 --- a/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html +++ /dev/null @@ -1,16 +0,0 @@ - 
    Setting log file to '//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
-Starting: parse design source files
-(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
-(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/ram2e/CPLD/RAM2E.v'
-(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/ram2e/CPLD/UFM-LCMXO2.v'
-(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/REFB.v'
-INFO - //Mac/iCloud/Repos/ram2e/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E'
-INFO - //Mac/iCloud/Repos/ram2e/CPLD/RAM2E.v(1,1-473,10) (VERI-9000) elaborating module 'RAM2E'
-INFO - //Mac/iCloud/Repos/ram2e/CPLD/UFM-LCMXO2.v(1,1-334,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1'
-INFO - //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
-INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
-INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
-INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
-Done: design load finished with (0) errors, and (0) warnings
-
-
    \ No newline at end of file diff --git a/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior deleted file mode 100644 index 3d035e6..0000000 --- a/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior +++ /dev/null @@ -1,119 +0,0 @@ -Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 5 -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: 6 -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd. -Design name: RAM2E -NCD version: 3.3 -Vendor: LATTICE -Device: LCMXO2-640HC -Package: TQFP100 -Performance: M -Package Status: Final Version 1.39. -Performance Hardware Data Status: Final Version 34.4. -// Design: RAM2E -// Package: TQFP100 -// ncd File: ram2e_lcmxo2_640hc_impl1.ncd -// Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Dec 28 23:23:47 2023 -// M: Minimum Performance Grade -// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml - -I/O Timing Report (All units are in ns) - -Worst Case Results across Performance Grades (M, 6, 5, 4): - -// Input Setup and Hold Times - -Port Clock Edge Setup Performance_Grade Hold Performance_Grade ----------------------------------------------------------------------- -Ain[0] C14M R 2.463 4 -0.066 M -Ain[1] C14M R 1.330 4 0.135 6 -Ain[2] C14M R 1.221 4 0.223 4 -Ain[3] C14M R 2.776 4 -0.165 M -Ain[4] C14M R 1.603 4 0.140 M -Ain[5] C14M R 0.021 6 1.287 4 -Ain[6] C14M R 1.444 4 0.205 M -Ain[7] C14M R 1.816 4 0.114 M -Din[0] C14M R 8.919 4 0.723 4 -Din[1] C14M R 8.410 4 1.156 4 -Din[2] C14M R 8.503 4 1.181 4 -Din[3] C14M R 8.783 4 0.110 M -Din[4] C14M R 10.420 4 1.022 4 -Din[5] C14M R 8.001 4 0.566 4 -Din[6] C14M R 9.731 4 1.050 4 -Din[7] C14M R 10.052 4 0.862 4 -PHI1 C14M R 2.579 4 3.047 4 -RD[0] C14M R 0.267 4 0.866 4 -RD[1] C14M R 0.173 4 0.937 4 -RD[2] C14M R 0.100 4 1.018 4 -RD[3] C14M R 0.267 4 0.866 4 -RD[4] C14M R 0.172 4 0.936 4 -RD[5] C14M R 0.267 4 0.866 4 -RD[6] C14M R 0.766 4 0.420 4 -RD[7] C14M R 0.267 4 0.866 4 -nC07X C14M R 0.998 4 0.405 6 -nEN80 C14M R 6.107 4 0.114 M -nWE C14M R 6.726 4 0.069 M - - -// Clock to Output Delay - -Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------- -BA[0] C14M R 8.629 4 2.885 M -BA[1] C14M R 8.629 4 2.885 M -CKEout C14M F 8.629 4 2.885 M -DQMH C14M R 8.609 4 2.892 M -DQML C14M R 8.609 4 2.892 M -LED C14M R 19.935 4 8.161 M -RAout[0] C14M F 8.695 4 2.890 M -RAout[10] C14M F 8.629 4 2.885 M -RAout[11] C14M F 8.629 4 2.885 M -RAout[1] C14M F 8.695 4 2.890 M -RAout[2] C14M F 8.695 4 2.890 M -RAout[3] C14M F 8.695 4 2.890 M -RAout[4] C14M F 8.695 4 2.890 M -RAout[5] C14M F 8.695 4 2.890 M -RAout[6] C14M F 8.695 4 2.890 M -RAout[7] C14M F 8.695 4 2.890 M -RAout[8] C14M F 8.629 4 2.885 M -RAout[9] C14M F 8.629 4 2.885 M -RD[0] C14M R 11.414 4 3.265 M -RD[1] C14M R 11.811 4 3.265 M -RD[2] C14M R 11.925 4 3.265 M -RD[3] C14M R 11.384 4 3.265 M -RD[4] C14M R 12.301 4 3.371 M -RD[5] C14M R 12.767 4 3.371 M -RD[6] C14M R 12.010 4 3.371 M -RD[7] C14M R 12.313 4 3.371 M -Vout[0] C14M R 9.553 4 3.402 M -Vout[1] C14M R 9.553 4 3.402 M -Vout[2] C14M R 9.553 4 3.402 M -Vout[3] C14M R 9.553 4 3.402 M -Vout[4] C14M R 9.553 4 3.402 M -Vout[5] C14M R 9.553 4 3.402 M -Vout[6] C14M R 9.553 4 3.402 M -Vout[7] C14M R 9.553 4 3.402 M -nCASout C14M F 8.629 4 2.885 M -nDOE C14M R 12.048 4 3.811 M -nRASout C14M F 8.629 4 2.885 M -nRWEout C14M F 8.629 4 2.885 M -nVOE C14M R 12.164 4 3.783 M -WARNING: you must also run trce with hold speed: 4 -WARNING: you must also run trce with setup speed: 6 -WARNING: you must also run trce with hold speed: 6 diff --git a/CPLD/LCMXO2-640HC/msg_file.log b/CPLD/LCMXO2-640HC/msg_file.log deleted file mode 100644 index fe5110d..0000000 --- a/CPLD/LCMXO2-640HC/msg_file.log +++ /dev/null @@ -1,29 +0,0 @@ -SCUBA, Version Diamond (64-bit) 3.12.1.454 -Wed Sep 20 04:17:14 2023 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 - Circuit name : REFB - Module type : efb - Module Version : 1.2 - Ports : - Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] - Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq - I/O buffer : not inserted - EDIF output : REFB.edn - Verilog output : REFB.v - Verilog template : REFB_tmpl.v - Verilog purpose : for synthesis and simulation - Bus notation : big endian - Report output : REFB.srp - Estimated Resource Usage: - -END SCUBA Module Synthesis - diff --git a/CPLD/LCMXO2-640HC/promote.xml b/CPLD/LCMXO2-640HC/promote.xml deleted file mode 100644 index 8bd66e9..0000000 --- a/CPLD/LCMXO2-640HC/promote.xml +++ /dev/null @@ -1,3 +0,0 @@ - - - diff --git a/CPLD/LCMXO2-640HC/reportview.xml b/CPLD/LCMXO2-640HC/reportview.xml deleted file mode 100644 index ed7b29c..0000000 --- a/CPLD/LCMXO2-640HC/reportview.xml +++ /dev/null @@ -1,10 +0,0 @@ - - - - - - - - - -