From 1bbca43cfd320422c24c84570afa354e6ceb1eca Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Thu, 28 Dec 2023 23:24:48 -0500 Subject: [PATCH] RC --- .../RAM2E_LCMXO2_1200HC_tcl.html | 17 ++++ .../impl1/RAM2E_LCMXO2_1200HC_impl1.alt | 2 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1.bgn | 4 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1.bit | Bin 9711 -> 9711 bytes .../impl1/RAM2E_LCMXO2_1200HC_impl1.edi | 2 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1.jed | 4 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1.mrp | 16 ++-- .../impl1/RAM2E_LCMXO2_1200HC_impl1.pad | 4 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1.prf | 2 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1.srr | 87 +++++++++--------- .../impl1/RAM2E_LCMXO2_1200HC_impl1.tw1 | 4 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1.twr | 4 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1_bgn.html | 4 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt | 2 +- .../RAM2E_LCMXO2_1200HC_impl1_iotiming.html | 2 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf | 2 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo | 4 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html | 4 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html | 4 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1_par.html | 48 +++++----- .../impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt | 2 +- .../RAM2E_LCMXO2_1200HC_impl1_summary.html | 2 +- .../RAM2E_LCMXO2_1200HC_impl1_synplify.html | 87 +++++++++--------- .../impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html | 4 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html | 4 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf | 2 +- .../impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo | 4 +- .../impl1/hdla_gen_hierarchy.html | 4 +- .../impl1/ram2e_lcmxo2_1200hc_impl1.ior | 2 +- CPLD/LCMXO2-1200HC/promote.xml | 2 +- .../impl1/RAM2E_LCMXO2_640HC_impl1.alt | 2 +- .../impl1/RAM2E_LCMXO2_640HC_impl1.bgn | 4 +- .../impl1/RAM2E_LCMXO2_640HC_impl1.bit | Bin 6942 -> 6942 bytes .../impl1/RAM2E_LCMXO2_640HC_impl1.edi | 2 +- .../impl1/RAM2E_LCMXO2_640HC_impl1.jed | 4 +- .../impl1/RAM2E_LCMXO2_640HC_impl1.mrp | 14 +-- .../impl1/RAM2E_LCMXO2_640HC_impl1.pad | 4 +- .../impl1/RAM2E_LCMXO2_640HC_impl1.prf | 2 +- .../impl1/RAM2E_LCMXO2_640HC_impl1.srr | 85 ++++++++--------- .../impl1/RAM2E_LCMXO2_640HC_impl1.tw1 | 4 +- .../impl1/RAM2E_LCMXO2_640HC_impl1.twr | 4 +- .../impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html | 2 +- .../impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt | 2 +- .../RAM2E_LCMXO2_640HC_impl1_iotiming.html | 2 +- .../impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf | 2 +- .../impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo | 4 +- .../impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html | 2 +- .../impl1/RAM2E_LCMXO2_640HC_impl1_pad.html | 4 +- .../impl1/RAM2E_LCMXO2_640HC_impl1_par.html | 50 +++++----- .../impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt | 2 +- .../RAM2E_LCMXO2_640HC_impl1_summary.html | 2 +- .../RAM2E_LCMXO2_640HC_impl1_synplify.html | 85 ++++++++--------- .../impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html | 4 +- .../impl1/RAM2E_LCMXO2_640HC_impl1_twr.html | 4 +- .../impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf | 2 +- .../impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo | 4 +- .../impl1/ram2e_lcmxo2_640hc_impl1.ior | 2 +- CPLD/LCMXO2-640HC/promote.xml | 2 +- 58 files changed, 329 insertions(+), 300 deletions(-) diff --git a/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html index be4e2bb..6c1fa4d 100644 --- a/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html +++ b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html @@ -59,6 +59,23 @@ prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200H +pn231228231137 +#Start recording tcl command: 12/26/2023 23:38:54 +#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC +prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf" +prj_run Export -impl impl1 +prj_run Export -impl impl1 +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 -forceAll +prj_run Export -impl impl1 +#Stop recording: 12/28/2023 23:11:37 + + +


diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt index 6a839f5..fbfdb79 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt @@ -1,6 +1,6 @@ NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * NOTE All Rights Reserved * -NOTE DATE CREATED: Thu Dec 28 23:10:34 2023 * +NOTE DATE CREATED: Thu Dec 28 23:24:00 2023 * NOTE DESIGN NAME: RAM2E * NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 * NOTE PIN ASSIGNMENTS * diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn index f295f02..9b2aaa0 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn @@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Dec 28 23:10:30 2023 +Thu Dec 28 23:23:57 2023 Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf @@ -82,5 +82,5 @@ Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510). Initialized UFM Pages: 321 Pages (Page 190 to Page 510). Total CPU Time: 3 secs -Total REAL Time: 4 secs +Total REAL Time: 3 secs Peak Memory Usage: 275 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bit b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bit index 6ed6435046874e1cba51ec42089e1e08797fefe0..01415201d9617c256924fb6256e4dc4f5dc49c59 100644 GIT binary patch delta 16 YcmaFw{oZ@RM^+Design Summary @@ -407,7 +407,7 @@ Instance Name: ram2e_ufm/ufmefb/EFBInst_0 Run Time and Memory Usage ------------------------- - Total CPU Time: 1 secs + Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 64 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html index 226fada..64cc09c 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html @@ -14,7 +14,7 @@ Performance Grade: 4 PACKAGE: TQFP100 Package Status: Final Version 1.44 -Thu Dec 28 23:10:10 2023 +Thu Dec 28 23:23:38 2023 Pinout by Port Name: +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ @@ -318,7 +318,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Dec 28 23:10:13 2023 +Thu Dec 28 23:23:42 2023 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html index 745393f..4309f56 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html @@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Dec 28 23:10:01 2023 +Thu Dec 28 23:23:31 2023 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir @@ -26,17 +26,17 @@ Preference file: RAM2E_LCMXO2_1200HC_impl1.prf. Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 58.069 0 0.342 0 15 Completed +5_1 * 0 58.069 0 0.342 0 13 Completed * : Design saved. -Total (real) run time for 1-seed: 15 secs +Total (real) run time for 1-seed: 13 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "RAM2E_LCMXO2_1200HC_impl1_map.ncd" -Thu Dec 28 23:10:01 2023 +Thu Dec 28 23:23:31 2023 Best Par Run @@ -89,17 +89,17 @@ The following 1 signal is selected to use the secondary clock routing resources: No signal is selected as Global Set/Reset. Starting Placer Phase 0. ........ -Finished Placer Phase 0. REAL time: 3 secs +Finished Placer Phase 0. REAL time: 2 secs Starting Placer Phase 1. .................... Placer score = 82860. -Finished Placer Phase 1. REAL time: 8 secs +Finished Placer Phase 1. REAL time: 7 secs Starting Placer Phase 2. . Placer score = 82610 -Finished Placer Phase 2. REAL time: 9 secs +Finished Placer Phase 2. REAL time: 7 secs @@ -141,7 +141,7 @@ I/O Bank Usage Summary: | 3 | 20 / 20 (100%) | 3.3V | - | +----------+----------------+------------+-----------+ -Total placer CPU time: 7 secs +Total placer CPU time: 6 secs Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd. @@ -149,9 +149,9 @@ Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd. Starting router resource preassignment WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. -Completed router resource preassignment. Real time: 13 secs +Completed router resource preassignment. Real time: 12 secs -Start NBR router at 23:10:14 12/28/23 +Start NBR router at 23:23:43 12/28/23 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) @@ -166,32 +166,32 @@ Note: NBR uses a different method to calculate timing slacks. The your design. ***************************************************************** -Start NBR special constraint process at 23:10:14 12/28/23 +Start NBR special constraint process at 23:23:43 12/28/23 -Start NBR section for initial routing at 23:10:14 12/28/23 +Start NBR section for initial routing at 23:23:43 12/28/23 Level 4, iteration 1 19(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 58.075ns/0.000ns; real time: 14 secs +Estimated worst slack/total negative slack<setup>: 58.075ns/0.000ns; real time: 12 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) -Start NBR section for normal routing at 23:10:15 12/28/23 +Start NBR section for normal routing at 23:23:43 12/28/23 Level 4, iteration 1 3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 14 secs +Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 12 secs Level 4, iteration 2 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 14 secs +Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 12 secs -Start NBR section for setup/hold timing optimization with effort level 3 at 23:10:15 12/28/23 +Start NBR section for setup/hold timing optimization with effort level 3 at 23:23:43 12/28/23 -Start NBR section for re-routing at 23:10:15 12/28/23 +Start NBR section for re-routing at 23:23:43 12/28/23 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 14 secs +Estimated worst slack/total negative slack<setup>: 58.069ns/0.000ns; real time: 12 secs -Start NBR section for post-routing at 23:10:15 12/28/23 +Start NBR section for post-routing at 23:23:43 12/28/23 End NBR router with 0 unrouted connection @@ -206,8 +206,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored -Total CPU time 13 secs -Total REAL time: 15 secs +Total CPU time 12 secs +Total REAL time: 13 secs Completely routed. End of route. 1330 routed (100.00%); 0 unrouted. @@ -229,8 +229,8 @@ PAR_SUMMARY::Worst slack<hold /<ns>> = 0.342 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 -Total CPU time to completion: 14 secs -Total REAL time to completion: 15 secs +Total CPU time to completion: 12 secs +Total REAL time to completion: 13 secs par done! diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt index 400c070..500b722 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt @@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11 Implementation : impl1 -# Written on Thu Dec 28 23:09:48 2023 +# Written on Thu Dec 28 23:23:22 2023 ##### FILES SYNTAX CHECKED ############################################## Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc" diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html index fd74f38..6e0b806 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html @@ -62,7 +62,7 @@ Updated: -2023/12/28 23:10:34 +2023/12/28 23:24:01 Implementation Location: diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html index 1f2c0a9..51a4fa0 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html @@ -12,7 +12,7 @@ #OS: Windows 8 6.2 #Hostname: ZANEMACWIN11 -# Thu Dec 28 23:09:45 2023 +# Thu Dec 28 23:23:19 2023 #Implementation: impl1 @@ -61,6 +61,8 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202 @I::"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v" (library work) @I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work) Verilog syntax check successful! +File \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v changed - recompiling +File \\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v changed - recompiling Selecting top level module RAM2E @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. Running optimization stage 1 on VHI ....... @@ -82,7 +84,7 @@ Running optimization stage 1 on RAM2E ....... Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) Running optimization stage 2 on RAM2E ....... @N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused. -Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) +Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) Running optimization stage 2 on RAM2E_UFM ....... @N: CL159 :"\\Mac\iCloud\Repos\RAM2E\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused. Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) @@ -100,7 +102,7 @@ At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Dec 28 23:09:45 2023 +# Thu Dec 28 23:23:19 2023 ###########################################################] ###########################################################[ @@ -121,13 +123,14 @@ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode +File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Dec 28 23:09:46 2023 +# Thu Dec 28 23:23:20 2023 ###########################################################] @@ -137,12 +140,12 @@ For a summary of runtime and memory usage for all design units, please see file: @END -At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB) +At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Dec 28 23:09:46 2023 +# Thu Dec 28 23:23:20 2023 ###########################################################] ###########################################################[ @@ -165,15 +168,15 @@ Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug @N|Running in 64-bit mode File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling -At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Dec 28 23:09:47 2023 +# Thu Dec 28 23:23:21 2023 ###########################################################] -# Thu Dec 28 23:09:47 2023 +# Thu Dec 28 23:23:21 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -192,10 +195,10 @@ Implementation : impl1 Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) -Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 140MB) +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB) Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc @L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt @@ -243,17 +246,17 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) -Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) -Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) @N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E -Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB) +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) @@ -312,7 +315,7 @@ Finished Pre Mapping Phase. Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) -Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) @@ -322,10 +325,10 @@ Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Dec 28 23:09:49 2023 +# Thu Dec 28 23:23:23 2023 ###########################################################] -# Thu Dec 28 23:09:49 2023 +# Thu Dec 28 23:23:23 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -344,34 +347,34 @@ Implementation : impl1 Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ -Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 127MB peak: 127MB) +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) @N: MF916 |Option synthesis_strategy=base is enabled. @N: MF248 |Running in 64-bit mode. @N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) -Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB) +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) -Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 139MB) +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) -Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB) +Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB) -Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) @N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0] @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. -Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) +Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB) Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) @@ -387,22 +390,22 @@ Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CP Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) -Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB) +Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) -Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB) +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) -Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB) +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB) -Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB) +Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ - 1 0h:00m:02s 33.71ns 284 / 122 + 1 0h:00m:01s 33.71ns 284 / 122 -Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB) +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 211MB peak: 211MB) @N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. @A: BN291 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":163:4:163:9|Boundary register BA_1_.fb (in view: work.RAM2E(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @@ -411,30 +414,30 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB) -Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB) +Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB) Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB) +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) -Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) +Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) -Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB) +Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB) @W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N: MT615 |Found clock C14M with period 69.84ns ##### START OF TIMING REPORT #####[ -# Timing report written on Thu Dec 28 23:09:54 2023 +# Timing report written on Thu Dec 28 23:23:26 2023 # @@ -656,10 +659,10 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In Timing exceptions that could not be applied -Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB) +Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB) -Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB) +Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB) --------------------------------------- Resource Usage Report @@ -694,10 +697,10 @@ VHI: 3 VLO: 3 Mapper successful! -At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 79MB peak: 217MB) +At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 80MB peak: 217MB) -Process took 0h:00m:04s realtime, 0h:00m:04s cputime -# Thu Dec 28 23:09:54 2023 +Process took 0h:00m:03s realtime, 0h:00m:03s cputime +# Thu Dec 28 23:23:26 2023 ###########################################################] diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html index d1f1a08..96c2755 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:09:59 2023 +Thu Dec 28 23:23:29 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -128,7 +128,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:09:59 2023 +Thu Dec 28 23:23:29 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html index 2a571cc..6596462 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:10:17 2023 +Thu Dec 28 23:23:45 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -628,7 +628,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:10:17 2023 +Thu Dec 28 23:23:45 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf index e74d3da..e58d2ec 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf @@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "RAM2E") - (DATE "Thu Dec 28 23:10:25 2023") + (DATE "Thu Dec 28 23:23:53 2023") (VENDOR "Lattice") (PROGRAM "ldbanno") (VERSION "Diamond (64-bit) 3.12.1.454") diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo index 4821083..a280446 100644 --- a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 // ldbanno -n Verilog -o RAM2E_LCMXO2_1200HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd -// Netlist created on Thu Dec 28 23:09:57 2023 -// Netlist written on Thu Dec 28 23:10:24 2023 +// Netlist created on Thu Dec 28 23:23:27 2023 +// Netlist written on Thu Dec 28 23:23:52 2023 // Design is for device LCMXO2-1200HC // Design is for package TQFP100 // Design is for performance grade 4 diff --git a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html index 7c84143..15f7f6d 100644 --- a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html +++ b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html @@ -5,8 +5,8 @@ Starting: parse design source files (VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v' (VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v' INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E' -INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-463,10) (VERI-9000) elaborating module 'RAM2E' -INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-333,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1' +INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.v(1,1-473,10) (VERI-9000) elaborating module 'RAM2E' +INFO - //Mac/iCloud/Repos/RAM2E/CPLD/UFM-LCMXO2.v(1,1-334,10) (VERI-9000) elaborating module 'RAM2E_UFM_uniq_1' INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1' INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1' diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior b/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior index be29cb8..d3d1f69 100644 --- a/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior +++ b/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior @@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 34.4. // Package: TQFP100 // ncd File: ram2e_lcmxo2_1200hc_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Dec 28 23:10:20 2023 +// Written on Thu Dec 28 23:23:48 2023 // M: Minimum Performance Grade // iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml diff --git a/CPLD/LCMXO2-1200HC/promote.xml b/CPLD/LCMXO2-1200HC/promote.xml index b1d2d7e..dfdba36 100644 --- a/CPLD/LCMXO2-1200HC/promote.xml +++ b/CPLD/LCMXO2-1200HC/promote.xml @@ -1,3 +1,3 @@ - + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt index c423c9a..a2966b6 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt @@ -1,6 +1,6 @@ NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * NOTE All Rights Reserved * -NOTE DATE CREATED: Thu Dec 28 23:10:32 2023 * +NOTE DATE CREATED: Thu Dec 28 23:23:58 2023 * NOTE DESIGN NAME: RAM2E * NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 * NOTE PIN ASSIGNMENTS * diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn index d9a4ab2..2878fee 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn @@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Dec 28 23:10:28 2023 +Thu Dec 28 23:23:55 2023 Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf @@ -82,5 +82,5 @@ Available General Purpose Flash Memory: 191 Pages (Page 0 to Page 190). Initialized UFM Pages: 1 Page (Page 190). Total CPU Time: 3 secs -Total REAL Time: 4 secs +Total REAL Time: 3 secs Peak Memory Usage: 267 MB diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bit b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bit index bdb8c2844bf33a48f141e35ff0400dced8e8d91c..ae990d6be4d306792147e74cf06d2219ef55a593 100644 GIT binary patch delta 16 XcmbPdHqUIrdsZW3D^sJ5U$mqEHt7Z& delta 16 XcmbPdHqUIrdsagODDesign Summary diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html index 330925e..8d4838a 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html @@ -14,7 +14,7 @@ Performance Grade: 4 PACKAGE: TQFP100 Package Status: Final Version 1.39 -Thu Dec 28 23:10:10 2023 +Thu Dec 28 23:23:38 2023 Pinout by Port Name: +-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ @@ -290,7 +290,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Dec 28 23:10:13 2023 +Thu Dec 28 23:23:41 2023 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html index e121eb7..b47cccb 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html @@ -12,7 +12,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. -Thu Dec 28 23:10:01 2023 +Thu Dec 28 23:23:31 2023 C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir @@ -26,17 +26,17 @@ Preference file: RAM2E_LCMXO2_640HC_impl1.prf. Level/ Number Worst Timing Worst Timing Run NCD Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status ---------- -------- ----- ------ ----------- ----------- ---- ------ -5_1 * 0 57.938 0 0.379 0 15 Completed +5_1 * 0 57.938 0 0.379 0 13 Completed * : Design saved. -Total (real) run time for 1-seed: 15 secs +Total (real) run time for 1-seed: 13 secs par done! Note: user must run 'Trace' for timing closure signoff. Lattice Place and Route Report for Design "RAM2E_LCMXO2_640HC_impl1_map.ncd" -Thu Dec 28 23:10:01 2023 +Thu Dec 28 23:23:31 2023 Best Par Run @@ -89,17 +89,17 @@ The following 1 signal is selected to use the secondary clock routing resources: No signal is selected as Global Set/Reset. Starting Placer Phase 0. ........... -Finished Placer Phase 0. REAL time: 2 secs +Finished Placer Phase 0. REAL time: 0 secs Starting Placer Phase 1. .................... Placer score = 69810. -Finished Placer Phase 1. REAL time: 9 secs +Finished Placer Phase 1. REAL time: 7 secs Starting Placer Phase 2. . Placer score = 69262 -Finished Placer Phase 2. REAL time: 9 secs +Finished Placer Phase 2. REAL time: 7 secs @@ -137,7 +137,7 @@ I/O Bank Usage Summary: | 3 | 20 / 20 (100%) | 3.3V | - | +----------+----------------+------------+-----------+ -Total placer CPU time: 7 secs +Total placer CPU time: 6 secs Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd. @@ -145,9 +145,9 @@ Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd. Starting router resource preassignment WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew. -Completed router resource preassignment. Real time: 13 secs +Completed router resource preassignment. Real time: 11 secs -Start NBR router at 23:10:14 12/28/23 +Start NBR router at 23:23:42 12/28/23 ***************************************************************** Info: NBR allows conflicts(one node used by more than one signal) @@ -162,35 +162,35 @@ Note: NBR uses a different method to calculate timing slacks. The your design. ***************************************************************** -Start NBR special constraint process at 23:10:14 12/28/23 +Start NBR special constraint process at 23:23:42 12/28/23 -Start NBR section for initial routing at 23:10:14 12/28/23 +Start NBR section for initial routing at 23:23:42 12/28/23 Level 4, iteration 1 19(0.04%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 58.137ns/0.000ns; real time: 13 secs +Estimated worst slack/total negative slack<setup>: 58.137ns/0.000ns; real time: 11 secs Info: Initial congestion level at 75% usage is 0 Info: Initial congestion area at 75% usage is 0 (0.00%) -Start NBR section for normal routing at 23:10:14 12/28/23 +Start NBR section for normal routing at 23:23:42 12/28/23 Level 4, iteration 1 8(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 13 secs +Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 11 secs Level 4, iteration 2 1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 13 secs +Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 11 secs Level 4, iteration 3 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 13 secs +Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 12 secs -Start NBR section for setup/hold timing optimization with effort level 3 at 23:10:14 12/28/23 +Start NBR section for setup/hold timing optimization with effort level 3 at 23:23:43 12/28/23 -Start NBR section for re-routing at 23:10:15 12/28/23 +Start NBR section for re-routing at 23:23:43 12/28/23 Level 4, iteration 1 0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; -Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 14 secs +Estimated worst slack/total negative slack<setup>: 57.938ns/0.000ns; real time: 12 secs -Start NBR section for post-routing at 23:10:15 12/28/23 +Start NBR section for post-routing at 23:23:43 12/28/23 End NBR router with 0 unrouted connection @@ -205,8 +205,8 @@ Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored -Total CPU time 13 secs -Total REAL time: 14 secs +Total CPU time 12 secs +Total REAL time: 12 secs Completely routed. End of route. 1330 routed (100.00%); 0 unrouted. @@ -228,8 +228,8 @@ PAR_SUMMARY::Worst slack<hold /<ns>> = 0.379 PAR_SUMMARY::Timing score<hold /<ns>> = 0.000 PAR_SUMMARY::Number of errors = 0 -Total CPU time to completion: 13 secs -Total REAL time to completion: 15 secs +Total CPU time to completion: 12 secs +Total REAL time to completion: 13 secs par done! diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt index 649ec92..c2df067 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt @@ -13,7 +13,7 @@ Hostname: ZANEMACWIN11 Implementation : impl1 -# Written on Thu Dec 28 23:09:48 2023 +# Written on Thu Dec 28 23:23:20 2023 ##### FILES SYNTAX CHECKED ############################################## Constraint File(s): "\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.sdc" diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html index 0f147ac..717bd51 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html @@ -62,7 +62,7 @@ Updated: -2023/12/28 23:10:32 +2023/12/28 23:23:58 Implementation Location: diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html index c31b427..d8ae1c6 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html @@ -12,7 +12,7 @@ #OS: Windows 8 6.2 #Hostname: ZANEMACWIN11 -# Thu Dec 28 23:09:44 2023 +# Thu Dec 28 23:23:17 2023 #Implementation: impl1 @@ -61,19 +61,21 @@ Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 202 @I::"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v" (library work) @I::"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v" (library work) Verilog syntax check successful! +File \\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v changed - recompiling +File \\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v changed - recompiling Selecting top level module RAM2E @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. Running optimization stage 1 on VHI ....... -Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) +Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. Running optimization stage 1 on VLO ....... -Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 98MB) +Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) @N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. Running optimization stage 1 on EFB ....... -Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work. Running optimization stage 1 on REFB ....... -Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) @N: CG364 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":1:7:1:15|Synthesizing module RAM2E_UFM in library work. Running optimization stage 1 on RAM2E_UFM ....... Finished optimization stage 1 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 100MB peak: 101MB) @@ -82,25 +84,25 @@ Running optimization stage 1 on RAM2E ....... Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) Running optimization stage 2 on RAM2E ....... @N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\RAM2E.v":11:15:11:19|Input nWE80 is unused. -Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) +Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on RAM2E_UFM ....... @N: CL159 :"\\Mac\iCloud\Repos\ram2e\CPLD\UFM-LCMXO2.v":10:7:10:11|Input Ready is unused. -Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) +Finished optimization stage 2 on RAM2E_UFM (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on REFB ....... -Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) +Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on EFB ....... -Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) +Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on VLO ....... -Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) +Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) Running optimization stage 2 on VHI ....... -Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) +Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 102MB peak: 102MB) -At c_ver Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB) +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 102MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Dec 28 23:09:45 2023 +# Thu Dec 28 23:23:18 2023 ###########################################################] ###########################################################[ @@ -121,13 +123,14 @@ Implementation : impl1 Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ @N|Running in 64-bit mode +File \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Dec 28 23:09:45 2023 +# Thu Dec 28 23:23:18 2023 ###########################################################] @@ -137,12 +140,12 @@ For a summary of runtime and memory usage for all design units, please see file: @END -At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 30MB peak: 31MB) +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 31MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Dec 28 23:09:46 2023 +# Thu Dec 28 23:23:18 2023 ###########################################################] ###########################################################[ @@ -170,10 +173,10 @@ At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. -# Thu Dec 28 23:09:47 2023 +# Thu Dec 28 23:23:19 2023 ###########################################################] -# Thu Dec 28 23:09:47 2023 +# Thu Dec 28 23:23:19 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -213,7 +216,7 @@ Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0 Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 152MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB) @N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2. @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. @@ -240,20 +243,20 @@ Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h @N: FX493 |Applying initial value "1" on instance nRAS. @N: FX493 |Applying initial value "1" on instance nRASout. -Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) +Starting clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) -Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished clock optimization phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) -Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Starting clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) -Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished clock optimization report phase (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) @N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E -Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) +Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) @@ -309,7 +312,7 @@ Clock Tree ID Driving Element Drive Element Type Fanout Sample I @N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. -Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) +Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) @@ -322,10 +325,10 @@ Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Thu Dec 28 23:09:49 2023 +# Thu Dec 28 23:23:21 2023 ###########################################################] -# Thu Dec 28 23:09:49 2023 +# Thu Dec 28 23:23:21 2023 Copyright (C) 1994-2021 Synopsys, Inc. @@ -359,19 +362,19 @@ Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0 Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) -Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB) +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 178MB peak: 178MB) -Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) +Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 183MB peak: 183MB) @N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e.v":14:23:14:28|Found counter in view:work.RAM2E(verilog) instance FS[15:0] @W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. -Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) +Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 186MB peak: 186MB) Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 190MB) @@ -393,7 +396,7 @@ Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elaps Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 190MB peak: 191MB) -Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB) +Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 191MB peak: 191MB) Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 211MB peak: 211MB) @@ -411,30 +414,30 @@ Finished technology timing optimizations and critical path resynthesis (Real Tim Finished restoring hierarchy (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB) -Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB) +Start Writing Netlists (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 212MB) Writing Analyst data base \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm -Finished Writing Netlist Databases (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 212MB peak: 212MB) +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 212MB peak: 212MB) Writing EDIF Netlist and constraint files @N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\ram2e\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF -Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) -Finished Writing Netlists (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) +Finished Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 217MB peak: 217MB) -Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 215MB peak: 217MB) +Start final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 215MB peak: 217MB) @W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N: MT615 |Found clock C14M with period 69.84ns ##### START OF TIMING REPORT #####[ -# Timing report written on Thu Dec 28 23:09:54 2023 +# Timing report written on Thu Dec 28 23:23:25 2023 # @@ -656,10 +659,10 @@ ram2e_ufm.RWMask[0] FD1P3AX SP In Timing exceptions that could not be applied -Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB) +Finished final timing analysis (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB) -Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 217MB) +Finished timing report (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 216MB peak: 217MB) --------------------------------------- Resource Usage Report @@ -694,10 +697,10 @@ VHI: 3 VLO: 3 Mapper successful! -At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 79MB peak: 217MB) +At Mapper Exit (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 217MB) Process took 0h:00m:04s realtime, 0h:00m:04s cputime -# Thu Dec 28 23:09:54 2023 +# Thu Dec 28 23:23:25 2023 ###########################################################] diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html index 323a4c3..1027e13 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:09:59 2023 +Thu Dec 28 23:23:29 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -128,7 +128,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:09:59 2023 +Thu Dec 28 23:23:29 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html index 9b7e706..32b00c0 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html @@ -22,7 +22,7 @@ Setup and Hold Report -------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:10:16 2023 +Thu Dec 28 23:23:44 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -630,7 +630,7 @@ Constraints cover 1611 paths, 1 nets, and 1095 connections (82.33% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 -Thu Dec 28 23:10:16 2023 +Thu Dec 28 23:23:44 2023 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf index a190de7..3712166 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf @@ -1,7 +1,7 @@ (DELAYFILE (SDFVERSION "3.0") (DESIGN "RAM2E") - (DATE "Thu Dec 28 23:10:23 2023") + (DATE "Thu Dec 28 23:23:51 2023") (VENDOR "Lattice") (PROGRAM "ldbanno") (VERSION "Diamond (64-bit) 3.12.1.454") diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo index 71bdabd..8976b2c 100644 --- a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo @@ -2,8 +2,8 @@ // Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 // ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd -// Netlist created on Thu Dec 28 23:09:57 2023 -// Netlist written on Thu Dec 28 23:10:23 2023 +// Netlist created on Thu Dec 28 23:23:28 2023 +// Netlist written on Thu Dec 28 23:23:51 2023 // Design is for device LCMXO2-640HC // Design is for package TQFP100 // Design is for performance grade 4 diff --git a/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior index 0068b9c..3d035e6 100644 --- a/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior +++ b/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior @@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 34.4. // Package: TQFP100 // ncd File: ram2e_lcmxo2_640hc_impl1.ncd // Version: Diamond (64-bit) 3.12.1.454 -// Written on Thu Dec 28 23:10:19 2023 +// Written on Thu Dec 28 23:23:47 2023 // M: Minimum Performance Grade // iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/ram2e/CPLD/LCMXO2-640HC/promote.xml diff --git a/CPLD/LCMXO2-640HC/promote.xml b/CPLD/LCMXO2-640HC/promote.xml index 3764576..7633d81 100644 --- a/CPLD/LCMXO2-640HC/promote.xml +++ b/CPLD/LCMXO2-640HC/promote.xml @@ -1,3 +1,3 @@ - +