From 25b6032966aadab1fd65f8d8883325fdb8e13c52 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Wed, 10 Mar 2021 21:14:36 -0500 Subject: [PATCH] Removed old MAX II stuff from MAX V directory --- cpld_maxv/New folder/RAM2E.qsf | 259 -------------- cpld_maxv/New folder/RAM2E.qws | Bin 407 -> 0 bytes cpld_maxv/New folder/RAM2E.v | 636 --------------------------------- cpld_maxv/New folder/UFM.qip | 3 - cpld_maxv/New folder/UFM.v | 268 -------------- 5 files changed, 1166 deletions(-) delete mode 100644 cpld_maxv/New folder/RAM2E.qsf delete mode 100644 cpld_maxv/New folder/RAM2E.qws delete mode 100644 cpld_maxv/New folder/RAM2E.v delete mode 100644 cpld_maxv/New folder/UFM.qip delete mode 100644 cpld_maxv/New folder/UFM.v diff --git a/cpld_maxv/New folder/RAM2E.qsf b/cpld_maxv/New folder/RAM2E.qsf deleted file mode 100644 index c9ec12d..0000000 --- a/cpld_maxv/New folder/RAM2E.qsf +++ /dev/null @@ -1,259 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 1991-2013 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus II 32-bit -# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition -# Date created = 22:58:44 May 05, 2020 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# RAM2E_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "MAX II" -set_global_assignment -name DEVICE EPM240T100C5 -set_global_assignment -name TOP_LEVEL_ENTITY RAM2E -set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:58:44 MAY 05, 2020" -set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 -set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" -set_global_assignment -name VERILOG_FILE RAM2E.v -set_global_assignment -name SDC_FILE constraints.sdc -set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF -set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name FITTER_EFFORT "STANDARD FIT" -set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED -set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF -set_global_assignment -name SAFE_STATE_MACHINE ON -set_global_assignment -name PARALLEL_SYNTHESIS OFF -set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name MIF_FILE RAM2E.mif -set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" - -set_location_assignment PIN_12 -to C14M -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C14M - -set_location_assignment PIN_37 -to PHI1 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI1 -set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to PHI1 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI1 - -set_location_assignment PIN_51 -to nWE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE -set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE - -set_location_assignment PIN_28 -to nEN80 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nEN80 -set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nEN80 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80 - -set_location_assignment PIN_33 -to nWE80 -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80 -set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80 -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80 - -set_location_assignment PIN_52 -to nC07X -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nC07X -set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nC07X -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nC07X - -set_location_assignment PIN_56 -to Ain[0] -set_location_assignment PIN_54 -to Ain[1] -set_location_assignment PIN_43 -to Ain[2] -set_location_assignment PIN_47 -to Ain[3] -set_location_assignment PIN_44 -to Ain[4] -set_location_assignment PIN_34 -to Ain[5] -set_location_assignment PIN_39 -to Ain[6] -set_location_assignment PIN_53 -to Ain[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Ain -set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Ain -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Ain - -set_location_assignment PIN_38 -to Din[0] -set_location_assignment PIN_40 -to Din[1] -set_location_assignment PIN_42 -to Din[2] -set_location_assignment PIN_41 -to Din[3] -set_location_assignment PIN_48 -to Din[4] -set_location_assignment PIN_49 -to Din[5] -set_location_assignment PIN_36 -to Din[6] -set_location_assignment PIN_35 -to Din[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din -set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Din -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Din - -set_location_assignment PIN_55 -to nDOE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE -set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE - -set_location_assignment PIN_77 -to Dout[0] -set_location_assignment PIN_76 -to Dout[1] -set_location_assignment PIN_74 -to Dout[2] -set_location_assignment PIN_75 -to Dout[3] -set_location_assignment PIN_73 -to Dout[4] -set_location_assignment PIN_72 -to Dout[5] -set_location_assignment PIN_84 -to Dout[6] -set_location_assignment PIN_85 -to Dout[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout -set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout - -set_location_assignment PIN_50 -to nVOE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE -set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE - -set_location_assignment PIN_70 -to Vout[0] -set_location_assignment PIN_67 -to Vout[1] -set_location_assignment PIN_69 -to Vout[2] -set_location_assignment PIN_62 -to Vout[3] -set_location_assignment PIN_71 -to Vout[4] -set_location_assignment PIN_68 -to Vout[5] -set_location_assignment PIN_58 -to Vout[6] -set_location_assignment PIN_57 -to Vout[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Vout -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Vout -set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout - -set_location_assignment PIN_4 -to CKE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE -set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE - -set_location_assignment PIN_8 -to nCS -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS -set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS - -set_location_assignment PIN_2 -to nRWE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE -set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE - -set_location_assignment PIN_5 -to nRAS -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS -set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS - -set_location_assignment PIN_3 -to nCAS -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS -set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS - -set_location_assignment PIN_6 -to BA[0] -set_location_assignment PIN_14 -to BA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BA -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to BA -set_instance_assignment -name SLOW_SLEW_RATE ON -to BA -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA - -set_location_assignment PIN_18 -to RA[0] -set_location_assignment PIN_20 -to RA[1] -set_location_assignment PIN_30 -to RA[2] -set_location_assignment PIN_27 -to RA[3] -set_location_assignment PIN_26 -to RA[4] -set_location_assignment PIN_29 -to RA[5] -set_location_assignment PIN_21 -to RA[6] -set_location_assignment PIN_19 -to RA[7] -set_location_assignment PIN_17 -to RA[8] -set_location_assignment PIN_15 -to RA[9] -set_location_assignment PIN_16 -to RA[10] -set_location_assignment PIN_7 -to RA[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA -set_instance_assignment -name SLOW_SLEW_RATE ON -to RA -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA - -set_location_assignment PIN_100 -to DQMH -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH -set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQMH -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH - -set_location_assignment PIN_98 -to DQML -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQML -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML -set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQML -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML - -set_location_assignment PIN_97 -to RD[0] -set_location_assignment PIN_90 -to RD[1] -set_location_assignment PIN_99 -to RD[2] -set_location_assignment PIN_89 -to RD[3] -set_location_assignment PIN_91 -to RD[4] -set_location_assignment PIN_92 -to RD[5] -set_location_assignment PIN_95 -to RD[6] -set_location_assignment PIN_96 -to RD[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD -set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD -set_instance_assignment -name SLOW_SLEW_RATE ON -to RD -set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD - -set_global_assignment -name QIP_FILE UFM.qip \ No newline at end of file diff --git a/cpld_maxv/New folder/RAM2E.qws b/cpld_maxv/New folder/RAM2E.qws deleted file mode 100644 index ab951d37e7f6f2841374dfb0d8482ab716dd7f0f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 407 zcmZusOA5kJ44n7;&_j3tH=UK1Z{V2%W9Y%s3>wq$LBsS_E-0d`2yK}<+Yk-$QiLKVDrL~nVTqG-R7)}prf^+XqZ`e<#?`FDbW_gdJLi&`Hg{nk{oa9n1exMZM332c>k>KLn)K;swTL BSjPYW diff --git a/cpld_maxv/New folder/RAM2E.v b/cpld_maxv/New folder/RAM2E.v deleted file mode 100644 index 5c553eb..0000000 --- a/cpld_maxv/New folder/RAM2E.v +++ /dev/null @@ -1,636 +0,0 @@ -module RAM2E(C14M, PHI1, - nWE, nWE80, nEN80, nC07X, - Ain, Din, Dout, nDOE, Vout, nVOE, - CKE, nCS, nRAS, nCAS, nRWE, - BA, RA, RD, DQML, DQMH); - - /* Clocks */ - input C14M, PHI1; - - /* Control inputs */ - input nWE, nWE80, nEN80, nC07X; - - /* Delay for EN80 signal */ - //output DelayOut = 1'b0; - //input DelayIn; - wire EN80 = ~nEN80; - - /* Address Bus */ - input [7:0] Ain; // Multiplexed DRAM address input - - /* 6502 Data Bus */ - input [7:0] Din; // 6502 data bus inputs - reg DOEEN = 0; // 6502 data bus output enable from state machine - output nDOE = ~(EN80 & nWE & DOEEN); // 6502 data bus output enable - output reg [7:0] Dout; // 6502 data Bus output - - /* Video Data Bus */ - output nVOE = ~(~PHI1); /// Video data bus output enable - output reg [7:0] Vout; // Video data bus - - /* SDRAM */ - output reg CKE = 0; - output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1; - output reg [1:0] BA; - output reg [11:0] RA; - output reg DQML = 1, DQMH = 1; - wire RDOE = EN80 & ~nWE80; - inout [7:0] RD = RDOE ? Din[7:0] : 8'bZ; - - /* RAMWorks Bank Register and Capacity Mask */ - reg [7:0] RWBank = 0; // RAMWorks bank register - reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask - reg RWSel = 0; // RAMWorks bank register select - reg RWMaskSet = 0; // RAMWorks Mask register set flag - reg SetRWBankFF = 0; // Causes RWBank to be zeroed next RWSel access - - /* Command Sequence Detector */ - reg [2:0] CS = 0; // Command sequence state - reg [2:0] CmdTout = 0; // Command sequence timeout - - /* UFM Interface */ - reg [15:8] UFMD = 0; // *Parallel* UFM data register - reg ARCLK = 0; // UFM address register clock - // UFM address register data input tied to 0 - reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment - reg DRCLK = 0; // UFM data register clock - reg DRDIn = 0; // UFM data register input - reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address - reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy - reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy - wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous - wire RTPBusy; // 1 if real-time programming in progress. Asynchronous - wire DRDOut; // UFM data output - // UFM oscillator always enabled - wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz) - UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V) - .arclk (ARCLK), - .ardin (1'b0), - .arshft (ARShift), - .drclk (DRCLK), - .drdin (DRDIn), - .drshft (DRShift), - .erase (UFMErase), - .oscena (1'b1), - .program (UFMProgram), - .busy (UFMBusy), - .drdout (DRDOut), - .osc (UFMOsc), - .rtpbusy (RTPBusy)); - reg UFMBusyReg = 0; // UFMBusy registered to sync with C14M - reg RTPBusyReg = 0; // RTPBusy registered to sync with C14M - - /* UFM State & User Command Triggers */ - reg UFMInitDone = 0; // 1 if UFM initialization finished - reg UFMReqErase = 0; // 1 if UFM requires erase - reg UFMBitbang = 0; // Set by user command. Loads UFM outputs next RWSel - reg UFMPrgmEN = 0; // Set by user command. Programs UFM - reg UFMEraseEN = 0; // Set by user command. Erases UFM - reg DRCLKPulse = 0; // Set by user command. Causes DRCLK pulse next C14M - - /* State Counters */ - reg PHI1reg = 0; // Saved PHI1 at last rising clock edge - reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15 - reg [15:0] FS = 0; // Fast state counter - reg [3:0] S = 0; // IIe State counter - - /* State Counters */ - always @(posedge C14M) begin - // Increment fast state counter - FS <= FS+1; - // Synchronize Apple state counter to S1 when just entering PHI1 - PHI1reg <= PHI1; // Save old PHI1 - S <= (PHI1 & ~PHI1reg & Ready) ? 4'h1 : - S==4'h0 ? 4'h0 : - S==4'hF ? 4'hF : S+1; - end - - /* UFM Control */ - always @(posedge C14M) begin - // Synchronize asynchronous UFM signals - UFMBusyReg <= UFMBusy; - RTPBusyReg <= RTPBusy; - - if (S==4'h0) begin - if ((FS[15:13]==3'b101) | (FS[15:13]==3'b111 & UFMReqErase)) begin - // In states AXXX-BXXX and also EXXX-FXXX if erase/wrap req'd - // shift in 0's to address register - ARCLK <= FS[0]; // Clock address register - DRCLK <= 1'b0; // Don't clock data register - ARShift <= 1'b1; // Shift address registers - DRDIn <= 1'b0; // Don't care DRDIn - DRShift <= 1'b0; // Don't care DRDShift - end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4:1]==4'h4) begin - // In states CXXX-DXXX (substep 4) - // Xfer to data reg (repeat 256x 1x) - ARCLK <= 1'b0; // Don't clock address register - DRCLK <= FS[0]; // Clock data register - ARShift <= 1'b0; // Don't care ARShift - DRDIn <= 1'b0; // Don't care DRDIn - DRShift <= 1'b0; // Don't care DRShift - end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4]==1'b1) begin - // In states CXXX-DXXX (substeps 8-F) - // Save UFM D15-8, shift out D14-7 (repeat 256x 8x) - DRCLK <= FS[0]; // Clock data register - ARShift <= 1'b0; // ARShift is 0 because we want to increment - DRDIn <= 1'b0; // Don't care what to shift into data register - DRShift <= 1'b1; // Shift data register - // Shift into UFMD - if (FS[0]) UFMD[15:8] <= {UFMD[14:8], DRDOut}; - - // Compare and store mask - if (FS[4:1]==4'hF) begin - ARCLK <= FS[0]; // Clock address register to increment - // If byte is erased (0xFF, i.e. all 1's, is erased)... - if (UFMD[14:8]==7'b1111111 & DRDOut==1'b1) begin - // Current UFM address is where we want to store - UFMInitDone <= 1'b1; // Quit iterating - // Otherwise byte is valid setting (i.e. some bit is 0)... - end else begin - // Set RWMask, but if saved mask is 0x80, store ~0xFF - if (UFMD[14:8]==7'b1000000 & DRDOut==1'b0) begin - RWMask[7:0] <= {1'b1, ~7'h7F}; - end else RWMask[7:0] <= {UFMD[14], ~UFMD[13:8], ~DRDOut}; - // If last byte in sector... - if (FS[12:5]==8'hFF) begin - UFMReqErase <= 1'b1; // Mark need to erase - end - end - end else ARCLK <= 1'b0; // Don't clock address register - end else begin - ARCLK <= 1'b0; - DRCLK <= 1'b0; - ARShift <= 1'b0; - DRDIn <= 1'b0; - DRShift <= 1'b0; - end - - // Don't erase or program UFM during initialization - UFMErase <= 1'b0; - UFMProgram <= 1'b0; - // Keep DRCLK pulse control disabled during init - DRCLKPulse <= 1'b0; - end else begin - // Can only shift UFM data register now - ARCLK <= 1'b0; - ARShift <= 1'b0; - DRShift <= 1'b1; - - // UFM bitbang control - if (UFMBitbang & CS==3'h7 & RWSel & S==4'hC) begin - DRDIn <= Din[6]; - DRCLKPulse <= Din[7]; - DRCLK <= 1'b0; - end else begin - DRCLKPulse <= 1'b0; - DRCLK <= DRCLKPulse; - end - - // Set capacity mask - if (RWMaskSet & RWSel & S==4'hC) RWMask[7:0] <= {Din[7], ~Din[6:0]}; - - // UFM programming sequence - if (UFMPrgmEN | UFMEraseEN) begin - if (~UFMBusyReg & ~RTPBusyReg) begin - if (UFMReqErase | UFMEraseEN) UFMErase <= 1'b1; - else if (UFMPrgmEN) UFMProgram <= 1'b1; - end else if (UFMBusyReg) UFMReqErase <= 1'b0; - end - end - end - - /* SDRAM Control */ - always @(posedge C14M) begin - if (S==4'h0) begin - // SDRAM initialization - if (FS[15:0]==16'hFFC0) begin - // Precharge All - nCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b1; - nRWE <= 1'b0; - RA[10] <= 1'b1; // "all" - end else if (FS[15:4]==16'hFFD & FS[0]==1'b0) begin // Repeat 8x - // Auto-refresh - nCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b0; - nRWE <= 1'b1; - RA[10] <= 1'b0; - end else if (FS[15:0]==16'hFFE8) begin - // Set Mode Register - nCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b0; - nRWE <= 1'b0; - RA[10] <= 1'b0; // Reserved in mode register - end else if (FS[15:4]==12'hFFF & FS[0]==1'b0) begin // Repeat 8x - // Auto-refresh - nCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b0; - nRWE <= 1'b1; - RA[10] <= 1'b0; - end else begin // Otherwise send no-op - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - RA[10] <= 1'b0; - end - // Enable SDRAM clock after 65,280 cycles (~4.56ms) - CKE <= FS[15:8] == 8'hFF; - - // Mode register contents - BA[1:0] <= 2'b00; // Reserved - RA[11] <= 1'b0; // Reserved - // RA[10] set above ^ - RA[9] <= 1'b1; // "1" for single write mode - RA[8] <= 1'b0; // Reserved - RA[7] <= 1'b0; // "0" for not test mode - RA[6:4] <= 3'b010; // "2" for CAS latency 2 - RA[3] <= 1'b0; // "0" for sequential burst (not used) - RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst) - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - - // Begin normal operation after 128k init cycles (~9.15ms) - if (FS == 16'hFFFF) Ready <= 1'b1; - end else if (S==4'h1) begin - // Enable clock - CKE <= 1'b1; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'h2) begin - // Enable clock - CKE <= 1'b1; - - // Activate - nCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // SDRAM bank 0, high-order row address is 0 - BA <= 2'b00; - RA[11:8] <= 4'b0000; - // Row address is as previously latched - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'h3) begin - // Enable clock - CKE <= 1'b1; - - // Read - nCS <= 1'b0; - nRAS <= 1'b1; - nCAS <= 1'b0; - nRWE <= 1'b1; - - // SDRAM bank 0, RA[11,9:8] don't care - BA <= 2'b00; - RA[11] <= 1'b0; - RA[10] <= 1'b1; // (A10 set to auto-precharge) - RA[9] <= 1'b0; - RA[8] <= 1'b0; - // Latch column address for read command - RA[7:0] <= Ain[7:0]; - - // Read low byte (high byte is +4MB in ramworks) - DQML <= 1'b0; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'h4) begin - // Enable clock - CKE <= 1'b1; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'h5) begin - // Enable clock - CKE <= 1'b1; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'h6) begin - // Enable clock - CKE <= 1'b1; - - if (FS[5:4]==0) begin - // Auto-refresh - nCS <= 1'b0; - nRAS <= 1'b0; - nCAS <= 1'b0; - nRWE <= 1'b1; - end else begin - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - end - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'h7) begin - // Enable clock - CKE <= 1'b1; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - // Latch row address for activate command - RA[7:0] <= Ain[7:0]; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'h8) begin - // Enable clock if '245 output enabled - CKE <= EN80; - - // Activate if '245 output enabled - nCS <= nEN80; - nRAS <= 1'b0; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // SDRAM bank, RA[11:8] determine by RamWorks bank - BA <= RWBank[5:4]; - RA[11:8] <= RWBank[3:0]; - // Row address is as previously latched - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'h9) begin - // Enable clock if '245 output enabled - CKE <= EN80; - - // Read/Write if '245 output enabled - nCS <= nEN80; - nRAS <= 1'b1; - nCAS <= 1'b0; - nRWE <= nWE80; - - // SDRAM bank still determined by RamWorks, RA[11,9:8] don't care - BA <= RWBank[5:4]; - RA[11] <= 1'b0; - RA[10] <= 1'b1; // (A10 set to auto-precharge) - RA[9] <= 1'b0; - RA[8] <= RWBank[7]; - // Latch column address for R/W command - RA[7:0] <= Ain[7:0]; - - // Latch RAMWorks low nybble write select using old row address - RWSel <= RA[0] & ~RA[3] & ~nWE & ~nC07X; - - // Mask according to RAMWorks bank (high byte is +4MB) - DQML <= RWBank[6]; - DQMH <= ~RWBank[6]; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'hA) begin - // Enable clock if '245 output enabled - CKE <= EN80; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'hB) begin - // Disable clock - CKE <= 1'b0; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Enable data bus output - DOEEN <= 1'b1; - end else if (S==4'hC) begin - // Disable clock - CKE <= 1'b0; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Enable data bus output - DOEEN <= 1'b1; - - // RAMWorks Bank Register Select - if (RWSel) begin - // Latch RAMWorks bank if accessed - if (SetRWBankFF) RWBank <= 8'hFF; - else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]}; - - // Recognize command sequence and advance CS state - if ((CS==3'h0 & Din[7:0]==8'hFF) | - (CS==3'h1 & Din[7:0]==8'h00) | - (CS==3'h2 & Din[7:0]==8'h55) | - (CS==3'h3 & Din[7:0]==8'hAA) | - (CS==3'h4 & Din[7:0]==8'hC1) | - (CS==3'h5 & Din[7:0]==8'hAD) | - CS==3'h6 | CS==3'h7) CS <= CS+1; - else CS <= 0; // Back to beginning if it's not right - - if (CS==3'h6) begin // Recognize and submit command in CS6 - SetRWBankFF <= Din[7:0]==8'hFF; - if (Din[7:0]==8'hEF) UFMPrgmEN <= 1'b1; - if (Din[7:0]==8'hEE) UFMEraseEN <= 1'b1; - UFMBitbang <= Din[7:0]==8'hEA; - RWMaskSet <= Din[7:0]==8'hE0; - end else begin // Reset command triggers - SetRWBankFF <= 1'b0; - UFMBitbang <= 1'b0; - RWMaskSet <= 1'b0; - end - - CmdTout <= 0; // Reset command timeout if RWSel accessed - end else begin - CmdTout <= CmdTout+1; // Increment command timeout - // If command sequence times out, reset sequence state - if (CmdTout==3'h7) CS <= 0; - end - end else if (S==4'hD) begin - // Disable clock - CKE <= 1'b0; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Enable data bus output - DOEEN <= 1'b1; - end else if (S==4'hE) begin - // Disable clock - CKE <= 1'b0; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - // Latch row address for next video read - RA[7:0] <= Ain[7:0]; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Enable data bus output - DOEEN <= 1'b1; - end else if (S==4'hF) begin - // Disable clock - CKE <= 1'b0; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - // Latch row address for next video read - RA[7:0] <= Ain[7:0]; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Enable data bus output - DOEEN <= 1'b1; - end - end - always @(negedge C14M) begin - // Latch video and read data outputs - if (S==4'h6) Vout[7:0] <= RD[7:0]; - if (S==4'hC) Dout[7:0] <= RD[7:0]; - end -endmodule diff --git a/cpld_maxv/New folder/UFM.qip b/cpld_maxv/New folder/UFM.qip deleted file mode 100644 index e2d8458..0000000 --- a/cpld_maxv/New folder/UFM.qip +++ /dev/null @@ -1,3 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE" -set_global_assignment -name IP_TOOL_VERSION "13.0" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"] diff --git a/cpld_maxv/New folder/UFM.v b/cpld_maxv/New folder/UFM.v deleted file mode 100644 index ec5b564..0000000 --- a/cpld_maxv/New folder/UFM.v +++ /dev/null @@ -1,268 +0,0 @@ -// megafunction wizard: %ALTUFM_NONE% -// GENERATION: STANDARD -// VERSION: WM1.0 -// MODULE: ALTUFM_NONE - -// ============================================================ -// File Name: UFM.v -// Megafunction Name(s): -// ALTUFM_NONE -// -// Simulation Library Files(s): -// maxii -// ============================================================ -// ************************************************************ -// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -// -// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition -// ************************************************************ - - -//Copyright (C) 1991-2013 Altera Corporation -//Your use of Altera Corporation's design tools, logic functions -//and other software and tools, and its AMPP partner logic -//functions, and any output files from any of the foregoing -//(including device programming or simulation files), and any -//associated documentation or information are expressly subject -//to the terms and conditions of the Altera Program License -//Subscription Agreement, Altera MegaCore Function License -//Agreement, or other applicable license agreement, including, -//without limitation, that your use is for the sole purpose of -//programming logic devices manufactured by Altera and sold by -//Altera or its authorized distributors. Please refer to the -//applicable agreement for further details. - - -//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy -//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END -// synthesis VERILOG_INPUT_VERSION VERILOG_2001 -// altera message_off 10463 - - -//synthesis_resources = maxii_ufm 1 -//synopsys translate_off -`timescale 1 ps / 1 ps -//synopsys translate_on -module UFM_altufm_none_a7r - ( - arclk, - ardin, - arshft, - busy, - drclk, - drdin, - drdout, - drshft, - erase, - osc, - oscena, - program, - rtpbusy) ; - input arclk; - input ardin; - input arshft; - output busy; - input drclk; - input drdin; - output drdout; - input drshft; - input erase; - output osc; - input oscena; - input program; - output rtpbusy; - - wire wire_maxii_ufm_block1_bgpbusy; - wire wire_maxii_ufm_block1_busy; - wire wire_maxii_ufm_block1_drdout; - wire wire_maxii_ufm_block1_osc; - wire ufm_arclk; - wire ufm_ardin; - wire ufm_arshft; - wire ufm_bgpbusy; - wire ufm_busy; - wire ufm_drclk; - wire ufm_drdin; - wire ufm_drdout; - wire ufm_drshft; - wire ufm_erase; - wire ufm_osc; - wire ufm_oscena; - wire ufm_program; - - maxii_ufm maxii_ufm_block1 - ( - .arclk(ufm_arclk), - .ardin(ufm_ardin), - .arshft(ufm_arshft), - .bgpbusy(wire_maxii_ufm_block1_bgpbusy), - .busy(wire_maxii_ufm_block1_busy), - .drclk(ufm_drclk), - .drdin(ufm_drdin), - .drdout(wire_maxii_ufm_block1_drdout), - .drshft(ufm_drshft), - .erase(ufm_erase), - .osc(wire_maxii_ufm_block1_osc), - .oscena(ufm_oscena), - .program(ufm_program) - // synopsys translate_off - , - .ctrl_bgpbusy(1'b0), - .devclrn(1'b1), - .devpor(1'b1), - .sbdin(1'b0), - .sbdout() - // synopsys translate_on - ); - defparam - maxii_ufm_block1.address_width = 9, - maxii_ufm_block1.erase_time = 500000000, - maxii_ufm_block1.init_file = "RAM2E.mif", - maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem2 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem3 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem4 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem5 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem6 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem7 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem8 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, - maxii_ufm_block1.osc_sim_setting = 180000, - maxii_ufm_block1.program_time = 1600000, - maxii_ufm_block1.lpm_type = "maxii_ufm"; - assign - busy = ufm_busy, - drdout = ufm_drdout, - osc = ufm_osc, - rtpbusy = ufm_bgpbusy, - ufm_arclk = arclk, - ufm_ardin = ardin, - ufm_arshft = arshft, - ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy, - ufm_busy = wire_maxii_ufm_block1_busy, - ufm_drclk = drclk, - ufm_drdin = drdin, - ufm_drdout = wire_maxii_ufm_block1_drdout, - ufm_drshft = drshft, - ufm_erase = erase, - ufm_osc = wire_maxii_ufm_block1_osc, - ufm_oscena = oscena, - ufm_program = program; -endmodule //UFM_altufm_none_a7r -//VALID FILE - - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on -module UFM ( - arclk, - ardin, - arshft, - drclk, - drdin, - drshft, - erase, - oscena, - program, - busy, - drdout, - osc, - rtpbusy); - - input arclk; - input ardin; - input arshft; - input drclk; - input drdin; - input drshft; - input erase; - input oscena; - input program; - output busy; - output drdout; - output osc; - output rtpbusy; - - wire sub_wire0; - wire sub_wire1; - wire sub_wire2; - wire sub_wire3; - wire osc = sub_wire0; - wire rtpbusy = sub_wire1; - wire drdout = sub_wire2; - wire busy = sub_wire3; - - UFM_altufm_none_a7r UFM_altufm_none_a7r_component ( - .arshft (arshft), - .drclk (drclk), - .erase (erase), - .program (program), - .arclk (arclk), - .drdin (drdin), - .oscena (oscena), - .ardin (ardin), - .drshft (drshft), - .osc (sub_wire0), - .rtpbusy (sub_wire1), - .drdout (sub_wire2), - .busy (sub_wire3)); - -endmodule - -// ============================================================ -// CNX file retrieval info -// ============================================================ -// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II" -// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000" -// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II" -// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2E.mif" -// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" -// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none" -// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000" -// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000" -// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9" -// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk" -// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0 -// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin" -// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0 -// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft" -// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0 -// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy" -// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0 -// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk" -// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0 -// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin" -// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0 -// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout" -// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0 -// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft" -// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0 -// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase" -// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0 -// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc" -// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0 -// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena" -// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0 -// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program" -// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0 -// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy" -// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE -// Retrieval info: LIB_FILE: maxii