From 3fcf6a1bb2eedf296fdbcd42a45535f4ea589d1e Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Wed, 10 Mar 2021 21:14:12 -0500 Subject: [PATCH] Added MAX V CPLD firmware --- cpld_maxv/New folder/RAM2E.qsf | 259 +++++ cpld_maxv/New folder/RAM2E.qws | Bin 0 -> 407 bytes cpld_maxv/New folder/RAM2E.v | 636 +++++++++++ cpld_maxv/New folder/UFM.qip | 3 + cpld_maxv/New folder/UFM.v | 268 +++++ cpld_maxv/RAM2E - 16MB.mif | 26 + cpld_maxv/RAM2E - AF.mif | 273 +++++ cpld_maxv/RAM2E - E.mif | 25 + cpld_maxv/RAM2E - F.mif | 281 +++++ cpld_maxv/RAM2E.mif | 25 + cpld_maxv/RAM2E.qpf | 30 + cpld_maxv/RAM2E.qsf | 259 +++++ cpld_maxv/RAM2E.qws | Bin 0 -> 613 bytes cpld_maxv/RAM2E.v | 636 +++++++++++ cpld_maxv/UFM.qip | 3 + cpld_maxv/UFM.v | 268 +++++ cpld_maxv/constraints.sdc | 1 + cpld_maxv/db/RAM2E.(0).cnf.cdb | Bin 0 -> 35287 bytes cpld_maxv/db/RAM2E.(0).cnf.hdb | Bin 0 -> 4075 bytes cpld_maxv/db/RAM2E.(1).cnf.cdb | Bin 0 -> 1261 bytes cpld_maxv/db/RAM2E.(1).cnf.hdb | Bin 0 -> 928 bytes cpld_maxv/db/RAM2E.(2).cnf.cdb | Bin 0 -> 1263 bytes cpld_maxv/db/RAM2E.(2).cnf.hdb | Bin 0 -> 1018 bytes cpld_maxv/db/RAM2E.asm.qmsg | 6 + cpld_maxv/db/RAM2E.asm.rdb | Bin 0 -> 1405 bytes cpld_maxv/db/RAM2E.asm_labs.ddb | Bin 0 -> 2863 bytes cpld_maxv/db/RAM2E.cmp.cdb | Bin 0 -> 45831 bytes cpld_maxv/db/RAM2E.cmp.hdb | Bin 0 -> 18845 bytes cpld_maxv/db/RAM2E.cmp.idb | Bin 0 -> 13788 bytes cpld_maxv/db/RAM2E.cmp.kpt | Bin 0 -> 219 bytes cpld_maxv/db/RAM2E.cmp.logdb | 1 + cpld_maxv/db/RAM2E.cmp.rdb | Bin 0 -> 15115 bytes cpld_maxv/db/RAM2E.cmp0.ddb | Bin 0 -> 84616 bytes cpld_maxv/db/RAM2E.db_info | 3 + cpld_maxv/db/RAM2E.fit.qmsg | 39 + cpld_maxv/db/RAM2E.hier_info | 350 +++++++ cpld_maxv/db/RAM2E.hif | Bin 0 -> 576 bytes cpld_maxv/db/RAM2E.ipinfo | Bin 0 -> 351 bytes cpld_maxv/db/RAM2E.lpc.html | 50 + cpld_maxv/db/RAM2E.lpc.rdb | Bin 0 -> 508 bytes cpld_maxv/db/RAM2E.lpc.txt | 8 + cpld_maxv/db/RAM2E.map.cdb | Bin 0 -> 17249 bytes cpld_maxv/db/RAM2E.map.hdb | Bin 0 -> 18028 bytes cpld_maxv/db/RAM2E.map.logdb | 1 + cpld_maxv/db/RAM2E.map.qmsg | 19 + cpld_maxv/db/RAM2E.map.rdb | Bin 0 -> 1248 bytes cpld_maxv/db/RAM2E.pre_map.hdb | Bin 0 -> 16736 bytes cpld_maxv/db/RAM2E.pti_db_list.ddb | Bin 0 -> 191 bytes .../db/RAM2E.root_partition.map.reg_db.cdb | Bin 0 -> 210 bytes cpld_maxv/db/RAM2E.routing.rdb | Bin 0 -> 1464 bytes cpld_maxv/db/RAM2E.rtlv.hdb | Bin 0 -> 16558 bytes cpld_maxv/db/RAM2E.rtlv_sg.cdb | Bin 0 -> 28718 bytes cpld_maxv/db/RAM2E.rtlv_sg_swap.cdb | Bin 0 -> 816 bytes cpld_maxv/db/RAM2E.sgdiff.cdb | Bin 0 -> 17288 bytes cpld_maxv/db/RAM2E.sgdiff.hdb | Bin 0 -> 16780 bytes cpld_maxv/db/RAM2E.sld_design_entry.sci | Bin 0 -> 216 bytes cpld_maxv/db/RAM2E.sld_design_entry_dsc.sci | Bin 0 -> 216 bytes cpld_maxv/db/RAM2E.smart_action.txt | 1 + cpld_maxv/db/RAM2E.sta.qmsg | 22 + cpld_maxv/db/RAM2E.sta.rdb | Bin 0 -> 10721 bytes cpld_maxv/db/RAM2E.sta_cmp.5_slow.tdb | Bin 0 -> 43427 bytes cpld_maxv/db/RAM2E.syn_hier_info | 0 cpld_maxv/db/RAM2E.tis_db_list.ddb | Bin 0 -> 191 bytes cpld_maxv/db/RAM2E.tmw_info | 6 + cpld_maxv/db/RAM2E.vpr.ammdb | Bin 0 -> 612 bytes cpld_maxv/db/logic_util_heursitic.dat | Bin 0 -> 11396 bytes cpld_maxv/db/prev_cmp_RAM2E.qmsg | 94 ++ cpld_maxv/greybox_tmp/cbx_args.txt | 25 + cpld_maxv/incremental_db/README | 11 + .../compiled_partitions/RAM2E.db_info | 3 + .../RAM2E.root_partition.map.kpt | Bin 0 -> 2893 bytes cpld_maxv/output_files/RAM2E.asm.rpt | 114 ++ cpld_maxv/output_files/RAM2E.done | 1 + cpld_maxv/output_files/RAM2E.fit.rpt | 987 ++++++++++++++++++ cpld_maxv/output_files/RAM2E.fit.smsg | 4 + cpld_maxv/output_files/RAM2E.fit.summary | 11 + cpld_maxv/output_files/RAM2E.flow.rpt | 125 +++ cpld_maxv/output_files/RAM2E.jdi | 8 + cpld_maxv/output_files/RAM2E.map.rpt | 305 ++++++ cpld_maxv/output_files/RAM2E.map.smsg | 3 + cpld_maxv/output_files/RAM2E.map.summary | 9 + cpld_maxv/output_files/RAM2E.pin | 164 +++ cpld_maxv/output_files/RAM2E.pof | Bin 0 -> 7879 bytes cpld_maxv/output_files/RAM2E.sta.rpt | 809 ++++++++++++++ cpld_maxv/output_files/RAM2E.sta.summary | 17 + 85 files changed, 6189 insertions(+) create mode 100644 cpld_maxv/New folder/RAM2E.qsf create mode 100644 cpld_maxv/New folder/RAM2E.qws create mode 100644 cpld_maxv/New folder/RAM2E.v create mode 100644 cpld_maxv/New folder/UFM.qip create mode 100644 cpld_maxv/New folder/UFM.v create mode 100644 cpld_maxv/RAM2E - 16MB.mif create mode 100644 cpld_maxv/RAM2E - AF.mif create mode 100644 cpld_maxv/RAM2E - E.mif create mode 100644 cpld_maxv/RAM2E - F.mif create mode 100644 cpld_maxv/RAM2E.mif create mode 100644 cpld_maxv/RAM2E.qpf create mode 100644 cpld_maxv/RAM2E.qsf create mode 100644 cpld_maxv/RAM2E.qws create mode 100644 cpld_maxv/RAM2E.v create mode 100644 cpld_maxv/UFM.qip create mode 100644 cpld_maxv/UFM.v create mode 100644 cpld_maxv/constraints.sdc create mode 100644 cpld_maxv/db/RAM2E.(0).cnf.cdb create mode 100644 cpld_maxv/db/RAM2E.(0).cnf.hdb create mode 100644 cpld_maxv/db/RAM2E.(1).cnf.cdb create mode 100644 cpld_maxv/db/RAM2E.(1).cnf.hdb create mode 100644 cpld_maxv/db/RAM2E.(2).cnf.cdb create mode 100644 cpld_maxv/db/RAM2E.(2).cnf.hdb create mode 100644 cpld_maxv/db/RAM2E.asm.qmsg create mode 100644 cpld_maxv/db/RAM2E.asm.rdb create mode 100644 cpld_maxv/db/RAM2E.asm_labs.ddb create mode 100644 cpld_maxv/db/RAM2E.cmp.cdb create mode 100644 cpld_maxv/db/RAM2E.cmp.hdb create mode 100644 cpld_maxv/db/RAM2E.cmp.idb create mode 100644 cpld_maxv/db/RAM2E.cmp.kpt create mode 100644 cpld_maxv/db/RAM2E.cmp.logdb create mode 100644 cpld_maxv/db/RAM2E.cmp.rdb create mode 100644 cpld_maxv/db/RAM2E.cmp0.ddb create mode 100644 cpld_maxv/db/RAM2E.db_info create mode 100644 cpld_maxv/db/RAM2E.fit.qmsg create mode 100644 cpld_maxv/db/RAM2E.hier_info create mode 100644 cpld_maxv/db/RAM2E.hif create mode 100644 cpld_maxv/db/RAM2E.ipinfo create mode 100644 cpld_maxv/db/RAM2E.lpc.html create mode 100644 cpld_maxv/db/RAM2E.lpc.rdb create mode 100644 cpld_maxv/db/RAM2E.lpc.txt create mode 100644 cpld_maxv/db/RAM2E.map.cdb create mode 100644 cpld_maxv/db/RAM2E.map.hdb create mode 100644 cpld_maxv/db/RAM2E.map.logdb create mode 100644 cpld_maxv/db/RAM2E.map.qmsg create mode 100644 cpld_maxv/db/RAM2E.map.rdb create mode 100644 cpld_maxv/db/RAM2E.pre_map.hdb create mode 100644 cpld_maxv/db/RAM2E.pti_db_list.ddb create mode 100644 cpld_maxv/db/RAM2E.root_partition.map.reg_db.cdb create mode 100644 cpld_maxv/db/RAM2E.routing.rdb create mode 100644 cpld_maxv/db/RAM2E.rtlv.hdb create mode 100644 cpld_maxv/db/RAM2E.rtlv_sg.cdb create mode 100644 cpld_maxv/db/RAM2E.rtlv_sg_swap.cdb create mode 100644 cpld_maxv/db/RAM2E.sgdiff.cdb create mode 100644 cpld_maxv/db/RAM2E.sgdiff.hdb create mode 100644 cpld_maxv/db/RAM2E.sld_design_entry.sci create mode 100644 cpld_maxv/db/RAM2E.sld_design_entry_dsc.sci create mode 100644 cpld_maxv/db/RAM2E.smart_action.txt create mode 100644 cpld_maxv/db/RAM2E.sta.qmsg create mode 100644 cpld_maxv/db/RAM2E.sta.rdb create mode 100644 cpld_maxv/db/RAM2E.sta_cmp.5_slow.tdb create mode 100644 cpld_maxv/db/RAM2E.syn_hier_info create mode 100644 cpld_maxv/db/RAM2E.tis_db_list.ddb create mode 100644 cpld_maxv/db/RAM2E.tmw_info create mode 100644 cpld_maxv/db/RAM2E.vpr.ammdb create mode 100644 cpld_maxv/db/logic_util_heursitic.dat create mode 100644 cpld_maxv/db/prev_cmp_RAM2E.qmsg create mode 100644 cpld_maxv/greybox_tmp/cbx_args.txt create mode 100644 cpld_maxv/incremental_db/README create mode 100644 cpld_maxv/incremental_db/compiled_partitions/RAM2E.db_info create mode 100644 cpld_maxv/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt create mode 100644 cpld_maxv/output_files/RAM2E.asm.rpt create mode 100644 cpld_maxv/output_files/RAM2E.done create mode 100644 cpld_maxv/output_files/RAM2E.fit.rpt create mode 100644 cpld_maxv/output_files/RAM2E.fit.smsg create mode 100644 cpld_maxv/output_files/RAM2E.fit.summary create mode 100644 cpld_maxv/output_files/RAM2E.flow.rpt create mode 100644 cpld_maxv/output_files/RAM2E.jdi create mode 100644 cpld_maxv/output_files/RAM2E.map.rpt create mode 100644 cpld_maxv/output_files/RAM2E.map.smsg create mode 100644 cpld_maxv/output_files/RAM2E.map.summary create mode 100644 cpld_maxv/output_files/RAM2E.pin create mode 100644 cpld_maxv/output_files/RAM2E.pof create mode 100644 cpld_maxv/output_files/RAM2E.sta.rpt create mode 100644 cpld_maxv/output_files/RAM2E.sta.summary diff --git a/cpld_maxv/New folder/RAM2E.qsf b/cpld_maxv/New folder/RAM2E.qsf new file mode 100644 index 0000000..c9ec12d --- /dev/null +++ b/cpld_maxv/New folder/RAM2E.qsf @@ -0,0 +1,259 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 22:58:44 May 05, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# RAM2E_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX II" +set_global_assignment -name DEVICE EPM240T100C5 +set_global_assignment -name TOP_LEVEL_ENTITY RAM2E +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:58:44 MAY 05, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" +set_global_assignment -name VERILOG_FILE RAM2E.v +set_global_assignment -name SDC_FILE constraints.sdc +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name SAFE_STATE_MACHINE ON +set_global_assignment -name PARALLEL_SYNTHESIS OFF +set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name MIF_FILE RAM2E.mif +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" + +set_location_assignment PIN_12 -to C14M +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C14M + +set_location_assignment PIN_37 -to PHI1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI1 +set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to PHI1 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI1 + +set_location_assignment PIN_51 -to nWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE + +set_location_assignment PIN_28 -to nEN80 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nEN80 +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nEN80 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80 + +set_location_assignment PIN_33 -to nWE80 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80 +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80 + +set_location_assignment PIN_52 -to nC07X +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nC07X +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nC07X +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nC07X + +set_location_assignment PIN_56 -to Ain[0] +set_location_assignment PIN_54 -to Ain[1] +set_location_assignment PIN_43 -to Ain[2] +set_location_assignment PIN_47 -to Ain[3] +set_location_assignment PIN_44 -to Ain[4] +set_location_assignment PIN_34 -to Ain[5] +set_location_assignment PIN_39 -to Ain[6] +set_location_assignment PIN_53 -to Ain[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Ain +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Ain +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Ain + +set_location_assignment PIN_38 -to Din[0] +set_location_assignment PIN_40 -to Din[1] +set_location_assignment PIN_42 -to Din[2] +set_location_assignment PIN_41 -to Din[3] +set_location_assignment PIN_48 -to Din[4] +set_location_assignment PIN_49 -to Din[5] +set_location_assignment PIN_36 -to Din[6] +set_location_assignment PIN_35 -to Din[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Din +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Din + +set_location_assignment PIN_55 -to nDOE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE + +set_location_assignment PIN_77 -to Dout[0] +set_location_assignment PIN_76 -to Dout[1] +set_location_assignment PIN_74 -to Dout[2] +set_location_assignment PIN_75 -to Dout[3] +set_location_assignment PIN_73 -to Dout[4] +set_location_assignment PIN_72 -to Dout[5] +set_location_assignment PIN_84 -to Dout[6] +set_location_assignment PIN_85 -to Dout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout +set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout + +set_location_assignment PIN_50 -to nVOE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE + +set_location_assignment PIN_70 -to Vout[0] +set_location_assignment PIN_67 -to Vout[1] +set_location_assignment PIN_69 -to Vout[2] +set_location_assignment PIN_62 -to Vout[3] +set_location_assignment PIN_71 -to Vout[4] +set_location_assignment PIN_68 -to Vout[5] +set_location_assignment PIN_58 -to Vout[6] +set_location_assignment PIN_57 -to Vout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Vout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Vout +set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout + +set_location_assignment PIN_4 -to CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE +set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE + +set_location_assignment PIN_8 -to nCS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS + +set_location_assignment PIN_2 -to nRWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE + +set_location_assignment PIN_5 -to nRAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS + +set_location_assignment PIN_3 -to nCAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS + +set_location_assignment PIN_6 -to BA[0] +set_location_assignment PIN_14 -to BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to BA +set_instance_assignment -name SLOW_SLEW_RATE ON -to BA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA + +set_location_assignment PIN_18 -to RA[0] +set_location_assignment PIN_20 -to RA[1] +set_location_assignment PIN_30 -to RA[2] +set_location_assignment PIN_27 -to RA[3] +set_location_assignment PIN_26 -to RA[4] +set_location_assignment PIN_29 -to RA[5] +set_location_assignment PIN_21 -to RA[6] +set_location_assignment PIN_19 -to RA[7] +set_location_assignment PIN_17 -to RA[8] +set_location_assignment PIN_15 -to RA[9] +set_location_assignment PIN_16 -to RA[10] +set_location_assignment PIN_7 -to RA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA +set_instance_assignment -name SLOW_SLEW_RATE ON -to RA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA + +set_location_assignment PIN_100 -to DQMH +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQMH +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH + +set_location_assignment PIN_98 -to DQML +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQML +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML + +set_location_assignment PIN_97 -to RD[0] +set_location_assignment PIN_90 -to RD[1] +set_location_assignment PIN_99 -to RD[2] +set_location_assignment PIN_89 -to RD[3] +set_location_assignment PIN_91 -to RD[4] +set_location_assignment PIN_92 -to RD[5] +set_location_assignment PIN_95 -to RD[6] +set_location_assignment PIN_96 -to RD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD +set_instance_assignment -name SLOW_SLEW_RATE ON -to RD +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD + +set_global_assignment -name QIP_FILE UFM.qip \ No newline at end of file diff --git a/cpld_maxv/New folder/RAM2E.qws b/cpld_maxv/New folder/RAM2E.qws new file mode 100644 index 0000000000000000000000000000000000000000..ab951d37e7f6f2841374dfb0d8482ab716dd7f0f GIT binary patch literal 407 zcmZusOA5kJ44n7;&_j3tH=UK1Z{V2%W9Y%s3>wq$LBsS_E-0d`2yK}<+Yk-$QiLKVDrL~nVTqG-R7)}prf^+XqZ`e<#?`FDbW_gdJLi&`Hg{nk{oa9n1exMZM332c>k>KLn)K;swTL BSjPYW literal 0 HcmV?d00001 diff --git a/cpld_maxv/New folder/RAM2E.v b/cpld_maxv/New folder/RAM2E.v new file mode 100644 index 0000000..5c553eb --- /dev/null +++ b/cpld_maxv/New folder/RAM2E.v @@ -0,0 +1,636 @@ +module RAM2E(C14M, PHI1, + nWE, nWE80, nEN80, nC07X, + Ain, Din, Dout, nDOE, Vout, nVOE, + CKE, nCS, nRAS, nCAS, nRWE, + BA, RA, RD, DQML, DQMH); + + /* Clocks */ + input C14M, PHI1; + + /* Control inputs */ + input nWE, nWE80, nEN80, nC07X; + + /* Delay for EN80 signal */ + //output DelayOut = 1'b0; + //input DelayIn; + wire EN80 = ~nEN80; + + /* Address Bus */ + input [7:0] Ain; // Multiplexed DRAM address input + + /* 6502 Data Bus */ + input [7:0] Din; // 6502 data bus inputs + reg DOEEN = 0; // 6502 data bus output enable from state machine + output nDOE = ~(EN80 & nWE & DOEEN); // 6502 data bus output enable + output reg [7:0] Dout; // 6502 data Bus output + + /* Video Data Bus */ + output nVOE = ~(~PHI1); /// Video data bus output enable + output reg [7:0] Vout; // Video data bus + + /* SDRAM */ + output reg CKE = 0; + output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1; + output reg [1:0] BA; + output reg [11:0] RA; + output reg DQML = 1, DQMH = 1; + wire RDOE = EN80 & ~nWE80; + inout [7:0] RD = RDOE ? Din[7:0] : 8'bZ; + + /* RAMWorks Bank Register and Capacity Mask */ + reg [7:0] RWBank = 0; // RAMWorks bank register + reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask + reg RWSel = 0; // RAMWorks bank register select + reg RWMaskSet = 0; // RAMWorks Mask register set flag + reg SetRWBankFF = 0; // Causes RWBank to be zeroed next RWSel access + + /* Command Sequence Detector */ + reg [2:0] CS = 0; // Command sequence state + reg [2:0] CmdTout = 0; // Command sequence timeout + + /* UFM Interface */ + reg [15:8] UFMD = 0; // *Parallel* UFM data register + reg ARCLK = 0; // UFM address register clock + // UFM address register data input tied to 0 + reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment + reg DRCLK = 0; // UFM data register clock + reg DRDIn = 0; // UFM data register input + reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address + reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy + reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy + wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous + wire RTPBusy; // 1 if real-time programming in progress. Asynchronous + wire DRDOut; // UFM data output + // UFM oscillator always enabled + wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz) + UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V) + .arclk (ARCLK), + .ardin (1'b0), + .arshft (ARShift), + .drclk (DRCLK), + .drdin (DRDIn), + .drshft (DRShift), + .erase (UFMErase), + .oscena (1'b1), + .program (UFMProgram), + .busy (UFMBusy), + .drdout (DRDOut), + .osc (UFMOsc), + .rtpbusy (RTPBusy)); + reg UFMBusyReg = 0; // UFMBusy registered to sync with C14M + reg RTPBusyReg = 0; // RTPBusy registered to sync with C14M + + /* UFM State & User Command Triggers */ + reg UFMInitDone = 0; // 1 if UFM initialization finished + reg UFMReqErase = 0; // 1 if UFM requires erase + reg UFMBitbang = 0; // Set by user command. Loads UFM outputs next RWSel + reg UFMPrgmEN = 0; // Set by user command. Programs UFM + reg UFMEraseEN = 0; // Set by user command. Erases UFM + reg DRCLKPulse = 0; // Set by user command. Causes DRCLK pulse next C14M + + /* State Counters */ + reg PHI1reg = 0; // Saved PHI1 at last rising clock edge + reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15 + reg [15:0] FS = 0; // Fast state counter + reg [3:0] S = 0; // IIe State counter + + /* State Counters */ + always @(posedge C14M) begin + // Increment fast state counter + FS <= FS+1; + // Synchronize Apple state counter to S1 when just entering PHI1 + PHI1reg <= PHI1; // Save old PHI1 + S <= (PHI1 & ~PHI1reg & Ready) ? 4'h1 : + S==4'h0 ? 4'h0 : + S==4'hF ? 4'hF : S+1; + end + + /* UFM Control */ + always @(posedge C14M) begin + // Synchronize asynchronous UFM signals + UFMBusyReg <= UFMBusy; + RTPBusyReg <= RTPBusy; + + if (S==4'h0) begin + if ((FS[15:13]==3'b101) | (FS[15:13]==3'b111 & UFMReqErase)) begin + // In states AXXX-BXXX and also EXXX-FXXX if erase/wrap req'd + // shift in 0's to address register + ARCLK <= FS[0]; // Clock address register + DRCLK <= 1'b0; // Don't clock data register + ARShift <= 1'b1; // Shift address registers + DRDIn <= 1'b0; // Don't care DRDIn + DRShift <= 1'b0; // Don't care DRDShift + end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4:1]==4'h4) begin + // In states CXXX-DXXX (substep 4) + // Xfer to data reg (repeat 256x 1x) + ARCLK <= 1'b0; // Don't clock address register + DRCLK <= FS[0]; // Clock data register + ARShift <= 1'b0; // Don't care ARShift + DRDIn <= 1'b0; // Don't care DRDIn + DRShift <= 1'b0; // Don't care DRShift + end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4]==1'b1) begin + // In states CXXX-DXXX (substeps 8-F) + // Save UFM D15-8, shift out D14-7 (repeat 256x 8x) + DRCLK <= FS[0]; // Clock data register + ARShift <= 1'b0; // ARShift is 0 because we want to increment + DRDIn <= 1'b0; // Don't care what to shift into data register + DRShift <= 1'b1; // Shift data register + // Shift into UFMD + if (FS[0]) UFMD[15:8] <= {UFMD[14:8], DRDOut}; + + // Compare and store mask + if (FS[4:1]==4'hF) begin + ARCLK <= FS[0]; // Clock address register to increment + // If byte is erased (0xFF, i.e. all 1's, is erased)... + if (UFMD[14:8]==7'b1111111 & DRDOut==1'b1) begin + // Current UFM address is where we want to store + UFMInitDone <= 1'b1; // Quit iterating + // Otherwise byte is valid setting (i.e. some bit is 0)... + end else begin + // Set RWMask, but if saved mask is 0x80, store ~0xFF + if (UFMD[14:8]==7'b1000000 & DRDOut==1'b0) begin + RWMask[7:0] <= {1'b1, ~7'h7F}; + end else RWMask[7:0] <= {UFMD[14], ~UFMD[13:8], ~DRDOut}; + // If last byte in sector... + if (FS[12:5]==8'hFF) begin + UFMReqErase <= 1'b1; // Mark need to erase + end + end + end else ARCLK <= 1'b0; // Don't clock address register + end else begin + ARCLK <= 1'b0; + DRCLK <= 1'b0; + ARShift <= 1'b0; + DRDIn <= 1'b0; + DRShift <= 1'b0; + end + + // Don't erase or program UFM during initialization + UFMErase <= 1'b0; + UFMProgram <= 1'b0; + // Keep DRCLK pulse control disabled during init + DRCLKPulse <= 1'b0; + end else begin + // Can only shift UFM data register now + ARCLK <= 1'b0; + ARShift <= 1'b0; + DRShift <= 1'b1; + + // UFM bitbang control + if (UFMBitbang & CS==3'h7 & RWSel & S==4'hC) begin + DRDIn <= Din[6]; + DRCLKPulse <= Din[7]; + DRCLK <= 1'b0; + end else begin + DRCLKPulse <= 1'b0; + DRCLK <= DRCLKPulse; + end + + // Set capacity mask + if (RWMaskSet & RWSel & S==4'hC) RWMask[7:0] <= {Din[7], ~Din[6:0]}; + + // UFM programming sequence + if (UFMPrgmEN | UFMEraseEN) begin + if (~UFMBusyReg & ~RTPBusyReg) begin + if (UFMReqErase | UFMEraseEN) UFMErase <= 1'b1; + else if (UFMPrgmEN) UFMProgram <= 1'b1; + end else if (UFMBusyReg) UFMReqErase <= 1'b0; + end + end + end + + /* SDRAM Control */ + always @(posedge C14M) begin + if (S==4'h0) begin + // SDRAM initialization + if (FS[15:0]==16'hFFC0) begin + // Precharge All + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b0; + RA[10] <= 1'b1; // "all" + end else if (FS[15:4]==16'hFFD & FS[0]==1'b0) begin // Repeat 8x + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end else if (FS[15:0]==16'hFFE8) begin + // Set Mode Register + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b0; + RA[10] <= 1'b0; // Reserved in mode register + end else if (FS[15:4]==12'hFFF & FS[0]==1'b0) begin // Repeat 8x + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end else begin // Otherwise send no-op + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end + // Enable SDRAM clock after 65,280 cycles (~4.56ms) + CKE <= FS[15:8] == 8'hFF; + + // Mode register contents + BA[1:0] <= 2'b00; // Reserved + RA[11] <= 1'b0; // Reserved + // RA[10] set above ^ + RA[9] <= 1'b1; // "1" for single write mode + RA[8] <= 1'b0; // Reserved + RA[7] <= 1'b0; // "0" for not test mode + RA[6:4] <= 3'b010; // "2" for CAS latency 2 + RA[3] <= 1'b0; // "0" for sequential burst (not used) + RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst) + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + + // Begin normal operation after 128k init cycles (~9.15ms) + if (FS == 16'hFFFF) Ready <= 1'b1; + end else if (S==4'h1) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h2) begin + // Enable clock + CKE <= 1'b1; + + // Activate + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // SDRAM bank 0, high-order row address is 0 + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Row address is as previously latched + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h3) begin + // Enable clock + CKE <= 1'b1; + + // Read + nCS <= 1'b0; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= 1'b1; + + // SDRAM bank 0, RA[11,9:8] don't care + BA <= 2'b00; + RA[11] <= 1'b0; + RA[10] <= 1'b1; // (A10 set to auto-precharge) + RA[9] <= 1'b0; + RA[8] <= 1'b0; + // Latch column address for read command + RA[7:0] <= Ain[7:0]; + + // Read low byte (high byte is +4MB in ramworks) + DQML <= 1'b0; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h4) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h5) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h6) begin + // Enable clock + CKE <= 1'b1; + + if (FS[5:4]==0) begin + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + end else begin + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + end + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h7) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for activate command + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h8) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // Activate if '245 output enabled + nCS <= nEN80; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // SDRAM bank, RA[11:8] determine by RamWorks bank + BA <= RWBank[5:4]; + RA[11:8] <= RWBank[3:0]; + // Row address is as previously latched + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h9) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // Read/Write if '245 output enabled + nCS <= nEN80; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= nWE80; + + // SDRAM bank still determined by RamWorks, RA[11,9:8] don't care + BA <= RWBank[5:4]; + RA[11] <= 1'b0; + RA[10] <= 1'b1; // (A10 set to auto-precharge) + RA[9] <= 1'b0; + RA[8] <= RWBank[7]; + // Latch column address for R/W command + RA[7:0] <= Ain[7:0]; + + // Latch RAMWorks low nybble write select using old row address + RWSel <= RA[0] & ~RA[3] & ~nWE & ~nC07X; + + // Mask according to RAMWorks bank (high byte is +4MB) + DQML <= RWBank[6]; + DQMH <= ~RWBank[6]; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'hA) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'hB) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hC) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + + // RAMWorks Bank Register Select + if (RWSel) begin + // Latch RAMWorks bank if accessed + if (SetRWBankFF) RWBank <= 8'hFF; + else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]}; + + // Recognize command sequence and advance CS state + if ((CS==3'h0 & Din[7:0]==8'hFF) | + (CS==3'h1 & Din[7:0]==8'h00) | + (CS==3'h2 & Din[7:0]==8'h55) | + (CS==3'h3 & Din[7:0]==8'hAA) | + (CS==3'h4 & Din[7:0]==8'hC1) | + (CS==3'h5 & Din[7:0]==8'hAD) | + CS==3'h6 | CS==3'h7) CS <= CS+1; + else CS <= 0; // Back to beginning if it's not right + + if (CS==3'h6) begin // Recognize and submit command in CS6 + SetRWBankFF <= Din[7:0]==8'hFF; + if (Din[7:0]==8'hEF) UFMPrgmEN <= 1'b1; + if (Din[7:0]==8'hEE) UFMEraseEN <= 1'b1; + UFMBitbang <= Din[7:0]==8'hEA; + RWMaskSet <= Din[7:0]==8'hE0; + end else begin // Reset command triggers + SetRWBankFF <= 1'b0; + UFMBitbang <= 1'b0; + RWMaskSet <= 1'b0; + end + + CmdTout <= 0; // Reset command timeout if RWSel accessed + end else begin + CmdTout <= CmdTout+1; // Increment command timeout + // If command sequence times out, reset sequence state + if (CmdTout==3'h7) CS <= 0; + end + end else if (S==4'hD) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hE) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for next video read + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hF) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for next video read + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end + end + always @(negedge C14M) begin + // Latch video and read data outputs + if (S==4'h6) Vout[7:0] <= RD[7:0]; + if (S==4'hC) Dout[7:0] <= RD[7:0]; + end +endmodule diff --git a/cpld_maxv/New folder/UFM.qip b/cpld_maxv/New folder/UFM.qip new file mode 100644 index 0000000..e2d8458 --- /dev/null +++ b/cpld_maxv/New folder/UFM.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"] diff --git a/cpld_maxv/New folder/UFM.v b/cpld_maxv/New folder/UFM.v new file mode 100644 index 0000000..ec5b564 --- /dev/null +++ b/cpld_maxv/New folder/UFM.v @@ -0,0 +1,268 @@ +// megafunction wizard: %ALTUFM_NONE% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTUFM_NONE + +// ============================================================ +// File Name: UFM.v +// Megafunction Name(s): +// ALTUFM_NONE +// +// Simulation Library Files(s): +// maxii +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy +//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + +//synthesis_resources = maxii_ufm 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module UFM_altufm_none_a7r + ( + arclk, + ardin, + arshft, + busy, + drclk, + drdin, + drdout, + drshft, + erase, + osc, + oscena, + program, + rtpbusy) ; + input arclk; + input ardin; + input arshft; + output busy; + input drclk; + input drdin; + output drdout; + input drshft; + input erase; + output osc; + input oscena; + input program; + output rtpbusy; + + wire wire_maxii_ufm_block1_bgpbusy; + wire wire_maxii_ufm_block1_busy; + wire wire_maxii_ufm_block1_drdout; + wire wire_maxii_ufm_block1_osc; + wire ufm_arclk; + wire ufm_ardin; + wire ufm_arshft; + wire ufm_bgpbusy; + wire ufm_busy; + wire ufm_drclk; + wire ufm_drdin; + wire ufm_drdout; + wire ufm_drshft; + wire ufm_erase; + wire ufm_osc; + wire ufm_oscena; + wire ufm_program; + + maxii_ufm maxii_ufm_block1 + ( + .arclk(ufm_arclk), + .ardin(ufm_ardin), + .arshft(ufm_arshft), + .bgpbusy(wire_maxii_ufm_block1_bgpbusy), + .busy(wire_maxii_ufm_block1_busy), + .drclk(ufm_drclk), + .drdin(ufm_drdin), + .drdout(wire_maxii_ufm_block1_drdout), + .drshft(ufm_drshft), + .erase(ufm_erase), + .osc(wire_maxii_ufm_block1_osc), + .oscena(ufm_oscena), + .program(ufm_program) + // synopsys translate_off + , + .ctrl_bgpbusy(1'b0), + .devclrn(1'b1), + .devpor(1'b1), + .sbdin(1'b0), + .sbdout() + // synopsys translate_on + ); + defparam + maxii_ufm_block1.address_width = 9, + maxii_ufm_block1.erase_time = 500000000, + maxii_ufm_block1.init_file = "RAM2E.mif", + maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem2 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem3 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem4 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem5 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem6 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem7 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem8 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.osc_sim_setting = 180000, + maxii_ufm_block1.program_time = 1600000, + maxii_ufm_block1.lpm_type = "maxii_ufm"; + assign + busy = ufm_busy, + drdout = ufm_drdout, + osc = ufm_osc, + rtpbusy = ufm_bgpbusy, + ufm_arclk = arclk, + ufm_ardin = ardin, + ufm_arshft = arshft, + ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy, + ufm_busy = wire_maxii_ufm_block1_busy, + ufm_drclk = drclk, + ufm_drdin = drdin, + ufm_drdout = wire_maxii_ufm_block1_drdout, + ufm_drshft = drshft, + ufm_erase = erase, + ufm_osc = wire_maxii_ufm_block1_osc, + ufm_oscena = oscena, + ufm_program = program; +endmodule //UFM_altufm_none_a7r +//VALID FILE + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module UFM ( + arclk, + ardin, + arshft, + drclk, + drdin, + drshft, + erase, + oscena, + program, + busy, + drdout, + osc, + rtpbusy); + + input arclk; + input ardin; + input arshft; + input drclk; + input drdin; + input drshft; + input erase; + input oscena; + input program; + output busy; + output drdout; + output osc; + output rtpbusy; + + wire sub_wire0; + wire sub_wire1; + wire sub_wire2; + wire sub_wire3; + wire osc = sub_wire0; + wire rtpbusy = sub_wire1; + wire drdout = sub_wire2; + wire busy = sub_wire3; + + UFM_altufm_none_a7r UFM_altufm_none_a7r_component ( + .arshft (arshft), + .drclk (drclk), + .erase (erase), + .program (program), + .arclk (arclk), + .drdin (drdin), + .oscena (oscena), + .ardin (ardin), + .drshft (drshft), + .osc (sub_wire0), + .rtpbusy (sub_wire1), + .drdout (sub_wire2), + .busy (sub_wire3)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II" +// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II" +// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2E.mif" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none" +// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000" +// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000" +// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9" +// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk" +// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0 +// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin" +// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0 +// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft" +// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0 +// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy" +// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0 +// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk" +// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0 +// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin" +// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0 +// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout" +// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0 +// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft" +// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0 +// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase" +// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0 +// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc" +// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0 +// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena" +// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0 +// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program" +// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0 +// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy" +// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE +// Retrieval info: LIB_FILE: maxii diff --git a/cpld_maxv/RAM2E - 16MB.mif b/cpld_maxv/RAM2E - 16MB.mif new file mode 100644 index 0000000..5b546ed --- /dev/null +++ b/cpld_maxv/RAM2E - 16MB.mif @@ -0,0 +1,26 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=16; +DEPTH=512; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 000 : 8080; + [001..1FF] : FFFF; +END; diff --git a/cpld_maxv/RAM2E - AF.mif b/cpld_maxv/RAM2E - AF.mif new file mode 100644 index 0000000..fdefd00 --- /dev/null +++ b/cpld_maxv/RAM2E - AF.mif @@ -0,0 +1,273 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=16; +DEPTH=512; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 000 : 0000; + 001 : 0101; + 002 : 0202; + 003 : 0303; + 004 : 0404; + 005 : 0505; + 006 : 0606; + 007 : 0707; + 008 : 0808; + 009 : 0909; + 00A : 0A0A; + 00B : 0B0B; + 00C : 0C0C; + 00D : 0D0D; + 00E : 0E0E; + 00F : 0F0F; + 010 : 1010; + 011 : 1111; + 012 : 1212; + 013 : 1313; + 014 : 1414; + 015 : 1515; + 016 : 1616; + 017 : 1717; + 018 : 1818; + 019 : 1919; + 01A : 1A1A; + 01B : 1B1B; + 01C : 1C1C; + 01D : 1D1D; + 01E : 1E1E; + 01F : 1F1F; + 020 : 2020; + 021 : 2121; + 022 : 2222; + 023 : 2323; + 024 : 2424; + 025 : 2525; + 026 : 2626; + 027 : 2727; + 028 : 2828; + 029 : 2929; + 02A : 2A2A; + 02B : 2B2B; + 02C : 2C2C; + 02D : 2D2D; + 02E : 2E2E; + 02F : 2F2F; + 030 : 3030; + 031 : 3131; + 032 : 3232; + 033 : 3333; + 034 : 3434; + 035 : 3535; + 036 : 3636; + 037 : 3737; + 038 : 3838; + 039 : 3939; + 03A : 3A3A; + 03B : 3B3B; + 03C : 3C3C; + 03D : 3D3D; + 03E : 3E3E; + 03F : 3F3F; + 040 : 4040; + 041 : 4141; + 042 : 4242; + 043 : 4343; + 044 : 4444; + 045 : 4545; + 046 : 4646; + 047 : 4747; + 048 : 4848; + 049 : 4949; + 04A : 4A4A; + 04B : 4B4B; + 04C : 4C4C; + 04D : 4D4D; + 04E : 4E4E; + 04F : 4F4F; + 050 : 5050; + 051 : 5151; + 052 : 5252; + 053 : 5353; + 054 : 5454; + 055 : 5555; + 056 : 5656; + 057 : 5757; + 058 : 5858; + 059 : 5959; + 05A : 5A5A; + 05B : 5B5B; + 05C : 5C5C; + 05D : 5D5D; + 05E : 5E5E; + 05F : 5F5F; + 060 : 6060; + 061 : 6161; + 062 : 6262; + 063 : 6363; + 064 : 6464; + 065 : 6565; + 066 : 6666; + 067 : 6767; + 068 : 6868; + 069 : 6969; + 06A : 6A6A; + 06B : 6B6B; + 06C : 6C6C; + 06D : 6D6D; + 06E : 6E6E; + 06F : 6F6F; + 070 : 7070; + 071 : 7171; + 072 : 7272; + 073 : 7373; + 074 : 7474; + 075 : 7575; + 076 : 7676; + 077 : 7777; + 078 : 7878; + 079 : 7979; + 07A : 7A7A; + 07B : 7B7B; + 07C : 7C7C; + 07D : 7D7D; + 07E : 7E7E; + 07F : 7F7F; + 080 : 8080; + 081 : 8181; + 082 : 8282; + 083 : 8383; + 084 : 8484; + 085 : 8585; + 086 : 8686; + 087 : 8787; + 088 : 8888; + 089 : 8989; + 08A : 8A8A; + 08B : 8B8B; + 08C : 8C8C; + 08D : 8D8D; + 08E : 8E8E; + 08F : 8F8F; + 090 : 9090; + 091 : 9191; + 092 : 9292; + 093 : 9393; + 094 : 9494; + 095 : 9595; + 096 : 9696; + 097 : 9797; + 098 : 9898; + 099 : 9999; + 09A : 9A9A; + 09B : 9B9B; + 09C : 9C9C; + 09D : 9D9D; + 09E : 9E9E; + 09F : 9F9F; + 0A0 : A0A0; + 0A1 : A1A1; + 0A2 : A2A2; + 0A3 : A3A3; + 0A4 : A4A4; + 0A5 : A5A5; + 0A6 : A6A6; + 0A7 : A7A7; + 0A8 : A8A8; + 0A9 : A9A9; + 0AA : AAAA; + 0AB : ABAB; + 0AC : ACAC; + 0AD : ADAD; + 0AE : AEAE; + 0AF : AFAF; + 0B0 : B0B0; + 0B1 : B1B1; + 0B2 : B2B2; + 0B3 : B3B3; + 0B4 : B4B4; + 0B5 : B5B5; + 0B6 : B6B6; + 0B7 : B7B7; + 0B8 : B8B8; + 0B9 : B9B9; + 0BA : BABA; + 0BB : BBBB; + 0BC : BCBC; + 0BD : BDBD; + 0BE : BEBE; + 0BF : BFBF; + 0C0 : C0C0; + 0C1 : C1C1; + 0C2 : C2C2; + 0C3 : C3C3; + 0C4 : C4C4; + 0C5 : C5C5; + 0C6 : C6C6; + 0C7 : C7C7; + 0C8 : C8C8; + 0C9 : C9C9; + 0CA : CACA; + 0CB : CBCB; + 0CC : CCCC; + 0CD : CDCD; + 0CE : CECE; + 0CF : CFCF; + 0D0 : D0D0; + 0D1 : D1D1; + 0D2 : D2D2; + 0D3 : D3D3; + 0D4 : D4D4; + 0D5 : D5D5; + 0D6 : D6D6; + 0D7 : D7D7; + 0D8 : D8D8; + 0D9 : D9D9; + 0DA : DADA; + 0DB : DBDB; + 0DC : DCDC; + 0DD : DDDD; + 0DE : DEDE; + 0DF : DFDF; + 0E0 : E0E0; + 0E1 : E1E1; + 0E2 : E2E2; + 0E3 : E3E3; + 0E4 : E4E4; + 0E5 : E5E5; + 0E6 : E6E6; + 0E7 : E7E7; + 0E8 : E8E8; + 0E9 : E9E9; + 0EA : EAEA; + 0EB : EBEB; + 0EC : ECEC; + 0ED : EDED; + 0EE : EEEE; + 0EF : EFEF; + 0F0 : F0F0; + 0F1 : F1F1; + 0F2 : F2F2; + 0F3 : F3F3; + 0F4 : F4F4; + 0F5 : F5F5; + 0F6 : F6F6; + 0F7 : 7F7F; + [0F8..1FF] : FFFF; +END; diff --git a/cpld_maxv/RAM2E - E.mif b/cpld_maxv/RAM2E - E.mif new file mode 100644 index 0000000..80fa213 --- /dev/null +++ b/cpld_maxv/RAM2E - E.mif @@ -0,0 +1,25 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=16; +DEPTH=512; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + [000..1FF] : FFFF; +END; diff --git a/cpld_maxv/RAM2E - F.mif b/cpld_maxv/RAM2E - F.mif new file mode 100644 index 0000000..63b1e81 --- /dev/null +++ b/cpld_maxv/RAM2E - F.mif @@ -0,0 +1,281 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=16; +DEPTH=512; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 000 : 0000; + 001 : 0101; + 002 : 0202; + 003 : 0303; + 004 : 0404; + 005 : 0505; + 006 : 0606; + 007 : 0707; + 008 : 0808; + 009 : 0909; + 00A : 0A0A; + 00B : 0B0B; + 00C : 0C0C; + 00D : 0D0D; + 00E : 0E0E; + 00F : 0F0F; + 010 : 1010; + 011 : 1111; + 012 : 1212; + 013 : 1313; + 014 : 1414; + 015 : 1515; + 016 : 1616; + 017 : 1717; + 018 : 1818; + 019 : 1919; + 01A : 1A1A; + 01B : 1B1B; + 01C : 1C1C; + 01D : 1D1D; + 01E : 1E1E; + 01F : 1F1F; + 020 : 2020; + 021 : 2121; + 022 : 2222; + 023 : 2323; + 024 : 2424; + 025 : 2525; + 026 : 2626; + 027 : 2727; + 028 : 2828; + 029 : 2929; + 02A : 2A2A; + 02B : 2B2B; + 02C : 2C2C; + 02D : 2D2D; + 02E : 2E2E; + 02F : 2F2F; + 030 : 3030; + 031 : 3131; + 032 : 3232; + 033 : 3333; + 034 : 3434; + 035 : 3535; + 036 : 3636; + 037 : 3737; + 038 : 3838; + 039 : 3939; + 03A : 3A3A; + 03B : 3B3B; + 03C : 3C3C; + 03D : 3D3D; + 03E : 3E3E; + 03F : 3F3F; + 040 : 4040; + 041 : 4141; + 042 : 4242; + 043 : 4343; + 044 : 4444; + 045 : 4545; + 046 : 4646; + 047 : 4747; + 048 : 4848; + 049 : 4949; + 04A : 4A4A; + 04B : 4B4B; + 04C : 4C4C; + 04D : 4D4D; + 04E : 4E4E; + 04F : 4F4F; + 050 : 5050; + 051 : 5151; + 052 : 5252; + 053 : 5353; + 054 : 5454; + 055 : 5555; + 056 : 5656; + 057 : 5757; + 058 : 5858; + 059 : 5959; + 05A : 5A5A; + 05B : 5B5B; + 05C : 5C5C; + 05D : 5D5D; + 05E : 5E5E; + 05F : 5F5F; + 060 : 6060; + 061 : 6161; + 062 : 6262; + 063 : 6363; + 064 : 6464; + 065 : 6565; + 066 : 6666; + 067 : 6767; + 068 : 6868; + 069 : 6969; + 06A : 6A6A; + 06B : 6B6B; + 06C : 6C6C; + 06D : 6D6D; + 06E : 6E6E; + 06F : 6F6F; + 070 : 7070; + 071 : 7171; + 072 : 7272; + 073 : 7373; + 074 : 7474; + 075 : 7575; + 076 : 7676; + 077 : 7777; + 078 : 7878; + 079 : 7979; + 07A : 7A7A; + 07B : 7B7B; + 07C : 7C7C; + 07D : 7D7D; + 07E : 7E7E; + 07F : 7F7F; + 080 : 8080; + 081 : 8181; + 082 : 8282; + 083 : 8383; + 084 : 8484; + 085 : 8585; + 086 : 8686; + 087 : 8787; + 088 : 8888; + 089 : 8989; + 08A : 8A8A; + 08B : 8B8B; + 08C : 8C8C; + 08D : 8D8D; + 08E : 8E8E; + 08F : 8F8F; + 090 : 9090; + 091 : 9191; + 092 : 9292; + 093 : 9393; + 094 : 9494; + 095 : 9595; + 096 : 9696; + 097 : 9797; + 098 : 9898; + 099 : 9999; + 09A : 9A9A; + 09B : 9B9B; + 09C : 9C9C; + 09D : 9D9D; + 09E : 9E9E; + 09F : 9F9F; + 0A0 : A0A0; + 0A1 : A1A1; + 0A2 : A2A2; + 0A3 : A3A3; + 0A4 : A4A4; + 0A5 : A5A5; + 0A6 : A6A6; + 0A7 : A7A7; + 0A8 : A8A8; + 0A9 : A9A9; + 0AA : AAAA; + 0AB : ABAB; + 0AC : ACAC; + 0AD : ADAD; + 0AE : AEAE; + 0AF : AFAF; + 0B0 : B0B0; + 0B1 : B1B1; + 0B2 : B2B2; + 0B3 : B3B3; + 0B4 : B4B4; + 0B5 : B5B5; + 0B6 : B6B6; + 0B7 : B7B7; + 0B8 : B8B8; + 0B9 : B9B9; + 0BA : BABA; + 0BB : BBBB; + 0BC : BCBC; + 0BD : BDBD; + 0BE : BEBE; + 0BF : BFBF; + 0C0 : C0C0; + 0C1 : C1C1; + 0C2 : C2C2; + 0C3 : C3C3; + 0C4 : C4C4; + 0C5 : C5C5; + 0C6 : C6C6; + 0C7 : C7C7; + 0C8 : C8C8; + 0C9 : C9C9; + 0CA : CACA; + 0CB : CBCB; + 0CC : CCCC; + 0CD : CDCD; + 0CE : CECE; + 0CF : CFCF; + 0D0 : D0D0; + 0D1 : D1D1; + 0D2 : D2D2; + 0D3 : D3D3; + 0D4 : D4D4; + 0D5 : D5D5; + 0D6 : D6D6; + 0D7 : D7D7; + 0D8 : D8D8; + 0D9 : D9D9; + 0DA : DADA; + 0DB : DBDB; + 0DC : DCDC; + 0DD : DDDD; + 0DE : DEDE; + 0DF : DFDF; + 0E0 : E0E0; + 0E1 : E1E1; + 0E2 : E2E2; + 0E3 : E3E3; + 0E4 : E4E4; + 0E5 : E5E5; + 0E6 : E6E6; + 0E7 : E7E7; + 0E8 : E8E8; + 0E9 : E9E9; + 0EA : EAEA; + 0EB : EBEB; + 0EC : ECEC; + 0ED : EDED; + 0EE : EEEE; + 0EF : EFEF; + 0F0 : F0F0; + 0F1 : F1F1; + 0F2 : F2F2; + 0F3 : F3F3; + 0F4 : F4F4; + 0F5 : F5F5; + 0F6 : F6F6; + 0F7 : 7F7F; + 0F8 : F8F8; + 0F9 : F9F9; + 0FA : FAFA; + 0FB : FBFB; + 0FC : FCFC; + 0FD : FDFD; + 0FE : FEFE; + 0FF : 0F0F; + [100..1FF] : FFFF; +END; diff --git a/cpld_maxv/RAM2E.mif b/cpld_maxv/RAM2E.mif new file mode 100644 index 0000000..80fa213 --- /dev/null +++ b/cpld_maxv/RAM2E.mif @@ -0,0 +1,25 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=16; +DEPTH=512; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + [000..1FF] : FFFF; +END; diff --git a/cpld_maxv/RAM2E.qpf b/cpld_maxv/RAM2E.qpf new file mode 100644 index 0000000..100c9bd --- /dev/null +++ b/cpld_maxv/RAM2E.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 22:58:44 May 05, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "22:58:44 May 05, 2020" + +# Revisions + +PROJECT_REVISION = "RAM2E" diff --git a/cpld_maxv/RAM2E.qsf b/cpld_maxv/RAM2E.qsf new file mode 100644 index 0000000..43d7247 --- /dev/null +++ b/cpld_maxv/RAM2E.qsf @@ -0,0 +1,259 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 22:58:44 May 05, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# RAM2E_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX V" +set_global_assignment -name DEVICE 5M240ZT100C5 +set_global_assignment -name TOP_LEVEL_ENTITY RAM2E +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:58:44 MAY 05, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" +set_global_assignment -name VERILOG_FILE RAM2E.v +set_global_assignment -name SDC_FILE constraints.sdc +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name SAFE_STATE_MACHINE ON +set_global_assignment -name PARALLEL_SYNTHESIS OFF +set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name MIF_FILE RAM2E.mif +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" + +set_location_assignment PIN_12 -to C14M +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C14M + +set_location_assignment PIN_37 -to PHI1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI1 +set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to PHI1 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI1 + +set_location_assignment PIN_51 -to nWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE + +set_location_assignment PIN_28 -to nEN80 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nEN80 +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nEN80 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80 + +set_location_assignment PIN_33 -to nWE80 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80 +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80 + +set_location_assignment PIN_52 -to nC07X +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nC07X +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nC07X +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nC07X + +set_location_assignment PIN_56 -to Ain[0] +set_location_assignment PIN_54 -to Ain[1] +set_location_assignment PIN_43 -to Ain[2] +set_location_assignment PIN_47 -to Ain[3] +set_location_assignment PIN_44 -to Ain[4] +set_location_assignment PIN_34 -to Ain[5] +set_location_assignment PIN_39 -to Ain[6] +set_location_assignment PIN_53 -to Ain[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Ain +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Ain +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Ain + +set_location_assignment PIN_38 -to Din[0] +set_location_assignment PIN_40 -to Din[1] +set_location_assignment PIN_42 -to Din[2] +set_location_assignment PIN_41 -to Din[3] +set_location_assignment PIN_48 -to Din[4] +set_location_assignment PIN_49 -to Din[5] +set_location_assignment PIN_36 -to Din[6] +set_location_assignment PIN_35 -to Din[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Din +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Din + +set_location_assignment PIN_55 -to nDOE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE + +set_location_assignment PIN_77 -to Dout[0] +set_location_assignment PIN_76 -to Dout[1] +set_location_assignment PIN_74 -to Dout[2] +set_location_assignment PIN_75 -to Dout[3] +set_location_assignment PIN_73 -to Dout[4] +set_location_assignment PIN_72 -to Dout[5] +set_location_assignment PIN_84 -to Dout[6] +set_location_assignment PIN_85 -to Dout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout +set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout + +set_location_assignment PIN_50 -to nVOE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE + +set_location_assignment PIN_70 -to Vout[0] +set_location_assignment PIN_67 -to Vout[1] +set_location_assignment PIN_69 -to Vout[2] +set_location_assignment PIN_62 -to Vout[3] +set_location_assignment PIN_71 -to Vout[4] +set_location_assignment PIN_68 -to Vout[5] +set_location_assignment PIN_58 -to Vout[6] +set_location_assignment PIN_57 -to Vout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Vout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Vout +set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout + +set_location_assignment PIN_4 -to CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE +set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE + +set_location_assignment PIN_8 -to nCS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS + +set_location_assignment PIN_2 -to nRWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE + +set_location_assignment PIN_5 -to nRAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS + +set_location_assignment PIN_3 -to nCAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS + +set_location_assignment PIN_6 -to BA[0] +set_location_assignment PIN_14 -to BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to BA +set_instance_assignment -name SLOW_SLEW_RATE ON -to BA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA + +set_location_assignment PIN_18 -to RA[0] +set_location_assignment PIN_20 -to RA[1] +set_location_assignment PIN_30 -to RA[2] +set_location_assignment PIN_27 -to RA[3] +set_location_assignment PIN_26 -to RA[4] +set_location_assignment PIN_29 -to RA[5] +set_location_assignment PIN_21 -to RA[6] +set_location_assignment PIN_19 -to RA[7] +set_location_assignment PIN_17 -to RA[8] +set_location_assignment PIN_15 -to RA[9] +set_location_assignment PIN_16 -to RA[10] +set_location_assignment PIN_7 -to RA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA +set_instance_assignment -name SLOW_SLEW_RATE ON -to RA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA + +set_location_assignment PIN_100 -to DQMH +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQMH +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH + +set_location_assignment PIN_98 -to DQML +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQML +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML + +set_location_assignment PIN_97 -to RD[0] +set_location_assignment PIN_90 -to RD[1] +set_location_assignment PIN_99 -to RD[2] +set_location_assignment PIN_89 -to RD[3] +set_location_assignment PIN_91 -to RD[4] +set_location_assignment PIN_92 -to RD[5] +set_location_assignment PIN_95 -to RD[6] +set_location_assignment PIN_96 -to RD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD +set_instance_assignment -name SLOW_SLEW_RATE ON -to RD +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD + +set_global_assignment -name QIP_FILE UFM.qip \ No newline at end of file diff --git a/cpld_maxv/RAM2E.qws b/cpld_maxv/RAM2E.qws new file mode 100644 index 0000000000000000000000000000000000000000..9f0f8e8b91b9cde16083581c112ecaad90c281ca GIT binary patch literal 613 zcmbV}O-chn5QX22KV<0vvIrs)gpnjha48X7xsq%ILB>pvh9pi%MqG&3F?bd?ZoPn) zFh;*>S~rTI)zn{4)vH%M`*nRvRYRqks??coRA{0B*_gYYTquh0N4iy}UA0m3nQ|rC zA#YKasL9FDgwBTceAFOnp((XFw#{ks?d}~h?C1gGqc_X!3VD&@**qqSUNP(H(t8e1 zry2}%>;e7?&d%Fu=!|ESpUQ);oEQrEa?lFCG7kw(Hei#z9Ec^D9bMx~k6dGB!5K0) z)x=5-)>E|@S<@k{j-{=nr@>D}M$ELXWA$~R%l}OBF9FDgCpG?^Ds|teE^%cnw%D-< fJC6PivmHG@J%0Tqo1@hZ?|AP+3=gz0wLI1b!GmZw literal 0 HcmV?d00001 diff --git a/cpld_maxv/RAM2E.v b/cpld_maxv/RAM2E.v new file mode 100644 index 0000000..5c553eb --- /dev/null +++ b/cpld_maxv/RAM2E.v @@ -0,0 +1,636 @@ +module RAM2E(C14M, PHI1, + nWE, nWE80, nEN80, nC07X, + Ain, Din, Dout, nDOE, Vout, nVOE, + CKE, nCS, nRAS, nCAS, nRWE, + BA, RA, RD, DQML, DQMH); + + /* Clocks */ + input C14M, PHI1; + + /* Control inputs */ + input nWE, nWE80, nEN80, nC07X; + + /* Delay for EN80 signal */ + //output DelayOut = 1'b0; + //input DelayIn; + wire EN80 = ~nEN80; + + /* Address Bus */ + input [7:0] Ain; // Multiplexed DRAM address input + + /* 6502 Data Bus */ + input [7:0] Din; // 6502 data bus inputs + reg DOEEN = 0; // 6502 data bus output enable from state machine + output nDOE = ~(EN80 & nWE & DOEEN); // 6502 data bus output enable + output reg [7:0] Dout; // 6502 data Bus output + + /* Video Data Bus */ + output nVOE = ~(~PHI1); /// Video data bus output enable + output reg [7:0] Vout; // Video data bus + + /* SDRAM */ + output reg CKE = 0; + output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1; + output reg [1:0] BA; + output reg [11:0] RA; + output reg DQML = 1, DQMH = 1; + wire RDOE = EN80 & ~nWE80; + inout [7:0] RD = RDOE ? Din[7:0] : 8'bZ; + + /* RAMWorks Bank Register and Capacity Mask */ + reg [7:0] RWBank = 0; // RAMWorks bank register + reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask + reg RWSel = 0; // RAMWorks bank register select + reg RWMaskSet = 0; // RAMWorks Mask register set flag + reg SetRWBankFF = 0; // Causes RWBank to be zeroed next RWSel access + + /* Command Sequence Detector */ + reg [2:0] CS = 0; // Command sequence state + reg [2:0] CmdTout = 0; // Command sequence timeout + + /* UFM Interface */ + reg [15:8] UFMD = 0; // *Parallel* UFM data register + reg ARCLK = 0; // UFM address register clock + // UFM address register data input tied to 0 + reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment + reg DRCLK = 0; // UFM data register clock + reg DRDIn = 0; // UFM data register input + reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address + reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy + reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy + wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous + wire RTPBusy; // 1 if real-time programming in progress. Asynchronous + wire DRDOut; // UFM data output + // UFM oscillator always enabled + wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz) + UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V) + .arclk (ARCLK), + .ardin (1'b0), + .arshft (ARShift), + .drclk (DRCLK), + .drdin (DRDIn), + .drshft (DRShift), + .erase (UFMErase), + .oscena (1'b1), + .program (UFMProgram), + .busy (UFMBusy), + .drdout (DRDOut), + .osc (UFMOsc), + .rtpbusy (RTPBusy)); + reg UFMBusyReg = 0; // UFMBusy registered to sync with C14M + reg RTPBusyReg = 0; // RTPBusy registered to sync with C14M + + /* UFM State & User Command Triggers */ + reg UFMInitDone = 0; // 1 if UFM initialization finished + reg UFMReqErase = 0; // 1 if UFM requires erase + reg UFMBitbang = 0; // Set by user command. Loads UFM outputs next RWSel + reg UFMPrgmEN = 0; // Set by user command. Programs UFM + reg UFMEraseEN = 0; // Set by user command. Erases UFM + reg DRCLKPulse = 0; // Set by user command. Causes DRCLK pulse next C14M + + /* State Counters */ + reg PHI1reg = 0; // Saved PHI1 at last rising clock edge + reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15 + reg [15:0] FS = 0; // Fast state counter + reg [3:0] S = 0; // IIe State counter + + /* State Counters */ + always @(posedge C14M) begin + // Increment fast state counter + FS <= FS+1; + // Synchronize Apple state counter to S1 when just entering PHI1 + PHI1reg <= PHI1; // Save old PHI1 + S <= (PHI1 & ~PHI1reg & Ready) ? 4'h1 : + S==4'h0 ? 4'h0 : + S==4'hF ? 4'hF : S+1; + end + + /* UFM Control */ + always @(posedge C14M) begin + // Synchronize asynchronous UFM signals + UFMBusyReg <= UFMBusy; + RTPBusyReg <= RTPBusy; + + if (S==4'h0) begin + if ((FS[15:13]==3'b101) | (FS[15:13]==3'b111 & UFMReqErase)) begin + // In states AXXX-BXXX and also EXXX-FXXX if erase/wrap req'd + // shift in 0's to address register + ARCLK <= FS[0]; // Clock address register + DRCLK <= 1'b0; // Don't clock data register + ARShift <= 1'b1; // Shift address registers + DRDIn <= 1'b0; // Don't care DRDIn + DRShift <= 1'b0; // Don't care DRDShift + end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4:1]==4'h4) begin + // In states CXXX-DXXX (substep 4) + // Xfer to data reg (repeat 256x 1x) + ARCLK <= 1'b0; // Don't clock address register + DRCLK <= FS[0]; // Clock data register + ARShift <= 1'b0; // Don't care ARShift + DRDIn <= 1'b0; // Don't care DRDIn + DRShift <= 1'b0; // Don't care DRShift + end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4]==1'b1) begin + // In states CXXX-DXXX (substeps 8-F) + // Save UFM D15-8, shift out D14-7 (repeat 256x 8x) + DRCLK <= FS[0]; // Clock data register + ARShift <= 1'b0; // ARShift is 0 because we want to increment + DRDIn <= 1'b0; // Don't care what to shift into data register + DRShift <= 1'b1; // Shift data register + // Shift into UFMD + if (FS[0]) UFMD[15:8] <= {UFMD[14:8], DRDOut}; + + // Compare and store mask + if (FS[4:1]==4'hF) begin + ARCLK <= FS[0]; // Clock address register to increment + // If byte is erased (0xFF, i.e. all 1's, is erased)... + if (UFMD[14:8]==7'b1111111 & DRDOut==1'b1) begin + // Current UFM address is where we want to store + UFMInitDone <= 1'b1; // Quit iterating + // Otherwise byte is valid setting (i.e. some bit is 0)... + end else begin + // Set RWMask, but if saved mask is 0x80, store ~0xFF + if (UFMD[14:8]==7'b1000000 & DRDOut==1'b0) begin + RWMask[7:0] <= {1'b1, ~7'h7F}; + end else RWMask[7:0] <= {UFMD[14], ~UFMD[13:8], ~DRDOut}; + // If last byte in sector... + if (FS[12:5]==8'hFF) begin + UFMReqErase <= 1'b1; // Mark need to erase + end + end + end else ARCLK <= 1'b0; // Don't clock address register + end else begin + ARCLK <= 1'b0; + DRCLK <= 1'b0; + ARShift <= 1'b0; + DRDIn <= 1'b0; + DRShift <= 1'b0; + end + + // Don't erase or program UFM during initialization + UFMErase <= 1'b0; + UFMProgram <= 1'b0; + // Keep DRCLK pulse control disabled during init + DRCLKPulse <= 1'b0; + end else begin + // Can only shift UFM data register now + ARCLK <= 1'b0; + ARShift <= 1'b0; + DRShift <= 1'b1; + + // UFM bitbang control + if (UFMBitbang & CS==3'h7 & RWSel & S==4'hC) begin + DRDIn <= Din[6]; + DRCLKPulse <= Din[7]; + DRCLK <= 1'b0; + end else begin + DRCLKPulse <= 1'b0; + DRCLK <= DRCLKPulse; + end + + // Set capacity mask + if (RWMaskSet & RWSel & S==4'hC) RWMask[7:0] <= {Din[7], ~Din[6:0]}; + + // UFM programming sequence + if (UFMPrgmEN | UFMEraseEN) begin + if (~UFMBusyReg & ~RTPBusyReg) begin + if (UFMReqErase | UFMEraseEN) UFMErase <= 1'b1; + else if (UFMPrgmEN) UFMProgram <= 1'b1; + end else if (UFMBusyReg) UFMReqErase <= 1'b0; + end + end + end + + /* SDRAM Control */ + always @(posedge C14M) begin + if (S==4'h0) begin + // SDRAM initialization + if (FS[15:0]==16'hFFC0) begin + // Precharge All + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b0; + RA[10] <= 1'b1; // "all" + end else if (FS[15:4]==16'hFFD & FS[0]==1'b0) begin // Repeat 8x + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end else if (FS[15:0]==16'hFFE8) begin + // Set Mode Register + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b0; + RA[10] <= 1'b0; // Reserved in mode register + end else if (FS[15:4]==12'hFFF & FS[0]==1'b0) begin // Repeat 8x + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end else begin // Otherwise send no-op + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end + // Enable SDRAM clock after 65,280 cycles (~4.56ms) + CKE <= FS[15:8] == 8'hFF; + + // Mode register contents + BA[1:0] <= 2'b00; // Reserved + RA[11] <= 1'b0; // Reserved + // RA[10] set above ^ + RA[9] <= 1'b1; // "1" for single write mode + RA[8] <= 1'b0; // Reserved + RA[7] <= 1'b0; // "0" for not test mode + RA[6:4] <= 3'b010; // "2" for CAS latency 2 + RA[3] <= 1'b0; // "0" for sequential burst (not used) + RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst) + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + + // Begin normal operation after 128k init cycles (~9.15ms) + if (FS == 16'hFFFF) Ready <= 1'b1; + end else if (S==4'h1) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h2) begin + // Enable clock + CKE <= 1'b1; + + // Activate + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // SDRAM bank 0, high-order row address is 0 + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Row address is as previously latched + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h3) begin + // Enable clock + CKE <= 1'b1; + + // Read + nCS <= 1'b0; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= 1'b1; + + // SDRAM bank 0, RA[11,9:8] don't care + BA <= 2'b00; + RA[11] <= 1'b0; + RA[10] <= 1'b1; // (A10 set to auto-precharge) + RA[9] <= 1'b0; + RA[8] <= 1'b0; + // Latch column address for read command + RA[7:0] <= Ain[7:0]; + + // Read low byte (high byte is +4MB in ramworks) + DQML <= 1'b0; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h4) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h5) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h6) begin + // Enable clock + CKE <= 1'b1; + + if (FS[5:4]==0) begin + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + end else begin + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + end + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h7) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for activate command + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h8) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // Activate if '245 output enabled + nCS <= nEN80; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // SDRAM bank, RA[11:8] determine by RamWorks bank + BA <= RWBank[5:4]; + RA[11:8] <= RWBank[3:0]; + // Row address is as previously latched + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h9) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // Read/Write if '245 output enabled + nCS <= nEN80; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= nWE80; + + // SDRAM bank still determined by RamWorks, RA[11,9:8] don't care + BA <= RWBank[5:4]; + RA[11] <= 1'b0; + RA[10] <= 1'b1; // (A10 set to auto-precharge) + RA[9] <= 1'b0; + RA[8] <= RWBank[7]; + // Latch column address for R/W command + RA[7:0] <= Ain[7:0]; + + // Latch RAMWorks low nybble write select using old row address + RWSel <= RA[0] & ~RA[3] & ~nWE & ~nC07X; + + // Mask according to RAMWorks bank (high byte is +4MB) + DQML <= RWBank[6]; + DQMH <= ~RWBank[6]; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'hA) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'hB) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hC) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + + // RAMWorks Bank Register Select + if (RWSel) begin + // Latch RAMWorks bank if accessed + if (SetRWBankFF) RWBank <= 8'hFF; + else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]}; + + // Recognize command sequence and advance CS state + if ((CS==3'h0 & Din[7:0]==8'hFF) | + (CS==3'h1 & Din[7:0]==8'h00) | + (CS==3'h2 & Din[7:0]==8'h55) | + (CS==3'h3 & Din[7:0]==8'hAA) | + (CS==3'h4 & Din[7:0]==8'hC1) | + (CS==3'h5 & Din[7:0]==8'hAD) | + CS==3'h6 | CS==3'h7) CS <= CS+1; + else CS <= 0; // Back to beginning if it's not right + + if (CS==3'h6) begin // Recognize and submit command in CS6 + SetRWBankFF <= Din[7:0]==8'hFF; + if (Din[7:0]==8'hEF) UFMPrgmEN <= 1'b1; + if (Din[7:0]==8'hEE) UFMEraseEN <= 1'b1; + UFMBitbang <= Din[7:0]==8'hEA; + RWMaskSet <= Din[7:0]==8'hE0; + end else begin // Reset command triggers + SetRWBankFF <= 1'b0; + UFMBitbang <= 1'b0; + RWMaskSet <= 1'b0; + end + + CmdTout <= 0; // Reset command timeout if RWSel accessed + end else begin + CmdTout <= CmdTout+1; // Increment command timeout + // If command sequence times out, reset sequence state + if (CmdTout==3'h7) CS <= 0; + end + end else if (S==4'hD) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hE) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for next video read + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hF) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for next video read + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end + end + always @(negedge C14M) begin + // Latch video and read data outputs + if (S==4'h6) Vout[7:0] <= RD[7:0]; + if (S==4'hC) Dout[7:0] <= RD[7:0]; + end +endmodule diff --git a/cpld_maxv/UFM.qip b/cpld_maxv/UFM.qip new file mode 100644 index 0000000..e2d8458 --- /dev/null +++ b/cpld_maxv/UFM.qip @@ -0,0 +1,3 @@ +set_global_assignment -name IP_TOOL_NAME "ALTUFM_NONE" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "UFM.v"] diff --git a/cpld_maxv/UFM.v b/cpld_maxv/UFM.v new file mode 100644 index 0000000..613c750 --- /dev/null +++ b/cpld_maxv/UFM.v @@ -0,0 +1,268 @@ +// megafunction wizard: %ALTUFM_NONE% +// GENERATION: STANDARD +// VERSION: WM1.0 +// MODULE: ALTUFM_NONE + +// ============================================================ +// File Name: UFM.v +// Megafunction Name(s): +// ALTUFM_NONE +// +// Simulation Library Files(s): +// maxv +// ============================================================ +// ************************************************************ +// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +// +// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +// ************************************************************ + + +//Copyright (C) 1991-2013 Altera Corporation +//Your use of Altera Corporation's design tools, logic functions +//and other software and tools, and its AMPP partner logic +//functions, and any output files from any of the foregoing +//(including device programming or simulation files), and any +//associated documentation or information are expressly subject +//to the terms and conditions of the Altera Program License +//Subscription Agreement, Altera MegaCore Function License +//Agreement, or other applicable license agreement, including, +//without limitation, that your use is for the sole purpose of +//programming logic devices manufactured by Altera and sold by +//Altera or its authorized distributors. Please refer to the +//applicable agreement for further details. + + +//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy +//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END +// synthesis VERILOG_INPUT_VERSION VERILOG_2001 +// altera message_off 10463 + + +//synthesis_resources = maxv_ufm 1 +//synopsys translate_off +`timescale 1 ps / 1 ps +//synopsys translate_on +module UFM_altufm_none_e4r + ( + arclk, + ardin, + arshft, + busy, + drclk, + drdin, + drdout, + drshft, + erase, + osc, + oscena, + program, + rtpbusy) ; + input arclk; + input ardin; + input arshft; + output busy; + input drclk; + input drdin; + output drdout; + input drshft; + input erase; + output osc; + input oscena; + input program; + output rtpbusy; + + wire wire_maxii_ufm_block1_bgpbusy; + wire wire_maxii_ufm_block1_busy; + wire wire_maxii_ufm_block1_drdout; + wire wire_maxii_ufm_block1_osc; + wire ufm_arclk; + wire ufm_ardin; + wire ufm_arshft; + wire ufm_bgpbusy; + wire ufm_busy; + wire ufm_drclk; + wire ufm_drdin; + wire ufm_drdout; + wire ufm_drshft; + wire ufm_erase; + wire ufm_osc; + wire ufm_oscena; + wire ufm_program; + + maxv_ufm maxii_ufm_block1 + ( + .arclk(ufm_arclk), + .ardin(ufm_ardin), + .arshft(ufm_arshft), + .bgpbusy(wire_maxii_ufm_block1_bgpbusy), + .busy(wire_maxii_ufm_block1_busy), + .drclk(ufm_drclk), + .drdin(ufm_drdin), + .drdout(wire_maxii_ufm_block1_drdout), + .drshft(ufm_drshft), + .erase(ufm_erase), + .osc(wire_maxii_ufm_block1_osc), + .oscena(ufm_oscena), + .program(ufm_program) + // synopsys translate_off + , + .ctrl_bgpbusy(1'b0), + .devclrn(1'b1), + .devpor(1'b1), + .sbdin(1'b0), + .sbdout() + // synopsys translate_on + ); + defparam + maxii_ufm_block1.address_width = 9, + maxii_ufm_block1.erase_time = 500000000, + maxii_ufm_block1.init_file = "RAM2E.mif", + maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem2 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem3 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem4 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem5 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem6 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem7 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem8 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, + maxii_ufm_block1.osc_sim_setting = 180000, + maxii_ufm_block1.program_time = 1600000, + maxii_ufm_block1.lpm_type = "maxv_ufm"; + assign + busy = ufm_busy, + drdout = ufm_drdout, + osc = ufm_osc, + rtpbusy = ufm_bgpbusy, + ufm_arclk = arclk, + ufm_ardin = ardin, + ufm_arshft = arshft, + ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy, + ufm_busy = wire_maxii_ufm_block1_busy, + ufm_drclk = drclk, + ufm_drdin = drdin, + ufm_drdout = wire_maxii_ufm_block1_drdout, + ufm_drshft = drshft, + ufm_erase = erase, + ufm_osc = wire_maxii_ufm_block1_osc, + ufm_oscena = oscena, + ufm_program = program; +endmodule //UFM_altufm_none_e4r +//VALID FILE + + +// synopsys translate_off +`timescale 1 ps / 1 ps +// synopsys translate_on +module UFM ( + arclk, + ardin, + arshft, + drclk, + drdin, + drshft, + erase, + oscena, + program, + busy, + drdout, + osc, + rtpbusy); + + input arclk; + input ardin; + input arshft; + input drclk; + input drdin; + input drshft; + input erase; + input oscena; + input program; + output busy; + output drdout; + output osc; + output rtpbusy; + + wire sub_wire0; + wire sub_wire1; + wire sub_wire2; + wire sub_wire3; + wire osc = sub_wire0; + wire rtpbusy = sub_wire1; + wire drdout = sub_wire2; + wire busy = sub_wire3; + + UFM_altufm_none_e4r UFM_altufm_none_e4r_component ( + .arshft (arshft), + .drclk (drclk), + .erase (erase), + .program (program), + .arclk (arclk), + .drdin (drdin), + .oscena (oscena), + .ardin (ardin), + .drshft (drshft), + .osc (sub_wire0), + .rtpbusy (sub_wire1), + .drdout (sub_wire2), + .busy (sub_wire3)); + +endmodule + +// ============================================================ +// CNX file retrieval info +// ============================================================ +// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX V" +// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000" +// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX V" +// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2E.mif" +// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" +// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none" +// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000" +// Retrieval info: CONSTANT: PORT_ARCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_DRCLKENA STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PROGRAM_TIME NUMERIC "1600000" +// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9" +// Retrieval info: USED_PORT: arclk 0 0 0 0 INPUT NODEFVAL "arclk" +// Retrieval info: CONNECT: @arclk 0 0 0 0 arclk 0 0 0 0 +// Retrieval info: USED_PORT: ardin 0 0 0 0 INPUT NODEFVAL "ardin" +// Retrieval info: CONNECT: @ardin 0 0 0 0 ardin 0 0 0 0 +// Retrieval info: USED_PORT: arshft 0 0 0 0 INPUT NODEFVAL "arshft" +// Retrieval info: CONNECT: @arshft 0 0 0 0 arshft 0 0 0 0 +// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy" +// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0 +// Retrieval info: USED_PORT: drclk 0 0 0 0 INPUT NODEFVAL "drclk" +// Retrieval info: CONNECT: @drclk 0 0 0 0 drclk 0 0 0 0 +// Retrieval info: USED_PORT: drdin 0 0 0 0 INPUT NODEFVAL "drdin" +// Retrieval info: CONNECT: @drdin 0 0 0 0 drdin 0 0 0 0 +// Retrieval info: USED_PORT: drdout 0 0 0 0 OUTPUT NODEFVAL "drdout" +// Retrieval info: CONNECT: drdout 0 0 0 0 @drdout 0 0 0 0 +// Retrieval info: USED_PORT: drshft 0 0 0 0 INPUT NODEFVAL "drshft" +// Retrieval info: CONNECT: @drshft 0 0 0 0 drshft 0 0 0 0 +// Retrieval info: USED_PORT: erase 0 0 0 0 INPUT NODEFVAL "erase" +// Retrieval info: CONNECT: @erase 0 0 0 0 erase 0 0 0 0 +// Retrieval info: USED_PORT: osc 0 0 0 0 OUTPUT NODEFVAL "osc" +// Retrieval info: CONNECT: osc 0 0 0 0 @osc 0 0 0 0 +// Retrieval info: USED_PORT: oscena 0 0 0 0 INPUT NODEFVAL "oscena" +// Retrieval info: CONNECT: @oscena 0 0 0 0 oscena 0 0 0 0 +// Retrieval info: USED_PORT: program 0 0 0 0 INPUT NODEFVAL "program" +// Retrieval info: CONNECT: @program 0 0 0 0 program 0 0 0 0 +// Retrieval info: USED_PORT: rtpbusy 0 0 0 0 OUTPUT NODEFVAL "rtpbusy" +// Retrieval info: CONNECT: rtpbusy 0 0 0 0 @rtpbusy 0 0 0 0 +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.qip TRUE FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE +// Retrieval info: LIB_FILE: maxv diff --git a/cpld_maxv/constraints.sdc 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@@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Wed Mar 10 20:54:25 2021 diff --git a/cpld_maxv/db/RAM2E.fit.qmsg b/cpld_maxv/db/RAM2E.fit.qmsg new file mode 100644 index 0000000..267c129 --- /dev/null +++ b/cpld_maxv/db/RAM2E.fit.qmsg @@ -0,0 +1,39 @@ +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1615428149527 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1615428149562 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615428149621 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1615428149621 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1615428150075 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1615428150103 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1615428150459 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1615428150459 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1615428150459 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1615428150459 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1615428150459 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1615428150459 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1615428150459 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1615428150459 ""} +{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1615428150747 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1615428150756 "|RAM2E|DRCLK"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1615428150757 "|RAM2E|ARCLK"} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1615428150764 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1615428150765 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1615428150765 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1615428150765 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1615428150765 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615428150774 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1615428150775 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1615428150781 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1615428150794 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1615428150794 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1615428150802 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1615428150830 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1615428150830 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1615428150872 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1615428150877 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1615428150877 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1615428150878 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615428150984 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1615428151178 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615428151386 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1615428151403 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1615428151776 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615428151777 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1615428151814 ""} +{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "2e+01 ns 1.0% " "2e+01 ns of routing delay (approximately 1.0% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1615428152024 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "21 " "Router estimated average interconnect usage is 21% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "21 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/" { { 1 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1615428152066 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1615428152066 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615428152232 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.22 " "Total time spent on timing analysis during the Fitter is 0.22 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1615428152246 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1615428152251 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1615428152297 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1615428152414 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4766 " "Peak virtual memory: 4766 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1615428152724 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 10 21:02:32 2021 " "Processing ended: Wed Mar 10 21:02:32 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1615428152724 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1615428152724 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1615428152724 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1615428152724 ""} diff --git a/cpld_maxv/db/RAM2E.hier_info b/cpld_maxv/db/RAM2E.hier_info new file mode 100644 index 0000000..cba7dd3 --- /dev/null +++ b/cpld_maxv/db/RAM2E.hier_info @@ -0,0 +1,350 @@ +|RAM2E +C14M => CmdTout[0].CLK +C14M => CmdTout[1].CLK +C14M => CmdTout[2].CLK +C14M => RWMaskSet.CLK +C14M => UFMBitbang.CLK +C14M => UFMEraseEN.CLK +C14M => UFMPrgmEN.CLK +C14M => SetRWBankFF.CLK +C14M => CS[0].CLK +C14M => CS[1].CLK +C14M => CS[2].CLK +C14M => RWBank[0].CLK +C14M => RWBank[1].CLK +C14M => RWBank[2].CLK +C14M => RWBank[3].CLK +C14M => RWBank[4].CLK +C14M => RWBank[5].CLK +C14M => RWBank[6].CLK +C14M => RWBank[7].CLK +C14M => RWSel.CLK +C14M => Ready.CLK +C14M => DOEEN.CLK +C14M => DQMH~reg0.CLK +C14M => DQML~reg0.CLK +C14M => BA[0]~reg0.CLK +C14M => BA[1]~reg0.CLK +C14M => CKE~reg0.CLK +C14M => RA[0]~reg0.CLK +C14M => RA[1]~reg0.CLK +C14M => RA[2]~reg0.CLK +C14M => RA[3]~reg0.CLK +C14M => RA[4]~reg0.CLK +C14M => RA[5]~reg0.CLK +C14M => RA[6]~reg0.CLK +C14M => RA[7]~reg0.CLK +C14M => RA[8]~reg0.CLK +C14M => RA[9]~reg0.CLK +C14M => RA[10]~reg0.CLK +C14M => RA[11]~reg0.CLK +C14M => nRWE~reg0.CLK +C14M => nCAS~reg0.CLK +C14M => nRAS~reg0.CLK +C14M => nCS~reg0.CLK +C14M => DRCLKPulse.CLK +C14M => UFMProgram.CLK +C14M => UFMErase.CLK +C14M => UFMReqErase.CLK +C14M => RWMask[0].CLK +C14M => RWMask[1].CLK +C14M => RWMask[2].CLK +C14M => RWMask[3].CLK +C14M => RWMask[4].CLK +C14M => RWMask[5].CLK +C14M => RWMask[6].CLK +C14M => RWMask[7].CLK +C14M => UFMInitDone.CLK +C14M => UFMD[8].CLK +C14M => UFMD[9].CLK +C14M => UFMD[10].CLK +C14M => UFMD[11].CLK +C14M => UFMD[12].CLK +C14M => UFMD[13].CLK +C14M => UFMD[14].CLK +C14M => DRShift.CLK +C14M => DRDIn.CLK +C14M => ARShift.CLK +C14M => DRCLK.CLK +C14M => ARCLK.CLK +C14M => RTPBusyReg.CLK +C14M => UFMBusyReg.CLK +C14M => S[0].CLK +C14M => S[1].CLK +C14M => S[2].CLK +C14M => S[3].CLK +C14M => PHI1reg.CLK +C14M => FS[0].CLK +C14M => FS[1].CLK +C14M => FS[2].CLK +C14M => FS[3].CLK +C14M => FS[4].CLK +C14M => FS[5].CLK +C14M => FS[6].CLK +C14M => FS[7].CLK +C14M => FS[8].CLK +C14M => FS[9].CLK +C14M => FS[10].CLK +C14M => FS[11].CLK +C14M => FS[12].CLK +C14M => FS[13].CLK +C14M => FS[14].CLK +C14M => FS[15].CLK +C14M => Dout[0]~reg0.CLK +C14M => Dout[1]~reg0.CLK +C14M => Dout[2]~reg0.CLK +C14M => Dout[3]~reg0.CLK +C14M => Dout[4]~reg0.CLK +C14M => Dout[5]~reg0.CLK +C14M => Dout[6]~reg0.CLK +C14M => Dout[7]~reg0.CLK +C14M => Vout[0]~reg0.CLK +C14M => Vout[1]~reg0.CLK +C14M => Vout[2]~reg0.CLK +C14M => Vout[3]~reg0.CLK +C14M => Vout[4]~reg0.CLK +C14M => Vout[5]~reg0.CLK +C14M => Vout[6]~reg0.CLK +C14M => Vout[7]~reg0.CLK +PHI1 => S.IN1 +PHI1 => PHI1reg.DATAIN +PHI1 => nVOE.DATAIN +nWE => comb.IN0 +nWE => RWSel.IN1 +nWE80 => nRWE.DATAB +nWE80 => RDOE.IN0 +nEN80 => nCS.DATAB +nEN80 => nCS.DATAB +nEN80 => comb.IN1 +nEN80 => RDOE.IN1 +nEN80 => CKE.DATAB +nEN80 => CKE.DATAB +nEN80 => CKE.DATAB +nC07X => RWSel.IN1 +Ain[0] => RA.DATAB +Ain[0] => RA.DATAB +Ain[0] => RA.DATAB +Ain[0] => RA.DATAB +Ain[0] => RA.DATAB +Ain[1] => RA.DATAB +Ain[1] => RA.DATAB +Ain[1] => RA.DATAB +Ain[1] => RA.DATAB +Ain[1] => RA.DATAB +Ain[2] => RA.DATAB +Ain[2] => RA.DATAB +Ain[2] => RA.DATAB +Ain[2] => RA.DATAB +Ain[2] => RA.DATAB +Ain[3] => RA.DATAB +Ain[3] => RA.DATAB +Ain[3] => RA.DATAB +Ain[3] => RA.DATAB +Ain[3] => RA.DATAB +Ain[4] => RA.DATAB +Ain[4] => RA.DATAB +Ain[4] => RA.DATAB +Ain[4] => RA.DATAB +Ain[4] => RA.DATAB +Ain[5] => RA.DATAB +Ain[5] => RA.DATAB +Ain[5] => RA.DATAB +Ain[5] => RA.DATAB +Ain[5] => RA.DATAB +Ain[6] => RA.DATAB +Ain[6] => RA.DATAB +Ain[6] => RA.DATAB +Ain[6] => RA.DATAB +Ain[6] => RA.DATAB +Ain[7] => RA.DATAB +Ain[7] => RA.DATAB +Ain[7] => RA.DATAB +Ain[7] => RA.DATAB +Ain[7] => RA.DATAB +Din[0] => RWBank.IN1 +Din[0] => RD[0].DATAIN +Din[0] => RWMask.DATAB +Din[0] => Equal29.IN7 +Din[0] => Equal31.IN3 +Din[0] => Equal33.IN7 +Din[0] => Equal35.IN2 +Din[0] => Equal37.IN4 +Din[0] => Equal39.IN7 +Din[0] => Equal40.IN6 +Din[0] => Equal41.IN7 +Din[0] => Equal42.IN7 +Din[0] => Equal43.IN7 +Din[1] => RWBank.IN1 +Din[1] => RD[1].DATAIN +Din[1] => RWMask.DATAB +Din[1] => Equal29.IN6 +Din[1] => Equal31.IN7 +Din[1] => Equal33.IN3 +Din[1] => Equal35.IN7 +Din[1] => Equal37.IN7 +Din[1] => Equal39.IN6 +Din[1] => Equal40.IN5 +Din[1] => Equal41.IN5 +Din[1] => Equal42.IN4 +Din[1] => Equal43.IN6 +Din[2] => RWBank.IN1 +Din[2] => RD[2].DATAIN +Din[2] => RWMask.DATAB +Din[2] => Equal29.IN5 +Din[2] => Equal31.IN2 +Din[2] => Equal33.IN6 +Din[2] => Equal35.IN6 +Din[2] => Equal37.IN3 +Din[2] => Equal39.IN5 +Din[2] => Equal40.IN4 +Din[2] => Equal41.IN4 +Din[2] => Equal42.IN6 +Din[2] => Equal43.IN5 +Din[3] => RWBank.IN1 +Din[3] => RD[3].DATAIN +Din[3] => RWMask.DATAB +Din[3] => Equal29.IN4 +Din[3] => Equal31.IN6 +Din[3] => Equal33.IN2 +Din[3] => Equal35.IN5 +Din[3] => Equal37.IN2 +Din[3] => Equal39.IN4 +Din[3] => Equal40.IN3 +Din[3] => Equal41.IN3 +Din[3] => Equal42.IN3 +Din[3] => Equal43.IN4 +Din[4] => RWBank.IN1 +Din[4] => RD[4].DATAIN +Din[4] => RWMask.DATAB +Din[4] => Equal29.IN3 +Din[4] => Equal31.IN1 +Din[4] => Equal33.IN5 +Din[4] => Equal35.IN4 +Din[4] => Equal37.IN6 +Din[4] => Equal39.IN3 +Din[4] => Equal40.IN7 +Din[4] => Equal41.IN6 +Din[4] => Equal42.IN5 +Din[4] => Equal43.IN3 +Din[5] => RWBank.IN1 +Din[5] => RD[5].DATAIN +Din[5] => RWMask.DATAB +Din[5] => Equal29.IN2 +Din[5] => Equal31.IN5 +Din[5] => Equal33.IN1 +Din[5] => Equal35.IN3 +Din[5] => Equal37.IN1 +Din[5] => Equal39.IN2 +Din[5] => Equal40.IN2 +Din[5] => Equal41.IN2 +Din[5] => Equal42.IN2 +Din[5] => Equal43.IN2 +Din[6] => DRDIn.DATAB +Din[6] => RWBank.IN1 +Din[6] => RD[6].DATAIN +Din[6] => RWMask.DATAB +Din[6] => Equal29.IN1 +Din[6] => Equal31.IN0 +Din[6] => Equal33.IN4 +Din[6] => Equal35.IN1 +Din[6] => Equal37.IN5 +Din[6] => Equal39.IN1 +Din[6] => Equal40.IN1 +Din[6] => Equal41.IN1 +Din[6] => Equal42.IN1 +Din[6] => Equal43.IN1 +Din[7] => DRCLKPulse.DATAB +Din[7] => RWMask.DATAB +Din[7] => RWBank.IN1 +Din[7] => RD[7].DATAIN +Din[7] => Equal29.IN0 +Din[7] => Equal31.IN4 +Din[7] => Equal33.IN0 +Din[7] => Equal35.IN0 +Din[7] => Equal37.IN0 +Din[7] => Equal39.IN0 +Din[7] => Equal40.IN0 +Din[7] => Equal41.IN0 +Din[7] => Equal42.IN0 +Din[7] => Equal43.IN0 +Dout[0] <= Dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Dout[1] <= Dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Dout[2] <= Dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Dout[3] <= Dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Dout[4] <= Dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Dout[5] <= Dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Dout[6] <= Dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Dout[7] <= Dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +nDOE <= comb.DB_MAX_OUTPUT_PORT_TYPE +Vout[0] <= Vout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[1] <= Vout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[2] <= Vout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[3] <= Vout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[4] <= Vout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[5] <= Vout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[6] <= Vout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +Vout[7] <= Vout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +nVOE <= PHI1.DB_MAX_OUTPUT_PORT_TYPE +CKE <= CKE~reg0.DB_MAX_OUTPUT_PORT_TYPE +nCS <= nCS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRAS <= nRAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nCAS <= nCAS~reg0.DB_MAX_OUTPUT_PORT_TYPE +nRWE <= nRWE~reg0.DB_MAX_OUTPUT_PORT_TYPE +BA[0] <= BA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +BA[1] <= BA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[0] <= RA[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[1] <= RA[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[2] <= RA[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[3] <= RA[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[4] <= RA[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[5] <= RA[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[6] <= RA[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[7] <= RA[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[8] <= RA[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[9] <= RA[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[10] <= RA[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RA[11] <= RA[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +RD[0] <> RD[0] +RD[1] <> RD[1] +RD[2] <> RD[2] +RD[3] <> RD[3] +RD[4] <> RD[4] +RD[5] <> RD[5] +RD[6] <> RD[6] +RD[7] <> RD[7] +DQML <= DQML~reg0.DB_MAX_OUTPUT_PORT_TYPE +DQMH <= DQMH~reg0.DB_MAX_OUTPUT_PORT_TYPE + + +|RAM2E|UFM:UFM_inst +arclk => arclk.IN1 +ardin => ardin.IN1 +arshft => arshft.IN1 +drclk => drclk.IN1 +drdin => drdin.IN1 +drshft => drshft.IN1 +erase => erase.IN1 +oscena => oscena.IN1 +program => program.IN1 +busy <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.busy +drdout <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.drdout +osc <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.osc +rtpbusy <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.rtpbusy + + +|RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component +arclk => maxii_ufm_block1.ARCLK +ardin => maxii_ufm_block1.ARDIN +arshft => maxii_ufm_block1.ARSHFT +busy <= maxii_ufm_block1.BUSY +drclk => maxii_ufm_block1.DRCLK +drdin => maxii_ufm_block1.DRDIN +drdout <= maxii_ufm_block1.DRDOUT +drshft => maxii_ufm_block1.DRSHFT +erase => maxii_ufm_block1.ERASE +osc <= maxii_ufm_block1.OSC +oscena => maxii_ufm_block1.OSCENA +program => maxii_ufm_block1.PROGRAM +rtpbusy <= maxii_ufm_block1.BGPBUSY + + diff --git a/cpld_maxv/db/RAM2E.hif b/cpld_maxv/db/RAM2E.hif new file mode 100644 index 0000000000000000000000000000000000000000..a8f404b8bd9dc79db4b1a4aef8e46502ea61d23a GIT binary patch literal 576 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UFM_inst|UFM_altufm_none_e4r_component9000400000000
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@@ -0,0 +1,8 @@ ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; 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"*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1615428143615 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1615428143616 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 10 21:02:22 2021 " "Processing started: Wed Mar 10 21:02:22 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1615428143616 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1615428143616 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1615428143616 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1615428145711 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(38) " "Verilog HDL warning at RAM2E.v(38): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/RAM2E.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1615428145839 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1615428145848 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1615428145848 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1615428145928 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1615428145929 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_e4r " "Found entity 1: UFM_altufm_none_e4r" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1615428145929 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1615428145929 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1615428145929 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1615428146009 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(100) " "Verilog HDL assignment warning at RAM2E.v(100): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/RAM2E.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1615428146018 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(103) " "Verilog HDL assignment warning at RAM2E.v(103): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/RAM2E.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1615428146018 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(544) " "Verilog HDL assignment warning at RAM2E.v(544): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/RAM2E.v" 544 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1615428146023 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(561) " "Verilog HDL assignment warning at RAM2E.v(561): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/RAM2E.v" 561 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1615428146023 "|RAM2E"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/RAM2E.v" 79 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1615428146122 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_e4r UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component " "Elaborating entity \"UFM_altufm_none_e4r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component\"" { } { { "UFM.v" "UFM_altufm_none_e4r_component" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1615428146152 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "268 " "Implemented 268 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1615428147216 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1615428147216 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1615428147216 ""} { "Info" "ICUT_CUT_TM_LCELLS" "198 " "Implemented 198 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1615428147216 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1615428147216 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1615428147216 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1615428147485 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4567 " "Peak virtual memory: 4567 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1615428147569 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 10 21:02:27 2021 " "Processing ended: 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b/cpld_maxv/db/RAM2E.smart_action.txt @@ -0,0 +1 @@ +DONE diff --git a/cpld_maxv/db/RAM2E.sta.qmsg b/cpld_maxv/db/RAM2E.sta.qmsg new file mode 100644 index 0000000..21770fe --- /dev/null +++ b/cpld_maxv/db/RAM2E.sta.qmsg @@ -0,0 +1,22 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1615428156850 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1615428156851 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Mar 10 21:02:36 2021 " "Processing started: Wed Mar 10 21:02:36 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1615428156851 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1615428156851 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1615428156852 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1615428157066 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1615428157327 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1615428157381 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1615428157382 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1615428157449 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1615428157898 ""} +{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1615428157998 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1615428158012 "|RAM2E|DRCLK"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1615428158012 "|RAM2E|ARCLK"} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1615428158015 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 21.072 " "Worst-case setup slack is 21.072" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1615428158063 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1615428158063 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 21.072 0.000 C14M " " 21.072 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1615428158063 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1615428158063 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 3.158 " "Worst-case hold slack is 3.158" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1615428158076 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1615428158076 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.158 0.000 C14M " " 3.158 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1615428158076 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1615428158076 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1615428158092 ""} +{ "Info" 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report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1615428158213 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1615428158250 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1615428158251 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4514 " "Peak virtual memory: 4514 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1615428158380 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Mar 10 21:02:38 2021 " "Processing ended: Wed Mar 10 21:02:38 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1615428158380 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1615428158380 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1615428158380 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1615428158380 ""} diff --git a/cpld_maxv/db/RAM2E.sta.rdb b/cpld_maxv/db/RAM2E.sta.rdb new file mode 100644 index 0000000000000000000000000000000000000000..76dfef9afe82e6c2d15242b80e9019784fefc125 GIT binary patch literal 10721 zcmXw91yCJLkj8=pceen+Jp>O9!5tp%?)GqZcjw{m?he7--Q8US9Qp6AwyJyQo1U+` zx@T&(Y8w>{46Fhk{8Ku7K7yZG#mL^l%*L98nU#Twftf_m$;{G_goTxbgy|i^X) z;AdLT(d5I*7uP+^I9FeAm}0b9R|wr(8!t}O$7<`=XEX0*F7JSoL`!t%X(wkFwQXf9 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14:36:33 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1611862593703 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1611862593703 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1611862593703 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1611862594200 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(38) " "Verilog HDL warning at RAM2E.v(38): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1611862594267 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1611862594271 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1611862594271 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1611862594340 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1611862594340 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_a7r " "Found entity 1: UFM_altufm_none_a7r" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1611862594341 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1611862594341 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1611862594341 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1611862594391 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(100) " "Verilog HDL assignment warning at RAM2E.v(100): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862594395 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(103) " "Verilog HDL assignment warning at RAM2E.v(103): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862594395 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(544) " "Verilog HDL assignment warning at RAM2E.v(544): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 544 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862594395 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(561) " "Verilog HDL assignment warning at RAM2E.v(561): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 561 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862594395 "|RAM2E"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 79 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1611862594399 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_a7r UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component " "Elaborating entity \"UFM_altufm_none_a7r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component\"" { } { { "UFM.v" "UFM_altufm_none_a7r_component" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1611862594425 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "268 " "Implemented 268 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1611862595360 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1611862595360 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1611862595360 ""} { "Info" "ICUT_CUT_TM_LCELLS" "198 " "Implemented 198 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1611862595360 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1611862595360 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1611862595360 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1611862595434 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4566 " "Peak virtual memory: 4566 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862595516 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:36:35 2021 " "Processing ended: Thu Jan 28 14:36:35 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862595516 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862595516 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862595516 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1611862595516 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1611862596827 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1611862596828 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 28 14:36:36 2021 " "Processing started: Thu Jan 28 14:36:36 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1611862596828 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1611862596828 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1611862596829 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1611862596970 ""} +{ "Info" "0" "" "Project = RAM2E" { } { } 0 0 "Project = RAM2E" 0 0 "Fitter" 0 0 1611862596971 ""} +{ "Info" "0" "" "Revision = RAM2E" { } { } 0 0 "Revision = RAM2E" 0 0 "Fitter" 0 0 1611862596971 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1611862597039 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1611862597043 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611862597090 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611862597090 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1611862597149 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1611862597162 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862597357 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862597357 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862597357 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862597357 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862597357 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1611862597357 ""} +{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1611862597463 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1611862597467 "|RAM2E|DRCLK"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1611862597467 "|RAM2E|ARCLK"} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1611862597470 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1611862597470 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1611862597470 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1611862597470 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1611862597470 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611862597474 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611862597474 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1611862597479 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1611862597487 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1611862597488 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1611862597490 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1611862597511 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1611862597511 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1611862597552 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1611862597554 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1611862597555 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1611862597555 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862597600 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1611862597720 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862597937 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1611862597949 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1611862598355 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862598355 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1611862598402 ""} +{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "4e+01 ns 2.6% " "4e+01 ns of routing delay (approximately 2.6% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1611862598625 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1611862598662 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1611862598662 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862598820 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1611862598830 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862598835 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1611862598876 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1611862598978 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4758 " "Peak virtual memory: 4758 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862599258 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:36:39 2021 " "Processing ended: Thu Jan 28 14:36:39 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862599258 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862599258 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862599258 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1611862599258 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1611862600288 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1611862600289 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 28 14:36:40 2021 " "Processing started: Thu Jan 28 14:36:40 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1611862600289 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1611862600289 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1611862600289 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1611862600645 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1611862600652 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4515 " "Peak virtual memory: 4515 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862600967 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:36:40 2021 " "Processing ended: Thu Jan 28 14:36:40 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862600967 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862600967 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862600967 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1611862600967 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1611862601573 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1611862602252 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1611862602253 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 28 14:36:41 2021 " "Processing started: Thu Jan 28 14:36:41 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1611862602253 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1611862602253 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1611862602254 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1611862602417 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1611862602652 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1611862602701 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1611862602701 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1611862602760 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1611862603084 ""} +{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1611862603191 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1611862603205 "|RAM2E|DRCLK"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1611862603205 "|RAM2E|ARCLK"} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1611862603208 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 29.169 " "Worst-case setup slack is 29.169" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 29.169 0.000 C14M " " 29.169 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603267 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1611862603267 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.646 " "Worst-case hold slack is 1.646" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603277 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603277 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.646 0.000 C14M " " 1.646 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603277 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1611862603277 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1611862603289 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1611862603298 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.654 " "Worst-case minimum pulse width slack is 34.654" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.654 0.000 C14M " " 34.654 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603307 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1611862603307 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1611862603380 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1611862603420 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1611862603420 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4513 " "Peak virtual memory: 4513 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862603567 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:36:43 2021 " "Processing ended: Thu Jan 28 14:36:43 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862603567 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862603567 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862603567 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1611862603567 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 13 s " "Quartus II Full Compilation was successful. 0 errors, 13 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1611862604230 ""} diff --git a/cpld_maxv/greybox_tmp/cbx_args.txt b/cpld_maxv/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..c8d6a96 --- /dev/null +++ b/cpld_maxv/greybox_tmp/cbx_args.txt @@ -0,0 +1,25 @@ +ERASE_TIME=500000000 +INTENDED_DEVICE_FAMILY="MAX V" +LPM_FILE=RAM2E.mif +LPM_HINT=UNUSED +LPM_TYPE=altufm_none +OSC_FREQUENCY=180000 +PORT_ARCLKENA=PORT_UNUSED +PORT_DRCLKENA=PORT_UNUSED +PROGRAM_TIME=1600000 +WIDTH_UFM_ADDRESS=9 +DEVICE_FAMILY="MAX V" +CBX_AUTO_BLACKBOX=ALL +arclk +ardin +arshft +busy +drclk +drdin +drdout +drshft +erase +osc +oscena +program +rtpbusy diff --git a/cpld_maxv/incremental_db/README b/cpld_maxv/incremental_db/README new file mode 100644 index 0000000..9f62dcd --- /dev/null +++ b/cpld_maxv/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/cpld_maxv/incremental_db/compiled_partitions/RAM2E.db_info b/cpld_maxv/incremental_db/compiled_partitions/RAM2E.db_info new file mode 100644 index 0000000..13cf0a5 --- /dev/null +++ b/cpld_maxv/incremental_db/compiled_partitions/RAM2E.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Wed Sep 16 19:59:34 2020 diff --git a/cpld_maxv/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt b/cpld_maxv/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt new file mode 100644 index 0000000000000000000000000000000000000000..b06a357e3417d07324f95be3c71d6899c3323de5 GIT binary patch literal 2893 zcmV-T3$paA4*>uG0001Zob8?MPus{A#=q}hVdeWaId)zpS_uefxh=ai*-by76$*{p zjex)=PF1AU{oAi&2jT+jXP#5v8IRPDkmO{1W}Z1O^Ru&eb(dVsE`!DNCVt%*?VpB6 zuWqJy7nhffVDr+Kc)6P2E?zg}l{A9C*VARPUhV$-KL1B>auRggKOfAKV3NNSNc5`p zN`iy+{CXCIQ5dwkO$nP}OQK*LFTcz`#=+V2<5eKR_&>pi_%b+}&6D(#jW<69!QNGT ze{pv^UnHxGRh$IL{are|W&9~##*2?}Blv3`FVk1d^%)pwt>yz`_o?- zdmVh$Eoy*WVDNB!9#RH-*o&k1@1x~(6*Ff0a19+y7gy&UYODk7O>R+23(fa$M@PR> z7Lj<4$L9lXj7T}d(c!zdltrYRt-yQSIFWX8J(3fI1eC6KPC$Ybv`@PeNhqCi;Y2Bh z@*ywXKtJ4e86y3p7CDKBNI(0d@n7>#31t&0=$PF!L!_YbdBhn+;yJvT{eHVn*!e;7 z$u!yLY#M|ha+C%!DBU?ok0J>zMjwtSgHS!WCdniQDd=J1xdj>_8Ko{gSACv}WeM5f3c9Eq}U%n7~&OQU_( zB8)`8pB=1M_oMhTWfsXOTcKQt>mV7W^F%iSI!H=vw%9>BN>@EOMMy_OUhQ3^q;!;A zDcnUW%0|g4vujWpksY)yQqY8tLtUt$599cnvWVn!z?Q;YB%U;#$+x8AW6G{kC?cDP zI20YedwaIN=A_<5Iy!tyRa`v-4RMpyGi+^h?(7+cB5pVC8H6IT)r)16jgz!$&|^4T ze!k)Qs6CU?h|4^CI1-Wb4lAR5vNq@;1!cax{k)vsP|bLw(ufO3eWP&11>!yu65FTi z8+N+6h15qnO4lZ*^*++j*)J!u)-5o<1SZYLT*@#I#y^kabZlS-1D zbi;!pa(Nnrp@VsHIbBdYlC*GpAsa2{18Eub7ZfG7v<#R9?(9Tb2GBxQVw0!NErXE6 z4iyP&v)Qx9?MPNbzH1>Zq^cq8QWpNqpqcD{-~Ma+70GhCSmm%y0i^k-p|JAlc6k%e zo|}2$3bD!+M2@r!WKI(_0+|XLQ4t7LC?OSrY=sI_5eQgp`qBSQUu$t@A)Un2Dh47a zaTN$y@Vp8nEOfvMq%2g#3ZyJ}WCdatJhK8h3k9?SISU=N0%417%cCOkTV_QVi9gsACrb64pfRS0pYL6cA$ogA9Wv1O|)V2*xiq$5XspA%H_P~kvFeEiHUQ%J# z=!mSPv20KVl8S@8MuxB}hKlqy(Fy~?8$4Ad5Z<66D1r1wMziymZ^&?vbd{Jv9AvG4 zA&%^>5QP(9KvO|h0%?v-`%*Dnqp+sg!ywb4z^w!_9h=)^6l1NNkP?V?(1?^kvO~p4 z3B)@zkd#2cV?#mnGX)_J6?`R-^O$I}JIH%Xv^6B;KC(k#g_>LXhQclk zXDZH3AOxa;(gcDa+nzD+2MB}El@tU)Xy8pC2}09p0x=LCB@+mN(A<|`2t7~nfM|${+!6yoM1gJzBt%rCl|W2Hg<1(DMR?XqASy!V zU62&fu~7nvkpo?o54jP#tqQ3T70o0N9HDV0f!K(GXA+2x@br;DdSt`5DCXWkQS2-k z-PolVs!^|AlL?tnBs7o|LWX2<$QR%tL`X8!Lt)o2Y;pNp2r&{Bo)kigBtwoBUcii& zf>H`0O`^k;LI{+oFr^Su96C%XgcwH-dh*i-Ne&&X6q-CEgS;mlf*d@o6ynEZ>}xs( zA;dT)X6g5fxX~k7G~F;tIdk*^VD#4zT?!`w2J-ohsM>0*~V7{2eUtc#`g%`7z z^J{!`-QDu`>wV)*I@Y^_mF9z)$8T=tU;Xk(intU#mcp5_YA}1vmz?$g_TcXLxCS1K zeDq-V`vzU{8ti)L!Kh9u-W_dvhm zE|Tfxb-cCnWxh<-)9XgCSl?WHyuDs+o?rO*=|{g6z9W6p`esoWsO-Kze{J{W&py9b zxc)MmKbIJNW@4{dxUM|4d%h@MTqkIil+Me;tn|y4_0uVNG9hqn7>%G%)ssWuR>br5 z@UN@k+i82Y5?)#d|Go;I8hi5LC-ZN2_B&-^!OH9xj+5Ehx9TbFD64Z+t1PFjkD~@< zxtbkMb+kkHv7vnL>`Pg#V`uhDv&Q=9WJfBx+j`YHvFj=4j_PRV>c@ui-5ZK~nS^D9 ze0^k6xWCw0DldNQy^;GxHBfIUcC)z}l!s+)gBp2CJIo3_rLE>Hw;Y`3h@mI7ROnoN z1&I7d>SMb(<339D{Mb=SPuT2us`R|9KAvi86SN9*L_ey|o^wwX@b6lCs_R~TJx{V} z=R0}`e``p$QBQ6IQju4dft z=%rL(jXdSP>hJlHB}DFbbag>xdq;Qfs=|FX^>&r>MsDFTg7x;4`z>9xd!^+P*?p2; zdRs<)Jk_Z|Gr^B7z3)CrSD#N2Q|dD>%WKMg>?=jq>*FbPh^{d8^y6?weTGz_ z`utc^9rtT0@&mR|Fa7E~)$wCZ_1$Nl>O{qMiR`?bDcl`jYgd)t3uh@w_apV}x=+&8 zM`@Pj=bT;@HEV1+O>plib>r3YdAsw3s_>keT6?PPeob}!NIlhu-PL(Y-A%Mi<+=A% z=*OB;-ve8nr_>mUmtvvOOdzRZS?pt~4ZlY!N)xcAJ9Qe5}`_v4VIO!-kBhwjA}`jK|3kJ>8Sru-;nocE>* zzd}}PM~V6YVU@Y6@L1?tyGk9QE8M62IBpoY-_h0GY0Ir)_gR7(3bdSfy1yAj-N(1= zDfjAA_s47pKj&Ta!jBi!+EwZsHY?oH{pclh+@}d@Fv4;d-F?ebeS5v-mZ$rAM!l?U zZ|Uyygwlu8*T+@r=Q>p9DfJz`mb3I41V2C01a;S=!i~z0%FlV`DV}7W>f5C&%+dX5 zyOjPOlbtoCMo27s%6;3V^mnN0YX;XP)kNboH{ftUmWSy88ZJ z%SnR!*r)!bJIk@ped4JG;%!$m&gB>S!lSz{k=0eY<)cyej`Bo(?w6FB%C+2|a$e1d r{;A*D|9||7$9H7Y?&}Wq-AKc0B^R^HH$VLk(gCGo9ww;% literal 0 HcmV?d00001 diff --git a/cpld_maxv/output_files/RAM2E.asm.rpt b/cpld_maxv/output_files/RAM2E.asm.rpt new file mode 100644 index 0000000..839fec4 --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.asm.rpt @@ -0,0 +1,114 @@ +Assembler report for RAM2E +Wed Mar 10 21:02:34 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.pof + 6. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Wed Mar 10 21:02:34 2021 ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX V ; +; Device ; 5M240ZT100C5 ; ++-----------------------+---------------------------------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+-----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+-----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Security bit ; Off ; Off ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; +; In-System Programming Default Clamp State ; Tri-state ; Tri-state ; ++-----------------------------------------------------------------------------+-----------+---------------+ + + ++-----------------------------------------------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------------------------------------------+ +; File Name ; ++-----------------------------------------------------------------------------------------+ +; C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.pof ; ++-----------------------------------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------+ +; Assembler Device Options: C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.pof ; ++----------------+--------------------------------------------------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------------------------------------------------+ +; Device ; 5M240ZT100C5 ; +; JTAG usercode ; 0x0016E201 ; +; Checksum ; 0x0016E6F9 ; ++----------------+--------------------------------------------------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Assembler + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Wed Mar 10 21:02:33 2021 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 4516 megabytes + Info: Processing ended: Wed Mar 10 21:02:35 2021 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/cpld_maxv/output_files/RAM2E.done b/cpld_maxv/output_files/RAM2E.done new file mode 100644 index 0000000..e633e3f --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.done @@ -0,0 +1 @@ +Wed Mar 10 21:02:39 2021 diff --git a/cpld_maxv/output_files/RAM2E.fit.rpt b/cpld_maxv/output_files/RAM2E.fit.rpt new file mode 100644 index 0000000..cecc9b0 --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.fit.rpt @@ -0,0 +1,987 @@ +Fitter report for RAM2E +Wed Mar 10 21:02:32 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Pin-Out File + 6. Fitter Resource Usage Summary + 7. Input Pins + 8. Output Pins + 9. Bidir Pins + 10. I/O Bank Usage + 11. All Package Pins + 12. Output Pin Default Load For Reported TCO + 13. Fitter Resource Utilization by Entity + 14. Delay Chain Summary + 15. Control Signals + 16. Global & Other Fast Signals + 17. Non-Global High Fan-Out Signals + 18. Other Routing Usage Summary + 19. LAB Logic Elements + 20. LAB-wide Signals + 21. LAB Signals Sourced + 22. LAB Signals Sourced Out + 23. LAB Distinct Inputs + 24. Fitter Device Options + 25. Fitter Messages + 26. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; Fitter Summary ; ++---------------------------+-------------------------------------------------+ +; Fitter Status ; Successful - Wed Mar 10 21:02:32 2021 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX V ; +; Device ; 5M240ZT100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 189 / 240 ( 79 % ) ; +; Total pins ; 69 / 79 ( 87 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++---------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; 5M240ZT100C5 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Device I/O Standard ; 3.3-V LVCMOS ; ; +; Optimize Multi-Corner Timing ; On ; Off ; +; Fitter Effort ; Standard Fit ; Auto Fit ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; Slow Slew Rate ; Off ; Off ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.pin. + + ++------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+--------------------+ +; Resource ; Usage ; ++---------------------------------------------+--------------------+ +; Total logic elements ; 189 / 240 ( 79 % ) ; +; -- Combinational with no register ; 82 ; +; -- Register only ; 17 ; +; -- Combinational with a register ; 90 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 90 ; +; -- 3 input functions ; 43 ; +; -- 2 input functions ; 35 ; +; -- 1 input functions ; 3 ; +; -- 0 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 175 ; +; -- arithmetic mode ; 14 ; +; -- qfbk mode ; 9 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 14 ; +; -- asynchronous clear/load mode ; 0 ; +; ; ; +; Total registers ; 107 / 240 ( 45 % ) ; +; Total LABs ; 23 / 24 ( 96 % ) ; +; Logic elements in carry chains ; 15 ; +; Virtual pins ; 0 ; +; I/O pins ; 69 / 79 ( 87 % ) ; +; -- Clock pins ; 3 / 4 ( 75 % ) ; +; ; ; +; Global signals ; 1 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; +; Global clocks ; 1 / 4 ( 25 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 24% / 25% / 23% ; +; Peak interconnect usage (total/H/V) ; 24% / 25% / 23% ; +; Maximum fan-out ; 107 ; +; Highest non-global fan-out ; 35 ; +; Total fan-out ; 811 ; +; Average fan-out ; 3.13 ; ++---------------------------------------------+--------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; ++--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +; Ain[0] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[1] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[2] ; 43 ; 1 ; 6 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 107 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 4 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; ++--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; nCAS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nRAS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; nRWE ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ++---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Bidir Pins ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ +; RD[0] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; +; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; +; RD[2] ; 99 ; 2 ; 2 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; +; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; +; RD[4] ; 91 ; 2 ; 4 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; +; RD[5] ; 92 ; 2 ; 3 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; +; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; +; RD[7] ; 96 ; 2 ; 3 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; ++-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ + + ++-------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+-------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+-------------------+---------------+--------------+ +; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ; +; 2 ; 31 / 41 ( 76 % ) ; 3.3V ; -- ; ++----------+-------------------+---------------+--------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; 1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 2 ; 0 ; 1 ; nRWE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 3 ; 1 ; 1 ; nCAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 4 ; 2 ; 1 ; CKE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 5 ; 3 ; 1 ; nRAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 6 ; 4 ; 1 ; BA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 7 ; 5 ; 1 ; RA[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 8 ; 6 ; 1 ; nCS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 12 ; 7 ; 1 ; C14M ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 13 ; ; ; VCCINT ; power ; ; 1.8V ; -- ; ; -- ; -- ; +; 14 ; 8 ; 1 ; BA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 15 ; 9 ; 1 ; RA[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 16 ; 10 ; 1 ; RA[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 17 ; 11 ; 1 ; RA[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 18 ; 12 ; 1 ; RA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 19 ; 13 ; 1 ; RA[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 20 ; 14 ; 1 ; RA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 21 ; 15 ; 1 ; RA[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; 26 ; 20 ; 1 ; RA[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 27 ; 21 ; 1 ; RA[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 28 ; 22 ; 1 ; nEN80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 29 ; 23 ; 1 ; RA[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 30 ; 24 ; 1 ; RA[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 33 ; 25 ; 1 ; nWE80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 34 ; 26 ; 1 ; Ain[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 35 ; 27 ; 1 ; Din[7] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 36 ; 28 ; 1 ; Din[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 37 ; 29 ; 1 ; PHI1 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 38 ; 30 ; 1 ; Din[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 39 ; 31 ; 1 ; Ain[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 40 ; 32 ; 1 ; Din[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 41 ; 33 ; 1 ; Din[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 42 ; 34 ; 1 ; Din[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 43 ; 35 ; 1 ; Ain[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 44 ; 36 ; 1 ; Ain[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 46 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; On ; +; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; On ; +; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 60 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 62 ; 50 ; 2 ; Vout[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 63 ; ; ; VCCINT ; power ; ; 1.8V ; -- ; ; -- ; -- ; +; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; 67 ; 53 ; 2 ; Vout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 68 ; 54 ; 2 ; Vout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 69 ; 55 ; 2 ; Vout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 70 ; 56 ; 2 ; Vout[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 71 ; 57 ; 2 ; Vout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 72 ; 58 ; 2 ; Dout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 73 ; 59 ; 2 ; Dout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 74 ; 60 ; 2 ; Dout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; +; 75 ; 61 ; 2 ; Dout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 76 ; 62 ; 2 ; Dout[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 77 ; 63 ; 2 ; Dout[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 84 ; 68 ; 2 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 85 ; 69 ; 2 ; Dout[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 91 ; 75 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 92 ; 76 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 96 ; 78 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 97 ; 79 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 98 ; 80 ; 2 ; DQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 99 ; 81 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; +; 100 ; 82 ; 2 ; DQMH ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; ++----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------+-------+------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------+-------+------------------------+ +; 3.3-V LVTTL ; 10 pF ; Not Available ; +; 3.3-V LVCMOS ; 10 pF ; Not Available ; +; 2.5 V ; 10 pF ; Not Available ; +; 1.8 V ; 10 pF ; Not Available ; +; 1.5 V ; 10 pF ; Not Available ; +; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ; +; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ; +; 1.2 V ; 10 pF ; Not Available ; +; LVDS_E_3R ; 10 pF ; Not Available ; +; RSDS_E_3R ; 10 pF ; Not Available ; ++----------------------------+-------+------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ +; |RAM2E ; 189 (189) ; 107 ; 1 ; 69 ; 0 ; 82 (82) ; 17 (17) ; 90 (90) ; 15 (15) ; 9 (9) ; |RAM2E ; work ; +; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; work ; +; |UFM_altufm_none_e4r:UFM_altufm_none_e4r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component ; work ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------+ +; Delay Chain Summary ; ++---------+----------+---------------+ +; Name ; Pin Type ; Pad to Core 0 ; ++---------+----------+---------------+ +; nWE ; Input ; (0) ; +; nEN80 ; Input ; (0) ; +; PHI1 ; Input ; (1) ; +; C14M ; Input ; (0) ; +; nWE80 ; Input ; (0) ; +; Ain[0] ; Input ; (0) ; +; Ain[1] ; Input ; (0) ; +; Ain[2] ; Input ; (0) ; +; Ain[3] ; Input ; (0) ; +; Ain[4] ; Input ; (0) ; +; Ain[5] ; Input ; (0) ; +; Ain[6] ; Input ; (0) ; +; Ain[7] ; Input ; (0) ; +; Din[6] ; Input ; (0) ; +; Din[4] ; Input ; (0) ; +; Din[5] ; Input ; (0) ; +; Din[7] ; Input ; (0) ; +; Din[0] ; Input ; (0) ; +; Din[1] ; Input ; (0) ; +; Din[2] ; Input ; (0) ; +; Din[3] ; Input ; (0) ; +; nC07X ; Input ; (0) ; +; Dout[0] ; Output ; -- ; +; Dout[1] ; Output ; -- ; +; Dout[2] ; Output ; -- ; +; Dout[3] ; Output ; -- ; +; Dout[4] ; Output ; -- ; +; Dout[5] ; Output ; -- ; +; Dout[6] ; Output ; -- ; +; Dout[7] ; Output ; -- ; +; nDOE ; Output ; -- ; +; Vout[0] ; Output ; -- ; +; Vout[1] ; Output ; -- ; +; Vout[2] ; Output ; -- ; +; Vout[3] ; Output ; -- ; +; Vout[4] ; Output ; -- ; +; Vout[5] ; Output ; -- ; +; Vout[6] ; Output ; -- ; +; Vout[7] ; Output ; -- ; +; nVOE ; Output ; -- ; +; CKE ; Output ; -- ; +; nCS ; Output ; -- ; +; nRAS ; Output ; -- ; +; nCAS ; Output ; -- ; +; nRWE ; Output ; -- ; +; BA[0] ; Output ; -- ; +; BA[1] ; Output ; -- ; +; RA[0] ; Output ; -- ; +; RA[1] ; Output ; -- ; +; RA[2] ; Output ; -- ; +; RA[3] ; Output ; -- ; +; RA[4] ; Output ; -- ; +; RA[5] ; Output ; -- ; +; RA[6] ; Output ; -- ; +; RA[7] ; Output ; -- ; +; RA[8] ; Output ; -- ; +; RA[9] ; Output ; -- ; +; RA[10] ; Output ; -- ; +; RA[11] ; Output ; -- ; +; DQML ; Output ; -- ; +; DQMH ; Output ; -- ; +; RD[0] ; Bidir ; (0) ; +; RD[1] ; Bidir ; (0) ; +; RD[2] ; Bidir ; (0) ; +; RD[3] ; Bidir ; (0) ; +; RD[4] ; Bidir ; (0) ; +; RD[5] ; Bidir ; (0) ; +; RD[6] ; Bidir ; (0) ; +; RD[7] ; Bidir ; (0) ; ++---------+----------+---------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++-------------+-------------+---------+---------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++-------------+-------------+---------+---------------+--------+----------------------+------------------+ +; C14M ; PIN_12 ; 107 ; Clock ; yes ; Global Clock ; GCLK0 ; +; CS[0]~2 ; LC_X6_Y2_N4 ; 3 ; Clock enable ; no ; -- ; -- ; +; Equal9~0 ; LC_X6_Y2_N2 ; 14 ; Clock enable ; no ; -- ; -- ; +; Equal9~1 ; LC_X7_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ; +; RA[4]~1 ; LC_X2_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ; +; RDOE ; LC_X2_Y3_N8 ; 8 ; Output enable ; no ; -- ; -- ; +; RWBank[4]~1 ; LC_X4_Y2_N1 ; 13 ; Clock enable ; no ; -- ; -- ; +; RWMask[4]~2 ; LC_X5_Y2_N6 ; 8 ; Clock enable ; no ; -- ; -- ; +; S[2] ; LC_X7_Y2_N1 ; 20 ; Sync. clear ; no ; -- ; -- ; +; UFMD[8]~5 ; LC_X5_Y1_N6 ; 7 ; Clock enable ; no ; -- ; -- ; ++-------------+-------------+---------+---------------+--------+----------------------+------------------+ + + ++---------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++------+----------+---------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; ++------+----------+---------+----------------------+------------------+ +; C14M ; PIN_12 ; 107 ; Global Clock ; GCLK0 ; ++------+----------+---------+----------------------+------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------------------------------------------------------------------------------------------+---------+ +; Name ; Fan-Out ; ++----------------------------------------------------------------------------------------------+---------+ +; S[0] ; 35 ; +; S[1] ; 30 ; +; Equal9~4 ; 23 ; +; S[3] ; 22 ; +; S[2] ; 20 ; +; Equal9~0 ; 14 ; +; RWBank[4]~1 ; 13 ; +; Din[1] ; 11 ; +; Din[2] ; 10 ; +; Din[0] ; 10 ; +; CS[1] ; 9 ; +; FS[4] ; 9 ; +; Din[3] ; 8 ; +; Din[7] ; 8 ; +; Din[6] ; 8 ; +; RWMask[4]~2 ; 8 ; +; RDOE ; 8 ; +; SetRWBankFF ; 8 ; +; CS[0] ; 8 ; +; RWSel ; 8 ; +; RA[4]~1 ; 8 ; +; Equal9~1 ; 8 ; +; Din[5] ; 7 ; +; Din[4] ; 7 ; +; UFMD[8]~5 ; 7 ; +; always1~9 ; 7 ; +; CS[2] ; 7 ; +; FS[5] ; 7 ; +; UFMReqErase ; 6 ; +; UFMInitDone ; 6 ; +; FS[0] ; 6 ; +; always1~1 ; 5 ; +; FS[3] ; 5 ; +; FS[2]~27 ; 5 ; +; FS[7]~23 ; 5 ; +; FS[15] ; 5 ; +; FS[14] ; 5 ; +; FS[13] ; 5 ; +; PHI1 ; 4 ; +; nEN80 ; 4 ; +; UFMD[13] ; 4 ; +; CmdTout[0] ; 4 ; +; UFMEraseEN ; 4 ; +; UFMPrgmEN ; 4 ; +; Equal4~0 ; 4 ; +; Equal9~3 ; 4 ; +; DRCLK~0 ; 4 ; +; Equal9~2 ; 4 ; +; UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component|wire_maxii_ufm_block1_drdout ; 4 ; +; S[3]~9 ; 3 ; +; UFMD[11] ; 3 ; +; UFMD[9] ; 3 ; +; UFMD[10] ; 3 ; +; always1~6 ; 3 ; +; UFMD[12] ; 3 ; +; UFMD[8] ; 3 ; +; CS[0]~2 ; 3 ; +; CmdTout[1] ; 3 ; +; CS~0 ; 3 ; +; always2~7 ; 3 ; +; RWMaskSet~0 ; 3 ; +; S~4 ; 3 ; +; Ready ; 3 ; +; S[3]~2 ; 3 ; +; always1~2 ; 3 ; +; always1~0 ; 3 ; +; Equal10~4 ; 3 ; +; FS[2] ; 3 ; +; FS[1] ; 3 ; +; always2~0 ; 3 ; +; Ready~0 ; 3 ; +; Equal10~1 ; 3 ; +; FS[12]~1 ; 3 ; +; RD[7]~7 ; 2 ; +; RD[6]~6 ; 2 ; +; RD[5]~5 ; 2 ; +; RD[4]~4 ; 2 ; +; RD[3]~3 ; 2 ; +; RD[2]~2 ; 2 ; +; RD[1]~1 ; 2 ; +; RD[0]~0 ; 2 ; +; nWE80 ; 2 ; +; nWE ; 2 ; +; UFMD[14] ; 2 ; +; UFMEraseEN~0 ; 2 ; +; RWMask[4]~0 ; 2 ; +; UFMInitDone~0 ; 2 ; +; CmdTout[2] ; 2 ; +; Equal39~0 ; 2 ; +; RWMaskSet~1 ; 2 ; +; Equal27~1 ; 2 ; +; UFMBitbang~0 ; 2 ; +; S~3 ; 2 ; +; UFMBusyReg ; 2 ; +; always1~3 ; 2 ; +; UFMD[8]~4 ; 2 ; +; RWBank[6] ; 2 ; +; nCS~4 ; 2 ; +; nCS~3 ; 2 ; +; Equal12~0 ; 2 ; +; FS[7] ; 2 ; +; FS[6] ; 2 ; +; Equal10~2 ; 2 ; +; FS[11] ; 2 ; +; FS[10] ; 2 ; +; FS[9] ; 2 ; +; FS[8] ; 2 ; +; FS[12] ; 2 ; +; CKE~0 ; 2 ; +; UFMErase ; 2 ; +; UFMProgram ; 2 ; +; DRDIn ; 2 ; +; RA[3]~reg0 ; 2 ; +; RA[0]~reg0 ; 2 ; +; UFMProgram~_wirecell ; 1 ; +; UFMErase~_wirecell ; 1 ; +; nC07X ; 1 ; +; Ain[7] ; 1 ; +; Ain[6] ; 1 ; +; Ain[5] ; 1 ; +; Ain[4] ; 1 ; +; Ain[3] ; 1 ; +; Ain[2] ; 1 ; +; Ain[1] ; 1 ; +; Ain[0] ; 1 ; +; ~GND ; 1 ; +; RWMaskSet ; 1 ; +; always1~8 ; 1 ; +; always1~7 ; 1 ; +; Ready~1 ; 1 ; +; UFMReqErase~3 ; 1 ; +; UFMReqErase~2 ; 1 ; +; UFMReqErase~1 ; 1 ; +; UFMReqErase~0 ; 1 ; +; always1~5 ; 1 ; +; always1~4 ; 1 ; +; Add3~0 ; 1 ; +; always2~13 ; 1 ; +; Equal39~1 ; 1 ; +; always2~12 ; 1 ; +; always2~11 ; 1 ; +; always2~10 ; 1 ; +; always2~9 ; 1 ; +; always2~8 ; 1 ; +; always2~6 ; 1 ; +; always2~5 ; 1 ; +; always2~4 ; 1 ; +; always2~3 ; 1 ; +; always2~2 ; 1 ; +; always2~1 ; 1 ; +; RWSel~0 ; 1 ; +; RWMask[6] ; 1 ; +; RWMask[3] ; 1 ; +; RWMask[2] ; 1 ; +; RWMask[1] ; 1 ; +; RWMask[0] ; 1 ; +; RWMask[7] ; 1 ; +; RWMask[5] ; 1 ; +; RWMask[4] ; 1 ; +; Add1~0 ; 1 ; +; PHI1reg ; 1 ; +; UFMErase~0 ; 1 ; +; RTPBusyReg ; 1 ; +; UFMProgram~0 ; 1 ; +; DRCLKPulse ; 1 ; +; DRCLK~2 ; 1 ; +; DRCLK~1 ; 1 ; +; Equal27~0 ; 1 ; +; UFMBitbang ; 1 ; +; DQML~0 ; 1 ; +; RWBank[3] ; 1 ; +; RA~11 ; 1 ; +; RWBank[2] ; 1 ; +; RWBank[1] ; 1 ; +; RWBank[0] ; 1 ; +; RWBank[7] ; 1 ; +; RWBank[5] ; 1 ; +; RWBank[4] ; 1 ; +; nRWE~1 ; 1 ; +; nRWE~0 ; 1 ; +; nCAS~2 ; 1 ; +; nCAS~1 ; 1 ; +; nCAS~0 ; 1 ; +; FS[3]~29COUT1_46 ; 1 ; +; FS[3]~29 ; 1 ; +; FS[1]~25COUT1_44 ; 1 ; +; FS[1]~25 ; 1 ; +; FS[6]~21COUT1_52 ; 1 ; +; FS[6]~21 ; 1 ; +; Equal10~3 ; 1 ; +; nCS~2 ; 1 ; +; FS[5]~19COUT1_50 ; 1 ; +; FS[5]~19 ; 1 ; +; FS[4]~17COUT1_48 ; 1 ; +; FS[4]~17 ; 1 ; +; nCS~1 ; 1 ; +; nCS~0 ; 1 ; +; CKE~2 ; 1 ; +; FS[14]~13COUT1_64 ; 1 ; +; FS[14]~13 ; 1 ; +; FS[13]~11COUT1_62 ; 1 ; +; FS[13]~11 ; 1 ; +; FS[11]~9COUT1_60 ; 1 ; +; FS[11]~9 ; 1 ; +; FS[10]~7COUT1_58 ; 1 ; +; FS[10]~7 ; 1 ; +; Equal10~0 ; 1 ; +; FS[9]~5COUT1_56 ; 1 ; +; FS[9]~5 ; 1 ; +; FS[8]~3COUT1_54 ; 1 ; +; FS[8]~3 ; 1 ; +; CKE~1 ; 1 ; +; ARShift ; 1 ; +; ARCLK ; 1 ; +; DRShift ; 1 ; +; DRCLK ; 1 ; +; DQMH~reg0 ; 1 ; +; DQML~reg0 ; 1 ; +; RA[11]~reg0 ; 1 ; +; RA[10]~reg0 ; 1 ; +; RA[9]~reg0 ; 1 ; +; RA[8]~reg0 ; 1 ; +; RA[7]~reg0 ; 1 ; +; RA[6]~reg0 ; 1 ; +; RA[5]~reg0 ; 1 ; +; RA[4]~reg0 ; 1 ; +; RA[2]~reg0 ; 1 ; +; RA[1]~reg0 ; 1 ; +; BA[1]~reg0 ; 1 ; +; BA[0]~reg0 ; 1 ; +; nRWE~reg0 ; 1 ; +; nCAS~reg0 ; 1 ; +; nRAS~reg0 ; 1 ; +; nCS~reg0 ; 1 ; +; CKE~reg0 ; 1 ; +; Vout[7]~reg0 ; 1 ; +; Vout[6]~reg0 ; 1 ; +; Vout[5]~reg0 ; 1 ; +; Vout[4]~reg0 ; 1 ; +; Vout[3]~reg0 ; 1 ; +; Vout[2]~reg0 ; 1 ; +; Vout[1]~reg0 ; 1 ; +; Vout[0]~reg0 ; 1 ; +; comb~0 ; 1 ; +; DOEEN ; 1 ; +; Dout[7]~reg0 ; 1 ; +; Dout[6]~reg0 ; 1 ; +; Dout[5]~reg0 ; 1 ; +; Dout[4]~reg0 ; 1 ; +; Dout[3]~reg0 ; 1 ; +; Dout[2]~reg0 ; 1 ; +; Dout[1]~reg0 ; 1 ; +; Dout[0]~reg0 ; 1 ; +; UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component|wire_maxii_ufm_block1_bgpbusy ; 1 ; +; UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component|wire_maxii_ufm_block1_busy ; 1 ; ++----------------------------------------------------------------------------------------------+---------+ + + ++--------------------------------------------------+ +; Other Routing Usage Summary ; ++-----------------------------+--------------------+ +; Other Routing Resource Type ; Usage ; ++-----------------------------+--------------------+ +; C4s ; 150 / 784 ( 19 % ) ; +; Direct links ; 53 / 888 ( 6 % ) ; +; Global clocks ; 1 / 4 ( 25 % ) ; +; LAB clocks ; 6 / 32 ( 19 % ) ; +; LUT chains ; 17 / 216 ( 8 % ) ; +; Local interconnects ; 305 / 888 ( 34 % ) ; +; R4s ; 142 / 704 ( 20 % ) ; ++-----------------------------+--------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+------------------------------+ +; Number of Logic Elements (Average = 8.22) ; Number of LABs (Total = 23) ; ++--------------------------------------------+------------------------------+ +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 2 ; +; 8 ; 3 ; +; 9 ; 2 ; +; 10 ; 12 ; ++--------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 1.57) ; Number of LABs (Total = 23) ; ++------------------------------------+------------------------------+ +; 1 Clock ; 23 ; +; 1 Clock enable ; 11 ; +; 2 Clock enables ; 2 ; ++------------------------------------+------------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++---------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 8.61) ; Number of LABs (Total = 23) ; ++---------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 1 ; +; 7 ; 2 ; +; 8 ; 3 ; +; 9 ; 1 ; +; 10 ; 11 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; ++---------------------------------------------+------------------------------+ + + ++--------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 6.17) ; Number of LABs (Total = 23) ; ++-------------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 1 ; +; 5 ; 4 ; +; 6 ; 5 ; +; 7 ; 2 ; +; 8 ; 6 ; +; 9 ; 0 ; +; 10 ; 2 ; ++-------------------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 11.57) ; Number of LABs (Total = 23) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 2 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 3 ; +; 8 ; 0 ; +; 9 ; 3 ; +; 10 ; 0 ; +; 11 ; 1 ; +; 12 ; 1 ; +; 13 ; 2 ; +; 14 ; 4 ; +; 15 ; 2 ; +; 16 ; 0 ; +; 17 ; 1 ; +; 18 ; 0 ; +; 19 ; 2 ; +; 20 ; 0 ; +; 21 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (119006): Selected device 5M240ZT100C5 for design "RAM2E" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device 5M80ZT100C5 is compatible + Info (176445): Device 5M80ZT100I5 is compatible + Info (176445): Device 5M160ZT100C5 is compatible + Info (176445): Device 5M160ZT100I5 is compatible + Info (176445): Device 5M240ZT100I5 is compatible + Info (176445): Device 5M570ZT100C5 is compatible + Info (176445): Device 5M570ZT100I5 is compatible +Info (332104): Reading SDC File: 'constraints.sdc' +Warning (332060): Node: DRCLK was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: ARCLK was determined to be a clock but was found without an associated clock assignment. +Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements +Info (332111): Found 1 clocks + Info (332111): Period Clock Name + Info (332111): ======== ============ + Info (332111): 69.841 C14M +Info (186079): Completed User Assigned Global Signals Promotion Operation +Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 +Info (186079): Completed Auto Global Promotion Operation +Info (176234): Starting register packing +Info (186391): Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option +Info (186468): Started processing fast register assignments +Info (186469): Finished processing fast register assignments +Info (176235): Finished register packing +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 +Info (170193): Fitter routing operations beginning +Info (170089): 2e+01 ns of routing delay (approximately 1.0% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. +Info (170195): Router estimated average interconnect usage is 21% of the available device resources + Info (170196): Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 +Info (11888): Total time spent on timing analysis during the Fitter is 0.22 seconds. +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 +Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info (144001): Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 4766 megabytes + Info: Processing ended: Wed Mar 10 21:02:32 2021 + Info: Elapsed time: 00:00:04 + Info: Total CPU time (on all processors): 00:00:03 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.fit.smsg. + + diff --git a/cpld_maxv/output_files/RAM2E.fit.smsg b/cpld_maxv/output_files/RAM2E.fit.smsg new file mode 100644 index 0000000..6df10d8 --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.fit.smsg @@ -0,0 +1,4 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176244): Moving registers into LUTs to improve timing and density +Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00 diff --git a/cpld_maxv/output_files/RAM2E.fit.summary b/cpld_maxv/output_files/RAM2E.fit.summary new file mode 100644 index 0000000..2e6c39d --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.fit.summary @@ -0,0 +1,11 @@ +Fitter Status : Successful - Wed Mar 10 21:02:32 2021 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : RAM2E +Top-level Entity Name : RAM2E +Family : MAX V +Device : 5M240ZT100C5 +Timing Models : Final +Total logic elements : 189 / 240 ( 79 % ) +Total pins : 69 / 79 ( 87 % ) +Total virtual pins : 0 +UFM blocks : 1 / 1 ( 100 % ) diff --git a/cpld_maxv/output_files/RAM2E.flow.rpt b/cpld_maxv/output_files/RAM2E.flow.rpt new file mode 100644 index 0000000..3c3bd25 --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.flow.rpt @@ -0,0 +1,125 @@ +Flow report for RAM2E +Wed Mar 10 21:02:38 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-----------------------------------------------------------------------------+ +; Flow Summary ; ++---------------------------+-------------------------------------------------+ +; Flow Status ; Successful - Wed Mar 10 21:02:34 2021 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX V ; +; Device ; 5M240ZT100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 189 / 240 ( 79 % ) ; +; Total pins ; 69 / 79 ( 87 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++---------------------------+-------------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 03/10/2021 21:02:25 ; +; Main task ; Compilation ; +; Revision Name ; RAM2E ; ++-------------------+---------------------+ + + ++----------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++------------------------------------+--------------------------------+---------------+-------------+------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++------------------------------------+--------------------------------+---------------+-------------+------------+ +; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 10995770589204.161542814406368 ; -- ; -- ; -- ; +; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; +; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; +; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; OPTIMIZE_MULTI_CORNER_TIMING ; On ; Off ; -- ; -- ; +; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ; +; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; +; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ; +; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ; +; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ; ++------------------------------------+--------------------------------+---------------+-------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:05 ; 1.0 ; 4567 MB ; 00:00:02 ; +; Fitter ; 00:00:04 ; 1.0 ; 4766 MB ; 00:00:03 ; +; Assembler ; 00:00:01 ; 1.0 ; 4516 MB ; 00:00:01 ; +; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4514 MB ; 00:00:02 ; +; Total ; 00:00:12 ; -- ; -- ; 00:00:08 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; DESKTOP-DG54GN4 ; Windows 7 ; 6.2 ; x86_64 ; +; Fitter ; DESKTOP-DG54GN4 ; Windows 7 ; 6.2 ; x86_64 ; +; Assembler ; DESKTOP-DG54GN4 ; Windows 7 ; 6.2 ; x86_64 ; +; TimeQuest Timing Analyzer ; DESKTOP-DG54GN4 ; Windows 7 ; 6.2 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E +quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E +quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E +quartus_sta RAM2E -c RAM2E + + + diff --git a/cpld_maxv/output_files/RAM2E.jdi b/cpld_maxv/output_files/RAM2E.jdi new file mode 100644 index 0000000..3856185 --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/cpld_maxv/output_files/RAM2E.map.rpt b/cpld_maxv/output_files/RAM2E.map.rpt new file mode 100644 index 0000000..5543894 --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.map.rpt @@ -0,0 +1,305 @@ +Analysis & Synthesis report for RAM2E +Wed Mar 10 21:02:27 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis IP Cores Summary + 9. General Register Statistics + 10. Inverted Register Statistics + 11. Multiplexer Restructuring Statistics (Restructuring Performed) + 12. Port Connectivity Checks: "UFM:UFM_inst" + 13. Analysis & Synthesis Messages + 14. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+-------------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Wed Mar 10 21:02:27 2021 ; +; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX V ; +; Total logic elements ; 198 ; +; Total pins ; 69 ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------------+-------------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 5M240ZT100C5 ; ; +; Top-level entity name ; RAM2E ; RAM2E ; +; Family name ; MAX V ; Cyclone IV GX ; +; Safe State Machine ; On ; Off ; +; Parallel Synthesis ; Off ; On ; +; Power-Up Don't Care ; Off ; On ; +; Analysis & Synthesis Message Level ; High ; Medium ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; NOT Gate Push-Back ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Block Design Naming ; Auto ; Auto ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+----------------------------------------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------+----------------------------------------------------------------------------+---------+ +; RAM2E.v ; yes ; User Verilog HDL File ; C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/RAM2E.v ; ; +; RAM2E.mif ; yes ; User Memory Initialization File ; C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/RAM2E.mif ; ; +; UFM.v ; yes ; User Wizard-Generated File ; C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/UFM.v ; ; ++----------------------------------+-----------------+----------------------------------+----------------------------------------------------------------------------+---------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Total logic elements ; 198 ; +; -- Combinational with no register ; 91 ; +; -- Register only ; 26 ; +; -- Combinational with a register ; 81 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 90 ; +; -- 3 input functions ; 43 ; +; -- 2 input functions ; 35 ; +; -- 1 input functions ; 3 ; +; -- 0 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 184 ; +; -- arithmetic mode ; 14 ; +; -- qfbk mode ; 0 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 1 ; +; -- asynchronous clear/load mode ; 0 ; +; ; ; +; Total registers ; 107 ; +; Total logic cells in carry chains ; 15 ; +; I/O pins ; 69 ; +; UFM blocks ; 1 ; +; Maximum fan-out node ; C14M ; +; Maximum fan-out ; 107 ; +; Total fan-out ; 815 ; +; Average fan-out ; 3.04 ; ++---------------------------------------------+-------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ +; |RAM2E ; 198 (198) ; 107 ; 1 ; 69 ; 0 ; 91 (91) ; 26 (26) ; 81 (81) ; 15 (15) ; 0 (0) ; |RAM2E ; work ; +; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; work ; +; |UFM_altufm_none_e4r:UFM_altufm_none_e4r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component ; work ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+--------------+---------+--------------+--------------+---------------------+------------------------------------------------------------------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+--------------+---------+--------------+--------------+---------------------+------------------------------------------------------------------------+ +; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM2E|UFM:UFM_inst ; C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/UFM.v ; ++--------+--------------+---------+--------------+--------------+---------------------+------------------------------------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 107 ; +; Number of registers using Synchronous Clear ; 1 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 56 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------+---------+ +; nCS~reg0 ; 1 ; +; nRAS~reg0 ; 1 ; +; nCAS~reg0 ; 1 ; +; nRWE~reg0 ; 1 ; +; DQML~reg0 ; 1 ; +; DQMH~reg0 ; 1 ; +; Total number of inverted registers = 6 ; ; ++----------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[3] ; +; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[2] ; +; 16:1 ; 8 bits ; 80 LEs ; 8 LEs ; 72 LEs ; Yes ; |RAM2E|RA[4]~reg0 ; +; 9:1 ; 8 bits ; 48 LEs ; 16 LEs ; 32 LEs ; Yes ; |RAM2E|RWMask[4] ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "UFM:UFM_inst" ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ +; ardin ; Input ; Info ; Stuck at GND ; +; oscena ; Input ; Info ; Stuck at VCC ; +; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Wed Mar 10 21:02:22 2021 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (12021): Found 1 design units, including 1 entities, in source file ram2e.v + Info (12023): Found entity 1: RAM2E +Info (12021): Found 2 design units, including 2 entities, in source file ufm.v + Info (12023): Found entity 1: UFM_altufm_none_e4r + Info (12023): Found entity 2: UFM +Info (12127): Elaborating entity "RAM2E" for the top level hierarchy +Warning (10230): Verilog HDL assignment warning at RAM2E.v(100): truncated value with size 32 to match size of target (16) +Warning (10230): Verilog HDL assignment warning at RAM2E.v(103): truncated value with size 32 to match size of target (4) +Warning (10230): Verilog HDL assignment warning at RAM2E.v(544): truncated value with size 32 to match size of target (3) +Warning (10230): Verilog HDL assignment warning at RAM2E.v(561): truncated value with size 32 to match size of target (3) +Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" +Info (12128): Elaborating entity "UFM_altufm_none_e4r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component" +Info (21057): Implemented 268 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 22 input pins + Info (21059): Implemented 39 output pins + Info (21060): Implemented 8 bidirectional pins + Info (21061): Implemented 198 logic cells + Info (21070): Implemented 1 User Flash Memory blocks +Info (144001): Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.map.smsg +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 4567 megabytes + Info: Processing ended: Wed Mar 10 21:02:27 2021 + Info: Elapsed time: 00:00:05 + Info: Total CPU time (on all processors): 00:00:02 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld_maxv/output_files/RAM2E.map.smsg. + + diff --git a/cpld_maxv/output_files/RAM2E.map.smsg b/cpld_maxv/output_files/RAM2E.map.smsg new file mode 100644 index 0000000..11cd769 --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.map.smsg @@ -0,0 +1,3 @@ +Warning (10273): Verilog HDL warning at RAM2E.v(38): extended using "x" or "z" +Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword +Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword diff --git a/cpld_maxv/output_files/RAM2E.map.summary b/cpld_maxv/output_files/RAM2E.map.summary new file mode 100644 index 0000000..d1aea18 --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.map.summary @@ -0,0 +1,9 @@ +Analysis & Synthesis Status : Successful - Wed Mar 10 21:02:27 2021 +Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition +Revision Name : RAM2E +Top-level Entity Name : RAM2E +Family : MAX V +Total logic elements : 198 +Total pins : 69 +Total virtual pins : 0 +UFM blocks : 1 / 1 ( 100 % ) diff --git a/cpld_maxv/output_files/RAM2E.pin b/cpld_maxv/output_files/RAM2E.pin new file mode 100644 index 0000000..ca74001 --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.pin @@ -0,0 +1,164 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.8V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +CHIP "RAM2E" ASSIGNED TO AN: 5M240ZT100C5 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : 1 : gnd : : : : +nRWE : 2 : output : 3.3-V LVCMOS : : 1 : Y +nCAS : 3 : output : 3.3-V LVCMOS : : 1 : Y +CKE : 4 : output : 3.3-V LVCMOS : : 1 : Y +nRAS : 5 : output : 3.3-V LVCMOS : : 1 : Y +BA[0] : 6 : output : 3.3-V LVCMOS : : 1 : Y +RA[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y +nCS : 8 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 9 : power : : 3.3V : 1 : +GND : 10 : gnd : : : : +GND : 11 : gnd : : : : +C14M : 12 : input : 3.3-V LVCMOS : : 1 : Y +VCCINT : 13 : power : : 1.8V : : +BA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y +RA[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y +RA[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y +RA[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y +RA[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y +RA[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y +RA[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y +RA[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y +TMS : 22 : input : : : 1 : +TDI : 23 : input : : : 1 : +TCK : 24 : input : : : 1 : +TDO : 25 : output : : : 1 : +RA[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y +RA[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y +nEN80 : 28 : input : 3.3-V LVCMOS : : 1 : Y +RA[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y +RA[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 31 : power : : 3.3V : 1 : +GND : 32 : gnd : : : : +nWE80 : 33 : input : 3.3-V LVCMOS : : 1 : Y +Ain[5] : 34 : input : 3.3-V LVCMOS : : 1 : Y +Din[7] : 35 : input : 3.3-V LVCMOS : : 1 : Y +Din[6] : 36 : input : 3.3-V LVCMOS : : 1 : Y +PHI1 : 37 : input : 3.3-V LVCMOS : : 1 : Y +Din[0] : 38 : input : 3.3-V LVCMOS : : 1 : Y +Ain[6] : 39 : input : 3.3-V LVCMOS : : 1 : Y +Din[1] : 40 : input : 3.3-V LVCMOS : : 1 : Y +Din[3] : 41 : input : 3.3-V LVCMOS : : 1 : Y +Din[2] : 42 : input : 3.3-V LVCMOS : : 1 : Y +Ain[2] : 43 : input : 3.3-V LVCMOS : : 1 : Y +Ain[4] : 44 : input : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 45 : power : : 3.3V : 1 : +GND : 46 : gnd : : : : +Ain[3] : 47 : input : 3.3-V LVCMOS : : 1 : Y +Din[4] : 48 : input : 3.3-V LVCMOS : : 1 : Y +Din[5] : 49 : input : 3.3-V LVCMOS : : 1 : Y +nVOE : 50 : output : 3.3-V LVCMOS : : 1 : Y +nWE : 51 : input : 3.3-V LVCMOS : : 1 : Y +nC07X : 52 : input : 3.3-V LVCMOS : : 2 : Y +Ain[7] : 53 : input : 3.3-V LVCMOS : : 2 : Y +Ain[1] : 54 : input : 3.3-V LVCMOS : : 2 : Y +nDOE : 55 : output : 3.3-V LVCMOS : : 2 : Y +Ain[0] : 56 : input : 3.3-V LVCMOS : : 2 : Y +Vout[7] : 57 : output : 3.3-V LVCMOS : : 2 : Y +Vout[6] : 58 : output : 3.3-V LVCMOS : : 2 : Y +VCCIO2 : 59 : power : : 3.3V : 2 : +GND : 60 : gnd : : : : +GND* : 61 : : : : 2 : +Vout[3] : 62 : output : 3.3-V LVCMOS : : 2 : Y +VCCINT : 63 : power : : 1.8V : : +GND* : 64 : : : : 2 : +GND : 65 : gnd : : : : +GND* : 66 : : : : 2 : +Vout[1] : 67 : output : 3.3-V LVCMOS : : 2 : Y +Vout[5] : 68 : output : 3.3-V LVCMOS : : 2 : Y +Vout[2] : 69 : output : 3.3-V LVCMOS : : 2 : Y +Vout[0] : 70 : output : 3.3-V LVCMOS : : 2 : Y +Vout[4] : 71 : output : 3.3-V LVCMOS : : 2 : Y +Dout[5] : 72 : output : 3.3-V LVCMOS : : 2 : Y +Dout[4] : 73 : output : 3.3-V LVCMOS : : 2 : Y +Dout[2] : 74 : output : 3.3-V LVCMOS : : 2 : Y +Dout[3] : 75 : output : 3.3-V LVCMOS : : 2 : Y +Dout[1] : 76 : output : 3.3-V LVCMOS : : 2 : Y +Dout[0] : 77 : output : 3.3-V LVCMOS : : 2 : Y +GND* : 78 : : : : 2 : +GND : 79 : gnd : : : : +VCCIO2 : 80 : power : : 3.3V : 2 : +GND* : 81 : : : : 2 : +GND* : 82 : : : : 2 : +GND* : 83 : : : : 2 : +Dout[6] : 84 : output : 3.3-V LVCMOS : : 2 : Y +Dout[7] : 85 : output : 3.3-V LVCMOS : : 2 : Y +GND* : 86 : : : : 2 : +GND* : 87 : : : : 2 : +GND* : 88 : : : : 2 : +RD[3] : 89 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[4] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[5] : 92 : bidir : 3.3-V LVCMOS : : 2 : Y +GND : 93 : gnd : : : : +VCCIO2 : 94 : power : : 3.3V : 2 : +RD[6] : 95 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[7] : 96 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[0] : 97 : bidir : 3.3-V LVCMOS : : 2 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b/cpld_maxv/output_files/RAM2E.sta.rpt new file mode 100644 index 0000000..10c2009 --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.sta.rpt @@ -0,0 +1,809 @@ +TimeQuest Timing Analyzer report for RAM2E +Wed Mar 10 21:02:38 2021 +Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Fmax Summary + 7. Setup Summary + 8. Hold Summary + 9. Recovery Summary + 10. Removal Summary + 11. Minimum Pulse Width Summary + 12. Setup: 'C14M' + 13. Hold: 'C14M' + 14. Minimum Pulse Width: 'C14M' + 15. Setup Times + 16. Hold Times + 17. Clock to Output Times + 18. Minimum Clock to Output Times + 19. Propagation Delay + 20. Minimum Propagation Delay + 21. Setup Transfers + 22. Hold Transfers + 23. Report TCCS + 24. Report RSKM + 25. Unconstrained Paths + 26. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+-------------------------------------------------------------------+ +; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ; +; Revision Name ; RAM2E ; +; Device Family ; MAX V ; +; Device Name ; 5M240ZT100C5 ; +; Timing Models ; Final ; +; Delay Model ; Slow Model ; +; Rise/Fall Delays ; Unavailable ; ++--------------------+-------------------------------------------------------------------+ + + +Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time. ++-------------------------------------+ +; Parallel Compilation ; ++----------------------------+--------+ +; Processors ; Number ; ++----------------------------+--------+ +; Number detected on machine ; 8 ; +; Maximum allowed ; 1 ; ++----------------------------+--------+ + + ++-----------------------------------------------------+ +; SDC File List ; ++-----------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++-----------------+--------+--------------------------+ +; constraints.sdc ; OK ; Wed Mar 10 21:02:38 2021 ; ++-----------------+--------+--------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ +; C14M ; Base ; 69.841 ; 14.32 MHz ; 0.000 ; 34.920 ; ; ; ; ; ; ; ; ; ; ; { C14M } ; ++------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ + + ++-------------------------------------------------+ +; Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 35.22 MHz ; 35.22 MHz ; C14M ; ; ++-----------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++--------------------------------+ +; Setup Summary ; ++-------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------+ +; C14M ; 21.072 ; 0.000 ; ++-------+--------+---------------+ + + ++-------------------------------+ +; Hold Summary ; ++-------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------+ +; C14M ; 3.158 ; 0.000 ; ++-------+-------+---------------+ + + +-------------------- +; Recovery Summary ; +-------------------- +No paths to report. + + +------------------- +; Removal Summary ; +------------------- +No paths to report. + + ++--------------------------------+ +; Minimum Pulse Width Summary ; ++-------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------+ +; C14M ; 34.581 ; 0.000 ; ++-------+--------+---------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Setup: 'C14M' ; ++--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ +; 21.072 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.527 ; +; 21.073 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.526 ; +; 21.320 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.279 ; +; 21.321 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.278 ; +; 21.538 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.061 ; +; 21.538 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.061 ; +; 21.538 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.061 ; +; 21.538 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.061 ; +; 21.538 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.061 ; +; 21.538 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.061 ; +; 21.786 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.813 ; +; 21.786 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.813 ; +; 21.786 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.813 ; +; 21.786 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.813 ; +; 21.786 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.813 ; +; 21.786 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.813 ; +; 22.152 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.447 ; +; 22.153 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.446 ; +; 22.618 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.981 ; +; 22.618 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.981 ; +; 22.618 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.981 ; +; 22.618 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.981 ; +; 22.618 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.981 ; +; 22.618 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.981 ; +; 22.638 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.961 ; +; 22.638 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.961 ; +; 22.656 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.943 ; +; 22.656 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.943 ; +; 22.656 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.943 ; +; 22.791 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.808 ; +; 22.792 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.807 ; +; 22.881 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.718 ; +; 22.881 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.718 ; +; 22.899 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.700 ; +; 22.899 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.700 ; +; 22.899 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.700 ; +; 23.257 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.342 ; +; 23.257 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.342 ; +; 23.257 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.342 ; +; 23.257 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.342 ; +; 23.257 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.342 ; +; 23.257 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.342 ; +; 23.696 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.903 ; +; 23.696 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.903 ; +; 23.714 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.885 ; +; 23.714 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.885 ; +; 23.714 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.885 ; +; 24.379 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.220 ; +; 24.379 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.220 ; +; 24.397 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.202 ; +; 24.397 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.202 ; +; 24.397 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.202 ; +; 25.570 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.029 ; +; 25.570 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.029 ; +; 25.570 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.029 ; +; 25.813 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.786 ; +; 25.813 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.786 ; +; 25.813 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.786 ; +; 26.628 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.971 ; +; 26.628 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.971 ; +; 26.628 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.971 ; +; 27.311 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.288 ; +; 27.311 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.288 ; +; 27.311 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.288 ; +; 41.451 ; UFMD[14] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 28.069 ; +; 41.451 ; UFMD[14] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 28.069 ; +; 41.451 ; UFMD[14] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 28.069 ; +; 42.716 ; UFMD[14] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.804 ; +; 42.716 ; UFMD[14] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.804 ; +; 42.716 ; UFMD[14] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.804 ; +; 42.716 ; UFMD[14] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.804 ; +; 42.716 ; UFMD[14] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.804 ; +; 42.718 ; UFMD[14] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 26.802 ; +; 43.290 ; FS[15] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.230 ; +; 44.163 ; UFMD[13] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.357 ; +; 44.163 ; UFMD[13] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.357 ; +; 44.163 ; UFMD[13] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.357 ; +; 44.177 ; FS[14] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.343 ; +; 44.723 ; S[0] ; RWBank[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.797 ; +; 44.723 ; S[0] ; RWBank[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.797 ; +; 44.723 ; S[0] ; RWBank[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.797 ; +; 44.792 ; FS[13] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 24.728 ; +; 44.806 ; S[0] ; UFMPrgmEN ; C14M ; C14M ; 69.841 ; 0.000 ; 24.714 ; +; 44.811 ; S[0] ; UFMEraseEN ; C14M ; C14M ; 69.841 ; 0.000 ; 24.709 ; +; 44.971 ; S[3] ; RWBank[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.549 ; +; 44.971 ; S[3] ; RWBank[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.549 ; +; 44.971 ; S[3] ; RWBank[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.549 ; +; 45.054 ; S[3] ; UFMPrgmEN ; C14M ; C14M ; 69.841 ; 0.000 ; 24.466 ; +; 45.059 ; S[3] ; UFMEraseEN ; C14M ; C14M ; 69.841 ; 0.000 ; 24.461 ; +; 45.281 ; FS[15] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 24.239 ; +; 45.313 ; FS[7] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 24.207 ; +; 45.428 ; UFMD[13] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.092 ; +; 45.428 ; UFMD[13] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.092 ; +; 45.428 ; UFMD[13] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.092 ; +; 45.428 ; UFMD[13] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.092 ; +; 45.428 ; UFMD[13] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.092 ; +; 45.430 ; UFMD[13] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 24.090 ; +; 45.486 ; FS[8] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 24.034 ; +; 45.738 ; S[0] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 23.782 ; +; 45.738 ; S[0] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 23.782 ; ++--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------+ +; Hold: 'C14M' ; ++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ +; 3.158 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.197 ; +; 3.395 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.434 ; +; 3.411 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.450 ; +; 3.484 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.523 ; +; 3.495 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.534 ; +; 3.753 ; RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.792 ; +; 3.880 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.919 ; +; 3.986 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 4.025 ; +; 4.176 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.215 ; +; 4.247 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.286 ; +; 4.524 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.563 ; +; 4.810 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 4.849 ; +; 4.810 ; UFMEraseEN ; UFMEraseEN ; C14M ; C14M ; 0.000 ; 0.000 ; 4.849 ; +; 4.910 ; UFMReqErase ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 4.949 ; +; 4.955 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.994 ; +; 5.151 ; UFMD[10] ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.190 ; +; 5.217 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ; +; 5.217 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ; +; 5.231 ; RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.270 ; +; 5.231 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.270 ; +; 5.232 ; RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.271 ; +; 5.241 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.280 ; +; 5.243 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.282 ; +; 5.252 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.291 ; +; 5.271 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 5.310 ; +; 5.272 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.311 ; +; 5.280 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.319 ; +; 5.283 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.322 ; +; 5.312 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.351 ; +; 5.347 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.386 ; +; 5.369 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.408 ; +; 5.416 ; UFMPrgmEN ; UFMPrgmEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.455 ; +; 5.417 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 5.456 ; +; 5.441 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.480 ; +; 5.442 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.481 ; +; 5.452 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ; +; 5.453 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ; +; 5.453 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ; +; 5.458 ; UFMInitDone ; DRShift ; C14M ; C14M ; 0.000 ; 0.000 ; 5.497 ; +; 5.466 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.505 ; +; 5.473 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.512 ; +; 5.482 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.521 ; +; 5.484 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.523 ; +; 5.486 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.525 ; +; 5.489 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.528 ; +; 5.496 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.535 ; +; 5.508 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.547 ; +; 5.510 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.549 ; +; 5.514 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.553 ; +; 5.516 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.555 ; +; 5.952 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.991 ; +; 5.977 ; UFMD[8] ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 6.016 ; +; 5.987 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.026 ; +; 6.015 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.054 ; +; 6.018 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.057 ; +; 6.090 ; UFMBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 6.129 ; +; 6.096 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.135 ; +; 6.131 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.170 ; +; 6.159 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.198 ; +; 6.162 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.201 ; +; 6.275 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.314 ; +; 6.306 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.345 ; +; 6.375 ; SetRWBankFF ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.414 ; +; 6.419 ; FS[8] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.458 ; +; 6.444 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.483 ; +; 6.454 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ; +; 6.455 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.494 ; +; 6.488 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.527 ; +; 6.498 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.537 ; +; 6.516 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.555 ; +; 6.518 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.557 ; +; 6.598 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ; +; 6.616 ; RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.655 ; +; 6.624 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.663 ; +; 6.642 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.681 ; +; 6.662 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.701 ; +; 6.690 ; RWBank[5] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.729 ; +; 6.725 ; UFMD[14] ; RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.764 ; +; 6.786 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ; +; 6.795 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.834 ; +; 6.795 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.834 ; +; 6.795 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.834 ; +; 6.806 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.845 ; +; 6.851 ; RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.890 ; +; 6.930 ; FS[3] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.969 ; +; 6.942 ; FS[9] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.981 ; +; 6.942 ; FS[9] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.981 ; +; 6.942 ; FS[9] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.981 ; +; 7.023 ; FS[12] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ; +; 7.023 ; FS[12] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ; +; 7.023 ; FS[12] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ; +; 7.055 ; FS[8] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.094 ; +; 7.055 ; FS[8] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.094 ; +; 7.055 ; FS[8] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.094 ; +; 7.065 ; FS[2] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.104 ; +; 7.065 ; FS[2] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.104 ; +; 7.065 ; FS[2] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.104 ; +; 7.065 ; FS[2] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.104 ; +; 7.065 ; FS[2] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.104 ; +; 7.080 ; FS[11] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.119 ; ++-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------+ +; Minimum Pulse Width: 'C14M' ; ++--------+--------------+----------------+------------------+-------+------------+--------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+--------------+ +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; ARCLK ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; ARShift ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; BA[0]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; BA[1]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CKE~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CS[0] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CS[1] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CS[2] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CmdTout[0] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CmdTout[1] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CmdTout[2] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DOEEN ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DQMH~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DQML~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DRCLK ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DRCLKPulse ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DRDIn ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DRShift ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[0]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[1]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[2]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[3]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[4]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[5]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[6]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[7]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[0] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[10] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[11] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[12] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[13] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[14] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[15] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[1] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[2] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[3] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[4] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[5] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[6] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[7] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[8] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[9] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; PHI1reg ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[0]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[10]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[11]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[1]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[2]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[3]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[4]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[5]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[6]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[7]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[8]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[9]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RTPBusyReg ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[0] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[1] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[2] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[3] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[4] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[5] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[6] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[7] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMaskSet ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[0] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[1] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[2] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[3] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[4] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[5] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[6] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[7] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWSel ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Ready ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; S[0] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; S[1] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; S[2] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; S[3] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; SetRWBankFF ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMBitbang ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMBusyReg ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[10] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[11] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[12] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[13] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[14] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[8] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[9] ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMErase ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMEraseEN ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMInitDone ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMPrgmEN ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMProgram ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMReqErase ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[0]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[1]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[2]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[3]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[4]~reg0 ; ++--------+--------------+----------------+------------------+-------+------------+--------------+ + + ++-------------------------------------------------------------------------+ +; Setup Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; Ain[*] ; C14M ; 10.392 ; 10.392 ; Rise ; C14M ; +; Ain[0] ; C14M ; 6.603 ; 6.603 ; Rise ; C14M ; +; Ain[1] ; C14M ; 4.691 ; 4.691 ; Rise ; C14M ; +; Ain[2] ; C14M ; 6.626 ; 6.626 ; Rise ; C14M ; +; Ain[3] ; C14M ; 6.930 ; 6.930 ; Rise ; C14M ; +; Ain[4] ; C14M ; 10.392 ; 10.392 ; Rise ; C14M ; +; Ain[5] ; C14M ; 5.028 ; 5.028 ; Rise ; C14M ; +; Ain[6] ; C14M ; 6.885 ; 6.885 ; Rise ; C14M ; +; Ain[7] ; C14M ; 6.064 ; 6.064 ; Rise ; C14M ; +; Din[*] ; C14M ; 29.469 ; 29.469 ; Rise ; C14M ; +; Din[0] ; C14M ; 27.528 ; 27.528 ; Rise ; C14M ; +; Din[1] ; C14M ; 22.600 ; 22.600 ; Rise ; C14M ; +; Din[2] ; C14M ; 27.577 ; 27.577 ; Rise ; C14M ; +; Din[3] ; C14M ; 25.336 ; 25.336 ; Rise ; C14M ; +; Din[4] ; C14M ; 24.782 ; 24.782 ; Rise ; C14M ; +; Din[5] ; C14M ; 27.644 ; 27.644 ; Rise ; C14M ; +; Din[6] ; C14M ; 29.469 ; 29.469 ; Rise ; C14M ; +; Din[7] ; C14M ; 26.581 ; 26.581 ; Rise ; C14M ; +; PHI1 ; C14M ; 19.681 ; 19.681 ; Rise ; C14M ; +; nC07X ; C14M ; 12.752 ; 12.752 ; Rise ; C14M ; +; nEN80 ; C14M ; 11.289 ; 11.289 ; Rise ; C14M ; +; nWE ; C14M ; 17.804 ; 17.804 ; Rise ; C14M ; +; nWE80 ; C14M ; 14.258 ; 14.258 ; Rise ; C14M ; +; RD[*] ; C14M ; 7.204 ; 7.204 ; Fall ; C14M ; +; RD[0] ; C14M ; 6.761 ; 6.761 ; Fall ; C14M ; +; RD[1] ; C14M ; 7.123 ; 7.123 ; Fall ; C14M ; +; RD[2] ; C14M ; 6.930 ; 6.930 ; Fall ; C14M ; +; RD[3] ; C14M ; 6.958 ; 6.958 ; Fall ; C14M ; +; RD[4] ; C14M ; 5.017 ; 5.017 ; Fall ; C14M ; +; RD[5] ; C14M ; 7.204 ; 7.204 ; Fall ; C14M ; +; RD[6] ; C14M ; 6.905 ; 6.905 ; Fall ; C14M ; +; RD[7] ; C14M ; 5.074 ; 5.074 ; Fall ; C14M ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++---------------------------------------------------------------------------+ +; Hold Times ; ++-----------+------------+---------+---------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+---------+---------+------------+-----------------+ +; Ain[*] ; C14M ; -4.331 ; -4.331 ; Rise ; C14M ; +; Ain[0] ; C14M ; -6.243 ; -6.243 ; Rise ; C14M ; +; Ain[1] ; C14M ; -4.331 ; -4.331 ; Rise ; C14M ; +; Ain[2] ; C14M ; -6.266 ; -6.266 ; Rise ; C14M ; +; Ain[3] ; C14M ; -6.570 ; -6.570 ; Rise ; C14M ; +; Ain[4] ; C14M ; -10.032 ; -10.032 ; Rise ; C14M ; +; Ain[5] ; C14M ; -4.668 ; -4.668 ; Rise ; C14M ; +; Ain[6] ; C14M ; -6.525 ; -6.525 ; Rise ; C14M ; +; Ain[7] ; C14M ; -5.704 ; -5.704 ; Rise ; C14M ; +; Din[*] ; C14M ; -3.164 ; -3.164 ; Rise ; C14M ; +; Din[0] ; C14M ; -4.999 ; -4.999 ; Rise ; C14M ; +; Din[1] ; C14M ; -4.844 ; -4.844 ; Rise ; C14M ; +; Din[2] ; C14M ; -3.164 ; -3.164 ; Rise ; C14M ; +; Din[3] ; C14M ; -5.058 ; -5.058 ; Rise ; C14M ; +; Din[4] ; C14M ; -5.163 ; -5.163 ; Rise ; C14M ; +; Din[5] ; C14M ; -6.645 ; -6.645 ; Rise ; C14M ; +; Din[6] ; C14M ; -4.862 ; -4.862 ; Rise ; C14M ; +; Din[7] ; C14M ; -4.617 ; -4.617 ; Rise ; C14M ; +; PHI1 ; C14M ; -6.275 ; -6.275 ; Rise ; C14M ; +; nC07X ; C14M ; -12.392 ; -12.392 ; Rise ; C14M ; +; nEN80 ; C14M ; -7.086 ; -7.086 ; Rise ; C14M ; +; nWE ; C14M ; -17.444 ; -17.444 ; Rise ; C14M ; +; nWE80 ; C14M ; -13.898 ; -13.898 ; Rise ; C14M ; +; RD[*] ; C14M ; -4.655 ; -4.655 ; Fall ; C14M ; +; RD[0] ; C14M ; -6.398 ; -6.398 ; Fall ; C14M ; +; RD[1] ; C14M ; -4.676 ; -4.676 ; Fall ; C14M ; +; RD[2] ; C14M ; -6.117 ; -6.117 ; Fall ; C14M ; +; RD[3] ; C14M ; -4.767 ; -4.767 ; Fall ; C14M ; +; RD[4] ; C14M ; -4.655 ; -4.655 ; Fall ; C14M ; +; RD[5] ; C14M ; -6.305 ; -6.305 ; Fall ; C14M ; +; RD[6] ; C14M ; -6.507 ; -6.507 ; Fall ; C14M ; +; RD[7] ; C14M ; -4.689 ; -4.689 ; Fall ; C14M ; ++-----------+------------+---------+---------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Clock to Output Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; BA[*] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; BA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; BA[1] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; CKE ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; DQMH ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ; +; DQML ; C14M ; 20.694 ; 20.694 ; Rise ; C14M ; +; RA[*] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; +; RA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; RA[1] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; RA[2] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ; +; RA[3] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ; +; RA[4] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; RA[5] ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ; +; RA[6] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; RA[7] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; RA[8] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ; +; RA[9] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; +; RA[10] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ; +; RA[11] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; nCAS ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; nCS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; nDOE ; C14M ; 27.546 ; 27.546 ; Rise ; C14M ; +; nRAS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; nRWE ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; +; Dout[*] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ; +; Dout[0] ; C14M ; 17.336 ; 17.336 ; Fall ; C14M ; +; Dout[1] ; C14M ; 17.368 ; 17.368 ; Fall ; C14M ; +; Dout[2] ; C14M ; 19.308 ; 19.308 ; Fall ; C14M ; +; Dout[3] ; C14M ; 17.362 ; 17.362 ; Fall ; C14M ; +; Dout[4] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ; +; Dout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Dout[6] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ; +; Dout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[*] ; C14M ; 19.308 ; 19.308 ; Fall ; C14M ; +; Vout[0] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[1] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[2] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ; +; Vout[3] ; C14M ; 19.308 ; 19.308 ; Fall ; C14M ; +; Vout[4] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[6] ; C14M ; 19.301 ; 19.301 ; Fall ; C14M ; +; Vout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++-------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++-----------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++-----------+------------+--------+--------+------------+-----------------+ +; BA[*] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; BA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; BA[1] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; CKE ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; DQMH ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ; +; DQML ; C14M ; 20.694 ; 20.694 ; Rise ; C14M ; +; RA[*] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ; +; RA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; RA[1] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; RA[2] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ; +; RA[3] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ; +; RA[4] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; RA[5] ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ; +; RA[6] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; RA[7] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; RA[8] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ; +; RA[9] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; +; RA[10] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ; +; RA[11] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; nCAS ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; nCS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; nDOE ; C14M ; 27.546 ; 27.546 ; Rise ; C14M ; +; nRAS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; nRWE ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; +; Dout[*] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Dout[0] ; C14M ; 17.336 ; 17.336 ; Fall ; C14M ; +; Dout[1] ; C14M ; 17.368 ; 17.368 ; Fall ; C14M ; +; Dout[2] ; C14M ; 19.308 ; 19.308 ; Fall ; C14M ; +; Dout[3] ; C14M ; 17.362 ; 17.362 ; Fall ; C14M ; +; Dout[4] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ; +; Dout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Dout[6] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ; +; Dout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[*] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[0] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[1] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[2] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ; +; Vout[3] ; C14M ; 19.308 ; 19.308 ; Fall ; C14M ; +; Vout[4] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[6] ; C14M ; 19.301 ; 19.301 ; Fall ; C14M ; +; Vout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; ++-----------+------------+--------+--------+------------+-----------------+ + + ++------------------------------------------------------+ +; Propagation Delay ; ++------------+-------------+--------+----+----+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+----+----+--------+ +; Din[0] ; RD[0] ; 19.413 ; ; ; 19.413 ; +; Din[1] ; RD[1] ; 19.309 ; ; ; 19.309 ; +; Din[2] ; RD[2] ; 21.236 ; ; ; 21.236 ; +; Din[3] ; RD[3] ; 19.293 ; ; ; 19.293 ; +; Din[4] ; RD[4] ; 21.360 ; ; ; 21.360 ; +; Din[5] ; RD[5] ; 21.270 ; ; ; 21.270 ; +; Din[6] ; RD[6] ; 19.514 ; ; ; 19.514 ; +; Din[7] ; RD[7] ; 19.413 ; ; ; 19.413 ; +; PHI1 ; nVOE ; 22.485 ; ; ; 22.485 ; +; nEN80 ; RD[0] ; 23.245 ; ; ; 23.245 ; +; nEN80 ; RD[1] ; 21.416 ; ; ; 21.416 ; +; nEN80 ; RD[2] ; 23.245 ; ; ; 23.245 ; +; nEN80 ; RD[3] ; 21.416 ; ; ; 21.416 ; +; nEN80 ; RD[4] ; 21.416 ; ; ; 21.416 ; +; nEN80 ; RD[5] ; 23.245 ; ; ; 23.245 ; +; nEN80 ; RD[6] ; 23.245 ; ; ; 23.245 ; +; nEN80 ; RD[7] ; 23.245 ; ; ; 23.245 ; +; nEN80 ; nDOE ; 28.267 ; ; ; 28.267 ; +; nWE ; nDOE ; 30.113 ; ; ; 30.113 ; +; nWE80 ; RD[0] ; 25.521 ; ; ; 25.521 ; +; nWE80 ; RD[1] ; 23.692 ; ; ; 23.692 ; +; nWE80 ; RD[2] ; 25.521 ; ; ; 25.521 ; +; nWE80 ; RD[3] ; 23.692 ; ; ; 23.692 ; +; nWE80 ; RD[4] ; 23.692 ; ; ; 23.692 ; +; nWE80 ; RD[5] ; 25.521 ; ; ; 25.521 ; +; nWE80 ; RD[6] ; 25.521 ; ; ; 25.521 ; +; nWE80 ; RD[7] ; 25.521 ; ; ; 25.521 ; ++------------+-------------+--------+----+----+--------+ + + ++------------------------------------------------------+ +; Minimum Propagation Delay ; ++------------+-------------+--------+----+----+--------+ +; Input Port ; Output Port ; RR ; RF ; FR ; FF ; ++------------+-------------+--------+----+----+--------+ +; Din[0] ; RD[0] ; 19.413 ; ; ; 19.413 ; +; Din[1] ; RD[1] ; 19.309 ; ; ; 19.309 ; +; Din[2] ; RD[2] ; 21.236 ; ; ; 21.236 ; +; Din[3] ; RD[3] ; 19.293 ; ; ; 19.293 ; +; Din[4] ; RD[4] ; 21.360 ; ; ; 21.360 ; +; Din[5] ; RD[5] ; 21.270 ; ; ; 21.270 ; +; Din[6] ; RD[6] ; 19.514 ; ; ; 19.514 ; +; Din[7] ; RD[7] ; 19.413 ; ; ; 19.413 ; +; PHI1 ; nVOE ; 22.485 ; ; ; 22.485 ; +; nEN80 ; RD[0] ; 23.245 ; ; ; 23.245 ; +; nEN80 ; RD[1] ; 21.416 ; ; ; 21.416 ; +; nEN80 ; RD[2] ; 23.245 ; ; ; 23.245 ; +; nEN80 ; RD[3] ; 21.416 ; ; ; 21.416 ; +; nEN80 ; RD[4] ; 21.416 ; ; ; 21.416 ; +; nEN80 ; RD[5] ; 23.245 ; ; ; 23.245 ; +; nEN80 ; RD[6] ; 23.245 ; ; ; 23.245 ; +; nEN80 ; RD[7] ; 23.245 ; ; ; 23.245 ; +; nEN80 ; nDOE ; 28.267 ; ; ; 28.267 ; +; nWE ; nDOE ; 30.113 ; ; ; 30.113 ; +; nWE80 ; RD[0] ; 25.521 ; ; ; 25.521 ; +; nWE80 ; RD[1] ; 23.692 ; ; ; 23.692 ; +; nWE80 ; RD[2] ; 25.521 ; ; ; 25.521 ; +; nWE80 ; RD[3] ; 23.692 ; ; ; 23.692 ; +; nWE80 ; RD[4] ; 23.692 ; ; ; 23.692 ; +; nWE80 ; RD[5] ; 25.521 ; ; ; 25.521 ; +; nWE80 ; RD[6] ; 25.521 ; ; ; 25.521 ; +; nWE80 ; RD[7] ; 25.521 ; ; ; 25.521 ; ++------------+-------------+--------+----+----+--------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; C14M ; C14M ; 1352 ; 0 ; 64 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; C14M ; C14M ; 1352 ; 0 ; 64 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 2 ; 2 ; +; Unconstrained Input Ports ; 29 ; 29 ; +; Unconstrained Input Port Paths ; 143 ; 143 ; +; Unconstrained Output Ports ; 47 ; 47 ; +; Unconstrained Output Port Paths ; 65 ; 65 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition + Info: Processing started: Wed Mar 10 21:02:36 2021 +Info: Command: quartus_sta RAM2E -c RAM2E +Info: qsta_default_script.tcl version: #1 +Warning (20028): Parallel compilation is not licensed and has been disabled +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (306004): Started post-fitting delay annotation +Info (306005): Delay annotation completed successfully +Info (332104): Reading SDC File: 'constraints.sdc' +Warning (332060): Node: DRCLK was determined to be a clock but was found without an associated clock assignment. +Warning (332060): Node: ARCLK was determined to be a clock but was found without an associated clock assignment. +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info (332146): Worst-case setup slack is 21.072 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 21.072 0.000 C14M +Info (332146): Worst-case hold slack is 3.158 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 3.158 0.000 C14M +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 34.581 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 34.581 0.000 C14M +Info (332001): The selected device family is not supported by the report_metastability command. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 4514 megabytes + Info: Processing ended: Wed Mar 10 21:02:38 2021 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/cpld_maxv/output_files/RAM2E.sta.summary b/cpld_maxv/output_files/RAM2E.sta.summary new file mode 100644 index 0000000..7a28d92 --- /dev/null +++ b/cpld_maxv/output_files/RAM2E.sta.summary @@ -0,0 +1,17 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +Type : Setup 'C14M' +Slack : 21.072 +TNS : 0.000 + +Type : Hold 'C14M' +Slack : 3.158 +TNS : 0.000 + +Type : Minimum Pulse Width 'C14M' +Slack : 34.581 +TNS : 0.000 + +------------------------------------------------------------