From 6706e42efb1033bb400b751a9d8e8144a57bb691 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Mon, 18 Dec 2023 06:29:13 -0500 Subject: [PATCH] Revert "As sent to testers" This reverts commit aa65c256270fe6ff4ce89bd299c66a1d149a4454. --- .gitignore | 1 - CPLD/MAXII/RAM2E.qsf | 12 +- CPLD/MAXII/RAM2E.qws | Bin 619 -> 619 bytes CPLD/MAXII/UFM.v | 6 +- CPLD/MAXII/output_files/RAM2E.asm.rpt | 48 +- CPLD/MAXII/output_files/RAM2E.done | 2 +- CPLD/MAXII/output_files/RAM2E.fit.rpt | 288 +- CPLD/MAXII/output_files/RAM2E.fit.summary | 8 +- CPLD/MAXII/output_files/RAM2E.flow.rpt | 48 +- CPLD/MAXII/output_files/RAM2E.jdi | 2 +- CPLD/MAXII/output_files/RAM2E.map.rpt | 123 +- CPLD/MAXII/output_files/RAM2E.map.smsg | 6 +- CPLD/MAXII/output_files/RAM2E.map.summary | 8 +- CPLD/MAXII/output_files/RAM2E.pin | 4 +- CPLD/MAXII/output_files/RAM2E.pof | Bin 7877 -> 7861 bytes CPLD/MAXII/output_files/RAM2E.sta.rpt | 534 +- CPLD/MAXII/output_files/RAM2E.sta.summary | 26 +- CPLD/MAXV/RAM2E.qsf | 12 +- CPLD/MAXV/RAM2E.qws | Bin 619 -> 619 bytes CPLD/MAXV/UFM.v | 6 +- CPLD/MAXV/output_files/RAM2E.asm.rpt | 46 +- CPLD/MAXV/output_files/RAM2E.done | 2 +- CPLD/MAXV/output_files/RAM2E.fit.rpt | 265 +- CPLD/MAXV/output_files/RAM2E.fit.summary | 8 +- CPLD/MAXV/output_files/RAM2E.flow.rpt | 48 +- CPLD/MAXV/output_files/RAM2E.jdi | 2 +- CPLD/MAXV/output_files/RAM2E.map.rpt | 123 +- CPLD/MAXV/output_files/RAM2E.map.smsg | 6 +- CPLD/MAXV/output_files/RAM2E.map.summary | 8 +- CPLD/MAXV/output_files/RAM2E.pin | 4 +- CPLD/MAXV/output_files/RAM2E.pof | Bin 7877 -> 7861 bytes CPLD/MAXV/output_files/RAM2E.sta.rpt | 478 +- CPLD/MAXV/output_files/RAM2E.sta.summary | 22 +- CPLD/RAM2E-LCMXO2.v | 26 +- CPLD/RAM2E-MAX.mif | 28 - CPLD/RAM2E-MAX.v | 148 +- CPLD/RAM2E.mif | 25 + Hardware/LCMXO2/Docs.kicad_sch | 5539 ++++++++++------- .../RAM2E.4203B.LCMXO2-Placement 2.pdf | Bin 0 -> 141711 bytes .../RAM2E.4203B.LCMXO2-Schematic 2.pdf | Bin 0 -> 1232434 bytes Hardware/MAX/Docs.kicad_sch | 801 ++- 41 files changed, 5039 insertions(+), 3674 deletions(-) delete mode 100644 CPLD/RAM2E-MAX.mif create mode 100644 CPLD/RAM2E.mif create mode 100644 Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Placement 2.pdf create mode 100644 Hardware/LCMXO2/Documentation/RAM2E.4203B.LCMXO2-Schematic 2.pdf diff --git a/.gitignore b/.gitignore index 3b47f9c..3177f76 100644 --- a/.gitignore +++ b/.gitignore @@ -39,4 +39,3 @@ CPLD/LCMXO*/impl1/* !CPLD/LCMXO*/impl1/*.srr !CPLD/LCMXO*/impl1/*.twr !CPLD/LCMXO*/impl1/*.tw1 -*.bak diff --git a/CPLD/MAXII/RAM2E.qsf b/CPLD/MAXII/RAM2E.qsf index 7373ad3..722f2da 100644 --- a/CPLD/MAXII/RAM2E.qsf +++ b/CPLD/MAXII/RAM2E.qsf @@ -42,7 +42,7 @@ set_global_assignment -name DEVICE EPM240T100C5 set_global_assignment -name TOP_LEVEL_ENTITY RAM2E set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:26:23 AUGUST 20, 2023" -set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 SP0.02std Lite Edition" +set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 @@ -240,15 +240,9 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" set_global_assignment -name VERILOG_FILE "../RAM2E-MAX.v" set_global_assignment -name QIP_FILE UFM.qip -set_global_assignment -name MIF_FILE ../RAM2E-MAX.mif +set_global_assignment -name MIF_FILE ../RAM2E.mif set_global_assignment -name SDC_FILE ../RAM2E.sdc set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc" set_location_assignment PIN_88 -to LED set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED -set_instance_assignment -name SLOW_SLEW_RATE ON -to LED -set_location_assignment PIN_81 -to RCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RCLK -set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to RCLK -set_instance_assignment -name SLOW_SLEW_RATE OFF -to RCLK -set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY OFF -to RCLK -set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RCLK \ No newline at end of file +set_instance_assignment -name SLOW_SLEW_RATE ON -to LED \ No newline at end of file diff --git a/CPLD/MAXII/RAM2E.qws b/CPLD/MAXII/RAM2E.qws index b9a4426be1b34439a20dd2bc3b6dc808bd03b32e..8de3d3ecec64b3ff743c66893051e3ad1a1fae78 100644 GIT binary patch delta 62 zcmaFO@|tDBB1WExi>(ED7#J8582Mj57=Kqfa(3Jid<|3DbT HVPXIPUX2rJ delta 62 zcmaFO@|tDBBE|<37h4NHU|?WKVEF(4Kaj3qU|@Q%@qGfL3}ZErc^@bQ20+<=APnL# GF#rJE)E0XH diff --git a/CPLD/MAXII/UFM.v b/CPLD/MAXII/UFM.v index dc6b2e8..b139ed2 100644 --- a/CPLD/MAXII/UFM.v +++ b/CPLD/MAXII/UFM.v @@ -34,7 +34,7 @@ //https://fpgasoftware.intel.com/eula. -//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="../RAM2E-MAX.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy +//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="../RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy //VERSION_BEGIN 19.1 cbx_a_gray2bin 2019:09:22:11:00:27:SJ cbx_a_graycounter 2019:09:22:11:00:27:SJ cbx_altufm_none 2019:09:22:11:00:28:SJ cbx_cycloneii 2019:09:22:11:00:28:SJ cbx_lpm_add_sub 2019:09:22:11:00:28:SJ cbx_lpm_compare 2019:09:22:11:00:28:SJ cbx_lpm_counter 2019:09:22:11:00:28:SJ cbx_lpm_decode 2019:09:22:11:00:28:SJ cbx_lpm_mux 2019:09:22:11:00:28:SJ cbx_maxii 2019:09:22:11:00:28:SJ cbx_mgl 2019:09:22:11:02:15:SJ cbx_nadder 2019:09:22:11:00:28:SJ cbx_stratix 2019:09:22:11:00:28:SJ cbx_stratixii 2019:09:22:11:00:28:SJ cbx_util_mgl 2019:09:22:11:00:28:SJ VERSION_END // synthesis VERILOG_INPUT_VERSION VERILOG_2001 // altera message_off 10463 @@ -118,7 +118,7 @@ module UFM_altufm_none_lbr defparam maxii_ufm_block1.address_width = 9, maxii_ufm_block1.erase_time = 500000000, - maxii_ufm_block1.init_file = "../RAM2E-MAX.mif", + maxii_ufm_block1.init_file = "../RAM2E.mif", maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF, @@ -225,7 +225,7 @@ endmodule // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II" // Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II" -// Retrieval info: CONSTANT: LPM_FILE STRING "../RAM2E-MAX.mif" +// Retrieval info: CONSTANT: LPM_FILE STRING "../RAM2E.mif" // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" // Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none" // Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000" diff --git a/CPLD/MAXII/output_files/RAM2E.asm.rpt b/CPLD/MAXII/output_files/RAM2E.asm.rpt index 6d5a354..c9fac51 100644 --- a/CPLD/MAXII/output_files/RAM2E.asm.rpt +++ b/CPLD/MAXII/output_files/RAM2E.asm.rpt @@ -1,6 +1,6 @@ Assembler report for RAM2E -Tue Nov 21 06:54:42 2023 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Thu Sep 21 05:34:41 2023 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -10,7 +10,7 @@ Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Editio 2. Assembler Summary 3. Assembler Settings 4. Assembler Generated Files - 5. Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof + 5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof 6. Assembler Messages @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Tue Nov 21 06:54:42 2023 ; +; Assembler Status ; Successful - Thu Sep 21 05:34:41 2023 ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; ; Family ; MAX II ; @@ -53,23 +53,23 @@ https://fpgasoftware.intel.com/eula. +--------+---------+---------------+ -+--------------------------------------------------+ -; Assembler Generated Files ; -+--------------------------------------------------+ -; File Name ; -+--------------------------------------------------+ -; Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ; -+--------------------------------------------------+ ++------------------------------------------------+ +; Assembler Generated Files ; ++------------------------------------------------+ +; File Name ; ++------------------------------------------------+ +; /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ; ++------------------------------------------------+ -+----------------------------------------------------------------------------+ -; Assembler Device Options: Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ; -+----------------+-----------------------------------------------------------+ -; Option ; Setting ; -+----------------+-----------------------------------------------------------+ -; JTAG usercode ; 0x0016C0A4 ; -; Checksum ; 0x0016C524 ; -+----------------+-----------------------------------------------------------+ ++--------------------------------------------------------------------------+ +; Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ; ++----------------+---------------------------------------------------------+ +; Option ; Setting ; ++----------------+---------------------------------------------------------+ +; JTAG usercode ; 0x0016D33C ; +; Checksum ; 0x0016D634 ; ++----------------+---------------------------------------------------------+ +--------------------+ @@ -77,15 +77,15 @@ https://fpgasoftware.intel.com/eula. +--------------------+ Info: ******************************************************************* Info: Running Quartus Prime Assembler - Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Tue Nov 21 06:54:41 2023 + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Thu Sep 21 05:34:39 2023 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 13068 megabytes - Info: Processing ended: Tue Nov 21 06:54:42 2023 - Info: Elapsed time: 00:00:01 + Info: Peak virtual memory: 13092 megabytes + Info: Processing ended: Thu Sep 21 05:34:41 2023 + Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXII/output_files/RAM2E.done b/CPLD/MAXII/output_files/RAM2E.done index bf96c71..9e5945b 100644 --- a/CPLD/MAXII/output_files/RAM2E.done +++ b/CPLD/MAXII/output_files/RAM2E.done @@ -1 +1 @@ -Tue Nov 21 06:54:46 2023 +Thu Sep 21 05:34:46 2023 diff --git a/CPLD/MAXII/output_files/RAM2E.fit.rpt b/CPLD/MAXII/output_files/RAM2E.fit.rpt index 361cbba..5adbd10 100644 --- a/CPLD/MAXII/output_files/RAM2E.fit.rpt +++ b/CPLD/MAXII/output_files/RAM2E.fit.rpt @@ -1,6 +1,6 @@ Fitter report for RAM2E -Tue Nov 21 06:54:39 2023 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Thu Sep 21 05:34:37 2023 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -54,21 +54,21 @@ https://fpgasoftware.intel.com/eula. -+-------------------------------------------------------------------------------------+ -; Fitter Summary ; -+-----------------------+-------------------------------------------------------------+ -; Fitter Status ; Successful - Tue Nov 21 06:54:39 2023 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 209 / 240 ( 87 % ) ; -; Total pins ; 71 / 80 ( 89 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------+-------------------------------------------------------------+ ++---------------------------------------------------------------------+ +; Fitter Summary ; ++-----------------------+---------------------------------------------+ +; Fitter Status ; Successful - Thu Sep 21 05:34:37 2023 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX II ; +; Device ; EPM240T100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 197 / 240 ( 82 % ) ; +; Total pins ; 70 / 80 ( 88 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------+---------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------+ @@ -129,20 +129,20 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.02 ; +; Average used ; 1.03 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.9% ; -; Processors 3-4 ; 0.7% ; +; Processor 2 ; 1.2% ; +; Processors 3-4 ; 1.1% ; +----------------------------+-------------+ +--------------+ ; Pin-Out File ; +--------------+ -The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin. +The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin. +---------------------------------------------------------------------+ @@ -150,31 +150,31 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi +---------------------------------------------+-----------------------+ ; Resource ; Usage ; +---------------------------------------------+-----------------------+ -; Total logic elements ; 209 / 240 ( 87 % ) ; -; -- Combinational with no register ; 95 ; +; Total logic elements ; 197 / 240 ( 82 % ) ; +; -- Combinational with no register ; 85 ; ; -- Register only ; 19 ; -; -- Combinational with a register ; 95 ; +; -- Combinational with a register ; 93 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 99 ; -; -- 3 input functions ; 33 ; -; -- 2 input functions ; 53 ; -; -- 1 input functions ; 4 ; +; -- 4 input functions ; 103 ; +; -- 3 input functions ; 29 ; +; -- 2 input functions ; 42 ; +; -- 1 input functions ; 3 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 195 ; +; -- normal mode ; 183 ; ; -- arithmetic mode ; 14 ; ; -- qfbk mode ; 8 ; ; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 10 ; +; -- synchronous clear/load mode ; 12 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 114 / 240 ( 48 % ) ; +; Total registers ; 112 / 240 ( 47 % ) ; ; Total LABs ; 24 / 24 ( 100 % ) ; ; Logic elements in carry chains ; 15 ; ; Virtual pins ; 0 ; -; I/O pins ; 71 / 80 ( 89 % ) ; +; I/O pins ; 70 / 80 ( 88 % ) ; ; -- Clock pins ; 3 / 4 ( 75 % ) ; ; ; ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -185,12 +185,12 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi ; Global signals ; 1 ; ; -- Global clocks ; 1 / 4 ( 25 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 22.4% / 22.7% / 22.1% ; -; Peak interconnect usage (total/H/V) ; 22.4% / 22.7% / 22.1% ; -; Maximum fan-out ; 114 ; -; Highest non-global fan-out ; 36 ; -; Total fan-out ; 872 ; -; Average fan-out ; 3.10 ; +; Average interconnect usage (total/H/V) ; 22.5% / 24.3% / 20.7% ; +; Peak interconnect usage (total/H/V) ; 22.5% / 24.3% / 20.7% ; +; Maximum fan-out ; 112 ; +; Highest non-global fan-out ; 31 ; +; Total fan-out ; 847 ; +; Average fan-out ; 3.16 ; +---------------------------------------------+-----------------------+ @@ -207,16 +207,16 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi ; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 114 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 112 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 14 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 12 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; +; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 5 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; ; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; @@ -231,31 +231,30 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ ; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; +; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; ; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RCLK ; 81 ; 2 ; 6 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 8mA ; no ; User ; 10 pF ; - ; - ; ; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; @@ -265,8 +264,8 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi ; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nCAS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nRAS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nRWE ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; @@ -295,7 +294,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi ; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; +----------+-------------------+---------------+--------------+ ; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ; -; 2 ; 33 / 42 ( 79 % ) ; 3.3V ; -- ; +; 2 ; 32 / 42 ( 76 % ) ; 3.3V ; -- ; +----------+-------------------+---------------+--------------+ @@ -384,7 +383,7 @@ The pin-out file can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pi ; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 81 ; 65 ; 2 ; RCLK ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; +; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; ; 84 ; 68 ; 2 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; @@ -429,7 +428,7 @@ Note: User assignments will override these defaults. The user specified values a +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ -; |RAM2E ; 209 (209) ; 114 ; 1 ; 71 ; 0 ; 95 (95) ; 19 (19) ; 95 (95) ; 15 (15) ; 8 (8) ; |RAM2E ; RAM2E ; work ; +; |RAM2E ; 197 (197) ; 112 ; 1 ; 70 ; 0 ; 85 (85) ; 19 (19) ; 93 (93) ; 15 (15) ; 8 (8) ; |RAM2E ; RAM2E ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ; ; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ @@ -441,7 +440,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------+----------+---------------+ ; Name ; Pin Type ; Pad to Core 0 ; +---------+----------+---------------+ -; RCLK ; Output ; -- ; ; LED ; Output ; -- ; ; Dout[0] ; Output ; -- ; ; Dout[1] ; Output ; -- ; @@ -493,8 +491,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; nEN80 ; Input ; (0) ; ; nWE ; Input ; (0) ; ; PHI1 ; Input ; (1) ; -; C14M ; Input ; (0) ; ; Din[0] ; Input ; (0) ; +; C14M ; Input ; (0) ; ; nWE80 ; Input ; (0) ; ; Ain[0] ; Input ; (0) ; ; Ain[1] ; Input ; (0) ; @@ -515,23 +513,22 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +---------+----------+---------------+ -+---------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+--------------+-------------+---------+---------------+--------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; -+--------------+-------------+---------+---------------+--------+----------------------+------------------+ -; C14M ; PIN_12 ; 114 ; Clock ; yes ; Global Clock ; GCLK0 ; -; CS[0]~2 ; LC_X6_Y2_N5 ; 3 ; Clock enable ; no ; -- ; -- ; -; Equal17~1 ; LC_X7_Y2_N8 ; 16 ; Clock enable ; no ; -- ; -- ; -; Equal17~2 ; LC_X7_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ; -; RA[0]~15 ; LC_X2_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ; -; RDOE ; LC_X3_Y4_N4 ; 8 ; Output enable ; no ; -- ; -- ; -; RWMask~1 ; LC_X4_Y2_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -; S[2] ; LC_X5_Y1_N4 ; 22 ; Sync. clear ; no ; -- ; -- ; -; UFMD[7]~0 ; LC_X3_Y2_N0 ; 9 ; Clock enable ; no ; -- ; -- ; -; UFMProgram~3 ; LC_X3_Y3_N1 ; 2 ; Clock enable ; no ; -- ; -- ; -; always4~10 ; LC_X5_Y2_N5 ; 16 ; Clock enable ; no ; -- ; -- ; -+--------------+-------------+---------+---------------+--------+----------------------+------------------+ ++-------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++------------+-------------+---------+---------------+--------+----------------------+------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; ++------------+-------------+---------+---------------+--------+----------------------+------------------+ +; C14M ; PIN_12 ; 112 ; Clock ; yes ; Global Clock ; GCLK0 ; +; CS[0]~2 ; LC_X3_Y2_N8 ; 3 ; Clock enable ; no ; -- ; -- ; +; Equal9~1 ; LC_X3_Y3_N0 ; 16 ; Clock enable ; no ; -- ; -- ; +; Equal9~2 ; LC_X7_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ; +; RA[0]~15 ; LC_X2_Y2_N0 ; 8 ; Clock enable ; no ; -- ; -- ; +; RDOE ; LC_X3_Y3_N5 ; 8 ; Output enable ; no ; -- ; -- ; +; RWMask~1 ; LC_X4_Y1_N4 ; 8 ; Clock enable ; no ; -- ; -- ; +; S[2] ; LC_X6_Y3_N6 ; 22 ; Sync. clear ; no ; -- ; -- ; +; UFMD[15]~0 ; LC_X6_Y1_N2 ; 8 ; Clock enable ; no ; -- ; -- ; +; always2~8 ; LC_X3_Y3_N7 ; 16 ; Clock enable ; no ; -- ; -- ; ++------------+-------------+---------+---------------+--------+----------------------+------------------+ +---------------------------------------------------------------------+ @@ -539,7 +536,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------+----------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +------+----------+---------+----------------------+------------------+ -; C14M ; PIN_12 ; 114 ; Global Clock ; GCLK0 ; +; C14M ; PIN_12 ; 112 ; Global Clock ; GCLK0 ; +------+----------+---------+----------------------+------------------+ @@ -548,115 +545,120 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------+--------------------+ ; Routing Resource Type ; Usage ; +-----------------------+--------------------+ -; C4s ; 138 / 784 ( 18 % ) ; -; Direct links ; 37 / 888 ( 4 % ) ; +; C4s ; 139 / 784 ( 18 % ) ; +; Direct links ; 38 / 888 ( 4 % ) ; ; Global clocks ; 1 / 4 ( 25 % ) ; ; LAB clocks ; 6 / 32 ( 19 % ) ; -; LUT chains ; 5 / 216 ( 2 % ) ; -; Local interconnects ; 268 / 888 ( 30 % ) ; -; R4s ; 126 / 704 ( 18 % ) ; +; LUT chains ; 4 / 216 ( 2 % ) ; +; Local interconnects ; 282 / 888 ( 32 % ) ; +; R4s ; 134 / 704 ( 19 % ) ; +-----------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 8.71) ; Number of LABs (Total = 24) ; +; Number of Logic Elements (Average = 8.21) ; Number of LABs (Total = 24) ; +--------------------------------------------+------------------------------+ -; 1 ; 0 ; +; 1 ; 2 ; ; 2 ; 0 ; -; 3 ; 2 ; -; 4 ; 1 ; -; 5 ; 0 ; -; 6 ; 2 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 1 ; ; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 1 ; -; 10 ; 17 ; +; 8 ; 3 ; +; 9 ; 3 ; +; 10 ; 13 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.33) ; Number of LABs (Total = 24) ; +; LAB-wide Signals (Average = 1.38) ; Number of LABs (Total = 24) ; +------------------------------------+------------------------------+ -; 1 Clock ; 22 ; -; 1 Clock enable ; 7 ; -; 2 Clock enables ; 3 ; +; 1 Clock ; 23 ; +; 1 Clock enable ; 9 ; +; 2 Clock enables ; 1 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 8.96) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced (Average = 8.54) ; Number of LABs (Total = 24) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 0 ; +; 1 ; 2 ; ; 2 ; 0 ; -; 3 ; 2 ; -; 4 ; 1 ; -; 5 ; 0 ; -; 6 ; 2 ; +; 3 ; 1 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 1 ; ; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 1 ; -; 10 ; 16 ; -; 11 ; 0 ; -; 12 ; 0 ; +; 8 ; 3 ; +; 9 ; 2 ; +; 10 ; 11 ; +; 11 ; 1 ; +; 12 ; 1 ; ; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 0 ; -; 16 ; 1 ; +; 14 ; 1 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 6.04) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced Out (Average = 6.33) ; Number of LABs (Total = 24) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 1 ; -; 3 ; 4 ; +; 1 ; 2 ; +; 2 ; 0 ; +; 3 ; 2 ; ; 4 ; 2 ; -; 5 ; 1 ; -; 6 ; 6 ; -; 7 ; 4 ; -; 8 ; 3 ; -; 9 ; 1 ; -; 10 ; 1 ; -; 11 ; 1 ; +; 5 ; 3 ; +; 6 ; 4 ; +; 7 ; 3 ; +; 8 ; 2 ; +; 9 ; 2 ; +; 10 ; 3 ; +; 11 ; 0 ; +; 12 ; 1 ; +-------------------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 10.25) ; Number of LABs (Total = 24) ; +; Number of Distinct Inputs (Average = 10.42) ; Number of LABs (Total = 24) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 0 ; -; 3 ; 1 ; -; 4 ; 2 ; +; 3 ; 3 ; +; 4 ; 0 ; ; 5 ; 2 ; -; 6 ; 1 ; -; 7 ; 0 ; +; 6 ; 2 ; +; 7 ; 1 ; ; 8 ; 3 ; -; 9 ; 3 ; -; 10 ; 1 ; +; 9 ; 1 ; +; 10 ; 0 ; ; 11 ; 2 ; ; 12 ; 2 ; ; 13 ; 1 ; -; 14 ; 0 ; -; 15 ; 2 ; +; 14 ; 2 ; +; 15 ; 1 ; ; 16 ; 1 ; -; 17 ; 2 ; +; 17 ; 1 ; ; 18 ; 0 ; ; 19 ; 1 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 1 ; +----------------------------------------------+------------------------------+ @@ -699,12 +701,10 @@ Info (332111): Found 3 clocks Info (332111): 69.841 C14M Info (332111): 200.000 DRCLK Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 8 +Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 8 Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments -Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes - Warning (186483): Ignored assignment to node "nCS" because the DATAIN port is unconnected File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 43 Info (186469): Finished processing fast register assignments Info (176235): Finished register packing Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 @@ -715,25 +715,25 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 Info (170193): Fitter routing operations beginning -Info (170089): 4e+01 ns of routing delay (approximately 2.5% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. -Info (170195): Router estimated average interconnect usage is 21% of the available device resources - Info (170196): Router estimated peak interconnect usage is 21% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 +Info (170089): 5e+01 ns of routing delay (approximately 3.1% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. +Info (170195): Router estimated average interconnect usage is 20% of the available device resources + Info (170196): Router estimated peak interconnect usage is 20% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. Info (170201): Optimizations that may affect the design's routability were skipped -Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.45 seconds. +Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 +Info (11888): Total time spent on timing analysis during the Fitter is 0.83 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 -Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg -Info: Quartus Prime Fitter was successful. 0 errors, 3 warnings - Info: Peak virtual memory: 13750 megabytes - Info: Processing ended: Tue Nov 21 06:54:39 2023 - Info: Elapsed time: 00:00:06 +Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg +Info: Quartus Prime Fitter was successful. 0 errors, 1 warning + Info: Peak virtual memory: 13770 megabytes + Info: Processing ended: Thu Sep 21 05:34:37 2023 + Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:04 +----------------------------+ ; Fitter Suppressed Messages ; +----------------------------+ -The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg. +The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg. diff --git a/CPLD/MAXII/output_files/RAM2E.fit.summary b/CPLD/MAXII/output_files/RAM2E.fit.summary index 5b8bfe7..f06b8fb 100644 --- a/CPLD/MAXII/output_files/RAM2E.fit.summary +++ b/CPLD/MAXII/output_files/RAM2E.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Successful - Tue Nov 21 06:54:39 2023 -Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Fitter Status : Successful - Thu Sep 21 05:34:37 2023 +Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2E Top-level Entity Name : RAM2E Family : MAX II Device : EPM240T100C5 Timing Models : Final -Total logic elements : 209 / 240 ( 87 % ) -Total pins : 71 / 80 ( 89 % ) +Total logic elements : 197 / 240 ( 82 % ) +Total pins : 70 / 80 ( 88 % ) Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM2E.flow.rpt b/CPLD/MAXII/output_files/RAM2E.flow.rpt index e4c1ec2..ecb9121 100644 --- a/CPLD/MAXII/output_files/RAM2E.flow.rpt +++ b/CPLD/MAXII/output_files/RAM2E.flow.rpt @@ -1,6 +1,6 @@ Flow report for RAM2E -Tue Nov 21 06:54:45 2023 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Thu Sep 21 05:34:45 2023 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -38,21 +38,21 @@ https://fpgasoftware.intel.com/eula. -+-------------------------------------------------------------------------------------+ -; Flow Summary ; -+-----------------------+-------------------------------------------------------------+ -; Flow Status ; Successful - Tue Nov 21 06:54:42 2023 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 209 / 240 ( 87 % ) ; -; Total pins ; 71 / 80 ( 89 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------+-------------------------------------------------------------+ ++---------------------------------------------------------------------+ +; Flow Summary ; ++-----------------------+---------------------------------------------+ +; Flow Status ; Successful - Thu Sep 21 05:34:41 2023 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX II ; +; Device ; EPM240T100C5 ; +; Timing Models ; Final ; +; Total logic elements ; 197 / 240 ( 82 % ) ; +; Total pins ; 70 / 80 ( 88 % ) ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------+---------------------------------------------+ +-----------------------------------------+ @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 11/21/2023 06:54:05 ; +; Start date & time ; 09/21/2023 05:33:57 ; ; Main task ; Compilation ; ; Revision Name ; RAM2E ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------+------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 121381084694.170056764503816 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 121381084694.169528883703908 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; @@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:28 ; 1.0 ; 13107 MB ; 00:00:45 ; -; Fitter ; 00:00:06 ; 1.0 ; 13750 MB ; 00:00:04 ; -; Assembler ; 00:00:01 ; 1.0 ; 13068 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:02 ; 1.0 ; 13066 MB ; 00:00:01 ; -; Total ; 00:00:37 ; -- ; -- ; 00:00:51 ; +; Analysis & Synthesis ; 00:00:35 ; 1.0 ; 13144 MB ; 00:00:49 ; +; Fitter ; 00:00:04 ; 1.0 ; 13770 MB ; 00:00:04 ; +; Assembler ; 00:00:02 ; 1.0 ; 13091 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:02 ; 1.0 ; 13089 MB ; 00:00:02 ; +; Total ; 00:00:43 ; -- ; -- ; 00:00:56 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2E.jdi b/CPLD/MAXII/output_files/RAM2E.jdi index dad2d4f..eb86129 100644 --- a/CPLD/MAXII/output_files/RAM2E.jdi +++ b/CPLD/MAXII/output_files/RAM2E.jdi @@ -1,6 +1,6 @@ - + diff --git a/CPLD/MAXII/output_files/RAM2E.map.rpt b/CPLD/MAXII/output_files/RAM2E.map.rpt index 3e74109..da29b55 100644 --- a/CPLD/MAXII/output_files/RAM2E.map.rpt +++ b/CPLD/MAXII/output_files/RAM2E.map.rpt @@ -1,6 +1,6 @@ Analysis & Synthesis report for RAM2E -Tue Nov 21 06:54:32 2023 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Thu Sep 21 05:34:32 2023 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition --------------------- @@ -43,19 +43,19 @@ https://fpgasoftware.intel.com/eula. -+-------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+-----------------------------+-------------------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Tue Nov 21 06:54:32 2023 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX II ; -; Total logic elements ; 217 ; -; Total pins ; 71 ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------------+-------------------------------------------------------------+ ++---------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:34:32 2023 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX II ; +; Total logic elements ; 205 ; +; Total pins ; 70 ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------------+---------------------------------------------+ +------------------------------------------------------------------------------------------------------------+ @@ -146,15 +146,15 @@ https://fpgasoftware.intel.com/eula. +----------------------------+-------------+ -+-------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------+---------+ -; ../RAM2E-MAX.v ; yes ; User Verilog HDL File ; Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v ; ; -; UFM.v ; yes ; User Wizard-Generated File ; Y:/Repos/RAM2E/CPLD/MAXII/UFM.v ; ; -; ../RAM2E-MAX.mif ; yes ; User Memory Initialization File ; Y:/Repos/RAM2E/CPLD/RAM2E-MAX.mif ; ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------+---------+ ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+ +; ../RAM2E-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v ; ; +; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.mif ; ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+ +-----------------------------------------------------+ @@ -162,34 +162,34 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 217 ; -; -- Combinational with no register ; 103 ; +; Total logic elements ; 205 ; +; -- Combinational with no register ; 93 ; ; -- Register only ; 27 ; -; -- Combinational with a register ; 87 ; +; -- Combinational with a register ; 85 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 99 ; -; -- 3 input functions ; 33 ; -; -- 2 input functions ; 53 ; -; -- 1 input functions ; 4 ; +; -- 4 input functions ; 103 ; +; -- 3 input functions ; 29 ; +; -- 2 input functions ; 42 ; +; -- 1 input functions ; 3 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 203 ; +; -- normal mode ; 191 ; ; -- arithmetic mode ; 14 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 1 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 114 ; +; Total registers ; 112 ; ; Total logic cells in carry chains ; 15 ; -; I/O pins ; 71 ; +; I/O pins ; 70 ; ; UFM blocks ; 1 ; ; Maximum fan-out node ; C14M ; -; Maximum fan-out ; 114 ; -; Total fan-out ; 873 ; -; Average fan-out ; 3.02 ; +; Maximum fan-out ; 112 ; +; Total fan-out ; 850 ; +; Average fan-out ; 3.08 ; +---------------------------------------------+-------+ @@ -198,7 +198,7 @@ https://fpgasoftware.intel.com/eula. +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ -; |RAM2E ; 217 (217) ; 114 ; 1 ; 71 ; 0 ; 103 (103) ; 27 (27) ; 87 (87) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ; +; |RAM2E ; 205 (205) ; 112 ; 1 ; 70 ; 0 ; 93 (93) ; 27 (27) ; 85 (85) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ; ; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ @@ -219,12 +219,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 114 ; +; Total registers ; 112 ; ; Number of registers using Synchronous Clear ; 1 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 63 ; +; Number of registers using Clock Enable ; 60 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -234,12 +234,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------+---------+ ; Inverted Register ; Fan out ; +----------------------------------------+---------+ +; nCS~reg0 ; 1 ; ; nRAS~reg0 ; 1 ; ; nCAS~reg0 ; 1 ; ; nRWE~reg0 ; 1 ; ; DQML~reg0 ; 1 ; ; DQMH~reg0 ; 1 ; -; Total number of inverted registers = 5 ; ; +; Total number of inverted registers = 6 ; ; +----------------------------------------+---------+ @@ -249,7 +250,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |RAM2E|RA[0]~reg0 ; -; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[1] ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ; ; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[0] ; ; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RWMask[4] ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ @@ -271,37 +272,35 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis - Info: Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition - Info: Processing started: Tue Nov 21 06:54:04 2023 + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Thu Sep 21 05:33:57 2023 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (12021): Found 1 design units, including 1 entities, in source file /repos/ram2e/cpld/ram2e-max.v - Info (12023): Found entity 1: RAM2E File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1 +Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2e/cpld/ram2e-max.v + Info (12023): Found entity 1: RAM2E File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1 Info (12021): Found 2 design units, including 2 entities, in source file ufm.v - Info (12023): Found entity 1: UFM_altufm_none_lbr File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47 - Info (12023): Found entity 2: UFM File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166 + Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47 + Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166 Info (12127): Elaborating entity "RAM2E" for the top level hierarchy -Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 98 -Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217 -Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "nCS" is stuck at GND File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 43 -Info (21057): Implemented 289 device resources after synthesis - the final resource count might be different +Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 93 +Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217 +Info (21057): Implemented 276 device resources after synthesis - the final resource count might be different Info (21058): Implemented 22 input pins - Info (21059): Implemented 41 output pins + Info (21059): Implemented 40 output pins Info (21060): Implemented 8 bidirectional pins - Info (21061): Implemented 217 logic cells + Info (21061): Implemented 205 logic cells Info (21070): Implemented 1 User Flash Memory blocks -Info (144001): Generated suppressed messages file Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg -Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 2 warnings - Info: Peak virtual memory: 13107 megabytes - Info: Processing ended: Tue Nov 21 06:54:32 2023 - Info: Elapsed time: 00:00:28 - Info: Total CPU time (on all processors): 00:00:45 +Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 13144 megabytes + Info: Processing ended: Thu Sep 21 05:34:32 2023 + Info: Elapsed time: 00:00:35 + Info: Total CPU time (on all processors): 00:00:49 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ -The suppressed messages can be found in Y:/Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg. +The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg. diff --git a/CPLD/MAXII/output_files/RAM2E.map.smsg b/CPLD/MAXII/output_files/RAM2E.map.smsg index 2f8dc57..06be456 100644 --- a/CPLD/MAXII/output_files/RAM2E.map.smsg +++ b/CPLD/MAXII/output_files/RAM2E.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM2E-MAX.v(51): extended using "x" or "z" File: Y:/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 51 -Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73 -Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: Y:/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189 +Warning (10273): Verilog HDL warning at RAM2E-MAX.v(46): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 46 +Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189 diff --git a/CPLD/MAXII/output_files/RAM2E.map.summary b/CPLD/MAXII/output_files/RAM2E.map.summary index 75fae6d..8b68ed4 100644 --- a/CPLD/MAXII/output_files/RAM2E.map.summary +++ b/CPLD/MAXII/output_files/RAM2E.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Tue Nov 21 06:54:32 2023 -Quartus Prime Version : 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Analysis & Synthesis Status : Successful - Thu Sep 21 05:34:32 2023 +Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2E Top-level Entity Name : RAM2E Family : MAX II -Total logic elements : 217 -Total pins : 71 +Total logic elements : 205 +Total pins : 70 Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM2E.pin b/CPLD/MAXII/output_files/RAM2E.pin index ed77856..f8fa7ef 100644 --- a/CPLD/MAXII/output_files/RAM2E.pin +++ b/CPLD/MAXII/output_files/RAM2E.pin @@ -58,7 +58,7 @@ -- Pin directions (input, output or bidir) are based on device operating in user mode. --------------------------------------------------------------------------------- -Quartus Prime Version 19.1.0 Build 670 09/22/2019 Patches 0.02std SJ Lite Edition +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition CHIP "RAM2E" ASSIGNED TO AN: EPM240T100C5 Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment @@ -143,7 +143,7 @@ Dout[0] : 77 : output : 3.3-V LVCMOS : GND* : 78 : : : : 2 : GNDIO : 79 : gnd : : : : VCCIO2 : 80 : power : : 3.3V : 2 : -RCLK : 81 : output : 3.3-V LVCMOS : : 2 : Y +GND* : 81 : : : : 2 : GND* : 82 : : : : 2 : GND* : 83 : : : : 2 : Dout[6] : 84 : output : 3.3-V LVCMOS : : 2 : Y diff --git a/CPLD/MAXII/output_files/RAM2E.pof b/CPLD/MAXII/output_files/RAM2E.pof index c7ddf8e9833926c726923376d3d21ea1f0e95e44..d5b599ee334f3bd7f3560c379a9baeace736c5a3 100644 GIT binary patch literal 7861 zcmeHMe{57&b{;Pnk}83sl(y-X#M(Ant-2xnD2q_mc6O7Xs!8fpyDZsO;LR57(qwE2 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