From 73d958c1f88d16aecdca41832689fbccbabf2d00 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Mon, 12 Feb 2024 17:13:24 -0500 Subject: [PATCH] RC --- CPLD/MAXII/RAM2E.qsf | 7 ++-- CPLD/MAXII/RAM2E.qws | Bin 619 -> 619 bytes CPLD/MAXII/output_files/RAM2E.asm.rpt | 14 ++++---- CPLD/MAXII/output_files/RAM2E.done | 2 +- CPLD/MAXII/output_files/RAM2E.fit.rpt | 40 ++++++++++----------- CPLD/MAXII/output_files/RAM2E.fit.summary | 2 +- CPLD/MAXII/output_files/RAM2E.flow.rpt | 18 +++++----- CPLD/MAXII/output_files/RAM2E.map.rpt | 18 +++++----- CPLD/MAXII/output_files/RAM2E.map.smsg | 2 +- CPLD/MAXII/output_files/RAM2E.map.summary | 2 +- CPLD/MAXII/output_files/RAM2E.pof | Bin 7861 -> 7861 bytes CPLD/MAXII/output_files/RAM2E.sta.rpt | 18 +++++----- CPLD/MAXV/RAM2E.qsf | 12 ++++--- CPLD/MAXV/RAM2E.qws | Bin 619 -> 619 bytes CPLD/MAXV/output_files/RAM2E.asm.rpt | 14 ++++---- CPLD/MAXV/output_files/RAM2E.done | 2 +- CPLD/MAXV/output_files/RAM2E.fit.rpt | 42 +++++++++++----------- CPLD/MAXV/output_files/RAM2E.fit.summary | 2 +- CPLD/MAXV/output_files/RAM2E.flow.rpt | 18 +++++----- CPLD/MAXV/output_files/RAM2E.map.rpt | 18 +++++----- CPLD/MAXV/output_files/RAM2E.map.smsg | 2 +- CPLD/MAXV/output_files/RAM2E.map.summary | 2 +- CPLD/MAXV/output_files/RAM2E.pof | Bin 7861 -> 7861 bytes CPLD/MAXV/output_files/RAM2E.sta.rpt | 20 +++++------ CPLD/RAM2E.v | 7 ++-- 25 files changed, 132 insertions(+), 130 deletions(-) diff --git a/CPLD/MAXII/RAM2E.qsf b/CPLD/MAXII/RAM2E.qsf index 1cbc2e6..d0e1eb2 100644 --- a/CPLD/MAXII/RAM2E.qsf +++ b/CPLD/MAXII/RAM2E.qsf @@ -50,9 +50,10 @@ set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" -set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND" +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V set_location_assignment PIN_12 -to C14M set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M @@ -109,7 +110,7 @@ set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Din set_location_assignment PIN_55 -to nDOE set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE -set_instance_assignment -name SLOW_SLEW_RATE OFF -to nDOE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nDOE set_location_assignment PIN_77 -to Dout[0] @@ -234,10 +235,10 @@ set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" set_location_assignment PIN_88 -to LED set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED set_instance_assignment -name SLOW_SLEW_RATE ON -to LED + set_global_assignment -name VERILOG_FILE ../RAM2E.v set_global_assignment -name VERILOG_FILE "../UFM-MAX.v" set_global_assignment -name QIP_FILE UFM.qip diff --git a/CPLD/MAXII/RAM2E.qws b/CPLD/MAXII/RAM2E.qws index 6f6550b1515f374474cb1b0f7c4812ab3f4023cb..0056834e4465c3e2c6673f15896dcdffdf1da448 100644 GIT binary patch delta 64 zcmaFO@|tDBLMCQ`iHog-m<1RZ7!nx%|Nqaxz&L?{fmvYV`vgWArpZ7iKTrw`fU^HU K7|3B{VgLYW!xMG@ delta 64 zcmaFO@|tDBLMEoE6BkJ)U`Sy2|NlRbKElAjGi_@% diff --git a/CPLD/MAXII/output_files/RAM2E.asm.rpt b/CPLD/MAXII/output_files/RAM2E.asm.rpt index aac89fe..11f86d4 100644 --- a/CPLD/MAXII/output_files/RAM2E.asm.rpt +++ b/CPLD/MAXII/output_files/RAM2E.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2E -Wed Feb 07 19:21:24 2024 +Mon Feb 12 17:00:22 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Wed Feb 07 19:21:24 2024 ; +; Assembler Status ; Successful - Mon Feb 12 17:00:22 2024 ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; ; Family ; MAX II ; @@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula. +----------------+---------------------------------------------------------+ ; Option ; Setting ; +----------------+---------------------------------------------------------+ -; JTAG usercode ; 0x00164C1D ; -; Checksum ; 0x00165015 ; +; JTAG usercode ; 0x00164C21 ; +; Checksum ; 0x00165119 ; +----------------+---------------------------------------------------------+ @@ -78,13 +78,13 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Wed Feb 07 19:21:23 2024 + Info: Processing started: Mon Feb 12 17:00:21 2024 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 13061 megabytes - Info: Processing ended: Wed Feb 07 19:21:24 2024 + Info: Peak virtual memory: 13104 megabytes + Info: Processing ended: Mon Feb 12 17:00:22 2024 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXII/output_files/RAM2E.done b/CPLD/MAXII/output_files/RAM2E.done index 76f8d8f..c5630c1 100644 --- a/CPLD/MAXII/output_files/RAM2E.done +++ b/CPLD/MAXII/output_files/RAM2E.done @@ -1 +1 @@ -Wed Feb 07 19:21:30 2024 +Mon Feb 12 17:00:25 2024 diff --git a/CPLD/MAXII/output_files/RAM2E.fit.rpt b/CPLD/MAXII/output_files/RAM2E.fit.rpt index 70b8364..f416ed2 100644 --- a/CPLD/MAXII/output_files/RAM2E.fit.rpt +++ b/CPLD/MAXII/output_files/RAM2E.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2E -Wed Feb 07 19:21:16 2024 +Mon Feb 12 17:00:20 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Wed Feb 07 19:21:16 2024 ; +; Fitter Status ; Successful - Mon Feb 12 17:00:20 2024 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; @@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.02 ; +; Average used ; 1.04 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 1.0% ; -; Processors 3-4 ; 0.6% ; +; Processor 2 ; 1.6% ; +; Processors 3-4 ; 1.2% ; +----------------------------+-------------+ @@ -265,7 +265,7 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin. ; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nRWEout ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; @@ -719,17 +719,17 @@ Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes - Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 @@ -742,14 +742,14 @@ Info (170195): Router estimated average interconnect usage is 26% of the availab Info (170196): Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization. Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.52 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.38 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings - Info: Peak virtual memory: 13729 megabytes - Info: Processing ended: Wed Feb 07 19:21:16 2024 - Info: Elapsed time: 00:00:16 - Info: Total CPU time (on all processors): 00:00:05 + Info: Peak virtual memory: 13771 megabytes + Info: Processing ended: Mon Feb 12 17:00:20 2024 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:04 +----------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2E.fit.summary b/CPLD/MAXII/output_files/RAM2E.fit.summary index 47e5dbe..76f88c0 100644 --- a/CPLD/MAXII/output_files/RAM2E.fit.summary +++ b/CPLD/MAXII/output_files/RAM2E.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Wed Feb 07 19:21:16 2024 +Fitter Status : Successful - Mon Feb 12 17:00:20 2024 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2E Top-level Entity Name : RAM2E diff --git a/CPLD/MAXII/output_files/RAM2E.flow.rpt b/CPLD/MAXII/output_files/RAM2E.flow.rpt index 7729fdc..ef43b45 100644 --- a/CPLD/MAXII/output_files/RAM2E.flow.rpt +++ b/CPLD/MAXII/output_files/RAM2E.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2E -Wed Feb 07 19:21:29 2024 +Mon Feb 12 17:00:24 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Wed Feb 07 19:21:24 2024 ; +; Flow Status ; Successful - Mon Feb 12 17:00:22 2024 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 02/07/2024 19:20:29 ; +; Start date & time ; 02/12/2024 16:59:52 ; ; Main task ; Compilation ; ; Revision Name ; RAM2E ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------+------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +---------------------------------------+------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 121380219419.170735162907620 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 121380219419.170777519203424 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; @@ -86,11 +86,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:31 ; 1.0 ; 13109 MB ; 00:00:43 ; -; Fitter ; 00:00:16 ; 1.0 ; 13729 MB ; 00:00:05 ; -; Assembler ; 00:00:01 ; 1.0 ; 13057 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:03 ; 1.0 ; 13073 MB ; 00:00:02 ; -; Total ; 00:00:51 ; -- ; -- ; 00:00:51 ; +; Analysis & Synthesis ; 00:00:24 ; 1.0 ; 13133 MB ; 00:00:40 ; +; Fitter ; 00:00:03 ; 1.0 ; 13771 MB ; 00:00:04 ; +; Assembler ; 00:00:01 ; 1.0 ; 13100 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:01 ; 1.0 ; 13090 MB ; 00:00:01 ; +; Total ; 00:00:29 ; -- ; -- ; 00:00:46 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2E.map.rpt b/CPLD/MAXII/output_files/RAM2E.map.rpt index 761a538..2d5584d 100644 --- a/CPLD/MAXII/output_files/RAM2E.map.rpt +++ b/CPLD/MAXII/output_files/RAM2E.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2E -Wed Feb 07 19:20:58 2024 +Mon Feb 12 17:00:15 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Feb 07 19:20:58 2024 ; +; Analysis & Synthesis Status ; Successful - Mon Feb 12 17:00:15 2024 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; @@ -282,7 +282,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Wed Feb 07 19:20:27 2024 + Info: Processing started: Mon Feb 12 16:59:51 2024 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E Info (20032): Parallel compilation is enabled and will use up to 4 processors Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v @@ -293,11 +293,11 @@ Info (12021): Found 2 design units, including 2 entities, in source file ufm.v Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47 Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166 Info (12127): Elaborating entity "RAM2E" for the top level hierarchy -Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 137 +Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 136 Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 78 Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217 Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 76 + Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 75 Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 @@ -316,10 +316,10 @@ Info (21057): Implemented 323 device resources after synthesis - the final resou Info (21070): Implemented 1 User Flash Memory blocks Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings - Info: Peak virtual memory: 13109 megabytes - Info: Processing ended: Wed Feb 07 19:20:58 2024 - Info: Elapsed time: 00:00:31 - Info: Total CPU time (on all processors): 00:00:43 + Info: Peak virtual memory: 13133 megabytes + Info: Processing ended: Mon Feb 12 17:00:15 2024 + Info: Elapsed time: 00:00:24 + Info: Total CPU time (on all processors): 00:00:40 +------------------------------------------+ diff --git a/CPLD/MAXII/output_files/RAM2E.map.smsg b/CPLD/MAXII/output_files/RAM2E.map.smsg index d2971d0..c004b75 100644 --- a/CPLD/MAXII/output_files/RAM2E.map.smsg +++ b/CPLD/MAXII/output_files/RAM2E.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM2E.v(73): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 73 +Warning (10273): Verilog HDL warning at RAM2E.v(72): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 72 Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73 Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189 diff --git a/CPLD/MAXII/output_files/RAM2E.map.summary b/CPLD/MAXII/output_files/RAM2E.map.summary index c3d39e5..ce1b771 100644 --- a/CPLD/MAXII/output_files/RAM2E.map.summary +++ b/CPLD/MAXII/output_files/RAM2E.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Wed Feb 07 19:20:58 2024 +Analysis & Synthesis Status : Successful - Mon Feb 12 17:00:15 2024 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2E Top-level Entity Name : RAM2E diff --git a/CPLD/MAXII/output_files/RAM2E.pof b/CPLD/MAXII/output_files/RAM2E.pof index bd2e74bebcba2d1a3f7ba7c73d2244307a47db7b..c81c57385ffb1fa577ee63fd9f79b3bd7bf364c0 100644 GIT binary patch delta 42 scmdmLyVZ7s6eHvR$o J267mg7yw~X6EXk* delta 64 zcmaFO@|tDBLMEoE6BkJ)U`Sy2|NlRbKElAjGi_@% diff --git a/CPLD/MAXV/output_files/RAM2E.asm.rpt b/CPLD/MAXV/output_files/RAM2E.asm.rpt index 65366ef..3ddc06b 100644 --- a/CPLD/MAXV/output_files/RAM2E.asm.rpt +++ b/CPLD/MAXV/output_files/RAM2E.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2E -Wed Feb 07 19:21:24 2024 +Mon Feb 12 17:00:20 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -38,7 +38,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Wed Feb 07 19:21:24 2024 ; +; Assembler Status ; Successful - Mon Feb 12 17:00:20 2024 ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; ; Family ; MAX V ; @@ -67,8 +67,8 @@ https://fpgasoftware.intel.com/eula. +----------------+--------------------------------------------------------+ ; Option ; Setting ; +----------------+--------------------------------------------------------+ -; JTAG usercode ; 0x001651A3 ; -; Checksum ; 0x00165523 ; +; JTAG usercode ; 0x001651A7 ; +; Checksum ; 0x001654A7 ; +----------------+--------------------------------------------------------+ @@ -78,13 +78,13 @@ https://fpgasoftware.intel.com/eula. Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Wed Feb 07 19:21:23 2024 + Info: Processing started: Mon Feb 12 17:00:19 2024 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 13069 megabytes - Info: Processing ended: Wed Feb 07 19:21:24 2024 + Info: Peak virtual memory: 13104 megabytes + Info: Processing ended: Mon Feb 12 17:00:20 2024 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/MAXV/output_files/RAM2E.done b/CPLD/MAXV/output_files/RAM2E.done index 76f8d8f..f6da932 100644 --- a/CPLD/MAXV/output_files/RAM2E.done +++ b/CPLD/MAXV/output_files/RAM2E.done @@ -1 +1 @@ -Wed Feb 07 19:21:30 2024 +Mon Feb 12 17:00:24 2024 diff --git a/CPLD/MAXV/output_files/RAM2E.fit.rpt b/CPLD/MAXV/output_files/RAM2E.fit.rpt index 8b7c649..85088e4 100644 --- a/CPLD/MAXV/output_files/RAM2E.fit.rpt +++ b/CPLD/MAXV/output_files/RAM2E.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2E -Wed Feb 07 19:21:16 2024 +Mon Feb 12 17:00:18 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -57,7 +57,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Wed Feb 07 19:21:16 2024 ; +; Fitter Status ; Successful - Mon Feb 12 17:00:18 2024 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; @@ -129,13 +129,13 @@ https://fpgasoftware.intel.com/eula. ; Number detected on machine ; 4 ; ; Maximum allowed ; 4 ; ; ; ; -; Average used ; 1.02 ; +; Average used ; 1.04 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.9% ; -; Processors 3-4 ; 0.6% ; +; Processor 2 ; 1.7% ; +; Processors 3-4 ; 1.2% ; +----------------------------+-------------+ @@ -265,7 +265,7 @@ The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin. ; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nRWEout ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; @@ -706,8 +706,8 @@ Info (176444): Device migration not selected. If you intend to use device migrat Info (176445): Device 5M240ZT100I5 is compatible Info (176445): Device 5M570ZT100C5 is compatible Info (176445): Device 5M570ZT100I5 is compatible -Info (332104): Reading SDC File: '../RAM2E-MAX.sdc' Info (332104): Reading SDC File: '../RAM2E.sdc' +Info (332104): Reading SDC File: '../RAM2E-MAX.sdc' Warning (332060): Node: PHI1 was determined to be a clock but was found without an associated clock assignment. Info (13166): Register RefReq is being clocked by PHI1 Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements @@ -727,17 +727,17 @@ Info (186079): Completed Auto Global Promotion Operation Info (176234): Starting register packing Info (186468): Started processing fast register assignments Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes - Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 - Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 86 + Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 + Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 Info (186469): Finished processing fast register assignments Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01 +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. Info (170189): Fitter placement preparation operations beginning Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 @@ -750,14 +750,14 @@ Info (170195): Router estimated average interconnect usage is 25% of the availab Info (170196): Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization. Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 -Info (11888): Total time spent on timing analysis during the Fitter is 0.50 seconds. +Info (11888): Total time spent on timing analysis during the Fitter is 0.42 seconds. Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings - Info: Peak virtual memory: 13731 megabytes - Info: Processing ended: Wed Feb 07 19:21:16 2024 - Info: Elapsed time: 00:00:16 - Info: Total CPU time (on all processors): 00:00:05 + Info: Peak virtual memory: 13772 megabytes + Info: Processing ended: Mon Feb 12 17:00:18 2024 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:04 +----------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2E.fit.summary b/CPLD/MAXV/output_files/RAM2E.fit.summary index c2414e6..6945252 100644 --- a/CPLD/MAXV/output_files/RAM2E.fit.summary +++ b/CPLD/MAXV/output_files/RAM2E.fit.summary @@ -1,4 +1,4 @@ -Fitter Status : Successful - Wed Feb 07 19:21:16 2024 +Fitter Status : Successful - Mon Feb 12 17:00:18 2024 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2E Top-level Entity Name : RAM2E diff --git a/CPLD/MAXV/output_files/RAM2E.flow.rpt b/CPLD/MAXV/output_files/RAM2E.flow.rpt index d18520c..1181004 100644 --- a/CPLD/MAXV/output_files/RAM2E.flow.rpt +++ b/CPLD/MAXV/output_files/RAM2E.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2E -Wed Feb 07 19:21:29 2024 +Mon Feb 12 17:00:23 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -41,7 +41,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------+ ; Flow Summary ; +-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Wed Feb 07 19:21:24 2024 ; +; Flow Status ; Successful - Mon Feb 12 17:00:20 2024 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; @@ -60,7 +60,7 @@ https://fpgasoftware.intel.com/eula. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 02/07/2024 19:20:29 ; +; Start date & time ; 02/12/2024 16:59:50 ; ; Main task ; Compilation ; ; Revision Name ; RAM2E ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ https://fpgasoftware.intel.com/eula. +-------------------------------+------------------------------+---------------+-------------+------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------+------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 121380219419.170735162902460 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 121380219419.170777519012180 ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; @@ -85,11 +85,11 @@ https://fpgasoftware.intel.com/eula. +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:31 ; 1.0 ; 13110 MB ; 00:00:42 ; -; Fitter ; 00:00:16 ; 1.0 ; 13731 MB ; 00:00:05 ; -; Assembler ; 00:00:01 ; 1.0 ; 13065 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:03 ; 1.0 ; 13075 MB ; 00:00:02 ; -; Total ; 00:00:51 ; -- ; -- ; 00:00:50 ; +; Analysis & Synthesis ; 00:00:24 ; 1.0 ; 13131 MB ; 00:00:39 ; +; Fitter ; 00:00:03 ; 1.0 ; 13772 MB ; 00:00:04 ; +; Assembler ; 00:00:01 ; 1.0 ; 13100 MB ; 00:00:01 ; +; Timing Analyzer ; 00:00:02 ; 1.0 ; 13094 MB ; 00:00:01 ; +; Total ; 00:00:30 ; -- ; -- ; 00:00:45 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2E.map.rpt b/CPLD/MAXV/output_files/RAM2E.map.rpt index db621d9..12bf9de 100644 --- a/CPLD/MAXV/output_files/RAM2E.map.rpt +++ b/CPLD/MAXV/output_files/RAM2E.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2E -Wed Feb 07 19:20:58 2024 +Mon Feb 12 17:00:14 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -46,7 +46,7 @@ https://fpgasoftware.intel.com/eula. +---------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Feb 07 19:20:58 2024 ; +; Analysis & Synthesis Status ; Successful - Mon Feb 12 17:00:14 2024 ; ; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; @@ -282,7 +282,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Wed Feb 07 19:20:27 2024 + Info: Processing started: Mon Feb 12 16:59:50 2024 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E Info (20032): Parallel compilation is enabled and will use up to 4 processors Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v @@ -293,11 +293,11 @@ Info (12021): Found 2 design units, including 2 entities, in source file ufm.v Info (12023): Found entity 1: UFM_altufm_none_p8r File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47 Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166 Info (12127): Elaborating entity "RAM2E" for the top level hierarchy -Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 137 +Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 136 Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 78 Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217 Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 76 + Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 75 Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 @@ -316,10 +316,10 @@ Info (21057): Implemented 323 device resources after synthesis - the final resou Info (21070): Implemented 1 User Flash Memory blocks Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings - Info: Peak virtual memory: 13110 megabytes - Info: Processing ended: Wed Feb 07 19:20:58 2024 - Info: Elapsed time: 00:00:31 - Info: Total CPU time (on all processors): 00:00:42 + Info: Peak virtual memory: 13131 megabytes + Info: Processing ended: Mon Feb 12 17:00:14 2024 + Info: Elapsed time: 00:00:24 + Info: Total CPU time (on all processors): 00:00:39 +------------------------------------------+ diff --git a/CPLD/MAXV/output_files/RAM2E.map.smsg b/CPLD/MAXV/output_files/RAM2E.map.smsg index 0ea9ac4..585149c 100644 --- a/CPLD/MAXV/output_files/RAM2E.map.smsg +++ b/CPLD/MAXV/output_files/RAM2E.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM2E.v(73): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 73 +Warning (10273): Verilog HDL warning at RAM2E.v(72): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 72 Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73 Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189 diff --git a/CPLD/MAXV/output_files/RAM2E.map.summary b/CPLD/MAXV/output_files/RAM2E.map.summary index 001a682..b9089fc 100644 --- a/CPLD/MAXV/output_files/RAM2E.map.summary +++ b/CPLD/MAXV/output_files/RAM2E.map.summary @@ -1,4 +1,4 @@ -Analysis & Synthesis Status : Successful - Wed Feb 07 19:20:58 2024 +Analysis & Synthesis Status : Successful - Mon Feb 12 17:00:14 2024 Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition Revision Name : RAM2E Top-level Entity Name : RAM2E diff --git a/CPLD/MAXV/output_files/RAM2E.pof b/CPLD/MAXV/output_files/RAM2E.pof index fbf99ed7dca5f2c51bbef955b1f98cb82f2aba13..6da4da42cf1d1244f85dc3a200cd6bfe89c1309c 100644 GIT binary patch delta 24 gcmdmLyVZ7s6eDB(W@*L-QO19p=ZJ}OFy-(70BV~DkpKVy delta 24 gcmdmLyVZ7s6eHvR&C-kwqKv;b&k+;nVA?Pd0CR*0)&Kwi diff --git a/CPLD/MAXV/output_files/RAM2E.sta.rpt b/CPLD/MAXV/output_files/RAM2E.sta.rpt index e022f78..de4820b 100644 --- a/CPLD/MAXV/output_files/RAM2E.sta.rpt +++ b/CPLD/MAXV/output_files/RAM2E.sta.rpt @@ -1,5 +1,5 @@ Timing Analyzer report for RAM2E -Wed Feb 07 19:21:29 2024 +Mon Feb 12 17:00:23 2024 Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition @@ -84,7 +84,7 @@ https://fpgasoftware.intel.com/eula. ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; -; Processor 2 ; 0.1% ; +; Processor 2 ; 0.0% ; +----------------------------+-------------+ @@ -93,8 +93,8 @@ https://fpgasoftware.intel.com/eula. +------------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +------------------+--------+--------------------------+ -; ../RAM2E-MAX.sdc ; OK ; Wed Feb 07 19:21:29 2024 ; -; ../RAM2E.sdc ; OK ; Wed Feb 07 19:21:29 2024 ; +; ../RAM2E.sdc ; OK ; Mon Feb 12 17:00:23 2024 ; +; ../RAM2E-MAX.sdc ; OK ; Mon Feb 12 17:00:23 2024 ; +------------------+--------+--------------------------+ @@ -680,7 +680,7 @@ No non-DPA dedicated SERDES Receiver circuitry present in device or used in desi Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Wed Feb 07 19:21:26 2024 + Info: Processing started: Mon Feb 12 17:00:21 2024 Info: Command: quartus_sta RAM2E-MAXV -c RAM2E Info: qsta_default_script.tcl version: #1 Info (20032): Parallel compilation is enabled and will use up to 4 processors @@ -688,8 +688,8 @@ Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully -Info (332104): Reading SDC File: '../RAM2E-MAX.sdc' Info (332104): Reading SDC File: '../RAM2E.sdc' +Info (332104): Reading SDC File: '../RAM2E-MAX.sdc' Warning (332060): Node: PHI1 was determined to be a clock but was found without an associated clock assignment. Info (13166): Register RefReq is being clocked by PHI1 Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON @@ -721,9 +721,9 @@ Info (332001): The selected device family is not supported by the report_metasta Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 13075 megabytes - Info: Processing ended: Wed Feb 07 19:21:29 2024 - Info: Elapsed time: 00:00:03 - Info: Total CPU time (on all processors): 00:00:02 + Info: Peak virtual memory: 13094 megabytes + Info: Processing ended: Mon Feb 12 17:00:23 2024 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:01 diff --git a/CPLD/RAM2E.v b/CPLD/RAM2E.v index a86de2e..216047b 100644 --- a/CPLD/RAM2E.v +++ b/CPLD/RAM2E.v @@ -44,16 +44,15 @@ module RAM2E(C14M, PHI1, LED, input [7:0] Din; reg DOEEN; always @(posedge C14M) begin - DOEEN <= S==4'hB || S==4'hC || S==4'hD || S==4'hE || S==4'hF ; + DOEEN <= S==4'hB || S==4'hC || S==4'hD || S==4'hE || S==4'hF; end output nDOE; assign nDOE = !(!nEN80 && nWE && DOEEN); output [7:0] Dout; assign Dout[7:0] = RD[7:0]; /* Video Data Bus */ - reg VOE; + reg VOE; always @(negedge C14M) begin - VOE <= S==4'h7 || S==4'h8 || S==4'h9 || - S==4'hA || S==4'hB || S==4'hC; + VOE <= S==4'h7 || S==4'h8 || S==4'h9 || S==4'hA || S==4'hB || S==4'hC; end output nVOE; assign nVOE = !VOE; output reg [7:0] Vout; // Video data bus