From 75f7cfe481b64cf78e12f4647957b274f243eab2 Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Thu, 6 Jun 2024 22:08:56 -0400 Subject: [PATCH] Delete old Quartus reports and output --- CPLD/MAXII/output_files/RAM2E.asm.rpt | 91 --- CPLD/MAXII/output_files/RAM2E.done | 1 - CPLD/MAXII/output_files/RAM2E.fit.rpt | 760 --------------------- CPLD/MAXII/output_files/RAM2E.fit.smsg | 4 - CPLD/MAXII/output_files/RAM2E.fit.summary | 11 - CPLD/MAXII/output_files/RAM2E.flow.rpt | 118 ---- CPLD/MAXII/output_files/RAM2E.jdi | 8 - CPLD/MAXII/output_files/RAM2E.map.rpt | 330 ---------- CPLD/MAXII/output_files/RAM2E.map.smsg | 3 - CPLD/MAXII/output_files/RAM2E.map.summary | 9 - CPLD/MAXII/output_files/RAM2E.pin | 165 ----- CPLD/MAXII/output_files/RAM2E.pof | Bin 7861 -> 0 bytes CPLD/MAXII/output_files/RAM2E.sld | 1 - CPLD/MAXII/output_files/RAM2E.sta.rpt | 729 -------------------- CPLD/MAXII/output_files/RAM2E.sta.summary | 41 -- CPLD/MAXV/output_files/RAM2E.asm.rpt | 91 --- CPLD/MAXV/output_files/RAM2E.done | 1 - CPLD/MAXV/output_files/RAM2E.fit.rpt | 768 ---------------------- CPLD/MAXV/output_files/RAM2E.fit.smsg | 4 - CPLD/MAXV/output_files/RAM2E.fit.summary | 11 - CPLD/MAXV/output_files/RAM2E.flow.rpt | 117 ---- CPLD/MAXV/output_files/RAM2E.jdi | 8 - CPLD/MAXV/output_files/RAM2E.map.rpt | 330 ---------- CPLD/MAXV/output_files/RAM2E.map.smsg | 3 - CPLD/MAXV/output_files/RAM2E.map.summary | 9 - CPLD/MAXV/output_files/RAM2E.pin | 165 ----- CPLD/MAXV/output_files/RAM2E.pof | Bin 7861 -> 0 bytes CPLD/MAXV/output_files/RAM2E.sld | 1 - CPLD/MAXV/output_files/RAM2E.sta.rpt | 729 -------------------- CPLD/MAXV/output_files/RAM2E.sta.summary | 41 -- 30 files changed, 4549 deletions(-) delete mode 100644 CPLD/MAXII/output_files/RAM2E.asm.rpt delete mode 100644 CPLD/MAXII/output_files/RAM2E.done delete mode 100644 CPLD/MAXII/output_files/RAM2E.fit.rpt delete mode 100644 CPLD/MAXII/output_files/RAM2E.fit.smsg delete mode 100644 CPLD/MAXII/output_files/RAM2E.fit.summary delete mode 100644 CPLD/MAXII/output_files/RAM2E.flow.rpt delete mode 100644 CPLD/MAXII/output_files/RAM2E.jdi delete mode 100644 CPLD/MAXII/output_files/RAM2E.map.rpt delete mode 100644 CPLD/MAXII/output_files/RAM2E.map.smsg delete mode 100644 CPLD/MAXII/output_files/RAM2E.map.summary delete mode 100644 CPLD/MAXII/output_files/RAM2E.pin delete mode 100644 CPLD/MAXII/output_files/RAM2E.pof delete mode 100644 CPLD/MAXII/output_files/RAM2E.sld delete mode 100644 CPLD/MAXII/output_files/RAM2E.sta.rpt delete mode 100644 CPLD/MAXII/output_files/RAM2E.sta.summary delete mode 100644 CPLD/MAXV/output_files/RAM2E.asm.rpt delete mode 100644 CPLD/MAXV/output_files/RAM2E.done delete mode 100644 CPLD/MAXV/output_files/RAM2E.fit.rpt delete mode 100644 CPLD/MAXV/output_files/RAM2E.fit.smsg delete mode 100644 CPLD/MAXV/output_files/RAM2E.fit.summary delete mode 100644 CPLD/MAXV/output_files/RAM2E.flow.rpt delete mode 100644 CPLD/MAXV/output_files/RAM2E.jdi delete mode 100644 CPLD/MAXV/output_files/RAM2E.map.rpt delete mode 100644 CPLD/MAXV/output_files/RAM2E.map.smsg delete mode 100644 CPLD/MAXV/output_files/RAM2E.map.summary delete mode 100644 CPLD/MAXV/output_files/RAM2E.pin delete mode 100644 CPLD/MAXV/output_files/RAM2E.pof delete mode 100644 CPLD/MAXV/output_files/RAM2E.sld delete mode 100644 CPLD/MAXV/output_files/RAM2E.sta.rpt delete mode 100644 CPLD/MAXV/output_files/RAM2E.sta.summary diff --git a/CPLD/MAXII/output_files/RAM2E.asm.rpt b/CPLD/MAXII/output_files/RAM2E.asm.rpt deleted file mode 100644 index 8eb1daa..0000000 --- a/CPLD/MAXII/output_files/RAM2E.asm.rpt +++ /dev/null @@ -1,91 +0,0 @@ -Assembler report for RAM2E -Thu Feb 15 04:16:27 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof - 6. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2019 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Feb 15 04:16:27 2024 ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; -+-----------------------+---------------------------------------+ - - -+----------------------------------+ -; Assembler Settings ; -+--------+---------+---------------+ -; Option ; Setting ; Default Value ; -+--------+---------+---------------+ - - -+------------------------------------------------+ -; Assembler Generated Files ; -+------------------------------------------------+ -; File Name ; -+------------------------------------------------+ -; /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ; -+------------------------------------------------+ - - -+--------------------------------------------------------------------------+ -; Assembler Device Options: /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pof ; -+----------------+---------------------------------------------------------+ -; Option ; Setting ; -+----------------+---------------------------------------------------------+ -; JTAG usercode ; 0x00164C21 ; -; Checksum ; 0x00165119 ; -+----------------+---------------------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus Prime Assembler - Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Thu Feb 15 04:16:25 2024 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E -Info (115031): Writing out detailed assembly data for power analysis -Info (115030): Assembler is generating device programming files -Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 13103 megabytes - Info: Processing ended: Thu Feb 15 04:16:27 2024 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:01 - - diff --git a/CPLD/MAXII/output_files/RAM2E.done b/CPLD/MAXII/output_files/RAM2E.done deleted file mode 100644 index a2717e2..0000000 --- a/CPLD/MAXII/output_files/RAM2E.done +++ /dev/null @@ -1 +0,0 @@ -Thu Feb 15 04:16:32 2024 diff --git a/CPLD/MAXII/output_files/RAM2E.fit.rpt b/CPLD/MAXII/output_files/RAM2E.fit.rpt deleted file mode 100644 index 5edf267..0000000 --- a/CPLD/MAXII/output_files/RAM2E.fit.rpt +++ /dev/null @@ -1,760 +0,0 @@ -Fitter report for RAM2E -Thu Feb 15 04:16:23 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. Pin-Out File - 6. Fitter Resource Usage Summary - 7. Input Pins - 8. Output Pins - 9. Bidir Pins - 10. I/O Bank Usage - 11. All Package Pins - 12. Output Pin Default Load For Reported TCO - 13. Fitter Resource Utilization by Entity - 14. Delay Chain Summary - 15. Control Signals - 16. Global & Other Fast Signals - 17. Routing Usage Summary - 18. LAB Logic Elements - 19. LAB-wide Signals - 20. LAB Signals Sourced - 21. LAB Signals Sourced Out - 22. LAB Distinct Inputs - 23. Fitter Device Options - 24. Fitter Messages - 25. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2019 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+---------------------------------------------------------------------+ -; Fitter Summary ; -+-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Thu Feb 15 04:16:23 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 238 / 240 ( 99 % ) ; -; Total pins ; 70 / 80 ( 88 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------+---------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Device ; EPM240T100C5 ; ; -; Maximum processors allowed for parallel compilation ; 4 ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Always Enable Input Buffers ; Off ; Off ; -; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; -; Optimize Multi-Corner Timing ; Off ; Off ; -; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ; -; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; Normal ; Normal ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; Periphery to Core Placement and Routing Optimization ; Off ; Off ; -; Slow Slew Rate ; Off ; Off ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Delay Chains ; On ; On ; -; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; -; Auto Register Duplication ; Auto ; Auto ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.03 ; -; Maximum used ; 4 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; 1.2% ; -; Processors 3-4 ; 1.0% ; -+----------------------------+-------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.pin. - - -+---------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+-----------------------+ -; Resource ; Usage ; -+---------------------------------------------+-----------------------+ -; Total logic elements ; 238 / 240 ( 99 % ) ; -; -- Combinational with no register ; 112 ; -; -- Register only ; 19 ; -; -- Combinational with a register ; 107 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 116 ; -; -- 3 input functions ; 53 ; -; -- 2 input functions ; 46 ; -; -- 1 input functions ; 3 ; -; -- 0 input functions ; 1 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 224 ; -; -- arithmetic mode ; 14 ; -; -- qfbk mode ; 14 ; -; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 26 ; -; -- asynchronous clear/load mode ; 0 ; -; ; ; -; Total registers ; 126 / 240 ( 53 % ) ; -; Total LABs ; 24 / 24 ( 100 % ) ; -; Logic elements in carry chains ; 15 ; -; Virtual pins ; 0 ; -; I/O pins ; 70 / 80 ( 88 % ) ; -; -- Clock pins ; 3 / 4 ( 75 % ) ; -; ; ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -; ; ; -; -- Total Fixed Point DSP Blocks ; 0 ; -; -- Total Floating Point DSP Blocks ; 0 ; -; ; ; -; Global signals ; 2 ; -; -- Global clocks ; 2 / 4 ( 50 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 29.9% / 32.0% / 27.7% ; -; Peak interconnect usage (total/H/V) ; 29.9% / 32.0% / 27.7% ; -; Maximum fan-out ; 122 ; -; Highest non-global fan-out ; 34 ; -; Total fan-out ; 992 ; -; Average fan-out ; 3.21 ; -+---------------------------------------------+-----------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ; -+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ -; Ain[0] ; 56 ; 2 ; 8 ; 1 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[1] ; 54 ; 2 ; 8 ; 1 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[2] ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 122 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 15 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; -+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; CKEout ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; yes ; User ; 10 pF ; - ; - ; -; RAout[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RAout[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RAout[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RAout[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nRWEout ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Bidir Pins ; -+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; -+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; RD[0] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[2] ; 99 ; 2 ; 2 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[4] ; 91 ; 2 ; 4 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[5] ; 92 ; 2 ; 3 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[7] ; 96 ; 2 ; 3 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ - - -+-------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+-------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+-------------------+---------------+--------------+ -; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ; -; 2 ; 32 / 42 ( 76 % ) ; 3.3V ; -- ; -+----------+-------------------+---------------+--------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ -; 1 ; 83 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 2 ; 0 ; 1 ; nRWEout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 3 ; 1 ; 1 ; nCASout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 4 ; 2 ; 1 ; CKEout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 5 ; 3 ; 1 ; nRASout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 6 ; 4 ; 1 ; BA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 7 ; 5 ; 1 ; RAout[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 8 ; 6 ; 1 ; nCSout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 12 ; 7 ; 1 ; C14M ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 14 ; 8 ; 1 ; BA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 15 ; 9 ; 1 ; RAout[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 16 ; 10 ; 1 ; RAout[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 17 ; 11 ; 1 ; RAout[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 18 ; 12 ; 1 ; RAout[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 19 ; 13 ; 1 ; RAout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 20 ; 14 ; 1 ; RAout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 21 ; 15 ; 1 ; RAout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 26 ; 20 ; 1 ; RAout[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 27 ; 21 ; 1 ; RAout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 28 ; 22 ; 1 ; nEN80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 29 ; 23 ; 1 ; RAout[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 30 ; 24 ; 1 ; RAout[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 33 ; 25 ; 1 ; nWE80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 34 ; 26 ; 1 ; Ain[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 35 ; 27 ; 1 ; Din[7] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 36 ; 28 ; 1 ; Din[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 37 ; 29 ; 1 ; PHI1 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 38 ; 30 ; 1 ; Din[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 39 ; 31 ; 1 ; Ain[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 40 ; 32 ; 1 ; Din[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 41 ; 33 ; 1 ; Din[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 42 ; 34 ; 1 ; Din[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 43 ; 35 ; 1 ; Ain[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 44 ; 36 ; 1 ; Ain[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 62 ; 50 ; 2 ; Vout[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ; -; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 67 ; 53 ; 2 ; Vout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 68 ; 54 ; 2 ; Vout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 69 ; 55 ; 2 ; Vout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 70 ; 56 ; 2 ; Vout[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 71 ; 57 ; 2 ; Vout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 72 ; 58 ; 2 ; Dout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 73 ; 59 ; 2 ; Dout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 74 ; 60 ; 2 ; Dout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 75 ; 61 ; 2 ; Dout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 76 ; 62 ; 2 ; Dout[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 77 ; 63 ; 2 ; Dout[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 84 ; 68 ; 2 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 85 ; 69 ; 2 ; Dout[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 88 ; 72 ; 2 ; LED ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 91 ; 75 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 92 ; 76 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 96 ; 78 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 97 ; 79 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 98 ; 80 ; 2 ; DQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 99 ; 81 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 100 ; 82 ; 2 ; DQMH ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -+----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+-------------------------------------------------------------+ -; Output Pin Default Load For Reported TCO ; -+----------------------------+-------+------------------------+ -; I/O Standard ; Load ; Termination Resistance ; -+----------------------------+-------+------------------------+ -; 3.3-V LVTTL ; 10 pF ; Not Available ; -; 3.3-V LVCMOS ; 10 pF ; Not Available ; -; 2.5 V ; 10 pF ; Not Available ; -; 1.8 V ; 10 pF ; Not Available ; -; 1.5 V ; 10 pF ; Not Available ; -; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ; -; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ; -+----------------------------+-------+------------------------+ -Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -; |RAM2E ; 238 (182) ; 126 ; 1 ; 70 ; 0 ; 112 (88) ; 19 (16) ; 107 (78) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ; -; |RAM2E_UFM:ram2e_ufm| ; 56 (56) ; 32 ; 1 ; 0 ; 0 ; 24 (24) ; 3 (3) ; 29 (29) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ; -; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ; -; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+--------------------------------------+ -; Delay Chain Summary ; -+-----------+----------+---------------+ -; Name ; Pin Type ; Pad to Core 0 ; -+-----------+----------+---------------+ -; LED ; Output ; -- ; -; nWE80 ; Input ; (0) ; -; Dout[0] ; Output ; -- ; -; Dout[1] ; Output ; -- ; -; Dout[2] ; Output ; -- ; -; Dout[3] ; Output ; -- ; -; Dout[4] ; Output ; -- ; -; Dout[5] ; Output ; -- ; -; Dout[6] ; Output ; -- ; -; Dout[7] ; Output ; -- ; -; nDOE ; Output ; -- ; -; Vout[0] ; Output ; -- ; -; Vout[1] ; Output ; -- ; -; Vout[2] ; Output ; -- ; -; Vout[3] ; Output ; -- ; -; Vout[4] ; Output ; -- ; -; Vout[5] ; Output ; -- ; -; Vout[6] ; Output ; -- ; -; Vout[7] ; Output ; -- ; -; nVOE ; Output ; -- ; -; CKEout ; Output ; -- ; -; nCSout ; Output ; -- ; -; nRASout ; Output ; -- ; -; nCASout ; Output ; -- ; -; nRWEout ; Output ; -- ; -; BA[0] ; Output ; -- ; -; BA[1] ; Output ; -- ; -; RAout[0] ; Output ; -- ; -; RAout[1] ; Output ; -- ; -; RAout[2] ; Output ; -- ; -; RAout[3] ; Output ; -- ; -; RAout[4] ; Output ; -- ; -; RAout[5] ; Output ; -- ; -; RAout[6] ; Output ; -- ; -; RAout[7] ; Output ; -- ; -; RAout[8] ; Output ; -- ; -; RAout[9] ; Output ; -- ; -; RAout[10] ; Output ; -- ; -; RAout[11] ; Output ; -- ; -; DQML ; Output ; -- ; -; DQMH ; Output ; -- ; -; RD[0] ; Bidir ; (0) ; -; RD[1] ; Bidir ; (0) ; -; RD[2] ; Bidir ; (0) ; -; RD[3] ; Bidir ; (0) ; -; RD[4] ; Bidir ; (0) ; -; RD[5] ; Bidir ; (0) ; -; RD[6] ; Bidir ; (0) ; -; RD[7] ; Bidir ; (0) ; -; nEN80 ; Input ; (0) ; -; nWE ; Input ; (0) ; -; Ain[0] ; Input ; (0) ; -; Ain[1] ; Input ; (0) ; -; Ain[2] ; Input ; (0) ; -; Ain[3] ; Input ; (0) ; -; Ain[4] ; Input ; (0) ; -; Ain[5] ; Input ; (0) ; -; Ain[6] ; Input ; (0) ; -; Ain[7] ; Input ; (0) ; -; C14M ; Input ; (0) ; -; Din[0] ; Input ; (0) ; -; Din[6] ; Input ; (0) ; -; PHI1 ; Input ; (1) ; -; Din[1] ; Input ; (0) ; -; Din[5] ; Input ; (0) ; -; Din[7] ; Input ; (0) ; -; Din[4] ; Input ; (0) ; -; Din[2] ; Input ; (0) ; -; Din[3] ; Input ; (0) ; -; nC07X ; Input ; (0) ; -+-----------+----------+---------------+ - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; -+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+ -; BA[0]~0 ; LC_X2_Y3_N8 ; 2 ; Clock enable ; no ; -- ; -- ; -; BA[0]~1 ; LC_X4_Y3_N9 ; 3 ; Clock enable ; no ; -- ; -- ; -; C14M ; PIN_12 ; 122 ; Clock ; yes ; Global Clock ; GCLK0 ; -; CS[0]~2 ; LC_X4_Y2_N7 ; 3 ; Clock enable ; no ; -- ; -- ; -; DQML~0 ; LC_X2_Y4_N7 ; 2 ; Clock enable ; no ; -- ; -- ; -; Equal1~1 ; LC_X4_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ; -; Equal1~2 ; LC_X6_Y3_N7 ; 8 ; Clock enable ; no ; -- ; -- ; -; Mux14~0 ; LC_X2_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ; -; PHI1 ; PIN_37 ; 5 ; Clock ; yes ; Global Clock ; GCLK3 ; -; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X6_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ; -; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X3_Y1_N0 ; 8 ; Clock enable ; no ; -- ; -- ; -; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X4_Y2_N0 ; 16 ; Clock enable ; no ; -- ; -- ; -; RA[1]~2 ; LC_X2_Y3_N1 ; 6 ; Clock enable ; no ; -- ; -- ; -; RDOE ; LC_X5_Y4_N7 ; 8 ; Output enable ; no ; -- ; -- ; -; S[0] ; LC_X6_Y4_N8 ; 32 ; Sync. clear ; no ; -- ; -- ; -; S[3] ; LC_X6_Y4_N1 ; 34 ; Sync. clear ; no ; -- ; -- ; -+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+ - - -+---------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+------+----------+---------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; -+------+----------+---------+----------------------+------------------+ -; C14M ; PIN_12 ; 122 ; Global Clock ; GCLK0 ; -; PHI1 ; PIN_37 ; 5 ; Global Clock ; GCLK3 ; -+------+----------+---------+----------------------+------------------+ - - -+--------------------------------------------+ -; Routing Usage Summary ; -+-----------------------+--------------------+ -; Routing Resource Type ; Usage ; -+-----------------------+--------------------+ -; C4s ; 173 / 784 ( 22 % ) ; -; Direct links ; 43 / 888 ( 5 % ) ; -; Global clocks ; 2 / 4 ( 50 % ) ; -; LAB clocks ; 7 / 32 ( 22 % ) ; -; LUT chains ; 7 / 216 ( 3 % ) ; -; Local interconnects ; 340 / 888 ( 38 % ) ; -; R4s ; 174 / 704 ( 25 % ) ; -+-----------------------+--------------------+ - - -+---------------------------------------------------------------------------+ -; LAB Logic Elements ; -+--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 9.92) ; Number of LABs (Total = 24) ; -+--------------------------------------------+------------------------------+ -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 23 ; -+--------------------------------------------+------------------------------+ - - -+-------------------------------------------------------------------+ -; LAB-wide Signals ; -+------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.50) ; Number of LABs (Total = 24) ; -+------------------------------------+------------------------------+ -; 1 Clock ; 22 ; -; 1 Clock enable ; 9 ; -; 1 Sync. clear ; 2 ; -; 2 Clock enables ; 3 ; -+------------------------------------+------------------------------+ - - -+-----------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+----------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 10.13) ; Number of LABs (Total = 24) ; -+----------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 22 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 1 ; -+----------------------------------------------+------------------------------+ - - -+--------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 7.08) ; Number of LABs (Total = 24) ; -+-------------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 2 ; -; 4 ; 1 ; -; 5 ; 3 ; -; 6 ; 3 ; -; 7 ; 4 ; -; 8 ; 5 ; -; 9 ; 3 ; -; 10 ; 2 ; -; 11 ; 0 ; -; 12 ; 1 ; -+-------------------------------------------------+------------------------------+ - - -+-----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 12.50) ; Number of LABs (Total = 24) ; -+----------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 1 ; -; 3 ; 0 ; -; 4 ; 2 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 2 ; -; 10 ; 1 ; -; 11 ; 4 ; -; 12 ; 3 ; -; 13 ; 1 ; -; 14 ; 2 ; -; 15 ; 0 ; -; 16 ; 2 ; -; 17 ; 0 ; -; 18 ; 1 ; -; 19 ; 1 ; -; 20 ; 0 ; -; 21 ; 2 ; -; 22 ; 1 ; -+----------------------------------------------+------------------------------+ - - -+-------------------------------------------------------------------------+ -; Fitter Device Options ; -+----------------------------------------------+--------------------------+ -; Option ; Setting ; -+----------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Passive Serial ; -; Reserve all unused pins ; As output driving ground ; -+----------------------------------------------+--------------------------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (119006): Selected device EPM240T100C5 for design "RAM2E" -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. -Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info (176445): Device EPM240T100I5 is compatible - Info (176445): Device EPM240T100A5 is compatible - Info (176445): Device EPM570T100C5 is compatible - Info (176445): Device EPM570T100I5 is compatible - Info (176445): Device EPM570T100A5 is compatible -Info (332104): Reading SDC File: '../RAM2E.sdc' -Info (332104): Reading SDC File: '../RAM2E-MAX.sdc' -Warning (332060): Node: PHI1 was determined to be a clock but was found without an associated clock assignment. - Info (13166): Register RefReq is being clocked by PHI1 -Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements -Info (332111): Found 3 clocks - Info (332111): Period Clock Name - Info (332111): ======== ============ - Info (332111): 69.841 C14M - Info (332111): 200.000 ram2e_ufm|ARCLK|regout - Info (332111): 200.000 ram2e_ufm|DRCLK|regout -Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 -Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 - Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 20 - Info (186217): Destination "S~0" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 19 -Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 -Info (186079): Completed Auto Global Promotion Operation -Info (176234): Starting register packing -Info (186468): Started processing fast register assignments -Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes - Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 -Info (186469): Finished processing fast register assignments -Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 -Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. -Info (170189): Fitter placement preparation operations beginning -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01 -Info (170191): Fitter placement operations beginning -Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 -Info (170193): Fitter routing operations beginning -Info (170089): 5e+01 ns of routing delay (approximately 3.3% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. -Info (170195): Router estimated average interconnect usage is 26% of the available device resources - Info (170196): Router estimated peak interconnect usage is 26% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 -Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization. -Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.97 seconds. -Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 -Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg -Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings - Info: Peak virtual memory: 13770 megabytes - Info: Processing ended: Thu Feb 15 04:16:23 2024 - Info: Elapsed time: 00:00:08 - Info: Total CPU time (on all processors): 00:00:04 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.fit.smsg. - - diff --git a/CPLD/MAXII/output_files/RAM2E.fit.smsg b/CPLD/MAXII/output_files/RAM2E.fit.smsg deleted file mode 100644 index a3cd98a..0000000 --- a/CPLD/MAXII/output_files/RAM2E.fit.smsg +++ /dev/null @@ -1,4 +0,0 @@ -Extra Info (176273): Performing register packing on registers with non-logic cell location assignments -Extra Info (176274): Completed register packing on registers with non-logic cell location assignments -Extra Info (176244): Moving registers into LUTs to improve timing and density -Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00 diff --git a/CPLD/MAXII/output_files/RAM2E.fit.summary b/CPLD/MAXII/output_files/RAM2E.fit.summary deleted file mode 100644 index c933a9a..0000000 --- a/CPLD/MAXII/output_files/RAM2E.fit.summary +++ /dev/null @@ -1,11 +0,0 @@ -Fitter Status : Successful - Thu Feb 15 04:16:23 2024 -Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition -Revision Name : RAM2E -Top-level Entity Name : RAM2E -Family : MAX II -Device : EPM240T100C5 -Timing Models : Final -Total logic elements : 238 / 240 ( 99 % ) -Total pins : 70 / 80 ( 88 % ) -Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM2E.flow.rpt b/CPLD/MAXII/output_files/RAM2E.flow.rpt deleted file mode 100644 index 44e71e3..0000000 --- a/CPLD/MAXII/output_files/RAM2E.flow.rpt +++ /dev/null @@ -1,118 +0,0 @@ -Flow report for RAM2E -Thu Feb 15 04:16:31 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - 8. Flow Messages - 9. Flow Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2019 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+---------------------------------------------------------------------+ -; Flow Summary ; -+-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Thu Feb 15 04:16:27 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX II ; -; Device ; EPM240T100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 238 / 240 ( 99 % ) ; -; Total pins ; 70 / 80 ( 88 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------+---------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 02/15/2024 04:15:27 ; -; Main task ; Compilation ; -; Revision Name ; RAM2E ; -+-------------------+---------------------+ - - -+-----------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+---------------------------------------+------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+---------------------------------------+------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 121380219419.170798852707820 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; -; POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR ; 3.3V ; -- ; -- ; -- ; -; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -+---------------------------------------+------------------------------+---------------+-------------+------------+ - - -+--------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:47 ; 1.0 ; 13146 MB ; 00:00:47 ; -; Fitter ; 00:00:08 ; 1.0 ; 13770 MB ; 00:00:04 ; -; Assembler ; 00:00:02 ; 1.0 ; 13099 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:02 ; 1.0 ; 13089 MB ; 00:00:02 ; -; Total ; 00:00:59 ; -- ; -- ; 00:00:54 ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+----------------------+------------------+------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+----------------------+------------------+------------+------------+----------------+ -; Analysis & Synthesis ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; -; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; -; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; -; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; -+----------------------+------------------+------------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E -quartus_fit --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E -quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXII -c RAM2E -quartus_sta RAM2E-MAXII -c RAM2E - - - diff --git a/CPLD/MAXII/output_files/RAM2E.jdi b/CPLD/MAXII/output_files/RAM2E.jdi deleted file mode 100644 index eb86129..0000000 --- a/CPLD/MAXII/output_files/RAM2E.jdi +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/CPLD/MAXII/output_files/RAM2E.map.rpt b/CPLD/MAXII/output_files/RAM2E.map.rpt deleted file mode 100644 index 850260b..0000000 --- a/CPLD/MAXII/output_files/RAM2E.map.rpt +++ /dev/null @@ -1,330 +0,0 @@ -Analysis & Synthesis report for RAM2E -Thu Feb 15 04:16:13 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Parallel Compilation - 5. Analysis & Synthesis Source Files Read - 6. Analysis & Synthesis Resource Usage Summary - 7. Analysis & Synthesis Resource Utilization by Entity - 8. Analysis & Synthesis IP Cores Summary - 9. General Register Statistics - 10. Inverted Register Statistics - 11. Multiplexer Restructuring Statistics (Restructuring Performed) - 12. Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" - 13. Analysis & Synthesis Messages - 14. Analysis & Synthesis Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2019 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+---------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Thu Feb 15 04:16:13 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX II ; -; Total logic elements ; 252 ; -; Total pins ; 70 ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------------+---------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+------------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+------------------------------------------------------------------+--------------------+--------------------+ -; Device ; EPM240T100C5 ; ; -; Top-level entity name ; RAM2E ; RAM2E ; -; Family name ; MAX II ; Cyclone V ; -; Maximum processors allowed for parallel compilation ; 4 ; ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL_1993 ; VHDL_1993 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Infer RAMs from Raw Logic ; On ; On ; -; Parallel Synthesis ; On ; On ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Report Parameter Settings ; On ; On ; -; Report Source Assignments ; On ; On ; -; Report Connectivity Checks ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Block Design Naming ; Auto ; Auto ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -; Disable Register Merging Across Hierarchies ; Auto ; Auto ; -+------------------------------------------------------------------+--------------------+--------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -+----------------------------+-------------+ - - -+-------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+ -; ../RAM2E.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v ; ; -; ../UFM-MAX.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v ; ; -; UFM.v ; yes ; User Wizard-Generated File ; //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v ; ; -; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.mif ; ; -+----------------------------------+-----------------+----------------------------------+-----------------------------------------+---------+ - - -+-----------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+-------+ -; Resource ; Usage ; -+---------------------------------------------+-------+ -; Total logic elements ; 252 ; -; -- Combinational with no register ; 126 ; -; -- Register only ; 33 ; -; -- Combinational with a register ; 93 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 116 ; -; -- 3 input functions ; 53 ; -; -- 2 input functions ; 46 ; -; -- 1 input functions ; 3 ; -; -- 0 input functions ; 1 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 238 ; -; -- arithmetic mode ; 14 ; -; -- qfbk mode ; 0 ; -; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 3 ; -; -- asynchronous clear/load mode ; 0 ; -; ; ; -; Total registers ; 126 ; -; Total logic cells in carry chains ; 15 ; -; I/O pins ; 70 ; -; UFM blocks ; 1 ; -; Maximum fan-out node ; C14M ; -; Maximum fan-out ; 122 ; -; Total fan-out ; 1001 ; -; Average fan-out ; 3.10 ; -+---------------------------------------------+-------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -; |RAM2E ; 252 (191) ; 126 ; 1 ; 70 ; 0 ; 126 (97) ; 33 (25) ; 93 (69) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ; -; |RAM2E_UFM:ram2e_ufm| ; 61 (61) ; 32 ; 1 ; 0 ; 0 ; 29 (29) ; 8 (8) ; 24 (24) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ; -; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ; -; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis IP Cores Summary ; -+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+ -; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; -+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+ -; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1 ; N/A ; N/A ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM.v ; -+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+ - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 126 ; -; Number of registers using Synchronous Clear ; 3 ; -; Number of registers using Synchronous Load ; 0 ; -; Number of registers using Asynchronous Clear ; 0 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 59 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+---------------------------------------------------+ -; Inverted Register Statistics ; -+-----------------------------------------+---------+ -; Inverted Register ; Fan out ; -+-----------------------------------------+---------+ -; CKEout~reg0 ; 1 ; -; nRASout~reg0 ; 1 ; -; nCASout~reg0 ; 1 ; -; nRWEout~reg0 ; 1 ; -; DQML~reg0 ; 1 ; -; DQMH~reg0 ; 1 ; -; CKE ; 1 ; -; nRAS ; 1 ; -; nCAS ; 1 ; -; nRWE ; 1 ; -; Total number of inverted registers = 10 ; ; -+-----------------------------------------+---------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Restructuring Statistics (Restructuring Performed) ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ -; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ -; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ; -; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[1] ; -; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[5] ; -; 16:1 ; 2 bits ; 20 LEs ; 2 LEs ; 18 LEs ; Yes ; |RAM2E|BA[0]~reg0 ; -; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[6] ; -; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[1] ; -; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |RAM2E|DQML~reg0 ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" ; -+--------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------+--------+----------+-------------------------------------------------------------------------------------+ -; ardin ; Input ; Info ; Stuck at GND ; -; oscena ; Input ; Info ; Stuck at VCC ; -; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------+--------+----------+-------------------------------------------------------------------------------------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus Prime Analysis & Synthesis - Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Thu Feb 15 04:15:26 2024 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E -Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v - Info (12023): Found entity 1: RAM2E File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ufm-max.v - Info (12023): Found entity 1: RAM2E_UFM File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1 -Info (12021): Found 2 design units, including 2 entities, in source file ufm.v - Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47 - Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166 -Info (12127): Elaborating entity "RAM2E" for the top level hierarchy -Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 136 -Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 77 -Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217 -Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 75 -Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (21074): Design contains 1 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "nWE80" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 11 -Info (21057): Implemented 323 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 22 input pins - Info (21059): Implemented 40 output pins - Info (21060): Implemented 8 bidirectional pins - Info (21061): Implemented 252 logic cells - Info (21070): Implemented 1 User Flash Memory blocks -Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg -Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings - Info: Peak virtual memory: 13146 megabytes - Info: Processing ended: Thu Feb 15 04:16:13 2024 - Info: Elapsed time: 00:00:47 - Info: Total CPU time (on all processors): 00:00:47 - - -+------------------------------------------+ -; Analysis & Synthesis Suppressed Messages ; -+------------------------------------------+ -The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg. - - diff --git a/CPLD/MAXII/output_files/RAM2E.map.smsg b/CPLD/MAXII/output_files/RAM2E.map.smsg deleted file mode 100644 index c004b75..0000000 --- a/CPLD/MAXII/output_files/RAM2E.map.smsg +++ /dev/null @@ -1,3 +0,0 @@ -Warning (10273): Verilog HDL warning at RAM2E.v(72): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 72 -Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73 -Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189 diff --git a/CPLD/MAXII/output_files/RAM2E.map.summary b/CPLD/MAXII/output_files/RAM2E.map.summary deleted file mode 100644 index 18d0796..0000000 --- a/CPLD/MAXII/output_files/RAM2E.map.summary +++ /dev/null @@ -1,9 +0,0 @@ -Analysis & Synthesis Status : Successful - Thu Feb 15 04:16:13 2024 -Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition -Revision Name : RAM2E -Top-level Entity Name : RAM2E -Family : MAX II -Total logic elements : 252 -Total pins : 70 -Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM2E.pin b/CPLD/MAXII/output_files/RAM2E.pin deleted file mode 100644 index 10edbd1..0000000 --- a/CPLD/MAXII/output_files/RAM2E.pin +++ /dev/null @@ -1,165 +0,0 @@ - -- Copyright (C) 2019 Intel Corporation. All rights reserved. - -- Your use of Intel Corporation's design tools, logic functions - -- and other software and tools, and any partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Intel Program License - -- Subscription Agreement, the Intel Quartus Prime License Agreement, - -- the Intel FPGA IP License Agreement, or other applicable license - -- agreement, including, without limitation, that your use is for - -- the sole purpose of programming logic devices manufactured by - -- Intel and sold by Intel or its authorized distributors. Please - -- refer to the applicable agreement for further details, at - -- https://fpgasoftware.intel.com/eula. - -- - -- This is a Quartus Prime output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus Prime input file. This file cannot be used - -- to make Quartus Prime pin assignments - for instructions on how to make pin - -- assignments, please see Quartus Prime help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition -CHIP "RAM2E" ASSIGNED TO AN: EPM240T100C5 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -GND* : 1 : : : : 2 : -nRWEout : 2 : output : 3.3-V LVCMOS : : 1 : Y -nCASout : 3 : output : 3.3-V LVCMOS : : 1 : Y -CKEout : 4 : output : 3.3-V LVCMOS : : 1 : Y -nRASout : 5 : output : 3.3-V LVCMOS : : 1 : Y -BA[0] : 6 : output : 3.3-V LVCMOS : : 1 : Y -RAout[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y -nCSout : 8 : output : 3.3-V LVCMOS : : 1 : Y -VCCIO1 : 9 : power : : 3.3V : 1 : -GNDIO : 10 : gnd : : : : -GNDINT : 11 : gnd : : : : -C14M : 12 : input : 3.3-V LVCMOS : : 1 : Y -VCCINT : 13 : power : : 2.5V/3.3V : : -BA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y -RAout[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y -RAout[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y -RAout[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y -RAout[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y -RAout[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y -RAout[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y -RAout[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y -TMS : 22 : input : : : 1 : -TDI : 23 : input : : : 1 : -TCK : 24 : input : : : 1 : -TDO : 25 : output : : : 1 : -RAout[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y -RAout[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y -nEN80 : 28 : input : 3.3-V LVCMOS : : 1 : Y -RAout[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y -RAout[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y -VCCIO1 : 31 : power : : 3.3V : 1 : -GNDIO : 32 : gnd : : : : -nWE80 : 33 : input : 3.3-V LVCMOS : : 1 : Y -Ain[5] : 34 : input : 3.3-V LVCMOS : : 1 : Y -Din[7] : 35 : input : 3.3-V LVCMOS : : 1 : Y -Din[6] : 36 : input : 3.3-V LVCMOS : : 1 : Y -PHI1 : 37 : input : 3.3-V LVCMOS : : 1 : Y -Din[0] : 38 : input : 3.3-V LVCMOS : : 1 : Y -Ain[6] : 39 : input : 3.3-V LVCMOS : : 1 : Y -Din[1] : 40 : input : 3.3-V LVCMOS : : 1 : Y -Din[3] : 41 : input : 3.3-V LVCMOS : : 1 : Y -Din[2] : 42 : input : 3.3-V LVCMOS : : 1 : Y -Ain[2] : 43 : input : 3.3-V LVCMOS : : 1 : Y -Ain[4] : 44 : input : 3.3-V LVCMOS : : 1 : Y -VCCIO1 : 45 : power : : 3.3V : 1 : -GNDIO : 46 : gnd : : : : -Ain[3] : 47 : input : 3.3-V LVCMOS : : 1 : Y -Din[4] : 48 : input : 3.3-V LVCMOS : : 1 : Y -Din[5] : 49 : input : 3.3-V LVCMOS : : 1 : Y -nVOE : 50 : output : 3.3-V LVCMOS : : 1 : Y -nWE : 51 : input : 3.3-V LVCMOS : : 1 : Y -nC07X : 52 : input : 3.3-V LVCMOS : : 2 : Y -Ain[7] : 53 : input : 3.3-V LVCMOS : : 2 : Y -Ain[1] : 54 : input : 3.3-V LVCMOS : : 2 : Y -nDOE : 55 : output : 3.3-V LVCMOS : : 2 : Y -Ain[0] : 56 : input : 3.3-V LVCMOS : : 2 : Y -Vout[7] : 57 : output : 3.3-V LVCMOS : : 2 : Y -Vout[6] : 58 : output : 3.3-V LVCMOS : : 2 : Y -VCCIO2 : 59 : power : : 3.3V : 2 : -GNDIO : 60 : gnd : : : : -GND* : 61 : : : : 2 : -Vout[3] : 62 : output : 3.3-V LVCMOS : : 2 : Y -VCCINT : 63 : power : : 2.5V/3.3V : : -GND* : 64 : : : : 2 : -GNDINT : 65 : gnd : : : : -GND* : 66 : : : : 2 : -Vout[1] : 67 : output : 3.3-V LVCMOS : : 2 : Y -Vout[5] : 68 : output : 3.3-V LVCMOS : : 2 : Y -Vout[2] : 69 : output : 3.3-V LVCMOS : : 2 : Y -Vout[0] : 70 : output : 3.3-V LVCMOS : : 2 : Y -Vout[4] : 71 : output : 3.3-V LVCMOS : : 2 : Y -Dout[5] : 72 : output : 3.3-V LVCMOS : : 2 : Y -Dout[4] : 73 : output : 3.3-V LVCMOS : : 2 : Y -Dout[2] : 74 : output : 3.3-V LVCMOS : : 2 : Y -Dout[3] : 75 : output : 3.3-V LVCMOS : : 2 : Y -Dout[1] : 76 : output : 3.3-V LVCMOS : : 2 : Y -Dout[0] : 77 : output : 3.3-V LVCMOS : : 2 : Y -GND* : 78 : : : : 2 : -GNDIO : 79 : gnd : : : : -VCCIO2 : 80 : power : : 3.3V : 2 : -GND* : 81 : : : : 2 : -GND* : 82 : : : : 2 : -GND* : 83 : : : : 2 : -Dout[6] : 84 : output : 3.3-V LVCMOS : : 2 : Y -Dout[7] : 85 : output : 3.3-V LVCMOS : : 2 : Y -GND* : 86 : : : : 2 : -GND* : 87 : : : : 2 : -LED : 88 : output : 3.3-V LVTTL : : 2 : Y -RD[3] : 89 : bidir : 3.3-V LVCMOS : : 2 : Y -RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y -RD[4] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y -RD[5] : 92 : bidir : 3.3-V LVCMOS : : 2 : Y -GNDIO : 93 : gnd : : : : -VCCIO2 : 94 : power : : 3.3V : 2 : -RD[6] : 95 : bidir : 3.3-V LVCMOS : : 2 : Y -RD[7] : 96 : bidir : 3.3-V LVCMOS : : 2 : Y -RD[0] : 97 : bidir : 3.3-V LVCMOS : : 2 : Y -DQML : 98 : output : 3.3-V LVCMOS : : 2 : Y -RD[2] : 99 : bidir : 3.3-V LVCMOS : : 2 : Y -DQMH : 100 : output : 3.3-V LVCMOS : : 2 : Y diff --git a/CPLD/MAXII/output_files/RAM2E.pof b/CPLD/MAXII/output_files/RAM2E.pof deleted file mode 100644 index c81c57385ffb1fa577ee63fd9f79b3bd7bf364c0..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 7861 zcmeHMZ*Y{yc|U;@_Hz|JzaM^T>$dQ-wX3&oY2Jj- z*3Da=YHr@NwRY{MtgOMqrzLEyC`t}Z<6~W^z+QtdgL&jCe464n^f8`- z4hsC!_62$xKKwUwB=F5x(%<)z3KQ5R4LuH=%Y5CtQD%e*jB#WO@SFt#(WW$lQjFEGk zCsM%AbT_ZWXuZbe^Rc2?-Q_v?EbD!$GamydtqFPvFDUNd-Om*MYd zIR6)hzH&xyL)+nBRh5rFb$Jfx_3zyHduu zv{wiIVd=g@54EH(q&MzOUra6U_{A@K(u1==7=2atnrRA7(xPYIC!q5t-Nc|)R zEj}l=;1SQ6_)?s~&q;lfq|?I#d~zA$M?u`BG=9tw;^;>$J&&w+$rBFh9dT!t?wb7O zHokfA8hOAa&6vr5$K+8mDaquIVnz<)ZRjL=l%#0foFCKqkNgycXfr-DngPcXnL!Dh zAb%B4`I?i=#fVa;d{f7;mlc&qU4j3M+!1|@l+cv$mGq-s-eAcdBCtWO(L=$mLMCU< zKP^e&d@<`LuWfzVeM1ZhLVB|!RZmaAXV;B=rmD=j!3Ef*@?bY;jZ<_E{g~*?oAab& zm{eoHpF?(IA8X8J52SaA1NmZPu_lLNBa?~!;7u~YKzAS(^~Zv`Zlwa|@f6l#VK|Qj z^amZIL&v=B{&rF+epd!`=pW?4$&-n-VcvC8${x) z59mXAdu}q&MQOj5QN>I9nLeh4VEKhP;T~d6u6W5kbTmiGGYHV1qo|4a?lWgw?}_S$ z8fuuQn==LHXOYJP`GeY=7ct-G8TIl=9)Z*P=#E(Y1lD1AxayDDf91E8i~pF__F47( zs`2~(*&QAAS7j)13iQT?%5UngeQUg2eEgLPef|9UU1hhry|2Gjb3@AVtDSm*esuL8 zsuum{%WcsGi)!R8viz~3cfZh&uH9e0v~TV!(QnOblx5?Y8P|PLbKmSq z>koGSxpXArzyIEgFE=&a%aUW&?e14^KV0)+dw@^wOKo@D@kVpY!jtKAYH`QG6Fuqb zTh?^$xdm~7{ioq4Y5XSqIOd8b9gW<`dDG{&^;07SPDdP;>Jj9hNZ9opDo#^|oA{t| z5#Qycd9!kSY3Zf7@lIr^#_{QxzGLMD`DGRmQplak;~r7K*{j6#Jwc#v%e?P1-5T^o z&$ZIm`aS`}8Li%yku{i`sVnXp) zI0YV)9T*IruLaTG10$#lDmp~Mp2vK0iq3VbLwWw&*ay1E`_*8#>o-#kUl-7KGO4>Y z-#rSxPm;e0Q*vGAz{khbue(e2hddB68XNdRu0R_mt8`=6Dd^V`-chg1?|kkXm3{ijl~t>MBFaJ)uUDzY8-8H< z75{mqe(>Q9j}5&$w@oYyHI7$5(bn@Y)i|nBkF4+!j2;_VAeh7I~5SQNspS>sGep#YRRY3Nt2?)LH(J{2i{loBs z?e|81;NUFE0b6T*B(KnhtzF1hJ9;^c;KwcV^~CY6EEw=H{%_RXVwPw z--3O4>Yv=@6`qNS-NWnE@r3qOYK7(ByR)n=yZHJ0-tT|+<7{~0jaB2dvnyu&>1b8W zJnNqe4WYX1lJWcU{k;Pf;f0~{a|h>E%m}?zQ+A`RpX9f9{cYj!{cow>J}))UxICa%O3^_Y8z z82kV-nZj4y$6Wr8aTwuRBS1ex~cHur{>5)WIvau(b&0jBL>BO*a5b_fR5`=y! zwCDQ@T$UeL7@5I$)#D!e14E@5eF8exZ5<=$(El{@wvh6G0|v`a{%O$hd}`)i0r`h< zGpWH6J-`PZ81c{!w!$m;H2)3%CUj!tw~xm&4%MWRyg|p{$Hz|E`pHwo#Em7H?`7g# zIHu0YlQG25@}CfnZs2H;d7~$X-ZJh#ts%$qqn;hxpCiK4lbrJ0a|=)7d{fP({uB0H zKkVZg%QF$reInP>Qv|ot!r~(iObf^P{1hQWNTW{OE)TbP9@sZQOZ_5jQA-CC$H(+P zz& z2Gs76c`H+0u2iqBv-y8;=c2_YWW}ac9h0*vs%QV*&BeACj^7u${CQa@@jKw>+3lZZ z^K;AJ>3{FY+6A*K!)HDB(CpCY%}<4_{+%ak@6ZixukQG9@7x*t{!#x#m4%LnzA~z+ z@3j7zXqeIaDYZ?;e%vdX_FX@DL2YSzCG^$N>QKn)uc*K813dpZ&cAp~8*h!aPqeoW zFJ6r2zp47`>wD#gY4^jvIqwgrQ_DII?rTr?y#2k-<;$)73FtUHhWH|53plGx)OCdU zA0mN_e-Nj@&)pa$JCIj7ZqG+lj)`wTcf^Du{+l$(MxwFbp@Aj`g{5D@9*YBh*F&L9 zqW%Cif%g$+9rbxdPLcOqBH42phjkLjSIdWVDi=n+(Z6V(2d8i(iU4X& zp#B2>*fdU@`+Pz%uL#wY$LTD10{wjn96lwlh~f>_r|{9wB$Q^TFA{zRCz2UU_NxMm z`7!iocg!dBw{ysI^zp0fGlRKDEgl1%^AevummpUaDeA>e13zZUmW5s5Prw64pJPSz zccUjWcpP#e=k$7tokl%i{Ult1{-%=%iYxJ6MVNERM?VA}{`MA$qwjjhJe-fi#attC zhQwuRl3V_;*$0hqJrS9RNm1Q4)uI=Vf@0^P3Zdl!3EGxU?yJe#_8$vn-I-DQRJ{s!X)W-*! zHq74VOwz=yAsVl_sn$Lp$1-e2b|Ccp*D8BKU+`0Bvh4ND^K(brL$xLS`_6q3X*%z` z=L|G8t$4O$tfM_Ww%BtzO7*AQzE?gypZ*)Sa_>Wr;Qhp_;U1_)OkPhU z!DHyAzD!>+_sJr7!pO@Ex|q5`_lmy9au$z2?Z^c3((~&j_6PXB7E0~F_p?2w|M{$l zyHpZ_OY(VXWINGAjXoOK7^mn|6jCOkTZ$XH=M@C#kXOQwmiS>G3BzaBv45H$ezADP z0RO6WGI-|Pw{+xvX(V`W8egCuwV6-JDakF(r|uEc`|bMG@~_=*aDLaSnZ8EfX&hi(ZO0XTzFhym=$8ed%Il_o5vn!62qA!9{`=Ac RUwYvGsRw4;--@3c_#a4zaCra# diff --git a/CPLD/MAXII/output_files/RAM2E.sld b/CPLD/MAXII/output_files/RAM2E.sld deleted file mode 100644 index 41a6030..0000000 --- a/CPLD/MAXII/output_files/RAM2E.sld +++ /dev/null @@ -1 +0,0 @@ - diff --git a/CPLD/MAXII/output_files/RAM2E.sta.rpt b/CPLD/MAXII/output_files/RAM2E.sta.rpt deleted file mode 100644 index d12f129..0000000 --- a/CPLD/MAXII/output_files/RAM2E.sta.rpt +++ /dev/null @@ -1,729 +0,0 @@ -Timing Analyzer report for RAM2E -Thu Feb 15 04:16:31 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Timing Analyzer Summary - 3. Parallel Compilation - 4. SDC File List - 5. Clocks - 6. Fmax Summary - 7. Setup Summary - 8. Hold Summary - 9. Recovery Summary - 10. Removal Summary - 11. Minimum Pulse Width Summary - 12. Setup: 'ram2e_ufm|ARCLK|regout' - 13. Setup: 'ram2e_ufm|DRCLK|regout' - 14. Setup: 'C14M' - 15. Hold: 'ram2e_ufm|DRCLK|regout' - 16. Hold: 'ram2e_ufm|ARCLK|regout' - 17. Hold: 'C14M' - 18. Setup Transfers - 19. Hold Transfers - 20. Report TCCS - 21. Report RSKM - 22. Unconstrained Paths Summary - 23. Clock Status Summary - 24. Unconstrained Input Ports - 25. Unconstrained Output Ports - 26. Unconstrained Input Ports - 27. Unconstrained Output Ports - 28. Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2019 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+-----------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+-----------------------+-----------------------------------------------------+ -; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; -; Timing Analyzer ; Legacy Timing Analyzer ; -; Revision Name ; RAM2E ; -; Device Family ; MAX II ; -; Device Name ; EPM240T100C5 ; -; Timing Models ; Final ; -; Delay Model ; Slow Model ; -; Rise/Fall Delays ; Unavailable ; -+-----------------------+-----------------------------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 2 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; -+----------------------------+-------------+ - - -+------------------------------------------------------+ -; SDC File List ; -+------------------+--------+--------------------------+ -; SDC File Path ; Status ; Read at ; -+------------------+--------+--------------------------+ -; ../RAM2E.sdc ; OK ; Thu Feb 15 04:16:31 2024 ; -; ../RAM2E-MAX.sdc ; OK ; Thu Feb 15 04:16:31 2024 ; -+------------------+--------+--------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+ -; C14M ; Base ; 69.841 ; 14.32 MHz ; 0.000 ; 34.920 ; ; ; ; ; ; ; ; ; ; ; { C14M } ; -; ram2e_ufm|ARCLK|regout ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ram2e_ufm|ARCLK|regout } ; -; ram2e_ufm|DRCLK|regout ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ram2e_ufm|DRCLK|regout } ; -+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+ - - -+-------------------------------------------------------------+ -; Fmax Summary ; -+-----------+-----------------+------------------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+-----------+-----------------+------------------------+------+ -; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|ARCLK|regout ; ; -; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|DRCLK|regout ; ; -; 68.17 MHz ; 68.17 MHz ; C14M ; ; -+-----------+-----------------+------------------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - -+--------------------------------------------------+ -; Setup Summary ; -+------------------------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+------------------------+---------+---------------+ -; ram2e_ufm|ARCLK|regout ; -23.723 ; -23.723 ; -; ram2e_ufm|DRCLK|regout ; -23.713 ; -23.713 ; -; C14M ; -10.120 ; -109.885 ; -+------------------------+---------+---------------+ - - -+--------------------------------------------------+ -; Hold Summary ; -+------------------------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+------------------------+---------+---------------+ -; ram2e_ufm|DRCLK|regout ; -16.306 ; -16.306 ; -; ram2e_ufm|ARCLK|regout ; -16.276 ; -16.276 ; -; C14M ; 1.415 ; 0.000 ; -+------------------------+---------+---------------+ - - --------------------- -; Recovery Summary ; --------------------- -No paths to report. - - -------------------- -; Removal Summary ; -------------------- -No paths to report. - - -+-------------------------------------------------+ -; Minimum Pulse Width Summary ; -+------------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+------------------------+--------+---------------+ -; C14M ; 34.654 ; 0.000 ; -; ram2e_ufm|ARCLK|regout ; 70.000 ; 0.000 ; -; ram2e_ufm|DRCLK|regout ; 70.000 ; 0.000 ; -+------------------------+--------+---------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'ram2e_ufm|ARCLK|regout' ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; -23.723 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -2.195 ; 1.529 ; -; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000 ; 0.000 ; 80.000 ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'ram2e_ufm|DRCLK|regout' ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; -23.713 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.165 ; 1.549 ; -; -23.693 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.165 ; 1.529 ; -; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'C14M' ; -+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+ -; -10.120 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.953 ; -; -10.120 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.953 ; -; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ; -; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ; -; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ; -; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ; -; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ; -; -9.711 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 11.544 ; -; -9.027 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 10.860 ; -; -7.930 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.763 ; -; -7.925 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 9.758 ; -; -6.497 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.165 ; 8.330 ; -; 27.586 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.001 ; -; 27.586 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.001 ; -; 27.729 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.858 ; -; 27.729 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.858 ; -; 27.800 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.787 ; -; 27.800 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.787 ; -; 28.220 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.367 ; -; 28.220 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.367 ; -; 28.226 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.361 ; -; 28.226 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.361 ; -; 28.226 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.361 ; -; 28.369 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.218 ; -; 28.369 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.218 ; -; 28.369 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.218 ; -; 28.440 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.147 ; -; 28.440 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.147 ; -; 28.440 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.147 ; -; 28.860 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.727 ; -; 28.860 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.727 ; -; 28.860 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.727 ; -; 28.910 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.677 ; -; 28.910 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.677 ; -; 28.910 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.677 ; -; 29.053 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.534 ; -; 29.053 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.534 ; -; 29.053 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.534 ; -; 29.124 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.463 ; -; 29.124 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.463 ; -; 29.124 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.463 ; -; 29.544 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.043 ; -; 29.544 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.043 ; -; 29.544 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.043 ; -; 29.726 ; S[1] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.861 ; -; 30.004 ; S[3] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.583 ; -; 30.351 ; S[2] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 4.236 ; -; 30.681 ; S[0] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 3.906 ; -; 31.064 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.523 ; -; 31.134 ; RA[10] ; RAr[10] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.453 ; -; 31.373 ; RA[9] ; RAr[9] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.214 ; -; 31.459 ; RA[8] ; RAr[8] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.128 ; -; 31.701 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.886 ; -; 31.732 ; S[3] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 2.855 ; -; 31.854 ; RA[11] ; RAr[11] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.733 ; -; 31.909 ; S[2] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 2.678 ; -; 31.932 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.655 ; -; 31.945 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 2.642 ; -; 32.013 ; S[0] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 2.574 ; -; 32.533 ; RA[3] ; RAr[3] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.054 ; -; 32.562 ; RA[6] ; RAr[6] ; C14M ; C14M ; 34.920 ; 0.000 ; 2.025 ; -; 32.597 ; S[1] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 1.990 ; -; 32.955 ; RA[0] ; RAr[0] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.632 ; -; 32.974 ; RA[4] ; RAr[4] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.613 ; -; 32.977 ; RA[7] ; RAr[7] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.610 ; -; 32.979 ; RA[5] ; RAr[5] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.608 ; -; 32.980 ; RA[1] ; RAr[1] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.607 ; -; 32.981 ; RA[2] ; RAr[2] ; C14M ; C14M ; 34.920 ; 0.000 ; 1.606 ; -; 55.823 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.685 ; -; 55.823 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.685 ; -; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ; -; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ; -; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ; -; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ; -; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ; -; 56.232 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.276 ; -; 56.355 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 13.153 ; -; 56.360 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 13.148 ; -; 56.403 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.105 ; -; 56.403 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 13.105 ; -; 56.476 ; FS[15] ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 13.032 ; -; 56.481 ; FS[15] ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 69.841 ; 0.000 ; 13.027 ; -; 56.524 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.984 ; -; 56.524 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.984 ; -; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ; -; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ; -; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ; -; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ; -; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ; -; 56.812 ; FS[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.696 ; -; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ; -; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ; -; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ; -; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ; -; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ; -; 56.866 ; FS[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.642 ; -; 56.916 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 69.841 ; 0.000 ; 12.592 ; -; 56.933 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.575 ; -; 56.933 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.575 ; -; 56.933 ; FS[15] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.575 ; -+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'ram2e_ufm|DRCLK|regout' ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; -16.306 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.165 ; 1.529 ; -; -16.286 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.165 ; 1.549 ; -; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'ram2e_ufm|ARCLK|regout' ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; -16.276 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -2.195 ; 1.529 ; -; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000 ; 0.000 ; 80.000 ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'C14M' ; -+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ -; 1.415 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.636 ; -; 1.644 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.865 ; -; 1.650 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.871 ; -; 1.665 ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.886 ; -; 1.684 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 1.905 ; -; 1.701 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.922 ; -; 1.715 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.936 ; -; 1.914 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.135 ; -; 1.916 ; RWBank[2] ; RA[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.137 ; -; 1.968 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.189 ; -; 1.971 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.192 ; -; 1.973 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.194 ; -; 1.973 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.194 ; -; 1.979 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.200 ; -; 2.026 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.247 ; -; 2.107 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ; -; 2.107 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ; -; 2.125 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.346 ; -; 2.127 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.348 ; -; 2.134 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.355 ; -; 2.144 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.365 ; -; 2.151 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.372 ; -; 2.153 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.374 ; -; 2.170 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.391 ; -; 2.174 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.395 ; -; 2.175 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.396 ; -; 2.189 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.410 ; -; 2.190 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.411 ; -; 2.207 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.428 ; -; 2.214 ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.435 ; -; 2.222 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.443 ; -; 2.222 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 2.443 ; -; 2.228 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.449 ; -; 2.233 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.454 ; -; 2.239 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ; -; 2.239 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ; -; 2.240 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ; -; 2.240 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.461 ; -; 2.248 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.469 ; -; 2.249 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.470 ; -; 2.250 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.471 ; -; 2.255 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.476 ; -; 2.259 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.480 ; -; 2.262 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.483 ; -; 2.271 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.492 ; -; 2.273 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.494 ; -; 2.286 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 2.507 ; -; 2.345 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.566 ; -; 2.346 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.567 ; -; 2.362 ; S[1] ; RDOE ; C14M ; C14M ; 0.000 ; 0.000 ; 2.583 ; -; 2.417 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.638 ; -; 2.455 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.676 ; -; 2.486 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.707 ; -; 2.528 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.749 ; -; 2.544 ; RWSel ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 2.765 ; -; 2.551 ; PHI1r ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.772 ; -; 2.552 ; PHI1r ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.773 ; -; 2.553 ; PHI1r ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.774 ; -; 2.555 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.776 ; -; 2.621 ; RAM2E_UFM:ram2e_ufm|UFMErase ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.842 ; -; 2.633 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.854 ; -; 2.722 ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.943 ; -; 2.838 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 3.059 ; -; 2.839 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.060 ; -; 2.842 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.063 ; -; 2.843 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.064 ; -; 2.855 ; RWBank[6] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.076 ; -; 2.860 ; RWBank[5] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.081 ; -; 2.921 ; RAM2E_UFM:ram2e_ufm|UFMErase ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.142 ; -; 2.938 ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.159 ; -; 2.957 ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.178 ; -; 2.966 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.187 ; -; 2.976 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.197 ; -; 2.983 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.204 ; -; 2.985 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.206 ; -; 2.994 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.215 ; -; 3.005 ; S[1] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.226 ; -; 3.014 ; S[1] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.235 ; -; 3.015 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.236 ; -; 3.016 ; S[1] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.237 ; -; 3.077 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.298 ; -; 3.087 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.308 ; -; 3.094 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.315 ; -; 3.096 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.317 ; -; 3.096 ; FS[11] ; RA[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.317 ; -; 3.128 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.349 ; -; 3.129 ; S[3] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.350 ; -; 3.132 ; FS[0] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.353 ; -; 3.134 ; S[3] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.355 ; -; 3.155 ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.376 ; -; 3.172 ; RWBank[0] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.393 ; -; 3.173 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.394 ; -; 3.174 ; RWBank[0] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.395 ; -; 3.179 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ; -; 3.179 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ; -; 3.180 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.401 ; -; 3.188 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ; -; 3.188 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ; -; 3.202 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.423 ; -; 3.205 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.426 ; -+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------+ -; Setup Transfers ; -+------------------------+------------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------------------+------------------------+----------+----------+----------+----------+ -; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ; -; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ; -; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ; -; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ; -; C14M ; ram2e_ufm|DRCLK|regout ; 2 ; 0 ; 0 ; 0 ; -; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1 ; 0 ; 0 ; 0 ; -+------------------------+------------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+---------------------------------------------------------------------------------------------+ -; Hold Transfers ; -+------------------------+------------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------------------+------------------------+----------+----------+----------+----------+ -; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ; -; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ; -; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ; -; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ; -; C14M ; ram2e_ufm|DRCLK|regout ; 2 ; 0 ; 0 ; 0 ; -; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1 ; 0 ; 0 ; 0 ; -+------------------------+------------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - ---------------- -; Report TCCS ; ---------------- -No dedicated SERDES Transmitter circuitry present in device or used in design - - ---------------- -; Report RSKM ; ---------------- -No non-DPA dedicated SERDES Receiver circuitry present in device or used in design - - -+------------------------------------------------+ -; Unconstrained Paths Summary ; -+---------------------------------+-------+------+ -; Property ; Setup ; Hold ; -+---------------------------------+-------+------+ -; Illegal Clocks ; 0 ; 0 ; -; Unconstrained Clocks ; 1 ; 1 ; -; Unconstrained Input Ports ; 28 ; 28 ; -; Unconstrained Input Port Paths ; 169 ; 169 ; -; Unconstrained Output Ports ; 47 ; 47 ; -; Unconstrained Output Port Paths ; 83 ; 83 ; -+---------------------------------+-------+------+ - - -+------------------------------------------------------------------------+ -; Clock Status Summary ; -+------------------------+------------------------+------+---------------+ -; Target ; Clock ; Type ; Status ; -+------------------------+------------------------+------+---------------+ -; C14M ; C14M ; Base ; Constrained ; -; PHI1 ; ; Base ; Unconstrained ; -; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; Base ; Constrained ; -; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; Base ; Constrained ; -+------------------------+------------------------+------+---------------+ - - -+---------------------------------------------------------------------------------------------------+ -; Unconstrained Input Ports ; -+------------+--------------------------------------------------------------------------------------+ -; Input Port ; Comment ; -+------------+--------------------------------------------------------------------------------------+ -; Ain[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; PHI1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -+------------+--------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------+ -; Unconstrained Output Ports ; -+-------------+---------------------------------------------------------------------------------------+ -; Output Port ; Comment ; -+-------------+---------------------------------------------------------------------------------------+ -; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; CKEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nCASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nRASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nRWEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -+-------------+---------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------+ -; Unconstrained Input Ports ; -+------------+--------------------------------------------------------------------------------------+ -; Input Port ; Comment ; -+------------+--------------------------------------------------------------------------------------+ -; Ain[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; PHI1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -+------------+--------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------+ -; Unconstrained Output Ports ; -+-------------+---------------------------------------------------------------------------------------+ -; Output Port ; Comment ; -+-------------+---------------------------------------------------------------------------------------+ -; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; CKEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nCASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nRASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nRWEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -+-------------+---------------------------------------------------------------------------------------+ - - -+--------------------------+ -; Timing Analyzer Messages ; -+--------------------------+ -Info: ******************************************************************* -Info: Running Quartus Prime Timing Analyzer - Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Thu Feb 15 04:16:29 2024 -Info: Command: quartus_sta RAM2E-MAXII -c RAM2E -Info: qsta_default_script.tcl version: #1 -Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Info (332104): Reading SDC File: '../RAM2E.sdc' -Info (332104): Reading SDC File: '../RAM2E-MAX.sdc' -Warning (332060): Node: PHI1 was determined to be a clock but was found without an associated clock assignment. - Info (13166): Register RefReq is being clocked by PHI1 -Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. -Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. -Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. -Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -23.723 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): -23.723 -23.723 ram2e_ufm|ARCLK|regout - Info (332119): -23.713 -23.713 ram2e_ufm|DRCLK|regout - Info (332119): -10.120 -109.885 C14M -Info (332146): Worst-case hold slack is -16.306 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): -16.306 -16.306 ram2e_ufm|DRCLK|regout - Info (332119): -16.276 -16.276 ram2e_ufm|ARCLK|regout - Info (332119): 1.415 0.000 C14M -Info (332140): No Recovery paths to report -Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is 34.654 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 34.654 0.000 C14M - Info (332119): 70.000 0.000 ram2e_ufm|ARCLK|regout - Info (332119): 70.000 0.000 ram2e_ufm|DRCLK|regout -Info (332001): The selected device family is not supported by the report_metastability command. -Info (332102): Design is not fully constrained for setup requirements -Info (332102): Design is not fully constrained for hold requirements -Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 13089 megabytes - Info: Processing ended: Thu Feb 15 04:16:31 2024 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:02 - - diff --git a/CPLD/MAXII/output_files/RAM2E.sta.summary b/CPLD/MAXII/output_files/RAM2E.sta.summary deleted file mode 100644 index e20e85a..0000000 --- a/CPLD/MAXII/output_files/RAM2E.sta.summary +++ /dev/null @@ -1,41 +0,0 @@ ------------------------------------------------------------- -Timing Analyzer Summary ------------------------------------------------------------- - -Type : Setup 'ram2e_ufm|ARCLK|regout' -Slack : -23.723 -TNS : -23.723 - -Type : Setup 'ram2e_ufm|DRCLK|regout' -Slack : -23.713 -TNS : -23.713 - -Type : Setup 'C14M' -Slack : -10.120 -TNS : -109.885 - -Type : Hold 'ram2e_ufm|DRCLK|regout' -Slack : -16.306 -TNS : -16.306 - -Type : Hold 'ram2e_ufm|ARCLK|regout' -Slack : -16.276 -TNS : -16.276 - -Type : Hold 'C14M' -Slack : 1.415 -TNS : 0.000 - -Type : Minimum Pulse Width 'C14M' -Slack : 34.654 -TNS : 0.000 - -Type : Minimum Pulse Width 'ram2e_ufm|ARCLK|regout' -Slack : 70.000 -TNS : 0.000 - -Type : Minimum Pulse Width 'ram2e_ufm|DRCLK|regout' -Slack : 70.000 -TNS : 0.000 - ------------------------------------------------------------- diff --git a/CPLD/MAXV/output_files/RAM2E.asm.rpt b/CPLD/MAXV/output_files/RAM2E.asm.rpt deleted file mode 100644 index c432024..0000000 --- a/CPLD/MAXV/output_files/RAM2E.asm.rpt +++ /dev/null @@ -1,91 +0,0 @@ -Assembler report for RAM2E -Thu Feb 15 04:16:27 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof - 6. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2019 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Feb 15 04:16:27 2024 ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX V ; -; Device ; 5M240ZT100C5 ; -+-----------------------+---------------------------------------+ - - -+----------------------------------+ -; Assembler Settings ; -+--------+---------+---------------+ -; Option ; Setting ; Default Value ; -+--------+---------+---------------+ - - -+-----------------------------------------------+ -; Assembler Generated Files ; -+-----------------------------------------------+ -; File Name ; -+-----------------------------------------------+ -; /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ; -+-----------------------------------------------+ - - -+-------------------------------------------------------------------------+ -; Assembler Device Options: /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pof ; -+----------------+--------------------------------------------------------+ -; Option ; Setting ; -+----------------+--------------------------------------------------------+ -; JTAG usercode ; 0x001651A7 ; -; Checksum ; 0x001654A7 ; -+----------------+--------------------------------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus Prime Assembler - Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Thu Feb 15 04:16:25 2024 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E -Info (115031): Writing out detailed assembly data for power analysis -Info (115030): Assembler is generating device programming files -Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 13095 megabytes - Info: Processing ended: Thu Feb 15 04:16:27 2024 - Info: Elapsed time: 00:00:02 - Info: Total CPU time (on all processors): 00:00:01 - - diff --git a/CPLD/MAXV/output_files/RAM2E.done b/CPLD/MAXV/output_files/RAM2E.done deleted file mode 100644 index 92f137e..0000000 --- a/CPLD/MAXV/output_files/RAM2E.done +++ /dev/null @@ -1 +0,0 @@ -Thu Feb 15 04:16:33 2024 diff --git a/CPLD/MAXV/output_files/RAM2E.fit.rpt b/CPLD/MAXV/output_files/RAM2E.fit.rpt deleted file mode 100644 index 4c2311a..0000000 --- a/CPLD/MAXV/output_files/RAM2E.fit.rpt +++ /dev/null @@ -1,768 +0,0 @@ -Fitter report for RAM2E -Thu Feb 15 04:16:23 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Fitter Summary - 3. Fitter Settings - 4. Parallel Compilation - 5. Pin-Out File - 6. Fitter Resource Usage Summary - 7. Input Pins - 8. Output Pins - 9. Bidir Pins - 10. I/O Bank Usage - 11. All Package Pins - 12. Output Pin Default Load For Reported TCO - 13. Fitter Resource Utilization by Entity - 14. Delay Chain Summary - 15. Control Signals - 16. Global & Other Fast Signals - 17. Routing Usage Summary - 18. LAB Logic Elements - 19. LAB-wide Signals - 20. LAB Signals Sourced - 21. LAB Signals Sourced Out - 22. LAB Distinct Inputs - 23. Fitter Device Options - 24. Fitter Messages - 25. Fitter Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2019 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+---------------------------------------------------------------------+ -; Fitter Summary ; -+-----------------------+---------------------------------------------+ -; Fitter Status ; Successful - Thu Feb 15 04:16:23 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX V ; -; Device ; 5M240ZT100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 238 / 240 ( 99 % ) ; -; Total pins ; 70 / 79 ( 89 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------+---------------------------------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Settings ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ -; Device ; 5M240ZT100C5 ; ; -; Maximum processors allowed for parallel compilation ; 4 ; ; -; Minimum Core Junction Temperature ; 0 ; ; -; Maximum Core Junction Temperature ; 85 ; ; -; Fit Attempts to Skip ; 0 ; 0.0 ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Router Timing Optimization Level ; Normal ; Normal ; -; Placement Effort Multiplier ; 1.0 ; 1.0 ; -; Router Effort Multiplier ; 1.0 ; 1.0 ; -; Always Enable Input Buffers ; Off ; Off ; -; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; -; Optimize Multi-Corner Timing ; Off ; Off ; -; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ; -; Power Optimization During Fitting ; Normal compilation ; Normal compilation ; -; Optimize Timing ; Normal compilation ; Normal compilation ; -; Optimize Timing for ECOs ; Off ; Off ; -; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ; -; Optimize IOC Register Placement for Timing ; Normal ; Normal ; -; Limit to One Fitting Attempt ; Off ; Off ; -; Final Placement Optimizations ; Automatically ; Automatically ; -; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; -; Fitter Initial Placement Seed ; 1 ; 1 ; -; Periphery to Core Placement and Routing Optimization ; Off ; Off ; -; Slow Slew Rate ; Off ; Off ; -; PCI I/O ; Off ; Off ; -; Weak Pull-Up Resistor ; Off ; Off ; -; Enable Bus-Hold Circuitry ; Off ; Off ; -; Auto Delay Chains ; On ; On ; -; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; -; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; -; Perform Register Duplication for Performance ; Off ; Off ; -; Perform Register Retiming for Performance ; Off ; Off ; -; Perform Asynchronous Signal Pipelining ; Off ; Off ; -; Fitter Effort ; Auto Fit ; Auto Fit ; -; Physical Synthesis Effort Level ; Normal ; Normal ; -; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; -; Auto Register Duplication ; Auto ; Auto ; -; Auto Global Clock ; On ; On ; -; Auto Global Register Control Signals ; On ; On ; -; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; -+--------------------------------------------------------------------+--------------------------------+--------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.03 ; -; Maximum used ; 4 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; 1.1% ; -; Processors 3-4 ; 0.9% ; -+----------------------------+-------------+ - - -+--------------+ -; Pin-Out File ; -+--------------+ -The pin-out file can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.pin. - - -+---------------------------------------------------------------------+ -; Fitter Resource Usage Summary ; -+---------------------------------------------+-----------------------+ -; Resource ; Usage ; -+---------------------------------------------+-----------------------+ -; Total logic elements ; 238 / 240 ( 99 % ) ; -; -- Combinational with no register ; 112 ; -; -- Register only ; 19 ; -; -- Combinational with a register ; 107 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 116 ; -; -- 3 input functions ; 53 ; -; -- 2 input functions ; 46 ; -; -- 1 input functions ; 3 ; -; -- 0 input functions ; 1 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 224 ; -; -- arithmetic mode ; 14 ; -; -- qfbk mode ; 14 ; -; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 24 ; -; -- asynchronous clear/load mode ; 0 ; -; ; ; -; Total registers ; 126 / 240 ( 53 % ) ; -; Total LABs ; 24 / 24 ( 100 % ) ; -; Logic elements in carry chains ; 15 ; -; Virtual pins ; 0 ; -; I/O pins ; 70 / 79 ( 89 % ) ; -; -- Clock pins ; 3 / 4 ( 75 % ) ; -; ; ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -; ; ; -; -- Total Fixed Point DSP Blocks ; 0 ; -; -- Total Floating Point DSP Blocks ; 0 ; -; ; ; -; Global signals ; 2 ; -; -- Global clocks ; 2 / 4 ( 50 % ) ; -; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 26.9% / 26.8% / 27.1% ; -; Peak interconnect usage (total/H/V) ; 26.9% / 26.8% / 27.1% ; -; Maximum fan-out ; 122 ; -; Highest non-global fan-out ; 34 ; -; Total fan-out ; 992 ; -; Average fan-out ; 3.21 ; -+---------------------------------------------+-----------------------+ - - -+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Input Pins ; -+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; Slow Slew Rate ; -+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ -; Ain[0] ; 56 ; 2 ; 8 ; 1 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[1] ; 54 ; 2 ; 8 ; 1 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[2] ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 122 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 15 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 13 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; Din[7] ; 35 ; 1 ; 3 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; PHI1 ; 37 ; 1 ; 4 ; 0 ; 1 ; 5 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; nC07X ; 52 ; 2 ; 8 ; 1 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; nEN80 ; 28 ; 1 ; 2 ; 0 ; 1 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; nWE ; 51 ; 1 ; 7 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -; nWE80 ; 33 ; 1 ; 3 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; no ; -+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+----------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Output Pins ; -+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; -+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; CKEout ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[3] ; 75 ; 2 ; 7 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[4] ; 73 ; 2 ; 8 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; LED ; 88 ; 2 ; 5 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 16mA ; no ; User ; 10 pF ; - ; - ; -; RAout[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RAout[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RAout[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; RAout[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RAout[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; nCASout ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nCSout ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; nRASout ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; nRWEout ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -+-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Bidir Pins ; -+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; -+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ -; RD[0] ; 97 ; 2 ; 3 ; 5 ; 3 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[1] ; 90 ; 2 ; 4 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[2] ; 99 ; 2 ; 2 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[3] ; 89 ; 2 ; 4 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[4] ; 91 ; 2 ; 4 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[5] ; 92 ; 2 ; 3 ; 5 ; 0 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[6] ; 95 ; 2 ; 3 ; 5 ; 1 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -; RD[7] ; 96 ; 2 ; 3 ; 5 ; 2 ; 2 ; 0 ; no ; no ; yes ; no ; no ; yes ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; RDOE ; - ; -+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ - - -+-------------------------------------------------------------+ -; I/O Bank Usage ; -+----------+-------------------+---------------+--------------+ -; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; -+----------+-------------------+---------------+--------------+ -; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ; -; 2 ; 32 / 41 ( 78 % ) ; 3.3V ; -- ; -+----------+-------------------+---------------+--------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------+ -; All Package Pins ; -+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; -+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -; 1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 2 ; 0 ; 1 ; nRWEout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 3 ; 1 ; 1 ; nCASout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 4 ; 2 ; 1 ; CKEout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 5 ; 3 ; 1 ; nRASout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 6 ; 4 ; 1 ; BA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 7 ; 5 ; 1 ; RAout[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 8 ; 6 ; 1 ; nCSout ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 12 ; 7 ; 1 ; C14M ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 13 ; ; ; VCCINT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -; 14 ; 8 ; 1 ; BA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 15 ; 9 ; 1 ; RAout[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 16 ; 10 ; 1 ; RAout[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 17 ; 11 ; 1 ; RAout[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 18 ; 12 ; 1 ; RAout[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 19 ; 13 ; 1 ; RAout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 20 ; 14 ; 1 ; RAout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 21 ; 15 ; 1 ; RAout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; -; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; -; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; -; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; -; 26 ; 20 ; 1 ; RAout[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 27 ; 21 ; 1 ; RAout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 28 ; 22 ; 1 ; nEN80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 29 ; 23 ; 1 ; RAout[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 30 ; 24 ; 1 ; RAout[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 33 ; 25 ; 1 ; nWE80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 34 ; 26 ; 1 ; Ain[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 35 ; 27 ; 1 ; Din[7] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 36 ; 28 ; 1 ; Din[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 37 ; 29 ; 1 ; PHI1 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 38 ; 30 ; 1 ; Din[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 39 ; 31 ; 1 ; Ain[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 40 ; 32 ; 1 ; Din[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 41 ; 33 ; 1 ; Din[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 42 ; 34 ; 1 ; Din[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 43 ; 35 ; 1 ; Ain[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 44 ; 36 ; 1 ; Ain[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 46 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 60 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 62 ; 50 ; 2 ; Vout[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 63 ; ; ; VCCINT ; power ; ; 1.8V ; -- ; ; -- ; -- ; -; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; -; 67 ; 53 ; 2 ; Vout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 68 ; 54 ; 2 ; Vout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 69 ; 55 ; 2 ; Vout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 70 ; 56 ; 2 ; Vout[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 71 ; 57 ; 2 ; Vout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 72 ; 58 ; 2 ; Dout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 73 ; 59 ; 2 ; Dout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 74 ; 60 ; 2 ; Dout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ; -; 75 ; 61 ; 2 ; Dout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 76 ; 62 ; 2 ; Dout[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 77 ; 63 ; 2 ; Dout[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 84 ; 68 ; 2 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 85 ; 69 ; 2 ; Dout[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; -; 88 ; 72 ; 2 ; LED ; output ; 3.3-V LVTTL ; ; Column I/O ; Y ; no ; Off ; -; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 91 ; 75 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 92 ; 76 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; -; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; -; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 96 ; 78 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 97 ; 79 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 98 ; 80 ; 2 ; DQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -; 99 ; 81 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ; -; 100 ; 82 ; 2 ; DQMH ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ; -+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ -Note: Pin directions (input, output or bidir) are based on device operating in user mode. - - -+-------------------------------------------------------------+ -; Output Pin Default Load For Reported TCO ; -+----------------------------+-------+------------------------+ -; I/O Standard ; Load ; Termination Resistance ; -+----------------------------+-------+------------------------+ -; 3.3-V LVTTL ; 10 pF ; Not Available ; -; 3.3-V LVCMOS ; 10 pF ; Not Available ; -; 2.5 V ; 10 pF ; Not Available ; -; 1.8 V ; 10 pF ; Not Available ; -; 1.5 V ; 10 pF ; Not Available ; -; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ; -; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ; -; 1.2 V ; 10 pF ; Not Available ; -; LVDS_E_3R ; 10 pF ; Not Available ; -; RSDS_E_3R ; 10 pF ; Not Available ; -+----------------------------+-------+------------------------+ -Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Fitter Resource Utilization by Entity ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -; |RAM2E ; 238 (182) ; 126 ; 1 ; 70 ; 0 ; 112 (88) ; 19 (16) ; 107 (78) ; 15 (15) ; 14 (9) ; |RAM2E ; RAM2E ; work ; -; |RAM2E_UFM:ram2e_ufm| ; 56 (56) ; 32 ; 1 ; 0 ; 0 ; 24 (24) ; 3 (3) ; 29 (29) ; 0 (0) ; 5 (5) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ; -; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ; -; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+--------------------------------------+ -; Delay Chain Summary ; -+-----------+----------+---------------+ -; Name ; Pin Type ; Pad to Core 0 ; -+-----------+----------+---------------+ -; LED ; Output ; -- ; -; nWE80 ; Input ; (0) ; -; Dout[0] ; Output ; -- ; -; Dout[1] ; Output ; -- ; -; Dout[2] ; Output ; -- ; -; Dout[3] ; Output ; -- ; -; Dout[4] ; Output ; -- ; -; Dout[5] ; Output ; -- ; -; Dout[6] ; Output ; -- ; -; Dout[7] ; Output ; -- ; -; nDOE ; Output ; -- ; -; Vout[0] ; Output ; -- ; -; Vout[1] ; Output ; -- ; -; Vout[2] ; Output ; -- ; -; Vout[3] ; Output ; -- ; -; Vout[4] ; Output ; -- ; -; Vout[5] ; Output ; -- ; -; Vout[6] ; Output ; -- ; -; Vout[7] ; Output ; -- ; -; nVOE ; Output ; -- ; -; CKEout ; Output ; -- ; -; nCSout ; Output ; -- ; -; nRASout ; Output ; -- ; -; nCASout ; Output ; -- ; -; nRWEout ; Output ; -- ; -; BA[0] ; Output ; -- ; -; BA[1] ; Output ; -- ; -; RAout[0] ; Output ; -- ; -; RAout[1] ; Output ; -- ; -; RAout[2] ; Output ; -- ; -; RAout[3] ; Output ; -- ; -; RAout[4] ; Output ; -- ; -; RAout[5] ; Output ; -- ; -; RAout[6] ; Output ; -- ; -; RAout[7] ; Output ; -- ; -; RAout[8] ; Output ; -- ; -; RAout[9] ; Output ; -- ; -; RAout[10] ; Output ; -- ; -; RAout[11] ; Output ; -- ; -; DQML ; Output ; -- ; -; DQMH ; Output ; -- ; -; RD[0] ; Bidir ; (0) ; -; RD[1] ; Bidir ; (0) ; -; RD[2] ; Bidir ; (0) ; -; RD[3] ; Bidir ; (0) ; -; RD[4] ; Bidir ; (0) ; -; RD[5] ; Bidir ; (0) ; -; RD[6] ; Bidir ; (0) ; -; RD[7] ; Bidir ; (0) ; -; nEN80 ; Input ; (0) ; -; nWE ; Input ; (0) ; -; Ain[0] ; Input ; (0) ; -; Ain[1] ; Input ; (0) ; -; Ain[2] ; Input ; (0) ; -; Ain[3] ; Input ; (0) ; -; Ain[4] ; Input ; (0) ; -; Ain[5] ; Input ; (0) ; -; Ain[6] ; Input ; (0) ; -; Ain[7] ; Input ; (0) ; -; C14M ; Input ; (0) ; -; Din[0] ; Input ; (0) ; -; Din[6] ; Input ; (0) ; -; PHI1 ; Input ; (1) ; -; Din[1] ; Input ; (0) ; -; Din[5] ; Input ; (0) ; -; Din[7] ; Input ; (0) ; -; Din[4] ; Input ; (0) ; -; Din[2] ; Input ; (0) ; -; Din[3] ; Input ; (0) ; -; nC07X ; Input ; (0) ; -+-----------+----------+---------------+ - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Control Signals ; -+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; -+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+ -; BA[0]~0 ; LC_X2_Y3_N5 ; 2 ; Clock enable ; no ; -- ; -- ; -; BA[0]~1 ; LC_X5_Y2_N3 ; 3 ; Clock enable ; no ; -- ; -- ; -; C14M ; PIN_12 ; 122 ; Clock ; yes ; Global Clock ; GCLK0 ; -; CS[0]~2 ; LC_X3_Y1_N8 ; 3 ; Clock enable ; no ; -- ; -- ; -; DQML~0 ; LC_X2_Y4_N5 ; 2 ; Clock enable ; no ; -- ; -- ; -; Equal1~1 ; LC_X2_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ; -; Equal1~2 ; LC_X7_Y4_N7 ; 8 ; Clock enable ; no ; -- ; -- ; -; Mux14~0 ; LC_X2_Y3_N8 ; 2 ; Clock enable ; no ; -- ; -- ; -; PHI1 ; PIN_37 ; 5 ; Clock ; yes ; Global Clock ; GCLK3 ; -; RAM2E_UFM:ram2e_ufm|RWMask~1 ; LC_X7_Y1_N7 ; 8 ; Clock enable ; no ; -- ; -- ; -; RAM2E_UFM:ram2e_ufm|UFMD[15]~1 ; LC_X3_Y1_N3 ; 8 ; Clock enable ; no ; -- ; -- ; -; RAM2E_UFM:ram2e_ufm|always2~8 ; LC_X4_Y2_N1 ; 16 ; Clock enable ; no ; -- ; -- ; -; RA[1]~2 ; LC_X2_Y3_N9 ; 6 ; Clock enable ; no ; -- ; -- ; -; RDOE ; LC_X3_Y3_N4 ; 8 ; Output enable ; no ; -- ; -- ; -; S[0] ; LC_X3_Y3_N3 ; 32 ; Sync. clear ; no ; -- ; -- ; -; S[3] ; LC_X3_Y3_N6 ; 34 ; Sync. clear ; no ; -- ; -- ; -+--------------------------------+-------------+---------+---------------+--------+----------------------+------------------+ - - -+---------------------------------------------------------------------+ -; Global & Other Fast Signals ; -+------+----------+---------+----------------------+------------------+ -; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; -+------+----------+---------+----------------------+------------------+ -; C14M ; PIN_12 ; 122 ; Global Clock ; GCLK0 ; -; PHI1 ; PIN_37 ; 5 ; Global Clock ; GCLK3 ; -+------+----------+---------+----------------------+------------------+ - - -+--------------------------------------------+ -; Routing Usage Summary ; -+-----------------------+--------------------+ -; Routing Resource Type ; Usage ; -+-----------------------+--------------------+ -; C4s ; 163 / 784 ( 21 % ) ; -; Direct links ; 57 / 888 ( 6 % ) ; -; Global clocks ; 2 / 4 ( 50 % ) ; -; LAB clocks ; 7 / 32 ( 22 % ) ; -; LUT chains ; 5 / 216 ( 2 % ) ; -; Local interconnects ; 340 / 888 ( 38 % ) ; -; R4s ; 150 / 704 ( 21 % ) ; -+-----------------------+--------------------+ - - -+---------------------------------------------------------------------------+ -; LAB Logic Elements ; -+--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 9.92) ; Number of LABs (Total = 24) ; -+--------------------------------------------+------------------------------+ -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 23 ; -+--------------------------------------------+------------------------------+ - - -+-------------------------------------------------------------------+ -; LAB-wide Signals ; -+------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.42) ; Number of LABs (Total = 24) ; -+------------------------------------+------------------------------+ -; 1 Clock ; 21 ; -; 1 Clock enable ; 9 ; -; 1 Sync. clear ; 2 ; -; 2 Clock enables ; 1 ; -; 2 Clocks ; 1 ; -+------------------------------------+------------------------------+ - - -+-----------------------------------------------------------------------------+ -; LAB Signals Sourced ; -+----------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 10.13) ; Number of LABs (Total = 24) ; -+----------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 0 ; -; 8 ; 1 ; -; 9 ; 0 ; -; 10 ; 22 ; -; 11 ; 0 ; -; 12 ; 0 ; -; 13 ; 0 ; -; 14 ; 0 ; -; 15 ; 1 ; -+----------------------------------------------+------------------------------+ - - -+--------------------------------------------------------------------------------+ -; LAB Signals Sourced Out ; -+-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 7.21) ; Number of LABs (Total = 24) ; -+-------------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 1 ; -; 2 ; 0 ; -; 3 ; 2 ; -; 4 ; 0 ; -; 5 ; 1 ; -; 6 ; 3 ; -; 7 ; 6 ; -; 8 ; 4 ; -; 9 ; 3 ; -; 10 ; 3 ; -; 11 ; 0 ; -; 12 ; 1 ; -+-------------------------------------------------+------------------------------+ - - -+-----------------------------------------------------------------------------+ -; LAB Distinct Inputs ; -+----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 12.54) ; Number of LABs (Total = 24) ; -+----------------------------------------------+------------------------------+ -; 0 ; 0 ; -; 1 ; 0 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 2 ; -; 5 ; 0 ; -; 6 ; 0 ; -; 7 ; 2 ; -; 8 ; 1 ; -; 9 ; 2 ; -; 10 ; 1 ; -; 11 ; 3 ; -; 12 ; 2 ; -; 13 ; 1 ; -; 14 ; 2 ; -; 15 ; 1 ; -; 16 ; 2 ; -; 17 ; 1 ; -; 18 ; 1 ; -; 19 ; 1 ; -; 20 ; 1 ; -; 21 ; 0 ; -; 22 ; 0 ; -; 23 ; 0 ; -; 24 ; 1 ; -+----------------------------------------------+------------------------------+ - - -+-------------------------------------------------------------------------+ -; Fitter Device Options ; -+----------------------------------------------+--------------------------+ -; Option ; Setting ; -+----------------------------------------------+--------------------------+ -; Enable user-supplied start-up clock (CLKUSR) ; Off ; -; Enable device-wide reset (DEV_CLRn) ; Off ; -; Enable device-wide output enable (DEV_OE) ; Off ; -; Enable INIT_DONE output ; Off ; -; Configuration scheme ; Passive Serial ; -; Reserve all unused pins ; As output driving ground ; -+----------------------------------------------+--------------------------+ - - -+-----------------+ -; Fitter Messages ; -+-----------------+ -Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (119006): Selected device 5M240ZT100C5 for design "RAM2E" -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time -Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. -Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices - Info (176445): Device 5M80ZT100C5 is compatible - Info (176445): Device 5M80ZT100I5 is compatible - Info (176445): Device 5M160ZT100C5 is compatible - Info (176445): Device 5M160ZT100I5 is compatible - Info (176445): Device 5M240ZT100I5 is compatible - Info (176445): Device 5M570ZT100C5 is compatible - Info (176445): Device 5M570ZT100I5 is compatible -Info (332104): Reading SDC File: '../RAM2E.sdc' -Info (332104): Reading SDC File: '../RAM2E-MAX.sdc' -Warning (332060): Node: PHI1 was determined to be a clock but was found without an associated clock assignment. - Info (13166): Register RefReq is being clocked by PHI1 -Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements -Info (332111): Found 3 clocks - Info (332111): Period Clock Name - Info (332111): ======== ============ - Info (332111): 69.841 C14M - Info (332111): 200.000 ram2e_ufm|ARCLK|regout - Info (332111): 200.000 ram2e_ufm|DRCLK|regout -Info (186079): Completed User Assigned Global Signals Promotion Operation -Info (186215): Automatically promoted signal "C14M" to use Global clock in PIN 12 File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 -Info (186216): Automatically promoted some destinations of signal "PHI1" to use Global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 - Info (186217): Destination "PHI1r" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 20 - Info (186217): Destination "S~0" may be non-global or may not use global clock File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 19 -Info (186228): Pin "PHI1" drives global clock, but is not placed in a dedicated clock pin position File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 8 -Info (186079): Completed Auto Global Promotion Operation -Info (176234): Starting register packing -Info (186468): Started processing fast register assignments -Warning (186473): Ignored the FAST_OUTPUT_REGISTER assignment made to the following nodes - Warning (186484): Ignored assignment to node "RAout[0]" because node "RAr[0]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[1]" because node "RAr[1]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[2]" because node "RAr[2]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[3]" because node "RAr[3]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[4]" because node "RAr[4]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[5]" because node "RAr[5]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[6]" because node "RAr[6]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 - Warning (186484): Ignored assignment to node "RAout[7]" because node "RAr[7]", which is feeding it, is not a register File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 85 -Info (186469): Finished processing fast register assignments -Info (176235): Finished register packing -Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 -Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family. -Info (170189): Fitter placement preparation operations beginning -Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 -Info (170191): Fitter placement operations beginning -Info (170137): Fitter placement was successful -Info (170192): Fitter placement operations ending: elapsed time is 00:00:02 -Info (170193): Fitter routing operations beginning -Info (170089): 2e+01 ns of routing delay (approximately 1.1% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. -Info (170195): Router estimated average interconnect usage is 25% of the available device resources - Info (170196): Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 -Info (170202): The Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and routability requirements required full optimization. -Info (170194): Fitter routing operations ending: elapsed time is 00:00:01 -Info (11888): Total time spent on timing analysis during the Fitter is 0.84 seconds. -Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 -Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg -Info: Quartus Prime Fitter was successful. 0 errors, 11 warnings - Info: Peak virtual memory: 13771 megabytes - Info: Processing ended: Thu Feb 15 04:16:23 2024 - Info: Elapsed time: 00:00:08 - Info: Total CPU time (on all processors): 00:00:05 - - -+----------------------------+ -; Fitter Suppressed Messages ; -+----------------------------+ -The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.fit.smsg. - - diff --git a/CPLD/MAXV/output_files/RAM2E.fit.smsg b/CPLD/MAXV/output_files/RAM2E.fit.smsg deleted file mode 100644 index a3cd98a..0000000 --- a/CPLD/MAXV/output_files/RAM2E.fit.smsg +++ /dev/null @@ -1,4 +0,0 @@ -Extra Info (176273): Performing register packing on registers with non-logic cell location assignments -Extra Info (176274): Completed register packing on registers with non-logic cell location assignments -Extra Info (176244): Moving registers into LUTs to improve timing and density -Extra Info (176245): Finished moving registers into LUTs: elapsed time is 00:00:00 diff --git a/CPLD/MAXV/output_files/RAM2E.fit.summary b/CPLD/MAXV/output_files/RAM2E.fit.summary deleted file mode 100644 index 0cdbb60..0000000 --- a/CPLD/MAXV/output_files/RAM2E.fit.summary +++ /dev/null @@ -1,11 +0,0 @@ -Fitter Status : Successful - Thu Feb 15 04:16:23 2024 -Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition -Revision Name : RAM2E -Top-level Entity Name : RAM2E -Family : MAX V -Device : 5M240ZT100C5 -Timing Models : Final -Total logic elements : 238 / 240 ( 99 % ) -Total pins : 70 / 79 ( 89 % ) -Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXV/output_files/RAM2E.flow.rpt b/CPLD/MAXV/output_files/RAM2E.flow.rpt deleted file mode 100644 index 5f4307d..0000000 --- a/CPLD/MAXV/output_files/RAM2E.flow.rpt +++ /dev/null @@ -1,117 +0,0 @@ -Flow report for RAM2E -Thu Feb 15 04:16:32 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - 8. Flow Messages - 9. Flow Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2019 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+---------------------------------------------------------------------+ -; Flow Summary ; -+-----------------------+---------------------------------------------+ -; Flow Status ; Successful - Thu Feb 15 04:16:27 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX V ; -; Device ; 5M240ZT100C5 ; -; Timing Models ; Final ; -; Total logic elements ; 238 / 240 ( 99 % ) ; -; Total pins ; 70 / 79 ( 89 % ) ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------+---------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 02/15/2024 04:15:29 ; -; Main task ; Compilation ; -; Revision Name ; RAM2E ; -+-------------------+---------------------+ - - -+---------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+-------------------------------+------------------------------+---------------+-------------+------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+-------------------------------+------------------------------+---------------+-------------+------------+ -; COMPILER_SIGNATURE_ID ; 121380219419.170798852904876 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; NUM_PARALLEL_PROCESSORS ; 4 ; -- ; -- ; -- ; -; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; -; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; -+-------------------------------+------------------------------+---------------+-------------+------------+ - - -+--------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:45 ; 1.0 ; 13146 MB ; 00:00:47 ; -; Fitter ; 00:00:08 ; 1.0 ; 13771 MB ; 00:00:05 ; -; Assembler ; 00:00:02 ; 1.0 ; 13091 MB ; 00:00:01 ; -; Timing Analyzer ; 00:00:03 ; 1.0 ; 13093 MB ; 00:00:02 ; -; Total ; 00:00:58 ; -- ; -- ; 00:00:55 ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+----------------------+------------------+------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+----------------------+------------------+------------+------------+----------------+ -; Analysis & Synthesis ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; -; Fitter ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; -; Assembler ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; -; Timing Analyzer ; ZaneMacWin11 ; Windows 10 ; 10.0 ; x86_64 ; -+----------------------+------------------+------------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E -quartus_fit --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E -quartus_asm --read_settings_files=off --write_settings_files=off RAM2E-MAXV -c RAM2E -quartus_sta RAM2E-MAXV -c RAM2E - - - diff --git a/CPLD/MAXV/output_files/RAM2E.jdi b/CPLD/MAXV/output_files/RAM2E.jdi deleted file mode 100644 index bec8212..0000000 --- a/CPLD/MAXV/output_files/RAM2E.jdi +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/CPLD/MAXV/output_files/RAM2E.map.rpt b/CPLD/MAXV/output_files/RAM2E.map.rpt deleted file mode 100644 index e734fd8..0000000 --- a/CPLD/MAXV/output_files/RAM2E.map.rpt +++ /dev/null @@ -1,330 +0,0 @@ -Analysis & Synthesis report for RAM2E -Thu Feb 15 04:16:13 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Analysis & Synthesis Summary - 3. Analysis & Synthesis Settings - 4. Parallel Compilation - 5. Analysis & Synthesis Source Files Read - 6. Analysis & Synthesis Resource Usage Summary - 7. Analysis & Synthesis Resource Utilization by Entity - 8. Analysis & Synthesis IP Cores Summary - 9. General Register Statistics - 10. Inverted Register Statistics - 11. Multiplexer Restructuring Statistics (Restructuring Performed) - 12. Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" - 13. Analysis & Synthesis Messages - 14. Analysis & Synthesis Suppressed Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2019 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+---------------------------------------------------------------------------+ -; Analysis & Synthesis Summary ; -+-----------------------------+---------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Thu Feb 15 04:16:13 2024 ; -; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; -; Revision Name ; RAM2E ; -; Top-level Entity Name ; RAM2E ; -; Family ; MAX V ; -; Total logic elements ; 252 ; -; Total pins ; 70 ; -; Total virtual pins ; 0 ; -; UFM blocks ; 1 / 1 ( 100 % ) ; -+-----------------------------+---------------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Settings ; -+------------------------------------------------------------------+--------------------+--------------------+ -; Option ; Setting ; Default Value ; -+------------------------------------------------------------------+--------------------+--------------------+ -; Device ; 5M240ZT100C5 ; ; -; Top-level entity name ; RAM2E ; RAM2E ; -; Family name ; MAX V ; Cyclone V ; -; Maximum processors allowed for parallel compilation ; 4 ; ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Restructure Multiplexers ; Auto ; Auto ; -; Create Debugging Nodes for IP Cores ; Off ; Off ; -; Preserve fewer node names ; On ; On ; -; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; -; Verilog Version ; Verilog_2001 ; Verilog_2001 ; -; VHDL Version ; VHDL_1993 ; VHDL_1993 ; -; State Machine Processing ; Auto ; Auto ; -; Safe State Machine ; Off ; Off ; -; Extract Verilog State Machines ; On ; On ; -; Extract VHDL State Machines ; On ; On ; -; Ignore Verilog initial constructs ; Off ; Off ; -; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; -; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; -; Add Pass-Through Logic to Inferred RAMs ; On ; On ; -; Infer RAMs from Raw Logic ; On ; On ; -; Parallel Synthesis ; On ; On ; -; NOT Gate Push-Back ; On ; On ; -; Power-Up Don't Care ; On ; On ; -; Remove Redundant Logic Cells ; Off ; Off ; -; Remove Duplicate Registers ; On ; On ; -; Ignore CARRY Buffers ; Off ; Off ; -; Ignore CASCADE Buffers ; Off ; Off ; -; Ignore GLOBAL Buffers ; Off ; Off ; -; Ignore ROW GLOBAL Buffers ; Off ; Off ; -; Ignore LCELL Buffers ; Off ; Off ; -; Ignore SOFT Buffers ; On ; On ; -; Limit AHDL Integers to 32 Bits ; Off ; Off ; -; Optimization Technique ; Balanced ; Balanced ; -; Carry Chain Length ; 70 ; 70 ; -; Auto Carry Chains ; On ; On ; -; Auto Open-Drain Pins ; On ; On ; -; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; -; Auto Shift Register Replacement ; Auto ; Auto ; -; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; -; Auto Clock Enable Replacement ; On ; On ; -; Allow Synchronous Control Signals ; On ; On ; -; Force Use of Synchronous Clear Signals ; Off ; Off ; -; Auto Resource Sharing ; Off ; Off ; -; Use LogicLock Constraints during Resource Balancing ; On ; On ; -; Ignore translate_off and synthesis_off directives ; Off ; Off ; -; Report Parameter Settings ; On ; On ; -; Report Source Assignments ; On ; On ; -; Report Connectivity Checks ; On ; On ; -; Ignore Maximum Fan-Out Assignments ; Off ; Off ; -; Synchronization Register Chain Length ; 2 ; 2 ; -; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; -; HDL message level ; Level2 ; Level2 ; -; Suppress Register Optimization Related Messages ; Off ; Off ; -; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; -; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; -; Clock MUX Protection ; On ; On ; -; Block Design Naming ; Auto ; Auto ; -; Synthesis Effort ; Auto ; Auto ; -; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; -; Analysis & Synthesis Message Level ; Medium ; Medium ; -; Disable Register Merging Across Hierarchies ; Auto ; Auto ; -+------------------------------------------------------------------+--------------------+--------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 1 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -+----------------------------+-------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Source Files Read ; -+----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+ -; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; -+----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+ -; ../RAM2E.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v ; ; -; ../UFM-MAX.v ; yes ; User Verilog HDL File ; //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v ; ; -; UFM.v ; yes ; User Wizard-Generated File ; //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v ; ; -; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/Home/Repos/RAM2E/CPLD/RAM2E.mif ; ; -+----------------------------------+-----------------+----------------------------------+----------------------------------------+---------+ - - -+-----------------------------------------------------+ -; Analysis & Synthesis Resource Usage Summary ; -+---------------------------------------------+-------+ -; Resource ; Usage ; -+---------------------------------------------+-------+ -; Total logic elements ; 252 ; -; -- Combinational with no register ; 126 ; -; -- Register only ; 33 ; -; -- Combinational with a register ; 93 ; -; ; ; -; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 116 ; -; -- 3 input functions ; 53 ; -; -- 2 input functions ; 46 ; -; -- 1 input functions ; 3 ; -; -- 0 input functions ; 1 ; -; ; ; -; Logic elements by mode ; ; -; -- normal mode ; 238 ; -; -- arithmetic mode ; 14 ; -; -- qfbk mode ; 0 ; -; -- register cascade mode ; 0 ; -; -- synchronous clear/load mode ; 3 ; -; -- asynchronous clear/load mode ; 0 ; -; ; ; -; Total registers ; 126 ; -; Total logic cells in carry chains ; 15 ; -; I/O pins ; 70 ; -; UFM blocks ; 1 ; -; Maximum fan-out node ; C14M ; -; Maximum fan-out ; 122 ; -; Total fan-out ; 1001 ; -; Average fan-out ; 3.10 ; -+---------------------------------------------+-------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis Resource Utilization by Entity ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -; |RAM2E ; 252 (191) ; 126 ; 1 ; 70 ; 0 ; 126 (97) ; 33 (25) ; 93 (69) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ; -; |RAM2E_UFM:ram2e_ufm| ; 61 (61) ; 32 ; 1 ; 0 ; 0 ; 29 (29) ; 8 (8) ; 24 (24) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm ; RAM2E_UFM ; work ; -; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM ; work ; -; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ; -+--------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------+---------------------+--------------+ -Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; Analysis & Synthesis IP Cores Summary ; -+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+ -; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; -+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+ -; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1 ; N/A ; N/A ; |RAM2E|RAM2E_UFM:ram2e_ufm|UFM:UFM_inst ; UFM.v ; -+--------+---------------------------+---------+--------------+--------------+-----------------------------------------+-----------------+ - - -+------------------------------------------------------+ -; General Register Statistics ; -+----------------------------------------------+-------+ -; Statistic ; Value ; -+----------------------------------------------+-------+ -; Total registers ; 126 ; -; Number of registers using Synchronous Clear ; 3 ; -; Number of registers using Synchronous Load ; 0 ; -; Number of registers using Asynchronous Clear ; 0 ; -; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 59 ; -; Number of registers using Preset ; 0 ; -+----------------------------------------------+-------+ - - -+---------------------------------------------------+ -; Inverted Register Statistics ; -+-----------------------------------------+---------+ -; Inverted Register ; Fan out ; -+-----------------------------------------+---------+ -; CKEout~reg0 ; 1 ; -; nRASout~reg0 ; 1 ; -; nCASout~reg0 ; 1 ; -; nRWEout~reg0 ; 1 ; -; DQML~reg0 ; 1 ; -; DQMH~reg0 ; 1 ; -; CKE ; 1 ; -; nRAS ; 1 ; -; nCAS ; 1 ; -; nRWE ; 1 ; -; Total number of inverted registers = 10 ; ; -+-----------------------------------------+---------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------+ -; Multiplexer Restructuring Statistics (Restructuring Performed) ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ -; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ -; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ; -; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[1] ; -; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RAM2E_UFM:ram2e_ufm|RWMask[5] ; -; 16:1 ; 2 bits ; 20 LEs ; 2 LEs ; 18 LEs ; Yes ; |RAM2E|BA[0]~reg0 ; -; 17:1 ; 4 bits ; 44 LEs ; 8 LEs ; 36 LEs ; Yes ; |RAM2E|RA[6] ; -; 19:1 ; 2 bits ; 24 LEs ; 4 LEs ; 20 LEs ; Yes ; |RAM2E|RA[1] ; -; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; Yes ; |RAM2E|DQML~reg0 ; -+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------+ - - -+------------------------------------------------------------------------------------------------------------------+ -; Port Connectivity Checks: "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" ; -+--------+--------+----------+-------------------------------------------------------------------------------------+ -; Port ; Type ; Severity ; Details ; -+--------+--------+----------+-------------------------------------------------------------------------------------+ -; ardin ; Input ; Info ; Stuck at GND ; -; oscena ; Input ; Info ; Stuck at VCC ; -; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; -+--------+--------+----------+-------------------------------------------------------------------------------------+ - - -+-------------------------------+ -; Analysis & Synthesis Messages ; -+-------------------------------+ -Info: ******************************************************************* -Info: Running Quartus Prime Analysis & Synthesis - Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Thu Feb 15 04:15:28 2024 -Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E -Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ram2e.v - Info (12023): Found entity 1: RAM2E File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 1 -Info (12021): Found 1 design units, including 1 entities, in source file //mac/home/repos/ram2e/cpld/ufm-max.v - Info (12023): Found entity 1: RAM2E_UFM File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 1 -Info (12021): Found 2 design units, including 2 entities, in source file ufm.v - Info (12023): Found entity 1: UFM_altufm_none_p8r File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47 - Info (12023): Found entity 2: UFM File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166 -Info (12127): Elaborating entity "RAM2E" for the top level hierarchy -Info (12128): Elaborating entity "RAM2E_UFM" for hierarchy "RAM2E_UFM:ram2e_ufm" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 136 -Info (12128): Elaborating entity "UFM" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst" File: //Mac/Home/Repos/RAM2E/CPLD/UFM-MAX.v Line: 77 -Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217 -Warning (13024): Output pins are stuck at VCC or GND - Warning (13410): Pin "nCSout" is stuck at GND File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 75 -Warning (14632): Output pin "Dout[0]" driven by bidirectional pin "RD[0]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[1]" driven by bidirectional pin "RD[1]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[2]" driven by bidirectional pin "RD[2]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[3]" driven by bidirectional pin "RD[3]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[4]" driven by bidirectional pin "RD[4]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[5]" driven by bidirectional pin "RD[5]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[6]" driven by bidirectional pin "RD[6]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (14632): Output pin "Dout[7]" driven by bidirectional pin "RD[7]" cannot be tri-stated File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 50 -Warning (21074): Design contains 1 input pin(s) that do not drive logic - Warning (15610): No output dependent on input pin "nWE80" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 11 -Info (21057): Implemented 323 device resources after synthesis - the final resource count might be different - Info (21058): Implemented 22 input pins - Info (21059): Implemented 40 output pins - Info (21060): Implemented 8 bidirectional pins - Info (21061): Implemented 252 logic cells - Info (21070): Implemented 1 User Flash Memory blocks -Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg -Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 12 warnings - Info: Peak virtual memory: 13146 megabytes - Info: Processing ended: Thu Feb 15 04:16:13 2024 - Info: Elapsed time: 00:00:45 - Info: Total CPU time (on all processors): 00:00:47 - - -+------------------------------------------+ -; Analysis & Synthesis Suppressed Messages ; -+------------------------------------------+ -The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg. - - diff --git a/CPLD/MAXV/output_files/RAM2E.map.smsg b/CPLD/MAXV/output_files/RAM2E.map.smsg deleted file mode 100644 index 585149c..0000000 --- a/CPLD/MAXV/output_files/RAM2E.map.smsg +++ /dev/null @@ -1,3 +0,0 @@ -Warning (10273): Verilog HDL warning at RAM2E.v(72): extended using "x" or "z" File: //Mac/Home/Repos/RAM2E/CPLD/RAM2E.v Line: 72 -Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73 -Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/Home/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189 diff --git a/CPLD/MAXV/output_files/RAM2E.map.summary b/CPLD/MAXV/output_files/RAM2E.map.summary deleted file mode 100644 index a0d20be..0000000 --- a/CPLD/MAXV/output_files/RAM2E.map.summary +++ /dev/null @@ -1,9 +0,0 @@ -Analysis & Synthesis Status : Successful - Thu Feb 15 04:16:13 2024 -Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition -Revision Name : RAM2E -Top-level Entity Name : RAM2E -Family : MAX V -Total logic elements : 252 -Total pins : 70 -Total virtual pins : 0 -UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXV/output_files/RAM2E.pin b/CPLD/MAXV/output_files/RAM2E.pin deleted file mode 100644 index f8d5ceb..0000000 --- a/CPLD/MAXV/output_files/RAM2E.pin +++ /dev/null @@ -1,165 +0,0 @@ - -- Copyright (C) 2019 Intel Corporation. All rights reserved. - -- Your use of Intel Corporation's design tools, logic functions - -- and other software and tools, and any partner logic - -- functions, and any output files from any of the foregoing - -- (including device programming or simulation files), and any - -- associated documentation or information are expressly subject - -- to the terms and conditions of the Intel Program License - -- Subscription Agreement, the Intel Quartus Prime License Agreement, - -- the Intel FPGA IP License Agreement, or other applicable license - -- agreement, including, without limitation, that your use is for - -- the sole purpose of programming logic devices manufactured by - -- Intel and sold by Intel or its authorized distributors. Please - -- refer to the applicable agreement for further details, at - -- https://fpgasoftware.intel.com/eula. - -- - -- This is a Quartus Prime output file. It is for reporting purposes only, and is - -- not intended for use as a Quartus Prime input file. This file cannot be used - -- to make Quartus Prime pin assignments - for instructions on how to make pin - -- assignments, please see Quartus Prime help. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- NC : No Connect. This pin has no internal connection to the device. - -- DNU : Do Not Use. This pin MUST NOT be connected. - -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.8V). - -- VCCIO : Dedicated power pin, which MUST be connected to VCC - -- of its bank. - -- Bank 1: 3.3V - -- Bank 2: 3.3V - -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. - -- It can also be used to report unused dedicated pins. The connection - -- on the board for unused dedicated pins depends on whether this will - -- be used in a future design. One example is device migration. When - -- using device migration, refer to the device pin-tables. If it is a - -- GND pin in the pin table or if it will not be used in a future design - -- for another purpose the it MUST be connected to GND. If it is an unused - -- dedicated pin, then it can be connected to a valid signal on the board - -- (low, high, or toggling) if that signal is required for a different - -- revision of the design. - -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. - -- This pin should be connected to GND. It may also be connected to a - -- valid signal on the board (low, high, or toggling) if that signal - -- is required for a different revision of the design. - -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND - -- or leave it unconnected. - -- RESERVED : Unused I/O pin, which MUST be left unconnected. - -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. - -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. - -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. - -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. - --------------------------------------------------------------------------------- - - - - --------------------------------------------------------------------------------- - -- Pin directions (input, output or bidir) are based on device operating in user mode. - --------------------------------------------------------------------------------- - -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition -CHIP "RAM2E" ASSIGNED TO AN: 5M240ZT100C5 - -Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment -------------------------------------------------------------------------------------------------------------- -GND : 1 : gnd : : : : -nRWEout : 2 : output : 3.3-V LVCMOS : : 1 : Y -nCASout : 3 : output : 3.3-V LVCMOS : : 1 : Y -CKEout : 4 : output : 3.3-V LVCMOS : : 1 : Y -nRASout : 5 : output : 3.3-V LVCMOS : : 1 : Y -BA[0] : 6 : output : 3.3-V LVCMOS : : 1 : Y -RAout[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y -nCSout : 8 : output : 3.3-V LVCMOS : : 1 : Y -VCCIO1 : 9 : power : : 3.3V : 1 : -GND : 10 : gnd : : : : -GND : 11 : gnd : : : : -C14M : 12 : input : 3.3-V LVCMOS : : 1 : Y -VCCINT : 13 : power : : 1.8V : : -BA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y -RAout[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y -RAout[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y -RAout[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y -RAout[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y -RAout[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y -RAout[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y -RAout[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y -TMS : 22 : input : : : 1 : -TDI : 23 : input : : : 1 : -TCK : 24 : input : : : 1 : -TDO : 25 : output : : : 1 : -RAout[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y -RAout[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y -nEN80 : 28 : input : 3.3-V LVCMOS : : 1 : Y -RAout[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y -RAout[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y -VCCIO1 : 31 : power : : 3.3V : 1 : -GND : 32 : gnd : : : : -nWE80 : 33 : input : 3.3-V LVCMOS : : 1 : Y -Ain[5] : 34 : input : 3.3-V LVCMOS : : 1 : Y -Din[7] : 35 : input : 3.3-V LVCMOS : : 1 : Y -Din[6] : 36 : input : 3.3-V LVCMOS : : 1 : Y -PHI1 : 37 : input : 3.3-V LVCMOS : : 1 : Y -Din[0] : 38 : input : 3.3-V LVCMOS : : 1 : Y -Ain[6] : 39 : input : 3.3-V LVCMOS : : 1 : Y -Din[1] : 40 : input : 3.3-V LVCMOS : : 1 : Y -Din[3] : 41 : input : 3.3-V LVCMOS : : 1 : Y -Din[2] : 42 : input : 3.3-V LVCMOS : : 1 : Y -Ain[2] : 43 : input : 3.3-V LVCMOS : : 1 : Y -Ain[4] : 44 : input : 3.3-V LVCMOS : : 1 : Y -VCCIO1 : 45 : power : : 3.3V : 1 : -GND : 46 : gnd : : : : -Ain[3] : 47 : input : 3.3-V LVCMOS : : 1 : Y -Din[4] : 48 : input : 3.3-V LVCMOS : : 1 : Y -Din[5] : 49 : input : 3.3-V LVCMOS : : 1 : Y -nVOE : 50 : output : 3.3-V LVCMOS : : 1 : Y -nWE : 51 : input : 3.3-V LVCMOS : : 1 : Y -nC07X : 52 : input : 3.3-V LVCMOS : : 2 : Y -Ain[7] : 53 : input : 3.3-V LVCMOS : : 2 : Y -Ain[1] : 54 : input : 3.3-V LVCMOS : : 2 : Y -nDOE : 55 : output : 3.3-V LVCMOS : : 2 : Y -Ain[0] : 56 : input : 3.3-V LVCMOS : : 2 : Y -Vout[7] : 57 : output : 3.3-V LVCMOS : : 2 : Y -Vout[6] : 58 : output : 3.3-V LVCMOS : : 2 : Y -VCCIO2 : 59 : power : : 3.3V : 2 : -GND : 60 : gnd : : : : -GND* : 61 : : : : 2 : -Vout[3] : 62 : output : 3.3-V LVCMOS : : 2 : Y -VCCINT : 63 : power : : 1.8V : : -GND* : 64 : : : : 2 : -GND : 65 : gnd : : : : -GND* : 66 : : : : 2 : -Vout[1] : 67 : output : 3.3-V LVCMOS : : 2 : Y -Vout[5] : 68 : output : 3.3-V LVCMOS : : 2 : Y -Vout[2] : 69 : output : 3.3-V LVCMOS : : 2 : Y -Vout[0] : 70 : output : 3.3-V LVCMOS : : 2 : Y -Vout[4] : 71 : output : 3.3-V LVCMOS : : 2 : Y -Dout[5] : 72 : output : 3.3-V LVCMOS : : 2 : Y -Dout[4] : 73 : output : 3.3-V LVCMOS : : 2 : Y -Dout[2] : 74 : output : 3.3-V LVCMOS : : 2 : Y -Dout[3] : 75 : output : 3.3-V LVCMOS : : 2 : Y -Dout[1] : 76 : output : 3.3-V LVCMOS : : 2 : Y -Dout[0] : 77 : output : 3.3-V LVCMOS : : 2 : Y -GND* : 78 : : : : 2 : -GND : 79 : gnd : : : : -VCCIO2 : 80 : power : : 3.3V : 2 : -GND* : 81 : : : : 2 : -GND* : 82 : : : : 2 : -GND* : 83 : : : : 2 : -Dout[6] : 84 : output : 3.3-V LVCMOS : : 2 : Y -Dout[7] : 85 : output : 3.3-V LVCMOS : : 2 : Y -GND* : 86 : : : : 2 : -GND* : 87 : : : : 2 : -LED : 88 : output : 3.3-V LVTTL : : 2 : Y -RD[3] : 89 : bidir : 3.3-V LVCMOS : : 2 : Y -RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y -RD[4] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y -RD[5] : 92 : bidir : 3.3-V LVCMOS : : 2 : Y -GND : 93 : gnd : : : : -VCCIO2 : 94 : power : : 3.3V : 2 : -RD[6] : 95 : bidir : 3.3-V LVCMOS : : 2 : Y -RD[7] : 96 : bidir : 3.3-V LVCMOS : : 2 : Y -RD[0] : 97 : bidir : 3.3-V LVCMOS : : 2 : Y -DQML : 98 : output : 3.3-V LVCMOS : : 2 : Y -RD[2] : 99 : bidir : 3.3-V LVCMOS : : 2 : Y -DQMH : 100 : output : 3.3-V LVCMOS : : 2 : Y diff --git a/CPLD/MAXV/output_files/RAM2E.pof b/CPLD/MAXV/output_files/RAM2E.pof deleted file mode 100644 index 6da4da42cf1d1244f85dc3a200cd6bfe89c1309c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 7861 zcmeHMdvH|Od0!bxmM4JmkYtDx49PT3XBuo_83V)k_(f!Y>QNFp$ZyT`T7Zj8M5g2e8X_Ut)d zf9KqlkTdmV%*gW_C4V$-YY}qt-{^A?v-%vaEwrv|9SwHudg|%~Q7vFf(O*h_DJAd)q z`|g^%YU9=obHBfS<5tLqt_V#7<5?p8p5=RtX#u&2eHJuFtUmAsDNl{t5A>O_Gs1z7RT?`1-L9(qZ1p2C;VISH{dxbaex3z- zkkj;e{v^DZv5(hfzp!uUZ)&i1yclGaWS9Ajq$7!2c@4S%pUVEpV9h1WYW;J|xZY)a zjd;PI^e{!CmooY=X!zz?)1VK&(U(|RiUcV{d0an;qes?nMJdfmD#vGrpTw&`9R7HL zydoXrE#!Fagg){W;A>%4VeuTY`umE6YS7f2&UW_omVhUbuTJEA9`=>Z7JTYYdSk|ZtD{6wQ&_3L4f?3L@cuV44{zT+ z?NI4h=9QW+SB)-@9bGhac=ZpS?#dW_34YV|j%ojScFy!&H8ZL{_%n92W-6_@=4osH zfc9!KO`{bHdPjeLbPD*Rk3LXcd-HI7^Pe9)3H>O&|6S-$U(j3XZ>+ou{BJ&39jc`G zz4yn0{ylqkWmDrP-#`1O_VztnX1)@4;uc>~U+>Egxo)oSy8~_}wIu#8 z&()>tUR&{GdpqjF)(6*8n!NicUD{@|O_T#KjhBtLM_iF0ElhlE9I>zR3M($PLJo!1 zDv+<_;JR*8=Y!UMeq27NKR<~YS;q{nq!f60q))dPeBh;!H{yZcz&{8Y=%{o*fq6h_ zt&Chw2lSwhj2>Q&^tk3Oq!`_A_?R(eIWu2)bFSbOd_S+WaAS}G&Nv^dk8<|dy0Fs) zy0m#K>nF)CA}%s%@W>Q5Bez=Rn4(bm6g+-uOT;u4qQGw`+gPs=0+xkU1PfV$Xt`4hD377a# z9z_}>N+^Sa1^Z_yyl+MVH21^JL&yhWiah0XjC@DPE>mB?#ebaO0N3JxR7oB~|N4$2 zgsm_B!y(t(DRZX3;B%gQzKI=F(aZ70K72pQa$RnN*9~9!@~=!cl~U5-sp@6szVi})ep?F{gVqnU8%n^ zZP)Dd$k(fX|HSap4=!#4|3du(v#fry*cZ<5pY|{KqxG|{OKBUw-rl~Z*6i^kaqpI`;hFJ~_S1cJ zGqcW#cDp~6gS-2DqnrC|)sakNN00O3n|nK6>sj&S-o?TGJ;%{okPp=PEktaopH>BC z`;Q0srcN3#Z;K7~+>w=+=Rg)Q)gIHL49CSKrZGaV3$1U5D7ReO@CYc zB9mHZmXl*GG2d@f8utxir1CuAlZ$f@&+w@*=)rFiDJUx{T7DF^%6?$Y!Y-TiY~v&} zOsY1VQpz97Dic>aJlZaJoCg! z!Mh#W&tH}WN=6k=gO9*-EwJYDJhlxhXqWvp{J|EtpU7d7mFe(=OLe2L`Z*qVbfoSz zW$tZ?OGkCLrDHLrN?tj>0p0*k)Yw|p0ui1foYNvaVaN7~-M8|h#=eI>M3Mu0_MBoW z{QfXE0TJ_=?!?Ul* z2J@*Ud_gaK;LW9n4~y#Ui>AyT1^=oU!|^LJRzFF-y+@nYXPn-+*Vua9HSvpa^xu}O zb9xR7_TRYa+4tPfj=NKj^kq_s{rH%s29pCzeNCkWUZY5NR`W)_IF4n6JnOa-z7=2VEvmPb6)g z4BgnV_(pD1P(PD01>63Q94I0i33|p&9&U==tLHaeaw;>A?IS3iKT^dN`-y<4N4V51{{IxX}gn zjJ~;F5=EIyF}C)MQbHCq>f7Sk{scZz5`G<|A=GyuZ~F~&JQ{q4%7$O5O*sn7)S2W2 z{=Q;)&SgCh2RBzqT}rDw<_FpO$Wxv{-yE;FK5*PmBo$6Ih;Fwsx z6b^BYIlz-%p#K$nzkq!w>*-$!skGOfa#IB-<&@7K#8sHQp)R0nMw8jk`2G~rc@qsg zSA--dhdgocArQ!AlUfKC&3bfQYN=Eo$de~2L9lQ6Q7QtN_>sT9)bBbZlHTk4^_};O zMBi=?>~mGXIF+h|v6?+|3-YK^y7ad5+u;8GO!3RV&-^2wb7bYQg*r3m)(xYTA5IU2 zE>7FkZsT)~LO1JgFWP>5<+1R=qu17M7_FLBJtK5+_KaQDezKUIrSG}-!|19*SKs|{ zsk3T~avh<{;n@`-dw!~L>5{(Z{*LD5hpw*PG7A2j?azL7#>Ls8^7+YDo$ZT6{P^EJ z)^~mD_J#4W_=!F97iZ(`PI>>CJ-fg4t(R6m^2jqs8<*9g|MsR6i52te+ROV#9MCVx zPV$$L^paT}1E_aR*&Syc%Kp*!}6NicZVf99z?&A*Dl$}1p z@{PX5iFj0K^CjYTN{g1u{l^IROJYfIuss^EI4R5zdoE1a&oP|;^2ZV2or--bK<5@8 zpZ~B=6K$U@YfH$bl#p6*Qme=N5BtH#$)xgJjTVLdmNYZ^^;Z8}(fE!28`SI#BHTY( zgdQ^aW41n@;ox_n{~9pQ|Mjyq+lc!w!#1XJx&I=hnW8c4H&G8Xi`%j|4Gk^@bV2mr zz$pp_yWW|YqV92dth^}FY+l+6r}{S+D@h6_xeg68F?tEv}X~SVFB{Gu zXKl?Sw(Qh7e4J3+&@bX;aXh!d#kES6%;!3fPM7JXKfz}?C5=C_2e0C%4E;xR9xv1h z=uDR71@cQfh16<8i;w-w<^zH#&FUFG+KG;M4t~C2N^8xc^b3XJ}Lh=l%)>-CJF?h=WS_>wo* z1@=dO5%ZJ0=dAE{-Z;om5B1BMHYB6v`|F8f=qE2d{Ow&w4z0SfdV9^3eV<;pvig_5 zym04(6*oK&ANGYqU&=I9J$K|#@AT@*n!_)iesTE~U0vw=4>6|^w?Do0a3TBHF4foj z^XkzTrl^Z^^z_QgOYsf2-C*KdKd17rHvHb+tE-==IjqJi^qzO#xzxU4c~D;r_s_`f znd80j{?^7@7sh40eNQBkb&{v;{vGQ3Z1+QM-@Biz8u;jwj;G=;E^1HL)vb84=PAqI zAxIQu#Kbjg{Q=d)H7A1jfsXovpE%p_O^JuPmS^@V6&(^*&ekt#PeDn0JW;Q@c#-y^ zKXD#F5A`Yvs0{^>qRY8boa=0xX%(xVCyqRrdO`dd4LaJFE<>GM>azI(KGQ-;*rhW| z7&qr~QE($~^-*!CbMzMn-K?OyoW>N5`-gr;JD@En#m)CbR?qgg-4`)#_G{@#F8rlp z7aNx=ufg*;{)Bv>hx#k)m+hPTw80DT?fGa%f{Di@yW{=`{WV!$i*dY3IR1oudEevs zEb#~aOxXQj=(t}P92@U44(qmlN{cT7{v^9r-t-yqGk9;~Pw$Q`9SQs~c_~6mF+Z@2 zFV{b37rzfY-*0{&Sk`HNA9xp^GmFfe=;QuR!U63M>688W94=(Pc>a8y{9ngoR%mMF f#4kc~%`ZYo$`}8>h`<*S_ diff --git a/CPLD/MAXV/output_files/RAM2E.sta.rpt b/CPLD/MAXV/output_files/RAM2E.sta.rpt deleted file mode 100644 index c4a4926..0000000 --- a/CPLD/MAXV/output_files/RAM2E.sta.rpt +++ /dev/null @@ -1,729 +0,0 @@ -Timing Analyzer report for RAM2E -Thu Feb 15 04:16:32 2024 -Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Timing Analyzer Summary - 3. Parallel Compilation - 4. SDC File List - 5. Clocks - 6. Fmax Summary - 7. Setup Summary - 8. Hold Summary - 9. Recovery Summary - 10. Removal Summary - 11. Minimum Pulse Width Summary - 12. Setup: 'ram2e_ufm|DRCLK|regout' - 13. Setup: 'ram2e_ufm|ARCLK|regout' - 14. Setup: 'C14M' - 15. Hold: 'ram2e_ufm|ARCLK|regout' - 16. Hold: 'ram2e_ufm|DRCLK|regout' - 17. Hold: 'C14M' - 18. Setup Transfers - 19. Hold Transfers - 20. Report TCCS - 21. Report RSKM - 22. Unconstrained Paths Summary - 23. Clock Status Summary - 24. Unconstrained Input Ports - 25. Unconstrained Output Ports - 26. Unconstrained Input Ports - 27. Unconstrained Output Ports - 28. Timing Analyzer Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 2019 Intel Corporation. All rights reserved. -Your use of Intel Corporation's design tools, logic functions -and other software and tools, and any partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Intel Program License -Subscription Agreement, the Intel Quartus Prime License Agreement, -the Intel FPGA IP License Agreement, or other applicable license -agreement, including, without limitation, that your use is for -the sole purpose of programming logic devices manufactured by -Intel and sold by Intel or its authorized distributors. Please -refer to the applicable agreement for further details, at -https://fpgasoftware.intel.com/eula. - - - -+-----------------------------------------------------------------------------+ -; Timing Analyzer Summary ; -+-----------------------+-----------------------------------------------------+ -; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; -; Timing Analyzer ; Legacy Timing Analyzer ; -; Revision Name ; RAM2E ; -; Device Family ; MAX V ; -; Device Name ; 5M240ZT100C5 ; -; Timing Models ; Final ; -; Delay Model ; Slow Model ; -; Rise/Fall Delays ; Unavailable ; -+-----------------------+-----------------------------------------------------+ - - -+------------------------------------------+ -; Parallel Compilation ; -+----------------------------+-------------+ -; Processors ; Number ; -+----------------------------+-------------+ -; Number detected on machine ; 4 ; -; Maximum allowed ; 4 ; -; ; ; -; Average used ; 1.00 ; -; Maximum used ; 2 ; -; ; ; -; Usage by Processor ; % Time Used ; -; Processor 1 ; 100.0% ; -; Processor 2 ; 0.0% ; -+----------------------------+-------------+ - - -+------------------------------------------------------+ -; SDC File List ; -+------------------+--------+--------------------------+ -; SDC File Path ; Status ; Read at ; -+------------------+--------+--------------------------+ -; ../RAM2E.sdc ; OK ; Thu Feb 15 04:16:31 2024 ; -; ../RAM2E-MAX.sdc ; OK ; Thu Feb 15 04:16:31 2024 ; -+------------------+--------+--------------------------+ - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Clocks ; -+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+ -; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; -+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+ -; C14M ; Base ; 69.841 ; 14.32 MHz ; 0.000 ; 34.920 ; ; ; ; ; ; ; ; ; ; ; { C14M } ; -; ram2e_ufm|ARCLK|regout ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ram2e_ufm|ARCLK|regout } ; -; ram2e_ufm|DRCLK|regout ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ram2e_ufm|DRCLK|regout } ; -+------------------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------------------------+ - - -+-------------------------------------------------------------+ -; Fmax Summary ; -+-----------+-----------------+------------------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+-----------+-----------------+------------------------+------+ -; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|ARCLK|regout ; ; -; 10.0 MHz ; 10.0 MHz ; ram2e_ufm|DRCLK|regout ; ; -; 27.75 MHz ; 27.75 MHz ; C14M ; ; -+-----------+-----------------+------------------------+------+ -This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. - - -+--------------------------------------------------+ -; Setup Summary ; -+------------------------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+------------------------+---------+---------------+ -; ram2e_ufm|DRCLK|regout ; -25.469 ; -25.469 ; -; ram2e_ufm|ARCLK|regout ; -25.439 ; -25.439 ; -; C14M ; -18.223 ; -201.658 ; -+------------------------+---------+---------------+ - - -+--------------------------------------------------+ -; Hold Summary ; -+------------------------+---------+---------------+ -; Clock ; Slack ; End Point TNS ; -+------------------------+---------+---------------+ -; ram2e_ufm|ARCLK|regout ; -14.560 ; -14.560 ; -; ram2e_ufm|DRCLK|regout ; -14.560 ; -14.560 ; -; C14M ; 3.156 ; 0.000 ; -+------------------------+---------+---------------+ - - --------------------- -; Recovery Summary ; --------------------- -No paths to report. - - -------------------- -; Removal Summary ; -------------------- -No paths to report. - - -+-------------------------------------------------+ -; Minimum Pulse Width Summary ; -+------------------------+--------+---------------+ -; Clock ; Slack ; End Point TNS ; -+------------------------+--------+---------------+ -; C14M ; 34.581 ; 0.000 ; -; ram2e_ufm|ARCLK|regout ; 70.000 ; 0.000 ; -; ram2e_ufm|DRCLK|regout ; 70.000 ; 0.000 ; -+------------------------+--------+---------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'ram2e_ufm|DRCLK|regout' ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; -25.469 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.477 ; 2.993 ; -; -25.439 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.001 ; -2.477 ; 2.963 ; -; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 200.000 ; 0.000 ; 80.000 ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'ram2e_ufm|ARCLK|regout' ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; -25.439 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.001 ; -2.477 ; 2.963 ; -; 100.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 200.000 ; 0.000 ; 80.000 ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Setup: 'C14M' ; -+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+ -; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ; -; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ; -; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ; -; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ; -; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ; -; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ; -; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ; -; -18.223 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 20.380 ; -; -17.497 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|LEDEN ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 19.654 ; -; -14.015 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 16.172 ; -; -14.004 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 16.161 ; -; -10.358 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; ram2e_ufm|DRCLK|regout ; C14M ; 0.001 ; 2.477 ; 12.515 ; -; 16.903 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.696 ; -; 16.903 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.696 ; -; 16.903 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.696 ; -; 16.993 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.606 ; -; 16.993 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.606 ; -; 16.993 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.606 ; -; 17.034 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.565 ; -; 17.034 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.565 ; -; 17.034 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.565 ; -; 17.124 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.475 ; -; 17.124 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.475 ; -; 17.124 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.475 ; -; 17.625 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.974 ; -; 17.625 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.974 ; -; 17.625 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.974 ; -; 17.715 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.884 ; -; 17.715 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.884 ; -; 17.715 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.884 ; -; 17.828 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.771 ; -; 17.828 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.771 ; -; 17.828 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.771 ; -; 17.918 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.681 ; -; 17.918 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.681 ; -; 17.918 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 16.681 ; -; 20.070 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.529 ; -; 20.070 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.529 ; -; 20.201 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.398 ; -; 20.201 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 14.398 ; -; 20.792 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.807 ; -; 20.792 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.807 ; -; 20.995 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.604 ; -; 20.995 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.604 ; -; 22.233 ; S[2] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 12.366 ; -; 23.933 ; S[3] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 10.666 ; -; 24.168 ; S[0] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 10.431 ; -; 25.342 ; S[1] ; VOE ; C14M ; C14M ; 34.920 ; 0.000 ; 9.257 ; -; 25.631 ; S[2] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 8.968 ; -; 27.763 ; S[3] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 6.836 ; -; 28.027 ; RA[8] ; RAr[8] ; C14M ; C14M ; 34.920 ; 0.000 ; 6.572 ; -; 28.362 ; RA[11] ; RAr[11] ; C14M ; C14M ; 34.920 ; 0.000 ; 6.237 ; -; 28.707 ; nCAS ; nCASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.892 ; -; 29.373 ; S[0] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 5.226 ; -; 29.587 ; S[1] ; RAT ; C14M ; C14M ; 34.920 ; 0.000 ; 5.012 ; -; 30.153 ; nRWE ; nRWEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.446 ; -; 30.163 ; nRAS ; nRASout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.436 ; -; 30.336 ; RA[6] ; RAr[6] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.263 ; -; 30.364 ; RA[2] ; RAr[2] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.235 ; -; 30.410 ; RA[9] ; RAr[9] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.189 ; -; 30.411 ; CKE ; CKEout~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.188 ; -; 30.417 ; RA[10] ; RAr[10] ; C14M ; C14M ; 34.920 ; 0.000 ; 4.182 ; -; 31.443 ; RA[0] ; RAr[0] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.156 ; -; 31.443 ; RA[3] ; RAr[3] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.156 ; -; 31.443 ; RA[4] ; RAr[4] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.156 ; -; 31.444 ; RA[1] ; RAr[1] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.155 ; -; 31.444 ; RA[7] ; RAr[7] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.155 ; -; 31.452 ; RA[5] ; RAr[5] ; C14M ; C14M ; 34.920 ; 0.000 ; 3.147 ; -; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ; -; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ; -; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ; -; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ; -; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ; -; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ; -; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ; -; 33.825 ; S[2] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 35.695 ; -; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ; -; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ; -; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ; -; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ; -; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ; -; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ; -; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ; -; 35.938 ; S[3] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 69.841 ; 0.000 ; 33.582 ; -; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ; -; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ; -; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ; -; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ; -; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ; -; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ; -; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ; -; 36.829 ; S[2] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.691 ; -; 36.851 ; S[2] ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 69.841 ; 0.000 ; 32.669 ; -; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ; -; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ; -; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ; -; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ; -; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ; -; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ; -; 36.947 ; S[0] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 69.841 ; 0.000 ; 32.573 ; -+---------+-----------------------------------------------------------------------------------------------------------------+---------------------------------+------------------------+-------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'ram2e_ufm|ARCLK|regout' ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; -14.560 ; RAM2E_UFM:ram2e_ufm|ARShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ram2e_ufm|ARCLK|regout ; 0.000 ; -2.477 ; 2.963 ; -; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 0.000 ; 0.000 ; 80.000 ; -+---------+-----------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'ram2e_ufm|DRCLK|regout' ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ -; -14.560 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.477 ; 2.963 ; -; -14.530 ; RAM2E_UFM:ram2e_ufm|DRShift ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; ram2e_ufm|DRCLK|regout ; 0.000 ; -2.477 ; 2.993 ; -; 60.000 ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RAM2E_UFM:ram2e_ufm|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 0.000 ; 0.000 ; 80.000 ; -+---------+-----------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------+------------------------+------------------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------------------------------+ -; Hold: 'C14M' ; -+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ -; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; -+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ -; 3.156 ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.195 ; -; 3.164 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.203 ; -; 3.170 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.209 ; -; 3.364 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.403 ; -; 3.394 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 3.433 ; -; 3.418 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.457 ; -; 3.450 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.489 ; -; 3.543 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.582 ; -; 3.547 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.586 ; -; 3.741 ; RAM2E_UFM:ram2e_ufm|DRDIn ; RAM2E_UFM:ram2e_ufm|DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 3.780 ; -; 3.752 ; RAM2E_UFM:ram2e_ufm|UFMProgram ; RAM2E_UFM:ram2e_ufm|UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.791 ; -; 3.752 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 3.791 ; -; 3.776 ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; RAM2E_UFM:ram2e_ufm|UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 3.815 ; -; 3.814 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.853 ; -; 3.817 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.856 ; -; 3.829 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.868 ; -; 3.865 ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 3.904 ; -; 3.935 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.974 ; -; 3.938 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.977 ; -; 3.951 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.990 ; -; 4.101 ; PHI1r ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.140 ; -; 4.102 ; PHI1r ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.141 ; -; 4.106 ; PHI1r ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.145 ; -; 4.224 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.263 ; -; 4.479 ; RAM2E_UFM:ram2e_ufm|UFMD[15] ; RAM2E_UFM:ram2e_ufm|RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.518 ; -; 4.839 ; CmdSetRWBankFFChip ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.878 ; -; 4.849 ; RAM2E_UFM:ram2e_ufm|DRCLKPulse ; RAM2E_UFM:ram2e_ufm|DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 4.888 ; -; 5.135 ; S[3] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.174 ; -; 5.217 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ; -; 5.217 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ; -; 5.218 ; RWBank[7] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.257 ; -; 5.231 ; RA[10] ; RA[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.270 ; -; 5.266 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.305 ; -; 5.267 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.306 ; -; 5.271 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.310 ; -; 5.284 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.323 ; -; 5.287 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.326 ; -; 5.420 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMProgStart ; C14M ; C14M ; 0.000 ; 0.000 ; 5.459 ; -; 5.443 ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; RAM2E_UFM:ram2e_ufm|UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.482 ; -; 5.443 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.482 ; -; 5.452 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ; -; 5.453 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ; -; 5.455 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.494 ; -; 5.457 ; S[1] ; RDOE ; C14M ; C14M ; 0.000 ; 0.000 ; 5.496 ; -; 5.464 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.503 ; -; 5.465 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.504 ; -; 5.466 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.505 ; -; 5.482 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.521 ; -; 5.486 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.525 ; -; 5.514 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.553 ; -; 5.515 ; S[0] ; nCAS ; C14M ; C14M ; 0.000 ; 0.000 ; 5.554 ; -; 5.530 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.569 ; -; 5.534 ; RAM2E_UFM:ram2e_ufm|CmdEraseMAX ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.573 ; -; 5.564 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.603 ; -; 5.574 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.613 ; -; 5.704 ; CmdLEDGet ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.743 ; -; 5.895 ; CmdSetRWBankFFLED ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.934 ; -; 6.001 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.040 ; -; 6.002 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.041 ; -; 6.006 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.045 ; -; 6.064 ; RAM2E_UFM:ram2e_ufm|UFMD[12] ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.103 ; -; 6.145 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.184 ; -; 6.146 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.185 ; -; 6.150 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.189 ; -; 6.174 ; PHI1r ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.213 ; -; 6.290 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.329 ; -; 6.294 ; RWBank[1] ; RA[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.333 ; -; 6.298 ; RAM2E_UFM:ram2e_ufm|UFMD[13] ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.337 ; -; 6.310 ; RAM2E_UFM:ram2e_ufm|UFMD[11] ; RAM2E_UFM:ram2e_ufm|RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.349 ; -; 6.318 ; RWBank[6] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.357 ; -; 6.321 ; FS[15] ; DQML~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.360 ; -; 6.323 ; FS[15] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.362 ; -; 6.348 ; RAM2E_UFM:ram2e_ufm|LEDEN ; RAM2E_UFM:ram2e_ufm|LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 6.387 ; -; 6.351 ; RWBank[4] ; RA[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.390 ; -; 6.371 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.410 ; -; 6.389 ; Ready ; RDOE ; C14M ; C14M ; 0.000 ; 0.000 ; 6.428 ; -; 6.393 ; RAM2E_UFM:ram2e_ufm|CmdPrgmMAX ; RAM2E_UFM:ram2e_ufm|UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 6.432 ; -; 6.425 ; RAM2E_UFM:ram2e_ufm|RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.464 ; -; 6.452 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.491 ; -; 6.454 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ; -; 6.455 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.494 ; -; 6.457 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.496 ; -; 6.466 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.505 ; -; 6.484 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.523 ; -; 6.488 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.527 ; -; 6.509 ; RAM2E_UFM:ram2e_ufm|UFMD[14] ; RAM2E_UFM:ram2e_ufm|RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.548 ; -; 6.537 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.576 ; -; 6.542 ; RAM2E_UFM:ram2e_ufm|UFMD[8] ; RAM2E_UFM:ram2e_ufm|UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.581 ; -; 6.549 ; RAM2E_UFM:ram2e_ufm|RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.588 ; -; 6.598 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ; -; 6.610 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.649 ; -; 6.613 ; RAM2E_UFM:ram2e_ufm|UFMD[10] ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.652 ; -; 6.632 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.671 ; -; 6.692 ; RAM2E_UFM:ram2e_ufm|RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.731 ; -; 6.754 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.793 ; -; 6.774 ; FS[10] ; RA[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.813 ; -; 6.776 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.815 ; -; 6.786 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ; -; 6.786 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ; -; 6.786 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ; -+-------+----------------------------------+----------------------------------+--------------+-------------+--------------+------------+------------+ - - -+---------------------------------------------------------------------------------------------+ -; Setup Transfers ; -+------------------------+------------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------------------+------------------------+----------+----------+----------+----------+ -; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ; -; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ; -; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ; -; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ; -; C14M ; ram2e_ufm|DRCLK|regout ; 2 ; 0 ; 0 ; 0 ; -; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1 ; 0 ; 0 ; 0 ; -+------------------------+------------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - -+---------------------------------------------------------------------------------------------+ -; Hold Transfers ; -+------------------------+------------------------+----------+----------+----------+----------+ -; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; -+------------------------+------------------------+----------+----------+----------+----------+ -; C14M ; C14M ; 1539 ; 0 ; 56 ; 0 ; -; ram2e_ufm|DRCLK|regout ; C14M ; 13 ; 0 ; 0 ; 0 ; -; C14M ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ; -; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; 1 ; 0 ; 0 ; 0 ; -; C14M ; ram2e_ufm|DRCLK|regout ; 2 ; 0 ; 0 ; 0 ; -; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; 1 ; 0 ; 0 ; 0 ; -+------------------------+------------------------+----------+----------+----------+----------+ -Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. - - ---------------- -; Report TCCS ; ---------------- -No dedicated SERDES Transmitter circuitry present in device or used in design - - ---------------- -; Report RSKM ; ---------------- -No non-DPA dedicated SERDES Receiver circuitry present in device or used in design - - -+------------------------------------------------+ -; Unconstrained Paths Summary ; -+---------------------------------+-------+------+ -; Property ; Setup ; Hold ; -+---------------------------------+-------+------+ -; Illegal Clocks ; 0 ; 0 ; -; Unconstrained Clocks ; 1 ; 1 ; -; Unconstrained Input Ports ; 28 ; 28 ; -; Unconstrained Input Port Paths ; 169 ; 169 ; -; Unconstrained Output Ports ; 47 ; 47 ; -; Unconstrained Output Port Paths ; 83 ; 83 ; -+---------------------------------+-------+------+ - - -+------------------------------------------------------------------------+ -; Clock Status Summary ; -+------------------------+------------------------+------+---------------+ -; Target ; Clock ; Type ; Status ; -+------------------------+------------------------+------+---------------+ -; C14M ; C14M ; Base ; Constrained ; -; PHI1 ; ; Base ; Unconstrained ; -; ram2e_ufm|ARCLK|regout ; ram2e_ufm|ARCLK|regout ; Base ; Constrained ; -; ram2e_ufm|DRCLK|regout ; ram2e_ufm|DRCLK|regout ; Base ; Constrained ; -+------------------------+------------------------+------+---------------+ - - -+---------------------------------------------------------------------------------------------------+ -; Unconstrained Input Ports ; -+------------+--------------------------------------------------------------------------------------+ -; Input Port ; Comment ; -+------------+--------------------------------------------------------------------------------------+ -; Ain[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; PHI1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -+------------+--------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------+ -; Unconstrained Output Ports ; -+-------------+---------------------------------------------------------------------------------------+ -; Output Port ; Comment ; -+-------------+---------------------------------------------------------------------------------------+ -; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; CKEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nCASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nRASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nRWEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -+-------------+---------------------------------------------------------------------------------------+ - - -+---------------------------------------------------------------------------------------------------+ -; Unconstrained Input Ports ; -+------------+--------------------------------------------------------------------------------------+ -; Input Port ; Comment ; -+------------+--------------------------------------------------------------------------------------+ -; Ain[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Ain[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; PHI1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; -+------------+--------------------------------------------------------------------------------------+ - - -+-----------------------------------------------------------------------------------------------------+ -; Unconstrained Output Ports ; -+-------------+---------------------------------------------------------------------------------------+ -; Output Port ; Comment ; -+-------------+---------------------------------------------------------------------------------------+ -; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; CKEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RAout[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nCASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nRASout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nRWEout ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; -+-------------+---------------------------------------------------------------------------------------+ - - -+--------------------------+ -; Timing Analyzer Messages ; -+--------------------------+ -Info: ******************************************************************* -Info: Running Quartus Prime Timing Analyzer - Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition - Info: Processing started: Thu Feb 15 04:16:29 2024 -Info: Command: quartus_sta RAM2E-MAXV -c RAM2E -Info: qsta_default_script.tcl version: #1 -Info (20032): Parallel compilation is enabled and will use up to 4 processors -Info (21077): Low junction temperature is 0 degrees C -Info (21077): High junction temperature is 85 degrees C -Info (334003): Started post-fitting delay annotation -Info (334004): Delay annotation completed successfully -Info (332104): Reading SDC File: '../RAM2E.sdc' -Info (332104): Reading SDC File: '../RAM2E-MAX.sdc' -Warning (332060): Node: PHI1 was determined to be a clock but was found without an associated clock assignment. - Info (13166): Register RefReq is being clocked by PHI1 -Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. -Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|ARCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. -Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ram2e_ufm|DRCLK|regout are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. -Critical Warning (332148): Timing requirements not met -Info (332146): Worst-case setup slack is -25.469 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): -25.469 -25.469 ram2e_ufm|DRCLK|regout - Info (332119): -25.439 -25.439 ram2e_ufm|ARCLK|regout - Info (332119): -18.223 -201.658 C14M -Info (332146): Worst-case hold slack is -14.560 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): -14.560 -14.560 ram2e_ufm|ARCLK|regout - Info (332119): -14.560 -14.560 ram2e_ufm|DRCLK|regout - Info (332119): 3.156 0.000 C14M -Info (332140): No Recovery paths to report -Info (332140): No Removal paths to report -Info (332146): Worst-case minimum pulse width slack is 34.581 - Info (332119): Slack End Point TNS Clock - Info (332119): ========= =================== ===================== - Info (332119): 34.581 0.000 C14M - Info (332119): 70.000 0.000 ram2e_ufm|ARCLK|regout - Info (332119): 70.000 0.000 ram2e_ufm|DRCLK|regout -Info (332001): The selected device family is not supported by the report_metastability command. -Info (332102): Design is not fully constrained for setup requirements -Info (332102): Design is not fully constrained for hold requirements -Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings - Info: Peak virtual memory: 13093 megabytes - Info: Processing ended: Thu Feb 15 04:16:32 2024 - Info: Elapsed time: 00:00:03 - Info: Total CPU time (on all processors): 00:00:02 - - diff --git a/CPLD/MAXV/output_files/RAM2E.sta.summary b/CPLD/MAXV/output_files/RAM2E.sta.summary deleted file mode 100644 index 801c9c9..0000000 --- a/CPLD/MAXV/output_files/RAM2E.sta.summary +++ /dev/null @@ -1,41 +0,0 @@ ------------------------------------------------------------- -Timing Analyzer Summary ------------------------------------------------------------- - -Type : Setup 'ram2e_ufm|DRCLK|regout' -Slack : -25.469 -TNS : -25.469 - -Type : Setup 'ram2e_ufm|ARCLK|regout' -Slack : -25.439 -TNS : -25.439 - -Type : Setup 'C14M' -Slack : -18.223 -TNS : -201.658 - -Type : Hold 'ram2e_ufm|ARCLK|regout' -Slack : -14.560 -TNS : -14.560 - -Type : Hold 'ram2e_ufm|DRCLK|regout' -Slack : -14.560 -TNS : -14.560 - -Type : Hold 'C14M' -Slack : 3.156 -TNS : 0.000 - -Type : Minimum Pulse Width 'C14M' -Slack : 34.581 -TNS : 0.000 - -Type : Minimum Pulse Width 'ram2e_ufm|ARCLK|regout' -Slack : 70.000 -TNS : 0.000 - -Type : Minimum Pulse Width 'ram2e_ufm|DRCLK|regout' -Slack : 70.000 -TNS : 0.000 - -------------------------------------------------------------