mirror of
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Remove old files
This commit is contained in:
Zane Kaminski
parent
385bd8cf01
commit
7a4150866d
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@ -1,26 +0,0 @@
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- Quartus II generated Memory Initialization File (.mif)
|
||||
|
||||
WIDTH=16;
|
||||
DEPTH=512;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
000 : 8080;
|
||||
[001..1FF] : FFFF;
|
||||
END;
|
||||
@ -1,273 +0,0 @@
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- Quartus II generated Memory Initialization File (.mif)
|
||||
|
||||
WIDTH=16;
|
||||
DEPTH=512;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
000 : 0000;
|
||||
001 : 0101;
|
||||
002 : 0202;
|
||||
003 : 0303;
|
||||
004 : 0404;
|
||||
005 : 0505;
|
||||
006 : 0606;
|
||||
007 : 0707;
|
||||
008 : 0808;
|
||||
009 : 0909;
|
||||
00A : 0A0A;
|
||||
00B : 0B0B;
|
||||
00C : 0C0C;
|
||||
00D : 0D0D;
|
||||
00E : 0E0E;
|
||||
00F : 0F0F;
|
||||
010 : 1010;
|
||||
011 : 1111;
|
||||
012 : 1212;
|
||||
013 : 1313;
|
||||
014 : 1414;
|
||||
015 : 1515;
|
||||
016 : 1616;
|
||||
017 : 1717;
|
||||
018 : 1818;
|
||||
019 : 1919;
|
||||
01A : 1A1A;
|
||||
01B : 1B1B;
|
||||
01C : 1C1C;
|
||||
01D : 1D1D;
|
||||
01E : 1E1E;
|
||||
01F : 1F1F;
|
||||
020 : 2020;
|
||||
021 : 2121;
|
||||
022 : 2222;
|
||||
023 : 2323;
|
||||
024 : 2424;
|
||||
025 : 2525;
|
||||
026 : 2626;
|
||||
027 : 2727;
|
||||
028 : 2828;
|
||||
029 : 2929;
|
||||
02A : 2A2A;
|
||||
02B : 2B2B;
|
||||
02C : 2C2C;
|
||||
02D : 2D2D;
|
||||
02E : 2E2E;
|
||||
02F : 2F2F;
|
||||
030 : 3030;
|
||||
031 : 3131;
|
||||
032 : 3232;
|
||||
033 : 3333;
|
||||
034 : 3434;
|
||||
035 : 3535;
|
||||
036 : 3636;
|
||||
037 : 3737;
|
||||
038 : 3838;
|
||||
039 : 3939;
|
||||
03A : 3A3A;
|
||||
03B : 3B3B;
|
||||
03C : 3C3C;
|
||||
03D : 3D3D;
|
||||
03E : 3E3E;
|
||||
03F : 3F3F;
|
||||
040 : 4040;
|
||||
041 : 4141;
|
||||
042 : 4242;
|
||||
043 : 4343;
|
||||
044 : 4444;
|
||||
045 : 4545;
|
||||
046 : 4646;
|
||||
047 : 4747;
|
||||
048 : 4848;
|
||||
049 : 4949;
|
||||
04A : 4A4A;
|
||||
04B : 4B4B;
|
||||
04C : 4C4C;
|
||||
04D : 4D4D;
|
||||
04E : 4E4E;
|
||||
04F : 4F4F;
|
||||
050 : 5050;
|
||||
051 : 5151;
|
||||
052 : 5252;
|
||||
053 : 5353;
|
||||
054 : 5454;
|
||||
055 : 5555;
|
||||
056 : 5656;
|
||||
057 : 5757;
|
||||
058 : 5858;
|
||||
059 : 5959;
|
||||
05A : 5A5A;
|
||||
05B : 5B5B;
|
||||
05C : 5C5C;
|
||||
05D : 5D5D;
|
||||
05E : 5E5E;
|
||||
05F : 5F5F;
|
||||
060 : 6060;
|
||||
061 : 6161;
|
||||
062 : 6262;
|
||||
063 : 6363;
|
||||
064 : 6464;
|
||||
065 : 6565;
|
||||
066 : 6666;
|
||||
067 : 6767;
|
||||
068 : 6868;
|
||||
069 : 6969;
|
||||
06A : 6A6A;
|
||||
06B : 6B6B;
|
||||
06C : 6C6C;
|
||||
06D : 6D6D;
|
||||
06E : 6E6E;
|
||||
06F : 6F6F;
|
||||
070 : 7070;
|
||||
071 : 7171;
|
||||
072 : 7272;
|
||||
073 : 7373;
|
||||
074 : 7474;
|
||||
075 : 7575;
|
||||
076 : 7676;
|
||||
077 : 7777;
|
||||
078 : 7878;
|
||||
079 : 7979;
|
||||
07A : 7A7A;
|
||||
07B : 7B7B;
|
||||
07C : 7C7C;
|
||||
07D : 7D7D;
|
||||
07E : 7E7E;
|
||||
07F : 7F7F;
|
||||
080 : 8080;
|
||||
081 : 8181;
|
||||
082 : 8282;
|
||||
083 : 8383;
|
||||
084 : 8484;
|
||||
085 : 8585;
|
||||
086 : 8686;
|
||||
087 : 8787;
|
||||
088 : 8888;
|
||||
089 : 8989;
|
||||
08A : 8A8A;
|
||||
08B : 8B8B;
|
||||
08C : 8C8C;
|
||||
08D : 8D8D;
|
||||
08E : 8E8E;
|
||||
08F : 8F8F;
|
||||
090 : 9090;
|
||||
091 : 9191;
|
||||
092 : 9292;
|
||||
093 : 9393;
|
||||
094 : 9494;
|
||||
095 : 9595;
|
||||
096 : 9696;
|
||||
097 : 9797;
|
||||
098 : 9898;
|
||||
099 : 9999;
|
||||
09A : 9A9A;
|
||||
09B : 9B9B;
|
||||
09C : 9C9C;
|
||||
09D : 9D9D;
|
||||
09E : 9E9E;
|
||||
09F : 9F9F;
|
||||
0A0 : A0A0;
|
||||
0A1 : A1A1;
|
||||
0A2 : A2A2;
|
||||
0A3 : A3A3;
|
||||
0A4 : A4A4;
|
||||
0A5 : A5A5;
|
||||
0A6 : A6A6;
|
||||
0A7 : A7A7;
|
||||
0A8 : A8A8;
|
||||
0A9 : A9A9;
|
||||
0AA : AAAA;
|
||||
0AB : ABAB;
|
||||
0AC : ACAC;
|
||||
0AD : ADAD;
|
||||
0AE : AEAE;
|
||||
0AF : AFAF;
|
||||
0B0 : B0B0;
|
||||
0B1 : B1B1;
|
||||
0B2 : B2B2;
|
||||
0B3 : B3B3;
|
||||
0B4 : B4B4;
|
||||
0B5 : B5B5;
|
||||
0B6 : B6B6;
|
||||
0B7 : B7B7;
|
||||
0B8 : B8B8;
|
||||
0B9 : B9B9;
|
||||
0BA : BABA;
|
||||
0BB : BBBB;
|
||||
0BC : BCBC;
|
||||
0BD : BDBD;
|
||||
0BE : BEBE;
|
||||
0BF : BFBF;
|
||||
0C0 : C0C0;
|
||||
0C1 : C1C1;
|
||||
0C2 : C2C2;
|
||||
0C3 : C3C3;
|
||||
0C4 : C4C4;
|
||||
0C5 : C5C5;
|
||||
0C6 : C6C6;
|
||||
0C7 : C7C7;
|
||||
0C8 : C8C8;
|
||||
0C9 : C9C9;
|
||||
0CA : CACA;
|
||||
0CB : CBCB;
|
||||
0CC : CCCC;
|
||||
0CD : CDCD;
|
||||
0CE : CECE;
|
||||
0CF : CFCF;
|
||||
0D0 : D0D0;
|
||||
0D1 : D1D1;
|
||||
0D2 : D2D2;
|
||||
0D3 : D3D3;
|
||||
0D4 : D4D4;
|
||||
0D5 : D5D5;
|
||||
0D6 : D6D6;
|
||||
0D7 : D7D7;
|
||||
0D8 : D8D8;
|
||||
0D9 : D9D9;
|
||||
0DA : DADA;
|
||||
0DB : DBDB;
|
||||
0DC : DCDC;
|
||||
0DD : DDDD;
|
||||
0DE : DEDE;
|
||||
0DF : DFDF;
|
||||
0E0 : E0E0;
|
||||
0E1 : E1E1;
|
||||
0E2 : E2E2;
|
||||
0E3 : E3E3;
|
||||
0E4 : E4E4;
|
||||
0E5 : E5E5;
|
||||
0E6 : E6E6;
|
||||
0E7 : E7E7;
|
||||
0E8 : E8E8;
|
||||
0E9 : E9E9;
|
||||
0EA : EAEA;
|
||||
0EB : EBEB;
|
||||
0EC : ECEC;
|
||||
0ED : EDED;
|
||||
0EE : EEEE;
|
||||
0EF : EFEF;
|
||||
0F0 : F0F0;
|
||||
0F1 : F1F1;
|
||||
0F2 : F2F2;
|
||||
0F3 : F3F3;
|
||||
0F4 : F4F4;
|
||||
0F5 : F5F5;
|
||||
0F6 : F6F6;
|
||||
0F7 : 7F7F;
|
||||
[0F8..1FF] : FFFF;
|
||||
END;
|
||||
@ -1,25 +0,0 @@
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- Quartus II generated Memory Initialization File (.mif)
|
||||
|
||||
WIDTH=16;
|
||||
DEPTH=512;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
[000..1FF] : FFFF;
|
||||
END;
|
||||
@ -1,281 +0,0 @@
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- Quartus II generated Memory Initialization File (.mif)
|
||||
|
||||
WIDTH=16;
|
||||
DEPTH=512;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
000 : 0000;
|
||||
001 : 0101;
|
||||
002 : 0202;
|
||||
003 : 0303;
|
||||
004 : 0404;
|
||||
005 : 0505;
|
||||
006 : 0606;
|
||||
007 : 0707;
|
||||
008 : 0808;
|
||||
009 : 0909;
|
||||
00A : 0A0A;
|
||||
00B : 0B0B;
|
||||
00C : 0C0C;
|
||||
00D : 0D0D;
|
||||
00E : 0E0E;
|
||||
00F : 0F0F;
|
||||
010 : 1010;
|
||||
011 : 1111;
|
||||
012 : 1212;
|
||||
013 : 1313;
|
||||
014 : 1414;
|
||||
015 : 1515;
|
||||
016 : 1616;
|
||||
017 : 1717;
|
||||
018 : 1818;
|
||||
019 : 1919;
|
||||
01A : 1A1A;
|
||||
01B : 1B1B;
|
||||
01C : 1C1C;
|
||||
01D : 1D1D;
|
||||
01E : 1E1E;
|
||||
01F : 1F1F;
|
||||
020 : 2020;
|
||||
021 : 2121;
|
||||
022 : 2222;
|
||||
023 : 2323;
|
||||
024 : 2424;
|
||||
025 : 2525;
|
||||
026 : 2626;
|
||||
027 : 2727;
|
||||
028 : 2828;
|
||||
029 : 2929;
|
||||
02A : 2A2A;
|
||||
02B : 2B2B;
|
||||
02C : 2C2C;
|
||||
02D : 2D2D;
|
||||
02E : 2E2E;
|
||||
02F : 2F2F;
|
||||
030 : 3030;
|
||||
031 : 3131;
|
||||
032 : 3232;
|
||||
033 : 3333;
|
||||
034 : 3434;
|
||||
035 : 3535;
|
||||
036 : 3636;
|
||||
037 : 3737;
|
||||
038 : 3838;
|
||||
039 : 3939;
|
||||
03A : 3A3A;
|
||||
03B : 3B3B;
|
||||
03C : 3C3C;
|
||||
03D : 3D3D;
|
||||
03E : 3E3E;
|
||||
03F : 3F3F;
|
||||
040 : 4040;
|
||||
041 : 4141;
|
||||
042 : 4242;
|
||||
043 : 4343;
|
||||
044 : 4444;
|
||||
045 : 4545;
|
||||
046 : 4646;
|
||||
047 : 4747;
|
||||
048 : 4848;
|
||||
049 : 4949;
|
||||
04A : 4A4A;
|
||||
04B : 4B4B;
|
||||
04C : 4C4C;
|
||||
04D : 4D4D;
|
||||
04E : 4E4E;
|
||||
04F : 4F4F;
|
||||
050 : 5050;
|
||||
051 : 5151;
|
||||
052 : 5252;
|
||||
053 : 5353;
|
||||
054 : 5454;
|
||||
055 : 5555;
|
||||
056 : 5656;
|
||||
057 : 5757;
|
||||
058 : 5858;
|
||||
059 : 5959;
|
||||
05A : 5A5A;
|
||||
05B : 5B5B;
|
||||
05C : 5C5C;
|
||||
05D : 5D5D;
|
||||
05E : 5E5E;
|
||||
05F : 5F5F;
|
||||
060 : 6060;
|
||||
061 : 6161;
|
||||
062 : 6262;
|
||||
063 : 6363;
|
||||
064 : 6464;
|
||||
065 : 6565;
|
||||
066 : 6666;
|
||||
067 : 6767;
|
||||
068 : 6868;
|
||||
069 : 6969;
|
||||
06A : 6A6A;
|
||||
06B : 6B6B;
|
||||
06C : 6C6C;
|
||||
06D : 6D6D;
|
||||
06E : 6E6E;
|
||||
06F : 6F6F;
|
||||
070 : 7070;
|
||||
071 : 7171;
|
||||
072 : 7272;
|
||||
073 : 7373;
|
||||
074 : 7474;
|
||||
075 : 7575;
|
||||
076 : 7676;
|
||||
077 : 7777;
|
||||
078 : 7878;
|
||||
079 : 7979;
|
||||
07A : 7A7A;
|
||||
07B : 7B7B;
|
||||
07C : 7C7C;
|
||||
07D : 7D7D;
|
||||
07E : 7E7E;
|
||||
07F : 7F7F;
|
||||
080 : 8080;
|
||||
081 : 8181;
|
||||
082 : 8282;
|
||||
083 : 8383;
|
||||
084 : 8484;
|
||||
085 : 8585;
|
||||
086 : 8686;
|
||||
087 : 8787;
|
||||
088 : 8888;
|
||||
089 : 8989;
|
||||
08A : 8A8A;
|
||||
08B : 8B8B;
|
||||
08C : 8C8C;
|
||||
08D : 8D8D;
|
||||
08E : 8E8E;
|
||||
08F : 8F8F;
|
||||
090 : 9090;
|
||||
091 : 9191;
|
||||
092 : 9292;
|
||||
093 : 9393;
|
||||
094 : 9494;
|
||||
095 : 9595;
|
||||
096 : 9696;
|
||||
097 : 9797;
|
||||
098 : 9898;
|
||||
099 : 9999;
|
||||
09A : 9A9A;
|
||||
09B : 9B9B;
|
||||
09C : 9C9C;
|
||||
09D : 9D9D;
|
||||
09E : 9E9E;
|
||||
09F : 9F9F;
|
||||
0A0 : A0A0;
|
||||
0A1 : A1A1;
|
||||
0A2 : A2A2;
|
||||
0A3 : A3A3;
|
||||
0A4 : A4A4;
|
||||
0A5 : A5A5;
|
||||
0A6 : A6A6;
|
||||
0A7 : A7A7;
|
||||
0A8 : A8A8;
|
||||
0A9 : A9A9;
|
||||
0AA : AAAA;
|
||||
0AB : ABAB;
|
||||
0AC : ACAC;
|
||||
0AD : ADAD;
|
||||
0AE : AEAE;
|
||||
0AF : AFAF;
|
||||
0B0 : B0B0;
|
||||
0B1 : B1B1;
|
||||
0B2 : B2B2;
|
||||
0B3 : B3B3;
|
||||
0B4 : B4B4;
|
||||
0B5 : B5B5;
|
||||
0B6 : B6B6;
|
||||
0B7 : B7B7;
|
||||
0B8 : B8B8;
|
||||
0B9 : B9B9;
|
||||
0BA : BABA;
|
||||
0BB : BBBB;
|
||||
0BC : BCBC;
|
||||
0BD : BDBD;
|
||||
0BE : BEBE;
|
||||
0BF : BFBF;
|
||||
0C0 : C0C0;
|
||||
0C1 : C1C1;
|
||||
0C2 : C2C2;
|
||||
0C3 : C3C3;
|
||||
0C4 : C4C4;
|
||||
0C5 : C5C5;
|
||||
0C6 : C6C6;
|
||||
0C7 : C7C7;
|
||||
0C8 : C8C8;
|
||||
0C9 : C9C9;
|
||||
0CA : CACA;
|
||||
0CB : CBCB;
|
||||
0CC : CCCC;
|
||||
0CD : CDCD;
|
||||
0CE : CECE;
|
||||
0CF : CFCF;
|
||||
0D0 : D0D0;
|
||||
0D1 : D1D1;
|
||||
0D2 : D2D2;
|
||||
0D3 : D3D3;
|
||||
0D4 : D4D4;
|
||||
0D5 : D5D5;
|
||||
0D6 : D6D6;
|
||||
0D7 : D7D7;
|
||||
0D8 : D8D8;
|
||||
0D9 : D9D9;
|
||||
0DA : DADA;
|
||||
0DB : DBDB;
|
||||
0DC : DCDC;
|
||||
0DD : DDDD;
|
||||
0DE : DEDE;
|
||||
0DF : DFDF;
|
||||
0E0 : E0E0;
|
||||
0E1 : E1E1;
|
||||
0E2 : E2E2;
|
||||
0E3 : E3E3;
|
||||
0E4 : E4E4;
|
||||
0E5 : E5E5;
|
||||
0E6 : E6E6;
|
||||
0E7 : E7E7;
|
||||
0E8 : E8E8;
|
||||
0E9 : E9E9;
|
||||
0EA : EAEA;
|
||||
0EB : EBEB;
|
||||
0EC : ECEC;
|
||||
0ED : EDED;
|
||||
0EE : EEEE;
|
||||
0EF : EFEF;
|
||||
0F0 : F0F0;
|
||||
0F1 : F1F1;
|
||||
0F2 : F2F2;
|
||||
0F3 : F3F3;
|
||||
0F4 : F4F4;
|
||||
0F5 : F5F5;
|
||||
0F6 : F6F6;
|
||||
0F7 : 7F7F;
|
||||
0F8 : F8F8;
|
||||
0F9 : F9F9;
|
||||
0FA : FAFA;
|
||||
0FB : FBFB;
|
||||
0FC : FCFC;
|
||||
0FD : FDFD;
|
||||
0FE : FEFE;
|
||||
0FF : 0F0F;
|
||||
[100..1FF] : FFFF;
|
||||
END;
|
||||
@ -1,25 +0,0 @@
|
||||
-- Copyright (C) 1991-2013 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
-- Quartus II generated Memory Initialization File (.mif)
|
||||
|
||||
WIDTH=16;
|
||||
DEPTH=512;
|
||||
|
||||
ADDRESS_RADIX=HEX;
|
||||
DATA_RADIX=HEX;
|
||||
|
||||
CONTENT BEGIN
|
||||
[000..1FF] : FFFF;
|
||||
END;
|
||||
@ -1,30 +0,0 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 22:58:44 May 05, 2020
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.0"
|
||||
DATE = "22:58:44 May 05, 2020"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "RAM2E"
|
||||
@ -1,259 +0,0 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2013 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 32-bit
|
||||
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
|
||||
# Date created = 22:58:44 May 05, 2020
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# RAM2E_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
set_global_assignment -name FAMILY "MAX II"
|
||||
set_global_assignment -name DEVICE EPM240T100C5
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:58:44 MAY 05, 2020"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
|
||||
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
|
||||
set_global_assignment -name VERILOG_FILE RAM2E.v
|
||||
set_global_assignment -name SDC_FILE constraints.sdc
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
|
||||
set_global_assignment -name SAFE_STATE_MACHINE ON
|
||||
set_global_assignment -name PARALLEL_SYNTHESIS OFF
|
||||
set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
|
||||
set_global_assignment -name MIF_FILE RAM2E.mif
|
||||
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF
|
||||
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
|
||||
|
||||
set_location_assignment PIN_12 -to C14M
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C14M
|
||||
|
||||
set_location_assignment PIN_37 -to PHI1
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI1
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to PHI1
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI1
|
||||
|
||||
set_location_assignment PIN_51 -to nWE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE
|
||||
|
||||
set_location_assignment PIN_28 -to nEN80
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nEN80
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nEN80
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80
|
||||
|
||||
set_location_assignment PIN_33 -to nWE80
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80
|
||||
|
||||
set_location_assignment PIN_52 -to nC07X
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nC07X
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nC07X
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nC07X
|
||||
|
||||
set_location_assignment PIN_56 -to Ain[0]
|
||||
set_location_assignment PIN_54 -to Ain[1]
|
||||
set_location_assignment PIN_43 -to Ain[2]
|
||||
set_location_assignment PIN_47 -to Ain[3]
|
||||
set_location_assignment PIN_44 -to Ain[4]
|
||||
set_location_assignment PIN_34 -to Ain[5]
|
||||
set_location_assignment PIN_39 -to Ain[6]
|
||||
set_location_assignment PIN_53 -to Ain[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Ain
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Ain
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Ain
|
||||
|
||||
set_location_assignment PIN_38 -to Din[0]
|
||||
set_location_assignment PIN_40 -to Din[1]
|
||||
set_location_assignment PIN_42 -to Din[2]
|
||||
set_location_assignment PIN_41 -to Din[3]
|
||||
set_location_assignment PIN_48 -to Din[4]
|
||||
set_location_assignment PIN_49 -to Din[5]
|
||||
set_location_assignment PIN_36 -to Din[6]
|
||||
set_location_assignment PIN_35 -to Din[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Din
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Din
|
||||
|
||||
set_location_assignment PIN_55 -to nDOE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE
|
||||
|
||||
set_location_assignment PIN_77 -to Dout[0]
|
||||
set_location_assignment PIN_76 -to Dout[1]
|
||||
set_location_assignment PIN_74 -to Dout[2]
|
||||
set_location_assignment PIN_75 -to Dout[3]
|
||||
set_location_assignment PIN_73 -to Dout[4]
|
||||
set_location_assignment PIN_72 -to Dout[5]
|
||||
set_location_assignment PIN_84 -to Dout[6]
|
||||
set_location_assignment PIN_85 -to Dout[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout
|
||||
|
||||
set_location_assignment PIN_50 -to nVOE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE
|
||||
|
||||
set_location_assignment PIN_70 -to Vout[0]
|
||||
set_location_assignment PIN_67 -to Vout[1]
|
||||
set_location_assignment PIN_69 -to Vout[2]
|
||||
set_location_assignment PIN_62 -to Vout[3]
|
||||
set_location_assignment PIN_71 -to Vout[4]
|
||||
set_location_assignment PIN_68 -to Vout[5]
|
||||
set_location_assignment PIN_58 -to Vout[6]
|
||||
set_location_assignment PIN_57 -to Vout[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Vout
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Vout
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout
|
||||
|
||||
set_location_assignment PIN_4 -to CKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE
|
||||
|
||||
set_location_assignment PIN_8 -to nCS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS
|
||||
|
||||
set_location_assignment PIN_2 -to nRWE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE
|
||||
|
||||
set_location_assignment PIN_5 -to nRAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS
|
||||
|
||||
set_location_assignment PIN_3 -to nCAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS
|
||||
|
||||
set_location_assignment PIN_6 -to BA[0]
|
||||
set_location_assignment PIN_14 -to BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BA
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to BA
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to BA
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA
|
||||
|
||||
set_location_assignment PIN_18 -to RA[0]
|
||||
set_location_assignment PIN_20 -to RA[1]
|
||||
set_location_assignment PIN_30 -to RA[2]
|
||||
set_location_assignment PIN_27 -to RA[3]
|
||||
set_location_assignment PIN_26 -to RA[4]
|
||||
set_location_assignment PIN_29 -to RA[5]
|
||||
set_location_assignment PIN_21 -to RA[6]
|
||||
set_location_assignment PIN_19 -to RA[7]
|
||||
set_location_assignment PIN_17 -to RA[8]
|
||||
set_location_assignment PIN_15 -to RA[9]
|
||||
set_location_assignment PIN_16 -to RA[10]
|
||||
set_location_assignment PIN_7 -to RA[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to RA
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA
|
||||
|
||||
set_location_assignment PIN_100 -to DQMH
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQMH
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH
|
||||
|
||||
set_location_assignment PIN_98 -to DQML
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQML
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQML
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML
|
||||
|
||||
set_location_assignment PIN_97 -to RD[0]
|
||||
set_location_assignment PIN_90 -to RD[1]
|
||||
set_location_assignment PIN_99 -to RD[2]
|
||||
set_location_assignment PIN_89 -to RD[3]
|
||||
set_location_assignment PIN_91 -to RD[4]
|
||||
set_location_assignment PIN_92 -to RD[5]
|
||||
set_location_assignment PIN_95 -to RD[6]
|
||||
set_location_assignment PIN_96 -to RD[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD
|
||||
set_instance_assignment -name SLOW_SLEW_RATE ON -to RD
|
||||
set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD
|
||||
set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD
|
||||
|
||||
set_global_assignment -name QIP_FILE UFM.qip
|
||||
Binary file not shown.
@ -1,636 +0,0 @@
|
||||
module RAM2E(C14M, PHI1,
|
||||
nWE, nWE80, nEN80, nC07X,
|
||||
Ain, Din, Dout, nDOE, Vout, nVOE,
|
||||
CKE, nCS, nRAS, nCAS, nRWE,
|
||||
BA, RA, RD, DQML, DQMH);
|
||||
|
||||
/* Clocks */
|
||||
input C14M, PHI1;
|
||||
|
||||
/* Control inputs */
|
||||
input nWE, nWE80, nEN80, nC07X;
|
||||
|
||||
/* Delay for EN80 signal */
|
||||
//output DelayOut = 1'b0;
|
||||
//input DelayIn;
|
||||
wire EN80 = ~nEN80;
|
||||
|
||||
/* Address Bus */
|
||||
input [7:0] Ain; // Multiplexed DRAM address input
|
||||
|
||||
/* 6502 Data Bus */
|
||||
input [7:0] Din; // 6502 data bus inputs
|
||||
reg DOEEN = 0; // 6502 data bus output enable from state machine
|
||||
output nDOE = ~(EN80 & nWE & DOEEN); // 6502 data bus output enable
|
||||
output reg [7:0] Dout; // 6502 data Bus output
|
||||
|
||||
/* Video Data Bus */
|
||||
output nVOE = ~(~PHI1); /// Video data bus output enable
|
||||
output reg [7:0] Vout; // Video data bus
|
||||
|
||||
/* SDRAM */
|
||||
output reg CKE = 0;
|
||||
output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1;
|
||||
output reg [1:0] BA;
|
||||
output reg [11:0] RA;
|
||||
output reg DQML = 1, DQMH = 1;
|
||||
wire RDOE = EN80 & ~nWE80;
|
||||
inout [7:0] RD = RDOE ? Din[7:0] : 8'bZ;
|
||||
|
||||
/* RAMWorks Bank Register and Capacity Mask */
|
||||
reg [7:0] RWBank = 0; // RAMWorks bank register
|
||||
reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask
|
||||
reg RWSel = 0; // RAMWorks bank register select
|
||||
reg RWMaskSet = 0; // RAMWorks Mask register set flag
|
||||
reg SetRWBankFF = 0; // Causes RWBank to be zeroed next RWSel access
|
||||
|
||||
/* Command Sequence Detector */
|
||||
reg [2:0] CS = 0; // Command sequence state
|
||||
reg [2:0] CmdTout = 0; // Command sequence timeout
|
||||
|
||||
/* UFM Interface */
|
||||
reg [15:8] UFMD = 0; // *Parallel* UFM data register
|
||||
reg ARCLK = 0; // UFM address register clock
|
||||
// UFM address register data input tied to 0
|
||||
reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment
|
||||
reg DRCLK = 0; // UFM data register clock
|
||||
reg DRDIn = 0; // UFM data register input
|
||||
reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address
|
||||
reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy
|
||||
reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy
|
||||
wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous
|
||||
wire RTPBusy; // 1 if real-time programming in progress. Asynchronous
|
||||
wire DRDOut; // UFM data output
|
||||
// UFM oscillator always enabled
|
||||
wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz)
|
||||
UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V)
|
||||
.arclk (ARCLK),
|
||||
.ardin (1'b0),
|
||||
.arshft (ARShift),
|
||||
.drclk (DRCLK),
|
||||
.drdin (DRDIn),
|
||||
.drshft (DRShift),
|
||||
.erase (UFMErase),
|
||||
.oscena (1'b1),
|
||||
.program (UFMProgram),
|
||||
.busy (UFMBusy),
|
||||
.drdout (DRDOut),
|
||||
.osc (UFMOsc),
|
||||
.rtpbusy (RTPBusy));
|
||||
reg UFMBusyReg = 0; // UFMBusy registered to sync with C14M
|
||||
reg RTPBusyReg = 0; // RTPBusy registered to sync with C14M
|
||||
|
||||
/* UFM State & User Command Triggers */
|
||||
reg UFMInitDone = 0; // 1 if UFM initialization finished
|
||||
reg UFMReqErase = 0; // 1 if UFM requires erase
|
||||
reg UFMBitbang = 0; // Set by user command. Loads UFM outputs next RWSel
|
||||
reg UFMPrgmEN = 0; // Set by user command. Programs UFM
|
||||
reg UFMEraseEN = 0; // Set by user command. Erases UFM
|
||||
reg DRCLKPulse = 0; // Set by user command. Causes DRCLK pulse next C14M
|
||||
|
||||
/* State Counters */
|
||||
reg PHI1reg = 0; // Saved PHI1 at last rising clock edge
|
||||
reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15
|
||||
reg [15:0] FS = 0; // Fast state counter
|
||||
reg [3:0] S = 0; // IIe State counter
|
||||
|
||||
/* State Counters */
|
||||
always @(posedge C14M) begin
|
||||
// Increment fast state counter
|
||||
FS <= FS+1;
|
||||
// Synchronize Apple state counter to S1 when just entering PHI1
|
||||
PHI1reg <= PHI1; // Save old PHI1
|
||||
S <= (PHI1 & ~PHI1reg & Ready) ? 4'h1 :
|
||||
S==4'h0 ? 4'h0 :
|
||||
S==4'hF ? 4'hF : S+1;
|
||||
end
|
||||
|
||||
/* UFM Control */
|
||||
always @(posedge C14M) begin
|
||||
// Synchronize asynchronous UFM signals
|
||||
UFMBusyReg <= UFMBusy;
|
||||
RTPBusyReg <= RTPBusy;
|
||||
|
||||
if (S==4'h0) begin
|
||||
if ((FS[15:13]==3'b101) | (FS[15:13]==3'b111 & UFMReqErase)) begin
|
||||
// In states AXXX-BXXX and also EXXX-FXXX if erase/wrap req'd
|
||||
// shift in 0's to address register
|
||||
ARCLK <= FS[0]; // Clock address register
|
||||
DRCLK <= 1'b0; // Don't clock data register
|
||||
ARShift <= 1'b1; // Shift address registers
|
||||
DRDIn <= 1'b0; // Don't care DRDIn
|
||||
DRShift <= 1'b0; // Don't care DRDShift
|
||||
end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4:1]==4'h4) begin
|
||||
// In states CXXX-DXXX (substep 4)
|
||||
// Xfer to data reg (repeat 256x 1x)
|
||||
ARCLK <= 1'b0; // Don't clock address register
|
||||
DRCLK <= FS[0]; // Clock data register
|
||||
ARShift <= 1'b0; // Don't care ARShift
|
||||
DRDIn <= 1'b0; // Don't care DRDIn
|
||||
DRShift <= 1'b0; // Don't care DRShift
|
||||
end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4]==1'b1) begin
|
||||
// In states CXXX-DXXX (substeps 8-F)
|
||||
// Save UFM D15-8, shift out D14-7 (repeat 256x 8x)
|
||||
DRCLK <= FS[0]; // Clock data register
|
||||
ARShift <= 1'b0; // ARShift is 0 because we want to increment
|
||||
DRDIn <= 1'b0; // Don't care what to shift into data register
|
||||
DRShift <= 1'b1; // Shift data register
|
||||
// Shift into UFMD
|
||||
if (FS[0]) UFMD[15:8] <= {UFMD[14:8], DRDOut};
|
||||
|
||||
// Compare and store mask
|
||||
if (FS[4:1]==4'hF) begin
|
||||
ARCLK <= FS[0]; // Clock address register to increment
|
||||
// If byte is erased (0xFF, i.e. all 1's, is erased)...
|
||||
if (UFMD[14:8]==7'b1111111 & DRDOut==1'b1) begin
|
||||
// Current UFM address is where we want to store
|
||||
UFMInitDone <= 1'b1; // Quit iterating
|
||||
// Otherwise byte is valid setting (i.e. some bit is 0)...
|
||||
end else begin
|
||||
// Set RWMask, but if saved mask is 0x80, store ~0xFF
|
||||
if (UFMD[14:8]==7'b1000000 & DRDOut==1'b0) begin
|
||||
RWMask[7:0] <= {1'b1, ~7'h7F};
|
||||
end else RWMask[7:0] <= {UFMD[14], ~UFMD[13:8], ~DRDOut};
|
||||
// If last byte in sector...
|
||||
if (FS[12:5]==8'hFF) begin
|
||||
UFMReqErase <= 1'b1; // Mark need to erase
|
||||
end
|
||||
end
|
||||
end else ARCLK <= 1'b0; // Don't clock address register
|
||||
end else begin
|
||||
ARCLK <= 1'b0;
|
||||
DRCLK <= 1'b0;
|
||||
ARShift <= 1'b0;
|
||||
DRDIn <= 1'b0;
|
||||
DRShift <= 1'b0;
|
||||
end
|
||||
|
||||
// Don't erase or program UFM during initialization
|
||||
UFMErase <= 1'b0;
|
||||
UFMProgram <= 1'b0;
|
||||
// Keep DRCLK pulse control disabled during init
|
||||
DRCLKPulse <= 1'b0;
|
||||
end else begin
|
||||
// Can only shift UFM data register now
|
||||
ARCLK <= 1'b0;
|
||||
ARShift <= 1'b0;
|
||||
DRShift <= 1'b1;
|
||||
|
||||
// UFM bitbang control
|
||||
if (UFMBitbang & CS==3'h7 & RWSel & S==4'hC) begin
|
||||
DRDIn <= Din[6];
|
||||
DRCLKPulse <= Din[7];
|
||||
DRCLK <= 1'b0;
|
||||
end else begin
|
||||
DRCLKPulse <= 1'b0;
|
||||
DRCLK <= DRCLKPulse;
|
||||
end
|
||||
|
||||
// Set capacity mask
|
||||
if (RWMaskSet & RWSel & S==4'hC) RWMask[7:0] <= {Din[7], ~Din[6:0]};
|
||||
|
||||
// UFM programming sequence
|
||||
if (UFMPrgmEN | UFMEraseEN) begin
|
||||
if (~UFMBusyReg & ~RTPBusyReg) begin
|
||||
if (UFMReqErase | UFMEraseEN) UFMErase <= 1'b1;
|
||||
else if (UFMPrgmEN) UFMProgram <= 1'b1;
|
||||
end else if (UFMBusyReg) UFMReqErase <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
/* SDRAM Control */
|
||||
always @(posedge C14M) begin
|
||||
if (S==4'h0) begin
|
||||
// SDRAM initialization
|
||||
if (FS[15:0]==16'hFFC0) begin
|
||||
// Precharge All
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b0;
|
||||
RA[10] <= 1'b1; // "all"
|
||||
end else if (FS[15:4]==16'hFFD & FS[0]==1'b0) begin // Repeat 8x
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end else if (FS[15:0]==16'hFFE8) begin
|
||||
// Set Mode Register
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b0;
|
||||
RA[10] <= 1'b0; // Reserved in mode register
|
||||
end else if (FS[15:4]==12'hFFF & FS[0]==1'b0) begin // Repeat 8x
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end else begin // Otherwise send no-op
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
RA[10] <= 1'b0;
|
||||
end
|
||||
// Enable SDRAM clock after 65,280 cycles (~4.56ms)
|
||||
CKE <= FS[15:8] == 8'hFF;
|
||||
|
||||
// Mode register contents
|
||||
BA[1:0] <= 2'b00; // Reserved
|
||||
RA[11] <= 1'b0; // Reserved
|
||||
// RA[10] set above ^
|
||||
RA[9] <= 1'b1; // "1" for single write mode
|
||||
RA[8] <= 1'b0; // Reserved
|
||||
RA[7] <= 1'b0; // "0" for not test mode
|
||||
RA[6:4] <= 3'b010; // "2" for CAS latency 2
|
||||
RA[3] <= 1'b0; // "0" for sequential burst (not used)
|
||||
RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst)
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
|
||||
// Begin normal operation after 128k init cycles (~9.15ms)
|
||||
if (FS == 16'hFFFF) Ready <= 1'b1;
|
||||
end else if (S==4'h1) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h2) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// Activate
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank 0, high-order row address is 0
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Row address is as previously latched
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h3) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// Read
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank 0, RA[11,9:8] don't care
|
||||
BA <= 2'b00;
|
||||
RA[11] <= 1'b0;
|
||||
RA[10] <= 1'b1; // (A10 set to auto-precharge)
|
||||
RA[9] <= 1'b0;
|
||||
RA[8] <= 1'b0;
|
||||
// Latch column address for read command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Read low byte (high byte is +4MB in ramworks)
|
||||
DQML <= 1'b0;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h4) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h5) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h6) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
if (FS[5:4]==0) begin
|
||||
// Auto-refresh
|
||||
nCS <= 1'b0;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= 1'b1;
|
||||
end else begin
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
end
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h7) begin
|
||||
// Enable clock
|
||||
CKE <= 1'b1;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
// Latch row address for activate command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h8) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// Activate if '245 output enabled
|
||||
nCS <= nEN80;
|
||||
nRAS <= 1'b0;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// SDRAM bank, RA[11:8] determine by RamWorks bank
|
||||
BA <= RWBank[5:4];
|
||||
RA[11:8] <= RWBank[3:0];
|
||||
// Row address is as previously latched
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'h9) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// Read/Write if '245 output enabled
|
||||
nCS <= nEN80;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b0;
|
||||
nRWE <= nWE80;
|
||||
|
||||
// SDRAM bank still determined by RamWorks, RA[11,9:8] don't care
|
||||
BA <= RWBank[5:4];
|
||||
RA[11] <= 1'b0;
|
||||
RA[10] <= 1'b1; // (A10 set to auto-precharge)
|
||||
RA[9] <= 1'b0;
|
||||
RA[8] <= RWBank[7];
|
||||
// Latch column address for R/W command
|
||||
RA[7:0] <= Ain[7:0];
|
||||
|
||||
// Latch RAMWorks low nybble write select using old row address
|
||||
RWSel <= RA[0] & ~RA[3] & ~nWE & ~nC07X;
|
||||
|
||||
// Mask according to RAMWorks bank (high byte is +4MB)
|
||||
DQML <= RWBank[6];
|
||||
DQMH <= ~RWBank[6];
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'hA) begin
|
||||
// Enable clock if '245 output enabled
|
||||
CKE <= EN80;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Inhibit data bus output
|
||||
DOEEN <= 1'b0;
|
||||
end else if (S==4'hB) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
end else if (S==4'hC) begin
|
||||
// Disable clock
|
||||
CKE <= 1'b0;
|
||||
|
||||
// NOP
|
||||
nCS <= 1'b1;
|
||||
nRAS <= 1'b1;
|
||||
nCAS <= 1'b1;
|
||||
nRWE <= 1'b1;
|
||||
|
||||
// Don't care bank, RA[11:8]
|
||||
BA <= 2'b00;
|
||||
RA[11:8] <= 4'b0000;
|
||||
|
||||
// Mask everything
|
||||
DQML <= 1'b1;
|
||||
DQMH <= 1'b1;
|
||||
|
||||
// Enable data bus output
|
||||
DOEEN <= 1'b1;
|
||||
|
||||
// RAMWorks Bank Register Select
|
||||
if (RWSel) begin
|
||||
// Latch RAMWorks bank if accessed
|
||||
if (SetRWBankFF) RWBank <= 8'hFF;
|
||||
else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]};
|
||||
|
||||
// Recognize command sequence and advance CS state
|
||||
if ((CS==3'h0 & Din[7:0]==8'hFF) |
|
||||
(CS==3'h1 & Din[7:0]==8'h00) |
|
||||
(CS==3'h2 & Din[7:0]==8'h55) |
|
||||
(CS==3'h3 & Din[7:0]==8'hAA) |
|
||||
(CS==3'h4 & Din[7:0]==8'hC1) |
|
||||
(CS==3'h5 & Din[7:0]==< | ||||