diff --git a/cpld/RAM2E.qws b/cpld/RAM2E.qws index 6cdca8d..0d77c12 100644 Binary files a/cpld/RAM2E.qws and b/cpld/RAM2E.qws differ diff --git a/cpld/RAM2E.v b/cpld/RAM2E.v index 942b793..47dfdbb 100644 --- a/cpld/RAM2E.v +++ b/cpld/RAM2E.v @@ -17,7 +17,6 @@ module RAM2E(C14M, PHI1, /* Address Bus */ input [7:0] Ain; // Multiplexed DRAM address input - reg [7:0] Areg; // Address saved for later /* 6502 Data Bus */ input [7:0] Din; // 6502 data bus inputs @@ -264,8 +263,8 @@ module RAM2E(C14M, PHI1, // Begin normal operation after 128k init cycles (~9.15ms) if (FS == 16'hFFFF) Ready <= 1'b1; end else if (S==4'h1) begin - // Disable clock - CKE <= 1'b0; + // Enable clock + CKE <= 1'b1; // NOP nCS <= 1'b1; @@ -284,48 +283,6 @@ module RAM2E(C14M, PHI1, // Inhibit data bus output DOEEN <= 1'b0; end else if (S==4'h2) begin - // Disable clock - CKE <= 1'b0; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // SDRAM bank 0, high-order row address is 0 - BA <= 2'b00; - RA[11:8] <= 4'b0000; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'h3) begin - // Enable clock - CKE <= 1'b1; - - // NOP - nCS <= 1'b1; - nRAS <= 1'b1; - nCAS <= 1'b1; - nRWE <= 1'b1; - - // Don't care bank, RA[11:8] - BA <= 2'b00; - RA[11:8] <= 4'b0000; - // Latch column address for read command - Areg[7:0] <= Ain[7:0]; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; - - // Inhibit data bus output - DOEEN <= 1'b0; - end else if (S==4'h4) begin // Enable clock CKE <= 1'b1; @@ -335,7 +292,7 @@ module RAM2E(C14M, PHI1, nCAS <= 1'b1; nRWE <= 1'b1; - // Don't care bank, RA[11:8] + // SDRAM bank 0, high-order row address is 0 BA <= 2'b00; RA[11:8] <= 4'b0000; // Row address is as previously latched @@ -346,7 +303,7 @@ module RAM2E(C14M, PHI1, // Inhibit data bus output DOEEN <= 1'b0; - end else if (S==4'h5) begin + end else if (S==4'h3) begin // Enable clock CKE <= 1'b1; @@ -362,12 +319,8 @@ module RAM2E(C14M, PHI1, RA[10] <= 1'b1; // (A10 set to auto-precharge) RA[9] <= 1'b0; RA[8] <= 1'b0; - // Output previously latched column address - RA[7:0] <= Areg[7:0]; - - // Mask everything - DQML <= 1'b1; - DQMH <= 1'b1; + // Latch column address for read command + RA[7:0] <= Ain[7:0]; // Read low byte (high byte is +4MB in ramworks) DQML <= 1'b0; @@ -375,7 +328,7 @@ module RAM2E(C14M, PHI1, // Inhibit data bus output DOEEN <= 1'b0; - end else if (S==4'h6) begin + end else if (S==4'h4) begin // Enable clock CKE <= 1'b1; @@ -395,7 +348,27 @@ module RAM2E(C14M, PHI1, // Inhibit data bus output DOEEN <= 1'b0; - end else if (S==4'h7) begin + end else if (S==4'h5) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h6) begin // Enable clock CKE <= 1'b1; @@ -413,6 +386,26 @@ module RAM2E(C14M, PHI1, nRWE <= 1'b1; end + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h7) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + // Don't care bank, RA[11:8] BA <= 2'b00; RA[11:8] <= 4'b0000; @@ -637,7 +630,7 @@ module RAM2E(C14M, PHI1, end always @(negedge C14M) begin // Latch video and read data outputs - if (S==4'h8) Vout[7:0] <= RD[7:0]; + if (S==4'h6) Vout[7:0] <= RD[7:0]; if (S==4'hC) Dout[7:0] <= RD[7:0]; end endmodule diff --git a/cpld/db/RAM2E.(0).cnf.cdb b/cpld/db/RAM2E.(0).cnf.cdb index bac185e..4187f8c 100755 Binary files a/cpld/db/RAM2E.(0).cnf.cdb and b/cpld/db/RAM2E.(0).cnf.cdb differ diff --git a/cpld/db/RAM2E.(0).cnf.hdb b/cpld/db/RAM2E.(0).cnf.hdb index c417831..0728203 100755 Binary files a/cpld/db/RAM2E.(0).cnf.hdb and b/cpld/db/RAM2E.(0).cnf.hdb differ diff --git a/cpld/db/RAM2E.asm.qmsg b/cpld/db/RAM2E.asm.qmsg index 23c4a84..b30f19f 100755 --- a/cpld/db/RAM2E.asm.qmsg +++ b/cpld/db/RAM2E.asm.qmsg @@ -1,6 +1,6 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600299289286 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600299289286 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 19:34:49 2020 " "Processing started: Wed Sep 16 19:34:49 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600299289286 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1600299289286 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1600299289286 ""} -{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1600299289446 ""} -{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1600299289456 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4524 " "Peak virtual memory: 4524 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600299289606 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 19:34:49 2020 " "Processing ended: Wed Sep 16 19:34:49 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600299289606 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600299289606 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600299289606 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1600299289606 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600301681638 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301681638 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:41 2020 " "Processing started: Wed Sep 16 20:14:41 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301681638 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1600301681638 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1600301681638 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1600301681798 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1600301681798 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4524 " "Peak virtual memory: 4524 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301681918 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:41 2020 " "Processing ended: Wed Sep 16 20:14:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301681918 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301681918 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301681918 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1600301681918 ""} diff --git a/cpld/db/RAM2E.asm.rdb b/cpld/db/RAM2E.asm.rdb index 783ba95..9584e4f 100755 Binary files a/cpld/db/RAM2E.asm.rdb and b/cpld/db/RAM2E.asm.rdb differ diff --git a/cpld/db/RAM2E.asm_labs.ddb b/cpld/db/RAM2E.asm_labs.ddb index 4130668..0bb936d 100755 Binary files a/cpld/db/RAM2E.asm_labs.ddb and b/cpld/db/RAM2E.asm_labs.ddb differ diff --git a/cpld/db/RAM2E.cmp.cdb b/cpld/db/RAM2E.cmp.cdb index 892e94d..c63d6f9 100755 Binary files a/cpld/db/RAM2E.cmp.cdb and b/cpld/db/RAM2E.cmp.cdb differ diff --git a/cpld/db/RAM2E.cmp.hdb b/cpld/db/RAM2E.cmp.hdb index 6f823f9..b262b4c 100755 Binary files a/cpld/db/RAM2E.cmp.hdb and b/cpld/db/RAM2E.cmp.hdb differ diff --git a/cpld/db/RAM2E.cmp.idb b/cpld/db/RAM2E.cmp.idb index f64c41a..7efc515 100755 Binary files a/cpld/db/RAM2E.cmp.idb and b/cpld/db/RAM2E.cmp.idb differ diff --git a/cpld/db/RAM2E.cmp.rdb b/cpld/db/RAM2E.cmp.rdb index 0842792..a3ec835 100755 Binary files a/cpld/db/RAM2E.cmp.rdb and b/cpld/db/RAM2E.cmp.rdb differ diff --git a/cpld/db/RAM2E.cmp0.ddb b/cpld/db/RAM2E.cmp0.ddb index 22996a7..3aa51cb 100755 Binary files a/cpld/db/RAM2E.cmp0.ddb and b/cpld/db/RAM2E.cmp0.ddb differ diff --git a/cpld/db/RAM2E.db_info b/cpld/db/RAM2E.db_info index 7a11d7e..5367950 100755 --- a/cpld/db/RAM2E.db_info +++ b/cpld/db/RAM2E.db_info @@ -1,3 +1,3 @@ Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition Version_Index = 302049280 -Creation_Time = Wed Sep 16 19:33:27 2020 +Creation_Time = Wed Sep 16 19:59:46 2020 diff --git a/cpld/db/RAM2E.fit.qmsg b/cpld/db/RAM2E.fit.qmsg index 345d23c..c9e12d8 100755 --- a/cpld/db/RAM2E.fit.qmsg +++ b/cpld/db/RAM2E.fit.qmsg @@ -1,39 +1,38 @@ -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1600299287061 ""} -{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1600299287063 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600299287091 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600299287091 ""} -{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1600299287121 ""} -{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1600299287126 ""} -{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600299287188 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1600299287188 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1600299287248 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600299287250 "|RAM2E|DRCLK"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600299287250 "|RAM2E|ARCLK"} -{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1600299287251 ""} -{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600299287252 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600299287252 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600299287252 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1600299287252 ""} -{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600299287254 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600299287254 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600299287256 ""} -{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1600299287261 ""} -{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600299287261 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1600299287262 ""} -{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1600299287275 ""} -{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1600299287275 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1600299287290 ""} -{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1600299287290 ""} -{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1600299287290 ""} -{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1600299287290 ""} -{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600299287310 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1600299287380 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600299287510 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1600299287520 ""} -{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1600299287742 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600299287742 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1600299287762 ""} -{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "2e+01 ns 1.2% " "2e+01 ns of routing delay (approximately 1.2% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1600299287883 ""} -{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1600299287903 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1600299287903 ""} -{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600299288022 ""} -{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1600299288022 ""} -{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600299288022 ""} -{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1600299288047 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1600299288095 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4767 " "Peak virtual memory: 4767 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600299288155 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 19:34:48 2020 " "Processing ended: Wed Sep 16 19:34:48 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600299288155 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600299288155 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600299288155 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1600299288155 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1600301679744 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1600301679744 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600301679774 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600301679774 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1600301679804 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1600301679814 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1600301679864 ""} +{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1600301679924 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600301679934 "|RAM2E|DRCLK"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600301679934 "|RAM2E|ARCLK"} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1600301679934 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301679934 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301679934 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301679934 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1600301679934 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600301679934 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600301679934 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600301679934 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1600301679944 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600301679944 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1600301679944 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1600301679954 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1600301679954 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1600301679974 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1600301679974 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1600301679974 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1600301679974 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301679994 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1600301680064 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301680194 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1600301680194 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1600301680404 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301680404 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1600301680424 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1600301680564 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1600301680564 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301680682 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1600301680690 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301680690 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1600301680712 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1600301680752 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4767 " "Peak virtual memory: 4767 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301680812 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:40 2020 " "Processing ended: Wed Sep 16 20:14:40 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301680812 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301680812 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301680812 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1600301680812 ""} diff --git a/cpld/db/RAM2E.hier_info b/cpld/db/RAM2E.hier_info index 1a11018..cba7dd3 100755 --- a/cpld/db/RAM2E.hier_info +++ b/cpld/db/RAM2E.hier_info @@ -19,14 +19,6 @@ C14M => RWBank[5].CLK C14M => RWBank[6].CLK C14M => RWBank[7].CLK C14M => RWSel.CLK -C14M => Areg[0].CLK -C14M => Areg[1].CLK -C14M => Areg[2].CLK -C14M => Areg[3].CLK -C14M => Areg[4].CLK -C14M => Areg[5].CLK -C14M => Areg[6].CLK -C14M => Areg[7].CLK C14M => Ready.CLK C14M => DOEEN.CLK C14M => DQMH~reg0.CLK @@ -133,42 +125,42 @@ Ain[0] => RA.DATAB Ain[0] => RA.DATAB Ain[0] => RA.DATAB Ain[0] => RA.DATAB -Ain[0] => Areg.DATAB +Ain[0] => RA.DATAB +Ain[1] => RA.DATAB Ain[1] => RA.DATAB Ain[1] => RA.DATAB Ain[1] => RA.DATAB Ain[1] => RA.DATAB -Ain[1] => Areg.DATAB Ain[2] => RA.DATAB Ain[2] => RA.DATAB Ain[2] => RA.DATAB Ain[2] => RA.DATAB -Ain[2] => Areg.DATAB +Ain[2] => RA.DATAB +Ain[3] => RA.DATAB Ain[3] => RA.DATAB Ain[3] => RA.DATAB Ain[3] => RA.DATAB Ain[3] => RA.DATAB -Ain[3] => Areg.DATAB Ain[4] => RA.DATAB Ain[4] => RA.DATAB Ain[4] => RA.DATAB Ain[4] => RA.DATAB -Ain[4] => Areg.DATAB +Ain[4] => RA.DATAB +Ain[5] => RA.DATAB Ain[5] => RA.DATAB Ain[5] => RA.DATAB Ain[5] => RA.DATAB Ain[5] => RA.DATAB -Ain[5] => Areg.DATAB Ain[6] => RA.DATAB Ain[6] => RA.DATAB Ain[6] => RA.DATAB Ain[6] => RA.DATAB -Ain[6] => Areg.DATAB +Ain[6] => RA.DATAB +Ain[7] => RA.DATAB Ain[7] => RA.DATAB Ain[7] => RA.DATAB Ain[7] => RA.DATAB Ain[7] => RA.DATAB -Ain[7] => Areg.DATAB Din[0] => RWBank.IN1 Din[0] => RD[0].DATAIN Din[0] => RWMask.DATAB diff --git a/cpld/db/RAM2E.hif b/cpld/db/RAM2E.hif index f1dab0e..584c4e4 100755 Binary files a/cpld/db/RAM2E.hif and b/cpld/db/RAM2E.hif differ diff --git a/cpld/db/RAM2E.map.cdb b/cpld/db/RAM2E.map.cdb index e7a4d77..78c1b51 100755 Binary files a/cpld/db/RAM2E.map.cdb and b/cpld/db/RAM2E.map.cdb differ diff --git a/cpld/db/RAM2E.map.hdb b/cpld/db/RAM2E.map.hdb index d7aa86f..dcb1aaa 100755 Binary files a/cpld/db/RAM2E.map.hdb and b/cpld/db/RAM2E.map.hdb differ diff --git a/cpld/db/RAM2E.map.qmsg b/cpld/db/RAM2E.map.qmsg index abc2600..c333a7d 100755 --- a/cpld/db/RAM2E.map.qmsg +++ b/cpld/db/RAM2E.map.qmsg @@ -1,19 +1,19 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600299285139 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600299285139 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 19:34:45 2020 " "Processing started: Wed Sep 16 19:34:45 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600299285139 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600299285139 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600299285139 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600299285319 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(39) " "Verilog HDL warning at RAM2E.v(39): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 39 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1600299285349 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600299285349 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600299285349 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600299285389 ""} -{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600299285389 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_e4r " "Found entity 1: UFM_altufm_none_e4r" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600299285389 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600299285389 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600299285389 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1600299285419 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(101) " "Verilog HDL assignment warning at RAM2E.v(101): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 101 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299285419 "|RAM2E"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(104) " "Verilog HDL assignment warning at RAM2E.v(104): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299285419 "|RAM2E"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(551) " "Verilog HDL assignment warning at RAM2E.v(551): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 551 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299285419 "|RAM2E"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(568) " "Verilog HDL assignment warning at RAM2E.v(568): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 568 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299285419 "|RAM2E"} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 80 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600299285429 ""} -{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_e4r UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component " "Elaborating entity \"UFM_altufm_none_e4r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component\"" { } { { "UFM.v" "UFM_altufm_none_e4r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600299285439 ""} -{ "Info" "ICUT_CUT_TM_SUMMARY" "278 " "Implemented 278 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1600299285969 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1600299285969 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1600299285969 ""} { "Info" "ICUT_CUT_TM_LCELLS" "208 " "Implemented 208 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1600299285969 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1600299285969 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1600299285969 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1600299286009 ""} -{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4575 " "Peak virtual memory: 4575 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600299286049 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 19:34:46 2020 " "Processing ended: Wed Sep 16 19:34:46 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600299286049 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600299286049 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600299286049 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600299286049 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600301677825 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301677825 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:37 2020 " "Processing started: Wed Sep 16 20:14:37 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301677825 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600301677825 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600301677825 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600301678014 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(38) " "Verilog HDL warning at RAM2E.v(38): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1600301678049 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301678049 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600301678049 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600301678093 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600301678093 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_e4r " "Found entity 1: UFM_altufm_none_e4r" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301678093 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301678093 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600301678093 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1600301678114 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(100) " "Verilog HDL assignment warning at RAM2E.v(100): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301678114 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(103) " "Verilog HDL assignment warning at RAM2E.v(103): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301678124 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(544) " "Verilog HDL assignment warning at RAM2E.v(544): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 544 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301678124 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(561) " "Verilog HDL assignment warning at RAM2E.v(561): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 561 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301678124 "|RAM2E"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 79 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600301678124 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_e4r UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component " "Elaborating entity \"UFM_altufm_none_e4r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component\"" { } { { "UFM.v" "UFM_altufm_none_e4r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600301678124 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "268 " "Implemented 268 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1600301678637 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1600301678637 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1600301678637 ""} { "Info" "ICUT_CUT_TM_LCELLS" "198 " "Implemented 198 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1600301678637 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1600301678637 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1600301678637 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1600301678679 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4568 " "Peak virtual memory: 4568 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301678723 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:38 2020 " "Processing ended: Wed Sep 16 20:14:38 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301678723 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301678723 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301678723 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600301678723 ""} diff --git a/cpld/db/RAM2E.map.rdb b/cpld/db/RAM2E.map.rdb index 541c185..f42c4f6 100755 Binary files a/cpld/db/RAM2E.map.rdb and b/cpld/db/RAM2E.map.rdb differ diff --git a/cpld/db/RAM2E.pre_map.hdb b/cpld/db/RAM2E.pre_map.hdb index ede3b57..52a496f 100755 Binary files a/cpld/db/RAM2E.pre_map.hdb and b/cpld/db/RAM2E.pre_map.hdb differ diff --git a/cpld/db/RAM2E.routing.rdb b/cpld/db/RAM2E.routing.rdb index 029b9a7..b9f2234 100755 Binary files a/cpld/db/RAM2E.routing.rdb and b/cpld/db/RAM2E.routing.rdb differ diff --git a/cpld/db/RAM2E.rtlv.hdb b/cpld/db/RAM2E.rtlv.hdb index fb26d6d..f1fc6e6 100755 Binary files a/cpld/db/RAM2E.rtlv.hdb and b/cpld/db/RAM2E.rtlv.hdb differ diff --git a/cpld/db/RAM2E.rtlv_sg.cdb b/cpld/db/RAM2E.rtlv_sg.cdb index e1d4e19..a0c5003 100755 Binary files a/cpld/db/RAM2E.rtlv_sg.cdb and b/cpld/db/RAM2E.rtlv_sg.cdb differ diff --git a/cpld/db/RAM2E.rtlv_sg_swap.cdb b/cpld/db/RAM2E.rtlv_sg_swap.cdb index 01b081d..adf349d 100755 Binary files a/cpld/db/RAM2E.rtlv_sg_swap.cdb and b/cpld/db/RAM2E.rtlv_sg_swap.cdb differ diff --git a/cpld/db/RAM2E.sgdiff.cdb b/cpld/db/RAM2E.sgdiff.cdb index 4e55e88..bbff58d 100755 Binary files a/cpld/db/RAM2E.sgdiff.cdb and b/cpld/db/RAM2E.sgdiff.cdb differ diff --git a/cpld/db/RAM2E.sgdiff.hdb b/cpld/db/RAM2E.sgdiff.hdb index 1a402da..8e99168 100755 Binary files a/cpld/db/RAM2E.sgdiff.hdb and b/cpld/db/RAM2E.sgdiff.hdb differ diff --git a/cpld/db/RAM2E.sta.qmsg b/cpld/db/RAM2E.sta.qmsg index 6adb96b..4c7af12 100755 --- a/cpld/db/RAM2E.sta.qmsg +++ b/cpld/db/RAM2E.sta.qmsg @@ -1,22 +1,22 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600299290603 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600299290603 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 19:34:50 2020 " "Processing started: Wed Sep 16 19:34:50 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600299290603 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600299290603 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600299290603 ""} -{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1600299290654 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600299290732 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600299290762 ""} -{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600299290762 ""} -{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1600299290792 ""} -{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1600299291033 ""} -{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1600299291181 ""} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600299291191 "|RAM2E|DRCLK"} -{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600299291191 "|RAM2E|ARCLK"} -{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1600299291191 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "setup 22.294 " "Worst-case setup slack is 22.294" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291221 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 22.294 0.000 C14M " " 22.294 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291221 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600299291221 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "hold 3.117 " "Worst-case hold slack is 3.117" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291231 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291231 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.117 0.000 C14M " " 3.117 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291231 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600299291231 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600299291241 ""} -{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600299291241 ""} -{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.581 " "Worst-case minimum pulse width slack is 34.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291251 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.581 0.000 C14M " " 34.581 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600299291251 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600299291251 ""} -{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1600299291301 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600299291321 ""} -{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600299291321 ""} -{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600299291391 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 19:34:51 2020 " "Processing ended: Wed Sep 16 19:34:51 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600299291391 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600299291391 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600299291391 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600299291391 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600301682828 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301682828 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:42 2020 " "Processing started: Wed Sep 16 20:14:42 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301682828 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600301682828 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600301682828 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1600301682880 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600301682962 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600301682991 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600301682991 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1600301683013 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1600301683244 ""} +{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1600301683302 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600301683312 "|RAM2E|DRCLK"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600301683312 "|RAM2E|ARCLK"} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1600301683312 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 21.694 " "Worst-case setup slack is 21.694" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683332 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683332 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 21.694 0.000 C14M " " 21.694 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683332 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301683332 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 3.144 " "Worst-case hold slack is 3.144" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683342 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683342 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.144 0.000 C14M " " 3.144 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683342 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301683342 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600301683342 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600301683352 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.581 " "Worst-case minimum pulse width slack is 34.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.581 0.000 C14M " " 34.581 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683362 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301683362 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1600301683402 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600301683432 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600301683432 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301683502 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:43 2020 " "Processing ended: Wed Sep 16 20:14:43 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301683502 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301683502 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301683502 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600301683502 ""} diff --git a/cpld/db/RAM2E.sta.rdb b/cpld/db/RAM2E.sta.rdb index 67b78e9..4760e3f 100755 Binary files a/cpld/db/RAM2E.sta.rdb and b/cpld/db/RAM2E.sta.rdb differ diff --git a/cpld/db/RAM2E.sta_cmp.5_slow.tdb b/cpld/db/RAM2E.sta_cmp.5_slow.tdb index 35a05e1..b772eb6 100755 Binary files a/cpld/db/RAM2E.sta_cmp.5_slow.tdb and b/cpld/db/RAM2E.sta_cmp.5_slow.tdb differ diff --git a/cpld/db/RAM2E.tmw_info b/cpld/db/RAM2E.tmw_info index e73b48d..590dceb 100644 --- a/cpld/db/RAM2E.tmw_info +++ b/cpld/db/RAM2E.tmw_info @@ -1,6 +1,6 @@ start_full_compilation:s:00:00:07 start_analysis_synthesis:s:00:00:02-start_full_compilation start_analysis_elaboration:s-start_full_compilation -start_fitter:s:00:00:03-start_full_compilation +start_fitter:s:00:00:02-start_full_compilation start_assembler:s:00:00:01-start_full_compilation -start_timing_analyzer:s:00:00:01-start_full_compilation +start_timing_analyzer:s:00:00:02-start_full_compilation diff --git a/cpld/db/RAM2E.vpr.ammdb b/cpld/db/RAM2E.vpr.ammdb index 61df104..20ebc98 100755 Binary files a/cpld/db/RAM2E.vpr.ammdb and b/cpld/db/RAM2E.vpr.ammdb differ diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat index 873c6d6..67c7583 100755 Binary files a/cpld/db/logic_util_heursitic.dat and b/cpld/db/logic_util_heursitic.dat differ diff --git a/cpld/db/prev_cmp_RAM2E.qmsg b/cpld/db/prev_cmp_RAM2E.qmsg index 5898656..a0de8fa 100755 --- a/cpld/db/prev_cmp_RAM2E.qmsg +++ b/cpld/db/prev_cmp_RAM2E.qmsg @@ -1,15 +1,93 @@ -{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600299211916 ""} -{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600299211916 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 19:33:31 2020 " "Processing started: Wed Sep 16 19:33:31 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600299211916 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600299211916 ""} -{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600299211916 ""} -{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600299212097 ""} -{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(39) " "Verilog HDL warning at RAM2E.v(39): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 39 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1600299212130 ""} -{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600299212132 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600299212132 ""} -{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1600299212161 ""} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(101) " "Verilog HDL assignment warning at RAM2E.v(101): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 101 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299212163 "|RAM2E"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(104) " "Verilog HDL assignment warning at RAM2E.v(104): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 104 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299212163 "|RAM2E"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(551) " "Verilog HDL assignment warning at RAM2E.v(551): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 551 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299212165 "|RAM2E"} -{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(568) " "Verilog HDL assignment warning at RAM2E.v(568): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 568 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600299212165 "|RAM2E"} -{ "Error" "ESGN_ENTITY_IS_MISSING" "UFM_inst UFM " "Node instance \"UFM_inst\" instantiates undefined entity \"UFM\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 80 0 0 } } } 0 12006 "Node instance \"%1!s!\" instantiates undefined entity \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600299212209 ""} -{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1600299212248 ""} -{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 5 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4566 " "Peak virtual memory: 4566 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600299212288 ""} { "Error" "EQEXE_END_BANNER_TIME" "Wed Sep 16 19:33:32 2020 " "Processing ended: Wed Sep 16 19:33:32 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600299212288 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600299212288 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600299212288 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600299212288 ""} -{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 3 s 5 s " "Quartus II Full Compilation was unsuccessful. 3 errors, 5 warnings" { } { } 0 293001 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600299212889 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600301660928 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301660928 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:20 2020 " "Processing started: Wed Sep 16 20:14:20 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301660928 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600301660928 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600301660928 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600301661124 ""} +{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(38) " "Verilog HDL warning at RAM2E.v(38): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1600301661165 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301661165 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600301661165 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600301661209 ""} +{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600301661209 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_e4r " "Found entity 1: UFM_altufm_none_e4r" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301661209 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301661209 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600301661209 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1600301661237 ""} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(100) " "Verilog HDL assignment warning at RAM2E.v(100): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301661239 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(103) " "Verilog HDL assignment warning at RAM2E.v(103): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301661239 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(544) " "Verilog HDL assignment warning at RAM2E.v(544): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 544 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301661239 "|RAM2E"} +{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(561) " "Verilog HDL assignment warning at RAM2E.v(561): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 561 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301661239 "|RAM2E"} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 79 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600301661280 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_e4r UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component " "Elaborating entity \"UFM_altufm_none_e4r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component\"" { } { { "UFM.v" "UFM_altufm_none_e4r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600301661280 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "268 " "Implemented 268 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1600301661771 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1600301661771 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1600301661771 ""} { "Info" "ICUT_CUT_TM_LCELLS" "198 " "Implemented 198 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1600301661771 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1600301661771 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1600301661771 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1600301661801 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4568 " "Peak virtual memory: 4568 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301661851 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:21 2020 " "Processing ended: Wed Sep 16 20:14:21 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301661851 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301661851 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301661851 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600301661851 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600301662763 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301662763 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:22 2020 " "Processing started: Wed Sep 16 20:14:22 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301662763 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1600301662763 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1600301662773 ""} +{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1600301662812 ""} +{ "Info" "0" "" "Project = RAM2E" { } { } 0 0 "Project = RAM2E" 0 0 "Fitter" 0 0 1600301662822 ""} +{ "Info" "0" "" "Revision = RAM2E" { } { } 0 0 "Revision = RAM2E" 0 0 "Fitter" 0 0 1600301662822 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1600301662852 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1600301662862 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600301662882 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600301662882 ""} +{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1600301662912 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1600301662922 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1600301662982 ""} +{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1600301663042 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600301663042 "|RAM2E|DRCLK"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600301663042 "|RAM2E|ARCLK"} +{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1600301663042 ""} +{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301663042 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301663042 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301663042 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1600301663042 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600301663052 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600301663052 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600301663052 ""} +{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1600301663052 ""} +{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600301663052 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1600301663052 ""} +{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1600301663072 ""} +{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1600301663072 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1600301663082 ""} +{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1600301663090 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1600301663090 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1600301663090 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301663110 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1600301663178 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301663309 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1600301663319 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1600301663521 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301663521 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1600301663541 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1600301663683 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1600301663683 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301663792 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.14 " "Total time spent on timing analysis during the Fitter is 0.14 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1600301663802 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301663802 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1600301663822 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1600301663871 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4767 " "Peak virtual memory: 4767 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301663952 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:23 2020 " "Processing ended: Wed Sep 16 20:14:23 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301663952 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301663952 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301663952 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1600301663952 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1600301664792 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301664792 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:24 2020 " "Processing started: Wed Sep 16 20:14:24 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301664792 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1600301664792 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1600301664792 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1600301664952 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1600301664952 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4524 " "Peak virtual memory: 4524 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301665092 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:25 2020 " "Processing ended: Wed Sep 16 20:14:25 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301665092 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301665092 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301665092 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1600301665092 ""} +{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1600301665682 ""} +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1600301665982 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301665982 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:25 2020 " "Processing started: Wed Sep 16 20:14:25 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301665982 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600301665982 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600301665982 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1600301666032 ""} +{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600301666122 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600301666152 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600301666152 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1600301666172 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1600301666410 ""} +{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1600301666462 ""} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600301666470 "|RAM2E|DRCLK"} +{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600301666470 "|RAM2E|ARCLK"} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1600301666470 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup 21.694 " "Worst-case setup slack is 21.694" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 21.694 0.000 C14M " " 21.694 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 3.144 " "Worst-case hold slack is 3.144" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.144 0.000 C14M " " 3.144 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600301666510 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600301666520 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.581 " "Worst-case minimum pulse width slack is 34.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666530 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666530 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.581 0.000 C14M " " 34.581 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666530 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301666530 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1600301666570 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600301666590 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600301666590 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301666660 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:26 2020 " "Processing ended: Wed Sep 16 20:14:26 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301666660 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301666660 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301666660 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600301666660 ""} +{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 13 s " "Quartus II Full Compilation was successful. 0 errors, 13 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600301667280 ""} diff --git a/cpld/incremental_db/compiled_partitions/RAM2E.db_info b/cpld/incremental_db/compiled_partitions/RAM2E.db_info new file mode 100644 index 0000000..13cf0a5 --- /dev/null +++ b/cpld/incremental_db/compiled_partitions/RAM2E.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +Version_Index = 302049280 +Creation_Time = Wed Sep 16 19:59:34 2020 diff --git a/cpld/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt index f2e0394..674b4f3 100755 Binary files a/cpld/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt differ diff --git a/cpld/output_files/RAM2E.asm.rpt b/cpld/output_files/RAM2E.asm.rpt index 2cc2e37..f002d49 100755 --- a/cpld/output_files/RAM2E.asm.rpt +++ b/cpld/output_files/RAM2E.asm.rpt @@ -1,5 +1,5 @@ Assembler report for RAM2E -Wed Sep 16 19:34:49 2020 +Wed Sep 16 20:14:41 2020 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -37,7 +37,7 @@ applicable agreement for further details. +---------------------------------------------------------------+ ; Assembler Summary ; +-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Wed Sep 16 19:34:49 2020 ; +; Assembler Status ; Successful - Wed Sep 16 20:14:41 2020 ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; ; Family ; MAX V ; @@ -90,8 +90,8 @@ applicable agreement for further details. ; Option ; Setting ; +----------------+---------------------------------------------------------------------------+ ; Device ; 5M240ZT100C5 ; -; JTAG usercode ; 0x0016E4E9 ; -; Checksum ; 0x0016E859 ; +; JTAG usercode ; 0x0016ED59 ; +; Checksum ; 0x0016F0C1 ; +----------------+---------------------------------------------------------------------------+ @@ -101,13 +101,13 @@ applicable agreement for further details. Info: ******************************************************************* Info: Running Quartus II 64-Bit Assembler Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Wed Sep 16 19:34:49 2020 + Info: Processing started: Wed Sep 16 20:14:41 2020 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E Info (115031): Writing out detailed assembly data for power analysis Info (115030): Assembler is generating device programming files Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4524 megabytes - Info: Processing ended: Wed Sep 16 19:34:49 2020 + Info: Processing ended: Wed Sep 16 20:14:41 2020 Info: Elapsed time: 00:00:00 Info: Total CPU time (on all processors): 00:00:00 diff --git a/cpld/output_files/RAM2E.done b/cpld/output_files/RAM2E.done index d21a61d..39c72ed 100755 --- a/cpld/output_files/RAM2E.done +++ b/cpld/output_files/RAM2E.done @@ -1 +1 @@ -Wed Sep 16 19:34:52 2020 +Wed Sep 16 20:14:44 2020 diff --git a/cpld/output_files/RAM2E.fit.rpt b/cpld/output_files/RAM2E.fit.rpt index 939dd58..a748e8c 100755 --- a/cpld/output_files/RAM2E.fit.rpt +++ b/cpld/output_files/RAM2E.fit.rpt @@ -1,5 +1,5 @@ Fitter report for RAM2E -Wed Sep 16 19:34:48 2020 +Wed Sep 16 20:14:40 2020 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -57,14 +57,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Fitter Summary ; +---------------------------+-------------------------------------------------+ -; Fitter Status ; Successful - Wed Sep 16 19:34:48 2020 ; +; Fitter Status ; Successful - Wed Sep 16 20:14:40 2020 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; ; Family ; MAX V ; ; Device ; 5M240ZT100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 199 / 240 ( 83 % ) ; +; Total logic elements ; 189 / 240 ( 79 % ) ; ; Total pins ; 69 / 79 ( 87 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -142,28 +142,28 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu +---------------------------------------------+--------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------+ -; Total logic elements ; 199 / 240 ( 83 % ) ; -; -- Combinational with no register ; 84 ; -; -- Register only ; 25 ; +; Total logic elements ; 189 / 240 ( 79 % ) ; +; -- Combinational with no register ; 82 ; +; -- Register only ; 17 ; ; -- Combinational with a register ; 90 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 99 ; -; -- 3 input functions ; 36 ; -; -- 2 input functions ; 35 ; +; -- 4 input functions ; 90 ; +; -- 3 input functions ; 42 ; +; -- 2 input functions ; 36 ; ; -- 1 input functions ; 3 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 185 ; +; -- normal mode ; 175 ; ; -- arithmetic mode ; 14 ; ; -- qfbk mode ; 9 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 14 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 115 / 240 ( 48 % ) ; -; Total LABs ; 24 / 24 ( 100 % ) ; +; Total registers ; 107 / 240 ( 45 % ) ; +; Total LABs ; 22 / 24 ( 92 % ) ; ; Logic elements in carry chains ; 15 ; ; Virtual pins ; 0 ; ; I/O pins ; 69 / 79 ( 87 % ) ; @@ -173,12 +173,12 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu ; UFM blocks ; 1 / 1 ( 100 % ) ; ; Global clocks ; 1 / 4 ( 25 % ) ; ; JTAGs ; 0 / 1 ( 0 % ) ; -; Average interconnect usage (total/H/V) ; 23% / 22% / 23% ; -; Peak interconnect usage (total/H/V) ; 23% / 22% / 23% ; -; Maximum fan-out ; 115 ; -; Highest non-global fan-out ; 25 ; -; Total fan-out ; 850 ; -; Average fan-out ; 3.16 ; +; Average interconnect usage (total/H/V) ; 24% / 26% / 22% ; +; Peak interconnect usage (total/H/V) ; 24% / 26% / 22% ; +; Maximum fan-out ; 107 ; +; Highest non-global fan-out ; 34 ; +; Total fan-out ; 810 ; +; Average fan-out ; 3.13 ; +---------------------------------------------+--------------------+ @@ -187,19 +187,19 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu +--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; +--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ -; Ain[0] ; 56 ; 2 ; 8 ; 1 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; -; Ain[1] ; 54 ; 2 ; 8 ; 1 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; -; Ain[2] ; 43 ; 1 ; 6 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; -; Ain[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; -; Ain[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; -; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; -; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; -; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 2 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; -; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 115 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; -; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[0] ; 56 ; 2 ; 8 ; 1 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[1] ; 54 ; 2 ; 8 ; 1 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[2] ; 43 ; 1 ; 6 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[3] ; 47 ; 1 ; 6 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[4] ; 44 ; 1 ; 6 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[5] ; 34 ; 1 ; 3 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[6] ; 39 ; 1 ; 5 ; 0 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Ain[7] ; 53 ; 2 ; 8 ; 1 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; C14M ; 12 ; 1 ; 1 ; 3 ; 3 ; 107 ; 0 ; yes ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Din[0] ; 38 ; 1 ; 4 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; ; Din[1] ; 40 ; 1 ; 5 ; 0 ; 2 ; 11 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; -; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; -; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 9 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Din[2] ; 42 ; 1 ; 5 ; 0 ; 0 ; 10 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; +; Din[3] ; 41 ; 1 ; 5 ; 0 ; 1 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; ; Din[4] ; 48 ; 1 ; 6 ; 0 ; 0 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; ; Din[5] ; 49 ; 1 ; 7 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; ; Din[6] ; 36 ; 1 ; 4 ; 0 ; 2 ; 8 ; 0 ; no ; no ; no ; Off ; 3.3-V LVCMOS ; User ; @@ -220,8 +220,8 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu ; BA[0] ; 6 ; 1 ; 1 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; -; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; @@ -230,31 +230,31 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu ; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[2] ; 30 ; 1 ; 3 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[3] ; 27 ; 1 ; 2 ; 0 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; RA[4] ; 26 ; 1 ; 2 ; 0 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[5] ; 29 ; 1 ; 2 ; 0 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[6] ; 21 ; 1 ; 1 ; 1 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[7] ; 19 ; 1 ; 1 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; nCAS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +; nCAS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; ; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nRAS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; -; nRWE ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ; +; nRWE ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; ; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ; +---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+ @@ -418,7 +418,7 @@ Note: User assignments will override these defaults. The user specified values a +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ -; |RAM2E ; 199 (199) ; 115 ; 1 ; 69 ; 0 ; 84 (84) ; 25 (25) ; 90 (90) ; 15 (15) ; 9 (9) ; |RAM2E ; work ; +; |RAM2E ; 189 (189) ; 107 ; 1 ; 69 ; 0 ; 82 (82) ; 17 (17) ; 90 (90) ; 15 (15) ; 9 (9) ; |RAM2E ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; work ; ; |UFM_altufm_none_e4r:UFM_altufm_none_e4r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ @@ -507,17 +507,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-------------+-------------+---------+---------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +-------------+-------------+---------+---------------+--------+----------------------+------------------+ -; C14M ; PIN_12 ; 115 ; Clock ; yes ; Global Clock ; GCLK0 ; -; CS[0]~2 ; LC_X6_Y1_N4 ; 3 ; Clock enable ; no ; -- ; -- ; -; Equal9~0 ; LC_X6_Y3_N7 ; 14 ; Clock enable ; no ; -- ; -- ; -; Equal9~1 ; LC_X6_Y3_N5 ; 8 ; Clock enable ; no ; -- ; -- ; -; Equal9~7 ; LC_X2_Y2_N7 ; 8 ; Clock enable ; no ; -- ; -- ; -; RA[4]~2 ; LC_X2_Y2_N5 ; 8 ; Clock enable ; no ; -- ; -- ; -; RDOE ; LC_X2_Y4_N6 ; 8 ; Output enable ; no ; -- ; -- ; -; RWBank[4]~1 ; LC_X7_Y2_N1 ; 13 ; Clock enable ; no ; -- ; -- ; -; RWMask[4]~2 ; LC_X5_Y2_N9 ; 8 ; Clock enable ; no ; -- ; -- ; -; S[1] ; LC_X6_Y3_N6 ; 23 ; Sync. clear ; no ; -- ; -- ; -; UFMD[8]~5 ; LC_X4_Y2_N7 ; 7 ; Clock enable ; no ; -- ; -- ; +; C14M ; PIN_12 ; 107 ; Clock ; yes ; Global Clock ; GCLK0 ; +; CS[0]~2 ; LC_X4_Y3_N1 ; 3 ; Clock enable ; no ; -- ; -- ; +; Equal9~0 ; LC_X6_Y4_N8 ; 14 ; Clock enable ; no ; -- ; -- ; +; Equal9~1 ; LC_X7_Y3_N5 ; 8 ; Clock enable ; no ; -- ; -- ; +; RA[4]~1 ; LC_X2_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ; +; RDOE ; LC_X3_Y4_N7 ; 8 ; Output enable ; no ; -- ; -- ; +; RWBank[4]~1 ; LC_X5_Y3_N2 ; 13 ; Clock enable ; no ; -- ; -- ; +; RWMask[4]~2 ; LC_X4_Y2_N8 ; 8 ; Clock enable ; no ; -- ; -- ; +; S[2] ; LC_X7_Y3_N4 ; 20 ; Sync. clear ; no ; -- ; -- ; +; UFMD[8]~5 ; LC_X3_Y2_N8 ; 7 ; Clock enable ; no ; -- ; -- ; +-------------+-------------+---------+---------------+--------+----------------------+------------------+ @@ -526,7 +525,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +------+----------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +------+----------+---------+----------------------+------------------+ -; C14M ; PIN_12 ; 115 ; Global Clock ; GCLK0 ; +; C14M ; PIN_12 ; 107 ; Global Clock ; GCLK0 ; +------+----------+---------+----------------------+------------------+ @@ -535,81 +534,79 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------------------------------------------------------+---------+ ; Name ; Fan-Out ; +----------------------------------------------------------------------------------------------+---------+ -; S[0] ; 25 ; -; S[3] ; 24 ; -; Equal9~6 ; 23 ; -; S[1] ; 23 ; -; S[2] ; 23 ; +; S[0] ; 34 ; +; S[1] ; 29 ; +; Equal9~4 ; 23 ; +; S[3] ; 22 ; +; S[2] ; 20 ; ; Equal9~0 ; 14 ; ; RWBank[4]~1 ; 13 ; ; Din[1] ; 11 ; -; CS[1] ; 10 ; -; Din[3] ; 9 ; -; Din[2] ; 9 ; -; Din[0] ; 9 ; -; CS[0] ; 9 ; +; Din[2] ; 10 ; +; Din[0] ; 10 ; +; CS[1] ; 9 ; +; Din[3] ; 8 ; ; Din[7] ; 8 ; ; Din[6] ; 8 ; ; RWMask[4]~2 ; 8 ; ; RDOE ; 8 ; -; Equal9~7 ; 8 ; ; SetRWBankFF ; 8 ; -; CS[2] ; 8 ; +; CS[0] ; 8 ; ; RWSel ; 8 ; -; RA[4]~2 ; 8 ; -; RA[4]~0 ; 8 ; -; Equal9~4 ; 8 ; +; RA[4]~1 ; 8 ; ; FS[4] ; 8 ; ; Equal9~1 ; 8 ; ; Din[5] ; 7 ; ; Din[4] ; 7 ; ; UFMD[8]~5 ; 7 ; ; always1~9 ; 7 ; -; FS[5] ; 7 ; +; CS[2] ; 7 ; +; UFMReqErase ; 6 ; ; UFMInitDone ; 6 ; -; FS[3] ; 6 ; ; FS[0] ; 6 ; -; Equal4~0 ; 5 ; -; UFMReqErase ; 5 ; +; FS[5] ; 6 ; ; always1~1 ; 5 ; -; FS[2]~25 ; 5 ; -; FS[7]~19 ; 5 ; +; FS[3] ; 5 ; +; FS[2]~27 ; 5 ; +; FS[7]~23 ; 5 ; ; FS[15] ; 5 ; ; FS[14] ; 5 ; ; FS[13] ; 5 ; ; PHI1 ; 4 ; ; nEN80 ; 4 ; -; always1~6 ; 4 ; ; UFMD[13] ; 4 ; ; CmdTout[0] ; 4 ; -; UFMBitbang~0 ; 4 ; ; UFMEraseEN ; 4 ; ; UFMPrgmEN ; 4 ; -; always1~2 ; 4 ; -; Equal9~5 ; 4 ; +; Equal4~0 ; 4 ; +; Equal9~3 ; 4 ; ; DRCLK~0 ; 4 ; +; Equal9~2 ; 4 ; ; UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component|wire_maxii_ufm_block1_drdout ; 4 ; ; S[3]~9 ; 3 ; ; UFMD[11] ; 3 ; ; UFMD[9] ; 3 ; ; UFMD[10] ; 3 ; +; always1~6 ; 3 ; ; UFMD[12] ; 3 ; ; UFMD[8] ; 3 ; ; CS[0]~2 ; 3 ; ; CmdTout[1] ; 3 ; ; CS~0 ; 3 ; -; RWMaskSet~1 ; 3 ; +; always2~7 ; 3 ; +; RWMaskSet~0 ; 3 ; ; S~4 ; 3 ; ; Ready ; 3 ; ; S[3]~2 ; 3 ; +; always1~2 ; 3 ; ; always1~0 ; 3 ; ; Equal10~4 ; 3 ; ; FS[2] ; 3 ; ; FS[1] ; 3 ; ; always2~0 ; 3 ; ; Ready~0 ; 3 ; +; nCS~2 ; 3 ; ; FS[6] ; 3 ; -; Equal9~2 ; 3 ; ; Equal10~1 ; 3 ; ; FS[12]~1 ; 3 ; ; RD[7]~7 ; 2 ; @@ -620,40 +617,33 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; RD[2]~2 ; 2 ; ; RD[1]~1 ; 2 ; ; RD[0]~0 ; 2 ; -; Ain[7] ; 2 ; -; Ain[6] ; 2 ; -; Ain[5] ; 2 ; -; Ain[4] ; 2 ; -; Ain[3] ; 2 ; -; Ain[2] ; 2 ; -; Ain[1] ; 2 ; -; Ain[0] ; 2 ; ; nWE80 ; 2 ; ; nWE ; 2 ; ; UFMD[14] ; 2 ; ; UFMEraseEN~0 ; 2 ; -; UFMReqErase~3 ; 2 ; -; UFMBusyReg ; 2 ; +; RWMask[4]~0 ; 2 ; ; UFMInitDone~0 ; 2 ; ; CmdTout[2] ; 2 ; -; Equal39~1 ; 2 ; -; always2~10 ; 2 ; +; Equal39~0 ; 2 ; +; RWMaskSet~1 ; 2 ; +; Equal27~1 ; 2 ; +; UFMBitbang~0 ; 2 ; ; S~3 ; 2 ; +; UFMBusyReg ; 2 ; ; always1~3 ; 2 ; ; UFMD[8]~4 ; 2 ; ; RWBank[6] ; 2 ; -; nRAS~2 ; 2 ; -; nRAS~1 ; 2 ; -; nCS~3 ; 2 ; -; nCS~1 ; 2 ; +; nCS~5 ; 2 ; +; nCS~4 ; 2 ; +; Equal12~0 ; 2 ; ; FS[7] ; 2 ; -; CKE~1 ; 2 ; ; Equal10~2 ; 2 ; ; FS[11] ; 2 ; ; FS[10] ; 2 ; ; FS[9] ; 2 ; ; FS[8] ; 2 ; ; FS[12] ; 2 ; +; CKE~0 ; 2 ; ; UFMErase ; 2 ; ; UFMProgram ; 2 ; ; DRDIn ; 2 ; @@ -662,32 +652,39 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; UFMProgram~_wirecell ; 1 ; ; UFMErase~_wirecell ; 1 ; ; nC07X ; 1 ; +; Ain[7] ; 1 ; +; Ain[6] ; 1 ; +; Ain[5] ; 1 ; +; Ain[4] ; 1 ; +; Ain[3] ; 1 ; +; Ain[2] ; 1 ; +; Ain[1] ; 1 ; +; Ain[0] ; 1 ; ; ~GND ; 1 ; -; UFMReqErase~4 ; 1 ; ; RWMaskSet ; 1 ; -; RWMask[4]~1 ; 1 ; ; always1~8 ; 1 ; ; always1~7 ; 1 ; ; Ready~1 ; 1 ; +; UFMReqErase~3 ; 1 ; ; UFMReqErase~2 ; 1 ; ; UFMReqErase~1 ; 1 ; ; UFMReqErase~0 ; 1 ; ; always1~5 ; 1 ; ; always1~4 ; 1 ; ; Add3~0 ; 1 ; +; always2~13 ; 1 ; +; Equal39~1 ; 1 ; ; always2~12 ; 1 ; -; Equal39~0 ; 1 ; ; always2~11 ; 1 ; +; always2~10 ; 1 ; ; always2~9 ; 1 ; ; always2~8 ; 1 ; -; always2~7 ; 1 ; ; always2~6 ; 1 ; ; always2~5 ; 1 ; ; always2~4 ; 1 ; ; always2~3 ; 1 ; ; always2~2 ; 1 ; ; always2~1 ; 1 ; -; RWMaskSet~0 ; 1 ; ; RWSel~0 ; 1 ; ; RWMask[6] ; 1 ; ; RWMask[3] ; 1 ; @@ -707,43 +704,34 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; DRCLK~1 ; 1 ; ; Equal27~0 ; 1 ; ; UFMBitbang ; 1 ; +; DQML~0 ; 1 ; ; RWBank[3] ; 1 ; -; RA~12 ; 1 ; +; RA~11 ; 1 ; ; RWBank[2] ; 1 ; ; RWBank[1] ; 1 ; ; RWBank[0] ; 1 ; ; RWBank[7] ; 1 ; -; Areg[7] ; 1 ; -; Areg[6] ; 1 ; -; Areg[5] ; 1 ; -; Areg[4] ; 1 ; -; Areg[3] ; 1 ; -; Areg[2] ; 1 ; -; Areg[1] ; 1 ; -; Areg[0] ; 1 ; ; RWBank[5] ; 1 ; ; RWBank[4] ; 1 ; -; Equal12~1 ; 1 ; +; nRWE~1 ; 1 ; ; nRWE~0 ; 1 ; +; nCAS~1 ; 1 ; ; nCAS~0 ; 1 ; -; nCS~2 ; 1 ; -; nRAS~0 ; 1 ; -; Equal12~0 ; 1 ; ; FS[3]~29COUT1_46 ; 1 ; ; FS[3]~29 ; 1 ; -; FS[5]~27COUT1_50 ; 1 ; -; FS[5]~27 ; 1 ; -; FS[1]~23COUT1_44 ; 1 ; -; FS[1]~23 ; 1 ; -; FS[4]~21COUT1_48 ; 1 ; -; FS[4]~21 ; 1 ; -; FS[6]~17COUT1_52 ; 1 ; -; FS[6]~17 ; 1 ; +; FS[1]~25COUT1_44 ; 1 ; +; FS[1]~25 ; 1 ; ; Equal10~3 ; 1 ; -; Equal9~3 ; 1 ; +; nCS~3 ; 1 ; +; FS[6]~21COUT1_52 ; 1 ; +; FS[6]~21 ; 1 ; +; FS[5]~19COUT1_50 ; 1 ; +; FS[5]~19 ; 1 ; +; FS[4]~17COUT1_48 ; 1 ; +; FS[4]~17 ; 1 ; +; nCS~1 ; 1 ; ; nCS~0 ; 1 ; ; CKE~2 ; 1 ; -; CKE~0 ; 1 ; ; FS[14]~13COUT1_64 ; 1 ; ; FS[14]~13 ; 1 ; ; FS[13]~11COUT1_62 ; 1 ; @@ -757,6 +745,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi ; FS[9]~5 ; 1 ; ; FS[8]~3COUT1_54 ; 1 ; ; FS[8]~3 ; 1 ; +; CKE~1 ; 1 ; ; ARShift ; 1 ; ; ARCLK ; 1 ; ; DRShift ; 1 ; @@ -808,62 +797,62 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +-----------------------------+--------------------+ ; Other Routing Resource Type ; Usage ; +-----------------------------+--------------------+ -; C4s ; 151 / 784 ( 19 % ) ; -; Direct links ; 54 / 888 ( 6 % ) ; +; C4s ; 142 / 784 ( 18 % ) ; +; Direct links ; 49 / 888 ( 6 % ) ; ; Global clocks ; 1 / 4 ( 25 % ) ; ; LAB clocks ; 6 / 32 ( 19 % ) ; -; LUT chains ; 14 / 216 ( 6 % ) ; -; Local interconnects ; 299 / 888 ( 34 % ) ; -; R4s ; 125 / 704 ( 18 % ) ; +; LUT chains ; 13 / 216 ( 6 % ) ; +; Local interconnects ; 306 / 888 ( 34 % ) ; +; R4s ; 151 / 704 ( 21 % ) ; +-----------------------------+--------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ -; Number of Logic Elements (Average = 8.29) ; Number of LABs (Total = 24) ; +; Number of Logic Elements (Average = 8.59) ; Number of LABs (Total = 22) ; +--------------------------------------------+------------------------------+ -; 1 ; 3 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 1 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 1 ; +; 5 ; 0 ; ; 6 ; 1 ; ; 7 ; 0 ; ; 8 ; 1 ; -; 9 ; 3 ; -; 10 ; 15 ; +; 9 ; 4 ; +; 10 ; 13 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ -; LAB-wide Signals (Average = 1.38) ; Number of LABs (Total = 24) ; +; LAB-wide Signals (Average = 1.36) ; Number of LABs (Total = 22) ; +------------------------------------+------------------------------+ -; 1 Clock ; 22 ; -; 1 Clock enable ; 7 ; -; 2 Clock enables ; 4 ; +; 1 Clock ; 21 ; +; 1 Clock enable ; 8 ; +; 2 Clock enables ; 1 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ -; Number of Signals Sourced (Average = 8.67) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced (Average = 9.00) ; Number of LABs (Total = 22) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 3 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 0 ; -; 5 ; 1 ; -; 6 ; 1 ; -; 7 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 1 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 1 ; ; 8 ; 1 ; -; 9 ; 3 ; -; 10 ; 12 ; -; 11 ; 1 ; +; 9 ; 4 ; +; 10 ; 11 ; +; 11 ; 0 ; ; 12 ; 1 ; ; 13 ; 0 ; ; 14 ; 0 ; @@ -875,50 +864,49 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ -; Number of Signals Sourced Out (Average = 6.13) ; Number of LABs (Total = 24) ; +; Number of Signals Sourced Out (Average = 6.68) ; Number of LABs (Total = 22) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 3 ; -; 2 ; 0 ; -; 3 ; 0 ; -; 4 ; 4 ; -; 5 ; 1 ; -; 6 ; 3 ; -; 7 ; 4 ; -; 8 ; 6 ; -; 9 ; 2 ; -; 10 ; 0 ; -; 11 ; 1 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 2 ; +; 4 ; 2 ; +; 5 ; 2 ; +; 6 ; 2 ; +; 7 ; 2 ; +; 8 ; 7 ; +; 9 ; 1 ; +; 10 ; 3 ; +-------------------------------------------------+------------------------------+ +-----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +----------------------------------------------+------------------------------+ -; Number of Distinct Inputs (Average = 11.25) ; Number of LABs (Total = 24) ; +; Number of Distinct Inputs (Average = 11.73) ; Number of LABs (Total = 22) ; +----------------------------------------------+------------------------------+ ; 0 ; 0 ; -; 1 ; 1 ; +; 1 ; 0 ; ; 2 ; 2 ; -; 3 ; 2 ; -; 4 ; 1 ; -; 5 ; 0 ; -; 6 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 1 ; +; 6 ; 1 ; ; 7 ; 1 ; ; 8 ; 0 ; -; 9 ; 2 ; -; 10 ; 2 ; +; 9 ; 5 ; +; 10 ; 0 ; ; 11 ; 1 ; -; 12 ; 2 ; +; 12 ; 1 ; ; 13 ; 1 ; -; 14 ; 0 ; +; 14 ; 2 ; ; 15 ; 1 ; ; 16 ; 1 ; -; 17 ; 3 ; -; 18 ; 1 ; -; 19 ; 0 ; +; 17 ; 1 ; +; 18 ; 0 ; +; 19 ; 2 ; ; 20 ; 1 ; -; 21 ; 2 ; +; 21 ; 1 ; +----------------------------------------------+------------------------------+ @@ -977,7 +965,6 @@ Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:00 Info (170193): Fitter routing operations beginning -Info (170089): 2e+01 ns of routing delay (approximately 1.2% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report. Info (170195): Router estimated average interconnect usage is 19% of the available device resources Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5 Info (170194): Fitter routing operations ending: elapsed time is 00:00:00 @@ -987,8 +974,8 @@ Warning (169174): The Reserve All Unused Pins setting has not been specified, an Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings Info: Peak virtual memory: 4767 megabytes - Info: Processing ended: Wed Sep 16 19:34:48 2020 - Info: Elapsed time: 00:00:02 + Info: Processing ended: Wed Sep 16 20:14:40 2020 + Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/RAM2E.fit.summary b/cpld/output_files/RAM2E.fit.summary index 355ceb6..06d81ca 100755 --- a/cpld/output_files/RAM2E.fit.summary +++ b/cpld/output_files/RAM2E.fit.summary @@ -1,11 +1,11 @@ -Fitter Status : Successful - Wed Sep 16 19:34:48 2020 +Fitter Status : Successful - Wed Sep 16 20:14:40 2020 Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : RAM2E Top-level Entity Name : RAM2E Family : MAX V Device : 5M240ZT100C5 Timing Models : Final -Total logic elements : 199 / 240 ( 83 % ) +Total logic elements : 189 / 240 ( 79 % ) Total pins : 69 / 79 ( 87 % ) Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/cpld/output_files/RAM2E.flow.rpt b/cpld/output_files/RAM2E.flow.rpt index 3ae128e..eabeaf8 100755 --- a/cpld/output_files/RAM2E.flow.rpt +++ b/cpld/output_files/RAM2E.flow.rpt @@ -1,5 +1,5 @@ Flow report for RAM2E -Wed Sep 16 19:34:51 2020 +Wed Sep 16 20:14:43 2020 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -40,14 +40,14 @@ applicable agreement for further details. +-----------------------------------------------------------------------------+ ; Flow Summary ; +---------------------------+-------------------------------------------------+ -; Flow Status ; Successful - Wed Sep 16 19:34:49 2020 ; +; Flow Status ; Successful - Wed Sep 16 20:14:41 2020 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; ; Family ; MAX V ; ; Device ; 5M240ZT100C5 ; ; Timing Models ; Final ; -; Total logic elements ; 199 / 240 ( 83 % ) ; +; Total logic elements ; 189 / 240 ( 79 % ) ; ; Total pins ; 69 / 79 ( 87 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -59,7 +59,7 @@ applicable agreement for further details. +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ -; Start date & time ; 09/16/2020 19:34:45 ; +; Start date & time ; 09/16/2020 20:14:37 ; ; Main task ; Compilation ; ; Revision Name ; RAM2E ; +-------------------+---------------------+ @@ -71,7 +71,7 @@ applicable agreement for further details. ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +------------------------------------+---------------------------------+---------------+-------------+------------+ ; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ; -; COMPILER_SIGNATURE_ID ; 207120313862967.160029928511600 ; -- ; -- ; -- ; +; COMPILER_SIGNATURE_ID ; 207120313862967.160030167703488 ; -- ; -- ; -- ; ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ; ; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ; ; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ; @@ -93,8 +93,8 @@ applicable agreement for further details. +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +---------------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:00:00 ; 1.0 ; 4575 MB ; 00:00:01 ; -; Fitter ; 00:00:02 ; 1.0 ; 4767 MB ; 00:00:01 ; +; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4568 MB ; 00:00:01 ; +; Fitter ; 00:00:01 ; 1.0 ; 4767 MB ; 00:00:01 ; ; Assembler ; 00:00:00 ; 1.0 ; 4524 MB ; 00:00:00 ; ; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4522 MB ; 00:00:01 ; ; Total ; 00:00:03 ; -- ; -- ; 00:00:03 ; diff --git a/cpld/output_files/RAM2E.jdi b/cpld/output_files/RAM2E.jdi index f4ff7e9..a754f33 100755 --- a/cpld/output_files/RAM2E.jdi +++ b/cpld/output_files/RAM2E.jdi @@ -1,6 +1,6 @@ - + diff --git a/cpld/output_files/RAM2E.map.rpt b/cpld/output_files/RAM2E.map.rpt index bc0671a..5c0d3aa 100755 --- a/cpld/output_files/RAM2E.map.rpt +++ b/cpld/output_files/RAM2E.map.rpt @@ -1,5 +1,5 @@ Analysis & Synthesis report for RAM2E -Wed Sep 16 19:34:46 2020 +Wed Sep 16 20:14:38 2020 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -45,12 +45,12 @@ applicable agreement for further details. +-------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+-------------------------------------------------+ -; Analysis & Synthesis Status ; Successful - Wed Sep 16 19:34:45 2020 ; +; Analysis & Synthesis Status ; Successful - Wed Sep 16 20:14:38 2020 ; ; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ; ; Revision Name ; RAM2E ; ; Top-level Entity Name ; RAM2E ; ; Family ; MAX V ; -; Total logic elements ; 208 ; +; Total logic elements ; 198 ; ; Total pins ; 69 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 1 / 1 ( 100 % ) ; @@ -157,34 +157,34 @@ Parallel compilation was disabled, but you have multiple processors available. E +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ -; Total logic elements ; 208 ; -; -- Combinational with no register ; 93 ; -; -- Register only ; 34 ; +; Total logic elements ; 198 ; +; -- Combinational with no register ; 91 ; +; -- Register only ; 26 ; ; -- Combinational with a register ; 81 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; -; -- 4 input functions ; 99 ; -; -- 3 input functions ; 36 ; -; -- 2 input functions ; 35 ; +; -- 4 input functions ; 90 ; +; -- 3 input functions ; 42 ; +; -- 2 input functions ; 36 ; ; -- 1 input functions ; 3 ; ; -- 0 input functions ; 1 ; ; ; ; ; Logic elements by mode ; ; -; -- normal mode ; 194 ; +; -- normal mode ; 184 ; ; -- arithmetic mode ; 14 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 1 ; ; -- asynchronous clear/load mode ; 0 ; ; ; ; -; Total registers ; 115 ; +; Total registers ; 107 ; ; Total logic cells in carry chains ; 15 ; ; I/O pins ; 69 ; ; UFM blocks ; 1 ; ; Maximum fan-out node ; C14M ; -; Maximum fan-out ; 115 ; -; Total fan-out ; 854 ; -; Average fan-out ; 3.07 ; +; Maximum fan-out ; 107 ; +; Total fan-out ; 814 ; +; Average fan-out ; 3.04 ; +---------------------------------------------+-------+ @@ -193,7 +193,7 @@ Parallel compilation was disabled, but you have multiple processors available. E +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ -; |RAM2E ; 208 (208) ; 115 ; 1 ; 69 ; 0 ; 93 (93) ; 34 (34) ; 81 (81) ; 15 (15) ; 0 (0) ; |RAM2E ; work ; +; |RAM2E ; 198 (198) ; 107 ; 1 ; 69 ; 0 ; 91 (91) ; 26 (26) ; 81 (81) ; 15 (15) ; 0 (0) ; |RAM2E ; work ; ; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; work ; ; |UFM_altufm_none_e4r:UFM_altufm_none_e4r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component ; work ; +-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+ @@ -214,12 +214,12 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ -; Total registers ; 115 ; +; Total registers ; 107 ; ; Number of registers using Synchronous Clear ; 1 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 0 ; ; Number of registers using Asynchronous Load ; 0 ; -; Number of registers using Clock Enable ; 64 ; +; Number of registers using Clock Enable ; 56 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ @@ -246,7 +246,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[3] ; ; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[2] ; -; 16:1 ; 8 bits ; 80 LEs ; 16 LEs ; 64 LEs ; Yes ; |RAM2E|RA[4]~reg0 ; +; 16:1 ; 8 bits ; 80 LEs ; 8 LEs ; 72 LEs ; Yes ; |RAM2E|RA[4]~reg0 ; ; 9:1 ; 8 bits ; 48 LEs ; 16 LEs ; 32 LEs ; Yes ; |RAM2E|RWMask[4] ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ @@ -268,7 +268,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Wed Sep 16 19:34:45 2020 + Info: Processing started: Wed Sep 16 20:14:37 2020 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E Warning (20028): Parallel compilation is not licensed and has been disabled Info (12021): Found 1 design units, including 1 entities, in source file ram2e.v @@ -277,22 +277,22 @@ Info (12021): Found 2 design units, including 2 entities, in source file ufm.v Info (12023): Found entity 1: UFM_altufm_none_e4r Info (12023): Found entity 2: UFM Info (12127): Elaborating entity "RAM2E" for the top level hierarchy -Warning (10230): Verilog HDL assignment warning at RAM2E.v(101): truncated value with size 32 to match size of target (16) -Warning (10230): Verilog HDL assignment warning at RAM2E.v(104): truncated value with size 32 to match size of target (4) -Warning (10230): Verilog HDL assignment warning at RAM2E.v(551): truncated value with size 32 to match size of target (3) -Warning (10230): Verilog HDL assignment warning at RAM2E.v(568): truncated value with size 32 to match size of target (3) +Warning (10230): Verilog HDL assignment warning at RAM2E.v(100): truncated value with size 32 to match size of target (16) +Warning (10230): Verilog HDL assignment warning at RAM2E.v(103): truncated value with size 32 to match size of target (4) +Warning (10230): Verilog HDL assignment warning at RAM2E.v(544): truncated value with size 32 to match size of target (3) +Warning (10230): Verilog HDL assignment warning at RAM2E.v(561): truncated value with size 32 to match size of target (3) Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" Info (12128): Elaborating entity "UFM_altufm_none_e4r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component" -Info (21057): Implemented 278 device resources after synthesis - the final resource count might be different +Info (21057): Implemented 268 device resources after synthesis - the final resource count might be different Info (21058): Implemented 22 input pins Info (21059): Implemented 39 output pins Info (21060): Implemented 8 bidirectional pins - Info (21061): Implemented 208 logic cells + Info (21061): Implemented 198 logic cells Info (21070): Implemented 1 User Flash Memory blocks Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings - Info: Peak virtual memory: 4575 megabytes - Info: Processing ended: Wed Sep 16 19:34:46 2020 + Info: Peak virtual memory: 4568 megabytes + Info: Processing ended: Wed Sep 16 20:14:38 2020 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/RAM2E.map.smsg b/cpld/output_files/RAM2E.map.smsg index 1a16445..11cd769 100755 --- a/cpld/output_files/RAM2E.map.smsg +++ b/cpld/output_files/RAM2E.map.smsg @@ -1,3 +1,3 @@ -Warning (10273): Verilog HDL warning at RAM2E.v(39): extended using "x" or "z" +Warning (10273): Verilog HDL warning at RAM2E.v(38): extended using "x" or "z" Warning (10463): Verilog HDL Declaration warning at UFM.v(72): "program" is SystemVerilog-2005 keyword Warning (10463): Verilog HDL Declaration warning at UFM.v(188): "program" is SystemVerilog-2005 keyword diff --git a/cpld/output_files/RAM2E.map.summary b/cpld/output_files/RAM2E.map.summary index 741a5aa..ab29896 100755 --- a/cpld/output_files/RAM2E.map.summary +++ b/cpld/output_files/RAM2E.map.summary @@ -1,9 +1,9 @@ -Analysis & Synthesis Status : Successful - Wed Sep 16 19:34:45 2020 +Analysis & Synthesis Status : Successful - Wed Sep 16 20:14:38 2020 Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition Revision Name : RAM2E Top-level Entity Name : RAM2E Family : MAX V -Total logic elements : 208 +Total logic elements : 198 Total pins : 69 Total virtual pins : 0 UFM blocks : 1 / 1 ( 100 % ) diff --git a/cpld/output_files/RAM2E.pof b/cpld/output_files/RAM2E.pof index c1f36ea..866d2b5 100755 Binary files a/cpld/output_files/RAM2E.pof and b/cpld/output_files/RAM2E.pof differ diff --git a/cpld/output_files/RAM2E.sta.rpt b/cpld/output_files/RAM2E.sta.rpt index 1404ddf..0b484cc 100755 --- a/cpld/output_files/RAM2E.sta.rpt +++ b/cpld/output_files/RAM2E.sta.rpt @@ -1,5 +1,5 @@ TimeQuest Timing Analyzer report for RAM2E -Wed Sep 16 19:34:51 2020 +Wed Sep 16 20:14:43 2020 Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition @@ -83,7 +83,7 @@ Parallel compilation was disabled, but you have multiple processors available. E +-----------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +-----------------+--------+--------------------------+ -; constraints.sdc ; OK ; Wed Sep 16 19:34:51 2020 ; +; constraints.sdc ; OK ; Wed Sep 16 20:14:43 2020 ; +-----------------+--------+--------------------------+ @@ -96,13 +96,13 @@ Parallel compilation was disabled, but you have multiple processors available. E +------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+ -+-------------------------------------------------+ -; Fmax Summary ; -+-----------+-----------------+------------+------+ -; Fmax ; Restricted Fmax ; Clock Name ; Note ; -+-----------+-----------------+------------+------+ -; 34.54 MHz ; 34.54 MHz ; C14M ; ; -+-----------+-----------------+------------+------+ ++------------------------------------------------+ +; Fmax Summary ; ++----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++----------+-----------------+------------+------+ +; 35.4 MHz ; 35.4 MHz ; C14M ; ; ++----------+-----------------+------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. @@ -111,7 +111,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+--------+---------------+ -; C14M ; 22.294 ; 0.000 ; +; C14M ; 21.694 ; 0.000 ; +-------+--------+---------------+ @@ -120,7 +120,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp +-------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------+-------+---------------+ -; C14M ; 3.117 ; 0.000 ; +; C14M ; 3.144 ; 0.000 ; +-------+-------+---------------+ @@ -150,106 +150,106 @@ No paths to report. +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ -; 22.294 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ; -; 22.294 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ; -; 22.294 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ; -; 22.294 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ; -; 22.294 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ; -; 22.294 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.305 ; -; 22.365 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.234 ; -; 22.365 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.234 ; -; 22.365 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.234 ; -; 22.488 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ; -; 22.488 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ; -; 22.488 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ; -; 22.488 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ; -; 22.488 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ; -; 22.488 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.111 ; -; 22.559 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.040 ; -; 22.559 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.040 ; -; 22.559 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.040 ; -; 22.805 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.794 ; -; 22.807 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.792 ; -; 22.825 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.774 ; -; 22.825 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.774 ; -; 22.999 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.600 ; -; 23.001 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.598 ; -; 23.019 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.580 ; -; 23.019 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.580 ; -; 23.370 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ; -; 23.370 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ; -; 23.370 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ; -; 23.370 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ; -; 23.370 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ; -; 23.370 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.229 ; -; 23.443 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.156 ; -; 23.443 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.156 ; -; 23.443 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.156 ; -; 23.881 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.718 ; -; 23.883 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.716 ; -; 23.903 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.696 ; -; 23.903 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.696 ; -; 24.036 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ; -; 24.036 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ; -; 24.036 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ; -; 24.036 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ; -; 24.036 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ; -; 24.036 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.563 ; -; 24.108 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.491 ; -; 24.108 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.491 ; -; 24.108 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.491 ; -; 24.541 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.058 ; -; 24.541 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.058 ; -; 24.541 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.058 ; -; 24.547 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.052 ; -; 24.549 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.050 ; -; 24.568 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.031 ; -; 24.568 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.031 ; -; 24.735 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.864 ; -; 24.735 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.864 ; -; 24.735 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.864 ; -; 25.619 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.980 ; -; 25.619 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.980 ; -; 25.619 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.980 ; -; 26.284 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.315 ; -; 26.284 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.315 ; -; 26.284 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.315 ; -; 40.888 ; UFMD[14] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 28.632 ; -; 41.955 ; UFMD[14] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ; -; 41.955 ; UFMD[14] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ; -; 41.955 ; UFMD[14] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ; -; 41.955 ; UFMD[14] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ; -; 41.955 ; UFMD[14] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ; -; 41.955 ; UFMD[14] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ; -; 41.955 ; UFMD[14] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.565 ; -; 42.894 ; FS[15] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.626 ; -; 43.480 ; UFMD[13] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.040 ; -; 43.730 ; S[0] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.790 ; -; 43.787 ; FS[14] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.733 ; -; 43.865 ; UFMD[9] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.655 ; -; 44.355 ; FS[7] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.165 ; -; 44.387 ; FS[13] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.133 ; -; 44.473 ; FS[4] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.047 ; -; 44.547 ; UFMD[13] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ; -; 44.547 ; UFMD[13] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ; -; 44.547 ; UFMD[13] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ; -; 44.547 ; UFMD[13] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ; -; 44.547 ; UFMD[13] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ; -; 44.547 ; UFMD[13] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ; -; 44.547 ; UFMD[13] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.973 ; -; 44.844 ; FS[15] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 24.676 ; -; 44.932 ; UFMD[9] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ; -; 44.932 ; UFMD[9] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ; -; 44.932 ; UFMD[9] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ; -; 44.932 ; UFMD[9] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ; -; 44.932 ; UFMD[9] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ; -; 44.932 ; UFMD[9] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ; -; 44.932 ; UFMD[9] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.588 ; -; 45.011 ; FS[8] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 24.509 ; -; 45.082 ; S[3] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 24.438 ; -; 45.186 ; FS[7] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 24.334 ; -; 45.257 ; UFMD[12] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.263 ; -; 45.419 ; FS[4] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 24.101 ; +; 21.694 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.905 ; +; 21.873 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ; +; 21.873 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ; +; 21.873 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ; +; 21.873 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ; +; 21.873 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ; +; 21.873 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ; +; 21.885 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.714 ; +; 22.064 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ; +; 22.064 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ; +; 22.064 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ; +; 22.064 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ; +; 22.064 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ; +; 22.064 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ; +; 22.113 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.486 ; +; 22.213 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.386 ; +; 22.213 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.386 ; +; 22.292 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ; +; 22.292 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ; +; 22.292 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ; +; 22.292 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ; +; 22.292 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ; +; 22.292 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ; +; 22.362 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.237 ; +; 22.362 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.237 ; +; 22.362 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.237 ; +; 22.478 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.121 ; +; 22.478 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.121 ; +; 22.627 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.972 ; +; 22.627 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.972 ; +; 22.627 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.972 ; +; 22.949 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.650 ; +; 23.140 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.459 ; +; 23.265 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.334 ; +; 23.265 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.334 ; +; 23.368 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.231 ; +; 23.391 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.208 ; +; 23.414 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.185 ; +; 23.414 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.185 ; +; 23.414 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.185 ; +; 23.570 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ; +; 23.570 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ; +; 23.570 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ; +; 23.570 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ; +; 23.570 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ; +; 23.570 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ; +; 23.915 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.684 ; +; 23.915 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.684 ; +; 24.064 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.535 ; +; 24.064 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.535 ; +; 24.064 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.535 ; +; 24.646 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.953 ; +; 25.589 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.010 ; +; 25.589 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.010 ; +; 25.589 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.010 ; +; 25.854 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.745 ; +; 25.854 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.745 ; +; 25.854 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.745 ; +; 26.641 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.958 ; +; 26.641 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.958 ; +; 26.641 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.958 ; +; 27.291 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.308 ; +; 27.291 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.308 ; +; 27.291 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.308 ; +; 41.591 ; UFMD[9] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.929 ; +; 41.784 ; FS[7] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 27.736 ; +; 41.793 ; FS[15] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 27.727 ; +; 42.673 ; UFMD[9] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ; +; 42.673 ; UFMD[9] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ; +; 42.673 ; UFMD[9] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ; +; 42.673 ; UFMD[9] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ; +; 42.673 ; UFMD[9] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ; +; 42.673 ; UFMD[9] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ; +; 42.673 ; UFMD[9] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ; +; 42.716 ; FS[14] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.804 ; +; 42.879 ; FS[15] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.641 ; +; 42.937 ; FS[11] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.583 ; +; 43.124 ; FS[10] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.396 ; +; 43.146 ; FS[8] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.374 ; +; 43.241 ; S[1] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 26.279 ; +; 43.347 ; FS[13] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.173 ; +; 43.431 ; FS[6] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.089 ; +; 43.785 ; FS[9] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.735 ; +; 43.803 ; FS[14] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.717 ; +; 43.953 ; FS[5] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.567 ; +; 43.961 ; FS[15] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ; +; 43.961 ; FS[15] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ; +; 43.961 ; FS[15] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ; +; 43.961 ; FS[15] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ; +; 43.961 ; FS[15] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ; +; 43.961 ; FS[15] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ; +; 43.961 ; FS[15] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ; +; 43.965 ; FS[12] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.555 ; +; 44.433 ; FS[13] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.087 ; +; 44.437 ; FS[2] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.083 ; +; 44.708 ; S[0] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 24.812 ; +; 44.745 ; CS[0] ; CS[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.775 ; +; 44.748 ; CS[0] ; CS[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.772 ; +; 44.749 ; CS[0] ; CS[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.771 ; +; 44.765 ; S[2] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 24.755 ; +--------+-----------+--------------+--------------+-------------+--------------+------------+------------+ @@ -258,106 +258,106 @@ No paths to report. +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ -; 3.117 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.156 ; -; 3.158 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.197 ; -; 3.742 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.781 ; -; 3.766 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.805 ; -; 3.801 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.840 ; -; 3.810 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.849 ; -; 3.814 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.853 ; -; 3.854 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.893 ; -; 3.856 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.895 ; -; 3.863 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.902 ; -; 3.971 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 4.010 ; -; 4.268 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.307 ; -; 4.271 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.310 ; -; 4.398 ; RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.437 ; -; 4.447 ; Areg[3] ; RA[3]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 4.486 ; -; 4.475 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.514 ; -; 5.029 ; CS[2] ; SetRWBankFF ; C14M ; C14M ; 0.000 ; 0.000 ; 5.068 ; +; 3.144 ; UFMD[13] ; UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.183 ; +; 3.171 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.210 ; +; 3.189 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.228 ; +; 3.202 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.241 ; +; 3.376 ; RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.415 ; +; 3.377 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.416 ; +; 3.429 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.468 ; +; 3.435 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.474 ; +; 3.467 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.506 ; +; 3.468 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.507 ; +; 3.752 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.791 ; +; 3.800 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.839 ; +; 3.808 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.847 ; +; 3.817 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.856 ; +; 3.837 ; UFMD[11] ; RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.876 ; +; 3.865 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.904 ; +; 3.881 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.920 ; +; 3.972 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 4.011 ; +; 4.207 ; S[3] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.246 ; +; 4.867 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 4.906 ; +; 4.878 ; UFMEraseEN ; UFMEraseEN ; C14M ; C14M ; 0.000 ; 0.000 ; 4.917 ; +; 4.913 ; S[2] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.952 ; +; 4.935 ; FS[4] ; DRShift ; C14M ; C14M ; 0.000 ; 0.000 ; 4.974 ; +; 5.216 ; UFMPrgmEN ; UFMPrgmEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.255 ; ; 5.217 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ; -; 5.218 ; Areg[1] ; RA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.257 ; -; 5.228 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 5.267 ; -; 5.231 ; RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.270 ; -; 5.241 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.280 ; -; 5.243 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.282 ; +; 5.237 ; UFMReqErase ; UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.276 ; +; 5.242 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.281 ; ; 5.252 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.291 ; -; 5.268 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 5.307 ; -; 5.280 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.319 ; -; 5.283 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.322 ; -; 5.305 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.344 ; -; 5.315 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.354 ; -; 5.317 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.356 ; -; 5.317 ; UFMEraseEN ; UFMEraseEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.356 ; -; 5.326 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.365 ; -; 5.328 ; UFMPrgmEN ; UFMPrgmEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.367 ; -; 5.397 ; UFMD[11] ; RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.436 ; -; 5.419 ; Areg[2] ; RA[2]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.458 ; -; 5.429 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ; -; 5.429 ; RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.468 ; -; 5.430 ; Areg[7] ; RA[7]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.469 ; -; 5.433 ; Areg[0] ; RA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.472 ; -; 5.442 ; DRCLKPulse ; DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 5.481 ; +; 5.254 ; SetRWBankFF ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.293 ; +; 5.261 ; SetRWBankFF ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.300 ; +; 5.267 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.306 ; +; 5.270 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.309 ; +; 5.291 ; UFMInitDone ; DRShift ; C14M ; C14M ; 0.000 ; 0.000 ; 5.330 ; +; 5.291 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.330 ; +; 5.302 ; S[0] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.341 ; +; 5.372 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.411 ; +; 5.383 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.422 ; +; 5.419 ; RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.458 ; +; 5.421 ; RWBank[4] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.460 ; +; 5.441 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 5.480 ; +; 5.442 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.481 ; ; 5.452 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ; -; 5.452 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ; -; 5.456 ; S[3] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.495 ; -; 5.465 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 5.504 ; +; 5.453 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ; +; 5.463 ; UFMBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.502 ; ; 5.466 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.505 ; -; 5.473 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.512 ; -; 5.483 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.522 ; -; 5.490 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.529 ; -; 5.505 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.544 ; -; 5.507 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.546 ; -; 5.507 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.546 ; -; 5.509 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.548 ; -; 5.510 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.549 ; -; 5.676 ; UFMReqErase ; UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.715 ; -; 5.815 ; UFMPrgmEN ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.854 ; +; 5.486 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.525 ; +; 5.490 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.529 ; +; 5.496 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.535 ; +; 5.497 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.536 ; +; 5.509 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.548 ; +; 5.514 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.553 ; +; 5.520 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.559 ; +; 5.543 ; UFMReqErase ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.582 ; +; 5.545 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.584 ; +; 5.548 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.587 ; ; 5.952 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.991 ; +; 5.971 ; S[1] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.010 ; ; 5.987 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.026 ; -; 6.015 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.054 ; -; 6.018 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.057 ; -; 6.095 ; S[2] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.134 ; +; 6.002 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.041 ; +; 6.005 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.044 ; ; 6.096 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.135 ; ; 6.131 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.170 ; -; 6.159 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.198 ; -; 6.162 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.201 ; -; 6.242 ; RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.281 ; +; 6.146 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.185 ; +; 6.149 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.188 ; ; 6.275 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.314 ; -; 6.278 ; RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.317 ; -; 6.286 ; Areg[5] ; RA[5]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.325 ; -; 6.292 ; Areg[6] ; RA[6]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.331 ; -; 6.306 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.345 ; -; 6.396 ; UFMReqErase ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 6.435 ; -; 6.416 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.455 ; +; 6.287 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.326 ; +; 6.293 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.332 ; +; 6.295 ; UFMD[14] ; RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.334 ; ; 6.419 ; FS[8] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.458 ; -; 6.429 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.468 ; -; 6.433 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.472 ; -; 6.444 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.483 ; +; 6.444 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.483 ; ; 6.454 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ; -; 6.454 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ; -; 6.475 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.514 ; -; 6.484 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.523 ; -; 6.485 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.524 ; -; 6.493 ; CS[1] ; SetRWBankFF ; C14M ; C14M ; 0.000 ; 0.000 ; 6.532 ; -; 6.509 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.548 ; -; 6.515 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.554 ; -; 6.538 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.577 ; -; 6.595 ; S[2] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.634 ; +; 6.455 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.494 ; +; 6.487 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 6.526 ; +; 6.488 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.527 ; +; 6.498 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.537 ; +; 6.499 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.538 ; +; 6.516 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.555 ; +; 6.534 ; UFMD[13] ; RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.573 ; +; 6.538 ; RTPBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 6.577 ; ; 6.598 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ; -; 6.619 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.658 ; -; 6.623 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.662 ; -; 6.658 ; CS[0] ; SetRWBankFF ; C14M ; C14M ; 0.000 ; 0.000 ; 6.697 ; -; 6.682 ; Areg[4] ; RA[4]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.721 ; -; 6.692 ; UFMD[13] ; RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.731 ; -; 6.708 ; UFMD[12] ; RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.747 ; -; 6.720 ; RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.759 ; -; 6.759 ; RWBank[7] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.798 ; -; 6.763 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.802 ; -; 6.791 ; FS[0] ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 6.830 ; -; 6.795 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.834 ; -; 6.795 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.834 ; -; 6.795 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.834 ; +; 6.601 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.640 ; +; 6.642 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.681 ; +; 6.643 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.682 ; +; 6.652 ; RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.691 ; +; 6.782 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ; +; 6.782 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ; +; 6.782 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ; +; 6.786 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ; +; 6.787 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.826 ; +; 6.918 ; UFMPrgmEN ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 6.957 ; +; 6.929 ; FS[9] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ; +; 6.929 ; FS[9] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ; +; 6.929 ; FS[9] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ; +; 6.930 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.969 ; +; 6.930 ; FS[3] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.969 ; +; 7.023 ; FS[12] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ; +; 7.023 ; FS[12] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ; +; 7.023 ; FS[12] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ; +; 7.043 ; SetRWBankFF ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.082 ; +; 7.046 ; SetRWBankFF ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.085 ; +-------+-------------+-------------+--------------+-------------+--------------+------------+------------+ @@ -368,14 +368,6 @@ No paths to report. +--------+--------------+----------------+------------------+-------+------------+--------------+ ; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; ARCLK ; ; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; ARShift ; -; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[0] ; -; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[1] ; -; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[2] ; -; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[3] ; -; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[4] ; -; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[5] ; -; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[6] ; -; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Areg[7] ; ; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; BA[0]~reg0 ; ; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; BA[1]~reg0 ; ; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CKE~reg0 ; @@ -466,6 +458,14 @@ No paths to report. ; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMErase ; ; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMEraseEN ; ; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMInitDone ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMPrgmEN ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMProgram ; +; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMReqErase ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[0]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[1]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[2]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[3]~reg0 ; +; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[4]~reg0 ; +--------+--------------+----------------+------------------+-------+------------+--------------+ @@ -474,38 +474,38 @@ No paths to report. +-----------+------------+--------+--------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+--------+--------+------------+-----------------+ -; Ain[*] ; C14M ; 7.377 ; 7.377 ; Rise ; C14M ; -; Ain[0] ; C14M ; 6.262 ; 6.262 ; Rise ; C14M ; -; Ain[1] ; C14M ; 6.408 ; 6.408 ; Rise ; C14M ; -; Ain[2] ; C14M ; 7.028 ; 7.028 ; Rise ; C14M ; -; Ain[3] ; C14M ; 7.145 ; 7.145 ; Rise ; C14M ; -; Ain[4] ; C14M ; 6.972 ; 6.972 ; Rise ; C14M ; -; Ain[5] ; C14M ; 5.239 ; 5.239 ; Rise ; C14M ; -; Ain[6] ; C14M ; 7.377 ; 7.377 ; Rise ; C14M ; -; Ain[7] ; C14M ; 6.200 ; 6.200 ; Rise ; C14M ; -; Din[*] ; C14M ; 28.839 ; 28.839 ; Rise ; C14M ; -; Din[0] ; C14M ; 28.839 ; 28.839 ; Rise ; C14M ; -; Din[1] ; C14M ; 19.557 ; 19.557 ; Rise ; C14M ; -; Din[2] ; C14M ; 26.970 ; 26.970 ; Rise ; C14M ; -; Din[3] ; C14M ; 24.844 ; 24.844 ; Rise ; C14M ; -; Din[4] ; C14M ; 21.873 ; 21.873 ; Rise ; C14M ; -; Din[5] ; C14M ; 21.507 ; 21.507 ; Rise ; C14M ; -; Din[6] ; C14M ; 24.111 ; 24.111 ; Rise ; C14M ; -; Din[7] ; C14M ; 27.444 ; 27.444 ; Rise ; C14M ; -; PHI1 ; C14M ; 19.269 ; 19.269 ; Rise ; C14M ; -; nC07X ; C14M ; 8.188 ; 8.188 ; Rise ; C14M ; -; nEN80 ; C14M ; 10.690 ; 10.690 ; Rise ; C14M ; -; nWE ; C14M ; 11.021 ; 11.021 ; Rise ; C14M ; -; nWE80 ; C14M ; 7.374 ; 7.374 ; Rise ; C14M ; -; RD[*] ; C14M ; 8.565 ; 8.565 ; Fall ; C14M ; -; RD[0] ; C14M ; 6.593 ; 6.593 ; Fall ; C14M ; -; RD[1] ; C14M ; 7.115 ; 7.115 ; Fall ; C14M ; -; RD[2] ; C14M ; 8.565 ; 8.565 ; Fall ; C14M ; -; RD[3] ; C14M ; 6.929 ; 6.929 ; Fall ; C14M ; -; RD[4] ; C14M ; 5.109 ; 5.109 ; Fall ; C14M ; -; RD[5] ; C14M ; 7.262 ; 7.262 ; Fall ; C14M ; -; RD[6] ; C14M ; 6.928 ; 6.928 ; Fall ; C14M ; -; RD[7] ; C14M ; 7.016 ; 7.016 ; Fall ; C14M ; +; Ain[*] ; C14M ; 7.321 ; 7.321 ; Rise ; C14M ; +; Ain[0] ; C14M ; 6.351 ; 6.351 ; Rise ; C14M ; +; Ain[1] ; C14M ; 6.333 ; 6.333 ; Rise ; C14M ; +; Ain[2] ; C14M ; 5.149 ; 5.149 ; Rise ; C14M ; +; Ain[3] ; C14M ; 7.321 ; 7.321 ; Rise ; C14M ; +; Ain[4] ; C14M ; 5.426 ; 5.426 ; Rise ; C14M ; +; Ain[5] ; C14M ; 5.226 ; 5.226 ; Rise ; C14M ; +; Ain[6] ; C14M ; 5.188 ; 5.188 ; Rise ; C14M ; +; Ain[7] ; C14M ; 4.595 ; 4.595 ; Rise ; C14M ; +; Din[*] ; C14M ; 33.634 ; 33.634 ; Rise ; C14M ; +; Din[0] ; C14M ; 33.634 ; 33.634 ; Rise ; C14M ; +; Din[1] ; C14M ; 26.017 ; 26.017 ; Rise ; C14M ; +; Din[2] ; C14M ; 32.536 ; 32.536 ; Rise ; C14M ; +; Din[3] ; C14M ; 31.960 ; 31.960 ; Rise ; C14M ; +; Din[4] ; C14M ; 31.598 ; 31.598 ; Rise ; C14M ; +; Din[5] ; C14M ; 33.103 ; 33.103 ; Rise ; C14M ; +; Din[6] ; C14M ; 31.911 ; 31.911 ; Rise ; C14M ; +; Din[7] ; C14M ; 31.466 ; 31.466 ; Rise ; C14M ; +; PHI1 ; C14M ; 16.699 ; 16.699 ; Rise ; C14M ; +; nC07X ; C14M ; 9.809 ; 9.809 ; Rise ; C14M ; +; nEN80 ; C14M ; 10.700 ; 10.700 ; Rise ; C14M ; +; nWE ; C14M ; 11.877 ; 11.877 ; Rise ; C14M ; +; nWE80 ; C14M ; 10.141 ; 10.141 ; Rise ; C14M ; +; RD[*] ; C14M ; 8.337 ; 8.337 ; Fall ; C14M ; +; RD[0] ; C14M ; 6.777 ; 6.777 ; Fall ; C14M ; +; RD[1] ; C14M ; 7.239 ; 7.239 ; Fall ; C14M ; +; RD[2] ; C14M ; 8.337 ; 8.337 ; Fall ; C14M ; +; RD[3] ; C14M ; 7.110 ; 7.110 ; Fall ; C14M ; +; RD[4] ; C14M ; 4.993 ; 4.993 ; Fall ; C14M ; +; RD[5] ; C14M ; 7.210 ; 7.210 ; Fall ; C14M ; +; RD[6] ; C14M ; 7.056 ; 7.056 ; Fall ; C14M ; +; RD[7] ; C14M ; 6.879 ; 6.879 ; Fall ; C14M ; +-----------+------------+--------+--------+------------+-----------------+ @@ -514,38 +514,38 @@ No paths to report. +-----------+------------+---------+---------+------------+-----------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +-----------+------------+---------+---------+------------+-----------------+ -; Ain[*] ; C14M ; -4.775 ; -4.775 ; Rise ; C14M ; -; Ain[0] ; C14M ; -5.895 ; -5.895 ; Rise ; C14M ; -; Ain[1] ; C14M ; -6.047 ; -6.047 ; Rise ; C14M ; -; Ain[2] ; C14M ; -4.801 ; -4.801 ; Rise ; C14M ; -; Ain[3] ; C14M ; -6.614 ; -6.614 ; Rise ; C14M ; -; Ain[4] ; C14M ; -6.610 ; -6.610 ; Rise ; C14M ; -; Ain[5] ; C14M ; -4.777 ; -4.777 ; Rise ; C14M ; -; Ain[6] ; C14M ; -4.775 ; -4.775 ; Rise ; C14M ; -; Ain[7] ; C14M ; -5.839 ; -5.839 ; Rise ; C14M ; -; Din[*] ; C14M ; -3.466 ; -3.466 ; Rise ; C14M ; -; Din[0] ; C14M ; -4.971 ; -4.971 ; Rise ; C14M ; -; Din[1] ; C14M ; -5.127 ; -5.127 ; Rise ; C14M ; -; Din[2] ; C14M ; -3.470 ; -3.470 ; Rise ; C14M ; -; Din[3] ; C14M ; -3.466 ; -3.466 ; Rise ; C14M ; -; Din[4] ; C14M ; -5.273 ; -5.273 ; Rise ; C14M ; -; Din[5] ; C14M ; -7.331 ; -7.331 ; Rise ; C14M ; -; Din[6] ; C14M ; -5.028 ; -5.028 ; Rise ; C14M ; -; Din[7] ; C14M ; -5.011 ; -5.011 ; Rise ; C14M ; -; PHI1 ; C14M ; -4.691 ; -4.691 ; Rise ; C14M ; -; nC07X ; C14M ; -7.828 ; -7.828 ; Rise ; C14M ; -; nEN80 ; C14M ; -7.050 ; -7.050 ; Rise ; C14M ; -; nWE ; C14M ; -10.661 ; -10.661 ; Rise ; C14M ; -; nWE80 ; C14M ; -7.014 ; -7.014 ; Rise ; C14M ; -; RD[*] ; C14M ; -4.677 ; -4.677 ; Fall ; C14M ; -; RD[0] ; C14M ; -6.232 ; -6.232 ; Fall ; C14M ; -; RD[1] ; C14M ; -4.677 ; -4.677 ; Fall ; C14M ; -; RD[2] ; C14M ; -6.203 ; -6.203 ; Fall ; C14M ; -; RD[3] ; C14M ; -4.885 ; -4.885 ; Fall ; C14M ; -; RD[4] ; C14M ; -4.749 ; -4.749 ; Fall ; C14M ; -; RD[5] ; C14M ; -6.858 ; -6.858 ; Fall ; C14M ; -; RD[6] ; C14M ; -4.728 ; -4.728 ; Fall ; C14M ; -; RD[7] ; C14M ; -6.238 ; -6.238 ; Fall ; C14M ; +; Ain[*] ; C14M ; -4.235 ; -4.235 ; Rise ; C14M ; +; Ain[0] ; C14M ; -5.991 ; -5.991 ; Rise ; C14M ; +; Ain[1] ; C14M ; -5.973 ; -5.973 ; Rise ; C14M ; +; Ain[2] ; C14M ; -4.789 ; -4.789 ; Rise ; C14M ; +; Ain[3] ; C14M ; -6.961 ; -6.961 ; Rise ; C14M ; +; Ain[4] ; C14M ; -5.066 ; -5.066 ; Rise ; C14M ; +; Ain[5] ; C14M ; -4.866 ; -4.866 ; Rise ; C14M ; +; Ain[6] ; C14M ; -4.828 ; -4.828 ; Rise ; C14M ; +; Ain[7] ; C14M ; -4.235 ; -4.235 ; Rise ; C14M ; +; Din[*] ; C14M ; -3.392 ; -3.392 ; Rise ; C14M ; +; Din[0] ; C14M ; -4.985 ; -4.985 ; Rise ; C14M ; +; Din[1] ; C14M ; -5.364 ; -5.364 ; Rise ; C14M ; +; Din[2] ; C14M ; -5.191 ; -5.191 ; Rise ; C14M ; +; Din[3] ; C14M ; -3.524 ; -3.524 ; Rise ; C14M ; +; Din[4] ; C14M ; -6.903 ; -6.903 ; Rise ; C14M ; +; Din[5] ; C14M ; -8.900 ; -8.900 ; Rise ; C14M ; +; Din[6] ; C14M ; -5.049 ; -5.049 ; Rise ; C14M ; +; Din[7] ; C14M ; -3.392 ; -3.392 ; Rise ; C14M ; +; PHI1 ; C14M ; -6.474 ; -6.474 ; Rise ; C14M ; +; nC07X ; C14M ; -9.449 ; -9.449 ; Rise ; C14M ; +; nEN80 ; C14M ; -8.428 ; -8.428 ; Rise ; C14M ; +; nWE ; C14M ; -11.517 ; -11.517 ; Rise ; C14M ; +; nWE80 ; C14M ; -9.781 ; -9.781 ; Rise ; C14M ; +; RD[*] ; C14M ; -4.631 ; -4.631 ; Fall ; C14M ; +; RD[0] ; C14M ; -6.415 ; -6.415 ; Fall ; C14M ; +; RD[1] ; C14M ; -6.551 ; -6.551 ; Fall ; C14M ; +; RD[2] ; C14M ; -6.279 ; -6.279 ; Fall ; C14M ; +; RD[3] ; C14M ; -4.745 ; -4.745 ; Fall ; C14M ; +; RD[4] ; C14M ; -4.631 ; -4.631 ; Fall ; C14M ; +; RD[5] ; C14M ; -6.798 ; -6.798 ; Fall ; C14M ; +; RD[6] ; C14M ; -4.782 ; -4.782 ; Fall ; C14M ; +; RD[7] ; C14M ; -4.806 ; -4.806 ; Fall ; C14M ; +-----------+------------+---------+---------+------------+-----------------+ @@ -558,44 +558,44 @@ No paths to report. ; BA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; ; BA[1] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; ; CKE ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; -; DQMH ; C14M ; 20.694 ; 20.694 ; Rise ; C14M ; -; DQML ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ; -; RA[*] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; -; RA[0] ; C14M ; 17.421 ; 17.421 ; Rise ; C14M ; -; RA[1] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; -; RA[2] ; C14M ; 17.350 ; 17.350 ; Rise ; C14M ; -; RA[3] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ; -; RA[4] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; DQMH ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ; +; DQML ; C14M ; 22.954 ; 22.954 ; Rise ; C14M ; +; RA[*] ; C14M ; 21.367 ; 21.367 ; Rise ; C14M ; +; RA[0] ; C14M ; 21.367 ; 21.367 ; Rise ; C14M ; +; RA[1] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; RA[2] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ; +; RA[3] ; C14M ; 21.293 ; 21.293 ; Rise ; C14M ; +; RA[4] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ; ; RA[5] ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ; ; RA[6] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; ; RA[7] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; ; RA[8] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ; -; RA[9] ; C14M ; 17.382 ; 17.382 ; Rise ; C14M ; +; RA[9] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; ; RA[10] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ; ; RA[11] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; -; nCAS ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; +; nCAS ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; ; nCS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; -; nDOE ; C14M ; 23.226 ; 23.226 ; Rise ; C14M ; +; nDOE ; C14M ; 28.930 ; 28.930 ; Rise ; C14M ; ; nRAS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; -; nRWE ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; nRWE ; C14M ; 21.334 ; 21.334 ; Rise ; C14M ; ; Dout[*] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ; -; Dout[0] ; C14M ; 17.336 ; 17.336 ; Fall ; C14M ; -; Dout[1] ; C14M ; 17.368 ; 17.368 ; Fall ; C14M ; +; Dout[0] ; C14M ; 17.365 ; 17.365 ; Fall ; C14M ; +; Dout[1] ; C14M ; 17.383 ; 17.383 ; Fall ; C14M ; ; Dout[2] ; C14M ; 19.308 ; 19.308 ; Fall ; C14M ; ; Dout[3] ; C14M ; 17.362 ; 17.362 ; Fall ; C14M ; ; Dout[4] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ; ; Dout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; ; Dout[6] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ; ; Dout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; -; Vout[*] ; C14M ; 17.350 ; 17.350 ; Fall ; C14M ; -; Vout[0] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; -; Vout[1] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; -; Vout[2] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ; +; Vout[*] ; C14M ; 19.325 ; 19.325 ; Fall ; C14M ; +; Vout[0] ; C14M ; 17.341 ; 17.341 ; Fall ; C14M ; +; Vout[1] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ; +; Vout[2] ; C14M ; 19.325 ; 19.325 ; Fall ; C14M ; ; Vout[3] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ; -; Vout[4] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; -; Vout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[4] ; C14M ; 17.341 ; 17.341 ; Fall ; C14M ; +; Vout[5] ; C14M ; 19.307 ; 19.307 ; Fall ; C14M ; ; Vout[6] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; -; Vout[7] ; C14M ; 17.350 ; 17.350 ; Fall ; C14M ; +; Vout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +-----------+------------+--------+--------+------------+-----------------+ @@ -608,29 +608,29 @@ No paths to report. ; BA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; ; BA[1] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; ; CKE ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; -; DQMH ; C14M ; 20.694 ; 20.694 ; Rise ; C14M ; -; DQML ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ; -; RA[*] ; C14M ; 17.350 ; 17.350 ; Rise ; C14M ; -; RA[0] ; C14M ; 17.421 ; 17.421 ; Rise ; C14M ; -; RA[1] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; -; RA[2] ; C14M ; 17.350 ; 17.350 ; Rise ; C14M ; -; RA[3] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ; -; RA[4] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; DQMH ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ; +; DQML ; C14M ; 22.954 ; 22.954 ; Rise ; C14M ; +; RA[*] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ; +; RA[0] ; C14M ; 21.367 ; 21.367 ; Rise ; C14M ; +; RA[1] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; +; RA[2] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ; +; RA[3] ; C14M ; 21.293 ; 21.293 ; Rise ; C14M ; +; RA[4] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ; ; RA[5] ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ; ; RA[6] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; ; RA[7] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; ; RA[8] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ; -; RA[9] ; C14M ; 17.382 ; 17.382 ; Rise ; C14M ; +; RA[9] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; ; RA[10] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ; ; RA[11] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; -; nCAS ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ; +; nCAS ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; ; nCS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; -; nDOE ; C14M ; 23.226 ; 23.226 ; Rise ; C14M ; +; nDOE ; C14M ; 28.930 ; 28.930 ; Rise ; C14M ; ; nRAS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ; -; nRWE ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ; +; nRWE ; C14M ; 21.334 ; 21.334 ; Rise ; C14M ; ; Dout[*] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; -; Dout[0] ; C14M ; 17.336 ; 17.336 ; Fall ; C14M ; -; Dout[1] ; C14M ; 17.368 ; 17.368 ; Fall ; C14M ; +; Dout[0] ; C14M ; 17.365 ; 17.365 ; Fall ; C14M ; +; Dout[1] ; C14M ; 17.383 ; 17.383 ; Fall ; C14M ; ; Dout[2] ; C14M ; 19.308 ; 19.308 ; Fall ; C14M ; ; Dout[3] ; C14M ; 17.362 ; 17.362 ; Fall ; C14M ; ; Dout[4] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ; @@ -638,14 +638,14 @@ No paths to report. ; Dout[6] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ; ; Dout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; ; Vout[*] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; -; Vout[0] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; -; Vout[1] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; -; Vout[2] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ; +; Vout[0] ; C14M ; 17.341 ; 17.341 ; Fall ; C14M ; +; Vout[1] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ; +; Vout[2] ; C14M ; 19.325 ; 19.325 ; Fall ; C14M ; ; Vout[3] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ; -; Vout[4] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; -; Vout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +; Vout[4] ; C14M ; 17.341 ; 17.341 ; Fall ; C14M ; +; Vout[5] ; C14M ; 19.307 ; 19.307 ; Fall ; C14M ; ; Vout[6] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; -; Vout[7] ; C14M ; 17.350 ; 17.350 ; Fall ; C14M ; +; Vout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ; +-----------+------------+--------+--------+------------+-----------------+ @@ -654,33 +654,33 @@ No paths to report. +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; Din[0] ; RD[0] ; 19.349 ; ; ; 19.349 ; -; Din[1] ; RD[1] ; 19.378 ; ; ; 19.378 ; -; Din[2] ; RD[2] ; 21.534 ; ; ; 21.534 ; -; Din[3] ; RD[3] ; 19.335 ; ; ; 19.335 ; -; Din[4] ; RD[4] ; 21.330 ; ; ; 21.330 ; -; Din[5] ; RD[5] ; 21.614 ; ; ; 21.614 ; -; Din[6] ; RD[6] ; 19.625 ; ; ; 19.625 ; -; Din[7] ; RD[7] ; 19.254 ; ; ; 19.254 ; -; PHI1 ; nVOE ; 22.494 ; ; ; 22.494 ; -; nEN80 ; RD[0] ; 19.829 ; ; ; 19.829 ; -; nEN80 ; RD[1] ; 21.564 ; ; ; 21.564 ; -; nEN80 ; RD[2] ; 19.829 ; ; ; 19.829 ; -; nEN80 ; RD[3] ; 21.564 ; ; ; 21.564 ; -; nEN80 ; RD[4] ; 21.564 ; ; ; 21.564 ; -; nEN80 ; RD[5] ; 19.829 ; ; ; 19.829 ; -; nEN80 ; RD[6] ; 19.829 ; ; ; 19.829 ; -; nEN80 ; RD[7] ; 19.829 ; ; ; 19.829 ; -; nEN80 ; nDOE ; 27.166 ; ; ; 27.166 ; -; nWE ; nDOE ; 24.346 ; ; ; 24.346 ; -; nWE80 ; RD[0] ; 22.991 ; ; ; 22.991 ; -; nWE80 ; RD[1] ; 24.726 ; ; ; 24.726 ; -; nWE80 ; RD[2] ; 22.991 ; ; ; 22.991 ; -; nWE80 ; RD[3] ; 24.726 ; ; ; 24.726 ; -; nWE80 ; RD[4] ; 24.726 ; ; ; 24.726 ; -; nWE80 ; RD[5] ; 22.991 ; ; ; 22.991 ; -; nWE80 ; RD[6] ; 22.991 ; ; ; 22.991 ; -; nWE80 ; RD[7] ; 22.991 ; ; ; 22.991 ; +; Din[0] ; RD[0] ; 19.492 ; ; ; 19.492 ; +; Din[1] ; RD[1] ; 19.340 ; ; ; 19.340 ; +; Din[2] ; RD[2] ; 21.309 ; ; ; 21.309 ; +; Din[3] ; RD[3] ; 19.308 ; ; ; 19.308 ; +; Din[4] ; RD[4] ; 21.375 ; ; ; 21.375 ; +; Din[5] ; RD[5] ; 21.226 ; ; ; 21.226 ; +; Din[6] ; RD[6] ; 19.287 ; ; ; 19.287 ; +; Din[7] ; RD[7] ; 19.338 ; ; ; 19.338 ; +; PHI1 ; nVOE ; 22.914 ; ; ; 22.914 ; +; nEN80 ; RD[0] ; 20.792 ; ; ; 20.792 ; +; nEN80 ; RD[1] ; 21.290 ; ; ; 21.290 ; +; nEN80 ; RD[2] ; 20.792 ; ; ; 20.792 ; +; nEN80 ; RD[3] ; 21.290 ; ; ; 21.290 ; +; nEN80 ; RD[4] ; 21.290 ; ; ; 21.290 ; +; nEN80 ; RD[5] ; 20.792 ; ; ; 20.792 ; +; nEN80 ; RD[6] ; 20.792 ; ; ; 20.792 ; +; nEN80 ; RD[7] ; 20.792 ; ; ; 20.792 ; +; nEN80 ; nDOE ; 25.564 ; ; ; 25.564 ; +; nWE ; nDOE ; 26.039 ; ; ; 26.039 ; +; nWE80 ; RD[0] ; 19.810 ; ; ; 19.810 ; +; nWE80 ; RD[1] ; 20.308 ; ; ; 20.308 ; +; nWE80 ; RD[2] ; 19.810 ; ; ; 19.810 ; +; nWE80 ; RD[3] ; 20.308 ; ; ; 20.308 ; +; nWE80 ; RD[4] ; 20.308 ; ; ; 20.308 ; +; nWE80 ; RD[5] ; 19.810 ; ; ; 19.810 ; +; nWE80 ; RD[6] ; 19.810 ; ; ; 19.810 ; +; nWE80 ; RD[7] ; 19.810 ; ; ; 19.810 ; +------------+-------------+--------+----+----+--------+ @@ -689,33 +689,33 @@ No paths to report. +------------+-------------+--------+----+----+--------+ ; Input Port ; Output Port ; RR ; RF ; FR ; FF ; +------------+-------------+--------+----+----+--------+ -; Din[0] ; RD[0] ; 19.349 ; ; ; 19.349 ; -; Din[1] ; RD[1] ; 19.378 ; ; ; 19.378 ; -; Din[2] ; RD[2] ; 21.534 ; ; ; 21.534 ; -; Din[3] ; RD[3] ; 19.335 ; ; ; 19.335 ; -; Din[4] ; RD[4] ; 21.330 ; ; ; 21.330 ; -; Din[5] ; RD[5] ; 21.614 ; ; ; 21.614 ; -; Din[6] ; RD[6] ; 19.625 ; ; ; 19.625 ; -; Din[7] ; RD[7] ; 19.254 ; ; ; 19.254 ; -; PHI1 ; nVOE ; 22.494 ; ; ; 22.494 ; -; nEN80 ; RD[0] ; 19.829 ; ; ; 19.829 ; -; nEN80 ; RD[1] ; 21.564 ; ; ; 21.564 ; -; nEN80 ; RD[2] ; 19.829 ; ; ; 19.829 ; -; nEN80 ; RD[3] ; 21.564 ; ; ; 21.564 ; -; nEN80 ; RD[4] ; 21.564 ; ; ; 21.564 ; -; nEN80 ; RD[5] ; 19.829 ; ; ; 19.829 ; -; nEN80 ; RD[6] ; 19.829 ; ; ; 19.829 ; -; nEN80 ; RD[7] ; 19.829 ; ; ; 19.829 ; -; nEN80 ; nDOE ; 27.166 ; ; ; 27.166 ; -; nWE ; nDOE ; 24.346 ; ; ; 24.346 ; -; nWE80 ; RD[0] ; 22.991 ; ; ; 22.991 ; -; nWE80 ; RD[1] ; 24.726 ; ; ; 24.726 ; -; nWE80 ; RD[2] ; 22.991 ; ; ; 22.991 ; -; nWE80 ; RD[3] ; 24.726 ; ; ; 24.726 ; -; nWE80 ; RD[4] ; 24.726 ; ; ; 24.726 ; -; nWE80 ; RD[5] ; 22.991 ; ; ; 22.991 ; -; nWE80 ; RD[6] ; 22.991 ; ; ; 22.991 ; -; nWE80 ; RD[7] ; 22.991 ; ; ; 22.991 ; +; Din[0] ; RD[0] ; 19.492 ; ; ; 19.492 ; +; Din[1] ; RD[1] ; 19.340 ; ; ; 19.340 ; +; Din[2] ; RD[2] ; 21.309 ; ; ; 21.309 ; +; Din[3] ; RD[3] ; 19.308 ; ; ; 19.308 ; +; Din[4] ; RD[4] ; 21.375 ; ; ; 21.375 ; +; Din[5] ; RD[5] ; 21.226 ; ; ; 21.226 ; +; Din[6] ; RD[6] ; 19.287 ; ; ; 19.287 ; +; Din[7] ; RD[7] ; 19.338 ; ; ; 19.338 ; +; PHI1 ; nVOE ; 22.914 ; ; ; 22.914 ; +; nEN80 ; RD[0] ; 20.792 ; ; ; 20.792 ; +; nEN80 ; RD[1] ; 21.290 ; ; ; 21.290 ; +; nEN80 ; RD[2] ; 20.792 ; ; ; 20.792 ; +; nEN80 ; RD[3] ; 21.290 ; ; ; 21.290 ; +; nEN80 ; RD[4] ; 21.290 ; ; ; 21.290 ; +; nEN80 ; RD[5] ; 20.792 ; ; ; 20.792 ; +; nEN80 ; RD[6] ; 20.792 ; ; ; 20.792 ; +; nEN80 ; RD[7] ; 20.792 ; ; ; 20.792 ; +; nEN80 ; nDOE ; 25.564 ; ; ; 25.564 ; +; nWE ; nDOE ; 26.039 ; ; ; 26.039 ; +; nWE80 ; RD[0] ; 19.810 ; ; ; 19.810 ; +; nWE80 ; RD[1] ; 20.308 ; ; ; 20.308 ; +; nWE80 ; RD[2] ; 19.810 ; ; ; 19.810 ; +; nWE80 ; RD[3] ; 20.308 ; ; ; 20.308 ; +; nWE80 ; RD[4] ; 20.308 ; ; ; 20.308 ; +; nWE80 ; RD[5] ; 19.810 ; ; ; 19.810 ; +; nWE80 ; RD[6] ; 19.810 ; ; ; 19.810 ; +; nWE80 ; RD[7] ; 19.810 ; ; ; 19.810 ; +------------+-------------+--------+----+----+--------+ @@ -724,7 +724,7 @@ No paths to report. +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C14M ; C14M ; 1432 ; 0 ; 64 ; 0 ; +; C14M ; C14M ; 1358 ; 0 ; 64 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -734,7 +734,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not +------------+----------+----------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +------------+----------+----------+----------+----------+----------+ -; C14M ; C14M ; 1432 ; 0 ; 64 ; 0 ; +; C14M ; C14M ; 1358 ; 0 ; 64 ; 0 ; +------------+----------+----------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. @@ -759,7 +759,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 2 ; 2 ; ; Unconstrained Input Ports ; 29 ; 29 ; -; Unconstrained Input Port Paths ; 151 ; 151 ; +; Unconstrained Input Port Paths ; 143 ; 143 ; ; Unconstrained Output Ports ; 47 ; 47 ; ; Unconstrained Output Port Paths ; 65 ; 65 ; +---------------------------------+-------+------+ @@ -771,7 +771,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design Info: ******************************************************************* Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition - Info: Processing started: Wed Sep 16 19:34:50 2020 + Info: Processing started: Wed Sep 16 20:14:42 2020 Info: Command: quartus_sta RAM2E -c RAM2E Info: qsta_default_script.tcl version: #1 Warning (20028): Parallel compilation is not licensed and has been disabled @@ -783,14 +783,14 @@ Info (332104): Reading SDC File: 'constraints.sdc' Warning (332060): Node: DRCLK was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: ARCLK was determined to be a clock but was found without an associated clock assignment. Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON -Info (332146): Worst-case setup slack is 22.294 +Info (332146): Worst-case setup slack is 21.694 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 22.294 0.000 C14M -Info (332146): Worst-case hold slack is 3.117 + Info (332119): 21.694 0.000 C14M +Info (332146): Worst-case hold slack is 3.144 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== - Info (332119): 3.117 0.000 C14M + Info (332119): 3.144 0.000 C14M Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 34.581 @@ -802,7 +802,7 @@ Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings Info: Peak virtual memory: 4522 megabytes - Info: Processing ended: Wed Sep 16 19:34:51 2020 + Info: Processing ended: Wed Sep 16 20:14:43 2020 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 diff --git a/cpld/output_files/RAM2E.sta.summary b/cpld/output_files/RAM2E.sta.summary index 5c627cc..8e64d7f 100755 --- a/cpld/output_files/RAM2E.sta.summary +++ b/cpld/output_files/RAM2E.sta.summary @@ -3,11 +3,11 @@ TimeQuest Timing Analyzer Summary ------------------------------------------------------------ Type : Setup 'C14M' -Slack : 22.294 +Slack : 21.694 TNS : 0.000 Type : Hold 'C14M' -Slack : 3.117 +Slack : 3.144 TNS : 0.000 Type : Minimum Pulse Width 'C14M'