diff --git a/.gitignore b/.gitignore
index 90e68eb..83814ac 100644
--- a/.gitignore
+++ b/.gitignore
@@ -27,3 +27,4 @@ fp-info-cache
*.DS_Store
Documentation/~$4203BManual.docx
+*.cdf
diff --git a/cpld/RAM2E.qsf b/cpld/RAM2E.qsf
index 43d7247..c9ec12d 100755
--- a/cpld/RAM2E.qsf
+++ b/cpld/RAM2E.qsf
@@ -36,8 +36,8 @@
# -------------------------------------------------------------------------- #
-set_global_assignment -name FAMILY "MAX V"
-set_global_assignment -name DEVICE 5M240ZT100C5
+set_global_assignment -name FAMILY "MAX II"
+set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY RAM2E
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:58:44 MAY 05, 2020"
diff --git a/cpld/RAM2E.qws b/cpld/RAM2E.qws
index 0d77c12..ab951d3 100644
Binary files a/cpld/RAM2E.qws and b/cpld/RAM2E.qws differ
diff --git a/cpld/UFM.v b/cpld/UFM.v
index 613c750..ec5b564 100755
--- a/cpld/UFM.v
+++ b/cpld/UFM.v
@@ -9,7 +9,7 @@
// ALTUFM_NONE
//
// Simulation Library Files(s):
-// maxv
+// maxii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
@@ -33,17 +33,17 @@
//applicable agreement for further details.
-//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX V" ERASE_TIME=500000000 LPM_FILE="RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
+//altufm_none CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="MAX II" ERASE_TIME=500000000 LPM_FILE="RAM2E.mif" OSC_FREQUENCY=180000 PORT_ARCLKENA="PORT_UNUSED" PORT_DRCLKENA="PORT_UNUSED" PROGRAM_TIME=1600000 WIDTH_UFM_ADDRESS=9 arclk ardin arshft busy drclk drdin drdout drshft erase osc oscena program rtpbusy
//VERSION_BEGIN 13.0 cbx_a_gray2bin 2013:06:12:18:03:43:SJ cbx_a_graycounter 2013:06:12:18:03:43:SJ cbx_altufm_none 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_counter 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_maxii 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
-//synthesis_resources = maxv_ufm 1
+//synthesis_resources = maxii_ufm 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
-module UFM_altufm_none_e4r
+module UFM_altufm_none_a7r
(
arclk,
ardin,
@@ -90,7 +90,7 @@ module UFM_altufm_none_e4r
wire ufm_oscena;
wire ufm_program;
- maxv_ufm maxii_ufm_block1
+ maxii_ufm maxii_ufm_block1
(
.arclk(ufm_arclk),
.ardin(ufm_ardin),
@@ -136,7 +136,7 @@ module UFM_altufm_none_e4r
maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF,
maxii_ufm_block1.osc_sim_setting = 180000,
maxii_ufm_block1.program_time = 1600000,
- maxii_ufm_block1.lpm_type = "maxv_ufm";
+ maxii_ufm_block1.lpm_type = "maxii_ufm";
assign
busy = ufm_busy,
drdout = ufm_drdout,
@@ -155,7 +155,7 @@ module UFM_altufm_none_e4r
ufm_osc = wire_maxii_ufm_block1_osc,
ufm_oscena = oscena,
ufm_program = program;
-endmodule //UFM_altufm_none_e4r
+endmodule //UFM_altufm_none_a7r
//VALID FILE
@@ -200,7 +200,7 @@ module UFM (
wire drdout = sub_wire2;
wire busy = sub_wire3;
- UFM_altufm_none_e4r UFM_altufm_none_e4r_component (
+ UFM_altufm_none_a7r UFM_altufm_none_a7r_component (
.arshft (arshft),
.drclk (drclk),
.erase (erase),
@@ -221,9 +221,9 @@ endmodule
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX V"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: ERASE_TIME NUMERIC "500000000"
-// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX V"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: LPM_FILE STRING "RAM2E.mif"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altufm_none"
@@ -265,4 +265,4 @@ endmodule
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE TRUE
-// Retrieval info: LIB_FILE: maxv
+// Retrieval info: LIB_FILE: maxii
diff --git a/cpld/db/RAM2E.(0).cnf.cdb b/cpld/db/RAM2E.(0).cnf.cdb
index 4187f8c..f8329f8 100755
Binary files a/cpld/db/RAM2E.(0).cnf.cdb and b/cpld/db/RAM2E.(0).cnf.cdb differ
diff --git a/cpld/db/RAM2E.(0).cnf.hdb b/cpld/db/RAM2E.(0).cnf.hdb
index 0728203..246465c 100755
Binary files a/cpld/db/RAM2E.(0).cnf.hdb and b/cpld/db/RAM2E.(0).cnf.hdb differ
diff --git a/cpld/db/RAM2E.(1).cnf.cdb b/cpld/db/RAM2E.(1).cnf.cdb
index 0b992e0..8882e09 100755
Binary files a/cpld/db/RAM2E.(1).cnf.cdb and b/cpld/db/RAM2E.(1).cnf.cdb differ
diff --git a/cpld/db/RAM2E.(1).cnf.hdb b/cpld/db/RAM2E.(1).cnf.hdb
index eea97fb..937adb6 100755
Binary files a/cpld/db/RAM2E.(1).cnf.hdb and b/cpld/db/RAM2E.(1).cnf.hdb differ
diff --git a/cpld/db/RAM2E.(2).cnf.cdb b/cpld/db/RAM2E.(2).cnf.cdb
index 2b5e8b5..093c6b9 100755
Binary files a/cpld/db/RAM2E.(2).cnf.cdb and b/cpld/db/RAM2E.(2).cnf.cdb differ
diff --git a/cpld/db/RAM2E.(2).cnf.hdb b/cpld/db/RAM2E.(2).cnf.hdb
index 5fc8aeb..77fea6d 100755
Binary files a/cpld/db/RAM2E.(2).cnf.hdb and b/cpld/db/RAM2E.(2).cnf.hdb differ
diff --git a/cpld/db/RAM2E.asm.qmsg b/cpld/db/RAM2E.asm.qmsg
index b30f19f..4deffde 100755
--- a/cpld/db/RAM2E.asm.qmsg
+++ b/cpld/db/RAM2E.asm.qmsg
@@ -1,6 +1,6 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600301681638 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301681638 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:41 2020 " "Processing started: Wed Sep 16 20:14:41 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301681638 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1600301681638 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1600301681638 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1600301681798 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1600301681798 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4524 " "Peak virtual memory: 4524 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301681918 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:41 2020 " "Processing ended: Wed Sep 16 20:14:41 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301681918 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301681918 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301681918 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1600301681918 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1611862639806 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1611862639807 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 28 14:37:19 2021 " "Processing started: Thu Jan 28 14:37:19 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1611862639807 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1611862639807 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1611862639807 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1611862640167 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1611862640175 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4515 " "Peak virtual memory: 4515 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862640491 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:37:20 2021 " "Processing ended: Thu Jan 28 14:37:20 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862640491 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862640491 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862640491 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1611862640491 ""}
diff --git a/cpld/db/RAM2E.asm.rdb b/cpld/db/RAM2E.asm.rdb
index 9584e4f..41717f2 100755
Binary files a/cpld/db/RAM2E.asm.rdb and b/cpld/db/RAM2E.asm.rdb differ
diff --git a/cpld/db/RAM2E.asm_labs.ddb b/cpld/db/RAM2E.asm_labs.ddb
index 0bb936d..2a67376 100755
Binary files a/cpld/db/RAM2E.asm_labs.ddb and b/cpld/db/RAM2E.asm_labs.ddb differ
diff --git a/cpld/db/RAM2E.cmp.cdb b/cpld/db/RAM2E.cmp.cdb
index c63d6f9..422acc9 100755
Binary files a/cpld/db/RAM2E.cmp.cdb and b/cpld/db/RAM2E.cmp.cdb differ
diff --git a/cpld/db/RAM2E.cmp.hdb b/cpld/db/RAM2E.cmp.hdb
index b262b4c..7dcb3ab 100755
Binary files a/cpld/db/RAM2E.cmp.hdb and b/cpld/db/RAM2E.cmp.hdb differ
diff --git a/cpld/db/RAM2E.cmp.idb b/cpld/db/RAM2E.cmp.idb
index 7efc515..46afab4 100755
Binary files a/cpld/db/RAM2E.cmp.idb and b/cpld/db/RAM2E.cmp.idb differ
diff --git a/cpld/db/RAM2E.cmp.rdb b/cpld/db/RAM2E.cmp.rdb
index a3ec835..23e1c50 100755
Binary files a/cpld/db/RAM2E.cmp.rdb and b/cpld/db/RAM2E.cmp.rdb differ
diff --git a/cpld/db/RAM2E.cmp0.ddb b/cpld/db/RAM2E.cmp0.ddb
index 3aa51cb..e84a239 100755
Binary files a/cpld/db/RAM2E.cmp0.ddb and b/cpld/db/RAM2E.cmp0.ddb differ
diff --git a/cpld/db/RAM2E.db_info b/cpld/db/RAM2E.db_info
index 5367950..26eaa57 100755
--- a/cpld/db/RAM2E.db_info
+++ b/cpld/db/RAM2E.db_info
@@ -1,3 +1,3 @@
Quartus_Version = Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
Version_Index = 302049280
-Creation_Time = Wed Sep 16 19:59:46 2020
+Creation_Time = Thu Jan 28 14:22:50 2021
diff --git a/cpld/db/RAM2E.fit.qmsg b/cpld/db/RAM2E.fit.qmsg
index c9e12d8..224c92d 100755
--- a/cpld/db/RAM2E.fit.qmsg
+++ b/cpld/db/RAM2E.fit.qmsg
@@ -1,38 +1,39 @@
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1600301679744 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1600301679744 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600301679774 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600301679774 ""}
-{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1600301679804 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1600301679814 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301679864 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1600301679864 ""}
-{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1600301679924 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600301679934 "|RAM2E|DRCLK"}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600301679934 "|RAM2E|ARCLK"}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1600301679934 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301679934 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301679934 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301679934 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1600301679934 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600301679934 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600301679934 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600301679934 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1600301679944 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600301679944 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1600301679944 ""}
-{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1600301679954 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1600301679954 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1600301679974 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1600301679974 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1600301679974 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1600301679974 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301679994 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1600301680064 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301680194 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1600301680194 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1600301680404 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301680404 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1600301680424 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1600301680564 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1600301680564 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301680682 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.13 " "Total time spent on timing analysis during the Fitter is 0.13 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1600301680690 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301680690 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1600301680712 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1600301680752 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4767 " "Peak virtual memory: 4767 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301680812 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:40 2020 " "Processing ended: Wed Sep 16 20:14:40 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301680812 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301680812 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301680812 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1600301680812 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1611862636770 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1611862636774 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611862636827 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611862636827 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1611862636909 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1611862636923 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862637106 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862637106 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862637106 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862637106 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862637106 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1611862637106 ""}
+{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1611862637227 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1611862637232 "|RAM2E|DRCLK"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1611862637232 "|RAM2E|ARCLK"}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1611862637235 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1611862637235 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1611862637235 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1611862637235 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1611862637235 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611862637238 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611862637239 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1611862637243 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1611862637251 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1611862637252 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1611862637254 ""}
+{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1611862637276 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1611862637277 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1611862637311 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1611862637313 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1611862637314 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1611862637314 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862637364 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1611862637478 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862637674 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1611862637685 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1611862638084 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862638084 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1611862638125 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "4e+01 ns 2.6% " "4e+01 ns of routing delay (approximately 2.6% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1611862638337 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1611862638383 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1611862638383 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862638534 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1611862638544 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862638548 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1611862638586 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1611862638665 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4758 " "Peak virtual memory: 4758 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862638764 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:37:18 2021 " "Processing ended: Thu Jan 28 14:37:18 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862638764 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862638764 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862638764 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1611862638764 ""}
diff --git a/cpld/db/RAM2E.hier_info b/cpld/db/RAM2E.hier_info
index cba7dd3..1472b2a 100755
--- a/cpld/db/RAM2E.hier_info
+++ b/cpld/db/RAM2E.hier_info
@@ -326,13 +326,13 @@ drshft => drshft.IN1
erase => erase.IN1
oscena => oscena.IN1
program => program.IN1
-busy <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.busy
-drdout <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.drdout
-osc <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.osc
-rtpbusy <= UFM_altufm_none_e4r:UFM_altufm_none_e4r_component.rtpbusy
+busy <= UFM_altufm_none_a7r:UFM_altufm_none_a7r_component.busy
+drdout <= UFM_altufm_none_a7r:UFM_altufm_none_a7r_component.drdout
+osc <= UFM_altufm_none_a7r:UFM_altufm_none_a7r_component.osc
+rtpbusy <= UFM_altufm_none_a7r:UFM_altufm_none_a7r_component.rtpbusy
-|RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component
+|RAM2E|UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component
arclk => maxii_ufm_block1.ARCLK
ardin => maxii_ufm_block1.ARDIN
arshft => maxii_ufm_block1.ARSHFT
diff --git a/cpld/db/RAM2E.hif b/cpld/db/RAM2E.hif
index 584c4e4..86c3704 100755
Binary files a/cpld/db/RAM2E.hif and b/cpld/db/RAM2E.hif differ
diff --git a/cpld/db/RAM2E.ipinfo b/cpld/db/RAM2E.ipinfo
index b9c2697..f61d3e4 100755
Binary files a/cpld/db/RAM2E.ipinfo and b/cpld/db/RAM2E.ipinfo differ
diff --git a/cpld/db/RAM2E.lpc.html b/cpld/db/RAM2E.lpc.html
index a8acc8f..dc80195 100755
--- a/cpld/db/RAM2E.lpc.html
+++ b/cpld/db/RAM2E.lpc.html
@@ -16,7 +16,7 @@
| Output only Bidir |
-| UFM_inst|UFM_altufm_none_e4r_component |
+UFM_inst|UFM_altufm_none_a7r_component |
9 |
0 |
0 |
diff --git a/cpld/db/RAM2E.lpc.rdb b/cpld/db/RAM2E.lpc.rdb
index 97e4bf1..6502319 100755
Binary files a/cpld/db/RAM2E.lpc.rdb and b/cpld/db/RAM2E.lpc.rdb differ
diff --git a/cpld/db/RAM2E.lpc.txt b/cpld/db/RAM2E.lpc.txt
index 9ebe4ce..686f237 100755
--- a/cpld/db/RAM2E.lpc.txt
+++ b/cpld/db/RAM2E.lpc.txt
@@ -3,6 +3,6 @@
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; UFM_inst|UFM_altufm_none_e4r_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+; UFM_inst|UFM_altufm_none_a7r_component ; 9 ; 0 ; 0 ; 0 ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; UFM_inst ; 9 ; 2 ; 0 ; 2 ; 4 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+----------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/cpld/db/RAM2E.map.cdb b/cpld/db/RAM2E.map.cdb
index 78c1b51..2a9c12b 100755
Binary files a/cpld/db/RAM2E.map.cdb and b/cpld/db/RAM2E.map.cdb differ
diff --git a/cpld/db/RAM2E.map.hdb b/cpld/db/RAM2E.map.hdb
index dcb1aaa..525931e 100755
Binary files a/cpld/db/RAM2E.map.hdb and b/cpld/db/RAM2E.map.hdb differ
diff --git a/cpld/db/RAM2E.map.qmsg b/cpld/db/RAM2E.map.qmsg
index c333a7d..dce62f6 100755
--- a/cpld/db/RAM2E.map.qmsg
+++ b/cpld/db/RAM2E.map.qmsg
@@ -1,19 +1,19 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600301677825 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301677825 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:37 2020 " "Processing started: Wed Sep 16 20:14:37 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301677825 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600301677825 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600301677825 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600301678014 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(38) " "Verilog HDL warning at RAM2E.v(38): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1600301678049 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301678049 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600301678049 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600301678093 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600301678093 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_e4r " "Found entity 1: UFM_altufm_none_e4r" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301678093 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301678093 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600301678093 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1600301678114 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(100) " "Verilog HDL assignment warning at RAM2E.v(100): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301678114 "|RAM2E"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(103) " "Verilog HDL assignment warning at RAM2E.v(103): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301678124 "|RAM2E"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(544) " "Verilog HDL assignment warning at RAM2E.v(544): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 544 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301678124 "|RAM2E"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(561) " "Verilog HDL assignment warning at RAM2E.v(561): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 561 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301678124 "|RAM2E"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 79 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600301678124 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_e4r UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component " "Elaborating entity \"UFM_altufm_none_e4r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component\"" { } { { "UFM.v" "UFM_altufm_none_e4r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600301678124 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "268 " "Implemented 268 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1600301678637 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1600301678637 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1600301678637 ""} { "Info" "ICUT_CUT_TM_LCELLS" "198 " "Implemented 198 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1600301678637 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1600301678637 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1600301678637 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1600301678679 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4568 " "Peak virtual memory: 4568 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301678723 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:38 2020 " "Processing ended: Wed Sep 16 20:14:38 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301678723 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301678723 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301678723 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600301678723 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1611862633422 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1611862633423 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 28 14:37:13 2021 " "Processing started: Thu Jan 28 14:37:13 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1611862633423 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1611862633423 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1611862633423 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1611862633931 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(38) " "Verilog HDL warning at RAM2E.v(38): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1611862634000 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1611862634004 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1611862634004 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1611862634076 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1611862634076 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_a7r " "Found entity 1: UFM_altufm_none_a7r" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1611862634077 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1611862634077 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1611862634077 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1611862634123 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(100) " "Verilog HDL assignment warning at RAM2E.v(100): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862634126 "|RAM2E"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(103) " "Verilog HDL assignment warning at RAM2E.v(103): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862634127 "|RAM2E"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(544) " "Verilog HDL assignment warning at RAM2E.v(544): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 544 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862634127 "|RAM2E"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(561) " "Verilog HDL assignment warning at RAM2E.v(561): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 561 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862634127 "|RAM2E"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 79 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1611862634131 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_a7r UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component " "Elaborating entity \"UFM_altufm_none_a7r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component\"" { } { { "UFM.v" "UFM_altufm_none_a7r_component" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1611862634134 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "268 " "Implemented 268 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1611862635054 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1611862635054 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1611862635054 ""} { "Info" "ICUT_CUT_TM_LCELLS" "198 " "Implemented 198 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1611862635054 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1611862635054 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1611862635054 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1611862635130 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4566 " "Peak virtual memory: 4566 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862635220 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:37:15 2021 " "Processing ended: Thu Jan 28 14:37:15 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862635220 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862635220 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862635220 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1611862635220 ""}
diff --git a/cpld/db/RAM2E.map.rdb b/cpld/db/RAM2E.map.rdb
index f42c4f6..bec4068 100755
Binary files a/cpld/db/RAM2E.map.rdb and b/cpld/db/RAM2E.map.rdb differ
diff --git a/cpld/db/RAM2E.pre_map.hdb b/cpld/db/RAM2E.pre_map.hdb
index 52a496f..9c3988b 100755
Binary files a/cpld/db/RAM2E.pre_map.hdb and b/cpld/db/RAM2E.pre_map.hdb differ
diff --git a/cpld/db/RAM2E.routing.rdb b/cpld/db/RAM2E.routing.rdb
index b9f2234..0f5bd4b 100755
Binary files a/cpld/db/RAM2E.routing.rdb and b/cpld/db/RAM2E.routing.rdb differ
diff --git a/cpld/db/RAM2E.rtlv.hdb b/cpld/db/RAM2E.rtlv.hdb
index f1fc6e6..367bcad 100755
Binary files a/cpld/db/RAM2E.rtlv.hdb and b/cpld/db/RAM2E.rtlv.hdb differ
diff --git a/cpld/db/RAM2E.rtlv_sg.cdb b/cpld/db/RAM2E.rtlv_sg.cdb
index a0c5003..3327b71 100755
Binary files a/cpld/db/RAM2E.rtlv_sg.cdb and b/cpld/db/RAM2E.rtlv_sg.cdb differ
diff --git a/cpld/db/RAM2E.rtlv_sg_swap.cdb b/cpld/db/RAM2E.rtlv_sg_swap.cdb
index adf349d..916a528 100755
Binary files a/cpld/db/RAM2E.rtlv_sg_swap.cdb and b/cpld/db/RAM2E.rtlv_sg_swap.cdb differ
diff --git a/cpld/db/RAM2E.sgdiff.cdb b/cpld/db/RAM2E.sgdiff.cdb
index bbff58d..bad1e1d 100755
Binary files a/cpld/db/RAM2E.sgdiff.cdb and b/cpld/db/RAM2E.sgdiff.cdb differ
diff --git a/cpld/db/RAM2E.sgdiff.hdb b/cpld/db/RAM2E.sgdiff.hdb
index 8e99168..be59b92 100755
Binary files a/cpld/db/RAM2E.sgdiff.hdb and b/cpld/db/RAM2E.sgdiff.hdb differ
diff --git a/cpld/db/RAM2E.sta.qmsg b/cpld/db/RAM2E.sta.qmsg
index 4c7af12..4763629 100755
--- a/cpld/db/RAM2E.sta.qmsg
+++ b/cpld/db/RAM2E.sta.qmsg
@@ -1,22 +1,22 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600301682828 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301682828 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:42 2020 " "Processing started: Wed Sep 16 20:14:42 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301682828 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600301682828 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600301682828 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1600301682880 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600301682962 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600301682991 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600301682991 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1600301683013 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1600301683244 ""}
-{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1600301683302 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600301683312 "|RAM2E|DRCLK"}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600301683312 "|RAM2E|ARCLK"}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1600301683312 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 21.694 " "Worst-case setup slack is 21.694" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683332 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683332 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 21.694 0.000 C14M " " 21.694 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683332 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301683332 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 3.144 " "Worst-case hold slack is 3.144" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683342 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683342 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.144 0.000 C14M " " 3.144 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683342 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301683342 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600301683342 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600301683352 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.581 " "Worst-case minimum pulse width slack is 34.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683362 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.581 0.000 C14M " " 34.581 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301683362 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301683362 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1600301683402 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600301683432 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600301683432 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301683502 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:43 2020 " "Processing ended: Wed Sep 16 20:14:43 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301683502 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301683502 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301683502 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600301683502 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1611862641831 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1611862641832 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 28 14:37:21 2021 " "Processing started: Thu Jan 28 14:37:21 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1611862641832 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1611862641832 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1611862641833 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1611862641982 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1611862642218 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1611862642274 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1611862642274 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1611862642341 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1611862642656 ""}
+{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1611862642749 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1611862642762 "|RAM2E|DRCLK"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1611862642762 "|RAM2E|ARCLK"}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1611862642766 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 29.169 " "Worst-case setup slack is 29.169" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862642809 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862642809 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 29.169 0.000 C14M " " 29.169 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862642809 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1611862642809 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.646 " "Worst-case hold slack is 1.646" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862642820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862642820 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.646 0.000 C14M " " 1.646 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862642820 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1611862642820 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1611862642830 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1611862642841 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.654 " "Worst-case minimum pulse width slack is 34.654" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862642857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862642857 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.654 0.000 C14M " " 34.654 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862642857 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1611862642857 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1611862642938 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1611862642979 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1611862642979 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4513 " "Peak virtual memory: 4513 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862643119 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:37:23 2021 " "Processing ended: Thu Jan 28 14:37:23 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862643119 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862643119 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862643119 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1611862643119 ""}
diff --git a/cpld/db/RAM2E.sta.rdb b/cpld/db/RAM2E.sta.rdb
index 4760e3f..6e658f9 100755
Binary files a/cpld/db/RAM2E.sta.rdb and b/cpld/db/RAM2E.sta.rdb differ
diff --git a/cpld/db/RAM2E.sta_cmp.5_slow.tdb b/cpld/db/RAM2E.sta_cmp.5_slow.tdb
index b772eb6..954685a 100755
Binary files a/cpld/db/RAM2E.sta_cmp.5_slow.tdb and b/cpld/db/RAM2E.sta_cmp.5_slow.tdb differ
diff --git a/cpld/db/RAM2E.tmw_info b/cpld/db/RAM2E.tmw_info
index 590dceb..e404785 100644
--- a/cpld/db/RAM2E.tmw_info
+++ b/cpld/db/RAM2E.tmw_info
@@ -1,6 +1,6 @@
-start_full_compilation:s:00:00:07
-start_analysis_synthesis:s:00:00:02-start_full_compilation
+start_full_compilation:s:00:00:11
+start_analysis_synthesis:s:00:00:03-start_full_compilation
start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:00:02-start_full_compilation
-start_assembler:s:00:00:01-start_full_compilation
+start_fitter:s:00:00:04-start_full_compilation
+start_assembler:s:00:00:02-start_full_compilation
start_timing_analyzer:s:00:00:02-start_full_compilation
diff --git a/cpld/db/RAM2E.vpr.ammdb b/cpld/db/RAM2E.vpr.ammdb
index 20ebc98..148b61d 100755
Binary files a/cpld/db/RAM2E.vpr.ammdb and b/cpld/db/RAM2E.vpr.ammdb differ
diff --git a/cpld/db/logic_util_heursitic.dat b/cpld/db/logic_util_heursitic.dat
index 67c7583..469ee44 100755
Binary files a/cpld/db/logic_util_heursitic.dat and b/cpld/db/logic_util_heursitic.dat differ
diff --git a/cpld/db/prev_cmp_RAM2E.qmsg b/cpld/db/prev_cmp_RAM2E.qmsg
index a0de8fa..4f424cb 100755
--- a/cpld/db/prev_cmp_RAM2E.qmsg
+++ b/cpld/db/prev_cmp_RAM2E.qmsg
@@ -1,93 +1,94 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600301660928 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301660928 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:20 2020 " "Processing started: Wed Sep 16 20:14:20 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301660928 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600301660928 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600301660928 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600301661124 ""}
-{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(38) " "Verilog HDL warning at RAM2E.v(38): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1600301661165 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301661165 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600301661165 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600301661209 ""}
-{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1600301661209 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_e4r " "Found entity 1: UFM_altufm_none_e4r" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301661209 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1600301661209 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1600301661209 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1600301661237 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(100) " "Verilog HDL assignment warning at RAM2E.v(100): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301661239 "|RAM2E"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(103) " "Verilog HDL assignment warning at RAM2E.v(103): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301661239 "|RAM2E"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(544) " "Verilog HDL assignment warning at RAM2E.v(544): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 544 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301661239 "|RAM2E"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(561) " "Verilog HDL assignment warning at RAM2E.v(561): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 561 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1600301661239 "|RAM2E"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 79 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600301661280 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_e4r UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component " "Elaborating entity \"UFM_altufm_none_e4r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component\"" { } { { "UFM.v" "UFM_altufm_none_e4r_component" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1600301661280 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "268 " "Implemented 268 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1600301661771 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1600301661771 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1600301661771 ""} { "Info" "ICUT_CUT_TM_LCELLS" "198 " "Implemented 198 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1600301661771 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1600301661771 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1600301661771 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1600301661801 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4568 " "Peak virtual memory: 4568 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301661851 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:21 2020 " "Processing ended: Wed Sep 16 20:14:21 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301661851 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301661851 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301661851 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600301661851 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1600301662763 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301662763 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:22 2020 " "Processing started: Wed Sep 16 20:14:22 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301662763 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1600301662763 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1600301662773 ""}
-{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1600301662812 ""}
-{ "Info" "0" "" "Project = RAM2E" { } { } 0 0 "Project = RAM2E" 0 0 "Fitter" 0 0 1600301662822 ""}
-{ "Info" "0" "" "Revision = RAM2E" { } { } 0 0 "Revision = RAM2E" 0 0 "Fitter" 0 0 1600301662822 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1600301662852 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E 5M240ZT100C5 " "Selected device 5M240ZT100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1600301662862 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600301662882 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600301662882 ""}
-{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1600301662912 ""}
-{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1600301662922 ""}
-{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100C5 " "Device 5M80ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M80ZT100I5 " "Device 5M80ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100C5 " "Device 5M160ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M160ZT100I5 " "Device 5M160ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M240ZT100I5 " "Device 5M240ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100C5 " "Device 5M570ZT100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "5M570ZT100I5 " "Device 5M570ZT100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1600301662982 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1600301662982 ""}
-{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1600301663042 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600301663042 "|RAM2E|DRCLK"}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1600301663042 "|RAM2E|ARCLK"}
-{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1600301663042 ""}
-{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301663042 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301663042 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1600301663042 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1600301663042 ""}
-{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600301663052 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1600301663052 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600301663052 ""}
-{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1600301663052 ""}
-{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1600301663052 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1600301663052 ""}
-{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1600301663072 ""}
-{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1600301663072 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1600301663082 ""}
-{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1600301663090 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1600301663090 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1600301663090 ""}
-{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301663110 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1600301663178 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301663309 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1600301663319 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1600301663521 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301663521 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1600301663541 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "19 " "Router estimated average interconnect usage is 19% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1600301663683 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1600301663683 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301663792 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.14 " "Total time spent on timing analysis during the Fitter is 0.14 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1600301663802 ""}
-{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600301663802 ""}
-{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1600301663822 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1600301663871 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4767 " "Peak virtual memory: 4767 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301663952 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:23 2020 " "Processing ended: Wed Sep 16 20:14:23 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301663952 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301663952 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301663952 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1600301663952 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1600301664792 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301664792 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:24 2020 " "Processing started: Wed Sep 16 20:14:24 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301664792 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1600301664792 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1600301664792 ""}
-{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1600301664952 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1600301664952 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4524 " "Peak virtual memory: 4524 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301665092 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:25 2020 " "Processing ended: Wed Sep 16 20:14:25 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301665092 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301665092 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:00 " "Total CPU time (on all processors): 00:00:00" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301665092 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1600301665092 ""}
-{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1600301665682 ""}
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1600301665982 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1600301665982 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 16 20:14:25 2020 " "Processing started: Wed Sep 16 20:14:25 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1600301665982 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1600301665982 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1600301665982 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1600301666032 ""}
-{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1600301666122 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600301666152 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1600301666152 ""}
-{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1600301666172 ""}
-{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1600301666410 ""}
-{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1600301666462 ""}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600301666470 "|RAM2E|DRCLK"}
-{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1600301666470 "|RAM2E|ARCLK"}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1600301666470 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup 21.694 " "Worst-case setup slack is 21.694" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 21.694 0.000 C14M " " 21.694 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 3.144 " "Worst-case hold slack is 3.144" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 3.144 0.000 C14M " " 3.144 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301666500 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600301666510 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1600301666520 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.581 " "Worst-case minimum pulse width slack is 34.581" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666530 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666530 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.581 0.000 C14M " " 34.581 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1600301666530 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1600301666530 ""}
-{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1600301666570 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600301666590 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1600301666590 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4522 " "Peak virtual memory: 4522 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1600301666660 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 16 20:14:26 2020 " "Processing ended: Wed Sep 16 20:14:26 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1600301666660 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1600301666660 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1600301666660 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600301666660 ""}
-{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 13 s " "Quartus II Full Compilation was successful. 0 errors, 13 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1600301667280 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1611862593702 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1611862593703 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 28 14:36:33 2021 " "Processing started: Thu Jan 28 14:36:33 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1611862593703 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1611862593703 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1611862593703 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1611862594200 ""}
+{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "RAM2E.v(38) " "Verilog HDL warning at RAM2E.v(38): extended using \"x\" or \"z\"" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 38 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1611862594267 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ram2e.v 1 1 " "Found 1 design units, including 1 entities, in source file ram2e.v" { { "Info" "ISGN_ENTITY_NAME" "1 RAM2E " "Found entity 1: RAM2E" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1611862594271 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1611862594271 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(72) " "Verilog HDL Declaration warning at UFM.v(72): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 72 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1611862594340 ""}
+{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "program UFM.v(188) " "Verilog HDL Declaration warning at UFM.v(188): \"program\" is SystemVerilog-2005 keyword" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 188 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 1 0 "Quartus II" 0 -1 1611862594340 ""}
+{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ufm.v 2 2 " "Found 2 design units, including 2 entities, in source file ufm.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_none_a7r " "Found entity 1: UFM_altufm_none_a7r" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 46 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1611862594341 ""} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Found entity 2: UFM" { } { { "UFM.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 165 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1611862594341 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1611862594341 ""}
+{ "Info" "ISGN_START_ELABORATION_TOP" "RAM2E " "Elaborating entity \"RAM2E\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1611862594391 ""}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 RAM2E.v(100) " "Verilog HDL assignment warning at RAM2E.v(100): truncated value with size 32 to match size of target (16)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 100 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862594395 "|RAM2E"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 RAM2E.v(103) " "Verilog HDL assignment warning at RAM2E.v(103): truncated value with size 32 to match size of target (4)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 103 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862594395 "|RAM2E"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(544) " "Verilog HDL assignment warning at RAM2E.v(544): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 544 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862594395 "|RAM2E"}
+{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 RAM2E.v(561) " "Verilog HDL assignment warning at RAM2E.v(561): truncated value with size 32 to match size of target (3)" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 561 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1611862594395 "|RAM2E"}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:UFM_inst " "Elaborating entity \"UFM\" for hierarchy \"UFM:UFM_inst\"" { } { { "RAM2E.v" "UFM_inst" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 79 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1611862594399 ""}
+{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_none_a7r UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component " "Elaborating entity \"UFM_altufm_none_a7r\" for hierarchy \"UFM:UFM_inst\|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component\"" { } { { "UFM.v" "UFM_altufm_none_a7r_component" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v" 216 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1611862594425 ""}
+{ "Info" "ICUT_CUT_TM_SUMMARY" "268 " "Implemented 268 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "22 " "Implemented 22 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1611862595360 ""} { "Info" "ICUT_CUT_TM_OPINS" "39 " "Implemented 39 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1611862595360 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" { } { } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1611862595360 ""} { "Info" "ICUT_CUT_TM_LCELLS" "198 " "Implemented 198 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1611862595360 ""} { "Info" "ICUT_CUT_TM_UFMS" "1 " "Implemented 1 User Flash Memory blocks" { } { } 0 21070 "Implemented %1!d! User Flash Memory blocks" 0 0 "Quartus II" 0 -1 1611862595360 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1611862595360 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg " "Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1611862595434 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4566 " "Peak virtual memory: 4566 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862595516 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:36:35 2021 " "Processing ended: Thu Jan 28 14:36:35 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862595516 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862595516 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862595516 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1611862595516 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1611862596827 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1611862596828 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 28 14:36:36 2021 " "Processing started: Thu Jan 28 14:36:36 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1611862596828 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1611862596828 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_fit --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1611862596829 ""}
+{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1611862596970 ""}
+{ "Info" "0" "" "Project = RAM2E" { } { } 0 0 "Project = RAM2E" 0 0 "Fitter" 0 0 1611862596971 ""}
+{ "Info" "0" "" "Revision = RAM2E" { } { } 0 0 "Revision = RAM2E" 0 0 "Fitter" 0 0 1611862596971 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1611862597039 ""}
+{ "Info" "IMPP_MPP_USER_DEVICE" "RAM2E EPM240T100C5 " "Selected device EPM240T100C5 for design \"RAM2E\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1611862597043 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611862597090 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1611862597090 ""}
+{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" { } { } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1611862597149 ""}
+{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1611862597162 ""}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Device EPM240T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862597357 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100A5 " "Device EPM240T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862597357 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Device EPM570T100C5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862597357 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Device EPM570T100I5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862597357 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100A5 " "Device EPM570T100A5 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1611862597357 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1611862597357 ""}
+{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1611862597463 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1611862597467 "|RAM2E|DRCLK"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1611862597467 "|RAM2E|ARCLK"}
+{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1611862597470 ""}
+{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1611862597470 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1611862597470 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 69.841 C14M " " 69.841 C14M" { } { } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1611862597470 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1611862597470 ""}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611862597474 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1611862597474 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Completed User Assigned Global Signals Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1611862597479 ""}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "C14M Global clock in PIN 12 " "Automatically promoted signal \"C14M\" to use Global clock in PIN 12" { } { { "RAM2E.v" "" { Text "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v" 8 -1 0 } } } 0 186215 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0 "Fitter" 0 -1 1611862597487 ""}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Completed Auto Global Promotion Operation" { } { } 0 186079 "Completed %1!s!" 0 0 "Fitter" 0 -1 1611862597488 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176234 "Starting register packing" 0 0 "Fitter" 0 -1 1611862597490 ""}
+{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 186391 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "Fitter" 0 -1 1611862597511 ""}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Moving registers into LUTs to improve timing and density" { } { } 1 176244 "Moving registers into LUTs to improve timing and density" 1 0 "Fitter" 0 -1 1611862597511 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Started processing fast register assignments" { } { } 0 186468 "Started processing fast register assignments" 0 0 "Fitter" 0 -1 1611862597552 ""}
+{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Finished processing fast register assignments" { } { } 0 186469 "Finished processing fast register assignments" 0 0 "Fitter" 0 -1 1611862597554 ""}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Finished moving registers into LUTs: elapsed time is 00:00:00" { } { } 1 176245 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "Fitter" 0 -1 1611862597555 ""}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1611862597555 ""}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862597600 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1611862597720 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862597937 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1611862597949 ""}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1611862598355 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862598355 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1611862598402 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_STATUS_DELAY_ADDED_FOR_HOLD" "4e+01 ns 2.6% " "4e+01 ns of routing delay (approximately 2.6% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." { } { } 0 170089 "%1!s! of routing delay (approximately %2!s! of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report." 0 0 "Fitter" 0 -1 1611862598625 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "18 " "Router estimated average interconnect usage is 18% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "18 X0_Y0 X8_Y5 " "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" { } { { "loc" "" { Generic "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/" { { 1 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} { { 11 { 0 "Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5"} 0 0 9 6 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1611862598662 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1611862598662 ""}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862598820 ""}
+{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.27 " "Total time spent on timing analysis during the Fitter is 0.27 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1611862598830 ""}
+{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1611862598835 ""}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1611862598876 ""}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg " "Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1611862598978 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4758 " "Peak virtual memory: 4758 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862599258 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:36:39 2021 " "Processing ended: Thu Jan 28 14:36:39 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862599258 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862599258 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862599258 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1611862599258 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1611862600288 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1611862600289 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 28 14:36:40 2021 " "Processing started: Thu Jan 28 14:36:40 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1611862600289 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1611862600289 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E " "Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1611862600289 ""}
+{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1611862600645 ""}
+{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1611862600652 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4515 " "Peak virtual memory: 4515 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862600967 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:36:40 2021 " "Processing ended: Thu Jan 28 14:36:40 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862600967 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862600967 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862600967 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1611862600967 ""}
+{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1611862601573 ""}
+{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1611862602252 ""}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition " "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1611862602253 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 28 14:36:41 2021 " "Processing started: Thu Jan 28 14:36:41 2021" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1611862602253 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1611862602253 ""}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta RAM2E -c RAM2E " "Command: quartus_sta RAM2E -c RAM2E" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1611862602254 ""}
+{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1611862602417 ""}
+{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" { } { } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Quartus II" 0 -1 1611862602652 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1611862602701 ""}
+{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1611862602701 ""}
+{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1611862602760 ""}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1611862603084 ""}
+{ "Info" "ISTA_SDC_FOUND" "constraints.sdc " "Reading SDC File: 'constraints.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1611862603191 ""}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "DRCLK " "Node: DRCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1611862603205 "|RAM2E|DRCLK"}
+{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "ARCLK " "Node: ARCLK was determined to be a clock but was found without an associated clock assignment." { } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Quartus II" 0 -1 1611862603205 "|RAM2E|ARCLK"}
+{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1611862603208 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "setup 29.169 " "Worst-case setup slack is 29.169" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603267 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 29.169 0.000 C14M " " 29.169 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603267 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1611862603267 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "hold 1.646 " "Worst-case hold slack is 1.646" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603277 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603277 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.646 0.000 C14M " " 1.646 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603277 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1611862603277 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1611862603289 ""}
+{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1611862603298 ""}
+{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 34.654 " "Worst-case minimum pulse width slack is 34.654" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603307 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 34.654 0.000 C14M " " 34.654 0.000 C14M " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1611862603307 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1611862603307 ""}
+{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1611862603380 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1611862603420 ""}
+{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1611862603420 ""}
+{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4513 " "Peak virtual memory: 4513 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1611862603567 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 28 14:36:43 2021 " "Processing ended: Thu Jan 28 14:36:43 2021" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1611862603567 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1611862603567 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1611862603567 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1611862603567 ""}
+{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 13 s " "Quartus II Full Compilation was successful. 0 errors, 13 warnings" { } { } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1611862604230 ""}
diff --git a/cpld/greybox_tmp/cbx_args.txt b/cpld/greybox_tmp/cbx_args.txt
index c8d6a96..51d7b3e 100644
--- a/cpld/greybox_tmp/cbx_args.txt
+++ b/cpld/greybox_tmp/cbx_args.txt
@@ -1,5 +1,5 @@
ERASE_TIME=500000000
-INTENDED_DEVICE_FAMILY="MAX V"
+INTENDED_DEVICE_FAMILY="MAX II"
LPM_FILE=RAM2E.mif
LPM_HINT=UNUSED
LPM_TYPE=altufm_none
@@ -8,7 +8,7 @@ PORT_ARCLKENA=PORT_UNUSED
PORT_DRCLKENA=PORT_UNUSED
PROGRAM_TIME=1600000
WIDTH_UFM_ADDRESS=9
-DEVICE_FAMILY="MAX V"
+DEVICE_FAMILY="MAX II"
CBX_AUTO_BLACKBOX=ALL
arclk
ardin
diff --git a/cpld/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt b/cpld/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt
index 674b4f3..fb0c74c 100755
Binary files a/cpld/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt and b/cpld/incremental_db/compiled_partitions/RAM2E.root_partition.map.kpt differ
diff --git a/cpld/output_files/RAM2E.asm.rpt b/cpld/output_files/RAM2E.asm.rpt
index f002d49..7e89669 100755
--- a/cpld/output_files/RAM2E.asm.rpt
+++ b/cpld/output_files/RAM2E.asm.rpt
@@ -1,5 +1,5 @@
Assembler report for RAM2E
-Wed Sep 16 20:14:41 2020
+Thu Jan 28 14:37:20 2021
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@@ -10,7 +10,7 @@ Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edit
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
- 5. Assembler Device Options: C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pof
+ 5. Assembler Device Options: C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pof
6. Assembler Messages
@@ -37,11 +37,11 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Wed Sep 16 20:14:41 2020 ;
+; Assembler Status ; Successful - Thu Jan 28 14:37:20 2021 ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
-; Family ; MAX V ;
-; Device ; 5M240ZT100C5 ;
+; Family ; MAX II ;
+; Device ; EPM240T100C5 ;
+-----------------------+---------------------------------------+
@@ -75,24 +75,24 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+-----------+---------------+
-+------------------------------------------------------------------+
-; Assembler Generated Files ;
-+------------------------------------------------------------------+
-; File Name ;
-+------------------------------------------------------------------+
-; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pof ;
-+------------------------------------------------------------------+
++------------------------------------------------------------------------------------+
+; Assembler Generated Files ;
++------------------------------------------------------------------------------------+
+; File Name ;
++------------------------------------------------------------------------------------+
+; C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pof ;
++------------------------------------------------------------------------------------+
-+--------------------------------------------------------------------------------------------+
-; Assembler Device Options: C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pof ;
-+----------------+---------------------------------------------------------------------------+
-; Option ; Setting ;
-+----------------+---------------------------------------------------------------------------+
-; Device ; 5M240ZT100C5 ;
-; JTAG usercode ; 0x0016ED59 ;
-; Checksum ; 0x0016F0C1 ;
-+----------------+---------------------------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------+
+; Assembler Device Options: C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pof ;
++----------------+---------------------------------------------------------------------------------------------+
+; Option ; Setting ;
++----------------+---------------------------------------------------------------------------------------------+
+; Device ; EPM240T100C5 ;
+; JTAG usercode ; 0x00170076 ;
+; Checksum ; 0x001703FE ;
++----------------+---------------------------------------------------------------------------------------------+
+--------------------+
@@ -101,14 +101,14 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 64-Bit Assembler
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
- Info: Processing started: Wed Sep 16 20:14:41 2020
+ Info: Processing started: Thu Jan 28 14:37:19 2021
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off RAM2E -c RAM2E
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 4524 megabytes
- Info: Processing ended: Wed Sep 16 20:14:41 2020
- Info: Elapsed time: 00:00:00
- Info: Total CPU time (on all processors): 00:00:00
+ Info: Peak virtual memory: 4515 megabytes
+ Info: Processing ended: Thu Jan 28 14:37:20 2021
+ Info: Elapsed time: 00:00:01
+ Info: Total CPU time (on all processors): 00:00:01
diff --git a/cpld/output_files/RAM2E.cdf b/cpld/output_files/RAM2E.cdf
deleted file mode 100644
index e80b434..0000000
--- a/cpld/output_files/RAM2E.cdf
+++ /dev/null
@@ -1,13 +0,0 @@
-/* Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition */
-JedecChain;
- FileRevision(JESD32A);
- DefaultMfr(6E);
-
- P ActionCode(Cfg)
- Device PartName(5M240ZT100) Path("C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/") File("RAM2E.pof") MfrSpec(OpMask(3) SEC_Device(5M240ZT100) Child_OpMask(2 3 3));
-
-ChainEnd;
-
-AlteraBegin;
- ChainType(JTAG);
-AlteraEnd;
diff --git a/cpld/output_files/RAM2E.done b/cpld/output_files/RAM2E.done
index 39c72ed..61f7143 100755
--- a/cpld/output_files/RAM2E.done
+++ b/cpld/output_files/RAM2E.done
@@ -1 +1 @@
-Wed Sep 16 20:14:44 2020
+Thu Jan 28 14:37:23 2021
diff --git a/cpld/output_files/RAM2E.fit.rpt b/cpld/output_files/RAM2E.fit.rpt
index a748e8c..5a3b0c7 100755
--- a/cpld/output_files/RAM2E.fit.rpt
+++ b/cpld/output_files/RAM2E.fit.rpt
@@ -1,5 +1,5 @@
Fitter report for RAM2E
-Wed Sep 16 20:14:40 2020
+Thu Jan 28 14:37:18 2021
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@@ -57,15 +57,15 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Fitter Summary ;
+---------------------------+-------------------------------------------------+
-; Fitter Status ; Successful - Wed Sep 16 20:14:40 2020 ;
+; Fitter Status ; Successful - Thu Jan 28 14:37:18 2021 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
-; Family ; MAX V ;
-; Device ; 5M240ZT100C5 ;
+; Family ; MAX II ;
+; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 189 / 240 ( 79 % ) ;
-; Total pins ; 69 / 79 ( 87 % ) ;
+; Total pins ; 69 / 80 ( 86 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+---------------------------+-------------------------------------------------+
@@ -76,7 +76,7 @@ applicable agreement for further details.
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------------------+--------------------------------+
-; Device ; 5M240ZT100C5 ; ;
+; Device ; EPM240T100C5 ; ;
; Minimum Core Junction Temperature ; 0 ; ;
; Maximum Core Junction Temperature ; 85 ; ;
; Fit Attempts to Skip ; 0 ; 0.0 ;
@@ -134,7 +134,7 @@ Parallel compilation was disabled, but you have multiple processors available. E
+--------------+
; Pin-Out File ;
+--------------+
-The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pin.
+The pin-out file can be found in C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.pin.
+------------------------------------------------------------------+
@@ -149,8 +149,8 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 90 ;
-; -- 3 input functions ; 42 ;
-; -- 2 input functions ; 36 ;
+; -- 3 input functions ; 43 ;
+; -- 2 input functions ; 35 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
@@ -159,25 +159,25 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; -- arithmetic mode ; 14 ;
; -- qfbk mode ; 9 ;
; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 14 ;
+; -- synchronous clear/load mode ; 10 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 107 / 240 ( 45 % ) ;
; Total LABs ; 22 / 24 ( 92 % ) ;
; Logic elements in carry chains ; 15 ;
; Virtual pins ; 0 ;
-; I/O pins ; 69 / 79 ( 87 % ) ;
+; I/O pins ; 69 / 80 ( 86 % ) ;
; -- Clock pins ; 3 / 4 ( 75 % ) ;
; ; ;
; Global signals ; 1 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
; Global clocks ; 1 / 4 ( 25 % ) ;
; JTAGs ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 24% / 26% / 22% ;
-; Peak interconnect usage (total/H/V) ; 24% / 26% / 22% ;
+; Average interconnect usage (total/H/V) ; 20% / 20% / 20% ;
+; Peak interconnect usage (total/H/V) ; 20% / 20% / 20% ;
; Maximum fan-out ; 107 ;
-; Highest non-global fan-out ; 34 ;
-; Total fan-out ; 810 ;
+; Highest non-global fan-out ; 35 ;
+; Total fan-out ; 811 ;
; Average fan-out ; 3.13 ;
+---------------------------------------------+--------------------+
@@ -221,7 +221,7 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; BA[1] ; 14 ; 1 ; 1 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; CKE ; 4 ; 1 ; 1 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; DQMH ; 100 ; 2 ; 2 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
-; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+; DQML ; 98 ; 2 ; 2 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[0] ; 77 ; 2 ; 7 ; 5 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[1] ; 76 ; 2 ; 7 ; 5 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[2] ; 74 ; 2 ; 8 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
@@ -230,7 +230,7 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; Dout[5] ; 72 ; 2 ; 8 ; 4 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[6] ; 84 ; 2 ; 6 ; 5 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Dout[7] ; 85 ; 2 ; 5 ; 5 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
-; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+; RA[0] ; 18 ; 1 ; 1 ; 1 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[10] ; 16 ; 1 ; 1 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[11] ; 7 ; 1 ; 1 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[1] ; 20 ; 1 ; 1 ; 1 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
@@ -243,18 +243,18 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; RA[8] ; 17 ; 1 ; 1 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; RA[9] ; 15 ; 1 ; 1 ; 2 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; Vout[0] ; 70 ; 2 ; 8 ; 4 ; 4 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
-; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
-; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+; Vout[1] ; 67 ; 2 ; 8 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
+; Vout[2] ; 69 ; 2 ; 8 ; 3 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[3] ; 62 ; 2 ; 8 ; 2 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[4] ; 71 ; 2 ; 8 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
-; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+; Vout[5] ; 68 ; 2 ; 8 ; 3 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[6] ; 58 ; 2 ; 8 ; 2 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; Vout[7] ; 57 ; 2 ; 8 ; 2 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
-; nCAS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
+; nCAS ; 3 ; 1 ; 1 ; 4 ; 1 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nCS ; 8 ; 1 ; 1 ; 3 ; 2 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nDOE ; 55 ; 2 ; 8 ; 1 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
; nRAS ; 5 ; 1 ; 1 ; 4 ; 3 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
-; nRWE ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+; nRWE ; 2 ; 1 ; 1 ; 4 ; 0 ; no ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 4mA ; yes ; User ; 10 pF ; - ; - ;
; nVOE ; 50 ; 1 ; 7 ; 0 ; 1 ; no ; yes ; no ; no ; no ; no ; On ; 3.3-V LVCMOS ; 4mA ; no ; User ; 10 pF ; - ; - ;
+---------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+----------------------+---------------------+
@@ -281,116 +281,116 @@ The pin-out file can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/outpu
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+-------------------+---------------+--------------+
; 1 ; 38 / 38 ( 100 % ) ; 3.3V ; -- ;
-; 2 ; 31 / 41 ( 76 % ) ; 3.3V ; -- ;
+; 2 ; 31 / 42 ( 74 % ) ; 3.3V ; -- ;
+----------+-------------------+---------------+--------------+
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
-; 1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 2 ; 0 ; 1 ; nRWE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 3 ; 1 ; 1 ; nCAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 4 ; 2 ; 1 ; CKE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 5 ; 3 ; 1 ; nRAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 6 ; 4 ; 1 ; BA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 7 ; 5 ; 1 ; RA[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 8 ; 6 ; 1 ; nCS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 12 ; 7 ; 1 ; C14M ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 13 ; ; ; VCCINT ; power ; ; 1.8V ; -- ; ; -- ; -- ;
-; 14 ; 8 ; 1 ; BA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 15 ; 9 ; 1 ; RA[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 16 ; 10 ; 1 ; RA[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 17 ; 11 ; 1 ; RA[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 18 ; 12 ; 1 ; RA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 19 ; 13 ; 1 ; RA[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 20 ; 14 ; 1 ; RA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 21 ; 15 ; 1 ; RA[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; 26 ; 20 ; 1 ; RA[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 27 ; 21 ; 1 ; RA[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 28 ; 22 ; 1 ; nEN80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 29 ; 23 ; 1 ; RA[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 30 ; 24 ; 1 ; RA[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 32 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 33 ; 25 ; 1 ; nWE80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 34 ; 26 ; 1 ; Ain[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 35 ; 27 ; 1 ; Din[7] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 36 ; 28 ; 1 ; Din[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 37 ; 29 ; 1 ; PHI1 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 38 ; 30 ; 1 ; Din[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 39 ; 31 ; 1 ; Ain[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 40 ; 32 ; 1 ; Din[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 41 ; 33 ; 1 ; Din[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 42 ; 34 ; 1 ; Din[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 43 ; 35 ; 1 ; Ain[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 44 ; 36 ; 1 ; Ain[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 46 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; On ;
-; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; On ;
-; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 60 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 62 ; 50 ; 2 ; Vout[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 63 ; ; ; VCCINT ; power ; ; 1.8V ; -- ; ; -- ; -- ;
-; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 65 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
-; 67 ; 53 ; 2 ; Vout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 68 ; 54 ; 2 ; Vout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 69 ; 55 ; 2 ; Vout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 70 ; 56 ; 2 ; Vout[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 71 ; 57 ; 2 ; Vout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 72 ; 58 ; 2 ; Dout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 73 ; 59 ; 2 ; Dout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 74 ; 60 ; 2 ; Dout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
-; 75 ; 61 ; 2 ; Dout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 76 ; 62 ; 2 ; Dout[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 77 ; 63 ; 2 ; Dout[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 79 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 84 ; 68 ; 2 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 85 ; 69 ; 2 ; Dout[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
-; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
-; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
-; 91 ; 75 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
-; 92 ; 76 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
-; 93 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
-; 96 ; 78 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
-; 97 ; 79 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
-; 98 ; 80 ; 2 ; DQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-; 99 ; 81 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
-; 100 ; 82 ; 2 ; DQMH ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
-+----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+
++------------------------------------------------------------------------------------------------------------------------------------------------+
+; All Package Pins ;
++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
+; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
+; 1 ; 83 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 2 ; 0 ; 1 ; nRWE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 3 ; 1 ; 1 ; nCAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 4 ; 2 ; 1 ; CKE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 5 ; 3 ; 1 ; nRAS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 6 ; 4 ; 1 ; BA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 7 ; 5 ; 1 ; RA[11] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 8 ; 6 ; 1 ; nCS ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 9 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
+; 11 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
+; 12 ; 7 ; 1 ; C14M ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 13 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
+; 14 ; 8 ; 1 ; BA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 15 ; 9 ; 1 ; RA[9] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 16 ; 10 ; 1 ; RA[10] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 17 ; 11 ; 1 ; RA[8] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 18 ; 12 ; 1 ; RA[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 19 ; 13 ; 1 ; RA[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 20 ; 14 ; 1 ; RA[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 21 ; 15 ; 1 ; RA[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 22 ; 16 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
+; 23 ; 17 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
+; 24 ; 18 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
+; 25 ; 19 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
+; 26 ; 20 ; 1 ; RA[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 27 ; 21 ; 1 ; RA[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 28 ; 22 ; 1 ; nEN80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 29 ; 23 ; 1 ; RA[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 30 ; 24 ; 1 ; RA[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 31 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 32 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
+; 33 ; 25 ; 1 ; nWE80 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 34 ; 26 ; 1 ; Ain[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 35 ; 27 ; 1 ; Din[7] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 36 ; 28 ; 1 ; Din[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 37 ; 29 ; 1 ; PHI1 ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 38 ; 30 ; 1 ; Din[0] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 39 ; 31 ; 1 ; Ain[6] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 40 ; 32 ; 1 ; Din[1] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 41 ; 33 ; 1 ; Din[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 42 ; 34 ; 1 ; Din[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 43 ; 35 ; 1 ; Ain[2] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 44 ; 36 ; 1 ; Ain[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 45 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 46 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
+; 47 ; 37 ; 1 ; Ain[3] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 48 ; 38 ; 1 ; Din[4] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 49 ; 39 ; 1 ; Din[5] ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 50 ; 40 ; 1 ; nVOE ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; On ;
+; 51 ; 41 ; 1 ; nWE ; input ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 52 ; 42 ; 2 ; nC07X ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 53 ; 43 ; 2 ; Ain[7] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 54 ; 44 ; 2 ; Ain[1] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 55 ; 45 ; 2 ; nDOE ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; On ;
+; 56 ; 46 ; 2 ; Ain[0] ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 57 ; 47 ; 2 ; Vout[7] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 58 ; 48 ; 2 ; Vout[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 59 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 60 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
+; 61 ; 49 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 62 ; 50 ; 2 ; Vout[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 63 ; ; ; VCCINT ; power ; ; 2.5V/3.3V ; -- ; ; -- ; -- ;
+; 64 ; 51 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 65 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ;
+; 66 ; 52 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ;
+; 67 ; 53 ; 2 ; Vout[1] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 68 ; 54 ; 2 ; Vout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 69 ; 55 ; 2 ; Vout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 70 ; 56 ; 2 ; Vout[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 71 ; 57 ; 2 ; Vout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 72 ; 58 ; 2 ; Dout[5] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 73 ; 59 ; 2 ; Dout[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 74 ; 60 ; 2 ; Dout[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
+; 75 ; 61 ; 2 ; Dout[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 76 ; 62 ; 2 ; Dout[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 77 ; 63 ; 2 ; Dout[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 78 ; 64 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 79 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
+; 80 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 81 ; 65 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 82 ; 66 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 83 ; 67 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 84 ; 68 ; 2 ; Dout[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 85 ; 69 ; 2 ; Dout[7] ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 86 ; 70 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 87 ; 71 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 88 ; 72 ; 2 ; GND* ; ; ; ; Column I/O ; ; no ; Off ;
+; 89 ; 73 ; 2 ; RD[3] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
+; 90 ; 74 ; 2 ; RD[1] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
+; 91 ; 75 ; 2 ; RD[4] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
+; 92 ; 76 ; 2 ; RD[5] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
+; 93 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ;
+; 94 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
+; 95 ; 77 ; 2 ; RD[6] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
+; 96 ; 78 ; 2 ; RD[7] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
+; 97 ; 79 ; 2 ; RD[0] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
+; 98 ; 80 ; 2 ; DQML ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
+; 99 ; 81 ; 2 ; RD[2] ; bidir ; 3.3-V LVCMOS ; ; Column I/O ; Y ; yes ; Off ;
+; 100 ; 82 ; 2 ; DQMH ; output ; 3.3-V LVCMOS ; ; Column I/O ; Y ; no ; Off ;
++----------+------------+----------+----------------+--------+--------------+-----------+------------+-----------------+----------+--------------+
Note: Pin directions (input, output or bidir) are based on device operating in user mode.
@@ -406,9 +406,6 @@ Note: Pin directions (input, output or bidir) are based on device operating in u
; 1.5 V ; 10 pF ; Not Available ;
; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ;
; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ;
-; 1.2 V ; 10 pF ; Not Available ;
-; LVDS_E_3R ; 10 pF ; Not Available ;
-; RSDS_E_3R ; 10 pF ; Not Available ;
+----------------------------+-------+------------------------+
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
@@ -420,7 +417,7 @@ Note: User assignments will override these defaults. The user specified values a
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+
; |RAM2E ; 189 (189) ; 107 ; 1 ; 69 ; 0 ; 82 (82) ; 17 (17) ; 90 (90) ; 15 (15) ; 9 (9) ; |RAM2E ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; work ;
-; |UFM_altufm_none_e4r:UFM_altufm_none_e4r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component ; work ;
+; |UFM_altufm_none_a7r:UFM_altufm_none_a7r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
@@ -508,15 +505,15 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
+-------------+-------------+---------+---------------+--------+----------------------+------------------+
; C14M ; PIN_12 ; 107 ; Clock ; yes ; Global Clock ; GCLK0 ;
-; CS[0]~2 ; LC_X4_Y3_N1 ; 3 ; Clock enable ; no ; -- ; -- ;
-; Equal9~0 ; LC_X6_Y4_N8 ; 14 ; Clock enable ; no ; -- ; -- ;
-; Equal9~1 ; LC_X7_Y3_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
-; RA[4]~1 ; LC_X2_Y2_N1 ; 8 ; Clock enable ; no ; -- ; -- ;
-; RDOE ; LC_X3_Y4_N7 ; 8 ; Output enable ; no ; -- ; -- ;
-; RWBank[4]~1 ; LC_X5_Y3_N2 ; 13 ; Clock enable ; no ; -- ; -- ;
-; RWMask[4]~2 ; LC_X4_Y2_N8 ; 8 ; Clock enable ; no ; -- ; -- ;
-; S[2] ; LC_X7_Y3_N4 ; 20 ; Sync. clear ; no ; -- ; -- ;
-; UFMD[8]~5 ; LC_X3_Y2_N8 ; 7 ; Clock enable ; no ; -- ; -- ;
+; CS[0]~2 ; LC_X5_Y4_N5 ; 3 ; Clock enable ; no ; -- ; -- ;
+; Equal9~0 ; LC_X6_Y2_N1 ; 14 ; Clock enable ; no ; -- ; -- ;
+; Equal9~1 ; LC_X6_Y2_N7 ; 8 ; Clock enable ; no ; -- ; -- ;
+; RA[4]~1 ; LC_X3_Y1_N5 ; 8 ; Clock enable ; no ; -- ; -- ;
+; RDOE ; LC_X3_Y1_N3 ; 8 ; Output enable ; no ; -- ; -- ;
+; RWBank[4]~1 ; LC_X6_Y4_N4 ; 13 ; Clock enable ; no ; -- ; -- ;
+; RWMask[4]~2 ; LC_X3_Y3_N9 ; 8 ; Clock enable ; no ; -- ; -- ;
+; S[2] ; LC_X6_Y2_N9 ; 20 ; Sync. clear ; no ; -- ; -- ;
+; UFMD[8]~5 ; LC_X4_Y3_N5 ; 7 ; Clock enable ; no ; -- ; -- ;
+-------------+-------------+---------+---------------+--------+----------------------+------------------+
@@ -534,8 +531,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+----------------------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+----------------------------------------------------------------------------------------------+---------+
-; S[0] ; 34 ;
-; S[1] ; 29 ;
+; S[0] ; 35 ;
+; S[1] ; 30 ;
; Equal9~4 ; 23 ;
; S[3] ; 22 ;
; S[2] ; 20 ;
@@ -545,6 +542,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Din[2] ; 10 ;
; Din[0] ; 10 ;
; CS[1] ; 9 ;
+; FS[4] ; 9 ;
; Din[3] ; 8 ;
; Din[7] ; 8 ;
; Din[6] ; 8 ;
@@ -554,17 +552,16 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; CS[0] ; 8 ;
; RWSel ; 8 ;
; RA[4]~1 ; 8 ;
-; FS[4] ; 8 ;
; Equal9~1 ; 8 ;
; Din[5] ; 7 ;
; Din[4] ; 7 ;
; UFMD[8]~5 ; 7 ;
; always1~9 ; 7 ;
; CS[2] ; 7 ;
+; FS[5] ; 7 ;
; UFMReqErase ; 6 ;
; UFMInitDone ; 6 ;
; FS[0] ; 6 ;
-; FS[5] ; 6 ;
; always1~1 ; 5 ;
; FS[3] ; 5 ;
; FS[2]~27 ; 5 ;
@@ -582,7 +579,7 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Equal9~3 ; 4 ;
; DRCLK~0 ; 4 ;
; Equal9~2 ; 4 ;
-; UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component|wire_maxii_ufm_block1_drdout ; 4 ;
+; UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component|wire_maxii_ufm_block1_drdout ; 4 ;
; S[3]~9 ; 3 ;
; UFMD[11] ; 3 ;
; UFMD[9] ; 3 ;
@@ -605,8 +602,6 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; FS[1] ; 3 ;
; always2~0 ; 3 ;
; Ready~0 ; 3 ;
-; nCS~2 ; 3 ;
-; FS[6] ; 3 ;
; Equal10~1 ; 3 ;
; FS[12]~1 ; 3 ;
; RD[7]~7 ; 2 ;
@@ -633,10 +628,11 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; always1~3 ; 2 ;
; UFMD[8]~4 ; 2 ;
; RWBank[6] ; 2 ;
-; nCS~5 ; 2 ;
; nCS~4 ; 2 ;
+; nCS~3 ; 2 ;
; Equal12~0 ; 2 ;
; FS[7] ; 2 ;
+; FS[6] ; 2 ;
; Equal10~2 ; 2 ;
; FS[11] ; 2 ;
; FS[10] ; 2 ;
@@ -715,16 +711,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; RWBank[4] ; 1 ;
; nRWE~1 ; 1 ;
; nRWE~0 ; 1 ;
+; nCAS~2 ; 1 ;
; nCAS~1 ; 1 ;
; nCAS~0 ; 1 ;
; FS[3]~29COUT1_46 ; 1 ;
; FS[3]~29 ; 1 ;
; FS[1]~25COUT1_44 ; 1 ;
; FS[1]~25 ; 1 ;
-; Equal10~3 ; 1 ;
-; nCS~3 ; 1 ;
; FS[6]~21COUT1_52 ; 1 ;
; FS[6]~21 ; 1 ;
+; Equal10~3 ; 1 ;
+; nCS~2 ; 1 ;
; FS[5]~19COUT1_50 ; 1 ;
; FS[5]~19 ; 1 ;
; FS[4]~17COUT1_48 ; 1 ;
@@ -787,8 +784,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Dout[2]~reg0 ; 1 ;
; Dout[1]~reg0 ; 1 ;
; Dout[0]~reg0 ; 1 ;
-; UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component|wire_maxii_ufm_block1_bgpbusy ; 1 ;
-; UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component|wire_maxii_ufm_block1_busy ; 1 ;
+; UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component|wire_maxii_ufm_block1_bgpbusy ; 1 ;
+; UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component|wire_maxii_ufm_block1_busy ; 1 ;
+----------------------------------------------------------------------------------------------+---------+
@@ -797,13 +794,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+-----------------------------+--------------------+
; Other Routing Resource Type ; Usage ;
+-----------------------------+--------------------+
-; C4s ; 142 / 784 ( 18 % ) ;
-; Direct links ; 49 / 888 ( 6 % ) ;
+; C4s ; 133 / 784 ( 17 % ) ;
+; Direct links ; 50 / 888 ( 6 % ) ;
; Global clocks ; 1 / 4 ( 25 % ) ;
; LAB clocks ; 6 / 32 ( 19 % ) ;
-; LUT chains ; 13 / 216 ( 6 % ) ;
-; Local interconnects ; 306 / 888 ( 34 % ) ;
-; R4s ; 151 / 704 ( 21 % ) ;
+; LUT chains ; 16 / 216 ( 7 % ) ;
+; Local interconnects ; 266 / 888 ( 30 % ) ;
+; R4s ; 115 / 704 ( 16 % ) ;
+-----------------------------+--------------------+
@@ -813,14 +810,14 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Number of Logic Elements (Average = 8.59) ; Number of LABs (Total = 22) ;
+--------------------------------------------+------------------------------+
; 1 ; 0 ;
-; 2 ; 1 ;
-; 3 ; 1 ;
+; 2 ; 0 ;
+; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 0 ;
-; 6 ; 1 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 4 ;
+; 6 ; 0 ;
+; 7 ; 1 ;
+; 8 ; 3 ;
+; 9 ; 2 ;
; 10 ; 13 ;
+--------------------------------------------+------------------------------+
@@ -830,8 +827,8 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.36) ; Number of LABs (Total = 22) ;
+------------------------------------+------------------------------+
-; 1 Clock ; 21 ;
-; 1 Clock enable ; 8 ;
+; 1 Clock ; 20 ;
+; 1 Clock enable ; 9 ;
; 2 Clock enables ; 1 ;
+------------------------------------+------------------------------+
@@ -843,17 +840,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
-; 2 ; 1 ;
-; 3 ; 1 ;
+; 2 ; 0 ;
+; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
-; 8 ; 1 ;
-; 9 ; 4 ;
+; 8 ; 3 ;
+; 9 ; 1 ;
; 10 ; 11 ;
-; 11 ; 0 ;
-; 12 ; 1 ;
+; 11 ; 2 ;
+; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
@@ -864,49 +861,48 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out (Average = 6.68) ; Number of LABs (Total = 22) ;
+; Number of Signals Sourced Out (Average = 5.91) ; Number of LABs (Total = 22) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
-; 3 ; 2 ;
-; 4 ; 2 ;
-; 5 ; 2 ;
-; 6 ; 2 ;
+; 3 ; 4 ;
+; 4 ; 3 ;
+; 5 ; 1 ;
+; 6 ; 3 ;
; 7 ; 2 ;
-; 8 ; 7 ;
+; 8 ; 6 ;
; 9 ; 1 ;
-; 10 ; 3 ;
+; 10 ; 1 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
-; Number of Distinct Inputs (Average = 11.73) ; Number of LABs (Total = 22) ;
+; Number of Distinct Inputs (Average = 10.05) ; Number of LABs (Total = 22) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 1 ;
+; 4 ; 1 ;
+; 5 ; 2 ;
; 6 ; 1 ;
-; 7 ; 1 ;
-; 8 ; 0 ;
-; 9 ; 5 ;
-; 10 ; 0 ;
-; 11 ; 1 ;
-; 12 ; 1 ;
+; 7 ; 0 ;
+; 8 ; 3 ;
+; 9 ; 1 ;
+; 10 ; 2 ;
+; 11 ; 2 ;
+; 12 ; 2 ;
; 13 ; 1 ;
-; 14 ; 2 ;
+; 14 ; 1 ;
; 15 ; 1 ;
-; 16 ; 1 ;
+; 16 ; 0 ;
; 17 ; 1 ;
; 18 ; 0 ;
-; 19 ; 2 ;
+; 19 ; 1 ;
; 20 ; 1 ;
-; 21 ; 1 ;
+----------------------------------------------+------------------------------+
@@ -929,19 +925,17 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
; Fitter Messages ;
+-----------------+
Warning (20028): Parallel compilation is not licensed and has been disabled
-Info (119006): Selected device 5M240ZT100C5 for design "RAM2E"
+Info (119006): Selected device EPM240T100C5 for design "RAM2E"
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device 5M80ZT100C5 is compatible
- Info (176445): Device 5M80ZT100I5 is compatible
- Info (176445): Device 5M160ZT100C5 is compatible
- Info (176445): Device 5M160ZT100I5 is compatible
- Info (176445): Device 5M240ZT100I5 is compatible
- Info (176445): Device 5M570ZT100C5 is compatible
- Info (176445): Device 5M570ZT100I5 is compatible
+ Info (176445): Device EPM240T100I5 is compatible
+ Info (176445): Device EPM240T100A5 is compatible
+ Info (176445): Device EPM570T100C5 is compatible
+ Info (176445): Device EPM570T100I5 is compatible
+ Info (176445): Device EPM570T100A5 is compatible
Info (332104): Reading SDC File: 'constraints.sdc'
Warning (332060): Node: DRCLK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: ARCLK was determined to be a clock but was found without an associated clock assignment.
@@ -965,23 +959,24 @@ Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 19% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
+Info (170089): 4e+01 ns of routing delay (approximately 2.6% of available device routing delay) has been added to meet hold timing. For more information, refer to the Estimated Delay Added for Hold Timing section in the Fitter report.
+Info (170195): Router estimated average interconnect usage is 18% of the available device resources
+ Info (170196): Router estimated peak interconnect usage is 18% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
-Info (11888): Total time spent on timing analysis during the Fitter is 0.13 seconds.
+Info (11888): Total time spent on timing analysis during the Fitter is 0.23 seconds.
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00
Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
-Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg
+Info (144001): Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg
Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 4767 megabytes
- Info: Processing ended: Wed Sep 16 20:14:40 2020
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
+ Info: Peak virtual memory: 4758 megabytes
+ Info: Processing ended: Thu Jan 28 14:37:18 2021
+ Info: Elapsed time: 00:00:03
+ Info: Total CPU time (on all processors): 00:00:03
+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
-The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg.
+The suppressed messages can be found in C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.fit.smsg.
diff --git a/cpld/output_files/RAM2E.fit.summary b/cpld/output_files/RAM2E.fit.summary
index 06d81ca..cf4e1b6 100755
--- a/cpld/output_files/RAM2E.fit.summary
+++ b/cpld/output_files/RAM2E.fit.summary
@@ -1,11 +1,11 @@
-Fitter Status : Successful - Wed Sep 16 20:14:40 2020
+Fitter Status : Successful - Thu Jan 28 14:37:18 2021
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
-Family : MAX V
-Device : 5M240ZT100C5
+Family : MAX II
+Device : EPM240T100C5
Timing Models : Final
Total logic elements : 189 / 240 ( 79 % )
-Total pins : 69 / 79 ( 87 % )
+Total pins : 69 / 80 ( 86 % )
Total virtual pins : 0
UFM blocks : 1 / 1 ( 100 % )
diff --git a/cpld/output_files/RAM2E.flow.rpt b/cpld/output_files/RAM2E.flow.rpt
index eabeaf8..9e57f9b 100755
--- a/cpld/output_files/RAM2E.flow.rpt
+++ b/cpld/output_files/RAM2E.flow.rpt
@@ -1,5 +1,5 @@
Flow report for RAM2E
-Wed Sep 16 20:14:43 2020
+Thu Jan 28 14:37:23 2021
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@@ -40,15 +40,15 @@ applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------+-------------------------------------------------+
-; Flow Status ; Successful - Wed Sep 16 20:14:41 2020 ;
+; Flow Status ; Successful - Thu Jan 28 14:37:20 2021 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
-; Family ; MAX V ;
-; Device ; 5M240ZT100C5 ;
+; Family ; MAX II ;
+; Device ; EPM240T100C5 ;
; Timing Models ; Final ;
; Total logic elements ; 189 / 240 ( 79 % ) ;
-; Total pins ; 69 / 79 ( 87 % ) ;
+; Total pins ; 69 / 80 ( 86 % ) ;
; Total virtual pins ; 0 ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
+---------------------------+-------------------------------------------------+
@@ -59,33 +59,33 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
-; Start date & time ; 09/16/2020 20:14:37 ;
+; Start date & time ; 01/28/2021 14:37:13 ;
; Main task ; Compilation ;
; Revision Name ; RAM2E ;
+-------------------+---------------------+
-+-----------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+------------------------------------+---------------------------------+---------------+-------------+------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+------------------------------------+---------------------------------+---------------+-------------+------------+
-; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ;
-; COMPILER_SIGNATURE_ID ; 207120313862967.160030167703488 ; -- ; -- ; -- ;
-; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
-; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ;
-; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; OPTIMIZE_MULTI_CORNER_TIMING ; On ; Off ; -- ; -- ;
-; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ;
-; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ;
-; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ;
-; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
-; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
-+------------------------------------+---------------------------------+---------------+-------------+------------+
++----------------------------------------------------------------------------------------------------------------+
+; Flow Non-Default Global Settings ;
++------------------------------------+--------------------------------+---------------+-------------+------------+
+; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
++------------------------------------+--------------------------------+---------------+-------------+------------+
+; ALLOW_POWER_UP_DONT_CARE ; Off ; On ; -- ; -- ;
+; COMPILER_SIGNATURE_ID ; 10995770589203.161186263308136 ; -- ; -- ; -- ;
+; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
+; IP_TOOL_NAME ; ALTUFM_NONE ; -- ; -- ; -- ;
+; IP_TOOL_VERSION ; 13.0 ; -- ; -- ; -- ;
+; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
+; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
+; OPTIMIZE_MULTI_CORNER_TIMING ; On ; Off ; -- ; -- ;
+; PARALLEL_SYNTHESIS ; Off ; On ; -- ; -- ;
+; POWER_DEFAULT_INPUT_IO_TOGGLE_RATE ; 12.5 % ; 12.5% ; -- ; -- ;
+; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ;
+; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
+; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ;
+; SYNTH_MESSAGE_LEVEL ; High ; Medium ; -- ; -- ;
+; SYNTH_TIMING_DRIVEN_SYNTHESIS ; Off ; -- ; -- ; -- ;
++------------------------------------+--------------------------------+---------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------+
@@ -93,11 +93,11 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:01 ; 1.0 ; 4568 MB ; 00:00:01 ;
-; Fitter ; 00:00:01 ; 1.0 ; 4767 MB ; 00:00:01 ;
-; Assembler ; 00:00:00 ; 1.0 ; 4524 MB ; 00:00:00 ;
-; TimeQuest Timing Analyzer ; 00:00:01 ; 1.0 ; 4522 MB ; 00:00:01 ;
-; Total ; 00:00:03 ; -- ; -- ; 00:00:03 ;
+; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4566 MB ; 00:00:02 ;
+; Fitter ; 00:00:03 ; 1.0 ; 4758 MB ; 00:00:03 ;
+; Assembler ; 00:00:01 ; 1.0 ; 4515 MB ; 00:00:01 ;
+; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4513 MB ; 00:00:02 ;
+; Total ; 00:00:08 ; -- ; -- ; 00:00:08 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
@@ -106,10 +106,10 @@ applicable agreement for further details.
+---------------------------+------------------+-----------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+---------------------------+------------------+-----------+------------+----------------+
-; Analysis & Synthesis ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
-; Fitter ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
-; Assembler ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
-; TimeQuest Timing Analyzer ; DESKTOP-G62HNQS ; Windows 7 ; 6.2 ; x86_64 ;
+; Analysis & Synthesis ; DESKTOP-DG54GN4 ; Windows 7 ; 6.2 ; x86_64 ;
+; Fitter ; DESKTOP-DG54GN4 ; Windows 7 ; 6.2 ; x86_64 ;
+; Assembler ; DESKTOP-DG54GN4 ; Windows 7 ; 6.2 ; x86_64 ;
+; TimeQuest Timing Analyzer ; DESKTOP-DG54GN4 ; Windows 7 ; 6.2 ; x86_64 ;
+---------------------------+------------------+-----------+------------+----------------+
diff --git a/cpld/output_files/RAM2E.jdi b/cpld/output_files/RAM2E.jdi
index a754f33..baa35a3 100755
--- a/cpld/output_files/RAM2E.jdi
+++ b/cpld/output_files/RAM2E.jdi
@@ -1,8 +1,8 @@
-
+
-
+
diff --git a/cpld/output_files/RAM2E.map.rpt b/cpld/output_files/RAM2E.map.rpt
index 5c0d3aa..e9b2487 100755
--- a/cpld/output_files/RAM2E.map.rpt
+++ b/cpld/output_files/RAM2E.map.rpt
@@ -1,5 +1,5 @@
Analysis & Synthesis report for RAM2E
-Wed Sep 16 20:14:38 2020
+Thu Jan 28 14:37:15 2021
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@@ -45,11 +45,11 @@ applicable agreement for further details.
+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Wed Sep 16 20:14:38 2020 ;
+; Analysis & Synthesis Status ; Successful - Thu Jan 28 14:37:15 2021 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
; Top-level Entity Name ; RAM2E ;
-; Family ; MAX V ;
+; Family ; MAX II ;
; Total logic elements ; 198 ;
; Total pins ; 69 ;
; Total virtual pins ; 0 ;
@@ -62,9 +62,9 @@ applicable agreement for further details.
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------------+--------------------+--------------------+
-; Device ; 5M240ZT100C5 ; ;
+; Device ; EPM240T100C5 ; ;
; Top-level entity name ; RAM2E ; RAM2E ;
-; Family name ; MAX V ; Cyclone IV GX ;
+; Family name ; MAX II ; Cyclone IV GX ;
; Safe State Machine ; On ; Off ;
; Parallel Synthesis ; Off ; On ;
; Power-Up Don't Care ; Off ; On ;
@@ -141,15 +141,15 @@ Parallel compilation was disabled, but you have multiple processors available. E
+----------------------------+--------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------+---------+
-; RAM2E.v ; yes ; User Verilog HDL File ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.v ; ;
-; RAM2E.mif ; yes ; User Memory Initialization File ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/RAM2E.mif ; ;
-; UFM.v ; yes ; User Wizard-Generated File ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v ; ;
-+----------------------------------+-----------------+----------------------------------+-----------------------------------------------------+---------+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------------------+---------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
++----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------------------+---------+
+; RAM2E.v ; yes ; User Verilog HDL File ; C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.v ; ;
+; RAM2E.mif ; yes ; User Memory Initialization File ; C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/RAM2E.mif ; ;
+; UFM.v ; yes ; User Wizard-Generated File ; C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v ; ;
++----------------------------------+-----------------+----------------------------------+-----------------------------------------------------------------------+---------+
+-----------------------------------------------------+
@@ -164,8 +164,8 @@ Parallel compilation was disabled, but you have multiple processors available. E
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 90 ;
-; -- 3 input functions ; 42 ;
-; -- 2 input functions ; 36 ;
+; -- 3 input functions ; 43 ;
+; -- 2 input functions ; 35 ;
; -- 1 input functions ; 3 ;
; -- 0 input functions ; 1 ;
; ; ;
@@ -183,7 +183,7 @@ Parallel compilation was disabled, but you have multiple processors available. E
; UFM blocks ; 1 ;
; Maximum fan-out node ; C14M ;
; Maximum fan-out ; 107 ;
-; Total fan-out ; 814 ;
+; Total fan-out ; 815 ;
; Average fan-out ; 3.04 ;
+---------------------------------------------+-------+
@@ -195,18 +195,18 @@ Parallel compilation was disabled, but you have multiple processors available. E
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+
; |RAM2E ; 198 (198) ; 107 ; 1 ; 69 ; 0 ; 91 (91) ; 26 (26) ; 81 (81) ; 15 (15) ; 0 (0) ; |RAM2E ; work ;
; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; work ;
-; |UFM_altufm_none_e4r:UFM_altufm_none_e4r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component ; work ;
+; |UFM_altufm_none_a7r:UFM_altufm_none_a7r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component ; work ;
+-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-+---------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis IP Cores Summary ;
-+--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------+
-; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
-+--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------+
-; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM2E|UFM:UFM_inst ; C:/Users/Zane/Documents/GitHub/RAM2E/cpld/UFM.v ;
-+--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis IP Cores Summary ;
++--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------------------------+
+; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
++--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------------------------+
+; Altera ; ALTUFM_NONE ; 13.0 ; N/A ; N/A ; |RAM2E|UFM:UFM_inst ; C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/UFM.v ;
++--------+--------------+---------+--------------+--------------+---------------------+-------------------------------------------------------------------+
+------------------------------------------------------+
@@ -268,13 +268,13 @@ Note: For table entries with two numbers listed, the numbers in parentheses indi
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
- Info: Processing started: Wed Sep 16 20:14:37 2020
+ Info: Processing started: Thu Jan 28 14:37:13 2021
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E -c RAM2E
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file ram2e.v
Info (12023): Found entity 1: RAM2E
Info (12021): Found 2 design units, including 2 entities, in source file ufm.v
- Info (12023): Found entity 1: UFM_altufm_none_e4r
+ Info (12023): Found entity 1: UFM_altufm_none_a7r
Info (12023): Found entity 2: UFM
Info (12127): Elaborating entity "RAM2E" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at RAM2E.v(100): truncated value with size 32 to match size of target (16)
@@ -282,24 +282,24 @@ Warning (10230): Verilog HDL assignment warning at RAM2E.v(103): truncated value
Warning (10230): Verilog HDL assignment warning at RAM2E.v(544): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at RAM2E.v(561): truncated value with size 32 to match size of target (3)
Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst"
-Info (12128): Elaborating entity "UFM_altufm_none_e4r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_e4r:UFM_altufm_none_e4r_component"
+Info (12128): Elaborating entity "UFM_altufm_none_a7r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_a7r:UFM_altufm_none_a7r_component"
Info (21057): Implemented 268 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 22 input pins
Info (21059): Implemented 39 output pins
Info (21060): Implemented 8 bidirectional pins
Info (21061): Implemented 198 logic cells
Info (21070): Implemented 1 User Flash Memory blocks
-Info (144001): Generated suppressed messages file C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg
+Info (144001): Generated suppressed messages file C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 5 warnings
- Info: Peak virtual memory: 4568 megabytes
- Info: Processing ended: Wed Sep 16 20:14:38 2020
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
+ Info: Peak virtual memory: 4566 megabytes
+ Info: Processing ended: Thu Jan 28 14:37:15 2021
+ Info: Elapsed time: 00:00:02
+ Info: Total CPU time (on all processors): 00:00:02
+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
-The suppressed messages can be found in C:/Users/Zane/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg.
+The suppressed messages can be found in C:/Users/wgfel_69wkrf3/OneDrive/Documents/GitHub/RAM2E/cpld/output_files/RAM2E.map.smsg.
diff --git a/cpld/output_files/RAM2E.map.summary b/cpld/output_files/RAM2E.map.summary
index ab29896..b2d32b6 100755
--- a/cpld/output_files/RAM2E.map.summary
+++ b/cpld/output_files/RAM2E.map.summary
@@ -1,8 +1,8 @@
-Analysis & Synthesis Status : Successful - Wed Sep 16 20:14:38 2020
+Analysis & Synthesis Status : Successful - Thu Jan 28 14:37:15 2021
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : RAM2E
Top-level Entity Name : RAM2E
-Family : MAX V
+Family : MAX II
Total logic elements : 198
Total pins : 69
Total virtual pins : 0
diff --git a/cpld/output_files/RAM2E.pin b/cpld/output_files/RAM2E.pin
index ca74001..488d736 100755
--- a/cpld/output_files/RAM2E.pin
+++ b/cpld/output_files/RAM2E.pin
@@ -23,7 +23,7 @@
---------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.8V).
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V).
-- VCCIO : Dedicated power pin, which MUST be connected to VCC
-- of its bank.
-- Bank 1: 3.3V
@@ -58,11 +58,11 @@
---------------------------------------------------------------------------------
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-CHIP "RAM2E" ASSIGNED TO AN: 5M240ZT100C5
+CHIP "RAM2E" ASSIGNED TO AN: EPM240T100C5
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
-GND : 1 : gnd : : : :
+GND* : 1 : : : : 2 :
nRWE : 2 : output : 3.3-V LVCMOS : : 1 : Y
nCAS : 3 : output : 3.3-V LVCMOS : : 1 : Y
CKE : 4 : output : 3.3-V LVCMOS : : 1 : Y
@@ -71,10 +71,10 @@ BA[0] : 6 : output : 3.3-V LVCMOS :
RA[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y
nCS : 8 : output : 3.3-V LVCMOS : : 1 : Y
VCCIO1 : 9 : power : : 3.3V : 1 :
-GND : 10 : gnd : : : :
-GND : 11 : gnd : : : :
+GNDIO : 10 : gnd : : : :
+GNDINT : 11 : gnd : : : :
C14M : 12 : input : 3.3-V LVCMOS : : 1 : Y
-VCCINT : 13 : power : : 1.8V : :
+VCCINT : 13 : power : : 2.5V/3.3V : :
BA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y
RA[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y
RA[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y
@@ -93,7 +93,7 @@ nEN80 : 28 : input : 3.3-V LVCMOS :
RA[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y
RA[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y
VCCIO1 : 31 : power : : 3.3V : 1 :
-GND : 32 : gnd : : : :
+GNDIO : 32 : gnd : : : :
nWE80 : 33 : input : 3.3-V LVCMOS : : 1 : Y
Ain[5] : 34 : input : 3.3-V LVCMOS : : 1 : Y
Din[7] : 35 : input : 3.3-V LVCMOS : : 1 : Y
@@ -107,7 +107,7 @@ Din[2] : 42 : input : 3.3-V LVCMOS :
Ain[2] : 43 : input : 3.3-V LVCMOS : : 1 : Y
Ain[4] : 44 : input : 3.3-V LVCMOS : : 1 : Y
VCCIO1 : 45 : power : : 3.3V : 1 :
-GND : 46 : gnd : : : :
+GNDIO : 46 : gnd : : : :
Ain[3] : 47 : input : 3.3-V LVCMOS : : 1 : Y
Din[4] : 48 : input : 3.3-V LVCMOS : : 1 : Y
Din[5] : 49 : input : 3.3-V LVCMOS : : 1 : Y
@@ -121,12 +121,12 @@ Ain[0] : 56 : input : 3.3-V LVCMOS :
Vout[7] : 57 : output : 3.3-V LVCMOS : : 2 : Y
Vout[6] : 58 : output : 3.3-V LVCMOS : : 2 : Y
VCCIO2 : 59 : power : : 3.3V : 2 :
-GND : 60 : gnd : : : :
+GNDIO : 60 : gnd : : : :
GND* : 61 : : : : 2 :
Vout[3] : 62 : output : 3.3-V LVCMOS : : 2 : Y
-VCCINT : 63 : power : : 1.8V : :
+VCCINT : 63 : power : : 2.5V/3.3V : :
GND* : 64 : : : : 2 :
-GND : 65 : gnd : : : :
+GNDINT : 65 : gnd : : : :
GND* : 66 : : : : 2 :
Vout[1] : 67 : output : 3.3-V LVCMOS : : 2 : Y
Vout[5] : 68 : output : 3.3-V LVCMOS : : 2 : Y
@@ -140,7 +140,7 @@ Dout[3] : 75 : output : 3.3-V LVCMOS :
Dout[1] : 76 : output : 3.3-V LVCMOS : : 2 : Y
Dout[0] : 77 : output : 3.3-V LVCMOS : : 2 : Y
GND* : 78 : : : : 2 :
-GND : 79 : gnd : : : :
+GNDIO : 79 : gnd : : : :
VCCIO2 : 80 : power : : 3.3V : 2 :
GND* : 81 : : : : 2 :
GND* : 82 : : : : 2 :
@@ -154,7 +154,7 @@ RD[3] : 89 : bidir : 3.3-V LVCMOS :
RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[4] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[5] : 92 : bidir : 3.3-V LVCMOS : : 2 : Y
-GND : 93 : gnd : : : :
+GNDIO : 93 : gnd : : : :
VCCIO2 : 94 : power : : 3.3V : 2 :
RD[6] : 95 : bidir : 3.3-V LVCMOS : : 2 : Y
RD[7] : 96 : bidir : 3.3-V LVCMOS : : 2 : Y
diff --git a/cpld/output_files/RAM2E.pof b/cpld/output_files/RAM2E.pof
index 866d2b5..5d3f3d9 100755
Binary files a/cpld/output_files/RAM2E.pof and b/cpld/output_files/RAM2E.pof differ
diff --git a/cpld/output_files/RAM2E.sta.rpt b/cpld/output_files/RAM2E.sta.rpt
index 0b484cc..0bfb889 100755
--- a/cpld/output_files/RAM2E.sta.rpt
+++ b/cpld/output_files/RAM2E.sta.rpt
@@ -1,5 +1,5 @@
TimeQuest Timing Analyzer report for RAM2E
-Wed Sep 16 20:14:43 2020
+Thu Jan 28 14:37:23 2021
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
@@ -59,8 +59,8 @@ applicable agreement for further details.
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name ; RAM2E ;
-; Device Family ; MAX V ;
-; Device Name ; 5M240ZT100C5 ;
+; Device Family ; MAX II ;
+; Device Name ; EPM240T100C5 ;
; Timing Models ; Final ;
; Delay Model ; Slow Model ;
; Rise/Fall Delays ; Unavailable ;
@@ -83,7 +83,7 @@ Parallel compilation was disabled, but you have multiple processors available. E
+-----------------+--------+--------------------------+
; SDC File Path ; Status ; Read at ;
+-----------------+--------+--------------------------+
-; constraints.sdc ; OK ; Wed Sep 16 20:14:43 2020 ;
+; constraints.sdc ; OK ; Thu Jan 28 14:37:22 2021 ;
+-----------------+--------+--------------------------+
@@ -96,13 +96,13 @@ Parallel compilation was disabled, but you have multiple processors available. E
+------------+------+--------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+----------+
-+------------------------------------------------+
-; Fmax Summary ;
-+----------+-----------------+------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+----------+-----------------+------------+------+
-; 35.4 MHz ; 35.4 MHz ; C14M ; ;
-+----------+-----------------+------------+------+
++-------------------------------------------------+
+; Fmax Summary ;
++-----------+-----------------+------------+------+
+; Fmax ; Restricted Fmax ; Clock Name ; Note ;
++-----------+-----------------+------------+------+
+; 86.93 MHz ; 86.93 MHz ; C14M ; ;
++-----------+-----------------+------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
@@ -111,7 +111,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
-; C14M ; 21.694 ; 0.000 ;
+; C14M ; 29.169 ; 0.000 ;
+-------+--------+---------------+
@@ -120,7 +120,7 @@ This panel reports FMAX for every clock in the design, regardless of the user-sp
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
-; C14M ; 3.144 ; 0.000 ;
+; C14M ; 1.646 ; 0.000 ;
+-------+-------+---------------+
@@ -141,7 +141,7 @@ No paths to report.
+-------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+--------+---------------+
-; C14M ; 34.581 ; 0.000 ;
+; C14M ; 34.654 ; 0.000 ;
+-------+--------+---------------+
@@ -150,106 +150,106 @@ No paths to report.
+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
-; 21.694 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.905 ;
-; 21.873 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ;
-; 21.873 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ;
-; 21.873 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ;
-; 21.873 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ;
-; 21.873 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ;
-; 21.873 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.726 ;
-; 21.885 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.714 ;
-; 22.064 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ;
-; 22.064 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ;
-; 22.064 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ;
-; 22.064 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ;
-; 22.064 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ;
-; 22.064 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.535 ;
-; 22.113 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.486 ;
-; 22.213 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.386 ;
-; 22.213 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.386 ;
-; 22.292 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ;
-; 22.292 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ;
-; 22.292 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ;
-; 22.292 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ;
-; 22.292 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ;
-; 22.292 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.307 ;
-; 22.362 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.237 ;
-; 22.362 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.237 ;
-; 22.362 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.237 ;
-; 22.478 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.121 ;
-; 22.478 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.121 ;
-; 22.627 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.972 ;
-; 22.627 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.972 ;
-; 22.627 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.972 ;
-; 22.949 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.650 ;
-; 23.140 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.459 ;
-; 23.265 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.334 ;
-; 23.265 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.334 ;
-; 23.368 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.231 ;
-; 23.391 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.208 ;
-; 23.414 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.185 ;
-; 23.414 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.185 ;
-; 23.414 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.185 ;
-; 23.570 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ;
-; 23.570 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ;
-; 23.570 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ;
-; 23.570 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ;
-; 23.570 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ;
-; 23.570 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.029 ;
-; 23.915 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.684 ;
-; 23.915 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.684 ;
-; 24.064 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.535 ;
-; 24.064 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.535 ;
-; 24.064 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.535 ;
-; 24.646 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.953 ;
-; 25.589 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.010 ;
-; 25.589 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.010 ;
-; 25.589 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 9.010 ;
-; 25.854 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.745 ;
-; 25.854 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.745 ;
-; 25.854 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 8.745 ;
-; 26.641 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.958 ;
-; 26.641 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.958 ;
-; 26.641 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.958 ;
-; 27.291 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.308 ;
-; 27.291 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.308 ;
-; 27.291 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.308 ;
-; 41.591 ; UFMD[9] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 27.929 ;
-; 41.784 ; FS[7] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 27.736 ;
-; 41.793 ; FS[15] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 27.727 ;
-; 42.673 ; UFMD[9] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ;
-; 42.673 ; UFMD[9] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ;
-; 42.673 ; UFMD[9] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ;
-; 42.673 ; UFMD[9] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ;
-; 42.673 ; UFMD[9] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ;
-; 42.673 ; UFMD[9] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ;
-; 42.673 ; UFMD[9] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.847 ;
-; 42.716 ; FS[14] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.804 ;
-; 42.879 ; FS[15] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 26.641 ;
-; 42.937 ; FS[11] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.583 ;
-; 43.124 ; FS[10] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.396 ;
-; 43.146 ; FS[8] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.374 ;
-; 43.241 ; S[1] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 26.279 ;
-; 43.347 ; FS[13] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.173 ;
-; 43.431 ; FS[6] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 26.089 ;
-; 43.785 ; FS[9] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.735 ;
-; 43.803 ; FS[14] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.717 ;
-; 43.953 ; FS[5] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.567 ;
-; 43.961 ; FS[15] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ;
-; 43.961 ; FS[15] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ;
-; 43.961 ; FS[15] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ;
-; 43.961 ; FS[15] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ;
-; 43.961 ; FS[15] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ;
-; 43.961 ; FS[15] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ;
-; 43.961 ; FS[15] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.559 ;
-; 43.965 ; FS[12] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.555 ;
-; 44.433 ; FS[13] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 25.087 ;
-; 44.437 ; FS[2] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 25.083 ;
-; 44.708 ; S[0] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 24.812 ;
-; 44.745 ; CS[0] ; CS[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.775 ;
-; 44.748 ; CS[0] ; CS[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.772 ;
-; 44.749 ; CS[0] ; CS[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 24.771 ;
-; 44.765 ; S[2] ; UFMReqErase ; C14M ; C14M ; 69.841 ; 0.000 ; 24.755 ;
+; 29.169 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.418 ;
+; 29.242 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.345 ;
+; 29.242 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.345 ;
+; 29.242 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.345 ;
+; 29.242 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.345 ;
+; 29.242 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.345 ;
+; 29.242 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.345 ;
+; 29.254 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.333 ;
+; 29.254 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.333 ;
+; 29.272 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.315 ;
+; 29.272 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.315 ;
+; 29.272 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.315 ;
+; 29.351 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.236 ;
+; 29.367 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.220 ;
+; 29.424 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.163 ;
+; 29.424 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.163 ;
+; 29.424 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.163 ;
+; 29.424 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.163 ;
+; 29.424 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.163 ;
+; 29.424 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.163 ;
+; 29.435 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.152 ;
+; 29.435 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.152 ;
+; 29.453 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.134 ;
+; 29.453 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.134 ;
+; 29.453 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.134 ;
+; 29.521 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.066 ;
+; 29.549 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.038 ;
+; 29.594 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.993 ;
+; 29.594 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.993 ;
+; 29.594 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.993 ;
+; 29.594 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.993 ;
+; 29.594 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.993 ;
+; 29.594 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.993 ;
+; 29.621 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.966 ;
+; 29.621 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.966 ;
+; 29.639 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.948 ;
+; 29.639 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.948 ;
+; 29.639 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.948 ;
+; 29.719 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.868 ;
+; 29.881 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.706 ;
+; 29.954 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.633 ;
+; 29.954 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.633 ;
+; 29.954 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.633 ;
+; 29.954 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.633 ;
+; 29.954 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.633 ;
+; 29.954 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.633 ;
+; 29.977 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.610 ;
+; 29.977 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.610 ;
+; 29.995 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.592 ;
+; 29.995 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.592 ;
+; 29.995 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.592 ;
+; 30.012 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.575 ;
+; 30.012 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.575 ;
+; 30.012 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.575 ;
+; 30.079 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.508 ;
+; 30.193 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.394 ;
+; 30.193 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.394 ;
+; 30.193 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.394 ;
+; 30.379 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.208 ;
+; 30.379 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.208 ;
+; 30.379 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.208 ;
+; 30.735 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.852 ;
+; 30.735 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.852 ;
+; 30.735 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 3.852 ;
+; 58.538 ; FS[7] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.970 ;
+; 58.601 ; FS[8] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.907 ;
+; 58.922 ; FS[9] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.586 ;
+; 58.953 ; FS[7] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.555 ;
+; 59.016 ; FS[8] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.492 ;
+; 59.040 ; UFMD[14] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 10.468 ;
+; 59.040 ; UFMD[14] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 10.468 ;
+; 59.046 ; FS[6] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.462 ;
+; 59.200 ; FS[11] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.308 ;
+; 59.229 ; FS[7] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.279 ;
+; 59.292 ; FS[8] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.216 ;
+; 59.328 ; S[0] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 10.180 ;
+; 59.328 ; S[0] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 10.180 ;
+; 59.330 ; FS[10] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.178 ;
+; 59.337 ; FS[9] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.171 ;
+; 59.461 ; FS[6] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.047 ;
+; 59.476 ; UFMD[14] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 10.032 ;
+; 59.476 ; UFMD[14] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 10.032 ;
+; 59.476 ; UFMD[14] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 10.032 ;
+; 59.476 ; UFMD[14] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 10.032 ;
+; 59.476 ; UFMD[14] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 10.032 ;
+; 59.476 ; UFMD[14] ; RWMask[6] ; C14M ; C14M ; 69.841 ; 0.000 ; 10.032 ;
+; 59.490 ; FS[7] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 10.018 ;
+; 59.510 ; S[3] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 9.998 ;
+; 59.510 ; S[3] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 9.998 ;
+; 59.519 ; FS[12] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 9.989 ;
+; 59.553 ; FS[8] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 9.955 ;
+; 59.604 ; UFMD[13] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 9.904 ;
+; 59.604 ; UFMD[13] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 9.904 ;
+; 59.613 ; FS[9] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 9.895 ;
+; 59.615 ; FS[11] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 9.893 ;
+; 59.680 ; S[1] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 9.828 ;
+; 59.680 ; S[1] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 9.828 ;
+; 59.737 ; FS[6] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 9.771 ;
+; 59.745 ; FS[10] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 9.763 ;
+; 59.764 ; S[0] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 9.744 ;
+--------+-----------+--------------+--------------+-------------+--------------+------------+------------+
@@ -258,106 +258,106 @@ No paths to report.
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
-; 3.144 ; UFMD[13] ; UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.183 ;
-; 3.171 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.210 ;
-; 3.189 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.228 ;
-; 3.202 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.241 ;
-; 3.376 ; RWMask[7] ; RWBank[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.415 ;
-; 3.377 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.416 ;
-; 3.429 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.468 ;
-; 3.435 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.474 ;
-; 3.467 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.506 ;
-; 3.468 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.507 ;
-; 3.752 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.791 ;
-; 3.800 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.839 ;
-; 3.808 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.847 ;
-; 3.817 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.856 ;
-; 3.837 ; UFMD[11] ; RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.876 ;
-; 3.865 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.904 ;
-; 3.881 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.920 ;
-; 3.972 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 4.011 ;
-; 4.207 ; S[3] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.246 ;
-; 4.867 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 4.906 ;
-; 4.878 ; UFMEraseEN ; UFMEraseEN ; C14M ; C14M ; 0.000 ; 0.000 ; 4.917 ;
-; 4.913 ; S[2] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.952 ;
-; 4.935 ; FS[4] ; DRShift ; C14M ; C14M ; 0.000 ; 0.000 ; 4.974 ;
-; 5.216 ; UFMPrgmEN ; UFMPrgmEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.255 ;
-; 5.217 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.256 ;
-; 5.237 ; UFMReqErase ; UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.276 ;
-; 5.242 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.281 ;
-; 5.252 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.291 ;
-; 5.254 ; SetRWBankFF ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.293 ;
-; 5.261 ; SetRWBankFF ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.300 ;
-; 5.267 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.306 ;
-; 5.270 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.309 ;
-; 5.291 ; UFMInitDone ; DRShift ; C14M ; C14M ; 0.000 ; 0.000 ; 5.330 ;
-; 5.291 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.330 ;
-; 5.302 ; S[0] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.341 ;
-; 5.372 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.411 ;
-; 5.383 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.422 ;
-; 5.419 ; RWMask[5] ; RWBank[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.458 ;
-; 5.421 ; RWBank[4] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.460 ;
-; 5.441 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 5.480 ;
-; 5.442 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.481 ;
-; 5.452 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ;
-; 5.453 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.492 ;
-; 5.463 ; UFMBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.502 ;
-; 5.466 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.505 ;
-; 5.486 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.525 ;
-; 5.490 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.529 ;
-; 5.496 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.535 ;
-; 5.497 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.536 ;
-; 5.509 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.548 ;
-; 5.514 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.553 ;
-; 5.520 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.559 ;
-; 5.543 ; UFMReqErase ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.582 ;
-; 5.545 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.584 ;
-; 5.548 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.587 ;
-; 5.952 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.991 ;
-; 5.971 ; S[1] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.010 ;
-; 5.987 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.026 ;
-; 6.002 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.041 ;
-; 6.005 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.044 ;
-; 6.096 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.135 ;
-; 6.131 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.170 ;
-; 6.146 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.185 ;
-; 6.149 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.188 ;
-; 6.275 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.314 ;
-; 6.287 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.326 ;
-; 6.293 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.332 ;
-; 6.295 ; UFMD[14] ; RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.334 ;
-; 6.419 ; FS[8] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.458 ;
-; 6.444 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.483 ;
-; 6.454 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ;
-; 6.455 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.494 ;
-; 6.487 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 6.526 ;
-; 6.488 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.527 ;
-; 6.498 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.537 ;
-; 6.499 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.538 ;
-; 6.516 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.555 ;
-; 6.534 ; UFMD[13] ; RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.573 ;
-; 6.538 ; RTPBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 6.577 ;
-; 6.598 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.637 ;
-; 6.601 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.640 ;
-; 6.642 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.681 ;
-; 6.643 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.682 ;
-; 6.652 ; RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.691 ;
-; 6.782 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ;
-; 6.782 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ;
-; 6.782 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.821 ;
-; 6.786 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.825 ;
-; 6.787 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.826 ;
-; 6.918 ; UFMPrgmEN ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 6.957 ;
-; 6.929 ; FS[9] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ;
-; 6.929 ; FS[9] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ;
-; 6.929 ; FS[9] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.968 ;
-; 6.930 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.969 ;
-; 6.930 ; FS[3] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.969 ;
-; 7.023 ; FS[12] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ;
-; 7.023 ; FS[12] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ;
-; 7.023 ; FS[12] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.062 ;
-; 7.043 ; SetRWBankFF ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.082 ;
-; 7.046 ; SetRWBankFF ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.085 ;
+; 1.646 ; UFMBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 1.867 ;
+; 1.661 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.882 ;
+; 1.680 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.901 ;
+; 1.692 ; UFMD[14] ; RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.913 ;
+; 1.693 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 1.914 ;
+; 1.693 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.914 ;
+; 1.708 ; UFMInitDone ; DRShift ; C14M ; C14M ; 0.000 ; 0.000 ; 1.929 ;
+; 1.710 ; UFMPrgmEN ; UFMPrgmEN ; C14M ; C14M ; 0.000 ; 0.000 ; 1.931 ;
+; 1.784 ; UFMD[13] ; UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.005 ;
+; 1.785 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.006 ;
+; 1.800 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.021 ;
+; 1.855 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.076 ;
+; 1.905 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.126 ;
+; 1.921 ; RWBank[5] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.142 ;
+; 1.971 ; UFMEraseEN ; UFMEraseEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.192 ;
+; 1.973 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.194 ;
+; 1.976 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.197 ;
+; 2.047 ; RWBank[4] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.268 ;
+; 2.089 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.310 ;
+; 2.107 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ;
+; 2.108 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 2.329 ;
+; 2.108 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.329 ;
+; 2.118 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.339 ;
+; 2.119 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.340 ;
+; 2.127 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.348 ;
+; 2.129 ; RWBank[0] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.350 ;
+; 2.146 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.367 ;
+; 2.151 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.372 ;
+; 2.152 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.373 ;
+; 2.156 ; UFMD[9] ; RWMask[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.377 ;
+; 2.162 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.383 ;
+; 2.165 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.386 ;
+; 2.166 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.387 ;
+; 2.168 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 2.389 ;
+; 2.215 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.436 ;
+; 2.216 ; RWBank[1] ; RA[9]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.437 ;
+; 2.218 ; DRCLKPulse ; DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 2.439 ;
+; 2.225 ; RWBank[7] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.446 ;
+; 2.230 ; UFMPrgmEN ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.451 ;
+; 2.232 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.453 ;
+; 2.233 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.454 ;
+; 2.239 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
+; 2.239 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
+; 2.239 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.460 ;
+; 2.246 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.467 ;
+; 2.250 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.471 ;
+; 2.253 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.474 ;
+; 2.259 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.480 ;
+; 2.272 ; RWMask[6] ; RWBank[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.493 ;
+; 2.273 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.494 ;
+; 2.281 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.502 ;
+; 2.284 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.505 ;
+; 2.291 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.512 ;
+; 2.342 ; UFMD[13] ; RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.563 ;
+; 2.356 ; UFMD[10] ; RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.577 ;
+; 2.455 ; S[0] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.676 ;
+; 2.501 ; RTPBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.722 ;
+; 2.507 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.728 ;
+; 2.519 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.740 ;
+; 2.559 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.780 ;
+; 2.562 ; RWBank[3] ; RA[11]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.783 ;
+; 2.628 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.849 ;
+; 2.634 ; UFMD[8] ; RWMask[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.855 ;
+; 2.703 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.924 ;
+; 2.740 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.961 ;
+; 2.754 ; UFMD[12] ; RWMask[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.975 ;
+; 2.755 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.976 ;
+; 2.771 ; PHI1reg ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.992 ;
+; 2.771 ; S[2] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.992 ;
+; 2.775 ; UFMEraseEN ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.996 ;
+; 2.812 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.033 ;
+; 2.855 ; RWBank[2] ; RA[10]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.076 ;
+; 2.886 ; UFMD[11] ; RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.107 ;
+; 2.940 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.161 ;
+; 2.943 ; RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.164 ;
+; 2.983 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.204 ;
+; 2.984 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.205 ;
+; 2.987 ; RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.208 ;
+; 3.051 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.272 ;
+; 3.088 ; CS[1] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.309 ;
+; 3.094 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.315 ;
+; 3.095 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.316 ;
+; 3.110 ; FS[0] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.331 ;
+; 3.173 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.394 ;
+; 3.179 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ;
+; 3.179 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.400 ;
+; 3.199 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.420 ;
+; 3.206 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.427 ;
+; 3.212 ; UFMPrgmEN ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.433 ;
+; 3.213 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.434 ;
+; 3.217 ; S[0] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.438 ;
+; 3.221 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.442 ;
+; 3.223 ; UFMD[11] ; RWMask[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.444 ;
+; 3.231 ; RWBank[6] ; DQMH~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.452 ;
+; 3.231 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.452 ;
+; 3.290 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.511 ;
+; 3.309 ; Ready ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.530 ;
+; 3.309 ; CS[2] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.530 ;
+; 3.323 ; S[0] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.544 ;
+; 3.325 ; UFMReqErase ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.546 ;
+-------+-------------+-------------+--------------+-------------+--------------+------------+------------+
@@ -366,106 +366,106 @@ No paths to report.
+--------+--------------+----------------+------------------+-------+------------+--------------+
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
+--------+--------------+----------------+------------------+-------+------------+--------------+
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; ARCLK ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; ARShift ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; BA[0]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; BA[1]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CKE~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CS[0] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CS[1] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CS[2] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CmdTout[0] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CmdTout[1] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; CmdTout[2] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DOEEN ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DQMH~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DQML~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DRCLK ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DRCLKPulse ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DRDIn ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; DRShift ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[0]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[1]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[2]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[3]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[4]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[5]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[6]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Dout[7]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[0] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[10] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[11] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[12] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[13] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[14] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[15] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[1] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[2] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[3] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[4] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[5] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[6] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[7] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[8] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; FS[9] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; PHI1reg ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[0]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[10]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[11]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[1]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[2]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[3]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[4]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[5]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[6]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[7]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[8]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RA[9]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RTPBusyReg ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[0] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[1] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[2] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[3] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[4] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[5] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[6] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWBank[7] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMaskSet ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[0] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[1] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[2] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[3] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[4] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[5] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[6] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWMask[7] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; RWSel ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; Ready ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; S[0] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; S[1] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; S[2] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; S[3] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; SetRWBankFF ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMBitbang ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMBusyReg ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[10] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[11] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[12] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[13] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[14] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[8] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMD[9] ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMErase ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMEraseEN ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMInitDone ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMPrgmEN ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMProgram ;
-; 34.581 ; 34.920 ; 0.339 ; High Pulse Width ; C14M ; Rise ; UFMReqErase ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[0]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[1]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[2]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[3]~reg0 ;
-; 34.581 ; 34.920 ; 0.339 ; Low Pulse Width ; C14M ; Fall ; Vout[4]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; ARCLK ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; ARShift ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; BA[0]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; BA[1]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; CKE~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; CS[0] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; CS[1] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; CS[2] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; CmdTout[0] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; CmdTout[1] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; CmdTout[2] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; DOEEN ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; DQMH~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; DQML~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; DRCLK ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; DRCLKPulse ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; DRDIn ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; DRShift ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Dout[0]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Dout[1]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Dout[2]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Dout[3]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Dout[4]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Dout[5]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Dout[6]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Dout[7]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[0] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[10] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[11] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[12] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[13] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[14] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[15] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[1] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[2] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[3] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[4] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[5] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[6] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[7] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[8] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; FS[9] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; PHI1reg ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[0]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[10]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[11]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[1]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[2]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[3]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[4]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[5]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[6]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[7]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[8]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RA[9]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RTPBusyReg ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWBank[0] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWBank[1] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWBank[2] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWBank[3] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWBank[4] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWBank[5] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWBank[6] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWBank[7] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWMaskSet ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWMask[0] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWMask[1] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWMask[2] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWMask[3] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWMask[4] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWMask[5] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWMask[6] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWMask[7] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; RWSel ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; Ready ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; S[0] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; S[1] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; S[2] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; S[3] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; SetRWBankFF ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMBitbang ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMBusyReg ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMD[10] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMD[11] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMD[12] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMD[13] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMD[14] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMD[8] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMD[9] ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMErase ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMEraseEN ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMInitDone ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMPrgmEN ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMProgram ;
+; 34.654 ; 34.920 ; 0.266 ; High Pulse Width ; C14M ; Rise ; UFMReqErase ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Vout[0]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Vout[1]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Vout[2]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Vout[3]~reg0 ;
+; 34.654 ; 34.920 ; 0.266 ; Low Pulse Width ; C14M ; Fall ; Vout[4]~reg0 ;
+--------+--------------+----------------+------------------+-------+------------+--------------+
@@ -474,79 +474,79 @@ No paths to report.
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
-; Ain[*] ; C14M ; 7.321 ; 7.321 ; Rise ; C14M ;
-; Ain[0] ; C14M ; 6.351 ; 6.351 ; Rise ; C14M ;
-; Ain[1] ; C14M ; 6.333 ; 6.333 ; Rise ; C14M ;
-; Ain[2] ; C14M ; 5.149 ; 5.149 ; Rise ; C14M ;
-; Ain[3] ; C14M ; 7.321 ; 7.321 ; Rise ; C14M ;
-; Ain[4] ; C14M ; 5.426 ; 5.426 ; Rise ; C14M ;
-; Ain[5] ; C14M ; 5.226 ; 5.226 ; Rise ; C14M ;
-; Ain[6] ; C14M ; 5.188 ; 5.188 ; Rise ; C14M ;
-; Ain[7] ; C14M ; 4.595 ; 4.595 ; Rise ; C14M ;
-; Din[*] ; C14M ; 33.634 ; 33.634 ; Rise ; C14M ;
-; Din[0] ; C14M ; 33.634 ; 33.634 ; Rise ; C14M ;
-; Din[1] ; C14M ; 26.017 ; 26.017 ; Rise ; C14M ;
-; Din[2] ; C14M ; 32.536 ; 32.536 ; Rise ; C14M ;
-; Din[3] ; C14M ; 31.960 ; 31.960 ; Rise ; C14M ;
-; Din[4] ; C14M ; 31.598 ; 31.598 ; Rise ; C14M ;
-; Din[5] ; C14M ; 33.103 ; 33.103 ; Rise ; C14M ;
-; Din[6] ; C14M ; 31.911 ; 31.911 ; Rise ; C14M ;
-; Din[7] ; C14M ; 31.466 ; 31.466 ; Rise ; C14M ;
-; PHI1 ; C14M ; 16.699 ; 16.699 ; Rise ; C14M ;
-; nC07X ; C14M ; 9.809 ; 9.809 ; Rise ; C14M ;
-; nEN80 ; C14M ; 10.700 ; 10.700 ; Rise ; C14M ;
-; nWE ; C14M ; 11.877 ; 11.877 ; Rise ; C14M ;
-; nWE80 ; C14M ; 10.141 ; 10.141 ; Rise ; C14M ;
-; RD[*] ; C14M ; 8.337 ; 8.337 ; Fall ; C14M ;
-; RD[0] ; C14M ; 6.777 ; 6.777 ; Fall ; C14M ;
-; RD[1] ; C14M ; 7.239 ; 7.239 ; Fall ; C14M ;
-; RD[2] ; C14M ; 8.337 ; 8.337 ; Fall ; C14M ;
-; RD[3] ; C14M ; 7.110 ; 7.110 ; Fall ; C14M ;
-; RD[4] ; C14M ; 4.993 ; 4.993 ; Fall ; C14M ;
-; RD[5] ; C14M ; 7.210 ; 7.210 ; Fall ; C14M ;
-; RD[6] ; C14M ; 7.056 ; 7.056 ; Fall ; C14M ;
-; RD[7] ; C14M ; 6.879 ; 6.879 ; Fall ; C14M ;
+; Ain[*] ; C14M ; 2.178 ; 2.178 ; Rise ; C14M ;
+; Ain[0] ; C14M ; 1.870 ; 1.870 ; Rise ; C14M ;
+; Ain[1] ; C14M ; 2.178 ; 2.178 ; Rise ; C14M ;
+; Ain[2] ; C14M ; 1.938 ; 1.938 ; Rise ; C14M ;
+; Ain[3] ; C14M ; 1.974 ; 1.974 ; Rise ; C14M ;
+; Ain[4] ; C14M ; 1.945 ; 1.945 ; Rise ; C14M ;
+; Ain[5] ; C14M ; 1.818 ; 1.818 ; Rise ; C14M ;
+; Ain[6] ; C14M ; 1.987 ; 1.987 ; Rise ; C14M ;
+; Ain[7] ; C14M ; 1.699 ; 1.699 ; Rise ; C14M ;
+; Din[*] ; C14M ; 10.595 ; 10.595 ; Rise ; C14M ;
+; Din[0] ; C14M ; 8.624 ; 8.624 ; Rise ; C14M ;
+; Din[1] ; C14M ; 7.948 ; 7.948 ; Rise ; C14M ;
+; Din[2] ; C14M ; 9.037 ; 9.037 ; Rise ; C14M ;
+; Din[3] ; C14M ; 8.716 ; 8.716 ; Rise ; C14M ;
+; Din[4] ; C14M ; 7.690 ; 7.690 ; Rise ; C14M ;
+; Din[5] ; C14M ; 10.595 ; 10.595 ; Rise ; C14M ;
+; Din[6] ; C14M ; 7.921 ; 7.921 ; Rise ; C14M ;
+; Din[7] ; C14M ; 9.921 ; 9.921 ; Rise ; C14M ;
+; PHI1 ; C14M ; 7.231 ; 7.231 ; Rise ; C14M ;
+; nC07X ; C14M ; 4.257 ; 4.257 ; Rise ; C14M ;
+; nEN80 ; C14M ; 4.077 ; 4.077 ; Rise ; C14M ;
+; nWE ; C14M ; 4.118 ; 4.118 ; Rise ; C14M ;
+; nWE80 ; C14M ; 4.408 ; 4.408 ; Rise ; C14M ;
+; RD[*] ; C14M ; 2.425 ; 2.425 ; Fall ; C14M ;
+; RD[0] ; C14M ; 2.350 ; 2.350 ; Fall ; C14M ;
+; RD[1] ; C14M ; 1.942 ; 1.942 ; Fall ; C14M ;
+; RD[2] ; C14M ; 1.980 ; 1.980 ; Fall ; C14M ;
+; RD[3] ; C14M ; 2.125 ; 2.125 ; Fall ; C14M ;
+; RD[4] ; C14M ; 1.799 ; 1.799 ; Fall ; C14M ;
+; RD[5] ; C14M ; 2.386 ; 2.386 ; Fall ; C14M ;
+; RD[6] ; C14M ; 2.016 ; 2.016 ; Fall ; C14M ;
+; RD[7] ; C14M ; 2.425 ; 2.425 ; Fall ; C14M ;
+-----------+------------+--------+--------+------------+-----------------+
-+---------------------------------------------------------------------------+
-; Hold Times ;
-+-----------+------------+---------+---------+------------+-----------------+
-; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+---------+---------+------------+-----------------+
-; Ain[*] ; C14M ; -4.235 ; -4.235 ; Rise ; C14M ;
-; Ain[0] ; C14M ; -5.991 ; -5.991 ; Rise ; C14M ;
-; Ain[1] ; C14M ; -5.973 ; -5.973 ; Rise ; C14M ;
-; Ain[2] ; C14M ; -4.789 ; -4.789 ; Rise ; C14M ;
-; Ain[3] ; C14M ; -6.961 ; -6.961 ; Rise ; C14M ;
-; Ain[4] ; C14M ; -5.066 ; -5.066 ; Rise ; C14M ;
-; Ain[5] ; C14M ; -4.866 ; -4.866 ; Rise ; C14M ;
-; Ain[6] ; C14M ; -4.828 ; -4.828 ; Rise ; C14M ;
-; Ain[7] ; C14M ; -4.235 ; -4.235 ; Rise ; C14M ;
-; Din[*] ; C14M ; -3.392 ; -3.392 ; Rise ; C14M ;
-; Din[0] ; C14M ; -4.985 ; -4.985 ; Rise ; C14M ;
-; Din[1] ; C14M ; -5.364 ; -5.364 ; Rise ; C14M ;
-; Din[2] ; C14M ; -5.191 ; -5.191 ; Rise ; C14M ;
-; Din[3] ; C14M ; -3.524 ; -3.524 ; Rise ; C14M ;
-; Din[4] ; C14M ; -6.903 ; -6.903 ; Rise ; C14M ;
-; Din[5] ; C14M ; -8.900 ; -8.900 ; Rise ; C14M ;
-; Din[6] ; C14M ; -5.049 ; -5.049 ; Rise ; C14M ;
-; Din[7] ; C14M ; -3.392 ; -3.392 ; Rise ; C14M ;
-; PHI1 ; C14M ; -6.474 ; -6.474 ; Rise ; C14M ;
-; nC07X ; C14M ; -9.449 ; -9.449 ; Rise ; C14M ;
-; nEN80 ; C14M ; -8.428 ; -8.428 ; Rise ; C14M ;
-; nWE ; C14M ; -11.517 ; -11.517 ; Rise ; C14M ;
-; nWE80 ; C14M ; -9.781 ; -9.781 ; Rise ; C14M ;
-; RD[*] ; C14M ; -4.631 ; -4.631 ; Fall ; C14M ;
-; RD[0] ; C14M ; -6.415 ; -6.415 ; Fall ; C14M ;
-; RD[1] ; C14M ; -6.551 ; -6.551 ; Fall ; C14M ;
-; RD[2] ; C14M ; -6.279 ; -6.279 ; Fall ; C14M ;
-; RD[3] ; C14M ; -4.745 ; -4.745 ; Fall ; C14M ;
-; RD[4] ; C14M ; -4.631 ; -4.631 ; Fall ; C14M ;
-; RD[5] ; C14M ; -6.798 ; -6.798 ; Fall ; C14M ;
-; RD[6] ; C14M ; -4.782 ; -4.782 ; Fall ; C14M ;
-; RD[7] ; C14M ; -4.806 ; -4.806 ; Fall ; C14M ;
-+-----------+------------+---------+---------+------------+-----------------+
++-------------------------------------------------------------------------+
+; Hold Times ;
++-----------+------------+--------+--------+------------+-----------------+
+; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
++-----------+------------+--------+--------+------------+-----------------+
+; Ain[*] ; C14M ; -1.145 ; -1.145 ; Rise ; C14M ;
+; Ain[0] ; C14M ; -1.316 ; -1.316 ; Rise ; C14M ;
+; Ain[1] ; C14M ; -1.624 ; -1.624 ; Rise ; C14M ;
+; Ain[2] ; C14M ; -1.384 ; -1.384 ; Rise ; C14M ;
+; Ain[3] ; C14M ; -1.420 ; -1.420 ; Rise ; C14M ;
+; Ain[4] ; C14M ; -1.391 ; -1.391 ; Rise ; C14M ;
+; Ain[5] ; C14M ; -1.264 ; -1.264 ; Rise ; C14M ;
+; Ain[6] ; C14M ; -1.433 ; -1.433 ; Rise ; C14M ;
+; Ain[7] ; C14M ; -1.145 ; -1.145 ; Rise ; C14M ;
+; Din[*] ; C14M ; -1.273 ; -1.273 ; Rise ; C14M ;
+; Din[0] ; C14M ; -1.488 ; -1.488 ; Rise ; C14M ;
+; Din[1] ; C14M ; -1.457 ; -1.457 ; Rise ; C14M ;
+; Din[2] ; C14M ; -1.485 ; -1.485 ; Rise ; C14M ;
+; Din[3] ; C14M ; -1.766 ; -1.766 ; Rise ; C14M ;
+; Din[4] ; C14M ; -1.510 ; -1.510 ; Rise ; C14M ;
+; Din[5] ; C14M ; -1.440 ; -1.440 ; Rise ; C14M ;
+; Din[6] ; C14M ; -1.409 ; -1.409 ; Rise ; C14M ;
+; Din[7] ; C14M ; -1.273 ; -1.273 ; Rise ; C14M ;
+; PHI1 ; C14M ; -2.662 ; -2.662 ; Rise ; C14M ;
+; nC07X ; C14M ; -3.703 ; -3.703 ; Rise ; C14M ;
+; nEN80 ; C14M ; -2.798 ; -2.798 ; Rise ; C14M ;
+; nWE ; C14M ; -3.564 ; -3.564 ; Rise ; C14M ;
+; nWE80 ; C14M ; -3.854 ; -3.854 ; Rise ; C14M ;
+; RD[*] ; C14M ; -1.196 ; -1.196 ; Fall ; C14M ;
+; RD[0] ; C14M ; -1.196 ; -1.196 ; Fall ; C14M ;
+; RD[1] ; C14M ; -1.300 ; -1.300 ; Fall ; C14M ;
+; RD[2] ; C14M ; -1.336 ; -1.336 ; Fall ; C14M ;
+; RD[3] ; C14M ; -1.331 ; -1.331 ; Fall ; C14M ;
+; RD[4] ; C14M ; -1.221 ; -1.221 ; Fall ; C14M ;
+; RD[5] ; C14M ; -1.323 ; -1.323 ; Fall ; C14M ;
+; RD[6] ; C14M ; -1.382 ; -1.382 ; Fall ; C14M ;
+; RD[7] ; C14M ; -1.242 ; -1.242 ; Fall ; C14M ;
++-----------+------------+--------+--------+------------+-----------------+
+-------------------------------------------------------------------------+
@@ -554,48 +554,48 @@ No paths to report.
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
-; BA[*] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; BA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; BA[1] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; CKE ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
-; DQMH ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ;
-; DQML ; C14M ; 22.954 ; 22.954 ; Rise ; C14M ;
-; RA[*] ; C14M ; 21.367 ; 21.367 ; Rise ; C14M ;
-; RA[0] ; C14M ; 21.367 ; 21.367 ; Rise ; C14M ;
-; RA[1] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
-; RA[2] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ;
-; RA[3] ; C14M ; 21.293 ; 21.293 ; Rise ; C14M ;
-; RA[4] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ;
-; RA[5] ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ;
-; RA[6] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
-; RA[7] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; RA[8] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ;
-; RA[9] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ;
-; RA[10] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ;
-; RA[11] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; nCAS ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; nCS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
-; nDOE ; C14M ; 28.930 ; 28.930 ; Rise ; C14M ;
-; nRAS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
-; nRWE ; C14M ; 21.334 ; 21.334 ; Rise ; C14M ;
-; Dout[*] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ;
-; Dout[0] ; C14M ; 17.365 ; 17.365 ; Fall ; C14M ;
-; Dout[1] ; C14M ; 17.383 ; 17.383 ; Fall ; C14M ;
-; Dout[2] ; C14M ; 19.308 ; 19.308 ; Fall ; C14M ;
-; Dout[3] ; C14M ; 17.362 ; 17.362 ; Fall ; C14M ;
-; Dout[4] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ;
-; Dout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
-; Dout[6] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ;
-; Dout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
-; Vout[*] ; C14M ; 19.325 ; 19.325 ; Fall ; C14M ;
-; Vout[0] ; C14M ; 17.341 ; 17.341 ; Fall ; C14M ;
-; Vout[1] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ;
-; Vout[2] ; C14M ; 19.325 ; 19.325 ; Fall ; C14M ;
-; Vout[3] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ;
-; Vout[4] ; C14M ; 17.341 ; 17.341 ; Fall ; C14M ;
-; Vout[5] ; C14M ; 19.307 ; 19.307 ; Fall ; C14M ;
-; Vout[6] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
-; Vout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
+; BA[*] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; BA[0] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; BA[1] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; CKE ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; DQMH ; C14M ; 15.891 ; 15.891 ; Rise ; C14M ;
+; DQML ; C14M ; 15.886 ; 15.886 ; Rise ; C14M ;
+; RA[*] ; C14M ; 16.974 ; 16.974 ; Rise ; C14M ;
+; RA[0] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; RA[1] ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; RA[2] ; C14M ; 15.852 ; 15.852 ; Rise ; C14M ;
+; RA[3] ; C14M ; 16.974 ; 16.974 ; Rise ; C14M ;
+; RA[4] ; C14M ; 15.898 ; 15.898 ; Rise ; C14M ;
+; RA[5] ; C14M ; 15.891 ; 15.891 ; Rise ; C14M ;
+; RA[6] ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; RA[7] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; RA[8] ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; RA[9] ; C14M ; 16.516 ; 16.516 ; Rise ; C14M ;
+; RA[10] ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; RA[11] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; nCAS ; C14M ; 16.516 ; 16.516 ; Rise ; C14M ;
+; nCS ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; nDOE ; C14M ; 18.408 ; 18.408 ; Rise ; C14M ;
+; nRAS ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; nRWE ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; Dout[*] ; C14M ; 16.490 ; 16.490 ; Fall ; C14M ;
+; Dout[0] ; C14M ; 15.865 ; 15.865 ; Fall ; C14M ;
+; Dout[1] ; C14M ; 15.886 ; 15.886 ; Fall ; C14M ;
+; Dout[2] ; C14M ; 16.485 ; 16.485 ; Fall ; C14M ;
+; Dout[3] ; C14M ; 15.879 ; 15.879 ; Fall ; C14M ;
+; Dout[4] ; C14M ; 16.490 ; 16.490 ; Fall ; C14M ;
+; Dout[5] ; C14M ; 15.851 ; 15.851 ; Fall ; C14M ;
+; Dout[6] ; C14M ; 15.858 ; 15.858 ; Fall ; C14M ;
+; Dout[7] ; C14M ; 15.852 ; 15.852 ; Fall ; C14M ;
+; Vout[*] ; C14M ; 15.864 ; 15.864 ; Fall ; C14M ;
+; Vout[0] ; C14M ; 15.852 ; 15.852 ; Fall ; C14M ;
+; Vout[1] ; C14M ; 15.851 ; 15.851 ; Fall ; C14M ;
+; Vout[2] ; C14M ; 15.858 ; 15.858 ; Fall ; C14M ;
+; Vout[3] ; C14M ; 15.858 ; 15.858 ; Fall ; C14M ;
+; Vout[4] ; C14M ; 15.864 ; 15.864 ; Fall ; C14M ;
+; Vout[5] ; C14M ; 15.852 ; 15.852 ; Fall ; C14M ;
+; Vout[6] ; C14M ; 15.851 ; 15.851 ; Fall ; C14M ;
+; Vout[7] ; C14M ; 15.851 ; 15.851 ; Fall ; C14M ;
+-----------+------------+--------+--------+------------+-----------------+
@@ -604,48 +604,48 @@ No paths to report.
+-----------+------------+--------+--------+------------+-----------------+
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
+-----------+------------+--------+--------+------------+-----------------+
-; BA[*] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; BA[0] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; BA[1] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; CKE ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
-; DQMH ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ;
-; DQML ; C14M ; 22.954 ; 22.954 ; Rise ; C14M ;
-; RA[*] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ;
-; RA[0] ; C14M ; 21.367 ; 21.367 ; Rise ; C14M ;
-; RA[1] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
-; RA[2] ; C14M ; 17.332 ; 17.332 ; Rise ; C14M ;
-; RA[3] ; C14M ; 21.293 ; 21.293 ; Rise ; C14M ;
-; RA[4] ; C14M ; 17.368 ; 17.368 ; Rise ; C14M ;
-; RA[5] ; C14M ; 17.375 ; 17.375 ; Rise ; C14M ;
-; RA[6] ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
-; RA[7] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; RA[8] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ;
-; RA[9] ; C14M ; 19.354 ; 19.354 ; Rise ; C14M ;
-; RA[10] ; C14M ; 17.376 ; 17.376 ; Rise ; C14M ;
-; RA[11] ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; nCAS ; C14M ; 17.383 ; 17.383 ; Rise ; C14M ;
-; nCS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
-; nDOE ; C14M ; 28.930 ; 28.930 ; Rise ; C14M ;
-; nRAS ; C14M ; 17.378 ; 17.378 ; Rise ; C14M ;
-; nRWE ; C14M ; 21.334 ; 21.334 ; Rise ; C14M ;
-; Dout[*] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
-; Dout[0] ; C14M ; 17.365 ; 17.365 ; Fall ; C14M ;
-; Dout[1] ; C14M ; 17.383 ; 17.383 ; Fall ; C14M ;
-; Dout[2] ; C14M ; 19.308 ; 19.308 ; Fall ; C14M ;
-; Dout[3] ; C14M ; 17.362 ; 17.362 ; Fall ; C14M ;
-; Dout[4] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ;
-; Dout[5] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
-; Dout[6] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ;
-; Dout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
-; Vout[*] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
-; Vout[0] ; C14M ; 17.341 ; 17.341 ; Fall ; C14M ;
-; Vout[1] ; C14M ; 19.315 ; 19.315 ; Fall ; C14M ;
-; Vout[2] ; C14M ; 19.325 ; 19.325 ; Fall ; C14M ;
-; Vout[3] ; C14M ; 17.337 ; 17.337 ; Fall ; C14M ;
-; Vout[4] ; C14M ; 17.341 ; 17.341 ; Fall ; C14M ;
-; Vout[5] ; C14M ; 19.307 ; 19.307 ; Fall ; C14M ;
-; Vout[6] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
-; Vout[7] ; C14M ; 17.332 ; 17.332 ; Fall ; C14M ;
+; BA[*] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; BA[0] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; BA[1] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; CKE ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; DQMH ; C14M ; 15.891 ; 15.891 ; Rise ; C14M ;
+; DQML ; C14M ; 15.886 ; 15.886 ; Rise ; C14M ;
+; RA[*] ; C14M ; 15.852 ; 15.852 ; Rise ; C14M ;
+; RA[0] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; RA[1] ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; RA[2] ; C14M ; 15.852 ; 15.852 ; Rise ; C14M ;
+; RA[3] ; C14M ; 16.974 ; 16.974 ; Rise ; C14M ;
+; RA[4] ; C14M ; 15.898 ; 15.898 ; Rise ; C14M ;
+; RA[5] ; C14M ; 15.891 ; 15.891 ; Rise ; C14M ;
+; RA[6] ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; RA[7] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; RA[8] ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; RA[9] ; C14M ; 16.516 ; 16.516 ; Rise ; C14M ;
+; RA[10] ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; RA[11] ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; nCAS ; C14M ; 16.516 ; 16.516 ; Rise ; C14M ;
+; nCS ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; nDOE ; C14M ; 18.408 ; 18.408 ; Rise ; C14M ;
+; nRAS ; C14M ; 15.892 ; 15.892 ; Rise ; C14M ;
+; nRWE ; C14M ; 15.896 ; 15.896 ; Rise ; C14M ;
+; Dout[*] ; C14M ; 15.851 ; 15.851 ; Fall ; C14M ;
+; Dout[0] ; C14M ; 15.865 ; 15.865 ; Fall ; C14M ;
+; Dout[1] ; C14M ; 15.886 ; 15.886 ; Fall ; C14M ;
+; Dout[2] ; C14M ; 16.485 ; 16.485 ; Fall ; C14M ;
+; Dout[3] ; C14M ; 15.879 ; 15.879 ; Fall ; C14M ;
+; Dout[4] ; C14M ; 16.490 ; 16.490 ; Fall ; C14M ;
+; Dout[5] ; C14M ; 15.851 ; 15.851 ; Fall ; C14M ;
+; Dout[6] ; C14M ; 15.858 ; 15.858 ; Fall ; C14M ;
+; Dout[7] ; C14M ; 15.852 ; 15.852 ; Fall ; C14M ;
+; Vout[*] ; C14M ; 15.851 ; 15.851 ; Fall ; C14M ;
+; Vout[0] ; C14M ; 15.852 ; 15.852 ; Fall ; C14M ;
+; Vout[1] ; C14M ; 15.851 ; 15.851 ; Fall ; C14M ;
+; Vout[2] ; C14M ; 15.858 ; 15.858 ; Fall ; C14M ;
+; Vout[3] ; C14M ; 15.858 ; 15.858 ; Fall ; C14M ;
+; Vout[4] ; C14M ; 15.864 ; 15.864 ; Fall ; C14M ;
+; Vout[5] ; C14M ; 15.852 ; 15.852 ; Fall ; C14M ;
+; Vout[6] ; C14M ; 15.851 ; 15.851 ; Fall ; C14M ;
+; Vout[7] ; C14M ; 15.851 ; 15.851 ; Fall ; C14M ;
+-----------+------------+--------+--------+------------+-----------------+
@@ -654,33 +654,33 @@ No paths to report.
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+--------+----+----+--------+
-; Din[0] ; RD[0] ; 19.492 ; ; ; 19.492 ;
-; Din[1] ; RD[1] ; 19.340 ; ; ; 19.340 ;
-; Din[2] ; RD[2] ; 21.309 ; ; ; 21.309 ;
-; Din[3] ; RD[3] ; 19.308 ; ; ; 19.308 ;
-; Din[4] ; RD[4] ; 21.375 ; ; ; 21.375 ;
-; Din[5] ; RD[5] ; 21.226 ; ; ; 21.226 ;
-; Din[6] ; RD[6] ; 19.287 ; ; ; 19.287 ;
-; Din[7] ; RD[7] ; 19.338 ; ; ; 19.338 ;
-; PHI1 ; nVOE ; 22.914 ; ; ; 22.914 ;
-; nEN80 ; RD[0] ; 20.792 ; ; ; 20.792 ;
-; nEN80 ; RD[1] ; 21.290 ; ; ; 21.290 ;
-; nEN80 ; RD[2] ; 20.792 ; ; ; 20.792 ;
-; nEN80 ; RD[3] ; 21.290 ; ; ; 21.290 ;
-; nEN80 ; RD[4] ; 21.290 ; ; ; 21.290 ;
-; nEN80 ; RD[5] ; 20.792 ; ; ; 20.792 ;
-; nEN80 ; RD[6] ; 20.792 ; ; ; 20.792 ;
-; nEN80 ; RD[7] ; 20.792 ; ; ; 20.792 ;
-; nEN80 ; nDOE ; 25.564 ; ; ; 25.564 ;
-; nWE ; nDOE ; 26.039 ; ; ; 26.039 ;
-; nWE80 ; RD[0] ; 19.810 ; ; ; 19.810 ;
-; nWE80 ; RD[1] ; 20.308 ; ; ; 20.308 ;
-; nWE80 ; RD[2] ; 19.810 ; ; ; 19.810 ;
-; nWE80 ; RD[3] ; 20.308 ; ; ; 20.308 ;
-; nWE80 ; RD[4] ; 20.308 ; ; ; 20.308 ;
-; nWE80 ; RD[5] ; 19.810 ; ; ; 19.810 ;
-; nWE80 ; RD[6] ; 19.810 ; ; ; 19.810 ;
-; nWE80 ; RD[7] ; 19.810 ; ; ; 19.810 ;
+; Din[0] ; RD[0] ; 15.297 ; ; ; 15.297 ;
+; Din[1] ; RD[1] ; 15.328 ; ; ; 15.328 ;
+; Din[2] ; RD[2] ; 15.982 ; ; ; 15.982 ;
+; Din[3] ; RD[3] ; 15.305 ; ; ; 15.305 ;
+; Din[4] ; RD[4] ; 15.978 ; ; ; 15.978 ;
+; Din[5] ; RD[5] ; 15.917 ; ; ; 15.917 ;
+; Din[6] ; RD[6] ; 15.376 ; ; ; 15.376 ;
+; Din[7] ; RD[7] ; 15.271 ; ; ; 15.271 ;
+; PHI1 ; nVOE ; 17.574 ; ; ; 17.574 ;
+; nEN80 ; RD[0] ; 15.606 ; ; ; 15.606 ;
+; nEN80 ; RD[1] ; 15.542 ; ; ; 15.542 ;
+; nEN80 ; RD[2] ; 15.606 ; ; ; 15.606 ;
+; nEN80 ; RD[3] ; 15.542 ; ; ; 15.542 ;
+; nEN80 ; RD[4] ; 15.542 ; ; ; 15.542 ;
+; nEN80 ; RD[5] ; 15.606 ; ; ; 15.606 ;
+; nEN80 ; RD[6] ; 15.606 ; ; ; 15.606 ;
+; nEN80 ; RD[7] ; 15.606 ; ; ; 15.606 ;
+; nEN80 ; nDOE ; 17.395 ; ; ; 17.395 ;
+; nWE ; nDOE ; 17.101 ; ; ; 17.101 ;
+; nWE80 ; RD[0] ; 15.969 ; ; ; 15.969 ;
+; nWE80 ; RD[1] ; 15.905 ; ; ; 15.905 ;
+; nWE80 ; RD[2] ; 15.969 ; ; ; 15.969 ;
+; nWE80 ; RD[3] ; 15.905 ; ; ; 15.905 ;
+; nWE80 ; RD[4] ; 15.905 ; ; ; 15.905 ;
+; nWE80 ; RD[5] ; 15.969 ; ; ; 15.969 ;
+; nWE80 ; RD[6] ; 15.969 ; ; ; 15.969 ;
+; nWE80 ; RD[7] ; 15.969 ; ; ; 15.969 ;
+------------+-------------+--------+----+----+--------+
@@ -689,33 +689,33 @@ No paths to report.
+------------+-------------+--------+----+----+--------+
; Input Port ; Output Port ; RR ; RF ; FR ; FF ;
+------------+-------------+--------+----+----+--------+
-; Din[0] ; RD[0] ; 19.492 ; ; ; 19.492 ;
-; Din[1] ; RD[1] ; 19.340 ; ; ; 19.340 ;
-; Din[2] ; RD[2] ; 21.309 ; ; ; 21.309 ;
-; Din[3] ; RD[3] ; 19.308 ; ; ; 19.308 ;
-; Din[4] ; RD[4] ; 21.375 ; ; ; 21.375 ;
-; Din[5] ; RD[5] ; 21.226 ; ; ; 21.226 ;
-; Din[6] ; RD[6] ; 19.287 ; ; ; 19.287 ;
-; Din[7] ; RD[7] ; 19.338 ; ; ; 19.338 ;
-; PHI1 ; nVOE ; 22.914 ; ; ; 22.914 ;
-; nEN80 ; RD[0] ; 20.792 ; ; ; 20.792 ;
-; nEN80 ; RD[1] ; 21.290 ; ; ; 21.290 ;
-; nEN80 ; RD[2] ; 20.792 ; ; ; 20.792 ;
-; nEN80 ; RD[3] ; 21.290 ; ; ; 21.290 ;
-; nEN80 ; RD[4] ; 21.290 ; ; ; 21.290 ;
-; nEN80 ; RD[5] ; 20.792 ; ; ; 20.792 ;
-; nEN80 ; RD[6] ; 20.792 ; ; ; 20.792 ;
-; nEN80 ; RD[7] ; 20.792 ; ; ; 20.792 ;
-; nEN80 ; nDOE ; 25.564 ; ; ; 25.564 ;
-; nWE ; nDOE ; 26.039 ; ; ; 26.039 ;
-; nWE80 ; RD[0] ; 19.810 ; ; ; 19.810 ;
-; nWE80 ; RD[1] ; 20.308 ; ; ; 20.308 ;
-; nWE80 ; RD[2] ; 19.810 ; ; ; 19.810 ;
-; nWE80 ; RD[3] ; 20.308 ; ; ; 20.308 ;
-; nWE80 ; RD[4] ; 20.308 ; ; ; 20.308 ;
-; nWE80 ; RD[5] ; 19.810 ; ; ; 19.810 ;
-; nWE80 ; RD[6] ; 19.810 ; ; ; 19.810 ;
-; nWE80 ; RD[7] ; 19.810 ; ; ; 19.810 ;
+; Din[0] ; RD[0] ; 15.297 ; ; ; 15.297 ;
+; Din[1] ; RD[1] ; 15.328 ; ; ; 15.328 ;
+; Din[2] ; RD[2] ; 15.982 ; ; ; 15.982 ;
+; Din[3] ; RD[3] ; 15.305 ; ; ; 15.305 ;
+; Din[4] ; RD[4] ; 15.978 ; ; ; 15.978 ;
+; Din[5] ; RD[5] ; 15.917 ; ; ; 15.917 ;
+; Din[6] ; RD[6] ; 15.376 ; ; ; 15.376 ;
+; Din[7] ; RD[7] ; 15.271 ; ; ; 15.271 ;
+; PHI1 ; nVOE ; 17.574 ; ; ; 17.574 ;
+; nEN80 ; RD[0] ; 15.606 ; ; ; 15.606 ;
+; nEN80 ; RD[1] ; 15.542 ; ; ; 15.542 ;
+; nEN80 ; RD[2] ; 15.606 ; ; ; 15.606 ;
+; nEN80 ; RD[3] ; 15.542 ; ; ; 15.542 ;
+; nEN80 ; RD[4] ; 15.542 ; ; ; 15.542 ;
+; nEN80 ; RD[5] ; 15.606 ; ; ; 15.606 ;
+; nEN80 ; RD[6] ; 15.606 ; ; ; 15.606 ;
+; nEN80 ; RD[7] ; 15.606 ; ; ; 15.606 ;
+; nEN80 ; nDOE ; 17.395 ; ; ; 17.395 ;
+; nWE ; nDOE ; 17.101 ; ; ; 17.101 ;
+; nWE80 ; RD[0] ; 15.969 ; ; ; 15.969 ;
+; nWE80 ; RD[1] ; 15.905 ; ; ; 15.905 ;
+; nWE80 ; RD[2] ; 15.969 ; ; ; 15.969 ;
+; nWE80 ; RD[3] ; 15.905 ; ; ; 15.905 ;
+; nWE80 ; RD[4] ; 15.905 ; ; ; 15.905 ;
+; nWE80 ; RD[5] ; 15.969 ; ; ; 15.969 ;
+; nWE80 ; RD[6] ; 15.969 ; ; ; 15.969 ;
+; nWE80 ; RD[7] ; 15.969 ; ; ; 15.969 ;
+------------+-------------+--------+----+----+--------+
@@ -724,7 +724,7 @@ No paths to report.
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
-; C14M ; C14M ; 1358 ; 0 ; 64 ; 0 ;
+; C14M ; C14M ; 1352 ; 0 ; 64 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -734,7 +734,7 @@ Entries labeled "false path" only account for clock-to-clock false paths and not
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
-; C14M ; C14M ; 1358 ; 0 ; 64 ; 0 ;
+; C14M ; C14M ; 1352 ; 0 ; 64 ; 0 ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
@@ -771,7 +771,7 @@ No dedicated SERDES Receiver circuitry present in device or used in design
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
- Info: Processing started: Wed Sep 16 20:14:42 2020
+ Info: Processing started: Thu Jan 28 14:37:21 2021
Info: Command: quartus_sta RAM2E -c RAM2E
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
@@ -783,27 +783,27 @@ Info (332104): Reading SDC File: 'constraints.sdc'
Warning (332060): Node: DRCLK was determined to be a clock but was found without an associated clock assignment.
Warning (332060): Node: ARCLK was determined to be a clock but was found without an associated clock assignment.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info (332146): Worst-case setup slack is 21.694
+Info (332146): Worst-case setup slack is 29.169
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
- Info (332119): 21.694 0.000 C14M
-Info (332146): Worst-case hold slack is 3.144
+ Info (332119): 29.169 0.000 C14M
+Info (332146): Worst-case hold slack is 1.646
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
- Info (332119): 3.144 0.000 C14M
+ Info (332119): 1.646 0.000 C14M
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is 34.581
+Info (332146): Worst-case minimum pulse width slack is 34.654
Info (332119): Slack End Point TNS Clock
Info (332119): ========= ============= =====================
- Info (332119): 34.581 0.000 C14M
+ Info (332119): 34.654 0.000 C14M
Info (332001): The selected device family is not supported by the report_metastability command.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
- Info: Peak virtual memory: 4522 megabytes
- Info: Processing ended: Wed Sep 16 20:14:43 2020
- Info: Elapsed time: 00:00:01
- Info: Total CPU time (on all processors): 00:00:01
+ Info: Peak virtual memory: 4513 megabytes
+ Info: Processing ended: Thu Jan 28 14:37:23 2021
+ Info: Elapsed time: 00:00:02
+ Info: Total CPU time (on all processors): 00:00:02
diff --git a/cpld/output_files/RAM2E.sta.summary b/cpld/output_files/RAM2E.sta.summary
index 8e64d7f..d38a6e6 100755
--- a/cpld/output_files/RAM2E.sta.summary
+++ b/cpld/output_files/RAM2E.sta.summary
@@ -3,15 +3,15 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------
Type : Setup 'C14M'
-Slack : 21.694
+Slack : 29.169
TNS : 0.000
Type : Hold 'C14M'
-Slack : 3.144
+Slack : 1.646
TNS : 0.000
Type : Minimum Pulse Width 'C14M'
-Slack : 34.581
+Slack : 34.654
TNS : 0.000
------------------------------------------------------------