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GW4203C.1.0 RC3

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Zane Kaminski
2024-07-20 07:09:18 -04:00
parent 0aa22f24f8
commit d6eb679db5
127 changed files with 43947 additions and 42911 deletions
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CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html
+49 -42
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@@ -12,11 +12,12 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
@@ -25,22 +26,22 @@ Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
margin-bottom: 5px;
font-size: 0.80em;
}
}
p {
font-size:78%;
}
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
@@ -66,39 +67,39 @@ Ignore Preference Error(s): True
a:visited {
color:#013C9A;
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
color:#5BAFD4;
}
}
.pass
{
background-color: #00ff00;
}
.fail
{
{
background-color: #ff0000;
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.comment
{
font-size: 90%;
font-size: 90%;
font-style: italic;
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-->
-->
</STYLE>
</STYLE>
</HEAD>
<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.11.3.469.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995 AT&amp;T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved.
Fri Jul 12 16:08:09 2024
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
C:/lscc/diamond/3.11_x64/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset
//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
@@ -111,8 +112,8 @@ Global Clock Resources:
---------- -------- ----- ------ ----------- ----------- ---- ------
5_1 * 0 57.398 0 0.379 0 35 Completed
* : Design saved.
Total (real) run time for 1-seed: 16 secs
Total (real) run time for 1-seed: 38 secs
par done!
@@ -136,20 +137,20 @@ I/O Bank Usage Summary:
Device: LCMXO2-640HC
Package: TQFP100
Performance: 4
Loading device for application par from file &apos;xo2c640.nph&apos; in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Loading device for application par from file &apos;xo2c640.nph&apos; in environment: C:/lscc/diamond/3.11_x64/ispfpga.
Package Status: Final Version 1.39.
Performance Hardware Data Status: Final Version 34.4.
License checked out.
Ignore Preference Error(s): True
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO (prelim) 70+4(JTAG)/80 93% used
70+4(JTAG)/79 94% bonded
70+4(JTAG)/79 94% bonded
IOLOGIC 22/80 27% used
SLICE 145/320 45% used
EFB 1/1 100% used
@@ -164,35 +165,41 @@ Note: NBR uses a different method to calculate timing slacks. The
The following 1 signal is selected to use the primary clock routing resources:
C14M_c (driver: C14M, clk load #: 84)
WARNING - par: Signal &quot;C14M_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;C14M&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
WARNING - par: Signal &quot;C14M_c&quot; is selected to use Primary clock resources. However, its driver comp &quot;C14M&quot; is located at &quot;62&quot;, which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
The following 1 signal is selected to use the secondary clock routing resources:
The following 1 signal is selected to use the secondary clock routing resources:
RWBank14 (driver: ram2e_ufm/SLICE_89, clk load #: 0, sr load #: 0, ce load #: 10)
No signal is selected as Global Set/Reset.
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
.............
Finished Placer Phase 0. REAL time: 3 secs
Starting Placer Phase 1.
Starting Placer Phase 1.
....................
Placer score = 70995.
Finished Placer Phase 1. REAL time: 9 secs
Placer score = 68344.
Finished Placer Phase 1. REAL time: 13 secs
Starting Placer Phase 2.
.
Starting Placer Phase 2.
.
Placer score = 68130
Finished Placer Phase 2. REAL time: 14 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
General PIO: 1 out of 80 (1%)
DCM : 0 out of 2 (0%)
DCC : 0 out of 8 (0%)
Global Clocks:
PRIMARY &quot;C14M_c&quot; from comp &quot;C14M&quot; on PIO site &quot;62 (PR5D)&quot;, clk load = 84
General PIO: 1 out of 80 (1%)
SECONDARY &quot;RWBank14&quot; from F0 on comp &quot;ram2e_ufm/SLICE_89&quot; on site &quot;R6C8B&quot;, clk load = 0, ce load = 10, sr load = 0
DCC : 0 out of 8 (0%)
PRIMARY : 1 out of 8 (12%)
SECONDARY: 1 out of 8 (12%)
@@ -200,7 +207,7 @@ NBR Summary
I/O Usage Summary (final):
70 + 4(JTAG) out of 80 (92.5%) PIO sites used.
70 + 4(JTAG) out of 79 (93.7%) bonded PIO sites used.
Number of PIO comps: 70; differential: 0.
Number of Vref pins used: 0.
@@ -211,9 +218,9 @@ WARNING - par: The following clock signals will be routed by using generic routi
| 0 | 11 / 19 ( 57%) | 3.3V | - |
| 1 | 20 / 20 (100%) | 3.3V | - |
| 2 | 19 / 20 ( 95%) | 3.3V | - |
+----------+----------------+------------+-----------+
| 3 | 20 / 20 (100%) | 3.3V | - |
+----------+----------------+------------+-----------+
+----------+----------------+------------+-----------+
Total placer CPU time: 8 secs
Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
@@ -227,14 +234,14 @@ All signals are completely routed.
Completed router resource preassignment. Real time: 26 secs
Start NBR router at 16:08:36 07/12/24
*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
in the earlier iterations. In each iteration, it tries to
solve the conflicts while keeping the critical connections
routed as short as possible. The routing process is said to
be completed when no conflicts exist and all connections
are routed.
Note: NBR uses a different method to calculate timing slacks. The
worst slack and total negative slack may not be the same as