From dec33238f1059e2158c26b92efe950616bb11eef Mon Sep 17 00:00:00 2001 From: Zane Kaminski Date: Thu, 21 Sep 2023 05:45:21 -0400 Subject: [PATCH] RC --- .gitignore | 47 +- CPLD/LCMXO2-1200HC/.setting.ini | 4 + CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf | 20 + CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC1.sty | 205 + .../RAM2E_LCMXO2_1200HC_tcl.html | 71 + CPLD/LCMXO2-1200HC/REFB.edn | 550 ++ CPLD/LCMXO2-1200HC/REFB.ipx | 8 + CPLD/LCMXO2-1200HC/REFB.lpc | 141 + CPLD/LCMXO2-1200HC/REFB.naf | 31 + CPLD/LCMXO2-1200HC/REFB.sort | 1 + CPLD/LCMXO2-1200HC/REFB.srp | 26 + CPLD/LCMXO2-1200HC/REFB.sym | Bin 0 -> 466 bytes CPLD/LCMXO2-1200HC/REFB.v | 113 + CPLD/LCMXO2-1200HC/REFB_generate.log | 44 + CPLD/LCMXO2-1200HC/REFB_tmpl.v | 8 + CPLD/LCMXO2-1200HC/_math_real.vhd | 2574 +++++++ CPLD/LCMXO2-1200HC/generate_core.tcl | 100 + CPLD/LCMXO2-1200HC/generate_ngd.tcl | 74 + .../impl1/RAM2E_LCMXO2_1200HC_impl1.alt | 78 + .../impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr | 41 + 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create mode 100644 CPLD/MAXII/output_files/RAM2E.flow.rpt create mode 100644 CPLD/MAXII/output_files/RAM2E.jdi create mode 100644 CPLD/MAXII/output_files/RAM2E.map.rpt create mode 100644 CPLD/MAXII/output_files/RAM2E.map.smsg create mode 100644 CPLD/MAXII/output_files/RAM2E.map.summary create mode 100644 CPLD/MAXII/output_files/RAM2E.pin create mode 100644 CPLD/MAXII/output_files/RAM2E.pof create mode 100644 CPLD/MAXII/output_files/RAM2E.sld create mode 100644 CPLD/MAXII/output_files/RAM2E.sta.rpt create mode 100644 CPLD/MAXII/output_files/RAM2E.sta.summary create mode 100644 CPLD/MAXV/RAM2E-MAXV.qpf create mode 100644 CPLD/MAXV/RAM2E.qsf create mode 100644 CPLD/MAXV/RAM2E.qws create mode 100644 CPLD/MAXV/UFM.qip create mode 100644 CPLD/MAXV/UFM.v create mode 100644 CPLD/MAXV/output_files/RAM2E.asm.rpt create mode 100644 CPLD/MAXV/output_files/RAM2E.done create mode 100644 CPLD/MAXV/output_files/RAM2E.fit.rpt create mode 100644 CPLD/MAXV/output_files/RAM2E.fit.smsg create mode 100644 CPLD/MAXV/output_files/RAM2E.fit.summary create mode 100644 CPLD/MAXV/output_files/RAM2E.flow.rpt create mode 100644 CPLD/MAXV/output_files/RAM2E.jdi create mode 100644 CPLD/MAXV/output_files/RAM2E.map.rpt create mode 100644 CPLD/MAXV/output_files/RAM2E.map.smsg create mode 100644 CPLD/MAXV/output_files/RAM2E.map.summary create mode 100644 CPLD/MAXV/output_files/RAM2E.pin create mode 100644 CPLD/MAXV/output_files/RAM2E.pof create mode 100644 CPLD/MAXV/output_files/RAM2E.sld create mode 100644 CPLD/MAXV/output_files/RAM2E.sta.rpt create mode 100644 CPLD/MAXV/output_files/RAM2E.sta.summary create mode 100644 CPLD/RAM2E-LCMXO2.lpf create mode 100644 CPLD/RAM2E-LCMXO2.mem create mode 100644 CPLD/RAM2E-LCMXO2.v create mode 100644 CPLD/RAM2E-MAX.sdc create mode 100644 CPLD/RAM2E-MAX.v create mode 100644 CPLD/RAM2E-old.v create mode 100644 CPLD/RAM2E.mif create mode 100644 CPLD/RAM2E.qsf create mode 100644 CPLD/RAM2E.sdc diff --git a/.gitignore b/.gitignore index 38a5900..c369a15 100644 --- a/.gitignore +++ b/.gitignore @@ -14,18 +14,41 @@ _autosave-* *-save.pro *-save.kicad_pcb fp-info-cache +Hardware/*/*-backups -# Netlist files (exported from Eeschema) -*.net - -# Autorouter files (exported from Pcbnew) -*.dsn -*.ses - -# Exported BOM files -*.xml +# Mac *.DS_Store -Documentation/~$4203BManual.docx -*.cdf -Documentation/~$4203BDevNote.docx + + +# Altera MAX II/V +CPLD/MAX*/db +CPLD/MAX*/incremental_db +CPLD/MAX*/greybox_tmp + + +# Lattice Diamond +CPLD/LCMXO*/*.dir +CPLD/LCMXO*/.build_status +CPLD/LCMXO*/.run_manager.ini +CPLD/LCMXO*/.recovery +CPLD/LCMXO*/.spread_sheet.ini +CPLD/LCMXO*/.spreadsheet_view.ini +CPLD/LCMXO*/impl1/* +!CPLD/LCMXO*/impl1/*.jed +!CPLD/LCMXO*/impl1/*.bit +!CPLD/LCMXO*/impl1/*.html +!CPLD/LCMXO*/impl1/*.rpt +!CPLD/LCMXO*/impl1/*.sdf +!CPLD/LCMXO*/impl1/*.vo +!CPLD/LCMXO*/impl1/*.alt +!CPLD/LCMXO*/impl1/*.areasrr +!CPLD/LCMXO*/impl1/*.bgn +!CPLD/LCMXO*/impl1/*.edi +!CPLD/LCMXO*/impl1/*.ior +!CPLD/LCMXO*/impl1/*.mrp +!CPLD/LCMXO*/impl1/*.pad +!CPLD/LCMXO*/impl1/*.prf +!CPLD/LCMXO*/impl1/*.srr +!CPLD/LCMXO*/impl1/*.twr +!CPLD/LCMXO*/impl1/*.tw1 diff --git a/CPLD/LCMXO2-1200HC/.setting.ini b/CPLD/LCMXO2-1200HC/.setting.ini new file mode 100644 index 0000000..5ac5d37 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/.setting.ini @@ -0,0 +1,4 @@ +[General] +Map.auto_tasks=MapTrace, MapVerilogSimFile +PAR.auto_tasks=PARTrace, IOTiming +Export.auto_tasks=IBIS, TimingSimFileVlg, Bitgen, Jedecgen diff --git a/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf new file mode 100644 index 0000000..0468376 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC1.sty b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC1.sty new file mode 100644 index 0000000..feec63c --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html new file mode 100644 index 0000000..cf1147b --- /dev/null +++ b/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC_tcl.html @@ -0,0 +1,71 @@ + +Lattice TCL Log + + +
pn230921045934
+#Start recording tcl command: 9/21/2023 04:58:28
+#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC; Project name: RAM2E_LCMXO2_1200HC
+prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf"
+prj_run PAR -impl impl1 -task IOTiming
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 9/21/2023 04:59:34
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+ + diff --git a/CPLD/LCMXO2-1200HC/REFB.edn b/CPLD/LCMXO2-1200HC/REFB.edn new file mode 100644 index 0000000..034bc84 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/REFB.edn @@ -0,0 +1,550 @@ +(edif REFB + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2023 9 20 4 45 58) + (program "SCUBA" (version "Diamond (64-bit) 3.12.1.454")))) + (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell EFB + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port WBCLKI + (direction INPUT)) + (port WBRSTI + (direction INPUT)) + (port WBCYCI + (direction INPUT)) + (port WBSTBI + (direction INPUT)) + (port WBWEI + (direction INPUT)) + (port WBADRI7 + (direction INPUT)) + (port WBADRI6 + (direction INPUT)) + (port WBADRI5 + (direction INPUT)) + (port WBADRI4 + (direction INPUT)) + (port WBADRI3 + (direction INPUT)) + (port WBADRI2 + (direction INPUT)) + (port WBADRI1 + (direction INPUT)) + (port WBADRI0 + (direction INPUT)) + (port WBDATI7 + (direction INPUT)) + (port WBDATI6 + (direction INPUT)) + (port WBDATI5 + (direction INPUT)) + (port WBDATI4 + (direction INPUT)) + (port WBDATI3 + (direction INPUT)) + (port WBDATI2 + (direction INPUT)) + (port WBDATI1 + (direction INPUT)) + (port WBDATI0 + (direction INPUT)) + (port PLL0DATI7 + (direction INPUT)) + (port PLL0DATI6 + (direction INPUT)) + (port PLL0DATI5 + (direction INPUT)) + (port PLL0DATI4 + (direction INPUT)) + (port PLL0DATI3 + (direction INPUT)) + (port PLL0DATI2 + (direction INPUT)) + (port PLL0DATI1 + (direction INPUT)) + (port PLL0DATI0 + (direction INPUT)) + (port PLL0ACKI + (direction INPUT)) + (port PLL1DATI7 + (direction INPUT)) + (port PLL1DATI6 + (direction INPUT)) + (port PLL1DATI5 + (direction INPUT)) + (port PLL1DATI4 + (direction INPUT)) + (port PLL1DATI3 + (direction INPUT)) + (port PLL1DATI2 + (direction INPUT)) + (port PLL1DATI1 + (direction INPUT)) + (port PLL1DATI0 + (direction INPUT)) + (port PLL1ACKI + (direction INPUT)) + (port I2C1SCLI + (direction INPUT)) + (port I2C1SDAI + (direction INPUT)) + (port I2C2SCLI + (direction INPUT)) + (port I2C2SDAI + (direction INPUT)) + (port SPISCKI + (direction INPUT)) + (port SPIMISOI + (direction INPUT)) + (port SPIMOSII + (direction INPUT)) + (port SPISCSN + (direction INPUT)) + (port TCCLKI + (direction INPUT)) + (port TCRSTN + (direction INPUT)) + (port TCIC + (direction INPUT)) + (port UFMSN + (direction INPUT)) + (port WBDATO7 + (direction OUTPUT)) + (port WBDATO6 + (direction OUTPUT)) + (port WBDATO5 + (direction OUTPUT)) + (port WBDATO4 + (direction OUTPUT)) + (port WBDATO3 + (direction OUTPUT)) + (port WBDATO2 + (direction OUTPUT)) + (port WBDATO1 + (direction OUTPUT)) + (port WBDATO0 + (direction OUTPUT)) + (port WBACKO + (direction OUTPUT)) + (port PLLCLKO + (direction OUTPUT)) + (port PLLRSTO + (direction OUTPUT)) + (port PLL0STBO + (direction OUTPUT)) + (port PLL1STBO + (direction OUTPUT)) + (port PLLWEO + (direction OUTPUT)) + (port PLLADRO4 + (direction OUTPUT)) + (port PLLADRO3 + (direction OUTPUT)) + (port PLLADRO2 + (direction OUTPUT)) + (port PLLADRO1 + (direction OUTPUT)) + (port PLLADRO0 + (direction OUTPUT)) + (port PLLDATO7 + (direction OUTPUT)) + (port PLLDATO6 + (direction OUTPUT)) + (port PLLDATO5 + (direction OUTPUT)) + (port PLLDATO4 + (direction OUTPUT)) + (port PLLDATO3 + (direction OUTPUT)) + (port PLLDATO2 + (direction OUTPUT)) + (port PLLDATO1 + (direction OUTPUT)) + (port PLLDATO0 + (direction OUTPUT)) + (port I2C1SCLO + (direction OUTPUT)) + (port I2C1SCLOEN + (direction OUTPUT)) + (port I2C1SDAO + (direction OUTPUT)) + (port I2C1SDAOEN + (direction OUTPUT)) + (port I2C2SCLO + (direction OUTPUT)) + (port I2C2SCLOEN + (direction OUTPUT)) + (port I2C2SDAO + (direction OUTPUT)) + (port I2C2SDAOEN + (direction OUTPUT)) + (port I2C1IRQO + (direction OUTPUT)) + (port I2C2IRQO + (direction OUTPUT)) + (port SPISCKO + (direction OUTPUT)) + (port SPISCKEN + (direction OUTPUT)) + (port SPIMISOO + (direction OUTPUT)) + (port SPIMISOEN + (direction OUTPUT)) + (port SPIMOSIO + (direction OUTPUT)) + (port SPIMOSIEN + (direction OUTPUT)) + (port SPIMCSN7 + (direction OUTPUT)) + (port SPIMCSN6 + (direction OUTPUT)) + (port SPIMCSN5 + (direction OUTPUT)) + (port SPIMCSN4 + (direction OUTPUT)) + (port SPIMCSN3 + (direction OUTPUT)) + (port SPIMCSN2 + (direction OUTPUT)) + (port SPIMCSN1 + (direction OUTPUT)) + (port SPIMCSN0 + (direction OUTPUT)) + (port SPICSNEN + (direction OUTPUT)) + (port SPIIRQO + (direction OUTPUT)) + (port TCINT + (direction OUTPUT)) + (port TCOC + (direction OUTPUT)) + (port WBCUFMIRQ + (direction OUTPUT)) + (port CFGWAKE + (direction OUTPUT)) + (port CFGSTDBY + (direction OUTPUT))))) + (cell REFB + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port wb_clk_i + (direction INPUT)) + (port wb_rst_i + (direction INPUT)) + (port wb_cyc_i + (direction INPUT)) + (port wb_stb_i + (direction INPUT)) + (port wb_we_i + (direction INPUT)) + (port (array (rename wb_adr_i "wb_adr_i(7:0)") 8) + (direction INPUT)) + (port (array (rename wb_dat_i "wb_dat_i(7:0)") 8) + (direction INPUT)) + (port (array (rename wb_dat_o "wb_dat_o(7:0)") 8) + (direction OUTPUT)) + (port wb_ack_o + (direction OUTPUT)) + (port wbc_ufm_irq + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance EFBInst_0 + (viewRef view1 + (cellRef EFB)) + (property UFM_INIT_FILE_FORMAT + (string "HEX")) + (property UFM_INIT_FILE_NAME + (string "../RAM2E-LCMXO2.mem")) + (property UFM_INIT_ALL_ZEROS + (string "DISABLED")) + (property UFM_INIT_START_PAGE + (string "190")) + (property UFM_INIT_PAGES + (string "321")) + (property DEV_DENSITY + (string "1200L")) + (property EFB_UFM + (string "ENABLED")) + (property TC_ICAPTURE + (string "DISABLED")) + (property TC_OVERFLOW + (string "DISABLED")) + (property TC_ICR_INT + (string "OFF")) + (property TC_OCR_INT + (string "OFF")) + (property TC_OV_INT + (string "OFF")) + (property TC_TOP_SEL + (string "OFF")) + (property TC_RESETN + (string "ENABLED")) + (property TC_OC_MODE + (string "TOGGLE")) + (property TC_OCR_SET + (string "32767")) + (property TC_TOP_SET + (string "65535")) + (property GSR + (string "ENABLED")) + (property TC_CCLK_SEL + (string "1")) + (property TC_MODE + (string "CTCM")) + (property TC_SCLK_SEL + (string "PCLOCK")) + (property EFB_TC_PORTMODE + (string "WB")) + (property EFB_TC + (string "DISABLED")) + (property SPI_WAKEUP + (string "DISABLED")) + (property SPI_INTR_RXOVR + (string "DISABLED")) + (property SPI_INTR_TXOVR + (string "DISABLED")) + (property SPI_INTR_RXRDY + (string "DISABLED")) + (property SPI_INTR_TXRDY + (string "DISABLED")) + (property SPI_SLAVE_HANDSHAKE + (string "DISABLED")) + (property SPI_PHASE_ADJ + (string "DISABLED")) + (property SPI_CLK_INV + (string "DISABLED")) + (property SPI_LSB_FIRST + (string "DISABLED")) + (property SPI_CLK_DIVIDER + (string "1")) + (property SPI_MODE + (string "MASTER")) + (property EFB_SPI + (string "DISABLED")) + (property I2C2_WAKEUP + (string "DISABLED")) + (property I2C2_GEN_CALL + (string "DISABLED")) + (property I2C2_CLK_DIVIDER + (string "1")) + (property I2C2_BUS_PERF + (string "100kHz")) + (property I2C2_SLAVE_ADDR + (string "0b1000010")) + (property I2C2_ADDRESSING + (string "7BIT")) + (property EFB_I2C2 + (string "DISABLED")) + (property I2C1_WAKEUP + (string "DISABLED")) + (property I2C1_GEN_CALL + (string "DISABLED")) + (property I2C1_CLK_DIVIDER + (string "1")) + (property I2C1_BUS_PERF + (string "100kHz")) + (property I2C1_SLAVE_ADDR + (string "0b1000001")) + (property I2C1_ADDRESSING + (string "7BIT")) + (property EFB_I2C1 + (string "DISABLED")) + (property EFB_WB_CLK_FREQ + (string "14.4"))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef UFMSN (instanceRef EFBInst_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef PLL1DATI7 (instanceRef EFBInst_0)) + (portRef PLL1DATI6 (instanceRef EFBInst_0)) + (portRef PLL1DATI5 (instanceRef EFBInst_0)) + (portRef PLL1DATI4 (instanceRef EFBInst_0)) + (portRef PLL1DATI3 (instanceRef EFBInst_0)) + (portRef PLL1DATI2 (instanceRef EFBInst_0)) + (portRef PLL1DATI1 (instanceRef EFBInst_0)) + (portRef PLL1DATI0 (instanceRef EFBInst_0)) + (portRef PLL1ACKI (instanceRef EFBInst_0)) + (portRef PLL0DATI7 (instanceRef EFBInst_0)) + (portRef PLL0DATI6 (instanceRef EFBInst_0)) + (portRef PLL0DATI5 (instanceRef EFBInst_0)) + (portRef PLL0DATI4 (instanceRef EFBInst_0)) + (portRef PLL0DATI3 (instanceRef EFBInst_0)) + (portRef PLL0DATI2 (instanceRef EFBInst_0)) + (portRef PLL0DATI1 (instanceRef EFBInst_0)) + (portRef PLL0DATI0 (instanceRef EFBInst_0)) + (portRef PLL0ACKI (instanceRef EFBInst_0)) + (portRef TCIC (instanceRef EFBInst_0)) + (portRef TCRSTN (instanceRef EFBInst_0)) + (portRef TCCLKI (instanceRef EFBInst_0)) + (portRef SPISCSN (instanceRef EFBInst_0)) + (portRef SPIMOSII (instanceRef EFBInst_0)) + (portRef SPIMISOI (instanceRef EFBInst_0)) + (portRef SPISCKI (instanceRef EFBInst_0)) + (portRef I2C2SDAI (instanceRef EFBInst_0)) + (portRef I2C2SCLI (instanceRef EFBInst_0)) + (portRef I2C1SDAI (instanceRef EFBInst_0)) + (portRef I2C1SCLI (instanceRef EFBInst_0)))) + (net wbc_ufm_irq + (joined + (portRef wbc_ufm_irq) + (portRef WBCUFMIRQ (instanceRef EFBInst_0)))) + (net wb_ack_o + (joined + (portRef wb_ack_o) + (portRef WBACKO (instanceRef EFBInst_0)))) + (net wb_dat_o7 + (joined + (portRef (member wb_dat_o 0)) + (portRef WBDATO7 (instanceRef EFBInst_0)))) + (net wb_dat_o6 + (joined + (portRef (member wb_dat_o 1)) + (portRef WBDATO6 (instanceRef EFBInst_0)))) + (net wb_dat_o5 + (joined + (portRef (member wb_dat_o 2)) + (portRef WBDATO5 (instanceRef EFBInst_0)))) + (net wb_dat_o4 + (joined + (portRef (member wb_dat_o 3)) + (portRef WBDATO4 (instanceRef EFBInst_0)))) + (net wb_dat_o3 + (joined + (portRef (member wb_dat_o 4)) + (portRef WBDATO3 (instanceRef EFBInst_0)))) + (net wb_dat_o2 + (joined + (portRef (member wb_dat_o 5)) + (portRef WBDATO2 (instanceRef EFBInst_0)))) + (net wb_dat_o1 + (joined + (portRef (member wb_dat_o 6)) + (portRef WBDATO1 (instanceRef EFBInst_0)))) + (net wb_dat_o0 + (joined + (portRef (member wb_dat_o 7)) + (portRef WBDATO0 (instanceRef EFBInst_0)))) + (net wb_dat_i7 + (joined + (portRef (member wb_dat_i 0)) + (portRef WBDATI7 (instanceRef EFBInst_0)))) + (net wb_dat_i6 + (joined + (portRef (member wb_dat_i 1)) + (portRef WBDATI6 (instanceRef EFBInst_0)))) + (net wb_dat_i5 + (joined + (portRef (member wb_dat_i 2)) + (portRef WBDATI5 (instanceRef EFBInst_0)))) + (net wb_dat_i4 + (joined + (portRef (member wb_dat_i 3)) + (portRef WBDATI4 (instanceRef EFBInst_0)))) + (net wb_dat_i3 + (joined + (portRef (member wb_dat_i 4)) + (portRef WBDATI3 (instanceRef EFBInst_0)))) + (net wb_dat_i2 + (joined + (portRef (member wb_dat_i 5)) + (portRef WBDATI2 (instanceRef EFBInst_0)))) + (net wb_dat_i1 + (joined + (portRef (member wb_dat_i 6)) + (portRef WBDATI1 (instanceRef EFBInst_0)))) + (net wb_dat_i0 + (joined + (portRef (member wb_dat_i 7)) + (portRef WBDATI0 (instanceRef EFBInst_0)))) + (net wb_adr_i7 + (joined + (portRef (member wb_adr_i 0)) + (portRef WBADRI7 (instanceRef EFBInst_0)))) + (net wb_adr_i6 + (joined + (portRef (member wb_adr_i 1)) + (portRef WBADRI6 (instanceRef EFBInst_0)))) + (net wb_adr_i5 + (joined + (portRef (member wb_adr_i 2)) + (portRef WBADRI5 (instanceRef EFBInst_0)))) + (net wb_adr_i4 + (joined + (portRef (member wb_adr_i 3)) + (portRef WBADRI4 (instanceRef EFBInst_0)))) + (net wb_adr_i3 + (joined + (portRef (member wb_adr_i 4)) + (portRef WBADRI3 (instanceRef EFBInst_0)))) + (net wb_adr_i2 + (joined + (portRef (member wb_adr_i 5)) + (portRef WBADRI2 (instanceRef EFBInst_0)))) + (net wb_adr_i1 + (joined + (portRef (member wb_adr_i 6)) + (portRef WBADRI1 (instanceRef EFBInst_0)))) + (net wb_adr_i0 + (joined + (portRef (member wb_adr_i 7)) + (portRef WBADRI0 (instanceRef EFBInst_0)))) + (net wb_we_i + (joined + (portRef wb_we_i) + (portRef WBWEI (instanceRef EFBInst_0)))) + (net wb_stb_i + (joined + (portRef wb_stb_i) + (portRef WBSTBI (instanceRef EFBInst_0)))) + (net wb_cyc_i + (joined + (portRef wb_cyc_i) + (portRef WBCYCI (instanceRef EFBInst_0)))) + (net wb_rst_i + (joined + (portRef wb_rst_i) + (portRef WBRSTI (instanceRef EFBInst_0)))) + (net wb_clk_i + (joined + (portRef wb_clk_i) + (portRef WBCLKI (instanceRef EFBInst_0)))))))) + (design REFB + (cellRef REFB + (libraryRef ORCLIB))) +) diff --git a/CPLD/LCMXO2-1200HC/REFB.ipx b/CPLD/LCMXO2-1200HC/REFB.ipx new file mode 100644 index 0000000..979cf73 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/REFB.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/CPLD/LCMXO2-1200HC/REFB.lpc b/CPLD/LCMXO2-1200HC/REFB.lpc new file mode 100644 index 0000000..a1d3684 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/REFB.lpc @@ -0,0 +1,141 @@ +[Device] +Family=machxo2 +PartType=LCMXO2-1200HC +PartName=LCMXO2-1200HC-4TG100C +SpeedGrade=4 +Package=TQFP100 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=EFB +CoreRevision=1.2 +ModuleName=REFB +SourceFormat=Verilog HDL +ParameterFileVersion=1.0 +Date=09/20/2023 +Time=04:45:58 + +[Parameters] +Verilog=1 +VHDL=0 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +freq= +i2c1=0 +i2c1config=0 +i2c1_addr=7-Bit Addressing +i2c1_ce=0 +i2c1_freq=100 +i2c1_sa=10000 +i2c1_we=0 +i2c2=0 +i2c2_addr=7-Bit Addressing +i2c2_ce=0 +i2c2_freq=100 +i2c2_sa=10000 +i2c2_we=0 +ufm_addr=7-Bit Addressing +ufm_sa=10000 +pll=0 +pll_cnt=1 +spi=0 +spi_clkinv=0 +spi_cs=1 +spi_en=0 +spi_freq=1 +spi_lsb=0 +spi_mode=Slave +spi_ib=0 +spi_ph=0 +spi_hs=0 +spi_rxo=0 +spi_rxr=0 +spi_txo=0 +spi_txr=0 +spi_we=0 +static_tc=Static +tc=0 +tc_clkinv=Positive +tc_ctr=1 +tc_div=1 +tc_ipcap=0 +tc_mode=CTCM +tc_ocr=32767 +tc_oflow=1 +tc_o=TOGGLE +tc_opcomp=0 +tc_osc=0 +tc_sa_oflow=0 +tc_top=65535 +ufm=1 +ufm0=0 +ufm1=0 +ufm2=0 +ufm3=0 +ufm_cfg0=0 +ufm_cfg1=0 +wb_clk_freq=14.4 +ufm_usage=SHARED_EBR_TAG +ufm_ebr=190 +ufm_remain= +mem_size=321 +ufm_start= +ufm_init=mem +memfile=../RAM2E-LCMXO2.mem +ufm_dt=hex +ufm0_ebr= +mem_size0=1 +ufm0_init=0 +memfile0= +ufm0_dt=hex +ufm1_ebr= +mem_size1=1 +ufm1_init=0 +memfile1= +ufm1_dt=hex +ufm2_ebr= +mem_size2=1 +ufm2_init=0 +memfile2= +ufm2_dt=hex +ufm3_ebr= +mem_size3=1 +ufm3_init=0 +memfile3= +ufm3_dt=hex +ufm_cfg0_ebr= +mem_size_cfg0=1 +ufm_cfg0_init=0 +memfile_cfg0= +ufm_cfg0_dt=hex +ufm_cfg1_ebr= +mem_size_cfg1=1 +ufm_cfg1_init=0 +memfile_cfg1= +ufm_cfg1_dt=hex +wb=1 +boot_option=Internal +efb_ufm=0 +boot_option_internal=Single Boot +internal_ufm0=0 +internal_ufm1=0 +efb_ufm_boot= +tamperdr=0 +t_pwd=0 +t_lockflash=0 +t_manmode=0 +t_jtagport=0 +t_sspiport=0 +t_sic2port=0 +t_wbport=0 +t_portlock=0 + +[Command] +cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 diff --git a/CPLD/LCMXO2-1200HC/REFB.naf b/CPLD/LCMXO2-1200HC/REFB.naf new file mode 100644 index 0000000..5c239f5 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/REFB.naf @@ -0,0 +1,31 @@ +wb_clk_i i +wb_rst_i i +wb_cyc_i i +wb_stb_i i +wb_we_i i +wb_adr_i[7] i +wb_adr_i[6] i +wb_adr_i[5] i +wb_adr_i[4] i +wb_adr_i[3] i +wb_adr_i[2] i +wb_adr_i[1] i +wb_adr_i[0] i +wb_dat_i[7] i +wb_dat_i[6] i +wb_dat_i[5] i +wb_dat_i[4] i +wb_dat_i[3] i +wb_dat_i[2] i +wb_dat_i[1] i +wb_dat_i[0] i +wb_dat_o[7] o +wb_dat_o[6] o +wb_dat_o[5] o +wb_dat_o[4] o +wb_dat_o[3] o +wb_dat_o[2] o +wb_dat_o[1] o +wb_dat_o[0] o +wb_ack_o o +wbc_ufm_irq o diff --git a/CPLD/LCMXO2-1200HC/REFB.sort b/CPLD/LCMXO2-1200HC/REFB.sort new file mode 100644 index 0000000..96fe0d5 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/REFB.sort @@ -0,0 +1 @@ +REFB.v diff --git a/CPLD/LCMXO2-1200HC/REFB.srp b/CPLD/LCMXO2-1200HC/REFB.srp new file mode 100644 index 0000000..b2c0184 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/REFB.srp @@ -0,0 +1,26 @@ +SCUBA, Version Diamond (64-bit) 3.12.1.454 +Wed Sep 20 04:45:58 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 + Circuit name : REFB + Module type : efb + Module Version : 1.2 + Ports : + Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] + Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq + I/O buffer : not inserted + EDIF output : REFB.edn + Verilog output : REFB.v + Verilog template : REFB_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : REFB.srp + Element Usage : + EFB : 1 + Estimated Resource Usage: diff --git a/CPLD/LCMXO2-1200HC/REFB.sym b/CPLD/LCMXO2-1200HC/REFB.sym new file mode 100644 index 0000000000000000000000000000000000000000..6588d30b2bc7e6a6518bfbc7efc6f7cfc3b4c069 GIT binary patch literal 466 zcmYk2F-XHu5QhJ23u;9u;?Th%Lnd*^AP6E3VlrxwilAtkq!vOejcGNwIEzzoa27`q zaTKTG;OOAwn90%E(f_?rYv9Pockk}qy@y@!D>FW%q7YW8DF)VLQ-CE|rOB}XbAvFG z2A2t2C%hJZf_JA!)Zd(bh)xjH$1O)G8lK7GjfJU%`rK~i)NSX;!U$fwpdr?AH1U} Ezqu<`l>h($ literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-1200HC/REFB.v b/CPLD/LCMXO2-1200HC/REFB.v new file mode 100644 index 0000000..c22ffce --- /dev/null +++ b/CPLD/LCMXO2-1200HC/REFB.v @@ -0,0 +1,113 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */ +/* Module Version: 1.2 */ +/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 */ +/* Wed Sep 20 04:45:58 2023 */ + + +`timescale 1 ns / 1 ps +module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i, + wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */; + input wire wb_clk_i; + input wire wb_rst_i; + input wire wb_cyc_i; + input wire wb_stb_i; + input wire wb_we_i; + input wire [7:0] wb_adr_i; + input wire [7:0] wb_dat_i; + output wire [7:0] wb_dat_o; + output wire wb_ack_o; + output wire wbc_ufm_irq; + + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ; + defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem" ; + defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ; + defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ; + defparam EFBInst_0.UFM_INIT_PAGES = 321 ; + defparam EFBInst_0.DEV_DENSITY = "1200L" ; + defparam EFBInst_0.EFB_UFM = "ENABLED" ; + defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ; + defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ; + defparam EFBInst_0.TC_ICR_INT = "OFF" ; + defparam EFBInst_0.TC_OCR_INT = "OFF" ; + defparam EFBInst_0.TC_OV_INT = "OFF" ; + defparam EFBInst_0.TC_TOP_SEL = "OFF" ; + defparam EFBInst_0.TC_RESETN = "ENABLED" ; + defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ; + defparam EFBInst_0.TC_OCR_SET = 32767 ; + defparam EFBInst_0.TC_TOP_SET = 65535 ; + defparam EFBInst_0.GSR = "ENABLED" ; + defparam EFBInst_0.TC_CCLK_SEL = 1 ; + defparam EFBInst_0.TC_MODE = "CTCM" ; + defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ; + defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ; + defparam EFBInst_0.EFB_TC = "DISABLED" ; + defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ; + defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ; + defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ; + defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ; + defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ; + defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ; + defparam EFBInst_0.SPI_MODE = "MASTER" ; + defparam EFBInst_0.EFB_SPI = "DISABLED" ; + defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ; + defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ; + defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ; + defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ; + defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ; + defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ; + defparam EFBInst_0.EFB_I2C2 = "DISABLED" ; + defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ; + defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ; + defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ; + defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ; + defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ; + defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ; + defparam EFBInst_0.EFB_I2C1 = "DISABLED" ; + defparam EFBInst_0.EFB_WB_CLK_FREQ = "14.4" ; + EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i), + .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]), + .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]), + .WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]), + .WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]), + .WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]), + .WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo), + .PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo), + .PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo), + .PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo), + .PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo), + .PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo), + .PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo), + .I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo), + .SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo), + .SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo), + .UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]), + .WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]), + .WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]), + .WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(), + .PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(), + .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(), + .PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(), + .I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(), + .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(), + .SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(), + .SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(), + .SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(), + .WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY()); + + + + // exemplar begin + // exemplar end + +endmodule diff --git a/CPLD/LCMXO2-1200HC/REFB_generate.log b/CPLD/LCMXO2-1200HC/REFB_generate.log new file mode 100644 index 0000000..dfa91b2 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/REFB_generate.log @@ -0,0 +1,44 @@ +Starting process: Module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.12.1.454 +Wed Sep 20 04:45:58 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 + Circuit name : REFB + Module type : efb + Module Version : 1.2 + Ports : + Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] + Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq + I/O buffer : not inserted + EDIF output : REFB.edn + Verilog output : REFB.v + Verilog template : REFB_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : REFB.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + +File: REFB.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/CPLD/LCMXO2-1200HC/REFB_tmpl.v b/CPLD/LCMXO2-1200HC/REFB_tmpl.v new file mode 100644 index 0000000..41a1e6a --- /dev/null +++ b/CPLD/LCMXO2-1200HC/REFB_tmpl.v @@ -0,0 +1,8 @@ +/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */ +/* Module Version: 1.2 */ +/* Wed Sep 20 04:45:58 2023 */ + +/* parameterized module instance */ +REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), + .wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ), + .wbc_ufm_irq( )); diff --git a/CPLD/LCMXO2-1200HC/_math_real.vhd b/CPLD/LCMXO2-1200HC/_math_real.vhd new file mode 100644 index 0000000..e1215d8 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/_math_real.vhd @@ -0,0 +1,2574 @@ + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package defines a standard for designers to use in +-- describing VHDL models that make use of common REAL constants +-- and common REAL elementary mathematical functions. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076- +-- 1993. +-- +-- Notes: +-- No declarations or definitions shall be included in, or +-- excluded from, this package. +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to provide a guideline for implementations to +-- verify their implementation of MATH_REAL. Tool developers may +-- choose to implement the package body in the most efficient +-- manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package MATH_REAL is + constant CopyRightNotice: STRING + := "Copyright 1996 IEEE. All rights reserved."; + + -- + -- Constant Definitions + -- + constant MATH_E : REAL := 2.71828_18284_59045_23536; + -- Value of e + constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; + -- Value of 1/e + constant MATH_PI : REAL := 3.14159_26535_89793_23846; + -- Value of pi + constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; + -- Value of 2*pi + constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; + -- Value of 1/pi + constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; + -- Value of pi/2 + constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; + -- Value of pi/3 + constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; + -- Value of pi/4 + constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; + -- Value 3*pi/2 + constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; + -- Natural log of 2 + constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; + -- Natural log of 10 + constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; + -- Log base 2 of e + constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; + -- Log base 10 of e + constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; + -- square root of 2 + constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; + -- square root of 1/2 + constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; + -- square root of pi + constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; + -- Conversion factor from degree to radian + constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; + -- Conversion factor from radian to degree + + -- + -- Function Declarations + -- + function SIGN (X: in REAL ) return REAL; + -- Purpose: + -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIGN(X)) <= 1.0 + -- Notes: + -- None + + function CEIL (X : in REAL ) return REAL; + -- Purpose: + -- Returns smallest INTEGER value (as REAL) not less than X + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CEIL(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function FLOOR (X : in REAL ) return REAL; + -- Purpose: + -- Returns largest INTEGER value (as REAL) not greater than X + -- Special values: + -- FLOOR(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- FLOOR(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function ROUND (X : in REAL ) return REAL; + -- Purpose: + -- Rounds X to the nearest integer value (as real). If X is + -- halfway between two integers, rounding is away from 0.0 + -- Special values: + -- ROUND(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ROUND(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function TRUNC (X : in REAL ) return REAL; + -- Purpose: + -- Truncates X towards 0.0 and returns truncated value + -- Special values: + -- TRUNC(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- TRUNC(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function "MOD" (X, Y: in REAL ) return REAL; + -- Purpose: + -- Returns floating point modulus of X/Y, with the same sign as + -- Y, and absolute value less than the absolute value of Y, and + -- for some INTEGER value N the result satisfies the relation + -- X = Y*N + MOD(X,Y) + -- Special values: + -- None + -- Domain: + -- X in REAL; Y in REAL and Y /= 0.0 + -- Error conditions: + -- Error if Y = 0.0 + -- Range: + -- ABS(MOD(X,Y)) < ABS(Y) + -- Notes: + -- None + + function REALMAX (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically larger of X and Y + -- Special values: + -- REALMAX(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMAX(X,Y) is mathematically unbounded + -- Notes: + -- None + + function REALMIN (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically smaller of X and Y + -- Special values: + -- REALMIN(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMIN(X,Y) is mathematically unbounded + -- Notes: + -- None + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); + -- Purpose: + -- Returns, in X, a pseudo-random number with uniform + -- distribution in the open interval (0.0, 1.0). + -- Special values: + -- None + -- Domain: + -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 + -- Error conditions: + -- Error if SEED1 or SEED2 outside of valid domain + -- Range: + -- 0.0 < X < 1.0 + -- Notes: + -- a) The semantics for this function are described by the + -- algorithm published by Pierre L'Ecuyer in "Communications + -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. + -- The algorithm is based on the combination of two + -- multiplicative linear congruential generators for 32-bit + -- platforms. + -- + -- b) Before the first call to UNIFORM, the seed values + -- (SEED1, SEED2) have to be initialized to values in the range + -- [1, 2147483562] and [1, 2147483398] respectively. The + -- seed values are modified after each call to UNIFORM. + -- + -- c) This random number generator is portable for 32-bit + -- computers, and it has a period of ~2.30584*(10**18) for each + -- set of seed values. + -- + -- d) For information on spectral tests for the algorithm, refer + -- to the L'Ecuyer article. + + function SQRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns square root of X + -- Special values: + -- SQRT(0.0) = 0.0 + -- SQRT(1.0) = 1.0 + -- Domain: + -- X >= 0.0 + -- Error conditions: + -- Error if X < 0.0 + -- Range: + -- SQRT(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of SQRT is + -- approximately given by: + -- SQRT(X) <= SQRT(REAL'HIGH) + + function CBRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns cube root of X + -- Special values: + -- CBRT(0.0) = 0.0 + -- CBRT(1.0) = 1.0 + -- CBRT(-1.0) = -1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CBRT(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of CBRT is approximately given by: + -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) + + function "**" (X : in INTEGER; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0 + -- 0**Y = 0.0; Y > 0.0 + -- X**1.0 = REAL(X); X >= 0 + -- 1**Y = 1.0 + -- Domain: + -- X > 0 + -- X = 0 for Y > 0.0 + -- X < 0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0 and Y /= 0.0 + -- Error if X = 0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function "**" (X : in REAL; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0.0 + -- 0.0**Y = 0.0; Y > 0.0 + -- X**1.0 = X; X >= 0.0 + -- 1.0**Y = 1.0 + -- Domain: + -- X > 0.0 + -- X = 0.0 for Y > 0.0 + -- X < 0.0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0.0 and Y /= 0.0 + -- Error if X = 0.0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function EXP (X : in REAL ) return REAL; + -- Purpose: + -- Returns e**X; where e = MATH_E + -- Special values: + -- EXP(0.0) = 1.0 + -- EXP(1.0) = MATH_E + -- EXP(-1.0) = MATH_1_OVER_E + -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) + -- Domain: + -- X in REAL such that EXP(X) <= REAL'HIGH + -- Error conditions: + -- Error if X > LOG(REAL'HIGH) + -- Range: + -- EXP(X) >= 0.0 + -- Notes: + -- a) The usable domain of EXP is approximately given by: + -- X <= LOG(REAL'HIGH) + + function LOG (X : in REAL ) return REAL; + -- Purpose: + -- Returns natural logarithm of X + -- Special values: + -- LOG(1.0) = 0.0 + -- LOG(MATH_E) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG is approximately given by: + -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) + + function LOG2 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 2 of X + -- Special values: + -- LOG2(1.0) = 0.0 + -- LOG2(2.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG2(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG2 is approximately given by: + -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) + + function LOG10 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 10 of X + -- Special values: + -- LOG10(1.0) = 0.0 + -- LOG10(10.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG10(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG10 is approximately given by: + -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) + + function LOG (X: in REAL; BASE: in REAL) return REAL; + -- Purpose: + -- Returns logarithm base BASE of X + -- Special values: + -- LOG(1.0, BASE) = 0.0 + -- LOG(BASE, BASE) = 1.0 + -- Domain: + -- X > 0.0 + -- BASE > 0.0 + -- BASE /= 1.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Error if BASE <= 0.0 + -- Error if BASE = 1.0 + -- Range: + -- LOG(X, BASE) is mathematically unbounded + -- Notes: + -- a) When BASE > 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) + -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) + + function SIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns sine of X; X in radians + -- Special values: + -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIN(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function COS ( X : in REAL ) return REAL; + -- Purpose: + -- Returns cosine of X; X in radians + -- Special values: + -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER + -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(COS(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function TAN (X : in REAL ) return REAL; + -- Purpose: + -- Returns tangent of X; X in radians + -- Special values: + -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL and + -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER + -- Error conditions: + -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an + -- INTEGER + -- Range: + -- TAN(X) is mathematically unbounded + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function ARCSIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse sine of X + -- Special values: + -- ARCSIN(0.0) = 0.0 + -- ARCSIN(1.0) = MATH_PI_OVER_2 + -- ARCSIN(-1.0) = -MATH_PI_OVER_2 + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCCOS (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse cosine of X + -- Special values: + -- ARCCOS(1.0) = 0.0 + -- ARCCOS(0.0) = MATH_PI_OVER_2 + -- ARCCOS(-1.0) = MATH_PI + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- 0.0 <= ARCCOS(X) <= MATH_PI + -- Notes: + -- None + + function ARCTAN (Y : in REAL) return REAL; + -- Purpose: + -- Returns the value of the angle in radians of the point + -- (1.0, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0) = 0.0 + -- Domain: + -- Y in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCTAN (Y : in REAL; X : in REAL) return REAL; + -- Purpose: + -- Returns the principal value of the angle in radians of + -- the point (X, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0, X) = 0.0 if X > 0.0 + -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 + -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 + -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 + -- Domain: + -- Y in REAL + -- X in REAL, X /= 0.0 when Y = 0.0 + -- Error conditions: + -- Error if X = 0.0 and Y = 0.0 + -- Range: + -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI + -- Notes: + -- None + + function SINH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic sine of X + -- Special values: + -- SINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- SINH(X) is mathematically unbounded + -- Notes: + -- a) The usable domain of SINH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + + function COSH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic cosine of X + -- Special values: + -- COSH(0.0) = 1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- COSH(X) >= 1.0 + -- Notes: + -- a) The usable domain of COSH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + function TANH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic tangent of X + -- Special values: + -- TANH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(TANH(X)) <= 1.0 + -- Notes: + -- None + + function ARCSINH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic sine of X + -- Special values: + -- ARCSINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ARCSINH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCSINH is approximately given by: + -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) + + function ARCCOSH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic cosine of X + -- Special values: + -- ARCCOSH(1.0) = 0.0 + -- Domain: + -- X >= 1.0 + -- Error conditions: + -- Error if X < 1.0 + -- Range: + -- ARCCOSH(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of ARCCOSH is + -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) + + function ARCTANH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic tangent of X + -- Special values: + -- ARCTANH(0.0) = 0.0 + -- Domain: + -- ABS(X) < 1.0 + -- Error conditions: + -- Error if ABS(X) >= 1.0 + -- Range: + -- ARCTANH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCTANH is approximately given by: + -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) + +end MATH_REAL; + + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. + +-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. + +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package body is a nonnormative implementation of the +-- functionality defined in the MATH_REAL package declaration. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076 +-- -1993. +-- +-- Notes: +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to clarify such semantics and provide a +-- guideline for implementations to verify their implementation +-- of MATH_REAL. Tool developers may choose to implement +-- the package body in the most efficient manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package body MATH_REAL is + + -- + -- Local Constants for Use in the Package Body Only + -- + constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 + constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 + constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi + constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic + constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries + constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria + constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic + + -- + -- Local Type Declarations for Cordic Operations + -- + type REAL_VECTOR is array (NATURAL range <>) of REAL; + type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; + subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); + subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); + subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); + subtype QUADRANT is INTEGER range 0 to 3; + type CORDIC_MODE_TYPE is (ROTATION, VECTORING); + + -- + -- Auxiliary Functions for Cordic Algorithms + -- + function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; + NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is + -- Description: + -- Returns power of two for a vector of values + -- Notes: + -- None + -- + variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); + variable TEMP : REAL := INITIAL_VALUE; + variable FLAG : BOOLEAN := TRUE; + begin + for I in 0 to NUMBER_OF_VALUES loop + V(I) := TEMP; + for P in D'RANGE loop + if I = D(P) then + FLAG := FALSE; + exit; + end if; + end loop; + if FLAG then + TEMP := TEMP/2.0; + end if; + FLAG := TRUE; + end loop; + return V; + end POWER_OF_2_SERIES; + + + constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( + NATURAL_VECTOR'(100, 90),1.0, + MAX_ITER); + + constant EPSILON : REAL_VECTOR_N := ( + 7.8539816339744827e-01, + 4.6364760900080606e-01, + 2.4497866312686413e-01, + 1.2435499454676144e-01, + 6.2418809995957351e-02, + 3.1239833430268277e-02, + 1.5623728620476830e-02, + 7.8123410601011116e-03, + 3.9062301319669717e-03, + 1.9531225164788189e-03, + 9.7656218955931937e-04, + 4.8828121119489829e-04, + 2.4414062014936175e-04, + 1.2207031189367021e-04, + 6.1035156174208768e-05, + 3.0517578115526093e-05, + 1.5258789061315760e-05, + 7.6293945311019699e-06, + 3.8146972656064960e-06, + 1.9073486328101870e-06, + 9.5367431640596080e-07, + 4.7683715820308876e-07, + 2.3841857910155801e-07, + 1.1920928955078067e-07, + 5.9604644775390553e-08, + 2.9802322387695303e-08, + 1.4901161193847654e-08, + 7.4505805969238281e-09 + ); + + function CORDIC ( X0 : in REAL; + Y0 : in REAL; + Z0 : in REAL; + N : in NATURAL; -- Precision factor + CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) + -- or vectoring (Y -> 0) + ) return REAL_ARR_3 is + -- Description: + -- Compute cordic values + -- Notes: + -- None + variable X : REAL := X0; + variable Y : REAL := Y0; + variable Z : REAL := Z0; + variable X_TEMP : REAL; + begin + if CORDIC_MODE = ROTATION then + for K in 0 to N loop + X_TEMP := X; + if ( Z >= 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + else + for K in 0 to N loop + X_TEMP := X; + if ( Y < 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + end if; + return REAL_ARR_3'(X, Y, Z); + end CORDIC; + + -- + -- Bodies for Global Mathematical Functions Start Here + -- + function SIGN (X: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + if ( X > 0.0 ) then + return 1.0; + elsif ( X < 0.0 ) then + return -1.0; + else + return 0.0; + end if; + end SIGN; + + function CEIL (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is X <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS(X) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD >= X then + return RD; + else + return RD + 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD <= X then + return RD + 1.0; + else + return RD; + end if; + end if; + end CEIL; + + function FLOOR (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is ABS(X) <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS( X ) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD <= X then + return RD; + else + return RD - 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD >= X then + return RD - 1.0; + else + return RD; + end if; + end if; + end FLOOR; + + function ROUND (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X + 0.5) if X > 0 + -- c) Returns CEIL(X - 0.5) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X + 0.5); + elsif X < 0.0 then + return CEIL( X - 0.5); + else + return 0.0; + end if; + end ROUND; + + function TRUNC (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X) if X > 0 + -- c) Returns CEIL(X) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X); + elsif X < 0.0 then + return CEIL( X); + else + return 0.0; + end if; + end TRUNC; + + + + + function "MOD" (X, Y: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable XNEGATIVE : BOOLEAN := X < 0.0; + variable YNEGATIVE : BOOLEAN := Y < 0.0; + variable VALUE : REAL; + begin + -- Check validity of input arguments + if (Y = 0.0) then + assert FALSE + report "MOD(X, 0.0) is undefined" + severity ERROR; + return 0.0; + end if; + + -- Compute value + if ( XNEGATIVE ) then + if ( YNEGATIVE ) then + VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + end if; + else + if ( YNEGATIVE ) then + VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + end if; + end if; + + return VALUE; + end "MOD"; + + + function REALMAX (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMAX(X,Y) = X when X = Y + -- + begin + if X >= Y then + return X; + else + return Y; + end if; + end REALMAX; + + function REALMIN (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMIN(X,Y) = X when X = Y + -- + begin + if X <= Y then + return X; + else + return Y; + end if; + end REALMIN; + + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) + is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + -- + variable Z, K: INTEGER; + variable TSEED1 : INTEGER := INTEGER'(SEED1); + variable TSEED2 : INTEGER := INTEGER'(SEED2); + begin + -- Check validity of arguments + if SEED1 > 2147483562 then + assert FALSE + report "SEED1 > 2147483562 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + if SEED2 > 2147483398 then + assert FALSE + report "SEED2 > 2147483398 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + -- Compute new seed values and pseudo-random number + K := TSEED1/53668; + TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; + + if TSEED1 < 0 then + TSEED1 := TSEED1 + 2147483563; + end if; + + K := TSEED2/52774; + TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; + + if TSEED2 < 0 then + TSEED2 := TSEED2 + 2147483399; + end if; + + Z := TSEED1 - TSEED2; + if Z < 1 then + Z := Z + 2147483562; + end if; + + -- Get output values + SEED1 := POSITIVE'(TSEED1); + SEED2 := POSITIVE'(TSEED2); + X := REAL(Z)*4.656613e-10; + end UNIFORM; + + + + function SQRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = 0.5*[F(n) + x/F(n)] + -- b) Returns 0.0 on error + -- + + constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor + + variable INIVAL: REAL; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + -- Check validity of argument + if ( X < 0.0 ) then + assert FALSE + report "X < 0.0 in SQRT(X)" + severity ERROR; + return 0.0; + end if; + + -- Get the square root for special cases + if X = 0.0 then + return 0.0; + else + if ( X = 1.0 ) then + return 1.0; + end if; + end if; + + -- Get the square root for general cases + INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise + OLDVAL := INIVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + + -- Check for relative and absolute error and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT) ) loop + OLDVAL := NEWVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + COUNT := COUNT + 1; + end loop; + return NEWVAL; + end SQRT; + + function CBRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; + -- + constant EPS : REAL := BASE_EPS*BASE_EPS; + + variable INIVAL: REAL; + variable XLOCAL : REAL := X; + variable NEGATIVE : BOOLEAN := X < 0.0; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + + -- Compute root for special cases + if X = 0.0 then + return 0.0; + elsif ( X = 1.0 ) then + return 1.0; + else + if X = -1.0 then + return -1.0; + end if; + end if; + + -- Compute root for general cases + if NEGATIVE then + XLOCAL := -X; + end if; + + INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but + -- imprecise + OLDVAL := INIVAL; + NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR + (ABS(NEWVAL - OLDVAL) > EPS ) ) AND + ( COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + COUNT := COUNT + 1; + end loop; + + if NEGATIVE then + NEWVAL := -NEWVAL; + end if; + + return NEWVAL; + end CBRT; + + function "**" (X : in INTEGER; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (REAL(X)); + end if; + + -- Get value for general case + return EXP (Y * LOG (REAL(X))); + end "**"; + + function "**" (X : in REAL; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0.0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0.0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0.0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1.0 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0.0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (X); + end if; + + -- Get value for general case + return EXP (Y * LOG (X)); + end "**"; + + function EXP (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) This function computes the exponential using the following + -- series: + -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 + -- and reduces argument X to take advantage of exp(x+y) = + -- exp(x)*exp(y) + -- + -- b) This implementation limits X to be less than LOG(REAL'HIGH) + -- to avoid overflow. Returns REAL'HIGH when X reaches that + -- limit + -- + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria + + variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument + variable XLOCAL : REAL := ABS(X); -- Use positive value + variable OLDVAL: REAL ; + variable COUNT: INTEGER ; + variable NEWVAL: REAL ; + variable LAST_TERM: REAL ; + variable FACTOR : REAL := 1.0; + + begin + -- Compute value for special cases + if X = 0.0 then + return 1.0; + end if; + + if XLOCAL = 1.0 then + if RECIPROCAL then + return MATH_1_OVER_E; + else + return MATH_E; + end if; + end if; + + if XLOCAL = 2.0 then + if RECIPROCAL then + return 1.0/MATH_E_P2; + else + return MATH_E_P2; + end if; + end if; + + if XLOCAL = 10.0 then + if RECIPROCAL then + return 1.0/MATH_E_P10; + else + return MATH_E_P10; + end if; + end if; + + if XLOCAL > LOG(REAL'HIGH) then + if RECIPROCAL then + return 0.0; + else + assert FALSE + report "X > LOG(REAL'HIGH) in EXP(X)" + severity NOTE; + return REAL'HIGH; + end if; + end if; + + -- Reduce argument to ABS(X) < 1.0 + while XLOCAL > 10.0 loop + XLOCAL := XLOCAL - 10.0; + FACTOR := FACTOR*MATH_E_P10; + end loop; + + while XLOCAL > 1.0 loop + XLOCAL := XLOCAL - 1.0; + FACTOR := FACTOR*MATH_E; + end loop; + + -- Compute value for case 0 < XLOCAL < 1 + OLDVAL := 1.0; + LAST_TERM := XLOCAL; + NEWVAL:= OLDVAL + LAST_TERM; + COUNT := 2; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); + NEWVAL := OLDVAL + LAST_TERM; + COUNT := COUNT + 1; + end loop; + + -- Compute final value using exp(x+y) = exp(x)*exp(y) + NEWVAL := NEWVAL*FACTOR; + + if RECIPROCAL then + NEWVAL := 1.0/NEWVAL; + end if; + + return NEWVAL; + end EXP; + + + -- + -- Auxiliary Functions to Compute LOG + -- + function ILOGB(X: in REAL) return INTEGER IS + -- Description: + -- Returns n such that -1 <= ABS(X)/2^n < 2 + -- Notes: + -- None + + variable N: INTEGER := 0; + variable Y: REAL := ABS(X); + + begin + if(Y = 1.0 or Y = 0.0) then + return 0; + end if; + + if( Y > 1.0) then + while Y >= 2.0 loop + Y := Y/2.0; + N := N+1; + end loop; + return N; + end if; + + -- O < Y < 1 + while Y < 1.0 loop + Y := Y*2.0; + N := N -1; + end loop; + return N; + end ILOGB; + + function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS + -- Description: + -- Returns X*2^n + -- Notes: + -- None + begin + return X*(2.0 ** N); + end LDEXP; + + function LOG (X : in REAL ) return REAL IS + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- + -- Notes: + -- a) Returns REAL'LOW on error + -- + -- Copyright (c) 1992 Regents of the University of California. + -- All rights reserved. + -- + -- Redistribution and use in source and binary forms, with or without + -- modification, are permitted provided that the following conditions + -- are met: + -- 1. Redistributions of source code must retain the above copyright + -- notice, this list of conditions and the following disclaimer. + -- 2. Redistributions in binary form must reproduce the above copyright + -- notice, this list of conditions and the following disclaimer in the + -- documentation and/or other materials provided with the distribution. + -- 3. All advertising materials mentioning features or use of this + -- software must display the following acknowledgement: + -- This product includes software developed by the University of + -- California, Berkeley and its contributors. + -- 4. Neither the name of the University nor the names of its + -- contributors may be used to endorse or promote products derived + -- from this software without specific prior written permission. + -- + -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' + -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR + -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + -- DAMAGE. + -- + -- NOTE: This VHDL version was generated using the C version of the + -- original function by the IEEE VHDL Mathematical Package + -- Working Group (CS/JT) + + constant N: INTEGER := 128; + + -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. + -- Used for generation of extend precision logarithms. + -- The constant 35184372088832 is 2^45, so the divide is exact. + -- It ensures correct reading of logF_head, even for inaccurate + -- decimal-to-binary conversion routines. (Everybody gets the + -- right answer for INTEGERs less than 2^53.) + -- Values for LOG(F) were generated using error < 10^-57 absolute + -- with the bc -l package. + + type REAL_VECTOR is array (NATURAL range <>) of REAL; + + constant A1:REAL := 0.08333333333333178827; + constant A2:REAL := 0.01250000000377174923; + constant A3:REAL := 0.002232139987919447809; + constant A4:REAL := 0.0004348877777076145742; + + constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( + 0.0, + 0.007782140442060381246, + 0.015504186535963526694, + 0.023167059281547608406, + 0.030771658666765233647, + 0.038318864302141264488, + 0.045809536031242714670, + 0.053244514518837604555, + 0.060624621816486978786, + 0.067950661908525944454, + 0.075223421237524235039, + 0.082443669210988446138, + 0.089612158689760690322, + 0.096729626458454731618, + 0.103796793681567578460, + 0.110814366340264314203, + 0.117783035656430001836, + 0.124703478501032805070, + 0.131576357788617315236, + 0.138402322859292326029, + 0.145182009844575077295, + 0.151916042025732167530, + 0.158605030176659056451, + 0.165249572895390883786, + 0.171850256926518341060, + 0.178407657472689606947, + 0.184922338493834104156, + 0.191394852999565046047, + 0.197825743329758552135, + 0.204215541428766300668, + 0.210564769107350002741, + 0.216873938300523150246, + 0.223143551314024080056, + 0.229374101064877322642, + 0.235566071312860003672, + 0.241719936886966024758, + 0.247836163904594286577, + 0.253915209980732470285, + 0.259957524436686071567, + 0.265963548496984003577, + 0.271933715484010463114, + 0.277868451003087102435, + 0.283768173130738432519, + 0.289633292582948342896, + 0.295464212893421063199, + 0.301261330578199704177, + 0.307025035294827830512, + 0.312755710004239517729, + 0.318453731118097493890, + 0.324119468654316733591, + 0.329753286372579168528, + 0.335355541920762334484, + 0.340926586970454081892, + 0.346466767346100823488, + 0.351976423156884266063, + 0.357455888922231679316, + 0.362905493689140712376, + 0.368325561158599157352, + 0.373716409793814818840, + 0.379078352934811846353, + 0.384411698910298582632, + 0.389716751140440464951, + 0.394993808240542421117, + 0.400243164127459749579, + 0.405465108107819105498, + 0.410659924985338875558, + 0.415827895143593195825, + 0.420969294644237379543, + 0.426084395310681429691, + 0.431173464818130014464, + 0.436236766774527495726, + 0.441274560805140936281, + 0.446287102628048160113, + 0.451274644139630254358, + 0.456237433481874177232, + 0.461175715122408291790, + 0.466089729924533457960, + 0.470979715219073113985, + 0.475845904869856894947, + 0.480688529345570714212, + 0.485507815781602403149, + 0.490303988045525329653, + 0.495077266798034543171, + 0.499827869556611403822, + 0.504556010751912253908, + 0.509261901790523552335, + 0.513945751101346104405, + 0.518607764208354637958, + 0.523248143765158602036, + 0.527867089620485785417, + 0.532464798869114019908, + 0.537041465897345915436, + 0.541597282432121573947, + 0.546132437597407260909, + 0.550647117952394182793, + 0.555141507540611200965, + 0.559615787935399566777, + 0.564070138285387656651, + 0.568504735352689749561, + 0.572919753562018740922, + 0.577315365035246941260, + 0.581691739635061821900, + 0.586049045003164792433, + 0.590387446602107957005, + 0.594707107746216934174, + 0.599008189645246602594, + 0.603290851438941899687, + 0.607555250224322662688, + 0.611801541106615331955, + 0.616029877215623855590, + 0.620240409751204424537, + 0.624433288012369303032, + 0.628608659422752680256, + 0.632766669570628437213, + 0.636907462236194987781, + 0.641031179420679109171, + 0.645137961373620782978, + 0.649227946625615004450, + 0.653301272011958644725, + 0.657358072709030238911, + 0.661398482245203922502, + 0.665422632544505177065, + 0.669430653942981734871, + 0.673422675212350441142, + 0.677398823590920073911, + 0.681359224807238206267, + 0.685304003098281100392, + 0.689233281238557538017, + 0.693147180560117703862); + + constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( + 0.0, + -0.00000000000000543229938420049, + 0.00000000000000172745674997061, + -0.00000000000001323017818229233, + -0.00000000000001154527628289872, + -0.00000000000000466529469958300, + 0.00000000000005148849572685810, + -0.00000000000002532168943117445, + -0.00000000000005213620639136504, + -0.00000000000001819506003016881, + 0.00000000000006329065958724544, + 0.00000000000008614512936087814, + -0.00000000000007355770219435028, + 0.00000000000009638067658552277, + 0.00000000000007598636597194141, + 0.00000000000002579999128306990, + -0.00000000000004654729747598444, + -0.00000000000007556920687451336, + 0.00000000000010195735223708472, + -0.00000000000017319034406422306, + -0.00000000000007718001336828098, + 0.00000000000010980754099855238, + -0.00000000000002047235780046195, + -0.00000000000008372091099235912, + 0.00000000000014088127937111135, + 0.00000000000012869017157588257, + 0.00000000000017788850778198106, + 0.00000000000006440856150696891, + 0.00000000000016132822667240822, + -0.00000000000007540916511956188, + -0.00000000000000036507188831790, + 0.00000000000009120937249914984, + 0.00000000000018567570959796010, + -0.00000000000003149265065191483, + -0.00000000000009309459495196889, + 0.00000000000017914338601329117, + -0.00000000000001302979717330866, + 0.00000000000023097385217586939, + 0.00000000000023999540484211737, + 0.00000000000015393776174455408, + -0.00000000000036870428315837678, + 0.00000000000036920375082080089, + -0.00000000000009383417223663699, + 0.00000000000009433398189512690, + 0.00000000000041481318704258568, + -0.00000000000003792316480209314, + 0.00000000000008403156304792424, + -0.00000000000034262934348285429, + 0.00000000000043712191957429145, + -0.00000000000010475750058776541, + -0.00000000000011118671389559323, + 0.00000000000037549577257259853, + 0.00000000000013912841212197565, + 0.00000000000010775743037572640, + 0.00000000000029391859187648000, + -0.00000000000042790509060060774, + 0.00000000000022774076114039555, + 0.00000000000010849569622967912, + -0.00000000000023073801945705758, + 0.00000000000015761203773969435, + 0.00000000000003345710269544082, + -0.00000000000041525158063436123, + 0.00000000000032655698896907146, + -0.00000000000044704265010452446, + 0.00000000000034527647952039772, + -0.00000000000007048962392109746, + 0.00000000000011776978751369214, + -0.00000000000010774341461609578, + 0.00000000000021863343293215910, + 0.00000000000024132639491333131, + 0.00000000000039057462209830700, + -0.00000000000026570679203560751, + 0.00000000000037135141919592021, + -0.00000000000017166921336082431, + -0.00000000000028658285157914353, + -0.00000000000023812542263446809, + 0.00000000000006576659768580062, + -0.00000000000028210143846181267, + 0.00000000000010701931762114254, + 0.00000000000018119346366441110, + 0.00000000000009840465278232627, + -0.00000000000033149150282752542, + -0.00000000000018302857356041668, + -0.00000000000016207400156744949, + 0.00000000000048303314949553201, + -0.00000000000071560553172382115, + 0.00000000000088821239518571855, + -0.00000000000030900580513238244, + -0.00000000000061076551972851496, + 0.00000000000035659969663347830, + 0.00000000000035782396591276383, + -0.00000000000046226087001544578, + 0.00000000000062279762917225156, + 0.00000000000072838947272065741, + 0.00000000000026809646615211673, + -0.00000000000010960825046059278, + 0.00000000000002311949383800537, + -0.00000000000058469058005299247, + -0.00000000000002103748251144494, + -0.00000000000023323182945587408, + -0.00000000000042333694288141916, + -0.00000000000043933937969737844, + 0.00000000000041341647073835565, + 0.00000000000006841763641591466, + 0.00000000000047585534004430641, + 0.00000000000083679678674757695, + -0.00000000000085763734646658640, + 0.00000000000021913281229340092, + -0.00000000000062242842536431148, + -0.00000000000010983594325438430, + 0.00000000000065310431377633651, + -0.00000000000047580199021710769, + -0.00000000000037854251265457040, + 0.00000000000040939233218678664, + 0.00000000000087424383914858291, + 0.00000000000025218188456842882, + -0.00000000000003608131360422557, + -0.00000000000050518555924280902, + 0.00000000000078699403323355317, + -0.00000000000067020876961949060, + 0.00000000000016108575753932458, + 0.00000000000058527188436251509, + -0.00000000000035246757297904791, + -0.00000000000018372084495629058, + 0.00000000000088606689813494916, + 0.00000000000066486268071468700, + 0.00000000000063831615170646519, + 0.00000000000025144230728376072, + -0.00000000000017239444525614834); + + variable M, J:INTEGER; + variable F1, F2, G, Q, U, U2, V: REAL; + variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs + variable ONE: REAL := 1.0; --Made variable so no constant folding occurs + + -- double logb(), ldexp(); + + variable U1:REAL; + + begin + + -- Check validity of argument + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = MATH_E ) then + return 1.0; + end if; + + -- Argument reduction: 1 <= g < 2; x/2^m = g; + -- y = F*(1 + f/F) for |f| <= 2^-8 + + M := ILOGB(X); + G := LDEXP(X, -M); + J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding + F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] + F2 := G - F1; + + -- Approximate expansion for log(1+f2/F1) ~= u + q + G := 1.0/(2.0*F1+F2); + U := 2.0*F2*G; + V := U*U; + Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); + + -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, + -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. + -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. + -- + if ( J /= 0 or M /= 0) then + U1 := U + 513.0; + U1 := U1 - 513.0; + + -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero + -- u1 = u to 24 bits. + -- + else + U1 := U; + --TRUNC(U1); --In c this is u1 = (double) (float) (u1) + end if; + + U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; + -- u1 + u2 = 2f/(2F+f) to extra precision. + + -- log(x) = log(2^m*F1*(1+f2/F1)) = + -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); + -- (exact) + (tiny) + + U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact + U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny + U2 := U2 + LOGF_TAIL(N)*REAL(M); + return (U1 + U2); + end LOG; + + + function LOG2 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG2(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 2.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG2_OF_E*LOG(X) ); + end LOG2; + + + function LOG10 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG10(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 10.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG10_OF_E*LOG(X) ); + end LOG10; + + + function LOG (X: in REAL; BASE: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + if ( BASE <= 0.0 or BASE = 1.0 ) then + assert FALSE + report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = BASE ) then + return 1.0; + end if; + + -- Compute value for general case + return ( LOG(X)/LOG(BASE)); + end LOG; + + + function SIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) SIN(-X) = -SIN(X) + -- b) SIN(X) = X if ABS(X) < EPS + -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS + -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) + -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS + -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in SIN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then + return 0.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 then + if NEGATIVE then + return -1.0; + else + return 1.0; + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + if NEGATIVE then + return 1.0; + else + return -1.0; + end if; + end if; + + if XLOCAL < EPS then + if NEGATIVE then + return -XLOCAL; + else + return XLOCAL; + end if; + else + if XLOCAL < BASE_EPS then + TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_2_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + -- Compute value for general cases + if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then + VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); + end if; + + N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); + case QUADRANT( N mod 4) is + when 0 => + VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); + when 1 => + VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, + ROTATION)(0); + when 2 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); + when 3 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, + ROTATION)(0); + end case; + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end SIN; + + + function COS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) COS(-X) = COS(X) + -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) + -- c) COS(MATH_PI + X) = -COS(X) + -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS + -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in COS(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then + return 1.0; + end if; + + if XLOCAL = MATH_PI then + return -1.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then + return 0.0; + end if; + + TEMP := ABS(XLOCAL); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS(XLOCAL -MATH_2_PI); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS (XLOCAL - MATH_PI); + if TEMP < EPS then + return (-1.0 + 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + -- Compute value for general cases + return SIN(MATH_PI_OVER_2 - XLOCAL); + end COS; + + function TAN (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) TAN(0.0) = 0.0 + -- b) TAN(-X) = -TAN(X) + -- c) Returns REAL'LOW on error if X < 0.0 + -- d) Returns REAL'HIGH on error if X > 0.0 + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X) ; + variable VALUE: REAL; + variable TEMP : REAL; + + begin + -- Make 0.0 <= XLOCAL <= MATH_2_PI + if XLOCAL > MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in TAN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Check validity of argument + if XLOCAL = MATH_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'LOW); + else + return(REAL'HIGH); + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'HIGH); + else + return(REAL'LOW); + end if; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_PI then + return 0.0; + end if; + + -- Compute value for general cases + VALUE := SIN(XLOCAL)/COS(XLOCAL); + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TAN; + + function ARCSIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCSIN(-X) = -ARCSIN(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of arguments + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCSIN(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + elsif XLOCAL = 1.0 then + if NEGATIVE then + return -MATH_PI_OVER_2; + else + return MATH_PI_OVER_2; + end if; + end if; + + -- Compute value for general cases + if XLOCAL < 0.9 then + VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCSIN; + + function ARCCOS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of argument + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCCOS(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + elsif X = 0.0 then + return MATH_PI_OVER_2; + elsif X = -1.0 then + return MATH_PI; + end if; + + -- Compute value for general cases + if XLOCAL > 0.9 then + VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); + end if; + + + if NEGATIVE then + VALUE := MATH_PI - VALUE; + end if; + + return VALUE; + end ARCCOS; + + + function ARCTAN (Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCTAN(-Y) = -ARCTAN(Y) + -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 + -- c) ARCTAN(Y) = Y for |Y| < EPS + + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; + + variable NEGATIVE : BOOLEAN := Y < 0.0; + variable RECIPROCAL : BOOLEAN; + variable YLOCAL : REAL := ABS(Y); + variable VALUE : REAL; + + begin + -- Make argument |Y| <=1.0 + if YLOCAL > 1.0 then + YLOCAL := 1.0/YLOCAL; + RECIPROCAL := TRUE; + else + RECIPROCAL := FALSE; + end if; + + -- Compute value for special cases + if YLOCAL = 0.0 then + if RECIPROCAL then + if NEGATIVE then + return (-MATH_PI_OVER_2); + else + return (MATH_PI_OVER_2); + end if; + else + return 0.0; + end if; + end if; + + if YLOCAL < EPS then + if NEGATIVE then + if RECIPROCAL then + return (-MATH_PI_OVER_2 + YLOCAL); + else + return -YLOCAL; + end if; + else + if RECIPROCAL then + return (MATH_PI_OVER_2 - YLOCAL); + else + return YLOCAL; + end if; + end if; + end if; + + -- Compute value for general cases + VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); + + if RECIPROCAL then + VALUE := MATH_PI_OVER_2 - VALUE; + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function ARCTAN (Y : in REAL; X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable YLOCAL : REAL; + variable VALUE : REAL; + begin + + -- Check validity of arguments + if (Y = 0.0 and X = 0.0 ) then + assert FALSE report + "ARCTAN(0.0, 0.0) is undetermined" + severity ERROR; + return 0.0; + end if; + + -- Compute value for special cases + if Y = 0.0 then + if X > 0.0 then + return 0.0; + else + return MATH_PI; + end if; + end if; + + if X = 0.0 then + if Y > 0.0 then + return MATH_PI_OVER_2; + else + return -MATH_PI_OVER_2; + end if; + end if; + + + -- Compute value for general cases + YLOCAL := ABS(Y/X); + + VALUE := ARCTAN(YLOCAL); + + if X < 0.0 then + VALUE := MATH_PI - VALUE; + end if; + + if Y < 0.0 then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function SINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/2.0 + -- b) SINH(-X) = SINH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)*0.5; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end SINH; + + function COSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) + EXP(-X))/2.0 + -- b) COSH(-X) = COSH(X) + + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 1.0; + end if; + + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP + 1.0/TEMP)*0.5; + + return VALUE; + end COSH; + + function TANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) + -- b) TANH(-X) = -TANH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TANH; + + function ARCSINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X + 1.0)) + + begin + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X + 1.0)) ); + end ARCSINH; + + + + function ARCCOSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 + -- b) Returns X on error + + begin + -- Check validity of arguments + if X < 1.0 then + assert FALSE + report "X < 1.0 in ARCCOSH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X - 1.0))); + end ARCCOSH; + + function ARCTANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 + -- b) Returns X on error + begin + -- Check validity of arguments + if ABS(X) >= 1.0 then + assert FALSE + report "ABS(X) >= 1.0 in ARCTANH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); + end ARCTANH; + +end MATH_REAL; diff --git a/CPLD/LCMXO2-1200HC/generate_core.tcl b/CPLD/LCMXO2-1200HC/generate_core.tcl new file mode 100644 index 0000000..47f429b --- /dev/null +++ b/CPLD/LCMXO2-1200HC/generate_core.tcl @@ -0,0 +1,100 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +proc GetCmdLine {lpcfile} { + global Para + + if [catch {open $lpcfile r} fileid] { + puts "Cannot open $para_file file!" + exit -1 + } + + seek $fileid 0 start + set default_match 0 + while {[gets $fileid line] >= 0} { + if {[string first "\[Command\]" $line] == 0} { + set default_match 1 + continue + } + if {[string first "\[" $line] == 0} { + set default_match 0 + } + if {$default_match == 1} { + if [regexp {([^=]*)=(.*)} $line match parameter value] { + if [regexp {([ |\t]*;)} $parameter match] {continue} + if [regexp {(.*)[ |\t]*;} $value match temp] { + set Para($parameter) $temp + } else { + set Para($parameter) $value + } + } + } + } + set default_match 0 + close $fileid + + return $Para(cmd_line) +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" + +set scuba "$Para(FPGAPath)/scuba" +set modulename "REFB" +set lang "verilog" +set lpcfile "$Para(sbp_path)/$modulename.lpc" +set arch "xo2c00" +set cmd_line [GetCmdLine $lpcfile] +set fdcfile "$Para(sbp_path)/$modulename.fdc" +if {[file exists $fdcfile] == 0} { + append scuba " " $cmd_line +} else { + append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" +} +set Para(result) [catch {eval exec "$scuba"} msg] +#puts $msg diff --git a/CPLD/LCMXO2-1200HC/generate_ngd.tcl b/CPLD/LCMXO2-1200HC/generate_ngd.tcl new file mode 100644 index 0000000..fcdb02c --- /dev/null +++ b/CPLD/LCMXO2-1200HC/generate_ngd.tcl @@ -0,0 +1,74 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" +set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" + +set Para(ModuleName) "REFB" +set Para(Module) "EFB" +set Para(libname) machxo2 +set Para(arch_name) xo2c00 +set Para(PartType) "LCMXO2-1200HC" + +set Para(tech_syn) machxo2 +set Para(tech_cae) machxo2 +set Para(Package) "TQFP100" +set Para(SpeedGrade) "4" +set Para(FMax) "100" +set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" + +#edif2ngd +set edif2ngd "$Para(FPGAPath)/edif2ngd" +set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] +#puts $msg + +#ngdbuild +set ngdbuild "$Para(FPGAPath)/ngdbuild" +set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] +#puts $msg diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt new file mode 100644 index 0000000..0f72508 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.alt @@ -0,0 +1,78 @@ +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Thu Sep 21 05:35:26 2023 * +NOTE DESIGN NAME: RAM2E * +NOTE DEVICE NAME: LCMXO2-1200HC-4TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[0] : 36 : inout * +NOTE PINS LED : 35 : out * +NOTE PINS C14M : 62 : in * +NOTE PINS DQMH : 49 : out * +NOTE PINS DQML : 48 : out * +NOTE PINS RD[7] : 43 : inout * +NOTE PINS RD[6] : 42 : inout * +NOTE PINS RD[5] : 41 : inout * +NOTE PINS RD[4] : 40 : inout * +NOTE PINS RD[3] : 39 : inout * +NOTE PINS RD[2] : 38 : inout * +NOTE PINS RD[1] : 37 : inout * +NOTE PINS RA[11] : 59 : out * +NOTE PINS RA[10] : 64 : out * +NOTE PINS RA[9] : 63 : out * +NOTE PINS RA[8] : 65 : out * +NOTE PINS RA[7] : 67 : out * +NOTE PINS RA[6] : 69 : out * +NOTE PINS RA[5] : 71 : out * +NOTE PINS RA[4] : 75 : out * +NOTE PINS RA[3] : 74 : out * +NOTE PINS RA[2] : 70 : out * +NOTE PINS RA[1] : 68 : out * +NOTE PINS RA[0] : 66 : out * +NOTE PINS BA[1] : 60 : out * +NOTE PINS BA[0] : 58 : out * +NOTE PINS nRWE : 51 : out * +NOTE PINS nCAS : 52 : out * +NOTE PINS nRAS : 54 : out * +NOTE PINS nCS : 57 : out * +NOTE PINS CKE : 53 : out * +NOTE PINS nVOE : 10 : out * +NOTE PINS Vout[7] : 12 : out * +NOTE PINS Vout[6] : 14 : out * +NOTE PINS Vout[5] : 16 : out * +NOTE PINS Vout[4] : 19 : out * +NOTE PINS Vout[3] : 13 : out * +NOTE PINS Vout[2] : 17 : out * +NOTE PINS Vout[1] : 15 : out * +NOTE PINS Vout[0] : 18 : out * +NOTE PINS nDOE : 20 : out * +NOTE PINS Dout[7] : 32 : out * +NOTE PINS Dout[6] : 31 : out * +NOTE PINS Dout[5] : 21 : out * +NOTE PINS Dout[4] : 24 : out * +NOTE PINS Dout[3] : 28 : out * +NOTE PINS Dout[2] : 25 : out * +NOTE PINS Dout[1] : 27 : out * +NOTE PINS Dout[0] : 30 : out * +NOTE PINS Din[7] : 87 : in * +NOTE PINS Din[6] : 88 : in * +NOTE PINS Din[5] : 99 : in * +NOTE PINS Din[4] : 1 : in * +NOTE PINS Din[3] : 9 : in * +NOTE PINS Din[2] : 98 : in * +NOTE PINS Din[1] : 97 : in * +NOTE PINS Din[0] : 96 : in * +NOTE PINS Ain[7] : 8 : in * +NOTE PINS Ain[6] : 86 : in * +NOTE PINS Ain[5] : 84 : in * +NOTE PINS Ain[4] : 78 : in * +NOTE PINS Ain[3] : 4 : in * +NOTE PINS Ain[2] : 7 : in * +NOTE PINS Ain[1] : 2 : in * +NOTE PINS Ain[0] : 3 : in * +NOTE PINS nC07X : 34 : in * +NOTE PINS nEN80 : 82 : in * +NOTE PINS nWE80 : 83 : in * +NOTE PINS nWE : 29 : in * +NOTE PINS PHI1 : 85 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr new file mode 100644 index 0000000..717f690 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.areasrr @@ -0,0 +1,41 @@ +---------------------------------------------------------------------- +Report for cell RAM2E.verilog + +Register bits: 111 of 1280 (9%) +PIC Latch: 0 +I/O cells: 70 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2D 9 100.0 + EFB 1 100.0 + FD1P3AX 48 100.0 + FD1P3IX 1 100.0 + FD1S3AX 22 100.0 + FD1S3IX 4 100.0 + GSR 1 100.0 + IB 22 100.0 + IFS1P3DX 1 100.0 + INV 1 100.0 + OB 40 100.0 + OFS1P3BX 6 100.0 + OFS1P3DX 27 100.0 + OFS1P3IX 2 100.0 + ORCALUT4 221 100.0 + PUR 1 100.0 + VHI 2 100.0 + VLO 2 100.0 +SUB MODULES + REFB 1 100.0 + + TOTAL 420 +---------------------------------------------------------------------- +Report for cell REFB.netlist + Instance path: ufmefb + Cell usage: + cell count Res Usage(%) + EFB 1 100.0 + VHI 1 50.0 + VLO 1 50.0 + + TOTAL 3 diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn new file mode 100644 index 0000000..0881a22 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bgn @@ -0,0 +1,86 @@ +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Thu Sep 21 05:35:21 2023 + + +Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf + +Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd. +Design name: RAM2E +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2E_LCMXO2_1200HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream Status: Final Version 1.95. + +Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.jed". + +=========== +UFM Summary. +=========== +UFM Size: 511 Pages (128*511 Bits). +UFM Utilization: General Purpose Flash Memory. + +Available General Purpose Flash Memory: 511 Pages (Page 0 to Page 510). +Initialized UFM Pages: 321 Pages (Page 190 to Page 510). + +Total CPU Time: 4 secs +Total REAL Time: 5 secs +Peak Memory Usage: 275 MB diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bit b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1.bit new file mode 100644 index 0000000000000000000000000000000000000000..47ca44149c567b7f41421f81f15a82f1a873b147 GIT binary patch literal 9265 zcmbta3s@6Z+CDQ3IKdQiLj!Ad5(DAlB>}X6r~?TxV7Sv(t*r^5K-UX}*y3+1LkuBU zRFF#nsYbL)Ti04^SGT$~Dq6Hu0o`4@YunVKwcY+JRkvDi`OjPe0srpvKhOX9WWMjb z-+Ru?ob#RUoHOVK29w!boWG37S+=q`fAy+@HTmY%rG#d6Y02tRleu{HDk7=aTxKp^ zW?BiJTUJ^Ik$A!*+G5j6SceFk6*Dcb*c?toPgh4xS5J?b83Tr@5jkd)c}-b7p(|cx zT0wA)5bEi1Gl6zlS#jYiVwGv-vUnmpF)b>2sX>#rFe7TII!dL|YnB$TELowRzAC=} zB$nnE6`Pmko7a>=Zu#n{e3c4hno7;_1Y2bqTV+~IZk8@n4V_w(88UN=*1(r5A)?fT zYG!=&%y{)PM3gEj8f3424L($KbTrVcUI8t&DptijH3VnI&5BWh>}95cJX8Mf*%!`O zz8vH%%U@GkY+gHz48Nu(TN6*H%99ggB zLz{#@NOS9;KH@^sp!yBLNC4;>UV>2oD7?z7Ipqn&8$eJOv*K)qxf}-#QWl2r!I9LIJAK&iojQ&d40; z0D^jSVwe|J2Okm5wCG7W<%PCDTgS`uAc%mq=O&h;z+658I;&AhsGk1zJ-8_&U;JY11P%BLFznuJx2z4LbuP^OA-@ z8PW~FrvlI}13q58FSdkJNl1bVBhv|Bf2;e}Pz3<=06w&a*e3+B;S{oP$dd{XEQb=L z3e$m)+`4!O_cBHf4~A0!pn_Rgju!=p52kd$8(>Cd0pW!U;gbW*>4gAvr$R(QAlDl# z%JID~q0wi#-k8pKv3x}fG)$C+gBcW6oa8GQYv>XVvU$B7+v`JBH1uqNbI1dHJJ0}3 z{lXpE<9$!Td8_3qQPTD)iO`{P3aQ~LKyV9N*!Xwps2WJLf0O<=J=QAcFgXIon;>zn zKDT<*paB$-S-()7DLgPtW-O&ac}X-pn4CA}T~lSZp9Gdn6bC^S0nj6v^If6Bb1XJ? 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BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Sep 21 05:35:17 2023
+
+
+Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC -w -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
+
+Loading design for application Bitgen from file RAM2E_LCMXO2_1200HC_impl1.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2E_LCMXO2_1200HC_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2E_LCMXO2_1200HC_impl1.bit".
+Total CPU Time: 4 secs 
+Total REAL Time: 4 secs 
+Peak Memory Usage: 275 MB
+
+
+
+

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+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt new file mode 100644 index 0000000..723be7e --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_cck.rpt @@ -0,0 +1,152 @@ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 + +# Written on Thu Sep 21 05:34:38 2023 + +##### DESIGN INFO ####################################################### + +Top View: "RAM2E" +Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc" + + + + +##### SUMMARY ############################################################ + +Found 0 issues in 0 out of 1 constraints + + +##### DETAILS ############################################################ + + + +Clock Relationships +******************* + +Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise +----------------------------------------------------------------------------------------------------------------------------------- +System C14M | 69.841 | No paths | No paths | No paths +C14M System | 69.841 | No paths | No paths | No paths +C14M C14M | 69.841 | No paths | 34.920 | No paths +=================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + +Unconstrained Start/End Points +****************************** + +p:Ain[0] +p:Ain[1] +p:Ain[2] +p:Ain[3] +p:Ain[4] +p:Ain[5] +p:Ain[6] +p:Ain[7] +p:BA[0] +p:BA[1] +p:CKE +p:DQMH +p:DQML +p:Din[0] +p:Din[1] +p:Din[2] +p:Din[3] +p:Din[4] +p:Din[5] +p:Din[6] +p:Din[7] +p:Dout[0] +p:Dout[1] +p:Dout[2] +p:Dout[3] +p:Dout[4] +p:Dout[5] +p:Dout[6] +p:Dout[7] +p:LED +p:PHI1 +p:RA[0] +p:RA[1] +p:RA[2] +p:RA[3] +p:RA[4] +p:RA[5] +p:RA[6] +p:RA[7] +p:RA[8] +p:RA[9] +p:RA[10] +p:RA[11] +p:RD[0] (bidir end point) +p:RD[0] (bidir start point) +p:RD[1] (bidir end point) +p:RD[1] (bidir start point) +p:RD[2] (bidir end point) +p:RD[2] (bidir start point) +p:RD[3] (bidir end point) +p:RD[3] (bidir start point) +p:RD[4] (bidir end point) +p:RD[4] (bidir start point) +p:RD[5] (bidir end point) +p:RD[5] (bidir start point) +p:RD[6] (bidir end point) +p:RD[6] (bidir start point) +p:RD[7] (bidir end point) +p:RD[7] (bidir start point) +p:Vout[0] +p:Vout[1] +p:Vout[2] +p:Vout[3] +p:Vout[4] +p:Vout[5] +p:Vout[6] +p:Vout[7] +p:nC07X +p:nCAS +p:nCS +p:nDOE +p:nEN80 +p:nRAS +p:nRWE +p:nVOE +p:nWE +p:nWE80 + + +Inapplicable constraints +************************ + +(none) + + +Applicable constraints with issues +********************************** + +(none) + + +Constraints with matching wildcard expressions +********************************************** + +(none) + + +Library Report +************** + + +# End of Constraint Checker Report diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_iotiming.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_iotiming.html new file mode 100644 index 0000000..bdf948f --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_iotiming.html @@ -0,0 +1,185 @@ + +I/O Timing Report + + +
I/O Timing Report
+Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2E
+// Package: TQFP100
+// ncd File: ram2e_lcmxo2_1200hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Thu Sep 21 05:35:11 2023
+// M: Minimum Performance Grade
+// iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port   Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+Ain[0] C14M  R    -0.231      M       2.350     4
+Ain[1] C14M  R     1.429      4       0.543     4
+Ain[2] C14M  R     1.518      4       0.412     4
+Ain[3] C14M  R    -0.231      M       2.350     4
+Ain[4] C14M  R     0.212      4       1.560     4
+Ain[5] C14M  R     0.742      4       1.110     4
+Ain[6] C14M  R     0.469      4       1.329     4
+Ain[7] C14M  R     1.416      4       0.531     4
+Din[0] C14M  R     8.327      4       1.958     4
+Din[1] C14M  R     5.826      4       2.521     4
+Din[2] C14M  R     6.539      4       2.135     4
+Din[3] C14M  R     5.849      4       2.648     4
+Din[4] C14M  R     7.061      4       2.095     4
+Din[5] C14M  R     6.295      4       2.894     4
+Din[6] C14M  R     4.991      4       2.892     4
+Din[7] C14M  R     6.416      4       2.971     4
+PHI1   C14M  R     1.151      4       4.842     4
+RD[0]  C14M  F    -0.266      M       3.107     4
+RD[1]  C14M  F    -0.248      M       3.183     4
+RD[2]  C14M  F    -0.105      M       2.610     4
+RD[3]  C14M  F    -0.243      M       3.107     4
+RD[4]  C14M  F     0.103      4       2.201     4
+RD[5]  C14M  F    -0.092      M       2.192     4
+RD[6]  C14M  F    -0.084      M       1.756     4
+RD[7]  C14M  F    -0.092      M       2.661     4
+nC07X  C14M  R    -0.316      M       2.625     4
+nEN80  C14M  R     5.220      4       0.032     M
+nWE    C14M  R    -0.093      M       2.033     4
+nWE80  C14M  R     1.630      4       0.329     6
+
+
+// Clock to Output Delay
+
+Port    Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+BA[0]   C14M  R    10.424         4        3.355          M
+BA[1]   C14M  R    10.424         4        3.355          M
+CKE     C14M  R    10.424         4        3.355          M
+DQMH    C14M  R    10.404         4        3.362          M
+DQML    C14M  R    10.404         4        3.362          M
+Dout[0] C14M  F    10.750         4        3.634          M
+Dout[1] C14M  F    10.750         4        3.634          M
+Dout[2] C14M  F    10.739         4        3.628          M
+Dout[3] C14M  F    10.750         4        3.634          M
+Dout[4] C14M  F    10.739         4        3.628          M
+Dout[5] C14M  F    10.739         4        3.628          M
+Dout[6] C14M  F    10.750         4        3.634          M
+Dout[7] C14M  F    10.750         4        3.634          M
+LED     C14M  R    21.299         4        8.576          M
+RA[0]   C14M  R    12.236         4        3.758          M
+RA[10]  C14M  R    10.490         4        3.360          M
+RA[11]  C14M  R    10.424         4        3.355          M
+RA[1]   C14M  R    10.490         4        3.360          M
+RA[2]   C14M  R    10.490         4        3.360          M
+RA[3]   C14M  R    11.808         4        3.656          M
+RA[4]   C14M  R    10.490         4        3.360          M
+RA[5]   C14M  R    10.490         4        3.360          M
+RA[6]   C14M  R    10.490         4        3.360          M
+RA[7]   C14M  R    10.490         4        3.360          M
+RA[8]   C14M  R    10.490         4        3.360          M
+RA[9]   C14M  R    10.490         4        3.360          M
+Vout[0] C14M  F    11.348         4        3.872          M
+Vout[1] C14M  F    11.434         4        3.871          M
+Vout[2] C14M  F    11.348         4        3.872          M
+Vout[3] C14M  F    11.434         4        3.871          M
+Vout[4] C14M  F    11.348         4        3.872          M
+Vout[5] C14M  F    11.348         4        3.872          M
+Vout[6] C14M  F    11.434         4        3.871          M
+Vout[7] C14M  F    11.434         4        3.871          M
+nCAS    C14M  R    10.424         4        3.355          M
+nCS     C14M  R    10.424         4        3.355          M
+nDOE    C14M  R    14.217         4        4.353          M
+nRAS    C14M  R    10.424         4        3.355          M
+nRWE    C14M  R    10.424         4        3.355          M
+WARNING: you must also run trce with hold speed: 4
+WARNING: you must also run trce with hold speed: 6
+WARNING: you must also run trce with setup speed: M
+
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+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf new file mode 100644 index 0000000..865c239 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.sdf @@ -0,0 +1,4852 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2E") + (DATE "Thu Sep 21 05:34:51 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_10") + (INSTANCE SLICE_10) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_11") + (INSTANCE SLICE_11) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_12") + (INSTANCE SLICE_12) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_13") + (INSTANCE SLICE_13) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_14") + (INSTANCE SLICE_14) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_15") + (INSTANCE SLICE_15) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_16") + (INSTANCE SLICE_16) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 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Dout\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH IOLDO Dout1 (2293:2420:2548)(2293:2420:2548)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1__MGIOL") + (INSTANCE Dout\[1\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IOLDO (546:556:567)(546:556:567)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + (TIMINGCHECK + (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86)) + (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36)) + ) + ) + (CELL + (CELLTYPE "Dout_0_") + (INSTANCE Dout\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH IOLDO Dout0 (2293:2420:2548)(2293:2420:2548)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0__MGIOL") + (INSTANCE Dout\[0\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IOLDO (546:556:567)(546:556:567)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + (TIMINGCHECK + (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86)) + (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36)) + ) + ) + (CELL + (CELLTYPE "Din_7_") + (INSTANCE Din\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_7_") + (INSTANCE Ain\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain7 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain7) (3330:3330:3330)) + (WIDTH (negedge Ain7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_6_") + (INSTANCE Ain\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain6 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain6) (3330:3330:3330)) + (WIDTH (negedge Ain6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_5_") + (INSTANCE Ain\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain5 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain5) (3330:3330:3330)) + (WIDTH (negedge Ain5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_4_") + (INSTANCE Ain\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain4 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain4) (3330:3330:3330)) + (WIDTH (negedge Ain4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_3_") + (INSTANCE Ain\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain3 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain3) (3330:3330:3330)) + (WIDTH (negedge Ain3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_2_") + (INSTANCE Ain\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain2 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain2) (3330:3330:3330)) + (WIDTH (negedge Ain2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_1_") + (INSTANCE Ain\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain1) (3330:3330:3330)) + (WIDTH (negedge Ain1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_0_") + (INSTANCE Ain\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain0) (3330:3330:3330)) + (WIDTH (negedge Ain0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nC07X") + (INSTANCE nC07X_I) + (DELAY + (ABSOLUTE + (IOPATH nC07X PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nC07X) (3330:3330:3330)) + (WIDTH (negedge nC07X) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nEN80") + (INSTANCE nEN80_I) + (DELAY + (ABSOLUTE + (IOPATH nEN80 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nEN80) (3330:3330:3330)) + (WIDTH (negedge nEN80) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nWE80") + (INSTANCE nWE80_I) + (DELAY + (ABSOLUTE + (IOPATH nWE80 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nWE80) (3330:3330:3330)) + (WIDTH (negedge nWE80) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nWE") + (INSTANCE nWE_I) + (DELAY + (ABSOLUTE + (IOPATH nWE PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nWE) (3330:3330:3330)) + (WIDTH (negedge nWE) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "PHI1") + (INSTANCE PHI1_I) + (DELAY + (ABSOLUTE + (IOPATH PHI1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI1) (3330:3330:3330)) + (WIDTH (negedge PHI1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "PHI1_MGIOL") + (INSTANCE PHI1_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "EFB_Buffer_Block") + (INSTANCE ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20) + (DELAY + (ABSOLUTE + (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278)) + (IOPATH WBCLKIin WBDATO1out (947:3204:5461)(947:3204:5461)) + (IOPATH WBCLKIin WBDATO2out (955:3211:5468)(955:3211:5468)) + (IOPATH WBCLKIin WBDATO3out (910:3173:5436)(910:3173:5436)) + (IOPATH WBCLKIin WBDATO4out (944:3217:5491)(944:3217:5491)) + (IOPATH WBCLKIin WBDATO5out (917:3672:6428)(917:3672:6428)) + (IOPATH WBCLKIin WBDATO6out (926:3191:5457)(926:3191:5457)) + (IOPATH WBCLKIin WBDATO7out (939:3201:5464)(939:3201:5464)) + (IOPATH WBCLKIin WBACKOout (903:1623:2343)(903:1623:2343)) + ) + ) + (TIMINGCHECK + (SETUPHOLD WBRSTIin (posedge WBCLKIin) (3138:3170:3203)(-3138:-1966:-794)) + (SETUPHOLD WBCYCIin (posedge WBCLKIin) (2616:2649:2682)(-2616:-1558:-501)) + (SETUPHOLD WBSTBIin (posedge WBCLKIin) (2605:2637:2670)(-2605:-1494:-384)) + (SETUPHOLD WBWEIin (posedge WBCLKIin) (1409:1442:1475)(-1409:-837:-266)) + (SETUPHOLD WBADRI0in (posedge WBCLKIin) (2058:2123:2188)(-2058:-1191:-324)) + (SETUPHOLD WBADRI1in (posedge WBCLKIin) (2068:2104:2140)(-2068:-1234:-401)) + (SETUPHOLD WBADRI2in (posedge WBCLKIin) (1928:1993:2058)(-1928:-1110:-292)) + (SETUPHOLD WBADRI3in (posedge WBCLKIin) (2167:2196:2226)(-2167:-1264:-361)) + (SETUPHOLD WBADRI4in (posedge WBCLKIin) (2072:2101:2130)(-2072:-1198:-324)) + (SETUPHOLD WBADRI5in (posedge WBCLKIin) (1611:1640:1670)(-1611:-950:-289)) + (SETUPHOLD WBADRI6in (posedge WBCLKIin) (2532:2564:2597)(-2532:-1380:-229)) + (SETUPHOLD WBADRI7in (posedge WBCLKIin) (2519:2551:2584)(-2519:-1377:-235)) + (SETUPHOLD WBDATI0in (posedge WBCLKIin) (1057:1262:1467)(-1037:-712:-388)) + (SETUPHOLD WBDATI1in (posedge WBCLKIin) (1114:1338:1563)(-1108:-785:-462)) + (SETUPHOLD WBDATI2in (posedge WBCLKIin) (916:1076:1237)(-912:-636:-360)) + (SETUPHOLD WBDATI3in (posedge WBCLKIin) (1145:1359:1573)(-1115:-782:-449)) + (SETUPHOLD WBDATI4in (posedge WBCLKIin) (1192:1400:1609)(-1176:-820:-464)) + (SETUPHOLD WBDATI5in (posedge WBCLKIin) (1027:1222:1418)(-1000:-706:-413)) + (SETUPHOLD WBDATI6in (posedge WBCLKIin) (1034:1248:1463)(-1034:-756:-479)) + (SETUPHOLD WBDATI7in (posedge WBCLKIin) (528:614:701)(-528:-398:-268)) + ) + (TIMINGCHECK + (WIDTH (posedge WBCLKIin) (4887:4887:4887)) + (WIDTH (negedge WBCLKIin) (4887:4887:4887)) + ) + ) + (CELL + (CELLTYPE "RAM2E") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_39/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_52/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_75/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_119/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_11/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_13/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_15/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_16/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_17/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_27/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_28/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_39/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_46/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI DQMH_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI DQML_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[11\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[10\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[9\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[8\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[7\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[6\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[5\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[4\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[2\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI BA\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI BA\[0\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI nRWE_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI nCAS_MGIOL/CLK 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(INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[9\]_MGIOL/IOLDO RA\[9\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[8\]_MGIOL/IOLDO RA\[8\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[7\]_MGIOL/IOLDO RA\[7\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[6\]_MGIOL/IOLDO RA\[6\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[5\]_MGIOL/IOLDO RA\[5\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[4\]_MGIOL/IOLDO RA\[4\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[2\]_MGIOL/IOLDO RA\[2\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[1\]_MGIOL/IOLDO RA\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nCAS_MGIOL/IOLDO nCAS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRAS_MGIOL/IOLDO nRAS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nCS_MGIOL/IOLDO nCS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT CKE_MGIOL/IOLDO CKE_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[4\]_MGIOL/IOLDO Vout\[4\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[3\]_MGIOL/IOLDO Vout\[3\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[7\]_MGIOL/IOLDO Dout\[7\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[6\]_MGIOL/IOLDO Dout\[6\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[5\]_MGIOL/IOLDO Dout\[5\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[4\]_MGIOL/IOLDO Dout\[4\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[3\]_MGIOL/IOLDO Dout\[3\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[2\]_MGIOL/IOLDO Dout\[2\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[1\]_MGIOL/IOLDO Dout\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[0\]_MGIOL/IOLDO Dout\[0\]_I/IOLDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo new file mode 100644 index 0000000..2a9bbde --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mapvo.vo @@ -0,0 +1,5908 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2E_LCMXO2_1200HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd +// Netlist created on Thu Sep 21 05:34:46 2023 +// Netlist written on Thu Sep 21 05:34:51 2023 +// Design is for device LCMXO2-1200HC +// Design is for package TQFP100 +// Design is for performance grade 4 + +`timescale 1 ns / 1 ps + +module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, + Vout, nVOE, CKE, nCS, nRAS, nCAS, nRWE, BA, RA, RD, DQML, DQMH ); + input C14M, PHI1, nWE, nWE80, nEN80, nC07X; + input [7:0] Ain; + input [7:0] Din; + output LED; + output [7:0] Dout; + output nDOE; + output [7:0] Vout; + output nVOE, CKE, nCS, nRAS, nCAS, nRWE; + output [1:0] BA; + output [11:0] RA; + output DQML, DQMH; + inout [7:0] RD; + wire \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , + \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , + \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , + \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , + \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , + \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , + \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , Ready, + PHI1reg, PHI1_c, RWSel, CO0_1, \CmdTout_3[0] , N_576_i, S_1, \CS[0] , + N_461, \S_RNII9DO1_0[1] , \CS[1] , N_511_i, N_504_i, + un1_CS_0_sqmuxa_i, N_637, \CS[2] , N_510_i, \Din_c[3] , \Din_c[2] , + \Din_c[0] , N_643, CmdBitbangMXO2_4_u_0_0_a2_0_1, CmdBitbangMXO2, + CmdBitbangMXO2_4, \Din_c[7] , \Din_c[5] , N_629, CmdExecMXO2, + CmdExecMXO2_4, N_466, N_478, \Din_c[4] , \Din_c[1] , N_476, + CmdLEDGet_4_u_0_0_a2_0_2, CmdLEDGet, CmdLEDGet_4, N_626, N_605, + CmdLEDSet, CmdLEDSet_4, CmdRWMaskSet, CmdRWMaskSet_4, N_401, + CmdSetRWBankFFLED, CmdSetRWBankFFLED_4, N_474, + CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0, CmdSetRWBankFFMXO2, + CmdSetRWBankFFMXO2_4, \CmdTout[1] , \CmdTout[2] , N_556_i, N_555_i, + \S[0] , \S[1] , \S[2] , \S[3] , N_6_i, DOEEN, \Ain_c[1] , + \wb_dato[0] , LEDEN_RNO, \un1_LEDEN_0_sqmuxa_1_i_0[0] , LEDEN, + N_558_i, \Ain_c[3] , \Ain_c[0] , N_552_i, N_127_i, \S_RNII9DO1_1[1] , + \RA_c[0] , \RA_c[3] , \RWMask[1] , N_591, \RWMask[0] , \RWBank_5[1] , + \RWBank_5[0] , LEDEN13, \RWBank[0] , \RWBank[1] , \RWMask[3] , + \RWMask[2] , \RWBank_5[3] , \RWBank_5[2] , \RWBank[2] , \RWBank[3] , + \RWMask[5] , \RWMask[4] , \RWBank_5[5] , \RWBank_5[4] , \RWBank[4] , + \RWBank[5] , \RWMask[7] , \RWMask[6] , \Din_c[6] , \RWBank_5[7] , + \RWBank_5[6] , \RWBank[6] , \RWBank[7] , \wb_dato[1] , N_291_i, + N_292_i, N_88, \wb_dato[3] , \wb_dato[2] , N_289_i, N_290_i, + \wb_dato[5] , \wb_dato[4] , N_287_i, N_288_i, \wb_dato[7] , + \wb_dato[6] , N_285, N_286_i, nWE_c, nEN80_c, nC07X_c, RWSel_2, nCS61, + nDOE_c, Ready_0_sqmuxa_0_a2_6_a2_4, N_489, Ready_0_sqmuxa, N_876_0, + wb_reqc_1, N_575, N_572, \S_s_0_1[0] , N_133_i, \S_s_0[0] , N_129_i, + N_131_i, wb_adr_7_5_214_0_1, N_388, \wb_adr_7_0_4[0] , N_642, N_376, + \wb_adr_RNO[1] , \wb_adr_7[0] , \un1_wb_adr_0_sqmuxa_2_i[0] , + \wb_adr[0] , \wb_adr[1] , N_41_i, N_43_i, \wb_adr[2] , \wb_adr[3] , + N_295, N_294, \wb_adr[4] , \wb_adr[5] , N_39_i, N_296, \wb_adr[6] , + \wb_adr[7] , wb_ack, N_300, N_395, wb_cyc_stb_RNO, N_104, wb_cyc_stb, + \wb_dati_7_0_0[1] , N_627, N_621, N_336, \wb_dati_7_0_a2_1[0] , N_484, + \wb_dati_7[1] , \wb_dati_7[0] , \wb_dati[0] , \wb_dati[1] , + \wb_dati_7_0_2[3] , \wb_dati_7_0_0[3] , \wb_dati_7_0_o2_0[2] , N_345, + \wb_dati_7[3] , \wb_dati_7[2] , \wb_dati[2] , \wb_dati[3] , + \wb_dati_7_0_0[4] , N_349, N_346, \wb_dati_7[5] , \wb_dati_7[4] , + \wb_dati[4] , \wb_dati[5] , \wb_dati_7_0_0[7] , \wb_dati_7_0_RNO[7] , + N_424, N_422, \wb_dati_7_0_1[6] , \wb_dati_7[7] , \wb_dati_7[6] , + \wb_dati[6] , \wb_dati[7] , N_397, wb_reqc_i, wb_adr_0_sqmuxa_i, + wb_req, wb_rst8, \S_RNII9DO1[1] , wb_rst, N_586, wb_we_7_iv_0_0_0_1, + N_584, N_475, wb_we_RNO, \un1_wb_cyc_stb_0_sqmuxa_1_i[0] , wb_we, + N_255, N_358_i, N_635, N_254, Vout3, nCAS_s_i_tz_0, + un1_CS_0_sqmuxa_0_0_a2_1_4, N_327, un1_CS_0_sqmuxa_0_0_0, + \wb_dati_7_0_a2_0_1[7] , N_579, CKE_6_iv_i_a2_0, CKE_6_iv_i_0_1, + CKE_6_iv_i_0, N_449, N_365, N_364, \un1_wb_adr_0_sqmuxa_2_1[0] , + N_623, N_616, N_279, N_633, N_264, N_570, N_452, + \wb_dati_7_0_a2_2_1[3] , N_644, N_455, DQML_s_i_a2_0, N_28_i, + wb_adr_7_5_214_a2_2_0, N_577, N_569, N_634, \wb_dati_7_0_a2_2_0[1] , + N_265_i, \un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] , \wb_dati_7_0_a2_0[6] , + \wb_dati_7_0_a2_4_0[7] , N_393, nCAS_0_sqmuxa, N_639, \RA_42[10] , + N_640, un1_nCS61_1_i, Ready_0_sqmuxa_0_a2_6_a2_2, N_562, N_377, N_628, + un1_CS_0_sqmuxa_0_0_a2_3_2, un1_CS_0_sqmuxa_0_0_3, + un1_CS_0_sqmuxa_0_0_2, N_567, N_561_i, nCS_6_u_i_0, N_559_1, N_559_i, + nRAS_2_iv_i, un1_CS_0_sqmuxa_0_0_a2_1, N_330, N_328, nCS_6_u_i_a2_1, + N_429, N_351, \wb_adr_7_0_a2_5_0[0] , \wb_adr_7_0_1[0] , + \wb_adr_7_0_0[0] , N_378, \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] , + un1_CS_0_sqmuxa_0_0_a2_4_2, un1_CS_0_sqmuxa_0_0_a2_4_4, N_565, + un1_CS_0_sqmuxa_0_0_a2_2_2, un1_CS_0_sqmuxa_0_0_a2_2_4, + \wb_adr_7_0_a2_0[0] , un1_CS_0_sqmuxa_0_0_a2_1_2, + un1_CS_0_sqmuxa_0_0_a2_3_0, N_394, N_49_i, N_456, N_477, N_566_i, + \BA_4[0] , \RA_42[11] , \BA_4[1] , N_59_i, \Ain_c[5] , \Ain_c[4] , + N_551_i, \RA_42_3_0[5] , \Ain_c[6] , N_550_i, \Ain_c[2] , \Ain_c[7] , + N_549_i, N_553_i, nWE80_c, nRWE_r_0, RDOE_i, LED_c, \RD_in[0] , + DQMH_c, DQML_c, \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , + \RD_in[3] , \RD_in[2] , \RD_in[1] , \RA_c[11] , \RA_c[10] , \RA_c[9] , + \RA_c[8] , \RA_c[7] , \RA_c[6] , \RA_c[5] , \RA_c[4] , \RA_c[2] , + \RA_c[1] , \BA_c[1] , \BA_c[0] , nRWE_c, nCAS_c, nRAS_c, nCS_c, CKE_c, + \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] , + \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , \Dout_c[7] , \Dout_c[6] , + \Dout_c[5] , \Dout_c[4] , \Dout_c[3] , \Dout_c[2] , \Dout_c[1] , + \Dout_c[0] , VCCI; + + SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), + .Q1(\FS[0] ), .FCO(\FS_cry[0] )); + SLICE_1 SLICE_1( .A0(\FS[15] ), .DI0(\FS_s[15] ), .CLK(C14M_c), + .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), .Q0(\FS[15] )); + SLICE_2 SLICE_2( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), + .DI0(\FS_s[13] ), .CLK(C14M_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), + .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] )); + SLICE_3 SLICE_3( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), + .DI0(\FS_s[11] ), .CLK(C14M_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), + .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] )); + SLICE_4 SLICE_4( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), + .DI0(\FS_s[9] ), .CLK(C14M_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), + .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] )); + SLICE_5 SLICE_5( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), + .DI0(\FS_s[7] ), .CLK(C14M_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), + .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] )); + SLICE_6 SLICE_6( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), + .DI0(\FS_s[5] ), .CLK(C14M_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), + .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] )); + SLICE_7 SLICE_7( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), + .DI0(\FS_s[3] ), .CLK(C14M_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), + .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] )); + SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), + .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), + .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); + SLICE_9 SLICE_9( .C1(Ready), .B1(PHI1reg), .A1(PHI1_c), .B0(RWSel), + .A0(CO0_1), .DI0(\CmdTout_3[0] ), .CE(N_576_i), .CLK(C14M_c), + .F0(\CmdTout_3[0] ), .Q0(CO0_1), .F1(S_1)); + SLICE_10 SLICE_10( .D1(\CS[0] ), .C1(N_461), .B1(\S_RNII9DO1_0[1] ), + .A1(\CS[1] ), .C0(\S_RNII9DO1_0[1] ), .B0(N_461), .A0(\CS[0] ), + .DI1(N_511_i), .DI0(N_504_i), .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), + .F0(N_504_i), .Q0(\CS[0] ), .F1(N_511_i), .Q1(\CS[1] )); + SLICE_11 SLICE_11( .C1(\S_RNII9DO1_0[1] ), .B1(N_461), .A1(\CS[0] ), + .C0(N_637), .B0(\CS[2] ), .A0(\CS[1] ), .DI0(N_510_i), + .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_510_i), .Q0(\CS[2] ), + .F1(N_637)); + SLICE_12 SLICE_12( .C1(\Din_c[3] ), .B1(\Din_c[2] ), .A1(\Din_c[0] ), + .D0(RWSel), .C0(N_643), .B0(CmdBitbangMXO2_4_u_0_0_a2_0_1), + .A0(CmdBitbangMXO2), .DI0(CmdBitbangMXO2_4), .CE(N_576_i), .CLK(C14M_c), + .F0(CmdBitbangMXO2_4), .Q0(CmdBitbangMXO2), + .F1(CmdBitbangMXO2_4_u_0_0_a2_0_1)); + SLICE_13 SLICE_13( .C1(RWSel), .B1(\Din_c[7] ), .A1(\Din_c[5] ), .D0(RWSel), + .C0(N_643), .B0(N_629), .A0(CmdExecMXO2), .DI0(CmdExecMXO2_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdExecMXO2_4), .Q0(CmdExecMXO2), + .F1(N_466)); + SLICE_14 SLICE_14( .D1(N_478), .C1(\Din_c[4] ), .B1(\Din_c[1] ), + .A1(\Din_c[0] ), .D0(RWSel), .C0(N_476), .B0(CmdLEDGet_4_u_0_0_a2_0_2), + .A0(CmdLEDGet), .DI0(CmdLEDGet_4), .CE(N_576_i), .CLK(C14M_c), + .F0(CmdLEDGet_4), .Q0(CmdLEDGet), .F1(CmdLEDGet_4_u_0_0_a2_0_2)); + SLICE_15 SLICE_15( .D1(N_626), .C1(N_476), .B1(\Din_c[4] ), .A1(\Din_c[1] ), + .C0(RWSel), .B0(N_605), .A0(CmdLEDSet), .DI0(CmdLEDSet_4), .CE(N_576_i), + .CLK(C14M_c), .F0(CmdLEDSet_4), .Q0(CmdLEDSet), .F1(N_605)); + SLICE_16 SLICE_16( .C1(\Din_c[1] ), .B1(\Din_c[4] ), .A1(N_476), .D0(RWSel), + .C0(N_643), .B0(N_626), .A0(CmdRWMaskSet), .DI0(CmdRWMaskSet_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdRWMaskSet_4), .Q0(CmdRWMaskSet), + .F1(N_643)); + SLICE_17 SLICE_17( .D1(N_626), .C1(N_476), .B1(\Din_c[4] ), .A1(\Din_c[1] ), + .C0(RWSel), .B0(N_401), .A0(CmdSetRWBankFFLED), .DI0(CmdSetRWBankFFLED_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdSetRWBankFFLED_4), + .Q0(CmdSetRWBankFFLED), .F1(N_401)); + SLICE_18 SLICE_18( .C1(N_474), .B1(\CS[2] ), .A1(\CS[1] ), .D0(RWSel), + .C0(N_476), .B0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), + .A0(CmdSetRWBankFFMXO2), .DI0(CmdSetRWBankFFMXO2_4), .CE(N_576_i), + .CLK(C14M_c), .F0(CmdSetRWBankFFMXO2_4), .Q0(CmdSetRWBankFFMXO2), + .F1(N_476)); + SLICE_19 SLICE_19( .D1(RWSel), .C1(CO0_1), .B1(\CmdTout[1] ), + .A1(\CmdTout[2] ), .C0(RWSel), .B0(\CmdTout[1] ), .A0(CO0_1), + .DI1(N_556_i), .DI0(N_555_i), .CE(N_576_i), .CLK(C14M_c), .F0(N_555_i), + .Q0(\CmdTout[1] ), .F1(N_556_i), .Q1(\CmdTout[2] )); + SLICE_20 SLICE_20( .D1(\S[0] ), .C1(\S[1] ), .B1(\S[2] ), .A1(\S[3] ), + .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), .DI0(N_6_i), + .CLK(C14M_c), .F0(N_6_i), .Q0(DOEEN), .F1(N_576_i)); + SLICE_21 SLICE_21( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[1] ), + .C0(\wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), .DI0(LEDEN_RNO), + .CE(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .CLK(C14M_c), .F0(LEDEN_RNO), + .Q0(LEDEN), .F1(N_558_i)); + SLICE_22 SLICE_22( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[3] ), .C0(\S[3] ), + .B0(\S[0] ), .A0(\Ain_c[0] ), .DI1(N_552_i), .DI0(N_127_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c), .F0(N_127_i), .Q0(\RA_c[0] ), + .F1(N_552_i), .Q1(\RA_c[3] )); + SLICE_23 SLICE_23( .C1(\RWMask[1] ), .B1(N_591), .A1(\Din_c[1] ), + .C0(\RWMask[0] ), .B0(N_591), .A0(\Din_c[0] ), .DI1(\RWBank_5[1] ), + .DI0(\RWBank_5[0] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[0] ), + .Q0(\RWBank[0] ), .F1(\RWBank_5[1] ), .Q1(\RWBank[1] )); + SLICE_24 SLICE_24( .C1(\RWMask[3] ), .B1(N_591), .A1(\Din_c[3] ), + .C0(\RWMask[2] ), .B0(N_591), .A0(\Din_c[2] ), .DI1(\RWBank_5[3] ), + .DI0(\RWBank_5[2] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[2] ), + .Q0(\RWBank[2] ), .F1(\RWBank_5[3] ), .Q1(\RWBank[3] )); + SLICE_25 SLICE_25( .C1(\RWMask[5] ), .B1(N_591), .A1(\Din_c[5] ), + .C0(\RWMask[4] ), .B0(N_591), .A0(\Din_c[4] ), .DI1(\RWBank_5[5] ), + .DI0(\RWBank_5[4] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[4] ), + .Q0(\RWBank[4] ), .F1(\RWBank_5[5] ), .Q1(\RWBank[5] )); + SLICE_26 SLICE_26( .C1(\RWMask[7] ), .B1(N_591), .A1(\Din_c[7] ), + .C0(\RWMask[6] ), .B0(N_591), .A0(\Din_c[6] ), .DI1(\RWBank_5[7] ), + .DI0(\RWBank_5[6] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[6] ), + .Q0(\RWBank[6] ), .F1(\RWBank_5[7] ), .Q1(\RWBank[7] )); + SLICE_27 SLICE_27( .C1(\wb_dato[1] ), .B1(\S[3] ), .A1(\Din_c[1] ), + .C0(\wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), .DI1(N_291_i), + .DI0(N_292_i), .CE(N_88), .CLK(C14M_c), .F0(N_292_i), .Q0(\RWMask[0] ), + .F1(N_291_i), .Q1(\RWMask[1] )); + SLICE_28 SLICE_28( .C1(\wb_dato[3] ), .B1(\S[3] ), .A1(\Din_c[3] ), + .C0(\wb_dato[2] ), .B0(\S[3] ), .A0(\Din_c[2] ), .DI1(N_289_i), + .DI0(N_290_i), .CE(N_88), .CLK(C14M_c), .F0(N_290_i), .Q0(\RWMask[2] ), + .F1(N_289_i), .Q1(\RWMask[3] )); + SLICE_29 SLICE_29( .C1(\wb_dato[5] ), .B1(\S[3] ), .A1(\Din_c[5] ), + .C0(\wb_dato[4] ), .B0(\S[3] ), .A0(\Din_c[4] ), .DI1(N_287_i), + .DI0(N_288_i), .CE(N_88), .CLK(C14M_c), .F0(N_288_i), .Q0(\RWMask[4] ), + .F1(N_287_i), .Q1(\RWMask[5] )); + SLICE_30 SLICE_30( .C1(\wb_dato[7] ), .B1(\S[3] ), .A1(\Din_c[7] ), + .C0(\wb_dato[6] ), .B0(\S[3] ), .A0(\Din_c[6] ), .DI1(N_285), + .DI0(N_286_i), .CE(N_88), .CLK(C14M_c), .F0(N_286_i), .Q0(\RWMask[6] ), + .F1(N_285), .Q1(\RWMask[7] )); + SLICE_31 SLICE_31( .C1(nWE_c), .B1(nEN80_c), .A1(DOEEN), .D0(nWE_c), + .C0(nC07X_c), .B0(\RA_c[3] ), .A0(\RA_c[0] ), .DI0(RWSel_2), .CE(nCS61), + .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(nDOE_c)); + SLICE_32 SLICE_32( .D1(Ready_0_sqmuxa_0_a2_6_a2_4), .C1(N_489), .B1(\FS[7] ), + .A1(\FS[6] ), .B0(Ready), .A0(Ready_0_sqmuxa), .DI0(N_876_0), .CLK(C14M_c), + .F0(N_876_0), .Q0(Ready), .F1(Ready_0_sqmuxa)); + SLICE_33 SLICE_33( .D1(wb_reqc_1), .C1(N_575), .B1(N_572), .A1(S_1), + .D0(\S_s_0_1[0] ), .C0(\S[1] ), .B0(\S[0] ), .A0(S_1), .DI1(N_133_i), + .DI0(\S_s_0[0] ), .CLK(C14M_c), .F0(\S_s_0[0] ), .Q0(\S[0] ), .F1(N_133_i), + .Q1(\S[1] )); + SLICE_34 SLICE_34( .D1(\S[3] ), .C1(\S[2] ), .B1(N_575), .A1(S_1), + .D0(\S[3] ), .C0(\S[2] ), .B0(N_575), .A0(S_1), .DI1(N_129_i), + .DI0(N_131_i), .CLK(C14M_c), .F0(N_131_i), .Q0(\S[2] ), .F1(N_129_i), + .Q1(\S[3] )); + SLICE_35 SLICE_35( .D1(wb_adr_7_5_214_0_1), .C1(\S[2] ), .B1(N_388), + .A1(\Din_c[1] ), .D0(\wb_adr_7_0_4[0] ), .C0(N_642), .B0(N_376), + .A0(\FS[13] ), .DI1(\wb_adr_RNO[1] ), .DI0(\wb_adr_7[0] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_adr_7[0] ), + .Q0(\wb_adr[0] ), .F1(\wb_adr_RNO[1] ), .Q1(\wb_adr[1] )); + SLICE_36 SLICE_36( .B1(\S[2] ), .A1(\Din_c[3] ), .B0(\S[2] ), + .A0(\Din_c[2] ), .DI1(N_41_i), .DI0(N_43_i), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_43_i), + .Q0(\wb_adr[2] ), .F1(N_41_i), .Q1(\wb_adr[3] )); + SLICE_37 SLICE_37( .C1(\S[2] ), .B1(\FS[14] ), .A1(\Din_c[5] ), .C0(\S[2] ), + .B0(\FS[14] ), .A0(\Din_c[4] ), .DI1(N_295), .DI0(N_294), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_294), + .Q0(\wb_adr[4] ), .F1(N_295), .Q1(\wb_adr[5] )); + SLICE_38 SLICE_38( .B1(\S[2] ), .A1(\Din_c[7] ), .C0(\S[2] ), .B0(\FS[14] ), + .A0(\Din_c[6] ), .DI1(N_39_i), .DI0(N_296), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_296), + .Q0(\wb_adr[6] ), .F1(N_39_i), .Q1(\wb_adr[7] )); + SLICE_39 SLICE_39( .D1(\FS[14] ), .C1(wb_ack), .B1(\FS[0] ), .A1(N_300), + .C0(\S[3] ), .B0(N_395), .A0(CmdExecMXO2), .DI0(wb_cyc_stb_RNO), + .CE(N_104), .CLK(C14M_c), .F0(wb_cyc_stb_RNO), .Q0(wb_cyc_stb), .F1(N_395)); + SLICE_40 SLICE_40( .D1(\wb_dati_7_0_0[1] ), .C1(N_627), .B1(N_621), + .A1(N_336), .D0(\wb_dati_7_0_a2_1[0] ), .C0(\wb_adr[0] ), .B0(\S[2] ), + .A0(N_484), .DI1(\wb_dati_7[1] ), .DI0(\wb_dati_7[0] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[0] ), + .Q0(\wb_dati[0] ), .F1(\wb_dati_7[1] ), .Q1(\wb_dati[1] )); + SLICE_41 SLICE_41( .C1(\wb_dati_7_0_2[3] ), .B1(\wb_dati_7_0_0[3] ), + .A1(N_336), .D0(\wb_dati_7_0_o2_0[2] ), .C0(\wb_adr[2] ), .B0(\S[2] ), + .A0(N_345), .DI1(\wb_dati_7[3] ), .DI0(\wb_dati_7[2] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[2] ), + .Q0(\wb_dati[2] ), .F1(\wb_dati_7[3] ), .Q1(\wb_dati[3] )); + SLICE_42 SLICE_42( .D1(\wb_dati_7_0_o2_0[2] ), .C1(\wb_adr[5] ), .B1(\S[2] ), + .A1(N_345), .D0(\wb_dati_7_0_0[4] ), .C0(N_349), .B0(N_346), .A0(N_345), + .DI1(\wb_dati_7[5] ), .DI0(\wb_dati_7[4] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[4] ), + .Q0(\wb_dati[4] ), .F1(\wb_dati_7[5] ), .Q1(\wb_dati[5] )); + SLICE_43 SLICE_43( .D1(\wb_dati_7_0_0[7] ), .C1(\wb_dati_7_0_RNO[7] ), + .B1(N_424), .A1(N_422), .C0(\wb_dati_7_0_1[6] ), .B0(N_627), .A0(N_621), + .DI1(\wb_dati_7[7] ), .DI0(\wb_dati_7[6] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[6] ), + .Q0(\wb_dati[6] ), .F1(\wb_dati_7[7] ), .Q1(\wb_dati[7] )); + SLICE_44 SLICE_44( .C1(\FS[13] ), .B1(\FS[12] ), .A1(\FS[11] ), + .D0(wb_reqc_1), .C0(\S[3] ), .B0(N_397), .A0(\FS[14] ), .DI0(wb_reqc_i), + .CE(wb_adr_0_sqmuxa_i), .LSR(\S[2] ), .CLK(C14M_c), .F0(wb_reqc_i), + .Q0(wb_req), .F1(N_397)); + SLICE_45 SLICE_45( .B1(wb_ack), .A1(\FS[14] ), .B0(\FS[15] ), .A0(\FS[14] ), + .DI0(wb_rst8), .LSR(\S_RNII9DO1[1] ), .CLK(C14M_c), .F0(wb_rst8), + .Q0(wb_rst), .F1(N_586)); + SLICE_46 SLICE_46( .D1(\FS[8] ), .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[12] ), + .D0(wb_we_7_iv_0_0_0_1), .C0(N_584), .B0(N_475), .A0(\FS[13] ), + .DI0(wb_we_RNO), .CE(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), .CLK(C14M_c), + .F0(wb_we_RNO), .Q0(wb_we), .F1(N_584)); + SLICE_47 SLICE_47( .D1(N_255), .C1(\S[0] ), .B1(\S_RNII9DO1[1] ), + .A1(\RWBank[6] ), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), + .F0(\S_RNII9DO1[1] ), .F1(N_358_i)); + SLICE_48 SLICE_48( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[1] ), .A1(\S[0] ), + .D0(N_635), .C0(\S[0] ), .B0(N_254), .A0(Vout3), .F0(nCAS_s_i_tz_0), + .F1(Vout3)); + SLICE_49 SLICE_49( .D1(un1_CS_0_sqmuxa_0_0_a2_1_4), .C1(RWSel), + .B1(\Din_c[6] ), .A1(\CS[0] ), .D0(RWSel), .C0(N_327), .B0(\CS[2] ), + .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_0), .F1(N_327)); + SLICE_50 SLICE_50( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[9] ), .A1(\FS[8] ), + .D0(\wb_dati_7_0_a2_0_1[7] ), .C0(N_621), .B0(N_579), .A0(\FS[9] ), + .F0(\wb_dati_7_0_RNO[7] ), .F1(\wb_dati_7_0_a2_0_1[7] )); + SLICE_51 SLICE_51( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), + .A1(CKE_6_iv_i_a2_0), .D0(\S[3] ), .C0(N_489), .B0(\FS[15] ), + .A0(CKE_6_iv_i_0_1), .F0(CKE_6_iv_i_0), .F1(CKE_6_iv_i_0_1)); + SLICE_52 SLICE_52( .D1(wb_req), .C1(N_449), .B1(N_300), .A1(\FS[0] ), + .D0(N_586), .C0(N_449), .B0(N_365), .A0(N_364), .F0(N_104), .F1(N_365)); + SLICE_53 SLICE_53( .D1(\S[3] ), .C1(\S[2] ), .B1(RWSel), .A1(\FS[15] ), + .D0(wb_reqc_1), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .B0(\S[2] ), + .A0(CmdExecMXO2), .F0(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), + .F1(\un1_wb_adr_0_sqmuxa_2_1[0] )); + SLICE_54 SLICE_54( .D1(\Din_c[2] ), .C1(\Din_c[1] ), .B1(\Din_c[0] ), + .A1(\CS[1] ), .D0(N_623), .C0(N_616), .B0(\Din_c[1] ), .A0(\CS[2] ), + .F0(N_279), .F1(N_623)); + SLICE_55 SLICE_55( .D1(\FS[4] ), .C1(N_633), .B1(\FS[5] ), .A1(N_264), + .D0(\FS[1] ), .C0(\FS[2] ), .B0(\FS[3] ), .A0(\FS[5] ), .F0(N_633), + .F1(N_570)); + SLICE_56 SLICE_56( .C1(\FS[15] ), .B1(\S_RNII9DO1[1] ), .A1(\FS[14] ), + .C0(\FS[13] ), .B0(N_452), .A0(\FS[12] ), .F0(N_621), .F1(N_452)); + SLICE_57 SLICE_57( .D1(\S_RNII9DO1_0[1] ), .C1(RWSel), .B1(CmdExecMXO2), + .A1(wb_ack), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[3] ), .A0(\S[2] ), + .F0(\S_RNII9DO1_0[1] ), .F1(N_364)); + SLICE_58 SLICE_58( .D1(\wb_dati_7_0_a2_2_1[3] ), .C1(N_644), .B1(N_455), + .A1(\FS[12] ), .D0(\FS[10] ), .C0(\FS[11] ), .B0(\FS[8] ), .A0(\FS[9] ), + .F0(\wb_dati_7_0_a2_2_1[3] ), .F1(\wb_dati_7_0_2[3] )); + SLICE_59 SLICE_59( .D1(nCS61), .C1(\RWBank[6] ), .B1(\S_RNII9DO1[1] ), + .A1(DQML_s_i_a2_0), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), + .F0(DQML_s_i_a2_0), .F1(N_28_i)); + SLICE_60 SLICE_60( .D1(wb_adr_7_5_214_a2_2_0), .C1(N_577), .B1(N_569), + .A1(N_475), .C0(\FS[10] ), .B0(\FS[12] ), .A0(\FS[13] ), + .F0(wb_adr_7_5_214_a2_2_0), .F1(wb_adr_7_5_214_0_1)); + SLICE_61 SLICE_61( .C1(N_634), .B1(\FS[13] ), .A1(\FS[12] ), .D0(\FS[10] ), + .C0(\FS[11] ), .B0(\FS[8] ), .A0(\FS[9] ), .F0(N_634), + .F1(\wb_dati_7_0_a2_2_0[1] )); + SLICE_62 SLICE_62( .D1(N_475), .C1(N_265_i), .B1(\FS[12] ), .A1(\FS[11] ), + .C0(\FS[8] ), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_265_i), .F1(N_388)); + SLICE_63 SLICE_63( .D1(N_264), .C1(N_254), .B1(\FS[7] ), .A1(\FS[6] ), + .C0(\FS[1] ), .B0(\FS[2] ), .A0(\FS[3] ), .F0(N_264), .F1(N_300)); + SLICE_64 SLICE_64( .C1(\FS[8] ), .B1(\FS[9] ), .A1(\FS[11] ), .D0(\FS[10] ), + .C0(\FS[12] ), .B0(N_577), .A0(wb_ack), + .F0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .F1(N_577)); + SLICE_65 SLICE_65( .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[10] ), + .C0(\FS[12] ), .B0(\FS[13] ), .A0(\wb_dati_7_0_a2_0[6] ), + .F0(\wb_dati_7_0_a2_4_0[7] ), .F1(\wb_dati_7_0_a2_0[6] )); + SLICE_66 SLICE_66( .B1(\S[2] ), .A1(\FS[14] ), .D0(\FS[12] ), .C0(\FS[13] ), + .B0(\FS[11] ), .A0(N_475), .F0(N_393), .F1(N_475)); + SLICE_67 SLICE_67( .B1(\S[1] ), .A1(\S[0] ), .D0(wb_reqc_1), .C0(\S[3] ), + .B0(\S[2] ), .A0(RWSel), .F0(LEDEN13), .F1(wb_reqc_1)); + SLICE_68 SLICE_68( .D1(\wb_adr[3] ), .C1(\S[2] ), .B1(N_627), .A1(N_455), + .D0(\FS[11] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[10] ), .F0(N_627), + .F1(\wb_dati_7_0_0[3] )); + SLICE_69 SLICE_69( .D1(nCAS_0_sqmuxa), .C1(\RWBank[2] ), .B1(N_639), + .A1(N_255), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), .F0(N_639), + .F1(\RA_42[10] )); + SLICE_70 SLICE_70( .D1(N_644), .C1(N_627), .B1(N_455), .A1(\FS[12] ), + .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), .F0(N_644), + .F1(N_345)); + SLICE_71 SLICE_71( .D1(nCS61), .C1(N_640), .B1(N_633), .A1(\FS[4] ), + .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), .F0(nCS61), + .F1(un1_nCS61_1_i)); + SLICE_72 SLICE_72( .D1(Ready_0_sqmuxa_0_a2_6_a2_2), .C1(N_449), .B1(\FS[5] ), + .A1(\FS[3] ), .D0(\S[2] ), .C0(\S[3] ), .B0(wb_reqc_1), .A0(\FS[15] ), + .F0(N_449), .F1(Ready_0_sqmuxa_0_a2_6_a2_4)); + SLICE_73 SLICE_73( .D1(N_562), .C1(N_455), .B1(\FS[12] ), .A1(\FS[11] ), + .D0(\FS[14] ), .C0(\S_RNII9DO1[1] ), .B0(\FS[15] ), .A0(\FS[13] ), + .F0(N_455), .F1(N_377)); + SLICE_74 SLICE_74( .C1(N_484), .B1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[10] ), + .C0(\FS[12] ), .B0(\FS[13] ), .A0(N_642), .F0(N_346), .F1(N_642)); + SLICE_75 SLICE_75( .D1(N_489), .C1(\FS[7] ), .B1(\FS[6] ), .A1(\FS[0] ), + .C0(\FS[15] ), .B0(\S_RNII9DO1[1] ), .A0(N_628), .F0(N_640), .F1(N_628)); + SLICE_76 SLICE_76( .B1(\FS[5] ), .A1(\FS[4] ), .D0(N_449), .C0(N_628), + .B0(N_254), .A0(N_264), .F0(nCAS_0_sqmuxa), .F1(N_254)); + SLICE_77 SLICE_77( .C1(N_466), .B1(\Din_c[6] ), .A1(\CS[0] ), + .D0(un1_CS_0_sqmuxa_0_0_a2_3_2), .C0(un1_CS_0_sqmuxa_0_0_3), + .B0(un1_CS_0_sqmuxa_0_0_2), .A0(N_474), .F0(un1_CS_0_sqmuxa_i), .F1(N_474)); + SLICE_78 SLICE_78( .B1(N_633), .A1(\FS[4] ), .D0(nCAS_s_i_tz_0), .C0(N_640), + .B0(N_567), .A0(nCAS_0_sqmuxa), .F0(N_561_i), .F1(N_567)); + SLICE_79 SLICE_79( .D1(nEN80_c), .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), + .B0(nCS_6_u_i_0), .A0(N_559_1), .F0(N_559_i), .F1(nCS_6_u_i_0)); + SLICE_80 SLICE_80( .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), .C0(\S[0] ), + .B0(N_635), .A0(N_559_1), .F0(nRAS_2_iv_i), .F1(N_635)); + SLICE_81 SLICE_81( .D1(\Din_c[6] ), .C1(\Din_c[4] ), .B1(\Din_c[3] ), + .A1(\CS[0] ), .D0(un1_CS_0_sqmuxa_0_0_a2_1), .C0(un1_CS_0_sqmuxa_0_0_0), + .B0(N_466), .A0(N_279), .F0(un1_CS_0_sqmuxa_0_0_2), + .F1(un1_CS_0_sqmuxa_0_0_a2_1)); + SLICE_82 SLICE_82( .D1(RWSel), .C1(\CmdTout[2] ), .B1(\CmdTout[1] ), + .A1(CO0_1), .D0(\S_RNII9DO1_0[1] ), .C0(N_461), .B0(N_330), .A0(N_328), + .F0(un1_CS_0_sqmuxa_0_0_3), .F1(N_461)); + SLICE_83 SLICE_83( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[0] ), .A1(\FS[15] ), + .D0(nCS_6_u_i_a2_1), .C0(N_628), .B0(N_570), .A0(N_429), .F0(N_559_1), + .F1(nCS_6_u_i_a2_1)); + SLICE_84 SLICE_84( .D1(\wb_dati_7_0_a2_0[6] ), .C1(N_455), .B1(\FS[12] ), + .A1(\FS[10] ), .D0(\wb_adr[6] ), .C0(\S[2] ), .B0(N_351), .A0(N_346), + .F0(\wb_dati_7_0_1[6] ), .F1(N_351)); + SLICE_85 SLICE_85( .D1(\wb_adr_7_0_a2_5_0[0] ), .C1(N_579), .B1(N_452), + .A1(\FS[8] ), .D0(\wb_adr_7_0_1[0] ), .C0(\wb_adr_7_0_0[0] ), .B0(N_378), + .A0(N_377), .F0(\wb_adr_7_0_4[0] ), .F1(\wb_adr_7_0_1[0] )); + SLICE_86 SLICE_86( .D1(\FS[14] ), .C1(\S_RNII9DO1[1] ), .B1(\FS[15] ), + .A1(\FS[8] ), .D0(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ), .C0(N_484), + .B0(LEDEN13), .A0(CmdLEDSet), .F0(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), + .F1(N_484)); + SLICE_87 SLICE_87( .D1(un1_CS_0_sqmuxa_0_0_a2_4_2), .C1(RWSel), + .B1(\Din_c[6] ), .A1(\CS[0] ), .C0(un1_CS_0_sqmuxa_0_0_a2_4_4), + .B0(\CS[2] ), .A0(\CS[1] ), .F0(N_330), .F1(un1_CS_0_sqmuxa_0_0_a2_4_4)); + SLICE_88 SLICE_88( .B1(\FS[13] ), .A1(\FS[12] ), .D0(N_634), .C0(N_569), + .B0(N_452), .A0(N_336), .F0(\wb_dati_7_0_o2_0[2] ), .F1(N_569)); + SLICE_89 SLICE_89( .B1(\FS[11] ), .A1(\FS[10] ), .D0(N_579), .C0(N_455), + .B0(\FS[9] ), .A0(\FS[8] ), .F0(N_378), .F1(N_579)); + SLICE_90 SLICE_90( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), + .C0(N_565), .B0(N_484), .A0(\FS[12] ), .F0(N_336), .F1(N_565)); + SLICE_91 SLICE_91( .D1(un1_CS_0_sqmuxa_0_0_a2_2_2), .C1(\Din_c[6] ), + .B1(\CS[2] ), .A1(\CS[0] ), .C0(un1_CS_0_sqmuxa_0_0_a2_2_4), .B0(RWSel), + .A0(\Din_c[7] ), .F0(N_328), .F1(un1_CS_0_sqmuxa_0_0_a2_2_4)); + SLICE_92 SLICE_92( .D1(N_562), .C1(\FS[13] ), .B1(\FS[12] ), .A1(\FS[11] ), + .D0(\wb_adr_7_0_a2_0[0] ), .C0(\S[2] ), .B0(N_452), .A0(\Din_c[0] ), + .F0(\wb_adr_7_0_0[0] ), .F1(\wb_adr_7_0_a2_0[0] )); + SLICE_93 SLICE_93( .D1(N_616), .C1(\Din_c[5] ), .B1(\Din_c[4] ), + .A1(\Din_c[1] ), .D0(un1_CS_0_sqmuxa_0_0_a2_1_2), .C0(\Din_c[7] ), + .B0(\Din_c[3] ), .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_a2_1_4), + .F1(un1_CS_0_sqmuxa_0_0_a2_1_2)); + SLICE_94 SLICE_94( .D1(\Din_c[3] ), .C1(\Din_c[2] ), .B1(\Din_c[0] ), + .A1(\Din_c[1] ), .D0(un1_CS_0_sqmuxa_0_0_a2_3_0), .C0(\Din_c[4] ), + .B0(\CS[2] ), .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_a2_3_2), + .F1(un1_CS_0_sqmuxa_0_0_a2_3_0)); + SLICE_95 SLICE_95( .D1(N_577), .C1(N_475), .B1(\FS[12] ), .A1(\FS[10] ), + .D0(\S[2] ), .C0(N_394), .B0(N_393), .A0(\Din_c[0] ), + .F0(wb_we_7_iv_0_0_0_1), .F1(N_394)); + SLICE_96 SLICE_96( .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), .D0(\S[0] ), + .C0(\RWBank[7] ), .B0(\RWBank[0] ), .A0(N_255), .F0(N_49_i), .F1(N_255)); + SLICE_97 SLICE_97( .B1(\FS[12] ), .A1(\FS[10] ), .D0(N_577), .C0(N_456), + .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_489), .F1(N_456)); + SLICE_98 SLICE_98( .C1(\Din_c[2] ), .B1(\Din_c[3] ), .A1(\Din_c[0] ), + .D0(N_626), .C0(N_477), .B0(\Din_c[7] ), .A0(\Din_c[5] ), + .F0(un1_CS_0_sqmuxa_0_0_a2_4_2), .F1(N_626)); + SLICE_99 SLICE_99( .B1(\Din_c[3] ), .A1(\Din_c[2] ), .D0(N_478), .C0(N_477), + .B0(\Din_c[5] ), .A0(\Din_c[0] ), .F0(un1_CS_0_sqmuxa_0_0_a2_2_2), + .F1(N_478)); + SLICE_100 SLICE_100( .C1(\Din_c[0] ), .B1(\Din_c[2] ), .A1(\Din_c[3] ), + .C0(N_629), .B0(\Din_c[4] ), .A0(\Din_c[1] ), + .F0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), .F1(N_629)); + SLICE_101 SLICE_101( .D1(\S[2] ), .C1(\S[3] ), .B1(\S[1] ), .A1(\S[0] ), + .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), .A0(\S[0] ), .F0(\S_RNII9DO1_1[1] ), + .F1(N_566_i)); + SLICE_102 SLICE_102( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[1] ), .A1(\S[0] ), + .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\RWBank[4] ), .F0(\BA_4[0] ), + .F1(\S_s_0_1[0] )); + SLICE_103 SLICE_103( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), + .A1(\RWBank[3] ), .D0(\S[2] ), .C0(\S[3] ), .B0(wb_reqc_1), .A0(\FS[15] ), + .F0(wb_adr_0_sqmuxa_i), .F1(\RA_42[11] )); + SLICE_104 SLICE_104( .D1(N_621), .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[8] ), + .D0(N_621), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[9] ), .F0(N_376), + .F1(N_349)); + SLICE_105 SLICE_105( .D1(wb_ack), .C1(N_579), .B1(N_569), .A1(\FS[9] ), + .D0(N_579), .C0(N_569), .B0(N_484), .A0(\FS[9] ), .F0(N_424), + .F1(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] )); + SLICE_106 SLICE_106( .B1(\S[1] ), .A1(\S[0] ), .C0(\S[0] ), .B0(\S[1] ), + .A0(nEN80_c), .F0(CKE_6_iv_i_a2_0), .F1(N_575)); + SLICE_107 SLICE_107( .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), + .B0(\S[3] ), .A0(\RWBank[5] ), .F0(\BA_4[1] ), .F1(N_572)); + SLICE_108 SLICE_108( .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), .D0(N_642), + .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ), .F0(N_422), + .F1(\wb_adr_7_0_a2_5_0[0] )); + SLICE_109 SLICE_109( .D1(\wb_dati_7_0_a2_4_0[7] ), .C1(\wb_adr[7] ), + .B1(\S[2] ), .A1(N_452), .D0(\wb_dati_7_0_a2_2_0[1] ), .C0(\wb_adr[1] ), + .B0(\S[2] ), .A0(N_452), .F0(\wb_dati_7_0_0[1] ), .F1(\wb_dati_7_0_0[7] )); + SLICE_110 SLICE_110( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), + .A1(\RWBank[1] ), .D0(wb_reqc_1), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), + .B0(\S[2] ), .A0(CmdBitbangMXO2), .F0(\un1_wb_adr_0_sqmuxa_2_i[0] ), + .F1(N_59_i)); + SLICE_111 SLICE_111( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[5] ), .C0(\S[3] ), + .B0(\S[0] ), .A0(\Ain_c[4] ), .F0(N_551_i), .F1(\RA_42_3_0[5] )); + SLICE_112 SLICE_112( .D1(\S[3] ), .C1(\S[1] ), .B1(\S[0] ), .A1(N_254), + .C0(\S[3] ), .B0(\S[0] ), .A0(\Ain_c[6] ), .F0(N_550_i), .F1(N_429)); + SLICE_113 SLICE_113( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[2] ), .C0(\S[3] ), + .B0(\S[0] ), .A0(\Ain_c[7] ), .F0(N_549_i), .F1(N_553_i)); + SLICE_114 SLICE_114( .D1(\wb_adr[4] ), .C1(\S[2] ), .B1(N_634), .A1(N_455), + .D0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .C0(N_455), .B0(LEDEN13), + .A0(CmdRWMaskSet), .F0(N_88), .F1(\wb_dati_7_0_0[4] )); + SLICE_115 SLICE_115( .B1(nWE80_c), .A1(nEN80_c), .D0(nWE80_c), .C0(\S[0] ), + .B0(nCAS_0_sqmuxa), .A0(un1_nCS61_1_i), .F0(nRWE_r_0), .F1(RDOE_i)); + SLICE_116 SLICE_116( .B1(\FS[9] ), .A1(\FS[8] ), .D0(N_456), .C0(\FS[13] ), + .B0(\FS[11] ), .A0(\FS[9] ), .F0(\wb_dati_7_0_a2_1[0] ), .F1(N_562)); + SLICE_117 SLICE_117( .D1(LEDEN), .C1(CmdSetRWBankFFMXO2), + .B1(CmdSetRWBankFFLED), .A1(CmdLEDGet), .B0(nEN80_c), .A0(LEDEN), + .F0(LED_c), .F1(N_591)); + SLICE_118 SLICE_118( .B1(\Din_c[4] ), .A1(\Din_c[1] ), .B0(\Din_c[2] ), + .A0(\Din_c[0] ), .F0(N_616), .F1(N_477)); + SLICE_119 SLICE_119( .D0(\FS[4] ), .C0(\FS[2] ), .B0(\FS[1] ), .A0(\FS[0] ), + .F0(Ready_0_sqmuxa_0_a2_6_a2_2)); + RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(\Din_c[0] ), + .RD0(RD[0])); + LED LED_I( .PADDO(LED_c), .LED(LED)); + C14M C14M_I( .PADDI(C14M_c), .C14M(C14M)); + DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH)); + DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_358_i), .CLK(C14M_c)); + DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML)); + DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_28_i), .CLK(C14M_c)); + RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(\Din_c[7] ), + .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(\Din_c[6] ), + .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(\Din_c[5] ), + .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(\Din_c[4] ), + .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(\Din_c[3] ), + .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(\Din_c[2] ), + .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(\Din_c[1] ), + .RD1(RD[1])); + RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11])); + RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(\RA_42[11] ), + .CLK(C14M_c)); + RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10])); + RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(\RA_42[10] ), + .CLK(C14M_c)); + RA_9_ \RA[9]_I ( .IOLDO(\RA_c[9] ), .RA9(RA[9])); + RA_9__MGIOL \RA[9]_MGIOL ( .IOLDO(\RA_c[9] ), .OPOS(N_59_i), .CLK(C14M_c)); + RA_8_ \RA[8]_I ( .IOLDO(\RA_c[8] ), .RA8(RA[8])); + RA_8__MGIOL \RA[8]_MGIOL ( .IOLDO(\RA_c[8] ), .OPOS(N_49_i), .CLK(C14M_c)); + RA_7_ \RA[7]_I ( .IOLDO(\RA_c[7] ), .RA7(RA[7])); + RA_7__MGIOL \RA[7]_MGIOL ( .IOLDO(\RA_c[7] ), .OPOS(N_549_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_6_ \RA[6]_I ( .IOLDO(\RA_c[6] ), .RA6(RA[6])); + RA_6__MGIOL \RA[6]_MGIOL ( .IOLDO(\RA_c[6] ), .OPOS(N_550_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_5_ \RA[5]_I ( .IOLDO(\RA_c[5] ), .RA5(RA[5])); + RA_5__MGIOL \RA[5]_MGIOL ( .IOLDO(\RA_c[5] ), .OPOS(\RA_42_3_0[5] ), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_4_ \RA[4]_I ( .IOLDO(\RA_c[4] ), .RA4(RA[4])); + RA_4__MGIOL \RA[4]_MGIOL ( .IOLDO(\RA_c[4] ), .OPOS(N_551_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .IOLDO(\RA_c[2] ), .RA2(RA[2])); + RA_2__MGIOL \RA[2]_MGIOL ( .IOLDO(\RA_c[2] ), .OPOS(N_553_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_1_ \RA[1]_I ( .IOLDO(\RA_c[1] ), .RA1(RA[1])); + RA_1__MGIOL \RA[1]_MGIOL ( .IOLDO(\RA_c[1] ), .OPOS(N_558_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0])); + BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1])); + BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), + .LSR(N_566_i), .CLK(C14M_c)); + BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0])); + BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), + .LSR(N_566_i), .CLK(C14M_c)); + nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE)); + nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(nRWE_r_0), .CLK(C14M_c)); + nCAS nCAS_I( .IOLDO(nCAS_c), .nCAS(nCAS)); + nCAS_MGIOL nCAS_MGIOL( .IOLDO(nCAS_c), .OPOS(N_561_i), .CLK(C14M_c)); + nRAS nRAS_I( .IOLDO(nRAS_c), .nRAS(nRAS)); + nRAS_MGIOL nRAS_MGIOL( .IOLDO(nRAS_c), .OPOS(nRAS_2_iv_i), .CLK(C14M_c)); + nCS nCS_I( .IOLDO(nCS_c), .nCS(nCS)); + nCS_MGIOL nCS_MGIOL( .IOLDO(nCS_c), .OPOS(N_559_i), .CLK(C14M_c)); + CKE CKE_I( .IOLDO(CKE_c), .CKE(CKE)); + CKE_MGIOL CKE_MGIOL( .IOLDO(CKE_c), .OPOS(CKE_6_iv_i_0), .CLK(C14M_c)); + nVOE nVOE_I( .PADDO(PHI1_c), .nVOE(nVOE)); + Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7])); + Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_6_ \Vout[6]_I ( .IOLDO(\Vout_c[6] ), .Vout6(Vout[6])); + Vout_6__MGIOL \Vout[6]_MGIOL ( .IOLDO(\Vout_c[6] ), .OPOS(\RD_in[6] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_5_ \Vout[5]_I ( .IOLDO(\Vout_c[5] ), .Vout5(Vout[5])); + Vout_5__MGIOL \Vout[5]_MGIOL ( .IOLDO(\Vout_c[5] ), .OPOS(\RD_in[5] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_4_ \Vout[4]_I ( .IOLDO(\Vout_c[4] ), .Vout4(Vout[4])); + Vout_4__MGIOL \Vout[4]_MGIOL ( .IOLDO(\Vout_c[4] ), .OPOS(\RD_in[4] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_3_ \Vout[3]_I ( .IOLDO(\Vout_c[3] ), .Vout3(Vout[3])); + Vout_3__MGIOL \Vout[3]_MGIOL ( .IOLDO(\Vout_c[3] ), .OPOS(\RD_in[3] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_2_ \Vout[2]_I ( .IOLDO(\Vout_c[2] ), .Vout2(Vout[2])); + Vout_2__MGIOL \Vout[2]_MGIOL ( .IOLDO(\Vout_c[2] ), .OPOS(\RD_in[2] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_1_ \Vout[1]_I ( .IOLDO(\Vout_c[1] ), .Vout1(Vout[1])); + Vout_1__MGIOL \Vout[1]_MGIOL ( .IOLDO(\Vout_c[1] ), .OPOS(\RD_in[1] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_0_ \Vout[0]_I ( .IOLDO(\Vout_c[0] ), .Vout0(Vout[0])); + Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), + .CE(Vout3), .CLK(C14M_c)); + nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE)); + Dout_7_ \Dout[7]_I ( .IOLDO(\Dout_c[7] ), .Dout7(Dout[7])); + Dout_7__MGIOL \Dout[7]_MGIOL ( .IOLDO(\Dout_c[7] ), .OPOS(\RD_in[7] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_6_ \Dout[6]_I ( .IOLDO(\Dout_c[6] ), .Dout6(Dout[6])); + Dout_6__MGIOL \Dout[6]_MGIOL ( .IOLDO(\Dout_c[6] ), .OPOS(\RD_in[6] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_5_ \Dout[5]_I ( .IOLDO(\Dout_c[5] ), .Dout5(Dout[5])); + Dout_5__MGIOL \Dout[5]_MGIOL ( .IOLDO(\Dout_c[5] ), .OPOS(\RD_in[5] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_4_ \Dout[4]_I ( .IOLDO(\Dout_c[4] ), .Dout4(Dout[4])); + Dout_4__MGIOL \Dout[4]_MGIOL ( .IOLDO(\Dout_c[4] ), .OPOS(\RD_in[4] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_3_ \Dout[3]_I ( .IOLDO(\Dout_c[3] ), .Dout3(Dout[3])); + Dout_3__MGIOL \Dout[3]_MGIOL ( .IOLDO(\Dout_c[3] ), .OPOS(\RD_in[3] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_2_ \Dout[2]_I ( .IOLDO(\Dout_c[2] ), .Dout2(Dout[2])); + Dout_2__MGIOL \Dout[2]_MGIOL ( .IOLDO(\Dout_c[2] ), .OPOS(\RD_in[2] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_1_ \Dout[1]_I ( .IOLDO(\Dout_c[1] ), .Dout1(Dout[1])); + Dout_1__MGIOL \Dout[1]_MGIOL ( .IOLDO(\Dout_c[1] ), .OPOS(\RD_in[1] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_0_ \Dout[0]_I ( .IOLDO(\Dout_c[0] ), .Dout0(Dout[0])); + Dout_0__MGIOL \Dout[0]_MGIOL ( .IOLDO(\Dout_c[0] ), .OPOS(\RD_in[0] ), + .CE(N_576_i), .CLK(C14M_c)); + Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0])); + Ain_7_ \Ain[7]_I ( .PADDI(\Ain_c[7] ), .Ain7(Ain[7])); + Ain_6_ \Ain[6]_I ( .PADDI(\Ain_c[6] ), .Ain6(Ain[6])); + Ain_5_ \Ain[5]_I ( .PADDI(\Ain_c[5] ), .Ain5(Ain[5])); + Ain_4_ \Ain[4]_I ( .PADDI(\Ain_c[4] ), .Ain4(Ain[4])); + Ain_3_ \Ain[3]_I ( .PADDI(\Ain_c[3] ), .Ain3(Ain[3])); + Ain_2_ \Ain[2]_I ( .PADDI(\Ain_c[2] ), .Ain2(Ain[2])); + Ain_1_ \Ain[1]_I ( .PADDI(\Ain_c[1] ), .Ain1(Ain[1])); + Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0])); + nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X)); + nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80)); + nWE80 nWE80_I( .PADDI(nWE80_c), .nWE80(nWE80)); + nWE nWE_I( .PADDI(nWE_c), .nWE(nWE)); + PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1)); + PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1reg)); + ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), .WBRSTI(wb_rst), + .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), + .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), + .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), + .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), + .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), + .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), + .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), + .WBDATO2(\wb_dato[2] ), .WBDATO3(\wb_dato[3] ), .WBDATO4(\wb_dato[4] ), + .WBDATO5(\wb_dato[5] ), .WBDATO6(\wb_dato[6] ), .WBDATO7(\wb_dato[7] ), + .WBACKO(wb_ack)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); +endmodule + +module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly; + + vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h000A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20001 \FS_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5002; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_9 ( input C1, B1, A1, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut4 S_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40003 \CmdTout_3_0_a2[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40003 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40004 \CS_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 \CS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0006 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40004 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA9AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_11 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40007 \CS_RNO_0[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 \CS_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0006 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6C6C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_12 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40009 CmdBitbangMXO2_4_u_0_0_a2_0_1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 CmdBitbangMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdBitbangMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_13 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 un1_CS_0_sqmuxa_0_0_a2_7( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 CmdExecMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdExecMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40012 CmdLEDGet_4_u_0_0_a2_0_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 CmdLEDGet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_15 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40013 CmdLEDSet_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40014 CmdLEDSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_16 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40007 CmdBitbangMXO2_4_u_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 CmdRWMaskSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_17 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40015 CmdSetRWBankFFLED_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40014 CmdSetRWBankFFLED_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_18 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 CmdSetRWBankFFLED_4_u_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 CmdSetRWBankFFMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre CmdSetRWBankFFMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_19 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40016 \CmdTout_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40017 \CmdTout_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CmdTout[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h006A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0606) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40018 \S_RNII9DO1_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40019 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre DOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_21 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40020 \RA_0io_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 LEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_22 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40020 \RA_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 \RA_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40014 \RWBank_5_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \RWBank_5_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_24 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40014 \RWBank_5_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \RWBank_5_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_25 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40014 \RWBank_5_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \RWBank_5_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_26 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40022 \RWBank_5_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \RWBank_5_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_27 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40023 \RWMask_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40023 \RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7474) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_28 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40023 \RWMask_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40023 \RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40023 \RWMask_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40023 \RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40021 \RWMask_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40023 \RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40024 nDOE_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 RWSel_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40026 Ready_0_sqmuxa_0_a2_6_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 Ready_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output + F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40028 \S_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40029 \S_s_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFBA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output + F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40030 \S_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40031 \S_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \S[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5510) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40032 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40032 \wb_adr_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40033 \wb_adr_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40033 \wb_adr_RNO[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_37 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40034 \wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 \wb_adr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_38 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40033 \wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 \wb_adr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_39 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40035 wb_cyc_stb_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40022 wb_cyc_stb_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h000E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40036 \wb_dati_7_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 \wb_dati_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_41 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \wb_dati_7_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40036 \wb_dati_7_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40036 \wb_dati_7_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 \wb_dati_7_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_43 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40039 \wb_dati_7_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 \wb_dati_7_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_44 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40011 wb_req_RNO_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 wb_req_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_45 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40027 \un1_LEDEN13_2_i_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40003 wb_rst8_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0006 wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40042 wb_we_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40043 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40044 DQMH_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 \S_RNII9DO1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40045 Vout3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 nCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40015 un1_CS_0_sqmuxa_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40047 un1_CS_0_sqmuxa_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40048 \wb_dati_7_0_a2_0_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40049 \wb_dati_7_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0D00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40050 CKE_6_iv_i_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40051 CKE_6_iv_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2F2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40052 \un1_LEDEN13_2_i_a2_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40053 \un1_LEDEN13_2_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40054 \un1_wb_adr_0_sqmuxa_2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40055 wb_we_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3FF5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40056 un1_CS_0_sqmuxa_0_0_a2_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40057 un1_CS_0_sqmuxa_0_0_o2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40058 nCS_6_u_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 un1_nCS61_1_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_56 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40059 \wb_dati_7_0_a2_5[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40060 \wb_dati_7_0_a2_6[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40061 \un1_LEDEN13_2_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40062 \S_RNII9DO1_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40063 \wb_dati_7_0_2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 \wb_dati_7_0_2_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4440) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40064 DQML_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40065 DQML_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7377) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_60 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40066 \wb_adr_RNO_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40009 \wb_adr_RNO_3[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2A20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_61 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40011 \wb_dati_7_0_a2_2_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40067 \FS_RNIOD6E_1[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40068 \wb_adr_RNO_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40069 \wb_adr_RNO_2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9595) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40039 \un1_LEDEN13_2_i_o2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \FS_RNI9FGA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40070 \FS_RNI6JJA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40013 \un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40007 \wb_dati_7_0_a2_0_0[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 \wb_dati_7_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_66 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40003 \FS_RNIJ9MH[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 wb_we_RNO_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 wb_reqc_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 wb_reqc_1_RNIRU4M1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40073 \wb_dati_7_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40015 \FS_RNIOD6E_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40074 \RA_42_0[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40075 \RA_42_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0208) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40063 \wb_dati_7_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40076 \FS_RNIOD6E[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40076 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40077 nRWE_r_0_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 \S_RNII9DO1_3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40026 Ready_0_sqmuxa_0_a2_6_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 \FS_RNI5OOF1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40078 \wb_adr_7_0_a2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40067 \FS_RNIK5632[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40078 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut4 \wb_dati_7_0_a2_5[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 \wb_dati_7_0_a2_5_RNIC22J[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_75 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40015 nCS_6_u_i_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 nCS_6_u_i_a2_4_RNI3A062( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 nCS_6_u_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 nCS_6_u_i_a2_4_RNICJKD2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40009 un1_CS_0_sqmuxa_0_0_a2_10( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40079 un1_CS_0_sqmuxa_0_0_2_RNIQS7F( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40079 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0103) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 nCAS_s_i_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 nCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40080 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40081 nCS_6_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40003 nCS_0io_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0212) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40082 nRAS_2_iv_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40083 nRAS_2_iv_i( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40082 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1212) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40083 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40018 un1_CS_0_sqmuxa_0_0_a2_1_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40047 un1_CS_0_sqmuxa_0_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40084 un1_CS_0_sqmuxa_0_0_a2_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 un1_CS_0_sqmuxa_0_0_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40084 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40025 nCS_6_u_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40085 nCS_6_u_i_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40085 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40086 \wb_dati_7_0_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40053 \wb_dati_7_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40086 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40087 \wb_adr_7_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 \wb_adr_7_0_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40087 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40067 \wb_dati_7_0_a2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 \un1_LEDEN_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40013 un1_CS_0_sqmuxa_0_0_a2_4_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 un1_CS_0_sqmuxa_0_0_a2_4( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40088 \FS_RNI9Q57[13] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40085 \wb_dati_7_0_o2_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40088 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 \wb_adr_7_0_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 \wb_adr_7_0_a2_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40089 \wb_dati_7_0_o2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 \wb_dati_7_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40089 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_91 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40015 un1_CS_0_sqmuxa_0_0_a2_2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 un1_CS_0_sqmuxa_0_0_a2_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40090 \wb_adr_7_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40091 \wb_adr_7_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40090 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40091 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40092 un1_CS_0_sqmuxa_0_0_a2_1_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40068 un1_CS_0_sqmuxa_0_0_a2_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40092 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40026 un1_CS_0_sqmuxa_0_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40065 un1_CS_0_sqmuxa_0_0_a2_3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40056 wb_we_RNO_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40093 wb_we_RNO_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40093 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40094 \RA_42_i_o2[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40095 \RA_0io_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40094 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40095 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_97 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40033 \wb_dati_7_0_a2_1[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 CKE_6_iv_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_98 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40096 un1_CS_0_sqmuxa_0_0_a2_16( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 un1_CS_0_sqmuxa_0_0_a2_4_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40096 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_99 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40003 un1_CS_0_sqmuxa_0_0_a2_12( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40013 un1_CS_0_sqmuxa_0_0_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_100 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40011 un1_CS_0_sqmuxa_0_0_a2_17( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40009 CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40097 wb_reqc_1_RNIEO5C1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40098 \S_RNII9DO1_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40097 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40098 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC289) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40099 \S_s_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 \BA_0io_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40099 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD550) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40056 \RA_0io_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 wb_req_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40065 \wb_dati_7_0_a2_3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40100 \wb_adr_7_0_a2_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40100 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40101 \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40045 \wb_dati_7_0_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40101 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_106 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40102 \S_RNINI6S[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40103 CKE_6_iv_i_0_1_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40103 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_107 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40102 \S_r_i_o2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 \BA_0io_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_108 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40007 \wb_adr_7_0_a2_5_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 \wb_dati_7_0_a2[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40104 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40037 \wb_dati_7_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 \wb_dati_7_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40105 \RA_0io_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 CmdBitbangMXO2_RNI8CSO1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40105 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0023) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_111 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40106 \RA_42_3_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 \RA_0io_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40106 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hABAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_112 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40107 nCS_6_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40020 \RA_0io_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40107 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40020 \RA_0io_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 \RA_0io_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40073 \wb_dati_7_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 \un1_RWMask_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 nWE80_pad_RNI3ICD( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40108 nRWE_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40108 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_116 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40102 \wb_adr_7_0_o2_2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40109 \wb_dati_7_0_a2_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40109 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_117 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40093 \RWBank_5_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40110 LED_pad_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40110 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_118 ( input B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40003 un1_CS_0_sqmuxa_0_0_a2_11( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40033 un1_CS_0_sqmuxa_0_0_a2_13( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_119 ( input D0, C0, B0, A0, output F0 ); + + lut40026 Ready_0_sqmuxa_0_a2_6_a2_2_0( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module xo2iobuf ( input I, T, output Z, PAD, input PADI ); + + IB INST1( .I(PADI), .O(Z)); + OBW INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module LED ( input PADDO, output LED ); + + xo2iobuf0111 LED_pad( .I(PADDO), .PAD(LED)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0111 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module C14M ( output PADDI, input C14M ); + + xo2iobuf0112 C14M_pad( .Z(PADDI), .PAD(C14M)); + + specify + (C14M => PADDI) = (0:0:0,0:0:0); + $width (posedge C14M, 0:0:0); + $width (negedge C14M, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0112 ( output Z, input PAD ); + + IB INST1( .I(PAD), .O(Z)); +endmodule + +module DQMH ( input IOLDO, output DQMH ); + + xo2iobuf0111 DQMH_pad( .I(IOLDO), .PAD(DQMH)); + + specify + (IOLDO => DQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module DQMH_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre DQMH_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre ( input D0, SP, CK, LSR, output Q ); + + FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module DQML ( input IOLDO, output DQML ); + + xo2iobuf0111 DQML_pad( .I(IOLDO), .PAD(DQML)); + + specify + (IOLDO => DQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module DQML_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre DQML_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + xo2iobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + xo2iobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + xo2iobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + xo2iobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + xo2iobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + xo2iobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RA_11_ ( input IOLDO, output RA11 ); + + xo2iobuf0111 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); + + specify + (IOLDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0113 \RA_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0113 ( input D0, SP, CK, LSR, output Q ); + + FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module RA_10_ ( input IOLDO, output RA10 ); + + xo2iobuf0111 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); + + specify + (IOLDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0113 \RA_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_9_ ( input IOLDO, output RA9 ); + + xo2iobuf0111 \RA_pad[9] ( .I(IOLDO), .PAD(RA9)); + + specify + (IOLDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0113 \RA_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_8_ ( input IOLDO, output RA8 ); + + xo2iobuf0111 \RA_pad[8] ( .I(IOLDO), .PAD(RA8)); + + specify + (IOLDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0113 \RA_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_7_ ( input IOLDO, output RA7 ); + + xo2iobuf0111 \RA_pad[7] ( .I(IOLDO), .PAD(RA7)); + + specify + (IOLDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_6_ ( input IOLDO, output RA6 ); + + xo2iobuf0111 \RA_pad[6] ( .I(IOLDO), .PAD(RA6)); + + specify + (IOLDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_5_ ( input IOLDO, output RA5 ); + + xo2iobuf0111 \RA_pad[5] ( .I(IOLDO), .PAD(RA5)); + + specify + (IOLDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_4_ ( input IOLDO, output RA4 ); + + xo2iobuf0111 \RA_pad[4] ( .I(IOLDO), .PAD(RA4)); + + specify + (IOLDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + + xo2iobuf0111 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input IOLDO, output RA2 ); + + xo2iobuf0111 \RA_pad[2] ( .I(IOLDO), .PAD(RA2)); + + specify + (IOLDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_1_ ( input IOLDO, output RA1 ); + + xo2iobuf0111 \RA_pad[1] ( .I(IOLDO), .PAD(RA1)); + + specify + (IOLDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + + xo2iobuf0111 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_1_ ( input IOLDO, output BA1 ); + + xo2iobuf0111 \BA_pad[1] ( .I(IOLDO), .PAD(BA1)); + + specify + (IOLDO => BA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); + wire VCCI, OPOS_dly, CLK_dly, LSR_dly; + + mfflsre0114 \BA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_dly), .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0114 ( input D0, SP, CK, LSR, output Q ); + + FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module BA_0_ ( input IOLDO, output BA0 ); + + xo2iobuf0111 \BA_pad[0] ( .I(IOLDO), .PAD(BA0)); + + specify + (IOLDO => BA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); + wire VCCI, OPOS_dly, CLK_dly, LSR_dly; + + mfflsre0114 \BA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_dly), .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRWE ( input IOLDO, output nRWE ); + + xo2iobuf0111 nRWE_pad( .I(IOLDO), .PAD(nRWE)); + + specify + (IOLDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nCAS ( input IOLDO, output nCAS ); + + xo2iobuf0111 nCAS_pad( .I(IOLDO), .PAD(nCAS)); + + specify + (IOLDO => nCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nCAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRAS ( input IOLDO, output nRAS ); + + xo2iobuf0111 nRAS_pad( .I(IOLDO), .PAD(nRAS)); + + specify + (IOLDO => nRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nCS ( input IOLDO, output nCS ); + + xo2iobuf0111 nCS_pad( .I(IOLDO), .PAD(nCS)); + + specify + (IOLDO => nCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nCS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CKE ( input IOLDO, output CKE ); + + xo2iobuf0111 CKE_pad( .I(IOLDO), .PAD(CKE)); + + specify + (IOLDO => CKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CKE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0113 CKE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nVOE ( input PADDO, output nVOE ); + + xo2iobuf0111 nVOE_pad( .I(PADDO), .PAD(nVOE)); + + specify + (PADDO => nVOE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_7_ ( input IOLDO, output Vout7 ); + + xo2iobuf0111 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7)); + + specify + (IOLDO => Vout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module Vout_6_ ( input IOLDO, output Vout6 ); + + xo2iobuf0111 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6)); + + specify + (IOLDO => Vout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_5_ ( input IOLDO, output Vout5 ); + + xo2iobuf0111 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5)); + + specify + (IOLDO => Vout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_4_ ( input IOLDO, output Vout4 ); + + xo2iobuf0111 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4)); + + specify + (IOLDO => Vout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_3_ ( input IOLDO, output Vout3 ); + + xo2iobuf0111 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3)); + + specify + (IOLDO => Vout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_2_ ( input IOLDO, output Vout2 ); + + xo2iobuf0111 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2)); + + specify + (IOLDO => Vout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_1_ ( input IOLDO, output Vout1 ); + + xo2iobuf0111 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1)); + + specify + (IOLDO => Vout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_0_ ( input IOLDO, output Vout0 ); + + xo2iobuf0111 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0)); + + specify + (IOLDO => Vout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module nDOE ( input PADDO, output nDOE ); + + xo2iobuf0111 nDOE_pad( .I(PADDO), .PAD(nDOE)); + + specify + (PADDO => nDOE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input IOLDO, output Dout7 ); + + xo2iobuf0115 \Dout_pad[7] ( .I(IOLDO), .PAD(Dout7)); + + specify + (IOLDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0115 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module Dout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_6_ ( input IOLDO, output Dout6 ); + + xo2iobuf0115 \Dout_pad[6] ( .I(IOLDO), .PAD(Dout6)); + + specify + (IOLDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_5_ ( input IOLDO, output Dout5 ); + + xo2iobuf0115 \Dout_pad[5] ( .I(IOLDO), .PAD(Dout5)); + + specify + (IOLDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_4_ ( input IOLDO, output Dout4 ); + + xo2iobuf0115 \Dout_pad[4] ( .I(IOLDO), .PAD(Dout4)); + + specify + (IOLDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_3_ ( input IOLDO, output Dout3 ); + + xo2iobuf0115 \Dout_pad[3] ( .I(IOLDO), .PAD(Dout3)); + + specify + (IOLDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_2_ ( input IOLDO, output Dout2 ); + + xo2iobuf0115 \Dout_pad[2] ( .I(IOLDO), .PAD(Dout2)); + + specify + (IOLDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_1_ ( input IOLDO, output Dout1 ); + + xo2iobuf0115 \Dout_pad[1] ( .I(IOLDO), .PAD(Dout1)); + + specify + (IOLDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_0_ ( input IOLDO, output Dout0 ); + + xo2iobuf0115 \Dout_pad[0] ( .I(IOLDO), .PAD(Dout0)); + + specify + (IOLDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + xo2iobuf0112 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + xo2iobuf0112 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + xo2iobuf0112 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + xo2iobuf0112 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + xo2iobuf0112 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + xo2iobuf0112 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + xo2iobuf0112 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + xo2iobuf0112 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module Ain_7_ ( output PADDI, input Ain7 ); + + xo2iobuf0112 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7)); + + specify + (Ain7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain7, 0:0:0); + $width (negedge Ain7, 0:0:0); + endspecify + +endmodule + +module Ain_6_ ( output PADDI, input Ain6 ); + + xo2iobuf0112 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6)); + + specify + (Ain6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain6, 0:0:0); + $width (negedge Ain6, 0:0:0); + endspecify + +endmodule + +module Ain_5_ ( output PADDI, input Ain5 ); + + xo2iobuf0112 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5)); + + specify + (Ain5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain5, 0:0:0); + $width (negedge Ain5, 0:0:0); + endspecify + +endmodule + +module Ain_4_ ( output PADDI, input Ain4 ); + + xo2iobuf0112 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4)); + + specify + (Ain4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain4, 0:0:0); + $width (negedge Ain4, 0:0:0); + endspecify + +endmodule + +module Ain_3_ ( output PADDI, input Ain3 ); + + xo2iobuf0112 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3)); + + specify + (Ain3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain3, 0:0:0); + $width (negedge Ain3, 0:0:0); + endspecify + +endmodule + +module Ain_2_ ( output PADDI, input Ain2 ); + + xo2iobuf0112 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2)); + + specify + (Ain2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain2, 0:0:0); + $width (negedge Ain2, 0:0:0); + endspecify + +endmodule + +module Ain_1_ ( output PADDI, input Ain1 ); + + xo2iobuf0112 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1)); + + specify + (Ain1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain1, 0:0:0); + $width (negedge Ain1, 0:0:0); + endspecify + +endmodule + +module Ain_0_ ( output PADDI, input Ain0 ); + + xo2iobuf0112 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0)); + + specify + (Ain0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain0, 0:0:0); + $width (negedge Ain0, 0:0:0); + endspecify + +endmodule + +module nC07X ( output PADDI, input nC07X ); + + xo2iobuf0112 nC07X_pad( .Z(PADDI), .PAD(nC07X)); + + specify + (nC07X => PADDI) = (0:0:0,0:0:0); + $width (posedge nC07X, 0:0:0); + $width (negedge nC07X, 0:0:0); + endspecify + +endmodule + +module nEN80 ( output PADDI, input nEN80 ); + + xo2iobuf0112 nEN80_pad( .Z(PADDI), .PAD(nEN80)); + + specify + (nEN80 => PADDI) = (0:0:0,0:0:0); + $width (posedge nEN80, 0:0:0); + $width (negedge nEN80, 0:0:0); + endspecify + +endmodule + +module nWE80 ( output PADDI, input nWE80 ); + + xo2iobuf0112 nWE80_pad( .Z(PADDI), .PAD(nWE80)); + + specify + (nWE80 => PADDI) = (0:0:0,0:0:0); + $width (posedge nWE80, 0:0:0); + $width (negedge nWE80, 0:0:0); + endspecify + +endmodule + +module nWE ( output PADDI, input nWE ); + + xo2iobuf0112 nWE_pad( .Z(PADDI), .PAD(nWE)); + + specify + (nWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nWE, 0:0:0); + $width (negedge nWE, 0:0:0); + endspecify + +endmodule + +module PHI1 ( output PADDI, input PHI1 ); + + xo2iobuf0112 PHI1_pad( .Z(PADDI), .PAD(PHI1)); + + specify + (PHI1 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI1, 0:0:0); + $width (negedge PHI1, 0:0:0); + endspecify + +endmodule + +module PHI1_MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre PHI1reg_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module smuxlregsre ( input D0, SP, CK, LSR, output Q ); + + IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, + WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, + WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output + WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, + WBACKO ); + wire VCCI, GNDI; + + EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), + .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), + .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), + .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), + .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), + .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), + .WBDATO1(WBDATO1), .WBDATO2(WBDATO2), .WBDATO3(WBDATO3), .WBDATO4(WBDATO4), + .WBDATO5(WBDATO5), .WBDATO6(WBDATO6), .WBDATO7(WBDATO7), .WBACKO(WBACKO), + .WBCUFMIRQ(), .UFMSN(VCCI), .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), + .I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), + .I2C2SCLI(GNDI), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), + .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), + .SPISCKEN(), .SPIMISOI(GNDI), .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), + .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), + .SPIMCSN3(), .SPIMCSN4(), .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), + .SPICSNEN(), .SPISCSN(GNDI), .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), + .TCIC(GNDI), .TCINT(), .TCOC(), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), + .PLL1STBO(), .PLLWEO(), .PLLADRO0(), .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), + .PLLADRO4(), .PLLDATO0(), .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), + .PLLDATO4(), .PLLDATO5(), .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), + .PLL0DATI1(GNDI), .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), + .PLL0DATI5(GNDI), .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), + .PLL1DATI0(GNDI), .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), + .PLL1DATI4(GNDI), .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), + .PLL1ACKI(GNDI)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); +endmodule + +module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, + WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, + WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, + WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, + WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output + I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input + I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, + I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, + input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output + SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, + SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, + input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, + PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, + PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, + PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, + PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, + PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI ); + wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, + WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, + WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, + WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, + WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, + PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, + PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, + PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, + PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, + I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, + SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, + UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, + WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, + PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, + PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, + PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, + PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, + I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, + I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, + I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, + SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, + SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, + SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, + CFGWAKE_buf, CFGSTDBY_buf; + + EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), + .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), + .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), + .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), + .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), + .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), + .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), + .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), + .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), + .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), + .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), + .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), + .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), + .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), + .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), + .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), + .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), + .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), + .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), + .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), + .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), + .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), + .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), + .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), + .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), + .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), + .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), + .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), + .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), + .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), + .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), + .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), + .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), + .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), + .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), + .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), + .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), + .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), + .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), + .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), + .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), + .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf)); + defparam INST10.DEV_DENSITY = "1200L"; + defparam INST10.EFB_I2C1 = "DISABLED"; + defparam INST10.EFB_I2C2 = "DISABLED"; + defparam INST10.EFB_SPI = "DISABLED"; + defparam INST10.EFB_TC = "DISABLED"; + defparam INST10.EFB_TC_PORTMODE = "WB"; + defparam INST10.EFB_UFM = "ENABLED"; + defparam INST10.EFB_WB_CLK_FREQ = "14.4"; + defparam INST10.GSR = "ENABLED"; + defparam INST10.I2C1_ADDRESSING = "7BIT"; + defparam INST10.I2C1_BUS_PERF = "100kHz"; + defparam INST10.I2C1_CLK_DIVIDER = 1; + defparam INST10.I2C1_GEN_CALL = "DISABLED"; + defparam INST10.I2C1_SLAVE_ADDR = "0b1000001"; + defparam INST10.I2C1_WAKEUP = "DISABLED"; + defparam INST10.I2C2_ADDRESSING = "7BIT"; + defparam INST10.I2C2_BUS_PERF = "100kHz"; + defparam INST10.I2C2_CLK_DIVIDER = 1; + defparam INST10.I2C2_GEN_CALL = "DISABLED"; + defparam INST10.I2C2_SLAVE_ADDR = "0b1000010"; + defparam INST10.I2C2_WAKEUP = "DISABLED"; + defparam INST10.SPI_CLK_DIVIDER = 1; + defparam INST10.SPI_CLK_INV = "DISABLED"; + defparam INST10.SPI_INTR_RXOVR = "DISABLED"; + defparam INST10.SPI_INTR_RXRDY = "DISABLED"; + defparam INST10.SPI_INTR_TXOVR = "DISABLED"; + defparam INST10.SPI_INTR_TXRDY = "DISABLED"; + defparam INST10.SPI_LSB_FIRST = "DISABLED"; + defparam INST10.SPI_MODE = "MASTER"; + defparam INST10.SPI_PHASE_ADJ = "DISABLED"; + defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED"; + defparam INST10.SPI_WAKEUP = "DISABLED"; + defparam INST10.TC_CCLK_SEL = 1; + defparam INST10.TC_ICAPTURE = "DISABLED"; + defparam INST10.TC_ICR_INT = "OFF"; + defparam INST10.TC_MODE = "CTCM"; + defparam INST10.TC_OCR_INT = "OFF"; + defparam INST10.TC_OCR_SET = 32767; + defparam INST10.TC_OC_MODE = "TOGGLE"; + defparam INST10.TC_OVERFLOW = "DISABLED"; + defparam INST10.TC_OV_INT = "OFF"; + defparam INST10.TC_RESETN = "ENABLED"; + defparam INST10.TC_SCLK_SEL = "PCLOCK"; + defparam INST10.TC_TOP_SEL = "OFF"; + defparam INST10.TC_TOP_SET = 65535; + defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED"; + defparam INST10.UFM_INIT_FILE_FORMAT = "HEX"; + defparam INST10.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem"; + defparam INST10.UFM_INIT_PAGES = 321; + defparam INST10.UFM_INIT_START_PAGE = 190; + EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), + .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), + .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), + .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), + .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), + .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), + .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), + .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), + .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), + .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), + .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), + .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), + .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), + .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), + .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), + .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), + .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), + .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), + .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), + .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), + .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), + .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), + .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), + .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), + .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), + .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), + .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), + .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), + .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), + .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), + .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), + .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), + .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), + .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), + .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), + .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), + .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), + .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), + .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), + .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), + .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), + .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), + .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), + .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), + .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), + .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), + .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), + .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), + .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), + .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), + .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), + .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), + .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), + .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), + .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), + .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), + .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), + .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), + .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), + .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), + .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), + .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), + .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), + .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), + .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), + .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), + .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), + .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), + .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), + .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), + .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), + .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), + .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), + .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), + .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), + .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), + .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), + .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), + .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), + .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), + .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), + .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), + .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), + .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), + .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), + .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), + .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), + .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), + .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), + .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), + .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), + .CFGSTDBYin(CFGSTDBY_buf)); +endmodule + +module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, + output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, + output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output + WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output + WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output + WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output + WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output + WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output + WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output + WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output + WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output + PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, + output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input + PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, + input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output + PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, + output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input + PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, + input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output + PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, + output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input + I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, + input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, + input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, + input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, + input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input + TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input + WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input + WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input + WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input + WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input + WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input + PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, + input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, + input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, + input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, + input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, + input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, + input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, + input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, + input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output + I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, + output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input + I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, + input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output + I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, + output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, + output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input + SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, + input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output + SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, + output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, + output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, + output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, + output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, + output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, + output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin ); + wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, + WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, + WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, + WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, + WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly; + + BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout)); + BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout)); + BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout)); + BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout)); + BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout)); + BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out)); + BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out)); + BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out)); + BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out)); + BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out)); + BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out)); + BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out)); + BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out)); + BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out)); + BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out)); + BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out)); + BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out)); + BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out)); + BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out)); + BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out)); + BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out)); + BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out)); + BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out)); + BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out)); + BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out)); + BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out)); + BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out)); + BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out)); + BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out)); + BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout)); + BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out)); + BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out)); + BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out)); + BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out)); + BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out)); + BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out)); + BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out)); + BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out)); + BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout)); + BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout)); + BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout)); + BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout)); + BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout)); + BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout)); + BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout)); + BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout)); + BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout)); + BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout)); + BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout)); + BUFBA TCIC_buf( .A(TCICin), .Z(TCICout)); + BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout)); + BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out)); + BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out)); + BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out)); + BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out)); + BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out)); + BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out)); + BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out)); + BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out)); + BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout)); + BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout)); + BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout)); + BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout)); + BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout)); + BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout)); + BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out)); + BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out)); + BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out)); + BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out)); + BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out)); + BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out)); + BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out)); + BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out)); + BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out)); + BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out)); + BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out)); + BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out)); + BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out)); + BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout)); + BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout)); + BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout)); + BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout)); + BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout)); + BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout)); + BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout)); + BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout)); + BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout)); + BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout)); + BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout)); + BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout)); + BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout)); + BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout)); + BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout)); + BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout)); + BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out)); + BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out)); + BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out)); + BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out)); + BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out)); + BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out)); + BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out)); + BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out)); + BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout)); + BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout)); + BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout)); + BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout)); + BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout)); + BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout)); + BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout)); + + specify + (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO2out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO3out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO4out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO5out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO6out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO7out) = (0:0:0,0:0:0); + (WBCLKIin => WBACKOout) = (0:0:0,0:0:0); + $setuphold + (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly); + $setuphold + (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly); + $setuphold + (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly); + $setuphold + (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly); + $setuphold + (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly); + $setuphold + (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly); + $setuphold + (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly); + $setuphold + (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly); + $setuphold + (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly); + $setuphold + (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly); + $setuphold + (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly); + $setuphold + (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly); + $setuphold + (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly); + $setuphold + (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly); + $setuphold + (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly); + $setuphold + (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly); + $setuphold + (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly); + $setuphold + (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly); + $setuphold + (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly); + $setuphold + (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly); + $width (posedge WBCLKIin, 0:0:0); + $width (negedge WBCLKIin, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html new file mode 100644 index 0000000..9a7029b --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_mrp.html @@ -0,0 +1,485 @@ + +Project Summary + + +

+            Lattice Mapping Report File for Design Module 'RAM2E'
+
+
+
+Design Information
+
+Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 4 -oc Commercial
+     RAM2E_LCMXO2_1200HC_impl1.ngd -o RAM2E_LCMXO2_1200HC_impl1_map.ncd -pr
+     RAM2E_LCMXO2_1200HC_impl1.prf -mp RAM2E_LCMXO2_1200HC_impl1.mrp -lpf //Mac/
+     iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synpl
+     ify.lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui
+     -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-1200HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  09/21/23  05:34:46
+
+
+Design Summary
+   Number of registers:    111 out of  1520 (7%)
+      PFU registers:           75 out of  1280 (6%)
+      PIO registers:           36 out of   240 (15%)
+   Number of SLICEs:       120 out of   640 (19%)
+      SLICEs as Logic/ROM:    120 out of   640 (19%)
+      SLICEs as RAM:            0 out of   480 (0%)
+      SLICEs as Carry:          9 out of   640 (1%)
+   Number of LUT4s:        239 out of  1280 (19%)
+      Number used as logic LUTs:        221
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of PIO sites used: 70 + 4(JTAG) out of 80 (93%)
+   Number of block RAMs:  0 out of 7 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        Yes
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Number of PLLs:  0 out of 1 (0%)
+   Number of DQSDLLs:  0 out of 2 (0%)
+   Number of CLKDIVC:  0 out of 4 (0%)
+   Number of ECLKSYNCA:  0 out of 4 (0%)
+   Number of ECLKBRIDGECS:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  1
+     Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
+   Number of Clock Enables:  11
+
+     Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
+     Net N_576_i: 17 loads, 9 LSLICEs
+     Net LEDEN13: 4 loads, 4 LSLICEs
+     Net nCS61: 1 loads, 1 LSLICEs
+     Net Vout3: 8 loads, 0 LSLICEs
+     Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
+     Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
+     Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
+     Net N_104: 1 loads, 1 LSLICEs
+     Net N_88: 4 loads, 4 LSLICEs
+     Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
+   Number of LSRs:  5
+     Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
+     Net S[2]: 1 loads, 1 LSLICEs
+     Net N_566_i: 2 loads, 0 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
+     Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net S[2]: 48 loads
+     Net S[3]: 48 loads
+     Net S[0]: 30 loads
+     Net FS[12]: 22 loads
+     Net FS[9]: 21 loads
+     Net S[1]: 21 loads
+     Net FS[10]: 20 loads
+     Net FS[11]: 19 loads
+     Net RWSel: 19 loads
+     Net FS[13]: 17 loads
+
+
+
+
+   Number of warnings:  1
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+     temporarily disable certain features of the device including Power
+     Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
+     Functionality is restored after the Flash Memory (UFM/Configuration)
+     Interface is disabled using Disable Configuration Interface command 0x26
+     followed by Bypass command 0xFF. 
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+
+| LED                 | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| C14M                | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| DQML                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[5]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[2]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[10]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[9]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[8]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[7]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[6]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[5]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[4]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[3]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[2]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[1]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[0]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| BA[1]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| BA[0]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRWE                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nCAS                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRAS                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+
+| nCS                 | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| CKE                 | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nVOE                | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Vout[7]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[6]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[5]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[4]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[3]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[2]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[1]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[0]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nDOE                | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[6]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Din[7]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[6]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[5]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[4]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[3]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[2]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[1]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[0]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+
+| Ain[7]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[6]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[5]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[4]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[3]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[2]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[1]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[0]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nC07X               | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nEN80               | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nWE80               | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nWE                 | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| PHI1                | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+
+
+
+Removed logic
+
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal Dout_0_.CN was merged into signal C14M_c
+Signal GND undriven or does not drive anything - clipped.
+Signal ufmefb/VCC undriven or does not drive anything - clipped.
+Signal ufmefb/GND undriven or does not drive anything - clipped.
+Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
+Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
+Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
+Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
+Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
+Signal ufmefb/TCOC undriven or does not drive anything - clipped.
+Signal ufmefb/TCINT undriven or does not drive anything - clipped.
+Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
+Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
+
+Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
+Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
+Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
+Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
+Signal N_1 undriven or does not drive anything - clipped.
+Block Vout_0_.CN was optimized away.
+Block GND was optimized away.
+Block ufmefb/VCC was optimized away.
+Block ufmefb/GND was optimized away.
+
+     
+
+
+
+Embedded Functional Block Connection Summary
+
+   Desired WISHBONE clock frequency: 14.4 MHz
+   Clock source:                     C14M_c
+   Reset source:                     wb_rst
+   Functions mode:
+      I2C #1 (Primary) Function:     DISABLED
+      I2C #2 (Secondary) Function:   DISABLED
+      SPI Function:                  DISABLED
+      Timer/Counter Function:        DISABLED
+      Timer/Counter Mode:            WB
+      UFM Connection:                ENABLED
+      PLL0 Connection:               DISABLED
+      PLL1 Connection:               DISABLED
+   I2C Function Summary:
+   --------------------
+
+      None
+   SPI Function Summary:
+   --------------------
+      None
+   Timer/Counter Function Summary:
+   ------------------------------
+      None
+   UFM Function Summary:
+   --------------------
+      UFM Utilization:        General Purpose Flash Memory
+      Initialized UFM Pages:  321 Pages (321*128 Bits)
+      Available General
+      Purpose Flash Memory:   511 Pages (511*128 Bits)
+
+           EBR Blocks with Unique
+      Initialization Data:    0
+
+           WID		EBR Instance
+      ---		------------
+
+
+
+
+ASIC Components
+---------------
+
+Instance Name: ufmefb/EFBInst_0
+         Type: EFB
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 1 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 63 MB
+        
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
+
+

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+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html new file mode 100644 index 0000000..81a51b2 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_pad.html @@ -0,0 +1,380 @@ + +PAD Specification File + + +
PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-1200HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.44
+
+Thu Sep 21 05:34:59 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                                 |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| Ain[0]    | 3/3      | LVCMOS33_IN   | PL3A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[1]    | 2/3      | LVCMOS33_IN   | PL2D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[2]    | 7/3      | LVCMOS33_IN   | PL3C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[3]    | 4/3      | LVCMOS33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[4]    | 78/0     | LVCMOS33_IN   | PT16C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[5]    | 84/0     | LVCMOS33_IN   | PT15A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[6]    | 86/0     | LVCMOS33_IN   | PT12C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[7]    | 8/3      | LVCMOS33_IN   | PL3D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| BA[0]     | 58/1     | LVCMOS33_OUT  | PR9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| BA[1]     | 60/1     | LVCMOS33_OUT  | PR8C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| C14M      | 62/1     | LVCMOS33_IN   | PR5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| CKE       | 53/1     | LVCMOS33_OUT  | PR9D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| DQMH      | 49/2     | LVCMOS33_OUT  | PB20D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| DQML      | 48/2     | LVCMOS33_OUT  | PB20C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Din[0]    | 96/0     | LVCMOS33_IN   | PT10B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[1]    | 97/0     | LVCMOS33_IN   | PT10A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[2]    | 98/0     | LVCMOS33_IN   | PT9B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[3]    | 9/3      | LVCMOS33_IN   | PL4A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[4]    | 1/3      | LVCMOS33_IN   | PL2C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[5]    | 99/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[6]    | 88/0     | LVCMOS33_IN   | PT12A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[7]    | 87/0     | LVCMOS33_IN   | PT12B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4C  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL10D |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL10C |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL9B  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6C  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| LED       | 35/2     | LVCMOS33_OUT  | PB9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| PHI1      | 85/0     | LVCMOS33_IN   | PT12D |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[0]     | 66/1     | LVCMOS33_OUT  | PR4D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[10]    | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[11]    | 59/1     | LVCMOS33_OUT  | PR8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[1]     | 68/1     | LVCMOS33_OUT  | PR4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[2]     | 70/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[3]     | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[4]     | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[5]     | 71/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[6]     | 69/1     | LVCMOS33_OUT  | PR4A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[7]     | 67/1     | LVCMOS33_OUT  | PR4C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[8]     | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[9]     | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RD[0]     | 36/2     | LVCMOS33_BIDI | PB11C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVCMOS33_BIDI | PB11D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVCMOS33_BIDI | PB11A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVCMOS33_BIDI | PB11B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVCMOS33_BIDI | PB15A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVCMOS33_BIDI | PB15B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVCMOS33_BIDI | PB18A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVCMOS33_BIDI | PB18B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| Vout[0]   | 18/3     | LVCMOS33_OUT  | PL8C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[1]   | 15/3     | LVCMOS33_OUT  | PL5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[2]   | 17/3     | LVCMOS33_OUT  | PL8B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[3]   | 13/3     | LVCMOS33_OUT  | PL5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[4]   | 19/3     | LVCMOS33_OUT  | PL8D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[5]   | 16/3     | LVCMOS33_OUT  | PL8A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[6]   | 14/3     | LVCMOS33_OUT  | PL5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[7]   | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nC07X     | 34/2     | LVCMOS33_IN   | PB9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nCAS      | 52/1     | LVCMOS33_OUT  | PR10C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nCS       | 57/1     | LVCMOS33_OUT  | PR9B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nDOE      | 20/3     | LVCMOS33_OUT  | PL9A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nEN80     | 82/0     | LVCMOS33_IN   | PT15C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nRAS      | 54/1     | LVCMOS33_OUT  | PR9C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWE      | 51/1     | LVCMOS33_OUT  | PR10D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nVOE      | 10/3     | LVCMOS33_OUT  | PL4B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nWE       | 29/2     | LVCMOS33_IN   | PB6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nWE80     | 83/0     | LVCMOS33_IN   | PT15B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[4]                | LOCATED    | LVCMOS33_IN   | PL2C  | L_GPLLT_IN    |           |           |
+| 2/3      | Ain[1]                | LOCATED    | LVCMOS33_IN   | PL2D  | L_GPLLC_IN    |           |           |
+| 3/3      | Ain[0]                | LOCATED    | LVCMOS33_IN   | PL3A  | PCLKT3_2      |           |           |
+| 4/3      | Ain[3]                | LOCATED    | LVCMOS33_IN   | PL3B  | PCLKC3_2      |           |           |
+| 7/3      | Ain[2]                | LOCATED    | LVCMOS33_IN   | PL3C  |               |           |           |
+| 8/3      | Ain[7]                | LOCATED    | LVCMOS33_IN   | PL3D  |               |           |           |
+| 9/3      | Din[3]                | LOCATED    | LVCMOS33_IN   | PL4A  |               |           |           |
+| 10/3     | nVOE                  | LOCATED    | LVCMOS33_OUT  | PL4B  |               |           |           |
+| 12/3     | Vout[7]               | LOCATED    | LVCMOS33_OUT  | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | Vout[3]               | LOCATED    | LVCMOS33_OUT  | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | Vout[6]               | LOCATED    | LVCMOS33_OUT  | PL5C  |               |           |           |
+| 15/3     | Vout[1]               | LOCATED    | LVCMOS33_OUT  | PL5D  |               |           |           |
+| 16/3     | Vout[5]               | LOCATED    | LVCMOS33_OUT  | PL8A  |               |           |           |
+| 17/3     | Vout[2]               | LOCATED    | LVCMOS33_OUT  | PL8B  |               |           |           |
+| 18/3     | Vout[0]               | LOCATED    | LVCMOS33_OUT  | PL8C  |               |           |           |
+| 19/3     | Vout[4]               | LOCATED    | LVCMOS33_OUT  | PL8D  |               |           |           |
+| 20/3     | nDOE                  | LOCATED    | LVCMOS33_OUT  | PL9A  | PCLKT3_0      |           |           |
+| 21/3     | Dout[5]               | LOCATED    | LVCMOS33_OUT  | PL9B  | PCLKC3_0      |           |           |
+| 24/3     | Dout[4]               | LOCATED    | LVCMOS33_OUT  | PL10C |               |           |           |
+| 25/3     | Dout[2]               | LOCATED    | LVCMOS33_OUT  | PL10D |               |           |           |
+| 27/2     | Dout[1]               | LOCATED    | LVCMOS33_OUT  | PB4C  | CSSPIN        |           |           |
+| 28/2     | Dout[3]               | LOCATED    | LVCMOS33_OUT  | PB4D  |               |           |           |
+| 29/2     | nWE                   | LOCATED    | LVCMOS33_IN   | PB6A  |               |           |           |
+| 30/2     | Dout[0]               | LOCATED    | LVCMOS33_OUT  | PB6B  |               |           |           |
+| 31/2     | Dout[6]               | LOCATED    | LVCMOS33_OUT  | PB6C  | MCLK/CCLK     |           |           |
+| 32/2     | Dout[7]               | LOCATED    | LVCMOS33_OUT  | PB6D  | SO/SPISO      |           |           |
+| 34/2     | nC07X                 | LOCATED    | LVCMOS33_IN   | PB9A  | PCLKT2_0      |           |           |
+| 35/2     | LED                   | LOCATED    | LVCMOS33_OUT  | PB9B  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVCMOS33_BIDI | PB11C |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVCMOS33_BIDI | PB11D |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVCMOS33_BIDI | PB11A | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVCMOS33_BIDI | PB11B | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVCMOS33_BIDI | PB15A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVCMOS33_BIDI | PB15B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVCMOS33_BIDI | PB18A |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVCMOS33_BIDI | PB18B |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |               | PB18C |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |               | PB18D |               |           |           |
+| 48/2     | DQML                  | LOCATED    | LVCMOS33_OUT  | PB20C | SN            |           |           |
+| 49/2     | DQMH                  | LOCATED    | LVCMOS33_OUT  | PB20D | SI/SISPI      |           |           |
+| 51/1     | nRWE                  | LOCATED    | LVCMOS33_OUT  | PR10D | DQ1           |           |           |
+| 52/1     | nCAS                  | LOCATED    | LVCMOS33_OUT  | PR10C | DQ1           |           |           |
+| 53/1     | CKE                   | LOCATED    | LVCMOS33_OUT  | PR9D  | DQ1           |           |           |
+| 54/1     | nRAS                  | LOCATED    | LVCMOS33_OUT  | PR9C  | DQ1           |           |           |
+| 57/1     | nCS                   | LOCATED    | LVCMOS33_OUT  | PR9B  | DQ1           |           |           |
+| 58/1     | BA[0]                 | LOCATED    | LVCMOS33_OUT  | PR9A  | DQ1           |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVCMOS33_OUT  | PR8D  | DQ1           |           |           |
+| 60/1     | BA[1]                 | LOCATED    | LVCMOS33_OUT  | PR8C  | DQ1           |           |           |
+| 61/1     |     unused, PULL:DOWN |            |               | PR8A  | DQS1          |           |           |
+| 62/1     | C14M                  | LOCATED    | LVCMOS33_IN   | PR5D  | PCLKC1_0/DQ0  |           |           |
+| 63/1     | RA[9]                 | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0/DQ0  |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVCMOS33_OUT  | PR5B  | DQS0N         |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVCMOS33_OUT  | PR5A  | DQS0          |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVCMOS33_OUT  | PR4D  | DQ0           |           |           |
+| 67/1     | RA[7]                 | LOCATED    | LVCMOS33_OUT  | PR4C  | DQ0           |           |           |
+| 68/1     | RA[1]                 | LOCATED    | LVCMOS33_OUT  | PR4B  | DQ0           |           |           |
+| 69/1     | RA[6]                 | LOCATED    | LVCMOS33_OUT  | PR4A  | DQ0           |           |           |
+| 70/1     | RA[2]                 | LOCATED    | LVCMOS33_OUT  | PR3B  | DQ0           |           |           |
+| 71/1     | RA[5]                 | LOCATED    | LVCMOS33_OUT  | PR3A  | DQ0           |           |           |
+| 74/1     | RA[3]                 | LOCATED    | LVCMOS33_OUT  | PR2B  | DQ0           |           |           |
+| 75/1     | RA[4]                 | LOCATED    | LVCMOS33_OUT  | PR2A  | DQ0           |           |           |
+| 76/0     |     unused, PULL:DOWN |            |               | PT17D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |               | PT17C | INITN         |           |           |
+| 78/0     | Ain[4]                | LOCATED    | LVCMOS33_IN   | PT16C |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |               | PT15D | PROGRAMN      |           |           |
+| 82/0     | nEN80                 | LOCATED    | LVCMOS33_IN   | PT15C | JTAGENB       |           |           |
+| 83/0     | nWE80                 | LOCATED    | LVCMOS33_IN   | PT15B |               |           |           |
+| 84/0     | Ain[5]                | LOCATED    | LVCMOS33_IN   | PT15A |               |           |           |
+| 85/0     | PHI1                  | LOCATED    | LVCMOS33_IN   | PT12D | SDA/PCLKC0_0  |           |           |
+| 86/0     | Ain[6]                | LOCATED    | LVCMOS33_IN   | PT12C | SCL/PCLKT0_0  |           |           |
+| 87/0     | Din[7]                | LOCATED    | LVCMOS33_IN   | PT12B | PCLKC0_1      |           |           |
+| 88/0     | Din[6]                | LOCATED    | LVCMOS33_IN   | PT12A | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT11D | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT11C | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT10D | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT10C | TDO           |           |           |
+| 96/0     | Din[0]                | LOCATED    | LVCMOS33_IN   | PT10B |               |           |           |
+| 97/0     | Din[1]                | LOCATED    | LVCMOS33_IN   | PT10A |               |           |           |
+| 98/0     | Din[2]                | LOCATED    | LVCMOS33_IN   | PT9B  |               |           |           |
+| 99/0     | Din[5]                | LOCATED    | LVCMOS33_IN   | PT9A  |               |           |           |
+| PB4A/2   |     unused, PULL:DOWN |            |               | PB4A  |               |           |           |
+| PB4B/2   |     unused, PULL:DOWN |            |               | PB4B  |               |           |           |
+| PB9C/2   |     unused, PULL:DOWN |            |               | PB9C  |               |           |           |
+| PB9D/2   |     unused, PULL:DOWN |            |               | PB9D  |               |           |           |
+| PB15C/2  |     unused, PULL:DOWN |            |               | PB15C |               |           |           |
+| PB15D/2  |     unused, PULL:DOWN |            |               | PB15D |               |           |           |
+| PB20A/2  |     unused, PULL:DOWN |            |               | PB20A |               |           |           |
+| PB20B/2  |     unused, PULL:DOWN |            |               | PB20B |               |           |           |
+| PL2A/3   |     unused, PULL:DOWN |            |               | PL2A  | L_GPLLT_FB    |           |           |
+| PL2B/3   |     unused, PULL:DOWN |            |               | PL2B  | L_GPLLC_FB    |           |           |
+| PL4C/3   |     unused, PULL:DOWN |            |               | PL4C  |               |           |           |
+| PL4D/3   |     unused, PULL:DOWN |            |               | PL4D  |               |           |           |
+| PL10A/3  |     unused, PULL:DOWN |            |               | PL10A |               |           |           |
+| PL10B/3  |     unused, PULL:DOWN |            |               | PL10B |               |           |           |
+| PR2C/1   |     unused, PULL:DOWN |            |               | PR2C  | DQ0           |           |           |
+| PR2D/1   |     unused, PULL:DOWN |            |               | PR2D  | DQ0           |           |           |
+| PR8B/1   |     unused, PULL:DOWN |            |               | PR8B  | DQS1N         |           |           |
+| PR10A/1  |     unused, PULL:DOWN |            |               | PR10A | DQ1           |           |           |
+| PR10B/1  |     unused, PULL:DOWN |            |               | PR10B | DQ1           |           |           |
+| PT9C/0   |     unused, PULL:DOWN |            |               | PT9C  |               |           |           |
+| PT9D/0   |     unused, PULL:DOWN |            |               | PT9D  |               |           |           |
+| PT11A/0  |     unused, PULL:DOWN |            |               | PT11A |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
+| PT16A/0  |     unused, PULL:DOWN |            |               | PT16A |               |           |           |
+| PT16B/0  |     unused, PULL:DOWN |            |               | PT16B |               |           |           |
+| PT16D/0  |     unused, PULL:DOWN |            |               | PT16D |               |           |           |
+| PT17A/0  |     unused, PULL:DOWN |            |               | PT17A |               |           |           |
+| PT17B/0  |     unused, PULL:DOWN |            |               | PT17B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT11D    | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT11C    | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT10D    | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT10C    | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "Ain[0]"  SITE  "3";
+LOCATE  COMP  "Ain[1]"  SITE  "2";
+LOCATE  COMP  "Ain[2]"  SITE  "7";
+LOCATE  COMP  "Ain[3]"  SITE  "4";
+LOCATE  COMP  "Ain[4]"  SITE  "78";
+LOCATE  COMP  "Ain[5]"  SITE  "84";
+LOCATE  COMP  "Ain[6]"  SITE  "86";
+LOCATE  COMP  "Ain[7]"  SITE  "8";
+LOCATE  COMP  "BA[0]"  SITE  "58";
+LOCATE  COMP  "BA[1]"  SITE  "60";
+LOCATE  COMP  "C14M"  SITE  "62";
+LOCATE  COMP  "CKE"  SITE  "53";
+LOCATE  COMP  "DQMH"  SITE  "49";
+LOCATE  COMP  "DQML"  SITE  "48";
+LOCATE  COMP  "Din[0]"  SITE  "96";
+LOCATE  COMP  "Din[1]"  SITE  "97";
+LOCATE  COMP  "Din[2]"  SITE  "98";
+LOCATE  COMP  "Din[3]"  SITE  "9";
+LOCATE  COMP  "Din[4]"  SITE  "1";
+LOCATE  COMP  "Din[5]"  SITE  "99";
+LOCATE  COMP  "Din[6]"  SITE  "88";
+LOCATE  COMP  "Din[7]"  SITE  "87";
+LOCATE  COMP  "Dout[0]"  SITE  "30";
+LOCATE  COMP  "Dout[1]"  SITE  "27";
+LOCATE  COMP  "Dout[2]"  SITE  "25";
+LOCATE  COMP  "Dout[3]"  SITE  "28";
+LOCATE  COMP  "Dout[4]"  SITE  "24";
+LOCATE  COMP  "Dout[5]"  SITE  "21";
+LOCATE  COMP  "Dout[6]"  SITE  "31";
+LOCATE  COMP  "Dout[7]"  SITE  "32";
+LOCATE  COMP  "LED"  SITE  "35";
+LOCATE  COMP  "PHI1"  SITE  "85";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "68";
+LOCATE  COMP  "RA[2]"  SITE  "70";
+LOCATE  COMP  "RA[3]"  SITE  "74";
+LOCATE  COMP  "RA[4]"  SITE  "75";
+LOCATE  COMP  "RA[5]"  SITE  "71";
+LOCATE  COMP  "RA[6]"  SITE  "69";
+LOCATE  COMP  "RA[7]"  SITE  "67";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "63";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "Vout[0]"  SITE  "18";
+LOCATE  COMP  "Vout[1]"  SITE  "15";
+LOCATE  COMP  "Vout[2]"  SITE  "17";
+LOCATE  COMP  "Vout[3]"  SITE  "13";
+LOCATE  COMP  "Vout[4]"  SITE  "19";
+LOCATE  COMP  "Vout[5]"  SITE  "16";
+LOCATE  COMP  "Vout[6]"  SITE  "14";
+LOCATE  COMP  "Vout[7]"  SITE  "12";
+LOCATE  COMP  "nC07X"  SITE  "34";
+LOCATE  COMP  "nCAS"  SITE  "52";
+LOCATE  COMP  "nCS"  SITE  "57";
+LOCATE  COMP  "nDOE"  SITE  "20";
+LOCATE  COMP  "nEN80"  SITE  "82";
+LOCATE  COMP  "nRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "51";
+LOCATE  COMP  "nVOE"  SITE  "10";
+LOCATE  COMP  "nWE"  SITE  "29";
+LOCATE  COMP  "nWE80"  SITE  "83";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Sep 21 05:35:04 2023
+
+
+
+
+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+
+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html new file mode 100644 index 0000000..e56b9bc --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_par.html @@ -0,0 +1,299 @@ + +Place & Route Report + + +
PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Sep 21 05:34:51 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_1200HC_impl1.p2t
+RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir
+RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset
+//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml
+
+
+Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            57.121       0            0.333        0            15           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 15 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2E_LCMXO2_1200HC_impl1_map.ncd"
+Thu Sep 21 05:34:51 2023
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_1200HC_impl1.prf
+Preference file: RAM2E_LCMXO2_1200HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2E_LCMXO2_1200HC_impl1_map.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)   70+4(JTAG)/108     69% used
+                  70+4(JTAG)/80      93% bonded
+   IOLOGIC           36/108          33% used
+
+   SLICE            120/640          18% used
+
+   EFB                1/1           100% used
+
+
+Number of Signals: 395
+Number of Connections: 1126
+
+Pin Constraint Summary:
+   70 out of 70 pins locked (100% locked).
+
+The following 1 signal is selected to use the primary clock routing resources:
+    C14M_c (driver: C14M, clk load #: 84)
+
+WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    N_576_i (driver: SLICE_20, clk load #: 0, sr load #: 0, ce load #: 17)
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+........
+Finished Placer Phase 0.  REAL time: 2 secs 
+
+Starting Placer Phase 1.
+..................
+Placer score = 78271.
+Finished Placer Phase 1.  REAL time: 8 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  77117
+Finished Placer Phase 2.  REAL time: 8 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 0 out of 8 (0%)
+  General PIO: 1 out of 108 (0%)
+  PLL        : 0 out of 1 (0%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 84
+  SECONDARY "N_576_i" from F1 on comp "SLICE_20" on site "R7C12C", clk load = 0, ce load = 17, sr load = 0
+
+  PRIMARY  : 1 out of 8 (12%)
+  SECONDARY: 1 out of 8 (12%)
+
+Edge Clocks:
+  No edge clock selected.
+
+
+
+
+I/O Usage Summary (final):
+   70 + 4(JTAG) out of 108 (68.5%) PIO sites used.
+   70 + 4(JTAG) out of 80 (92.5%) bonded PIO sites used.
+   Number of PIO comps: 70; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 12 / 19 ( 63%) | 3.3V       | -         |
+| 1        | 20 / 21 ( 95%) | 3.3V       | -         |
+| 2        | 18 / 20 ( 90%) | 3.3V       | -         |
+| 3        | 20 / 20 (100%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 7 secs 
+
+Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 1126 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+Completed router resource preassignment. Real time: 13 secs 
+
+Start NBR router at 05:35:04 09/21/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 05:35:05 09/21/23
+
+Start NBR section for initial routing at 05:35:05 09/21/23
+Level 4, iteration 1
+13(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 05:35:05 09/21/23
+Level 4, iteration 1
+4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs 
+Level 4, iteration 2
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 05:35:05 09/21/23
+
+Start NBR section for re-routing at 05:35:05 09/21/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 57.121ns/0.000ns; real time: 14 secs 
+
+Start NBR section for post-routing at 05:35:05 09/21/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : 57.121ns
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 14 secs 
+Total REAL time: 15 secs 
+Completely routed.
+End of route.  1126 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2E_LCMXO2_1200HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = 57.121
+PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.333
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 15 secs 
+Total REAL time to completion: 15 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
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+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt new file mode 100644 index 0000000..9586c36 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_scck.rpt @@ -0,0 +1,51 @@ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 + +# Written on Thu Sep 21 05:34:37 2023 + +##### FILES SYNTAX CHECKED ############################################## +Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc" + +#Run constraint checker to find more issues with constraints. +######################################################################### + + + +No issues found in constraint syntax. + + + +Clock Summary +************* + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------- +0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111 + +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +======================================================================================== + + +Clock Load Summary +****************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +---------------------------------------------------------------------------------------- +C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv) + +System 0 - - - - +======================================================================================== diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html new file mode 100644 index 0000000..03c1e47 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +

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RAM2E_LCMXO2_1200HC project summary
Module Name:RAM2E_LCMXO2_1200HCSynthesis:SynplifyPro
Implementation Name:impl1Strategy Name:Strategy1
Last Process:JEDEC FileState:Passed
Target Device:LCMXO2-1200HC-4TG100CDevice Family:MachXO2
Device Type:LCMXO2-1200HCPackage Type:TQFP100
Performance grade:4Operating conditions:COM
Logic preference file:RAM2E-LCMXO2.lpf
Physical Preference file:impl1/RAM2E_LCMXO2_1200HC_impl1.prf
Product Version:3.12.1.454Patch Version:
Updated:2023/09/21 05:35:26
Implementation Location://Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1
Project File://Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/RAM2E_LCMXO2_1200HC.ldf

+

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+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html new file mode 100644 index 0000000..9195ff3 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_synplify.html @@ -0,0 +1,755 @@ + +Synthesis Report + + +
Synthesis Report
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Thu Sep 21 05:34:34 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
+@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v" (library work)
+Verilog syntax check successful!
+
+Compiler output is up to date.  No re-compile necessary
+
+Selecting top level module RAM2E
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
+Running optimization stage 1 on RAM2E .......
+Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
+Running optimization stage 2 on RAM2E .......
+Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 97MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Sep 21 05:34:34 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Sep 21 05:34:34 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Sep 21 05:34:34 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Sep 21 05:34:36 2023
+
+###########################################################]
+# Thu Sep 21 05:34:36 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 141MB)
+
+Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
+@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt 
+See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 136MB peak: 141MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
+
+@N: FX493 |Applying initial value "0" on instance PHI1reg.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance DOEEN.
+@N: FX493 |Applying initial value "0" on instance RWSel.
+@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
+@N: FX493 |Applying initial value "1" on instance DQMH.
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
+@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
+@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
+@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
+@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
+@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
+@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "0000" on instance S[3:0].
+@N: FX493 |Applying initial value "1" on instance DQML.
+@N: FX493 |Applying initial value "0" on instance CKE.
+@N: FX493 |Applying initial value "1" on instance nCS.
+@N: FX493 |Applying initial value "1" on instance nRAS.
+@N: FX493 |Applying initial value "1" on instance nCAS.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 182MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=7 on top level netlist RAM2E 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 181MB peak: 182MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     111  
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+           Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin            Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+C14M       111       C14M(port)     wb_rst.C        -                 un1_C14M.I[0](inv)
+                                                                                        
+System     0         -              -               -                 -                 
+========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       C14M                port                   111        nCAS           
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:01s cputime
+# Thu Sep 21 05:34:38 2023
+
+###########################################################]
+# Thu Sep 21 05:34:38 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 179MB peak: 179MB)
+
+@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+
+@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+
+Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:02s		    29.35ns		 222 /       111
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
+
+Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\synwork\RAM2E_LCMXO2_1200HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-1200HC\impl1\RAM2E_LCMXO2_1200HC_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:03s; Memory used current: 211MB peak: 211MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
+
+@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-1200hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@N: MT615 |Found clock C14M with period 69.84ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Thu Sep 21 05:34:44 2023
+#
+
+
+Top view:               RAM2E
+Requested Frequency:    14.3 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 31.782
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+C14M               14.3 MHz      131.4 MHz     69.841        7.610         31.782     declared     default_clkgroup
+System             100.0 MHz     NA            10.000        NA            67.088     system       system_clkgroup 
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise 
+----------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack
+----------------------------------------------------------------------------------------------------------
+System    C14M    |  69.841      67.088  |  No paths    -      |  No paths    -       |  No paths    -    
+C14M      System  |  69.841      68.797  |  No paths    -      |  No paths    -       |  No paths    -    
+C14M      C14M    |  69.841      62.231  |  No paths    -      |  34.920      31.782  |  No paths    -    
+==========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: C14M
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                     Arrival           
+Instance     Reference     Type        Pin     Net        Time        Slack 
+             Clock                                                          
+----------------------------------------------------------------------------
+S[2]         C14M          FD1S3AX     Q       S[2]       1.350       31.782
+S[3]         C14M          FD1S3AX     Q       S[3]       1.350       31.782
+S[0]         C14M          FD1S3AX     Q       S[0]       1.312       31.820
+S[1]         C14M          FD1S3AX     Q       S[1]       1.280       31.852
+FS[9]        C14M          FD1S3AX     Q       FS[9]      1.284       62.425
+FS[11]       C14M          FD1S3AX     Q       FS[11]     1.276       62.433
+FS[8]        C14M          FD1S3AX     Q       FS[8]      1.260       62.449
+FS[12]       C14M          FD1S3AX     Q       FS[12]     1.288       62.525
+FS[10]       C14M          FD1S3AX     Q       FS[10]     1.280       62.533
+RWSel        C14M          FD1P3AX     Q       RWSel      1.276       63.482
+============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                Starting                                       Required           
+Instance        Reference     Type         Pin     Net         Time         Slack 
+                Clock                                                             
+----------------------------------------------------------------------------------
+Dout_0io[0]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[1]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[2]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[3]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[4]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[5]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[6]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[7]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Vout_0io[0]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
+Vout_0io[1]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
+==================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      34.920
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         34.449
+
+    - Propagation time:                      2.667
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     31.782
+
+    Number of logic level(s):                1
+    Starting point:                          S[2] / Q
+    Ending point:                            Dout_0io[0] / SP
+    The start point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
+    The end   point is clocked by            C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+S[2]                FD1S3AX      Q        Out     1.350     1.350 r     -         
+S[2]                Net          -        -       -         -           48        
+S_RNII9DO1_2[1]     ORCALUT4     B        In      0.000     1.350 r     -         
+S_RNII9DO1_2[1]     ORCALUT4     Z        Out     1.317     2.667 r     -         
+N_576_i             Net          -        -       -         -           18        
+Dout_0io[0]         OFS1P3DX     SP       In      0.000     2.667 r     -         
+==================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                                          Required           
+Instance       Reference     Type        Pin     Net                             Time         Slack 
+               Clock                                                                                
+----------------------------------------------------------------------------------------------------
+RWMask[0]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[1]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[2]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[3]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[4]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[5]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[6]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[7]      System        FD1P3AX     SP      N_88                            69.369       67.088
+LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0[0]     69.369       67.736
+wb_cyc_stb     System        FD1P3AX     SP      N_104                           69.369       67.736
+====================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      69.841
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         69.369
+
+    - Propagation time:                      2.282
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 67.088
+
+    Number of logic level(s):                2
+    Starting point:                          ufmefb.EFBInst_0 / WBACKO
+    Ending point:                            RWMask[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
+
+Instance / Net                                     Pin        Pin               Arrival     No. of    
+Name                                  Type         Name       Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------------------------
+ufmefb.EFBInst_0                      EFB          WBACKO     Out     0.000     0.000 r     -         
+wb_ack                                Net          -          -       -         -           5         
+un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     A          In      0.000     0.000 r     -         
+un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     Z          Out     1.017     1.017 r     -         
+un1_RWMask_0_sqmuxa_1_i_a2_0_1[0]     Net          -          -       -         -           1         
+un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
+un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
+N_88                                  Net          -          -       -         -           8         
+RWMask[0]                             FD1P3AX      SP         In      0.000     2.282 r     -         
+======================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_1200hc-4
+
+Register bits: 111 of 1280 (9%)
+PIC Latch:       0
+I/O cells:       70
+
+
+Details:
+BB:             8
+CCU2D:          9
+EFB:            1
+FD1P3AX:        48
+FD1P3IX:        1
+FD1S3AX:        22
+FD1S3IX:        4
+GSR:            1
+IB:             22
+IFS1P3DX:       1
+INV:            1
+OB:             40
+OFS1P3BX:       6
+OFS1P3DX:       27
+OFS1P3IX:       2
+ORCALUT4:       221
+PUR:            1
+VHI:            2
+VLO:            2
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 78MB peak: 211MB)
+
+Process took 0h:00m:06s realtime, 0h:00m:04s cputime
+# Thu Sep 21 05:34:44 2023
+
+###########################################################]
+
+
+
+

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+ + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html new file mode 100644 index 0000000..8c77acf --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_tw1.html @@ -0,0 +1,289 @@ + +Lattice Map TRACE Report + + +
Map TRACE Report
+
+Loading design for application trce from file ram2e_lcmxo2_1200hc_impl1_map.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Thu Sep 21 05:34:48 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2e_lcmxo2_1200hc_impl1_map.ncd
+Preference file: ram2e_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1491 items scored, 0 timing errors detected.
+Report:   87.268MHz is the maximum frequency for this preference.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
+            1491 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 58.471ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[11]  (from C14M_c +)
+   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+
+   Delay:              11.306ns  (30.3% logic, 69.7% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     69.930ns delay constraint less
+      0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452    SLICE_3.CLK to     SLICE_3.Q0 SLICE_3 (from C14M_c)
+ROUTE        19   e 1.234     SLICE_3.Q0 to    SLICE_64.A1 FS[11]
+CTOF_DEL    ---     0.495    SLICE_64.A1 to    SLICE_64.F1 SLICE_64
+ROUTE         4   e 1.234    SLICE_64.F1 to    SLICE_97.D0 N_577
+CTOF_DEL    ---     0.495    SLICE_97.D0 to    SLICE_97.F0 SLICE_97
+ROUTE         3   e 1.234    SLICE_97.F0 to    SLICE_75.D1 N_489
+CTOF_DEL    ---     0.495    SLICE_75.D1 to    SLICE_75.F1 SLICE_75
+ROUTE         3   e 0.480    SLICE_75.F1 to    SLICE_75.A0 N_628
+CTOF_DEL    ---     0.495    SLICE_75.A0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.234    SLICE_75.F0 to    SLICE_71.C1 N_640
+CTOF_DEL    ---     0.495    SLICE_71.C1 to    SLICE_71.F1 SLICE_71
+ROUTE         1   e 1.234    SLICE_71.F1 to   SLICE_115.A0 un1_nCS61_1_i
+CTOF_DEL    ---     0.495   SLICE_115.A0 to   SLICE_115.F0 SLICE_115
+ROUTE         1   e 1.234   SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
+                  --------
+                   11.306   (30.3% logic, 69.7% route), 7 logic levels.
+
+Report:   87.268MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   87.268 MHz|   7  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 1 clocks:
+
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Thu Sep 21 05:34:49 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_1200HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1_map.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2e_lcmxo2_1200hc_impl1_map.ncd
+Preference file: ram2e_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1491 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
+            1491 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[0]  (from C14M_c +)
+   Destination:    FF         Data in        FS[0]  (to C14M_c +)
+
+   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.434ns physical path delay SLICE_0 to SLICE_0 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    SLICE_0.CLK to     SLICE_0.Q1 SLICE_0 (from C14M_c)
+ROUTE         5   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
+CTOF_DEL    ---     0.101     SLICE_0.A1 to     SLICE_0.F1 SLICE_0
+ROUTE         1   e 0.001     SLICE_0.F1 to    SLICE_0.DI1 FS_s[0] (to C14M_c)
+                  --------
+                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 1 clocks:
+
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
+
+
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+
    + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html new file mode 100644 index 0000000..8c6da61 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_twr.html @@ -0,0 +1,1175 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2e_lcmxo2_1200hc_impl1.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-1200HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.44.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Thu Sep 21 05:35:07 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2e_lcmxo2_1200hc_impl1.ncd
+Preference file: ram2e_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1491 items scored, 0 timing errors detected.
+Report:   78.070MHz is the maximum frequency for this preference.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
+            1491 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 57.121ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[8]  (from C14M_c +)
+   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+
+   Delay:              12.829ns  (26.7% logic, 73.3% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.829ns physical path delay SLICE_5 to nRWE_MGIOL meets
+     69.930ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 69.950ns) by 57.121ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9A.CLK to       R5C9A.Q1 SLICE_5 (from C14M_c)
+ROUTE        15     2.743       R5C9A.Q1 to       R4C7B.B1 FS[8]
+CTOF_DEL    ---     0.495       R4C7B.B1 to       R4C7B.F1 SLICE_64
+ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
+CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
+ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
+CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
+ROUTE         3     0.453      R4C11C.F1 to      R4C11C.C0 N_628
+CTOF_DEL    ---     0.495      R4C11C.C0 to      R4C11C.F0 SLICE_75
+ROUTE         2     0.652      R4C11C.F0 to      R5C11B.D1 N_640
+CTOF_DEL    ---     0.495      R5C11B.D1 to      R5C11B.F1 SLICE_71
+ROUTE         1     1.023      R5C11B.F1 to      R5C13A.B0 un1_nCS61_1_i
+CTOF_DEL    ---     0.495      R5C13A.B0 to      R5C13A.F0 SLICE_115
+ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
+                  --------
+                   12.829   (26.7% logic, 73.3% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to      R5C9A.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
+                  --------
+                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 57.346ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        wb_dati[6]  (to C14M_c +)
+
+   Delay:              12.418ns  (27.6% logic, 72.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.418ns physical path delay SLICE_33 to SLICE_43 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.346ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
+ROUTE        30     3.112      R3C11C.Q0 to      R5C12C.B0 S[0]
+CTOF_DEL    ---     0.495      R5C12C.B0 to      R5C12C.F0 SLICE_47
+ROUTE         7     2.060      R5C12C.F0 to       R3C7C.C1 S_RNII9DO1[1]
+CTOF_DEL    ---     0.495       R3C7C.C1 to       R3C7C.F1 SLICE_86
+ROUTE         5     1.174       R3C7C.F1 to       R4C5A.D1 N_484
+CTOF_DEL    ---     0.495       R4C5A.D1 to       R4C5A.F1 SLICE_74
+ROUTE         3     0.984       R4C5A.F1 to       R4C5A.A0 N_642
+CTOF_DEL    ---     0.495       R4C5A.A0 to       R4C5A.F0 SLICE_74
+ROUTE         2     0.665       R4C5A.F0 to       R4C5C.A0 N_346
+CTOF_DEL    ---     0.495       R4C5C.A0 to       R4C5C.F0 SLICE_84
+ROUTE         1     1.001       R4C5C.F0 to       R3C5D.B0 wb_dati_7_0_1[6]
+CTOF_DEL    ---     0.495       R3C5D.B0 to       R3C5D.F0 SLICE_43
+ROUTE         1     0.000       R3C5D.F0 to      R3C5D.DI0 wb_dati_7[6] (to C14M_c)
+                  --------
+                   12.418   (27.6% logic, 72.4% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_43:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to      R3C5D.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 57.382ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[8]  (from C14M_c +)
+   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+
+   Delay:              12.568ns  (23.3% logic, 76.7% route), 6 logic levels.
+
+ Constraint Details:
+
+     12.568ns physical path delay SLICE_5 to nRWE_MGIOL meets
+     69.930ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 69.950ns) by 57.382ns
+
+ Physical Path Details:
+
+      Data path SLICE_5 to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9A.CLK to       R5C9A.Q1 SLICE_5 (from C14M_c)
+ROUTE        15     2.743       R5C9A.Q1 to       R4C7B.B1 FS[8]
+CTOF_DEL    ---     0.495       R4C7B.B1 to       R4C7B.F1 SLICE_64
+ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
+CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
+ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
+CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
+ROUTE         3     1.040      R4C11C.F1 to      R5C11D.B0 N_628
+CTOF_DEL    ---     0.495      R5C11D.B0 to      R5C11D.F0 SLICE_76
+ROUTE         3     1.322      R5C11D.F0 to      R5C13A.A0 nCAS_0_sqmuxa
+CTOF_DEL    ---     0.495      R5C13A.A0 to      R5C13A.F0 SLICE_115
+ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
+                  --------
+                   12.568   (23.3% logic, 76.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_5:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to      R5C9A.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
+                  --------
+                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 57.636ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[9]  (from C14M_c +)
+   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+
+   Delay:              12.314ns  (27.8% logic, 72.2% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.314ns physical path delay SLICE_4 to nRWE_MGIOL meets
+     69.930ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 69.950ns) by 57.636ns
+
+ Physical Path Details:
+
+      Data path SLICE_4 to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9B.CLK to       R5C9B.Q0 SLICE_4 (from C14M_c)
+ROUTE        21     2.228       R5C9B.Q0 to       R4C7B.A1 FS[9]
+CTOF_DEL    ---     0.495       R4C7B.A1 to       R4C7B.F1 SLICE_64
+ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
+CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
+ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
+CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
+ROUTE         3     0.453      R4C11C.F1 to      R4C11C.C0 N_628
+CTOF_DEL    ---     0.495      R4C11C.C0 to      R4C11C.F0 SLICE_75
+ROUTE         2     0.652      R4C11C.F0 to      R5C11B.D1 N_640
+CTOF_DEL    ---     0.495      R5C11B.D1 to      R5C11B.F1 SLICE_71
+ROUTE         1     1.023      R5C11B.F1 to      R5C13A.B0 un1_nCS61_1_i
+CTOF_DEL    ---     0.495      R5C13A.B0 to      R5C13A.F0 SLICE_115
+ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
+                  --------
+                   12.314   (27.8% logic, 72.2% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_4:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to      R5C9B.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
+                  --------
+                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 57.645ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        wb_adr[0]  (to C14M_c +)
+
+   Delay:              12.119ns  (24.2% logic, 75.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     12.119ns physical path delay SLICE_33 to SLICE_35 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 57.645ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
+ROUTE        30     3.112      R3C11C.Q0 to      R5C12C.B0 S[0]
+CTOF_DEL    ---     0.495      R5C12C.B0 to      R5C12C.F0 SLICE_47
+ROUTE         7     2.060      R5C12C.F0 to       R4C7C.C1 S_RNII9DO1[1]
+CTOF_DEL    ---     0.495       R4C7C.C1 to       R4C7C.F1 SLICE_56
+ROUTE         6     2.374       R4C7C.F1 to       R5C7D.A0 N_452
+CTOF_DEL    ---     0.495       R5C7D.A0 to       R5C7D.F0 SLICE_92
+ROUTE         1     0.645       R5C7D.F0 to       R5C5A.D0 wb_adr_7_0_0[0]
+CTOF_DEL    ---     0.495       R5C5A.D0 to       R5C5A.F0 SLICE_85
+ROUTE         1     1.001       R5C5A.F0 to       R4C5B.B0 wb_adr_7_0_4[0]
+CTOF_DEL    ---     0.495       R4C5B.B0 to       R4C5B.F0 SLICE_35
+ROUTE         1     0.000       R4C5B.F0 to      R4C5B.DI0 wb_adr_7[0] (to C14M_c)
+                  --------
+                   12.119   (24.2% logic, 75.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to      R4C5B.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 57.783ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[11]  (from C14M_c +)
+   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+
+   Delay:              12.167ns  (28.1% logic, 71.9% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.167ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     69.930ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 69.950ns) by 57.783ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R5C9C.CLK to       R5C9C.Q0 SLICE_3 (from C14M_c)
+ROUTE        19     2.081       R5C9C.Q0 to       R4C7B.C1 FS[11]
+CTOF_DEL    ---     0.495       R4C7B.C1 to       R4C7B.F1 SLICE_64
+ROUTE         4     0.659       R4C7B.F1 to       R4C6D.D0 N_577
+CTOF_DEL    ---     0.495       R4C6D.D0 to       R4C6D.F0 SLICE_97
+ROUTE         3     1.170       R4C6D.F0 to      R4C11C.D1 N_489
+CTOF_DEL    ---     0.495      R4C11C.D1 to      R4C11C.F1 SLICE_75
+ROUTE         3     0.453      R4C11C.F1 to      R4C11C.C0 N_628
+CTOF_DEL    ---     0.495      R4C11C.C0 to      R4C11C.F0 SLICE_75
+ROUTE         2     0.652      R4C11C.F0 to      R5C11B.D1 N_640
+CTOF_DEL    ---     0.495      R5C11B.D1 to      R5C11B.F1 SLICE_71
+ROUTE         1     1.023      R5C11B.F1 to      R5C13A.B0 un1_nCS61_1_i
+CTOF_DEL    ---     0.495      R5C13A.B0 to      R5C13A.F0 SLICE_115
+ROUTE         1     2.707      R5C13A.F0 to  IOL_R10D.OPOS nRWE_r_0 (to C14M_c)
+                  --------
+                   12.167   (28.1% logic, 71.9% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to      R5C9C.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     5.038       62.PADDI to   IOL_R10D.CLK C14M_c
+                  --------
+                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        Dout_0io[0]  (to C14M_c -)
+
+   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+
+ Constraint Details:
+
+      6.181ns physical path delay SLICE_33 to Dout[0]_MGIOL meets
+     34.965ns delay constraint less
+     -0.173ns skew and
+      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to Dout[0]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
+ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
+CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
+ROUTE        17     2.710      R7C12C.F1 to     IOL_B6B.CE N_576_i (to C14M_c)
+                  --------
+                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to Dout[0]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     5.038       62.PADDI to    IOL_B6B.CLK C14M_c
+                  --------
+                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        Dout_0io[1]  (to C14M_c -)
+
+   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+
+ Constraint Details:
+
+      6.181ns physical path delay SLICE_33 to Dout[1]_MGIOL meets
+     34.965ns delay constraint less
+     -0.173ns skew and
+      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to Dout[1]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
+ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
+CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
+ROUTE        17     2.710      R7C12C.F1 to     IOL_B4C.CE N_576_i (to C14M_c)
+                  --------
+                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to Dout[1]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     5.038       62.PADDI to    IOL_B4C.CLK C14M_c
+                  --------
+                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        Dout_0io[2]  (to C14M_c -)
+
+   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+
+ Constraint Details:
+
+      6.181ns physical path delay SLICE_33 to Dout[2]_MGIOL meets
+     34.965ns delay constraint less
+     -0.173ns skew and
+      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to Dout[2]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
+ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
+CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
+ROUTE        17     2.710      R7C12C.F1 to    IOL_L10D.CE N_576_i (to C14M_c)
+                  --------
+                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to Dout[2]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     5.038       62.PADDI to   IOL_L10D.CLK C14M_c
+                  --------
+                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 28.910ns (weighted slack = 57.820ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        Dout_0io[3]  (to C14M_c -)
+
+   Delay:               6.181ns  (15.3% logic, 84.7% route), 2 logic levels.
+
+ Constraint Details:
+
+      6.181ns physical path delay SLICE_33 to Dout[3]_MGIOL meets
+     34.965ns delay constraint less
+     -0.173ns skew and
+      0.047ns CE_SET requirement (totaling 35.091ns) by 28.910ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to Dout[3]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452     R3C11C.CLK to      R3C11C.Q0 SLICE_33 (from C14M_c)
+ROUTE        30     2.524      R3C11C.Q0 to      R7C12C.B1 S[0]
+CTOF_DEL    ---     0.495      R7C12C.B1 to      R7C12C.F1 SLICE_20
+ROUTE        17     2.710      R7C12C.F1 to     IOL_B4D.CE N_576_i (to C14M_c)
+                  --------
+                    6.181   (15.3% logic, 84.7% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     4.865       62.PADDI to     R3C11C.CLK C14M_c
+                  --------
+                    4.865   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to Dout[3]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     5.038       62.PADDI to    IOL_B4D.CLK C14M_c
+                  --------
+                    5.038   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   78.070MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   78.070 MHz|   7  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 1 clocks:
+
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Thu Sep 21 05:35:07 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_1200HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf 
+Design file:     ram2e_lcmxo2_1200hc_impl1.ncd
+Preference file: ram2e_lcmxo2_1200hc_impl1.prf
+Device,speed:    LCMXO2-1200HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1491 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
+            1491 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.333ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              wb_adr[2]  (from C14M_c +)
+   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
+
+   Delay:               0.306ns  (43.5% logic, 56.5% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.306ns physical path delay SLICE_36 to ufmefb/EFBInst_0 meets
+     -0.081ns WBADRI_HLD and
+      0.000ns delay constraint less
+     -0.054ns skew requirement (totaling -0.027ns) by 0.333ns
+
+ Physical Path Details:
+
+      Data path SLICE_36 to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C5C.CLK to       R2C5C.Q0 SLICE_36 (from C14M_c)
+ROUTE         2     0.173       R2C5C.Q0 to    EFB.WBADRI2 wb_adr[2] (to C14M_c)
+                  --------
+                    0.306   (43.5% logic, 56.5% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_36:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R2C5C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.722       62.PADDI to     EFB.WBCLKI C14M_c
+                  --------
+                    1.722   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.358ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              wb_adr[3]  (from C14M_c +)
+   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
+
+   Delay:               0.307ns  (43.3% logic, 56.7% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.307ns physical path delay SLICE_36 to ufmefb/EFBInst_0 meets
+     -0.105ns WBADRI_HLD and
+      0.000ns delay constraint less
+     -0.054ns skew requirement (totaling -0.051ns) by 0.358ns
+
+ Physical Path Details:
+
+      Data path SLICE_36 to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C5C.CLK to       R2C5C.Q1 SLICE_36 (from C14M_c)
+ROUTE         2     0.174       R2C5C.Q1 to    EFB.WBADRI3 wb_adr[3] (to C14M_c)
+                  --------
+                    0.307   (43.3% logic, 56.7% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_36:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R2C5C.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.722       62.PADDI to     EFB.WBCLKI C14M_c
+                  --------
+                    1.722   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdBitbangMXO2  (from C14M_c +)
+   Destination:    FF         Data in        CmdBitbangMXO2  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_12 to SLICE_12 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_12 to SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7D.CLK to       R4C7D.Q0 SLICE_12 (from C14M_c)
+ROUTE         2     0.132       R4C7D.Q0 to       R4C7D.A0 CmdBitbangMXO2
+CTOF_DEL    ---     0.101       R4C7D.A0 to       R4C7D.F0 SLICE_12
+ROUTE         1     0.000       R4C7D.F0 to      R4C7D.DI0 CmdBitbangMXO2_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R4C7D.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R4C7D.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdExecMXO2  (from C14M_c +)
+   Destination:    FF         Data in        CmdExecMXO2  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_13 to SLICE_13 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_13 to SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C7A.CLK to       R5C7A.Q0 SLICE_13 (from C14M_c)
+ROUTE         4     0.132       R5C7A.Q0 to       R5C7A.A0 CmdExecMXO2
+CTOF_DEL    ---     0.101       R5C7A.A0 to       R5C7A.F0 SLICE_13
+ROUTE         1     0.000       R5C7A.F0 to      R5C7A.DI0 CmdExecMXO2_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R5C7A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_13:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R5C7A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdLEDGet  (from C14M_c +)
+   Destination:    FF         Data in        CmdLEDGet  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_14 to SLICE_14 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_14 to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R7C8A.CLK to       R7C8A.Q0 SLICE_14 (from C14M_c)
+ROUTE         2     0.132       R7C8A.Q0 to       R7C8A.A0 CmdLEDGet
+CTOF_DEL    ---     0.101       R7C8A.A0 to       R7C8A.F0 SLICE_14
+ROUTE         1     0.000       R7C8A.F0 to      R7C8A.DI0 CmdLEDGet_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R7C8A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_14:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R7C8A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdLEDSet  (from C14M_c +)
+   Destination:    FF         Data in        CmdLEDSet  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C7A.CLK to       R3C7A.Q0 SLICE_15 (from C14M_c)
+ROUTE         2     0.132       R3C7A.Q0 to       R3C7A.A0 CmdLEDSet
+CTOF_DEL    ---     0.101       R3C7A.A0 to       R3C7A.F0 SLICE_15
+ROUTE         1     0.000       R3C7A.F0 to      R3C7A.DI0 CmdLEDSet_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R3C7A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R3C7A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdRWMaskSet  (from C14M_c +)
+   Destination:    FF         Data in        CmdRWMaskSet  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_16 to SLICE_16 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C7A.CLK to       R4C7A.Q0 SLICE_16 (from C14M_c)
+ROUTE         2     0.132       R4C7A.Q0 to       R4C7A.A0 CmdRWMaskSet
+CTOF_DEL    ---     0.101       R4C7A.A0 to       R4C7A.F0 SLICE_16
+ROUTE         1     0.000       R4C7A.F0 to      R4C7A.DI0 CmdRWMaskSet_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R4C7A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R4C7A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdSetRWBankFFLED  (from C14M_c +)
+   Destination:    FF         Data in        CmdSetRWBankFFLED  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_17 to SLICE_17 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_17 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R3C8B.CLK to       R3C8B.Q0 SLICE_17 (from C14M_c)
+ROUTE         2     0.132       R3C8B.Q0 to       R3C8B.A0 CmdSetRWBankFFLED
+CTOF_DEL    ---     0.101       R3C8B.A0 to       R3C8B.F0 SLICE_17
+ROUTE         1     0.000       R3C8B.F0 to      R3C8B.DI0 CmdSetRWBankFFLED_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R3C8B.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R3C8B.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdSetRWBankFFMXO2  (from C14M_c +)
+   Destination:    FF         Data in        CmdSetRWBankFFMXO2  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_18 to SLICE_18 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R7C7A.CLK to       R7C7A.Q0 SLICE_18 (from C14M_c)
+ROUTE         2     0.132       R7C7A.Q0 to       R7C7A.A0 CmdSetRWBankFFMXO2
+CTOF_DEL    ---     0.101       R7C7A.A0 to       R7C7A.F0 SLICE_18
+ROUTE         1     0.000       R7C7A.F0 to      R7C7A.DI0 CmdSetRWBankFFMXO2_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R7C7A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R7C7A.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[14]  (from C14M_c +)
+   Destination:    FF         Data in        FS[14]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_2 to SLICE_2 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_2 to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C9D.CLK to       R5C9D.Q1 SLICE_2 (from C14M_c)
+ROUTE        13     0.132       R5C9D.Q1 to       R5C9D.A1 FS[14]
+CTOF_DEL    ---     0.101       R5C9D.A1 to       R5C9D.F1 SLICE_2
+ROUTE         1     0.000       R5C9D.F1 to      R5C9D.DI1 FS_s[14] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R5C9D.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_2:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.668       62.PADDI to      R5C9D.CLK C14M_c
+                  --------
+                    1.668   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   1  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 1 clocks:
+
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
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    + + diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf new file mode 100644 index 0000000..0078982 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.sdf @@ -0,0 +1,4946 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2E") + (DATE "Thu Sep 21 05:35:16 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 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) + ) + (CELL + (CELLTYPE "Ain_7_") + (INSTANCE Ain\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain7 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain7) (3330:3330:3330)) + (WIDTH (negedge Ain7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_6_") + (INSTANCE Ain\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain6 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain6) (3330:3330:3330)) + (WIDTH (negedge Ain6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_5_") + (INSTANCE Ain\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain5 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain5) (3330:3330:3330)) + (WIDTH (negedge Ain5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_4_") + (INSTANCE Ain\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain4 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain4) (3330:3330:3330)) + (WIDTH (negedge Ain4) (3330:3330:3330)) + ) + ) + (CELL + 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(INSTANCE nC07X_I) + (DELAY + (ABSOLUTE + (IOPATH nC07X PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nC07X) (3330:3330:3330)) + (WIDTH (negedge nC07X) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nEN80") + (INSTANCE nEN80_I) + (DELAY + (ABSOLUTE + (IOPATH nEN80 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nEN80) (3330:3330:3330)) + (WIDTH (negedge nEN80) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nWE80") + (INSTANCE nWE80_I) + (DELAY + (ABSOLUTE + (IOPATH nWE80 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nWE80) (3330:3330:3330)) + (WIDTH (negedge nWE80) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nWE") + (INSTANCE nWE_I) + (DELAY + (ABSOLUTE + (IOPATH nWE PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nWE) (3330:3330:3330)) + (WIDTH (negedge nWE) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "PHI1") + (INSTANCE PHI1_I) + (DELAY + (ABSOLUTE + (IOPATH PHI1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI1) (3330:3330:3330)) + (WIDTH (negedge PHI1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "PHI1_MGIOL") + (INSTANCE PHI1_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "EFB_Buffer_Block") + (INSTANCE ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20) + (DELAY + (ABSOLUTE + (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278)) + (IOPATH WBCLKIin WBDATO1out (947:3204:5461)(947:3204:5461)) + (IOPATH WBCLKIin WBDATO2out (955:3211:5468)(955:3211:5468)) + (IOPATH WBCLKIin WBDATO3out (910:3173:5436)(910:3173:5436)) + (IOPATH WBCLKIin WBDATO4out (944:3217:5491)(944:3217:5491)) + (IOPATH WBCLKIin WBDATO5out (917:3672:6428)(917:3672:6428)) + (IOPATH WBCLKIin WBDATO6out (926:3191:5457)(926:3191:5457)) + (IOPATH WBCLKIin WBDATO7out (939:3201:5464)(939:3201:5464)) + (IOPATH WBCLKIin WBACKOout (903:1623:2343)(903:1623:2343)) + ) + ) + (TIMINGCHECK + (SETUPHOLD WBRSTIin (posedge WBCLKIin) (3138:3170:3203)(-3138:-1966:-794)) + (SETUPHOLD WBCYCIin (posedge WBCLKIin) (2616:2649:2682)(-2616:-1558:-501)) + (SETUPHOLD WBSTBIin (posedge WBCLKIin) (2605:2637:2670)(-2605:-1494:-384)) + (SETUPHOLD WBWEIin (posedge WBCLKIin) (1409:1442:1475)(-1409:-837:-266)) + (SETUPHOLD WBADRI0in (posedge WBCLKIin) (2058:2123:2188)(-2058:-1191:-324)) + (SETUPHOLD WBADRI1in (posedge WBCLKIin) (2068:2104:2140)(-2068:-1234:-401)) + (SETUPHOLD WBADRI2in (posedge WBCLKIin) (1928:1993:2058)(-1928:-1110:-292)) + (SETUPHOLD WBADRI3in (posedge WBCLKIin) (2167:2196:2226)(-2167:-1264:-361)) + (SETUPHOLD WBADRI4in (posedge WBCLKIin) (2072:2101:2130)(-2072:-1198:-324)) + (SETUPHOLD WBADRI5in (posedge WBCLKIin) (1611:1640:1670)(-1611:-950:-289)) + (SETUPHOLD WBADRI6in (posedge WBCLKIin) (2532:2564:2597)(-2532:-1380:-229)) + (SETUPHOLD WBADRI7in (posedge WBCLKIin) (2519:2551:2584)(-2519:-1377:-235)) + (SETUPHOLD WBDATI0in (posedge WBCLKIin) (1057:1262:1467)(-1037:-712:-388)) + (SETUPHOLD WBDATI1in (posedge WBCLKIin) (1114:1338:1563)(-1108:-785:-462)) + (SETUPHOLD WBDATI2in (posedge WBCLKIin) (916:1076:1237)(-912:-636:-360)) + (SETUPHOLD WBDATI3in (posedge WBCLKIin) (1145:1359:1573)(-1115:-782:-449)) + (SETUPHOLD WBDATI4in (posedge WBCLKIin) (1192:1400:1609)(-1176:-820:-464)) + (SETUPHOLD WBDATI5in (posedge WBCLKIin) (1027:1222:1418)(-1000:-706:-413)) + (SETUPHOLD WBDATI6in (posedge WBCLKIin) (1034:1248:1463)(-1034:-756:-479)) + (SETUPHOLD WBDATI7in (posedge WBCLKIin) (528:614:701)(-528:-398:-268)) + ) + (TIMINGCHECK + (WIDTH (posedge WBCLKIin) (4887:4887:4887)) + (WIDTH (negedge WBCLKIin) (4887:4887:4887)) + ) + ) + (CELL + (CELLTYPE "RAM2E") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_0/Q1 SLICE_39/A1 (1010:1164:1319)(1010:1164:1319)) + (INTERCONNECT SLICE_0/Q1 SLICE_52/A1 (1010:1164:1319)(1010:1164:1319)) + (INTERCONNECT SLICE_0/Q1 SLICE_75/A1 (1479:1669:1860)(1479:1669:1860)) + (INTERCONNECT SLICE_0/Q1 SLICE_119/D0 (868:965:1062)(868:965:1062)) + (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_0/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_1/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_2/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_2/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_3/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_3/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_4/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_4/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_5/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_5/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_6/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_6/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_7/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_7/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_9/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_11/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_13/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_14/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_15/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_16/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_17/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_23/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_23/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_24/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_24/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_25/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_25/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_26/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_26/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_27/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_27/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_28/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_28/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_29/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_29/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_30/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_30/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_31/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_32/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_33/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_33/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_39/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_44/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_45/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI SLICE_46/CLK (4198:4531:4865)(4198:4531:4865)) + (INTERCONNECT C14M_I/PADDI DQMH_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI DQML_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI RA\[11\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI RA\[10\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI RA\[9\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI RA\[8\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI RA\[7\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI RA\[6\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI RA\[5\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI RA\[4\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI RA\[2\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI RA\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI BA\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI BA\[0\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI nRWE_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI nCAS_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI nRAS_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI nCS_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI CKE_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Vout\[7\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Vout\[6\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Vout\[5\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Vout\[4\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Vout\[3\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Vout\[2\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Vout\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Vout\[0\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Dout\[7\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Dout\[6\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Dout\[5\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Dout\[4\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Dout\[3\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Dout\[2\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Dout\[1\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI Dout\[0\]_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI PHI1_MGIOL/CLK (4345:4691:5038)(4345:4691:5038)) + (INTERCONNECT C14M_I/PADDI + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (4345:4691:5038) + (4345:4691:5038)) + (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_1/Q0 SLICE_45/D0 (807:902:998)(807:902:998)) + (INTERCONNECT SLICE_1/Q0 SLICE_51/A0 (1017:1178:1339)(1017:1178:1339)) + (INTERCONNECT SLICE_1/Q0 SLICE_53/A1 (1344:1540:1736)(1344:1540:1736)) + (INTERCONNECT SLICE_1/Q0 SLICE_56/D1 (1182:1310:1438)(1182:1310:1438)) + (INTERCONNECT SLICE_1/Q0 SLICE_72/D0 (541:603:665)(541:603:665)) + (INTERCONNECT SLICE_1/Q0 SLICE_73/D0 (1546:1705:1865)(1546:1705:1865)) + (INTERCONNECT SLICE_1/Q0 SLICE_75/D0 (1134:1264:1395)(1134:1264:1395)) + (INTERCONNECT SLICE_1/Q0 SLICE_83/B1 (1376:1574:1773)(1376:1574:1773)) + (INTERCONNECT SLICE_1/Q0 SLICE_86/D1 (1546:1705:1865)(1546:1705:1865)) + (INTERCONNECT SLICE_1/Q0 SLICE_103/C0 (552:669:786)(552:669:786)) + (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_2/Q1 SLICE_37/B1 (1589:1789:1990)(1589:1789:1990)) + (INTERCONNECT SLICE_2/Q1 SLICE_37/B0 (1589:1789:1990)(1589:1789:1990)) + (INTERCONNECT SLICE_2/Q1 SLICE_38/C0 (1733:1953:2173)(1733:1953:2173)) + (INTERCONNECT SLICE_2/Q1 SLICE_39/B1 (1230:1399:1569)(1230:1399:1569)) + (INTERCONNECT SLICE_2/Q1 SLICE_44/C0 (999:1155:1312)(999:1155:1312)) + (INTERCONNECT SLICE_2/Q1 SLICE_45/A1 (1578:1778:1978)(1578:1778:1978)) + (INTERCONNECT SLICE_2/Q1 SLICE_45/A0 (1578:1778:1978)(1578:1778:1978)) + (INTERCONNECT SLICE_2/Q1 SLICE_56/A1 (1578:1778:1978)(1578:1778:1978)) + (INTERCONNECT SLICE_2/Q1 SLICE_66/A1 (2296:2558:2820)(2296:2558:2820)) + (INTERCONNECT SLICE_2/Q1 SLICE_73/C0 (1743:1964:2185)(1743:1964:2185)) + (INTERCONNECT SLICE_2/Q1 SLICE_86/A1 (1562:1760:1959)(1562:1760:1959)) + (INTERCONNECT SLICE_2/Q1 SLICE_97/A0 (1932:2162:2393)(1932:2162:2393)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_2/Q0 SLICE_35/D0 (1350:1483:1617)(1350:1483:1617)) + (INTERCONNECT SLICE_2/Q0 SLICE_44/B1 (1110:1275:1440)(1110:1275:1440)) + (INTERCONNECT SLICE_2/Q0 SLICE_46/A0 (1580:1781:1982)(1580:1781:1982)) + (INTERCONNECT SLICE_2/Q0 SLICE_56/C0 (1751:1973:2196)(1751:1973:2196)) + (INTERCONNECT SLICE_2/Q0 SLICE_60/A0 (2325:2590:2856)(2325:2590:2856)) + (INTERCONNECT SLICE_2/Q0 SLICE_61/B1 (2727:3027:3327)(2727:3027:3327)) + (INTERCONNECT SLICE_2/Q0 SLICE_65/A0 (1190:1357:1524)(1190:1357:1524)) + (INTERCONNECT SLICE_2/Q0 SLICE_66/A0 (1580:1781:1982)(1580:1781:1982)) + (INTERCONNECT SLICE_2/Q0 SLICE_73/A0 (1580:1781:1982)(1580:1781:1982)) + (INTERCONNECT SLICE_2/Q0 SLICE_74/D0 (2442:2677:2912)(2442:2677:2912)) + (INTERCONNECT SLICE_2/Q0 SLICE_88/D1 (2485:2717:2949)(2485:2717:2949)) + (INTERCONNECT SLICE_2/Q0 SLICE_90/D1 (1275:1400:1526)(1275:1400:1526)) + (INTERCONNECT SLICE_2/Q0 SLICE_92/A1 (1580:1781:1982)(1580:1781:1982)) + (INTERCONNECT SLICE_2/Q0 SLICE_97/B0 (2283:2551:2819)(2283:2551:2819)) + (INTERCONNECT SLICE_2/Q0 SLICE_108/B0 (2208:2468:2728)(2208:2468:2728)) + (INTERCONNECT SLICE_2/Q0 SLICE_116/C0 (1708:1933:2159)(1708:1933:2159)) + (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_3/Q1 SLICE_44/D1 (528:582:636)(528:582:636)) + (INTERCONNECT SLICE_3/Q1 SLICE_46/C1 (841:988:1135)(841:988:1135)) + (INTERCONNECT SLICE_3/Q1 SLICE_56/A0 (1410:1599:1789)(1410:1599:1789)) + (INTERCONNECT SLICE_3/Q1 SLICE_58/A1 (1810:2034:2259)(1810:2034:2259)) + (INTERCONNECT SLICE_3/Q1 SLICE_60/C0 (1241:1423:1605)(1241:1423:1605)) + (INTERCONNECT SLICE_3/Q1 SLICE_61/D1 (1230:1357:1484)(1230:1357:1484)) + (INTERCONNECT SLICE_3/Q1 SLICE_62/A1 (1440:1632:1825)(1440:1632:1825)) + (INTERCONNECT SLICE_3/Q1 SLICE_64/B0 (1442:1634:1826)(1442:1634:1826)) + (INTERCONNECT SLICE_3/Q1 SLICE_65/C0 (1216:1395:1575)(1216:1395:1575)) + (INTERCONNECT SLICE_3/Q1 SLICE_66/C0 (841:988:1135)(841:988:1135)) + (INTERCONNECT SLICE_3/Q1 SLICE_70/C1 (1611:1825:2039)(1611:1825:2039)) + (INTERCONNECT SLICE_3/Q1 SLICE_73/C1 (841:988:1135)(841:988:1135)) + (INTERCONNECT SLICE_3/Q1 SLICE_74/C0 (2026:2284:2542)(2026:2284:2542)) + (INTERCONNECT SLICE_3/Q1 SLICE_84/C1 (2026:2284:2542)(2026:2284:2542)) + (INTERCONNECT SLICE_3/Q1 SLICE_88/B1 (1472:1667:1862)(1472:1667:1862)) + (INTERCONNECT SLICE_3/Q1 SLICE_90/C0 (1241:1423:1605)(1241:1423:1605)) + (INTERCONNECT SLICE_3/Q1 SLICE_92/C1 (841:988:1135)(841:988:1135)) + (INTERCONNECT SLICE_3/Q1 SLICE_95/C1 (841:988:1135)(841:988:1135)) + (INTERCONNECT SLICE_3/Q1 SLICE_97/D1 (1230:1357:1484)(1230:1357:1484)) + (INTERCONNECT SLICE_3/Q1 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(INTERCONNECT SLICE_5/Q0 SLICE_32/A1 (1441:1635:1829)(1441:1635:1829)) + (INTERCONNECT SLICE_5/Q0 SLICE_63/D1 (528:586:644)(528:586:644)) + (INTERCONNECT SLICE_5/Q0 SLICE_75/B1 (2164:2427:2690)(2164:2427:2690)) + (INTERCONNECT SLICE_5/F1 SLICE_5/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/F0 SLICE_5/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/FCO SLICE_5/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_6/Q1 SLICE_6/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_6/Q1 SLICE_32/C1 (814:956:1099)(814:956:1099)) + (INTERCONNECT SLICE_6/Q1 SLICE_63/B1 (1409:1596:1783)(1409:1596:1783)) + (INTERCONNECT SLICE_6/Q1 SLICE_75/C1 (1178:1352:1526)(1178:1352:1526)) + (INTERCONNECT SLICE_6/Q0 SLICE_6/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_6/Q0 SLICE_55/D1 (549:610:671)(549:610:671)) + (INTERCONNECT SLICE_6/Q0 SLICE_55/D0 (549:610:671)(549:610:671)) + (INTERCONNECT SLICE_6/Q0 SLICE_72/C1 (924:1071:1219)(924:1071:1219)) + (INTERCONNECT SLICE_6/Q0 SLICE_76/B1 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(2075:2285:2495)(2075:2285:2495)) + (INTERCONNECT nWE80_I/PADDI SLICE_115/C0 (2075:2285:2495)(2075:2285:2495)) + (INTERCONNECT SLICE_115/F0 nRWE_MGIOL/OPOS (2313:2510:2707)(2313:2510:2707)) + (INTERCONNECT SLICE_115/F1 RD\[0\]_I/PADDT (1600:1744:1888)(1600:1744:1888)) + (INTERCONNECT SLICE_115/F1 RD\[7\]_I/PADDT (2390:2611:2833)(2390:2611:2833)) + (INTERCONNECT SLICE_115/F1 RD\[6\]_I/PADDT (2390:2611:2833)(2390:2611:2833)) + (INTERCONNECT SLICE_115/F1 RD\[5\]_I/PADDT (2390:2611:2833)(2390:2611:2833)) + (INTERCONNECT SLICE_115/F1 RD\[4\]_I/PADDT (2390:2611:2833)(2390:2611:2833)) + (INTERCONNECT SLICE_115/F1 RD\[3\]_I/PADDT (1600:1744:1888)(1600:1744:1888)) + (INTERCONNECT SLICE_115/F1 RD\[2\]_I/PADDT (1600:1744:1888)(1600:1744:1888)) + (INTERCONNECT SLICE_115/F1 RD\[1\]_I/PADDT (1600:1744:1888)(1600:1744:1888)) + (INTERCONNECT SLICE_117/F0 LED_I/PADDO (1124:1239:1355)(1124:1239:1355)) + (INTERCONNECT RD\[0\]_I/PADDI Vout\[0\]_MGIOL/OPOS (2735:2961:3187) + (2735:2961:3187)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_MGIOL/OPOS (1970:2136:2303) + (1970:2136:2303)) + (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (3308:3554:3800) + (3308:3554:3800)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_MGIOL/OPOS (2416:2609:2802) + (2416:2609:2802)) + (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (3321:3568:3816) + (3321:3568:3816)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_MGIOL/OPOS (3380:3625:3871) + (3380:3625:3871)) + (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (2885:3105:3325) + (2885:3105:3325)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_MGIOL/OPOS (3249:3500:3752) + (3249:3500:3752)) + (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (2876:3096:3316) + (2876:3096:3316)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_MGIOL/OPOS (3604:3887:4170) + (3604:3887:4170)) + (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (2884:3105:3326) + (2884:3105:3326)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_MGIOL/OPOS (1970:2136:2303) + (1970:2136:2303)) + (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (2467:2657:2847) + (2467:2657:2847)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_MGIOL/OPOS (3195:3448:3701) + (3195:3448:3701)) + (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (2794:3032:3271) + (2794:3032:3271)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_MGIOL/OPOS (1894:2047:2201) + (1894:2047:2201)) + (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[9\]_MGIOL/IOLDO RA\[9\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[8\]_MGIOL/IOLDO RA\[8\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[7\]_MGIOL/IOLDO RA\[7\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[6\]_MGIOL/IOLDO RA\[6\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[5\]_MGIOL/IOLDO RA\[5\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[4\]_MGIOL/IOLDO RA\[4\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[2\]_MGIOL/IOLDO RA\[2\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[1\]_MGIOL/IOLDO RA\[1\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nCAS_MGIOL/IOLDO nCAS_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nRAS_MGIOL/IOLDO nRAS_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nCS_MGIOL/IOLDO nCS_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT CKE_MGIOL/IOLDO CKE_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (7:62:118)(7:62:118)) + (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (7:62:118)(7:62:118)) + (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Vout\[4\]_MGIOL/IOLDO Vout\[4\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Vout\[3\]_MGIOL/IOLDO Vout\[3\]_I/IOLDO (7:62:118)(7:62:118)) + (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (7:62:118)(7:62:118)) + (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Dout\[7\]_MGIOL/IOLDO Dout\[7\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT Dout\[6\]_MGIOL/IOLDO Dout\[6\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT Dout\[5\]_MGIOL/IOLDO Dout\[5\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Dout\[4\]_MGIOL/IOLDO Dout\[4\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Dout\[3\]_MGIOL/IOLDO Dout\[3\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT Dout\[2\]_MGIOL/IOLDO Dout\[2\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Dout\[1\]_MGIOL/IOLDO Dout\[1\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT Dout\[0\]_MGIOL/IOLDO Dout\[0\]_I/IOLDO (30:36:43)(30:36:43)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo new file mode 100644 index 0000000..f5ba39f --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/RAM2E_LCMXO2_1200HC_impl1_vo.vo @@ -0,0 +1,6375 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2E_LCMXO2_1200HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml RAM2E_LCMXO2_1200HC_impl1.ncd +// Netlist created on Thu Sep 21 05:34:46 2023 +// Netlist written on Thu Sep 21 05:35:16 2023 +// Design is for device LCMXO2-1200HC +// Design is for package TQFP100 +// Design is for performance grade 4 + +`timescale 1 ns / 1 ps + +module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, + Vout, nVOE, CKE, nCS, nRAS, nCAS, nRWE, BA, RA, RD, DQML, DQMH ); + input C14M, PHI1, nWE, nWE80, nEN80, nC07X; + input [7:0] Ain; + input [7:0] Din; + output LED; + output [7:0] Dout; + output nDOE; + output [7:0] Vout; + output nVOE, CKE, nCS, nRAS, nCAS, nRWE; + output [1:0] BA; + output [11:0] RA; + output DQML, DQMH; + inout [7:0] RD; + wire \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , + \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , + \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , + \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , + \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , + \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , + \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , Ready, + PHI1reg, PHI1_c, RWSel, CO0_1, \CmdTout_3[0] , N_576_i, S_1, + \S_RNII9DO1_0[1] , \CS[0] , N_461, \CS[1] , N_511_i, N_504_i, + un1_CS_0_sqmuxa_i, N_637, \CS[2] , N_510_i, \Din_c[0] , \Din_c[2] , + \Din_c[3] , CmdBitbangMXO2_4_u_0_0_a2_0_1, N_643, CmdBitbangMXO2, + CmdBitbangMXO2_4, \Din_c[5] , \Din_c[7] , N_629, CmdExecMXO2, + CmdExecMXO2_4, N_466, \Din_c[4] , \Din_c[1] , N_478, + CmdLEDGet_4_u_0_0_a2_0_2, N_476, CmdLEDGet, CmdLEDGet_4, N_626, N_605, + CmdLEDSet, CmdLEDSet_4, CmdRWMaskSet, CmdRWMaskSet_4, N_401, + CmdSetRWBankFFLED, CmdSetRWBankFFLED_4, N_474, + CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0, CmdSetRWBankFFMXO2, + CmdSetRWBankFFMXO2_4, \CmdTout[1] , \CmdTout[2] , N_556_i, N_555_i, + \S[2] , \S[1] , \S[0] , \S[3] , N_6_i, DOEEN, \Ain_c[1] , + \wb_dato[0] , LEDEN_RNO, \un1_LEDEN_0_sqmuxa_1_i_0[0] , LEDEN, + N_558_i, \Ain_c[3] , \Ain_c[0] , N_552_i, N_127_i, \S_RNII9DO1_1[1] , + \RA_c[0] , \RA_c[3] , \RWMask[1] , N_591, \RWMask[0] , \RWBank_5[1] , + \RWBank_5[0] , LEDEN13, \RWBank[0] , \RWBank[1] , \RWMask[3] , + \RWMask[2] , \RWBank_5[3] , \RWBank_5[2] , \RWBank[2] , \RWBank[3] , + \RWMask[5] , \RWMask[4] , \RWBank_5[5] , \RWBank_5[4] , \RWBank[4] , + \RWBank[5] , \RWMask[7] , \Din_c[6] , \RWMask[6] , \RWBank_5[7] , + \RWBank_5[6] , \RWBank[6] , \RWBank[7] , \wb_dato[1] , N_291_i, + N_292_i, N_88, \wb_dato[3] , \wb_dato[2] , N_289_i, N_290_i, + \wb_dato[5] , \wb_dato[4] , N_287_i, N_288_i, \wb_dato[7] , + \wb_dato[6] , N_285, N_286_i, nEN80_c, nWE_c, nC07X_c, RWSel_2, nCS61, + nDOE_c, N_489, Ready_0_sqmuxa_0_a2_6_a2_4, Ready_0_sqmuxa, N_876_0, + N_572, wb_reqc_1, N_575, \S_s_0_1[0] , N_133_i, \S_s_0[0] , N_129_i, + N_131_i, N_388, wb_adr_7_5_214_0_1, N_642, \wb_adr_7_0_4[0] , N_376, + \wb_adr_RNO[1] , \wb_adr_7[0] , \un1_wb_adr_0_sqmuxa_2_i[0] , + \wb_adr[0] , \wb_adr[1] , N_41_i, N_43_i, \wb_adr[2] , \wb_adr[3] , + N_295, N_294, \wb_adr[4] , \wb_adr[5] , N_39_i, N_296, \wb_adr[6] , + \wb_adr[7] , N_300, wb_ack, N_395, wb_cyc_stb_RNO, N_104, wb_cyc_stb, + \wb_dati_7_0_0[1] , N_627, N_336, N_621, \wb_dati_7_0_a2_1[0] , N_484, + \wb_dati_7[1] , \wb_dati_7[0] , \wb_dati[0] , \wb_dati[1] , + \wb_dati_7_0_2[3] , \wb_dati_7_0_0[3] , \wb_dati_7_0_o2_0[2] , N_345, + \wb_dati_7[3] , \wb_dati_7[2] , \wb_dati[2] , \wb_dati[3] , N_346, + N_349, \wb_dati_7_0_0[4] , \wb_dati_7[5] , \wb_dati_7[4] , + \wb_dati[4] , \wb_dati[5] , \wb_dati_7_0_RNO[7] , \wb_dati_7_0_0[7] , + N_422, N_424, \wb_dati_7_0_1[6] , \wb_dati_7[7] , \wb_dati_7[6] , + \wb_dati[6] , \wb_dati[7] , N_397, wb_reqc_i, wb_adr_0_sqmuxa_i, + wb_req, wb_rst8, \S_RNII9DO1[1] , wb_rst, N_586, wb_we_7_iv_0_0_0_1, + N_584, N_475, wb_we_RNO, \un1_wb_cyc_stb_0_sqmuxa_1_i[0] , wb_we, + N_255, N_358_i, N_635, N_254, Vout3, nCAS_s_i_tz_0, + un1_CS_0_sqmuxa_0_0_a2_1_4, N_327, un1_CS_0_sqmuxa_0_0_0, + \wb_dati_7_0_a2_0_1[7] , N_579, CKE_6_iv_i_a2_0, CKE_6_iv_i_0_1, + CKE_6_iv_i_0, N_449, N_364, N_365, \un1_wb_adr_0_sqmuxa_2_1[0] , + N_616, N_623, N_279, N_264, N_633, N_570, N_452, N_455, N_644, + \wb_dati_7_0_a2_2_1[3] , DQML_s_i_a2_0, N_28_i, N_569, + wb_adr_7_5_214_a2_2_0, N_577, N_634, \wb_dati_7_0_a2_2_0[1] , N_265_i, + \un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] , \wb_dati_7_0_a2_0[6] , + \wb_dati_7_0_a2_4_0[7] , N_393, nCAS_0_sqmuxa, N_639, \RA_42[10] , + N_640, un1_nCS61_1_i, Ready_0_sqmuxa_0_a2_6_a2_2, N_562, N_377, N_628, + un1_CS_0_sqmuxa_0_0_2, un1_CS_0_sqmuxa_0_0_a2_3_2, + un1_CS_0_sqmuxa_0_0_3, N_567, N_561_i, nCS_6_u_i_0, N_559_1, N_559_i, + nRAS_2_iv_i, un1_CS_0_sqmuxa_0_0_a2_1, N_328, N_330, N_429, + nCS_6_u_i_a2_1, N_351, \wb_adr_7_0_a2_5_0[0] , \wb_adr_7_0_0[0] , + N_378, \wb_adr_7_0_1[0] , \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] , + un1_CS_0_sqmuxa_0_0_a2_4_2, un1_CS_0_sqmuxa_0_0_a2_4_4, N_565, + un1_CS_0_sqmuxa_0_0_a2_2_2, un1_CS_0_sqmuxa_0_0_a2_2_4, + \wb_adr_7_0_a2_0[0] , un1_CS_0_sqmuxa_0_0_a2_1_2, + un1_CS_0_sqmuxa_0_0_a2_3_0, N_394, N_49_i, N_456, N_477, N_566_i, + \BA_4[0] , \RA_42[11] , \BA_4[1] , N_59_i, \Ain_c[5] , \Ain_c[4] , + N_551_i, \RA_42_3_0[5] , \Ain_c[6] , N_550_i, \Ain_c[2] , \Ain_c[7] , + N_549_i, N_553_i, nWE80_c, nRWE_r_0, RDOE_i, LED_c, \RD_in[0] , + DQMH_c, DQML_c, \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , + \RD_in[3] , \RD_in[2] , \RD_in[1] , \RA_c[11] , \RA_c[10] , \RA_c[9] , + \RA_c[8] , \RA_c[7] , \RA_c[6] , \RA_c[5] , \RA_c[4] , \RA_c[2] , + \RA_c[1] , \BA_c[1] , \BA_c[0] , nRWE_c, nCAS_c, nRAS_c, nCS_c, CKE_c, + \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] , + \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , \Dout_c[7] , \Dout_c[6] , + \Dout_c[5] , \Dout_c[4] , \Dout_c[3] , \Dout_c[2] , \Dout_c[1] , + \Dout_c[0] , VCCI; + + SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), + .Q1(\FS[0] ), .FCO(\FS_cry[0] )); + SLICE_1 SLICE_1( .A0(\FS[15] ), .DI0(\FS_s[15] ), .CLK(C14M_c), + .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), .Q0(\FS[15] )); + SLICE_2 SLICE_2( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), + .DI0(\FS_s[13] ), .CLK(C14M_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), + .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] )); + SLICE_3 SLICE_3( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), + .DI0(\FS_s[11] ), .CLK(C14M_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), + .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] )); + SLICE_4 SLICE_4( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), + .DI0(\FS_s[9] ), .CLK(C14M_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), + .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] )); + SLICE_5 SLICE_5( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), + .DI0(\FS_s[7] ), .CLK(C14M_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), + .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] )); + SLICE_6 SLICE_6( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), + .DI0(\FS_s[5] ), .CLK(C14M_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), + .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] )); + SLICE_7 SLICE_7( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), + .DI0(\FS_s[3] ), .CLK(C14M_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), + .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] )); + SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), + .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), + .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); + SLICE_9 SLICE_9( .D1(Ready), .C1(PHI1reg), .B1(PHI1_c), .C0(RWSel), + .A0(CO0_1), .DI0(\CmdTout_3[0] ), .CE(N_576_i), .CLK(C14M_c), + .F0(\CmdTout_3[0] ), .Q0(CO0_1), .F1(S_1)); + SLICE_10 SLICE_10( .D1(\S_RNII9DO1_0[1] ), .C1(\CS[0] ), .B1(N_461), + .A1(\CS[1] ), .C0(\S_RNII9DO1_0[1] ), .B0(N_461), .A0(\CS[0] ), + .DI1(N_511_i), .DI0(N_504_i), .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), + .F0(N_504_i), .Q0(\CS[0] ), .F1(N_511_i), .Q1(\CS[1] )); + SLICE_11 SLICE_11( .D1(N_461), .C1(\CS[0] ), .B1(\S_RNII9DO1_0[1] ), + .D0(\CS[1] ), .C0(N_637), .A0(\CS[2] ), .DI0(N_510_i), + .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_510_i), .Q0(\CS[2] ), + .F1(N_637)); + SLICE_12 SLICE_12( .D1(\Din_c[0] ), .C1(\Din_c[2] ), .B1(\Din_c[3] ), + .D0(CmdBitbangMXO2_4_u_0_0_a2_0_1), .C0(N_643), .B0(RWSel), + .A0(CmdBitbangMXO2), .DI0(CmdBitbangMXO2_4), .CE(N_576_i), .CLK(C14M_c), + .F0(CmdBitbangMXO2_4), .Q0(CmdBitbangMXO2), + .F1(CmdBitbangMXO2_4_u_0_0_a2_0_1)); + SLICE_13 SLICE_13( .D1(RWSel), .C1(\Din_c[5] ), .B1(\Din_c[7] ), .D0(RWSel), + .C0(N_643), .B0(N_629), .A0(CmdExecMXO2), .DI0(CmdExecMXO2_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdExecMXO2_4), .Q0(CmdExecMXO2), + .F1(N_466)); + SLICE_14 SLICE_14( .D1(\Din_c[4] ), .C1(\Din_c[0] ), .B1(\Din_c[1] ), + .A1(N_478), .D0(CmdLEDGet_4_u_0_0_a2_0_2), .C0(RWSel), .B0(N_476), + .A0(CmdLEDGet), .DI0(CmdLEDGet_4), .CE(N_576_i), .CLK(C14M_c), + .F0(CmdLEDGet_4), .Q0(CmdLEDGet), .F1(CmdLEDGet_4_u_0_0_a2_0_2)); + SLICE_15 SLICE_15( .D1(N_476), .C1(\Din_c[1] ), .B1(\Din_c[4] ), .A1(N_626), + .D0(RWSel), .B0(N_605), .A0(CmdLEDSet), .DI0(CmdLEDSet_4), .CE(N_576_i), + .CLK(C14M_c), .F0(CmdLEDSet_4), .Q0(CmdLEDSet), .F1(N_605)); + SLICE_16 SLICE_16( .D1(N_476), .B1(\Din_c[4] ), .A1(\Din_c[1] ), .D0(N_643), + .C0(N_626), .B0(RWSel), .A0(CmdRWMaskSet), .DI0(CmdRWMaskSet_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdRWMaskSet_4), .Q0(CmdRWMaskSet), + .F1(N_643)); + SLICE_17 SLICE_17( .D1(N_626), .C1(\Din_c[1] ), .B1(N_476), .A1(\Din_c[4] ), + .C0(N_401), .B0(RWSel), .A0(CmdSetRWBankFFLED), .DI0(CmdSetRWBankFFLED_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdSetRWBankFFLED_4), + .Q0(CmdSetRWBankFFLED), .F1(N_401)); + SLICE_18 SLICE_18( .D1(\CS[2] ), .C1(N_474), .B1(\CS[1] ), + .D0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), .C0(RWSel), .B0(N_476), + .A0(CmdSetRWBankFFMXO2), .DI0(CmdSetRWBankFFMXO2_4), .CE(N_576_i), + .CLK(C14M_c), .F0(CmdSetRWBankFFMXO2_4), .Q0(CmdSetRWBankFFMXO2), + .F1(N_476)); + SLICE_19 SLICE_19( .D1(\CmdTout[1] ), .C1(RWSel), .B1(\CmdTout[2] ), + .A1(CO0_1), .D0(\CmdTout[1] ), .C0(RWSel), .A0(CO0_1), .DI1(N_556_i), + .DI0(N_555_i), .CE(N_576_i), .CLK(C14M_c), .F0(N_555_i), .Q0(\CmdTout[1] ), + .F1(N_556_i), .Q1(\CmdTout[2] )); + SLICE_20 SLICE_20( .D1(\S[2] ), .C1(\S[1] ), .B1(\S[0] ), .A1(\S[3] ), + .D0(\S[2] ), .C0(\S[1] ), .B0(\S[0] ), .A0(\S[3] ), .DI0(N_6_i), + .CLK(C14M_c), .F0(N_6_i), .Q0(DOEEN), .F1(N_576_i)); + SLICE_21 SLICE_21( .D1(\S[3] ), .C1(\Ain_c[1] ), .A1(\S[0] ), .D0(\S[3] ), + .C0(\wb_dato[0] ), .A0(\Din_c[0] ), .DI0(LEDEN_RNO), + .CE(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .CLK(C14M_c), .F0(LEDEN_RNO), + .Q0(LEDEN), .F1(N_558_i)); + SLICE_22 SLICE_22( .C1(\S[0] ), .B1(\Ain_c[3] ), .A1(\S[3] ), .C0(\S[0] ), + .B0(\Ain_c[0] ), .A0(\S[3] ), .DI1(N_552_i), .DI0(N_127_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c), .F0(N_127_i), .Q0(\RA_c[0] ), + .F1(N_552_i), .Q1(\RA_c[3] )); + SLICE_23 SLICE_23( .C1(\Din_c[1] ), .B1(\RWMask[1] ), .A1(N_591), + .D0(\RWMask[0] ), .B0(\Din_c[0] ), .A0(N_591), .DI1(\RWBank_5[1] ), + .DI0(\RWBank_5[0] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[0] ), + .Q0(\RWBank[0] ), .F1(\RWBank_5[1] ), .Q1(\RWBank[1] )); + SLICE_24 SLICE_24( .D1(\RWMask[3] ), .C1(\Din_c[3] ), .A1(N_591), + .C0(\Din_c[2] ), .B0(N_591), .A0(\RWMask[2] ), .DI1(\RWBank_5[3] ), + .DI0(\RWBank_5[2] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[2] ), + .Q0(\RWBank[2] ), .F1(\RWBank_5[3] ), .Q1(\RWBank[3] )); + SLICE_25 SLICE_25( .C1(\Din_c[5] ), .B1(N_591), .A1(\RWMask[5] ), + .D0(\Din_c[4] ), .B0(N_591), .A0(\RWMask[4] ), .DI1(\RWBank_5[5] ), + .DI0(\RWBank_5[4] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[4] ), + .Q0(\RWBank[4] ), .F1(\RWBank_5[5] ), .Q1(\RWBank[5] )); + SLICE_26 SLICE_26( .D1(N_591), .C1(\Din_c[7] ), .A1(\RWMask[7] ), .D0(N_591), + .C0(\Din_c[6] ), .B0(\RWMask[6] ), .DI1(\RWBank_5[7] ), + .DI0(\RWBank_5[6] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[6] ), + .Q0(\RWBank[6] ), .F1(\RWBank_5[7] ), .Q1(\RWBank[7] )); + SLICE_27 SLICE_27( .D1(\Din_c[1] ), .C1(\wb_dato[1] ), .B1(\S[3] ), + .C0(\wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), .DI1(N_291_i), + .DI0(N_292_i), .CE(N_88), .CLK(C14M_c), .F0(N_292_i), .Q0(\RWMask[0] ), + .F1(N_291_i), .Q1(\RWMask[1] )); + SLICE_28 SLICE_28( .D1(\S[3] ), .B1(\wb_dato[3] ), .A1(\Din_c[3] ), + .D0(\S[3] ), .C0(\Din_c[2] ), .B0(\wb_dato[2] ), .DI1(N_289_i), + .DI0(N_290_i), .CE(N_88), .CLK(C14M_c), .F0(N_290_i), .Q0(\RWMask[2] ), + .F1(N_289_i), .Q1(\RWMask[3] )); + SLICE_29 SLICE_29( .D1(\wb_dato[5] ), .C1(\Din_c[5] ), .B1(\S[3] ), + .C0(\Din_c[4] ), .B0(\S[3] ), .A0(\wb_dato[4] ), .DI1(N_287_i), + .DI0(N_288_i), .CE(N_88), .CLK(C14M_c), .F0(N_288_i), .Q0(\RWMask[4] ), + .F1(N_287_i), .Q1(\RWMask[5] )); + SLICE_30 SLICE_30( .D1(\S[3] ), .C1(\Din_c[7] ), .A1(\wb_dato[7] ), + .D0(\S[3] ), .C0(\Din_c[6] ), .B0(\wb_dato[6] ), .DI1(N_285), + .DI0(N_286_i), .CE(N_88), .CLK(C14M_c), .F0(N_286_i), .Q0(\RWMask[6] ), + .F1(N_285), .Q1(\RWMask[7] )); + SLICE_31 SLICE_31( .C1(nEN80_c), .B1(nWE_c), .A1(DOEEN), .D0(\RA_c[0] ), + .C0(\RA_c[3] ), .B0(nWE_c), .A0(nC07X_c), .DI0(RWSel_2), .CE(nCS61), + .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(nDOE_c)); + SLICE_32 SLICE_32( .D1(N_489), .C1(\FS[6] ), .B1(Ready_0_sqmuxa_0_a2_6_a2_4), + .A1(\FS[7] ), .C0(Ready_0_sqmuxa), .A0(Ready), .DI0(N_876_0), .CLK(C14M_c), + .F0(N_876_0), .Q0(Ready), .F1(Ready_0_sqmuxa)); + SLICE_33 SLICE_33( .D1(S_1), .C1(N_572), .B1(wb_reqc_1), .A1(N_575), + .D0(\S[1] ), .C0(\S_s_0_1[0] ), .B0(S_1), .A0(\S[0] ), .DI1(N_133_i), + .DI0(\S_s_0[0] ), .CLK(C14M_c), .F0(\S_s_0[0] ), .Q0(\S[0] ), .F1(N_133_i), + .Q1(\S[1] )); + SLICE_34 SLICE_34( .D1(N_575), .C1(S_1), .B1(\S[3] ), .A1(\S[2] ), + .D0(N_575), .C0(S_1), .B0(\S[3] ), .A0(\S[2] ), .DI1(N_129_i), + .DI0(N_131_i), .CLK(C14M_c), .F0(N_131_i), .Q0(\S[2] ), .F1(N_129_i), + .Q1(\S[3] )); + SLICE_35 SLICE_35( .D1(N_388), .C1(wb_adr_7_5_214_0_1), .B1(\Din_c[1] ), + .A1(\S[2] ), .D0(\FS[13] ), .C0(N_642), .B0(\wb_adr_7_0_4[0] ), .A0(N_376), + .DI1(\wb_adr_RNO[1] ), .DI0(\wb_adr_7[0] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_adr_7[0] ), + .Q0(\wb_adr[0] ), .F1(\wb_adr_RNO[1] ), .Q1(\wb_adr[1] )); + SLICE_36 SLICE_36( .D1(\S[2] ), .C1(\Din_c[3] ), .D0(\S[2] ), + .A0(\Din_c[2] ), .DI1(N_41_i), .DI0(N_43_i), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_43_i), + .Q0(\wb_adr[2] ), .F1(N_41_i), .Q1(\wb_adr[3] )); + SLICE_37 SLICE_37( .D1(\S[2] ), .B1(\FS[14] ), .A1(\Din_c[5] ), .D0(\S[2] ), + .C0(\Din_c[4] ), .B0(\FS[14] ), .DI1(N_295), .DI0(N_294), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_294), + .Q0(\wb_adr[4] ), .F1(N_295), .Q1(\wb_adr[5] )); + SLICE_38 SLICE_38( .D1(\S[2] ), .B1(\Din_c[7] ), .D0(\S[2] ), .C0(\FS[14] ), + .B0(\Din_c[6] ), .DI1(N_39_i), .DI0(N_296), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_296), + .Q0(\wb_adr[6] ), .F1(N_39_i), .Q1(\wb_adr[7] )); + SLICE_39 SLICE_39( .D1(N_300), .C1(wb_ack), .B1(\FS[14] ), .A1(\FS[0] ), + .C0(\S[3] ), .B0(N_395), .A0(CmdExecMXO2), .DI0(wb_cyc_stb_RNO), + .CE(N_104), .CLK(C14M_c), .F0(wb_cyc_stb_RNO), .Q0(wb_cyc_stb), .F1(N_395)); + SLICE_40 SLICE_40( .D1(\wb_dati_7_0_0[1] ), .C1(N_627), .B1(N_336), + .A1(N_621), .D0(\wb_adr[0] ), .C0(\wb_dati_7_0_a2_1[0] ), .B0(\S[2] ), + .A0(N_484), .DI1(\wb_dati_7[1] ), .DI0(\wb_dati_7[0] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[0] ), + .Q0(\wb_dati[0] ), .F1(\wb_dati_7[1] ), .Q1(\wb_dati[1] )); + SLICE_41 SLICE_41( .D1(\wb_dati_7_0_2[3] ), .C1(\wb_dati_7_0_0[3] ), + .B1(N_336), .D0(\wb_dati_7_0_o2_0[2] ), .C0(\S[2] ), .B0(\wb_adr[2] ), + .A0(N_345), .DI1(\wb_dati_7[3] ), .DI0(\wb_dati_7[2] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[2] ), + .Q0(\wb_dati[2] ), .F1(\wb_dati_7[3] ), .Q1(\wb_dati[3] )); + SLICE_42 SLICE_42( .D1(\wb_dati_7_0_o2_0[2] ), .C1(N_345), .B1(\S[2] ), + .A1(\wb_adr[5] ), .D0(N_345), .C0(N_346), .B0(N_349), + .A0(\wb_dati_7_0_0[4] ), .DI1(\wb_dati_7[5] ), .DI0(\wb_dati_7[4] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[4] ), + .Q0(\wb_dati[4] ), .F1(\wb_dati_7[5] ), .Q1(\wb_dati[5] )); + SLICE_43 SLICE_43( .D1(\wb_dati_7_0_RNO[7] ), .C1(\wb_dati_7_0_0[7] ), + .B1(N_422), .A1(N_424), .D0(N_627), .B0(\wb_dati_7_0_1[6] ), .A0(N_621), + .DI1(\wb_dati_7[7] ), .DI0(\wb_dati_7[6] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[6] ), + .Q0(\wb_dati[6] ), .F1(\wb_dati_7[7] ), .Q1(\wb_dati[7] )); + SLICE_44 SLICE_44( .D1(\FS[12] ), .B1(\FS[13] ), .A1(\FS[11] ), .D0(\S[3] ), + .C0(\FS[14] ), .B0(wb_reqc_1), .A0(N_397), .DI0(wb_reqc_i), + .CE(wb_adr_0_sqmuxa_i), .LSR(\S[2] ), .CLK(C14M_c), .F0(wb_reqc_i), + .Q0(wb_req), .F1(N_397)); + SLICE_45 SLICE_45( .B1(wb_ack), .A1(\FS[14] ), .D0(\FS[15] ), .A0(\FS[14] ), + .DI0(wb_rst8), .LSR(\S_RNII9DO1[1] ), .CLK(C14M_c), .F0(wb_rst8), + .Q0(wb_rst), .F1(N_586)); + SLICE_46 SLICE_46( .D1(\FS[10] ), .C1(\FS[12] ), .B1(\FS[8] ), .A1(\FS[9] ), + .D0(wb_we_7_iv_0_0_0_1), .C0(N_584), .B0(N_475), .A0(\FS[13] ), + .DI0(wb_we_RNO), .CE(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), .CLK(C14M_c), + .F0(wb_we_RNO), .Q0(wb_we), .F1(N_584)); + SLICE_47 SLICE_47( .D1(\RWBank[6] ), .C1(\S_RNII9DO1[1] ), .B1(\S[0] ), + .A1(N_255), .D0(\S[2] ), .C0(\S[3] ), .B0(\S[0] ), .A0(\S[1] ), + .F0(\S_RNII9DO1[1] ), .F1(N_358_i)); + SLICE_48 SLICE_48( .D1(\S[2] ), .C1(\S[0] ), .B1(\S[3] ), .A1(\S[1] ), + .D0(N_635), .C0(N_254), .B0(\S[0] ), .A0(Vout3), .F0(nCAS_s_i_tz_0), + .F1(Vout3)); + SLICE_49 SLICE_49( .D1(un1_CS_0_sqmuxa_0_0_a2_1_4), .C1(\Din_c[6] ), + .B1(RWSel), .A1(\CS[0] ), .D0(\CS[2] ), .C0(N_327), .B0(RWSel), + .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_0), .F1(N_327)); + SLICE_50 SLICE_50( .D1(\FS[10] ), .C1(\FS[11] ), .B1(\FS[8] ), .A1(\FS[9] ), + .D0(\wb_dati_7_0_a2_0_1[7] ), .C0(N_621), .B0(N_579), .A0(\FS[9] ), + .F0(\wb_dati_7_0_RNO[7] ), .F1(\wb_dati_7_0_a2_0_1[7] )); + SLICE_51 SLICE_51( .D1(\S[3] ), .C1(CKE_6_iv_i_a2_0), .B1(\S[2] ), + .A1(wb_reqc_1), .D0(N_489), .C0(CKE_6_iv_i_0_1), .B0(\S[3] ), + .A0(\FS[15] ), .F0(CKE_6_iv_i_0), .F1(CKE_6_iv_i_0_1)); + SLICE_52 SLICE_52( .D1(N_300), .C1(N_449), .B1(wb_req), .A1(\FS[0] ), + .D0(N_364), .C0(N_449), .B0(N_365), .A0(N_586), .F0(N_104), .F1(N_365)); + SLICE_53 SLICE_53( .D1(\S[2] ), .C1(RWSel), .B1(\S[3] ), .A1(\FS[15] ), + .D0(\S[2] ), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .B0(wb_reqc_1), + .A0(CmdExecMXO2), .F0(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), + .F1(\un1_wb_adr_0_sqmuxa_2_1[0] )); + SLICE_54 SLICE_54( .D1(\Din_c[0] ), .C1(\CS[1] ), .B1(\Din_c[2] ), + .A1(\Din_c[1] ), .D0(N_616), .C0(\CS[2] ), .B0(N_623), .A0(\Din_c[1] ), + .F0(N_279), .F1(N_623)); + SLICE_55 SLICE_55( .D1(\FS[5] ), .C1(N_264), .B1(N_633), .A1(\FS[4] ), + .D0(\FS[5] ), .C0(\FS[1] ), .B0(\FS[2] ), .A0(\FS[3] ), .F0(N_633), + .F1(N_570)); + SLICE_56 SLICE_56( .D1(\FS[15] ), .C1(\S_RNII9DO1[1] ), .A1(\FS[14] ), + .D0(N_452), .C0(\FS[13] ), .A0(\FS[12] ), .F0(N_621), .F1(N_452)); + SLICE_57 SLICE_57( .D1(RWSel), .C1(wb_ack), .B1(\S_RNII9DO1_0[1] ), + .A1(CmdExecMXO2), .D0(\S[2] ), .C0(\S[1] ), .B0(\S[0] ), .A0(\S[3] ), + .F0(\S_RNII9DO1_0[1] ), .F1(N_364)); + SLICE_58 SLICE_58( .D1(N_455), .C1(N_644), .B1(\wb_dati_7_0_a2_2_1[3] ), + .A1(\FS[12] ), .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), + .F0(\wb_dati_7_0_a2_2_1[3] ), .F1(\wb_dati_7_0_2[3] )); + SLICE_59 SLICE_59( .D1(DQML_s_i_a2_0), .C1(\S_RNII9DO1[1] ), .B1(nCS61), + .A1(\RWBank[6] ), .D0(\S[3] ), .C0(\S[0] ), .B0(\S[1] ), .A0(\S[2] ), + .F0(DQML_s_i_a2_0), .F1(N_28_i)); + SLICE_60 SLICE_60( .D1(N_569), .C1(wb_adr_7_5_214_a2_2_0), .B1(N_577), + .A1(N_475), .C0(\FS[12] ), .B0(\FS[10] ), .A0(\FS[13] ), + .F0(wb_adr_7_5_214_a2_2_0), .F1(wb_adr_7_5_214_0_1)); + SLICE_61 SLICE_61( .D1(\FS[12] ), .C1(N_634), .B1(\FS[13] ), .D0(\FS[8] ), + .C0(\FS[10] ), .B0(\FS[9] ), .A0(\FS[11] ), .F0(N_634), + .F1(\wb_dati_7_0_a2_2_0[1] )); + SLICE_62 SLICE_62( .D1(N_475), .C1(\FS[11] ), .B1(N_265_i), .A1(\FS[12] ), + .D0(\FS[10] ), .C0(\FS[9] ), .B0(\FS[8] ), .F0(N_265_i), .F1(N_388)); + SLICE_63 SLICE_63( .D1(\FS[7] ), .C1(N_264), .B1(\FS[6] ), .A1(N_254), + .C0(\FS[1] ), .B0(\FS[2] ), .A0(\FS[3] ), .F0(N_264), .F1(N_300)); + SLICE_64 SLICE_64( .C1(\FS[11] ), .B1(\FS[8] ), .A1(\FS[9] ), .D0(\FS[10] ), + .C0(N_577), .B0(\FS[12] ), .A0(wb_ack), + .F0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .F1(N_577)); + SLICE_65 SLICE_65( .D1(\FS[8] ), .B1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[10] ), + .C0(\FS[12] ), .B0(\wb_dati_7_0_a2_0[6] ), .A0(\FS[13] ), + .F0(\wb_dati_7_0_a2_4_0[7] ), .F1(\wb_dati_7_0_a2_0[6] )); + SLICE_66 SLICE_66( .C1(\S[2] ), .A1(\FS[14] ), .D0(N_475), .C0(\FS[12] ), + .B0(\FS[11] ), .A0(\FS[13] ), .F0(N_393), .F1(N_475)); + SLICE_67 SLICE_67( .C1(\S[1] ), .A1(\S[0] ), .D0(\S[3] ), .C0(wb_reqc_1), + .B0(\S[2] ), .A0(RWSel), .F0(LEDEN13), .F1(wb_reqc_1)); + SLICE_68 SLICE_68( .D1(N_455), .C1(N_627), .B1(\wb_adr[3] ), .A1(\S[2] ), + .D0(\FS[11] ), .C0(\FS[8] ), .B0(\FS[10] ), .A0(\FS[9] ), .F0(N_627), + .F1(\wb_dati_7_0_0[3] )); + SLICE_69 SLICE_69( .D1(nCAS_0_sqmuxa), .C1(N_639), .B1(N_255), + .A1(\RWBank[2] ), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), + .F0(N_639), .F1(\RA_42[10] )); + SLICE_70 SLICE_70( .D1(N_455), .C1(\FS[12] ), .B1(N_627), .A1(N_644), + .D0(\FS[10] ), .C0(\FS[11] ), .B0(\FS[8] ), .A0(\FS[9] ), .F0(N_644), + .F1(N_345)); + SLICE_71 SLICE_71( .D1(N_640), .C1(N_633), .B1(nCS61), .A1(\FS[4] ), + .D0(\S[1] ), .C0(\S[3] ), .B0(\S[0] ), .A0(\S[2] ), .F0(nCS61), + .F1(un1_nCS61_1_i)); + SLICE_72 SLICE_72( .D1(Ready_0_sqmuxa_0_a2_6_a2_2), .C1(\FS[5] ), + .B1(\FS[3] ), .A1(N_449), .D0(\FS[15] ), .C0(\S[2] ), .B0(wb_reqc_1), + .A0(\S[3] ), .F0(N_449), .F1(Ready_0_sqmuxa_0_a2_6_a2_4)); + SLICE_73 SLICE_73( .D1(N_562), .C1(\FS[12] ), .B1(N_455), .A1(\FS[11] ), + .D0(\FS[15] ), .C0(\FS[14] ), .B0(\S_RNII9DO1[1] ), .A0(\FS[13] ), + .F0(N_455), .F1(N_377)); + SLICE_74 SLICE_74( .D1(N_484), .B1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[13] ), + .C0(\FS[12] ), .B0(\FS[10] ), .A0(N_642), .F0(N_346), .F1(N_642)); + SLICE_75 SLICE_75( .D1(N_489), .C1(\FS[6] ), .B1(\FS[7] ), .A1(\FS[0] ), + .D0(\FS[15] ), .C0(N_628), .A0(\S_RNII9DO1[1] ), .F0(N_640), .F1(N_628)); + SLICE_76 SLICE_76( .B1(\FS[5] ), .A1(\FS[4] ), .D0(N_264), .C0(N_254), + .B0(N_628), .A0(N_449), .F0(nCAS_0_sqmuxa), .F1(N_254)); + SLICE_77 SLICE_77( .D1(\Din_c[6] ), .C1(\CS[0] ), .A1(N_466), + .D0(un1_CS_0_sqmuxa_0_0_2), .C0(N_474), .B0(un1_CS_0_sqmuxa_0_0_a2_3_2), + .A0(un1_CS_0_sqmuxa_0_0_3), .F0(un1_CS_0_sqmuxa_i), .F1(N_474)); + SLICE_78 SLICE_78( .C1(N_633), .A1(\FS[4] ), .D0(nCAS_0_sqmuxa), .C0(N_640), + .B0(nCAS_s_i_tz_0), .A0(N_567), .F0(N_561_i), .F1(N_567)); + SLICE_79 SLICE_79( .D1(\S[2] ), .C1(\S[3] ), .B1(nEN80_c), .A1(\S[1] ), + .C0(nCS_6_u_i_0), .A0(N_559_1), .F0(N_559_i), .F1(nCS_6_u_i_0)); + SLICE_80 SLICE_80( .D1(\S[1] ), .C1(\S[2] ), .B1(\S[3] ), .D0(N_559_1), + .C0(N_635), .B0(\S[0] ), .F0(nRAS_2_iv_i), .F1(N_635)); + SLICE_81 SLICE_81( .D1(\Din_c[4] ), .C1(\Din_c[3] ), .B1(\Din_c[6] ), + .A1(\CS[0] ), .D0(N_466), .C0(un1_CS_0_sqmuxa_0_0_0), + .B0(un1_CS_0_sqmuxa_0_0_a2_1), .A0(N_279), .F0(un1_CS_0_sqmuxa_0_0_2), + .F1(un1_CS_0_sqmuxa_0_0_a2_1)); + SLICE_82 SLICE_82( .D1(\CmdTout[1] ), .C1(RWSel), .B1(CO0_1), + .A1(\CmdTout[2] ), .D0(N_328), .C0(N_330), .B0(N_461), + .A0(\S_RNII9DO1_0[1] ), .F0(un1_CS_0_sqmuxa_0_0_3), .F1(N_461)); + SLICE_83 SLICE_83( .D1(\S[0] ), .C1(\S[3] ), .B1(\FS[15] ), .A1(\S[2] ), + .D0(N_429), .C0(N_570), .B0(N_628), .A0(nCS_6_u_i_a2_1), .F0(N_559_1), + .F1(nCS_6_u_i_a2_1)); + SLICE_84 SLICE_84( .D1(\FS[10] ), .C1(\FS[12] ), .B1(N_455), + .A1(\wb_dati_7_0_a2_0[6] ), .D0(\S[2] ), .C0(N_351), .B0(\wb_adr[6] ), + .A0(N_346), .F0(\wb_dati_7_0_1[6] ), .F1(N_351)); + SLICE_85 SLICE_85( .D1(\FS[8] ), .C1(N_579), .B1(\wb_adr_7_0_a2_5_0[0] ), + .A1(N_452), .D0(\wb_adr_7_0_0[0] ), .C0(N_378), .B0(\wb_adr_7_0_1[0] ), + .A0(N_377), .F0(\wb_adr_7_0_4[0] ), .F1(\wb_adr_7_0_1[0] )); + SLICE_86 SLICE_86( .D1(\FS[15] ), .C1(\S_RNII9DO1[1] ), .B1(\FS[8] ), + .A1(\FS[14] ), .D0(CmdLEDSet), .C0(N_484), + .B0(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ), .A0(LEDEN13), + .F0(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .F1(N_484)); + SLICE_87 SLICE_87( .D1(un1_CS_0_sqmuxa_0_0_a2_4_2), .C1(\Din_c[6] ), + .B1(\CS[0] ), .A1(RWSel), .D0(\CS[1] ), .C0(un1_CS_0_sqmuxa_0_0_a2_4_4), + .A0(\CS[2] ), .F0(N_330), .F1(un1_CS_0_sqmuxa_0_0_a2_4_4)); + SLICE_88 SLICE_88( .D1(\FS[13] ), .B1(\FS[12] ), .D0(N_452), .C0(N_569), + .B0(N_634), .A0(N_336), .F0(\wb_dati_7_0_o2_0[2] ), .F1(N_569)); + SLICE_89 SLICE_89( .D1(\FS[10] ), .B1(\FS[11] ), .D0(\FS[9] ), .C0(N_455), + .B0(\FS[8] ), .A0(N_579), .F0(N_378), .F1(N_579)); + SLICE_90 SLICE_90( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), + .C0(\FS[12] ), .B0(N_565), .A0(N_484), .F0(N_336), .F1(N_565)); + SLICE_91 SLICE_91( .D1(\Din_c[6] ), .C1(un1_CS_0_sqmuxa_0_0_a2_2_2), + .B1(\CS[0] ), .A1(\CS[2] ), .D0(\Din_c[7] ), + .C0(un1_CS_0_sqmuxa_0_0_a2_2_4), .B0(RWSel), .F0(N_328), + .F1(un1_CS_0_sqmuxa_0_0_a2_2_4)); + SLICE_92 SLICE_92( .D1(\FS[11] ), .C1(\FS[12] ), .B1(N_562), .A1(\FS[13] ), + .D0(\Din_c[0] ), .C0(\S[2] ), .B0(\wb_adr_7_0_a2_0[0] ), .A0(N_452), + .F0(\wb_adr_7_0_0[0] ), .F1(\wb_adr_7_0_a2_0[0] )); + SLICE_93 SLICE_93( .D1(N_616), .C1(\Din_c[5] ), .B1(\Din_c[1] ), + .A1(\Din_c[4] ), .D0(\CS[1] ), .C0(\Din_c[3] ), + .B0(un1_CS_0_sqmuxa_0_0_a2_1_2), .A0(\Din_c[7] ), + .F0(un1_CS_0_sqmuxa_0_0_a2_1_4), .F1(un1_CS_0_sqmuxa_0_0_a2_1_2)); + SLICE_94 SLICE_94( .D1(\Din_c[0] ), .C1(\Din_c[3] ), .B1(\Din_c[2] ), + .A1(\Din_c[1] ), .D0(\CS[2] ), .C0(un1_CS_0_sqmuxa_0_0_a2_3_0), + .B0(\Din_c[4] ), .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_a2_3_2), + .F1(un1_CS_0_sqmuxa_0_0_a2_3_0)); + SLICE_95 SLICE_95( .D1(\FS[10] ), .C1(\FS[12] ), .B1(N_577), .A1(N_475), + .D0(N_394), .C0(\Din_c[0] ), .B0(\S[2] ), .A0(N_393), + .F0(wb_we_7_iv_0_0_0_1), .F1(N_394)); + SLICE_96 SLICE_96( .C1(\S[1] ), .B1(\S[2] ), .A1(\S[3] ), .D0(\S[0] ), + .C0(\RWBank[7] ), .B0(N_255), .A0(\RWBank[0] ), .F0(N_49_i), .F1(N_255)); + SLICE_97 SLICE_97( .D1(\FS[12] ), .C1(\FS[10] ), .D0(N_577), .C0(N_456), + .B0(\FS[13] ), .A0(\FS[14] ), .F0(N_489), .F1(N_456)); + SLICE_98 SLICE_98( .D1(\Din_c[0] ), .C1(\Din_c[2] ), .B1(\Din_c[3] ), + .D0(N_477), .C0(N_626), .B0(\Din_c[5] ), .A0(\Din_c[7] ), + .F0(un1_CS_0_sqmuxa_0_0_a2_4_2), .F1(N_626)); + SLICE_99 SLICE_99( .C1(\Din_c[2] ), .B1(\Din_c[3] ), .D0(\Din_c[0] ), + .C0(N_478), .B0(\Din_c[5] ), .A0(N_477), .F0(un1_CS_0_sqmuxa_0_0_a2_2_2), + .F1(N_478)); + SLICE_100 SLICE_100( .D1(\Din_c[0] ), .C1(\Din_c[3] ), .B1(\Din_c[2] ), + .D0(\Din_c[1] ), .C0(N_629), .A0(\Din_c[4] ), + .F0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), .F1(N_629)); + SLICE_101 SLICE_101( .D1(\S[1] ), .C1(\S[2] ), .B1(\S[3] ), .A1(\S[0] ), + .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), .F0(\S_RNII9DO1_1[1] ), + .F1(N_566_i)); + SLICE_102 SLICE_102( .D1(\S[1] ), .C1(\S[0] ), .B1(\S[3] ), .A1(\S[2] ), + .D0(\S[1] ), .C0(\RWBank[4] ), .B0(\S[3] ), .A0(\S[2] ), .F0(\BA_4[0] ), + .F1(\S_s_0_1[0] )); + SLICE_103 SLICE_103( .D1(\RWBank[3] ), .C1(wb_reqc_1), .B1(\S[2] ), + .A1(\S[3] ), .D0(wb_reqc_1), .C0(\FS[15] ), .B0(\S[2] ), .A0(\S[3] ), + .F0(wb_adr_0_sqmuxa_i), .F1(\RA_42[11] )); + SLICE_104 SLICE_104( .D1(N_621), .C1(\FS[8] ), .B1(\FS[9] ), .A1(\FS[11] ), + .D0(N_621), .C0(\FS[10] ), .B0(\FS[9] ), .A0(\FS[11] ), .F0(N_376), + .F1(N_349)); + SLICE_105 SLICE_105( .D1(wb_ack), .C1(\FS[9] ), .B1(N_579), .A1(N_569), + .D0(N_569), .C0(\FS[9] ), .B0(N_579), .A0(N_484), .F0(N_424), + .F1(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] )); + SLICE_106 SLICE_106( .D1(\S[1] ), .C1(\S[0] ), .D0(\S[1] ), .C0(\S[0] ), + .B0(nEN80_c), .F0(CKE_6_iv_i_a2_0), .F1(N_575)); + SLICE_107 SLICE_107( .C1(\S[2] ), .B1(\S[3] ), .D0(\RWBank[5] ), .C0(\S[2] ), + .B0(\S[3] ), .A0(\S[1] ), .F0(\BA_4[1] ), .F1(N_572)); + SLICE_108 SLICE_108( .D1(\FS[10] ), .C1(\FS[12] ), .A1(\FS[9] ), + .D0(\FS[10] ), .C0(\FS[12] ), .B0(\FS[13] ), .A0(N_642), .F0(N_422), + .F1(\wb_adr_7_0_a2_5_0[0] )); + SLICE_109 SLICE_109( .D1(N_452), .C1(\wb_adr[7] ), + .B1(\wb_dati_7_0_a2_4_0[7] ), .A1(\S[2] ), .D0(N_452), + .C0(\wb_dati_7_0_a2_2_0[1] ), .B0(\wb_adr[1] ), .A0(\S[2] ), + .F0(\wb_dati_7_0_0[1] ), .F1(\wb_dati_7_0_0[7] )); + SLICE_110 SLICE_110( .D1(\S[2] ), .C1(\RWBank[1] ), .B1(wb_reqc_1), + .A1(\S[3] ), .D0(\S[2] ), .C0(CmdBitbangMXO2), .B0(wb_reqc_1), + .A0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .F0(\un1_wb_adr_0_sqmuxa_2_i[0] ), + .F1(N_59_i)); + SLICE_111 SLICE_111( .D1(\S[3] ), .B1(\Ain_c[5] ), .A1(\S[0] ), .D0(\S[3] ), + .C0(\Ain_c[4] ), .A0(\S[0] ), .F0(N_551_i), .F1(\RA_42_3_0[5] )); + SLICE_112 SLICE_112( .D1(\S[3] ), .C1(N_254), .B1(\S[1] ), .A1(\S[0] ), + .D0(\S[3] ), .B0(\Ain_c[6] ), .A0(\S[0] ), .F0(N_550_i), .F1(N_429)); + SLICE_113 SLICE_113( .D1(\S[3] ), .C1(\Ain_c[2] ), .A1(\S[0] ), .D0(\S[3] ), + .C0(\Ain_c[7] ), .A0(\S[0] ), .F0(N_549_i), .F1(N_553_i)); + SLICE_114 SLICE_114( .D1(\wb_adr[4] ), .C1(\S[2] ), .B1(N_455), .A1(N_634), + .D0(CmdRWMaskSet), .C0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .B0(N_455), + .A0(LEDEN13), .F0(N_88), .F1(\wb_dati_7_0_0[4] )); + SLICE_115 SLICE_115( .D1(nEN80_c), .C1(nWE80_c), .D0(\S[0] ), .C0(nWE80_c), + .B0(un1_nCS61_1_i), .A0(nCAS_0_sqmuxa), .F0(nRWE_r_0), .F1(RDOE_i)); + SLICE_116 SLICE_116( .B1(\FS[8] ), .A1(\FS[9] ), .D0(N_456), .C0(\FS[13] ), + .B0(\FS[11] ), .A0(\FS[9] ), .F0(\wb_dati_7_0_a2_1[0] ), .F1(N_562)); + SLICE_117 SLICE_117( .D1(CmdSetRWBankFFLED), .C1(CmdLEDGet), + .B1(CmdSetRWBankFFMXO2), .A1(LEDEN), .D0(LEDEN), .B0(nEN80_c), .F0(LED_c), + .F1(N_591)); + SLICE_118 SLICE_118( .C1(\Din_c[4] ), .B1(\Din_c[1] ), .D0(\Din_c[0] ), + .C0(\Din_c[2] ), .F0(N_616), .F1(N_477)); + SLICE_119 SLICE_119( .D0(\FS[0] ), .C0(\FS[1] ), .B0(\FS[2] ), .A0(\FS[4] ), + .F0(Ready_0_sqmuxa_0_a2_6_a2_2)); + RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(\Din_c[0] ), + .RD0(RD[0])); + LED LED_I( .PADDO(LED_c), .LED(LED)); + C14M C14M_I( .PADDI(C14M_c), .C14M(C14M)); + DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH)); + DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_358_i), .CLK(C14M_c)); + DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML)); + DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_28_i), .CLK(C14M_c)); + RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(\Din_c[7] ), + .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(\Din_c[6] ), + .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(\Din_c[5] ), + .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(\Din_c[4] ), + .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(\Din_c[3] ), + .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(\Din_c[2] ), + .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(\Din_c[1] ), + .RD1(RD[1])); + RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11])); + RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(\RA_42[11] ), + .CLK(C14M_c)); + RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10])); + RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(\RA_42[10] ), + .CLK(C14M_c)); + RA_9_ \RA[9]_I ( .IOLDO(\RA_c[9] ), .RA9(RA[9])); + RA_9__MGIOL \RA[9]_MGIOL ( .IOLDO(\RA_c[9] ), .OPOS(N_59_i), .CLK(C14M_c)); + RA_8_ \RA[8]_I ( .IOLDO(\RA_c[8] ), .RA8(RA[8])); + RA_8__MGIOL \RA[8]_MGIOL ( .IOLDO(\RA_c[8] ), .OPOS(N_49_i), .CLK(C14M_c)); + RA_7_ \RA[7]_I ( .IOLDO(\RA_c[7] ), .RA7(RA[7])); + RA_7__MGIOL \RA[7]_MGIOL ( .IOLDO(\RA_c[7] ), .OPOS(N_549_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_6_ \RA[6]_I ( .IOLDO(\RA_c[6] ), .RA6(RA[6])); + RA_6__MGIOL \RA[6]_MGIOL ( .IOLDO(\RA_c[6] ), .OPOS(N_550_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_5_ \RA[5]_I ( .IOLDO(\RA_c[5] ), .RA5(RA[5])); + RA_5__MGIOL \RA[5]_MGIOL ( .IOLDO(\RA_c[5] ), .OPOS(\RA_42_3_0[5] ), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_4_ \RA[4]_I ( .IOLDO(\RA_c[4] ), .RA4(RA[4])); + RA_4__MGIOL \RA[4]_MGIOL ( .IOLDO(\RA_c[4] ), .OPOS(N_551_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .IOLDO(\RA_c[2] ), .RA2(RA[2])); + RA_2__MGIOL \RA[2]_MGIOL ( .IOLDO(\RA_c[2] ), .OPOS(N_553_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_1_ \RA[1]_I ( .IOLDO(\RA_c[1] ), .RA1(RA[1])); + RA_1__MGIOL \RA[1]_MGIOL ( .IOLDO(\RA_c[1] ), .OPOS(N_558_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0])); + BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1])); + BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), + .LSR(N_566_i), .CLK(C14M_c)); + BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0])); + BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), + .LSR(N_566_i), .CLK(C14M_c)); + nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE)); + nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(nRWE_r_0), .CLK(C14M_c)); + nCAS nCAS_I( .IOLDO(nCAS_c), .nCAS(nCAS)); + nCAS_MGIOL nCAS_MGIOL( .IOLDO(nCAS_c), .OPOS(N_561_i), .CLK(C14M_c)); + nRAS nRAS_I( .IOLDO(nRAS_c), .nRAS(nRAS)); + nRAS_MGIOL nRAS_MGIOL( .IOLDO(nRAS_c), .OPOS(nRAS_2_iv_i), .CLK(C14M_c)); + nCS nCS_I( .IOLDO(nCS_c), .nCS(nCS)); + nCS_MGIOL nCS_MGIOL( .IOLDO(nCS_c), .OPOS(N_559_i), .CLK(C14M_c)); + CKE CKE_I( .IOLDO(CKE_c), .CKE(CKE)); + CKE_MGIOL CKE_MGIOL( .IOLDO(CKE_c), .OPOS(CKE_6_iv_i_0), .CLK(C14M_c)); + nVOE nVOE_I( .PADDO(PHI1_c), .nVOE(nVOE)); + Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7])); + Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_6_ \Vout[6]_I ( .IOLDO(\Vout_c[6] ), .Vout6(Vout[6])); + Vout_6__MGIOL \Vout[6]_MGIOL ( .IOLDO(\Vout_c[6] ), .OPOS(\RD_in[6] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_5_ \Vout[5]_I ( .IOLDO(\Vout_c[5] ), .Vout5(Vout[5])); + Vout_5__MGIOL \Vout[5]_MGIOL ( .IOLDO(\Vout_c[5] ), .OPOS(\RD_in[5] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_4_ \Vout[4]_I ( .IOLDO(\Vout_c[4] ), .Vout4(Vout[4])); + Vout_4__MGIOL \Vout[4]_MGIOL ( .IOLDO(\Vout_c[4] ), .OPOS(\RD_in[4] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_3_ \Vout[3]_I ( .IOLDO(\Vout_c[3] ), .Vout3(Vout[3])); + Vout_3__MGIOL \Vout[3]_MGIOL ( .IOLDO(\Vout_c[3] ), .OPOS(\RD_in[3] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_2_ \Vout[2]_I ( .IOLDO(\Vout_c[2] ), .Vout2(Vout[2])); + Vout_2__MGIOL \Vout[2]_MGIOL ( .IOLDO(\Vout_c[2] ), .OPOS(\RD_in[2] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_1_ \Vout[1]_I ( .IOLDO(\Vout_c[1] ), .Vout1(Vout[1])); + Vout_1__MGIOL \Vout[1]_MGIOL ( .IOLDO(\Vout_c[1] ), .OPOS(\RD_in[1] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_0_ \Vout[0]_I ( .IOLDO(\Vout_c[0] ), .Vout0(Vout[0])); + Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), + .CE(Vout3), .CLK(C14M_c)); + nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE)); + Dout_7_ \Dout[7]_I ( .IOLDO(\Dout_c[7] ), .Dout7(Dout[7])); + Dout_7__MGIOL \Dout[7]_MGIOL ( .IOLDO(\Dout_c[7] ), .OPOS(\RD_in[7] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_6_ \Dout[6]_I ( .IOLDO(\Dout_c[6] ), .Dout6(Dout[6])); + Dout_6__MGIOL \Dout[6]_MGIOL ( .IOLDO(\Dout_c[6] ), .OPOS(\RD_in[6] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_5_ \Dout[5]_I ( .IOLDO(\Dout_c[5] ), .Dout5(Dout[5])); + Dout_5__MGIOL \Dout[5]_MGIOL ( .IOLDO(\Dout_c[5] ), .OPOS(\RD_in[5] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_4_ \Dout[4]_I ( .IOLDO(\Dout_c[4] ), .Dout4(Dout[4])); + Dout_4__MGIOL \Dout[4]_MGIOL ( .IOLDO(\Dout_c[4] ), .OPOS(\RD_in[4] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_3_ \Dout[3]_I ( .IOLDO(\Dout_c[3] ), .Dout3(Dout[3])); + Dout_3__MGIOL \Dout[3]_MGIOL ( .IOLDO(\Dout_c[3] ), .OPOS(\RD_in[3] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_2_ \Dout[2]_I ( .IOLDO(\Dout_c[2] ), .Dout2(Dout[2])); + Dout_2__MGIOL \Dout[2]_MGIOL ( .IOLDO(\Dout_c[2] ), .OPOS(\RD_in[2] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_1_ \Dout[1]_I ( .IOLDO(\Dout_c[1] ), .Dout1(Dout[1])); + Dout_1__MGIOL \Dout[1]_MGIOL ( .IOLDO(\Dout_c[1] ), .OPOS(\RD_in[1] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_0_ \Dout[0]_I ( .IOLDO(\Dout_c[0] ), .Dout0(Dout[0])); + Dout_0__MGIOL \Dout[0]_MGIOL ( .IOLDO(\Dout_c[0] ), .OPOS(\RD_in[0] ), + .CE(N_576_i), .CLK(C14M_c)); + Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0])); + Ain_7_ \Ain[7]_I ( .PADDI(\Ain_c[7] ), .Ain7(Ain[7])); + Ain_6_ \Ain[6]_I ( .PADDI(\Ain_c[6] ), .Ain6(Ain[6])); + Ain_5_ \Ain[5]_I ( .PADDI(\Ain_c[5] ), .Ain5(Ain[5])); + Ain_4_ \Ain[4]_I ( .PADDI(\Ain_c[4] ), .Ain4(Ain[4])); + Ain_3_ \Ain[3]_I ( .PADDI(\Ain_c[3] ), .Ain3(Ain[3])); + Ain_2_ \Ain[2]_I ( .PADDI(\Ain_c[2] ), .Ain2(Ain[2])); + Ain_1_ \Ain[1]_I ( .PADDI(\Ain_c[1] ), .Ain1(Ain[1])); + Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0])); + nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X)); + nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80)); + nWE80 nWE80_I( .PADDI(nWE80_c), .nWE80(nWE80)); + nWE nWE_I( .PADDI(nWE_c), .nWE(nWE)); + PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1)); + PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1reg)); + ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), .WBRSTI(wb_rst), + .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), + .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), + .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), + .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), + .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), + .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), + .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), + .WBDATO2(\wb_dato[2] ), .WBDATO3(\wb_dato[3] ), .WBDATO4(\wb_dato[4] ), + .WBDATO5(\wb_dato[5] ), .WBDATO6(\wb_dato[6] ), .WBDATO7(\wb_dato[7] ), + .WBACKO(wb_ack)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); +endmodule + +module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly; + + vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h000A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20001 \FS_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5002; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_9 ( input D1, C1, B1, C0, A0, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut4 S_1( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40003 \CmdTout_3_0_a2[0] ( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40003 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0505) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40004 \CS_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 \CS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0006 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40004 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA9A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_11 ( input D1, C1, B1, D0, C0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40007 \CS_RNO_0[2] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 \CS_RNO[2] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0030) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5AAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_12 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40009 CmdBitbangMXO2_4_u_0_0_a2_0_1( .A(GNDI), .B(B1), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 CmdBitbangMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdBitbangMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_13 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 un1_CS_0_sqmuxa_0_0_a2_7( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 CmdExecMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdExecMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40013 CmdLEDGet_4_u_0_0_a2_0_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40014 CmdLEDGet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_15 ( input D1, C1, B1, A1, D0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40015 CmdLEDSet_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40016 CmdLEDSet_4_u_0_0_0( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_16 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40017 CmdBitbangMXO2_4_u_0_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 CmdRWMaskSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_17 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40019 CmdSetRWBankFFLED_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40020 CmdSetRWBankFFLED_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF2F2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_18 ( input D1, C1, B1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40021 CmdSetRWBankFFLED_4_u_0_0_a2_1( .A(GNDI), .B(B1), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 CmdSetRWBankFFMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre CmdSetRWBankFFMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_19 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40022 \CmdTout_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40023 \CmdTout_RNO[1] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CmdTout[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h060C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h050A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40024 \S_RNII9DO1_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre DOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_21 ( input D1, C1, A1, D0, C0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40026 \RA_0io_RNO[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40027 LEDEN_RNO( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_22 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40028 \RA_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40028 \RA_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC8C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_23 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 \RWBank_5_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40030 \RWBank_5_0[0] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_24 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40031 \RWBank_5_0[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40032 \RWBank_5_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDCDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40032 \RWBank_5_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40033 \RWBank_5_0[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input D1, C1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40034 \RWBank_5_0_0[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 \RWBank_5_0[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF30) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_27 ( input D1, C1, B1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40036 \RWMask_RNO[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40037 \RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h30FC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7474) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_28 ( input D1, B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \RWMask_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 \RWMask_RNO[2] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h55CC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0FCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_29 ( input D1, C1, B1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40040 \RWMask_RNO[5] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 \RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3F0C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2E2E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_30 ( input D1, C1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40042 \RWMask_RNO[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40039 \RWMask_RNO[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40043 nDOE_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40044 RWSel_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40045 Ready_0_sqmuxa_0_a2_6_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 Ready_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output + F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40047 \S_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 \S_s_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h008C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output + F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40049 \S_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40050 \S_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \S[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0C0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0A0D) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40051 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40052 \wb_adr_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input D1, C1, D0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40053 \wb_adr_RNO[3] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40054 \wb_adr_RNO[2] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_37 ( input D1, B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40055 \wb_adr_RNO[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40056 \wb_adr_RNO[4] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA33) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_38 ( input D1, B1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40057 \wb_adr_RNO[7] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40058 \wb_adr_RNO[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC0F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_39 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40059 wb_cyc_stb_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40060 wb_cyc_stb_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40061 \wb_dati_7_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40062 \wb_dati_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_41 ( input D1, C1, B1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40063 \wb_dati_7_0[3] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40064 \wb_dati_7_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40065 \wb_dati_7_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40066 \wb_dati_7_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_43 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40067 \wb_dati_7_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40068 \wb_dati_7_0[6] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_44 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40069 wb_req_RNO_1( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40070 wb_req_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_45 ( input B1, A1, D0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40071 \un1_LEDEN13_2_i_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 wb_rst8_0_a2( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre0006 wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40073 wb_we_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40074 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h70F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40075 DQMH_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40076 \S_RNII9DO1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40076 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40077 Vout3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40078 nCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40078 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40079 un1_CS_0_sqmuxa_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40080 un1_CS_0_sqmuxa_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40079 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40080 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40081 \wb_dati_7_0_a2_0_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40082 \wb_dati_7_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00B0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40082 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40083 CKE_6_iv_i_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40084 CKE_6_iv_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40083 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h30EE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40084 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF2F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40085 \un1_LEDEN13_2_i_a2_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40086 \un1_LEDEN13_2_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40085 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40086 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40087 \un1_wb_adr_0_sqmuxa_2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40088 wb_we_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40087 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3FDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40088 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40089 un1_CS_0_sqmuxa_0_0_a2_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40090 un1_CS_0_sqmuxa_0_0_o2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40089 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40090 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDCCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40091 nCS_6_u_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40092 un1_nCS61_1_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40091 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40092 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_56 ( input D1, C1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40093 \wb_dati_7_0_a2_5[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40094 \wb_dati_7_0_a2_6[1] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40093 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0500) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40094 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40095 \un1_LEDEN13_2_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40096 \S_RNII9DO1_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40095 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40096 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40097 \wb_dati_7_0_2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40098 \wb_dati_7_0_2_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40097 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40098 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40099 DQML_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40100 DQML_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40099 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0FBF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40100 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_60 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40101 \wb_adr_RNO_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40102 \wb_adr_RNO_3[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40101 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h20A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_61 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40103 \wb_dati_7_0_a2_2_0[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 \FS_RNIOD6E_1[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40103 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40104 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40105 \wb_adr_RNO_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40106 \wb_adr_RNO_2[1] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40105 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40106 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC03F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40107 \un1_LEDEN13_2_i_o2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40108 \FS_RNI9FGA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40107 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40108 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40109 \FS_RNI6JJA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40110 \un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40109 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40110 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40111 \wb_dati_7_0_a2_0_0[6] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40112 \wb_dati_7_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40111 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40112 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40003 \FS_RNIJ9MH[14] ( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40113 wb_we_RNO_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40113 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40114 wb_reqc_1( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40115 wb_reqc_1_RNIRU4M1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40114 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40115 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40116 \wb_dati_7_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40117 \FS_RNIOD6E_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40116 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40117 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40118 \RA_42_0[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40119 \RA_42_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40118 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF2) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40119 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0208) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40120 \wb_dati_7_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40121 \FS_RNIOD6E[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40120 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0E00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40121 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40122 nRWE_r_0_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40123 \S_RNII9DO1_3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40122 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40123 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40124 Ready_0_sqmuxa_0_a2_6_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40125 \FS_RNI5OOF1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40124 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40125 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40126 \wb_adr_7_0_a2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40127 \FS_RNIK5632[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40126 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00C4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40127 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40128 \wb_dati_7_0_a2_5[4] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40129 \wb_dati_7_0_a2_5_RNIC22J[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40128 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40129 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40079 nCS_6_u_i_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40130 nCS_6_u_i_a2_4_RNI3A062( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40130 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40071 nCS_6_u_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40131 nCS_6_u_i_a2_4_RNICJKD2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40131 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_77 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40132 un1_CS_0_sqmuxa_0_0_a2_10( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40133 un1_CS_0_sqmuxa_0_0_2_RNIQS7F( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40132 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40133 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0015) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40114 nCAS_s_i_o2( .A(A1), .B(GNDI), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40134 nCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40134 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF13) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input D1, C1, B1, A1, C0, A0, output F0, F1 ); + wire GNDI; + + lut40135 nCS_6_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40003 nCS_0io_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40135 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h001A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input D1, C1, B1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40136 nRAS_2_iv_0_a2_0( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40137 nRAS_2_iv_i( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40136 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h030C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40137 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00CF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40138 un1_CS_0_sqmuxa_0_0_a2_1_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40080 un1_CS_0_sqmuxa_0_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40138 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40139 un1_CS_0_sqmuxa_0_0_a2_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40066 un1_CS_0_sqmuxa_0_0_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40139 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h070F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40140 nCS_6_u_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40141 nCS_6_u_i_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40140 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40141 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40142 \wb_dati_7_0_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40143 \wb_dati_7_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40142 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40143 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40144 \wb_adr_7_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40145 \wb_adr_7_0_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40144 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8A88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40145 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40146 \wb_dati_7_0_a2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40147 \un1_LEDEN_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40146 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40147 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_87 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40148 un1_CS_0_sqmuxa_0_0_a2_4_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40149 un1_CS_0_sqmuxa_0_0_a2_4( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40148 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40149 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0050) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_88 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40150 \FS_RNI9Q57[13] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40151 \wb_dati_7_0_o2_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40150 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40151 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40152 \wb_adr_7_0_o2[0] ( .A(GNDI), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40153 \wb_adr_7_0_a2_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40152 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40153 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40154 \wb_dati_7_0_o2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40155 \wb_dati_7_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40154 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40155 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_91 ( input D1, C1, B1, A1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40156 un1_CS_0_sqmuxa_0_0_a2_2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40103 un1_CS_0_sqmuxa_0_0_a2_2( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40156 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40157 \wb_adr_7_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40158 \wb_adr_7_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40157 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0C0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40158 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40159 un1_CS_0_sqmuxa_0_0_a2_1_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40160 un1_CS_0_sqmuxa_0_0_a2_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40159 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40160 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40161 un1_CS_0_sqmuxa_0_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40162 un1_CS_0_sqmuxa_0_0_a2_3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40161 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40162 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40163 wb_we_RNO_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40164 wb_we_RNO_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40163 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40164 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40165 \RA_42_i_o2[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40166 \RA_0io_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40165 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFDFD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40166 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_97 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40053 \wb_dati_7_0_a2_1[0] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40167 CKE_6_iv_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40167 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_98 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40168 un1_CS_0_sqmuxa_0_0_a2_16( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40169 un1_CS_0_sqmuxa_0_0_a2_4_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40168 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40169 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_99 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40170 un1_CS_0_sqmuxa_0_0_a2_12( .A(GNDI), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40171 un1_CS_0_sqmuxa_0_0_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40170 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40171 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_100 ( input D1, C1, B1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40011 un1_CS_0_sqmuxa_0_0_a2_17( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40172 CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0( .A(A0), .B(GNDI), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40172 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40173 wb_reqc_1_RNIEO5C1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40174 \S_RNII9DO1_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40173 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40174 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE209) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40175 \S_s_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40176 \BA_0io_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40175 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8E0E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40176 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40177 \RA_0io_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40076 wb_req_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40177 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40178 \wb_dati_7_0_a2_3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40179 \wb_adr_7_0_a2_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40178 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40179 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40180 \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40077 \wb_dati_7_0_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40180 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_106 ( input D1, C1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40181 \S_RNINI6S[1] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40182 CKE_6_iv_i_0_1_RNO( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40181 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40182 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0333) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_107 ( input C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40183 \S_r_i_o2[1] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40184 \BA_0io_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40183 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40184 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_108 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40185 \wb_adr_7_0_a2_5_0[0] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40186 \wb_dati_7_0_a2[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40185 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h000A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40186 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40187 \wb_dati_7_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40188 \wb_dati_7_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40187 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40188 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40189 \RA_0io_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40190 CmdBitbangMXO2_RNI8CSO1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40189 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0031) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40190 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1011) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_111 ( input D1, B1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40191 \RA_42_3_0[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 \RA_0io_RNO[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40191 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCCDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_112 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40192 nCS_6_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40193 \RA_0io_RNO[6] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40192 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40193 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_113 ( input D1, C1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40026 \RA_0io_RNO[2] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 \RA_0io_RNO[7] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40194 \wb_dati_7_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40195 \un1_RWMask_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40194 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40195 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_115 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40196 nWE80_pad_RNI3ICD( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40197 nRWE_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40196 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40197 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_116 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40198 \wb_adr_7_0_o2_2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40199 \wb_dati_7_0_a2_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40198 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40199 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_117 ( input D1, C1, B1, A1, D0, B0, output F0, F1 ); + wire GNDI; + + lut40200 \RWBank_5_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40150 LED_pad_RNO( .A(GNDI), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40200 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_118 ( input C1, B1, D0, C0, output F0, F1 ); + wire GNDI; + + lut40201 un1_CS_0_sqmuxa_0_0_a2_11( .A(GNDI), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40202 un1_CS_0_sqmuxa_0_0_a2_13( .A(GNDI), .B(GNDI), .C(C0), .D(D0), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40201 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40202 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_119 ( input D0, C0, B0, A0, output F0 ); + + lut40203 Ready_0_sqmuxa_0_a2_6_a2_2_0( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40203 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module xo2iobuf ( input I, T, output Z, PAD, input PADI ); + + IB INST1( .I(PADI), .O(Z)); + OBW INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module LED ( input PADDO, output LED ); + + xo2iobuf0204 LED_pad( .I(PADDO), .PAD(LED)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0204 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module C14M ( output PADDI, input C14M ); + + xo2iobuf0205 C14M_pad( .Z(PADDI), .PAD(C14M)); + + specify + (C14M => PADDI) = (0:0:0,0:0:0); + $width (posedge C14M, 0:0:0); + $width (negedge C14M, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0205 ( output Z, input PAD ); + + IB INST1( .I(PAD), .O(Z)); +endmodule + +module DQMH ( input IOLDO, output DQMH ); + + xo2iobuf0204 DQMH_pad( .I(IOLDO), .PAD(DQMH)); + + specify + (IOLDO => DQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module DQMH_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre DQMH_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre ( input D0, SP, CK, LSR, output Q ); + + FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module DQML ( input IOLDO, output DQML ); + + xo2iobuf0204 DQML_pad( .I(IOLDO), .PAD(DQML)); + + specify + (IOLDO => DQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module DQML_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre DQML_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + xo2iobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + xo2iobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + xo2iobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + xo2iobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + xo2iobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + xo2iobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RA_11_ ( input IOLDO, output RA11 ); + + xo2iobuf0204 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); + + specify + (IOLDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0206 \RA_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0206 ( input D0, SP, CK, LSR, output Q ); + + FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module RA_10_ ( input IOLDO, output RA10 ); + + xo2iobuf0204 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); + + specify + (IOLDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0206 \RA_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_9_ ( input IOLDO, output RA9 ); + + xo2iobuf0204 \RA_pad[9] ( .I(IOLDO), .PAD(RA9)); + + specify + (IOLDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0206 \RA_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_8_ ( input IOLDO, output RA8 ); + + xo2iobuf0204 \RA_pad[8] ( .I(IOLDO), .PAD(RA8)); + + specify + (IOLDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0206 \RA_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_7_ ( input IOLDO, output RA7 ); + + xo2iobuf0204 \RA_pad[7] ( .I(IOLDO), .PAD(RA7)); + + specify + (IOLDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \RA_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_6_ ( input IOLDO, output RA6 ); + + xo2iobuf0204 \RA_pad[6] ( .I(IOLDO), .PAD(RA6)); + + specify + (IOLDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \RA_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_5_ ( input IOLDO, output RA5 ); + + xo2iobuf0204 \RA_pad[5] ( .I(IOLDO), .PAD(RA5)); + + specify + (IOLDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \RA_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_4_ ( input IOLDO, output RA4 ); + + xo2iobuf0204 \RA_pad[4] ( .I(IOLDO), .PAD(RA4)); + + specify + (IOLDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \RA_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + + xo2iobuf0204 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input IOLDO, output RA2 ); + + xo2iobuf0204 \RA_pad[2] ( .I(IOLDO), .PAD(RA2)); + + specify + (IOLDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \RA_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_1_ ( input IOLDO, output RA1 ); + + xo2iobuf0204 \RA_pad[1] ( .I(IOLDO), .PAD(RA1)); + + specify + (IOLDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \RA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + + xo2iobuf0204 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_1_ ( input IOLDO, output BA1 ); + + xo2iobuf0204 \BA_pad[1] ( .I(IOLDO), .PAD(BA1)); + + specify + (IOLDO => BA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); + wire VCCI, OPOS_dly, CLK_dly, LSR_dly; + + mfflsre0207 \BA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_dly), .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0207 ( input D0, SP, CK, LSR, output Q ); + + FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module BA_0_ ( input IOLDO, output BA0 ); + + xo2iobuf0204 \BA_pad[0] ( .I(IOLDO), .PAD(BA0)); + + specify + (IOLDO => BA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); + wire VCCI, OPOS_dly, CLK_dly, LSR_dly; + + mfflsre0207 \BA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_dly), .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRWE ( input IOLDO, output nRWE ); + + xo2iobuf0204 nRWE_pad( .I(IOLDO), .PAD(nRWE)); + + specify + (IOLDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nCAS ( input IOLDO, output nCAS ); + + xo2iobuf0204 nCAS_pad( .I(IOLDO), .PAD(nCAS)); + + specify + (IOLDO => nCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nCAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRAS ( input IOLDO, output nRAS ); + + xo2iobuf0204 nRAS_pad( .I(IOLDO), .PAD(nRAS)); + + specify + (IOLDO => nRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nCS ( input IOLDO, output nCS ); + + xo2iobuf0204 nCS_pad( .I(IOLDO), .PAD(nCS)); + + specify + (IOLDO => nCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nCS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CKE ( input IOLDO, output CKE ); + + xo2iobuf0204 CKE_pad( .I(IOLDO), .PAD(CKE)); + + specify + (IOLDO => CKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CKE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0206 CKE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nVOE ( input PADDO, output nVOE ); + + xo2iobuf0204 nVOE_pad( .I(PADDO), .PAD(nVOE)); + + specify + (PADDO => nVOE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_7_ ( input IOLDO, output Vout7 ); + + xo2iobuf0204 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7)); + + specify + (IOLDO => Vout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module Vout_6_ ( input IOLDO, output Vout6 ); + + xo2iobuf0204 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6)); + + specify + (IOLDO => Vout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_5_ ( input IOLDO, output Vout5 ); + + xo2iobuf0204 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5)); + + specify + (IOLDO => Vout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_4_ ( input IOLDO, output Vout4 ); + + xo2iobuf0204 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4)); + + specify + (IOLDO => Vout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_3_ ( input IOLDO, output Vout3 ); + + xo2iobuf0204 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3)); + + specify + (IOLDO => Vout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_2_ ( input IOLDO, output Vout2 ); + + xo2iobuf0204 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2)); + + specify + (IOLDO => Vout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_1_ ( input IOLDO, output Vout1 ); + + xo2iobuf0204 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1)); + + specify + (IOLDO => Vout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_0_ ( input IOLDO, output Vout0 ); + + xo2iobuf0204 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0)); + + specify + (IOLDO => Vout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module nDOE ( input PADDO, output nDOE ); + + xo2iobuf0204 nDOE_pad( .I(PADDO), .PAD(nDOE)); + + specify + (PADDO => nDOE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input IOLDO, output Dout7 ); + + xo2iobuf0208 \Dout_pad[7] ( .I(IOLDO), .PAD(Dout7)); + + specify + (IOLDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0208 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module Dout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Dout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_6_ ( input IOLDO, output Dout6 ); + + xo2iobuf0208 \Dout_pad[6] ( .I(IOLDO), .PAD(Dout6)); + + specify + (IOLDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Dout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_5_ ( input IOLDO, output Dout5 ); + + xo2iobuf0208 \Dout_pad[5] ( .I(IOLDO), .PAD(Dout5)); + + specify + (IOLDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Dout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_4_ ( input IOLDO, output Dout4 ); + + xo2iobuf0208 \Dout_pad[4] ( .I(IOLDO), .PAD(Dout4)); + + specify + (IOLDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Dout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_3_ ( input IOLDO, output Dout3 ); + + xo2iobuf0208 \Dout_pad[3] ( .I(IOLDO), .PAD(Dout3)); + + specify + (IOLDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Dout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_2_ ( input IOLDO, output Dout2 ); + + xo2iobuf0208 \Dout_pad[2] ( .I(IOLDO), .PAD(Dout2)); + + specify + (IOLDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Dout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_1_ ( input IOLDO, output Dout1 ); + + xo2iobuf0208 \Dout_pad[1] ( .I(IOLDO), .PAD(Dout1)); + + specify + (IOLDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Dout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_0_ ( input IOLDO, output Dout0 ); + + xo2iobuf0208 \Dout_pad[0] ( .I(IOLDO), .PAD(Dout0)); + + specify + (IOLDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0206 \Dout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + xo2iobuf0205 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + xo2iobuf0205 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + xo2iobuf0205 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + xo2iobuf0205 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + xo2iobuf0205 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + xo2iobuf0205 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + xo2iobuf0205 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + xo2iobuf0205 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module Ain_7_ ( output PADDI, input Ain7 ); + + xo2iobuf0205 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7)); + + specify + (Ain7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain7, 0:0:0); + $width (negedge Ain7, 0:0:0); + endspecify + +endmodule + +module Ain_6_ ( output PADDI, input Ain6 ); + + xo2iobuf0205 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6)); + + specify + (Ain6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain6, 0:0:0); + $width (negedge Ain6, 0:0:0); + endspecify + +endmodule + +module Ain_5_ ( output PADDI, input Ain5 ); + + xo2iobuf0205 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5)); + + specify + (Ain5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain5, 0:0:0); + $width (negedge Ain5, 0:0:0); + endspecify + +endmodule + +module Ain_4_ ( output PADDI, input Ain4 ); + + xo2iobuf0205 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4)); + + specify + (Ain4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain4, 0:0:0); + $width (negedge Ain4, 0:0:0); + endspecify + +endmodule + +module Ain_3_ ( output PADDI, input Ain3 ); + + xo2iobuf0205 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3)); + + specify + (Ain3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain3, 0:0:0); + $width (negedge Ain3, 0:0:0); + endspecify + +endmodule + +module Ain_2_ ( output PADDI, input Ain2 ); + + xo2iobuf0205 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2)); + + specify + (Ain2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain2, 0:0:0); + $width (negedge Ain2, 0:0:0); + endspecify + +endmodule + +module Ain_1_ ( output PADDI, input Ain1 ); + + xo2iobuf0205 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1)); + + specify + (Ain1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain1, 0:0:0); + $width (negedge Ain1, 0:0:0); + endspecify + +endmodule + +module Ain_0_ ( output PADDI, input Ain0 ); + + xo2iobuf0205 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0)); + + specify + (Ain0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain0, 0:0:0); + $width (negedge Ain0, 0:0:0); + endspecify + +endmodule + +module nC07X ( output PADDI, input nC07X ); + + xo2iobuf0205 nC07X_pad( .Z(PADDI), .PAD(nC07X)); + + specify + (nC07X => PADDI) = (0:0:0,0:0:0); + $width (posedge nC07X, 0:0:0); + $width (negedge nC07X, 0:0:0); + endspecify + +endmodule + +module nEN80 ( output PADDI, input nEN80 ); + + xo2iobuf0205 nEN80_pad( .Z(PADDI), .PAD(nEN80)); + + specify + (nEN80 => PADDI) = (0:0:0,0:0:0); + $width (posedge nEN80, 0:0:0); + $width (negedge nEN80, 0:0:0); + endspecify + +endmodule + +module nWE80 ( output PADDI, input nWE80 ); + + xo2iobuf0205 nWE80_pad( .Z(PADDI), .PAD(nWE80)); + + specify + (nWE80 => PADDI) = (0:0:0,0:0:0); + $width (posedge nWE80, 0:0:0); + $width (negedge nWE80, 0:0:0); + endspecify + +endmodule + +module nWE ( output PADDI, input nWE ); + + xo2iobuf0205 nWE_pad( .Z(PADDI), .PAD(nWE)); + + specify + (nWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nWE, 0:0:0); + $width (negedge nWE, 0:0:0); + endspecify + +endmodule + +module PHI1 ( output PADDI, input PHI1 ); + + xo2iobuf0205 PHI1_pad( .Z(PADDI), .PAD(PHI1)); + + specify + (PHI1 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI1, 0:0:0); + $width (negedge PHI1, 0:0:0); + endspecify + +endmodule + +module PHI1_MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre PHI1reg_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module smuxlregsre ( input D0, SP, CK, LSR, output Q ); + + IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, + WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, + WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output + WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, + WBACKO ); + wire VCCI, GNDI; + + EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), + .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), + .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), + .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), + .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), + .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), + .WBDATO1(WBDATO1), .WBDATO2(WBDATO2), .WBDATO3(WBDATO3), .WBDATO4(WBDATO4), + .WBDATO5(WBDATO5), .WBDATO6(WBDATO6), .WBDATO7(WBDATO7), .WBACKO(WBACKO), + .WBCUFMIRQ(), .UFMSN(VCCI), .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), + .I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), + .I2C2SCLI(GNDI), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), + .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), + .SPISCKEN(), .SPIMISOI(GNDI), .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), + .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), + .SPIMCSN3(), .SPIMCSN4(), .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), + .SPICSNEN(), .SPISCSN(GNDI), .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), + .TCIC(GNDI), .TCINT(), .TCOC(), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), + .PLL1STBO(), .PLLWEO(), .PLLADRO0(), .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), + .PLLADRO4(), .PLLDATO0(), .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), + .PLLDATO4(), .PLLDATO5(), .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), + .PLL0DATI1(GNDI), .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), + .PLL0DATI5(GNDI), .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), + .PLL1DATI0(GNDI), .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), + .PLL1DATI4(GNDI), .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), + .PLL1ACKI(GNDI)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); +endmodule + +module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, + WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, + WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, + WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, + WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output + I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input + I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, + I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, + input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output + SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, + SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, + input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, + PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, + PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, + PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, + PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, + PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI ); + wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, + WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, + WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, + WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, + WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, + PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, + PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, + PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, + PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, + I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, + SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, + UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, + WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, + PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, + PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, + PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, + PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, + I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, + I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, + I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, + SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, + SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, + SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, + CFGWAKE_buf, CFGSTDBY_buf; + + EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), + .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), + .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), + .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), + .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), + .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), + .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), + .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), + .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), + .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), + .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), + .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), + .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), + .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), + .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), + .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), + .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), + .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), + .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), + .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), + .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), + .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), + .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), + .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), + .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), + .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), + .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), + .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), + .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), + .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), + .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), + .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), + .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), + .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), + .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), + .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), + .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), + .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), + .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), + .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), + .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), + .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf)); + defparam INST10.DEV_DENSITY = "1200L"; + defparam INST10.EFB_I2C1 = "DISABLED"; + defparam INST10.EFB_I2C2 = "DISABLED"; + defparam INST10.EFB_SPI = "DISABLED"; + defparam INST10.EFB_TC = "DISABLED"; + defparam INST10.EFB_TC_PORTMODE = "WB"; + defparam INST10.EFB_UFM = "ENABLED"; + defparam INST10.EFB_WB_CLK_FREQ = "14.4"; + defparam INST10.GSR = "ENABLED"; + defparam INST10.I2C1_ADDRESSING = "7BIT"; + defparam INST10.I2C1_BUS_PERF = "100kHz"; + defparam INST10.I2C1_CLK_DIVIDER = 1; + defparam INST10.I2C1_GEN_CALL = "DISABLED"; + defparam INST10.I2C1_SLAVE_ADDR = "0b1000001"; + defparam INST10.I2C1_WAKEUP = "DISABLED"; + defparam INST10.I2C2_ADDRESSING = "7BIT"; + defparam INST10.I2C2_BUS_PERF = "100kHz"; + defparam INST10.I2C2_CLK_DIVIDER = 1; + defparam INST10.I2C2_GEN_CALL = "DISABLED"; + defparam INST10.I2C2_SLAVE_ADDR = "0b1000010"; + defparam INST10.I2C2_WAKEUP = "DISABLED"; + defparam INST10.SPI_CLK_DIVIDER = 1; + defparam INST10.SPI_CLK_INV = "DISABLED"; + defparam INST10.SPI_INTR_RXOVR = "DISABLED"; + defparam INST10.SPI_INTR_RXRDY = "DISABLED"; + defparam INST10.SPI_INTR_TXOVR = "DISABLED"; + defparam INST10.SPI_INTR_TXRDY = "DISABLED"; + defparam INST10.SPI_LSB_FIRST = "DISABLED"; + defparam INST10.SPI_MODE = "MASTER"; + defparam INST10.SPI_PHASE_ADJ = "DISABLED"; + defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED"; + defparam INST10.SPI_WAKEUP = "DISABLED"; + defparam INST10.TC_CCLK_SEL = 1; + defparam INST10.TC_ICAPTURE = "DISABLED"; + defparam INST10.TC_ICR_INT = "OFF"; + defparam INST10.TC_MODE = "CTCM"; + defparam INST10.TC_OCR_INT = "OFF"; + defparam INST10.TC_OCR_SET = 32767; + defparam INST10.TC_OC_MODE = "TOGGLE"; + defparam INST10.TC_OVERFLOW = "DISABLED"; + defparam INST10.TC_OV_INT = "OFF"; + defparam INST10.TC_RESETN = "ENABLED"; + defparam INST10.TC_SCLK_SEL = "PCLOCK"; + defparam INST10.TC_TOP_SEL = "OFF"; + defparam INST10.TC_TOP_SET = 65535; + defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED"; + defparam INST10.UFM_INIT_FILE_FORMAT = "HEX"; + defparam INST10.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem"; + defparam INST10.UFM_INIT_PAGES = 321; + defparam INST10.UFM_INIT_START_PAGE = 190; + EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), + .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), + .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), + .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), + .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), + .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), + .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), + .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), + .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), + .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), + .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), + .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), + .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), + .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), + .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), + .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), + .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), + .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), + .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), + .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), + .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), + .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), + .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), + .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), + .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), + .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), + .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), + .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), + .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), + .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), + .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), + .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), + .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), + .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), + .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), + .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), + .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), + .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), + .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), + .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), + .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), + .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), + .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), + .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), + .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), + .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), + .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), + .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), + .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), + .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), + .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), + .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), + .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), + .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), + .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), + .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), + .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), + .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), + .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), + .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), + .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), + .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), + .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), + .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), + .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), + .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), + .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), + .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), + .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), + .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), + .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), + .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), + .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), + .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), + .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), + .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), + .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), + .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), + .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), + .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), + .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), + .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), + .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), + .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), + .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), + .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), + .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), + .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), + .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), + .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), + .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), + .CFGSTDBYin(CFGSTDBY_buf)); +endmodule + +module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, + output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, + output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output + WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output + WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output + WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output + WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output + WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output + WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output + WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output + WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output + PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, + output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input + PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, + input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output + PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, + output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input + PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, + input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output + PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, + output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input + I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, + input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, + input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, + input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, + input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input + TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input + WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input + WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input + WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input + WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input + WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input + PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, + input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, + input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, + input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, + input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, + input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, + input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, + input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, + input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output + I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, + output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input + I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, + input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output + I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, + output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, + output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input + SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, + input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output + SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, + output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, + output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, + output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, + output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, + output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, + output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin ); + wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, + WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, + WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, + WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, + WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly; + + BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout)); + BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout)); + BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout)); + BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout)); + BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout)); + BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out)); + BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out)); + BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out)); + BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out)); + BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out)); + BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out)); + BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out)); + BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out)); + BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out)); + BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out)); + BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out)); + BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out)); + BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out)); + BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out)); + BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out)); + BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out)); + BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out)); + BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out)); + BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out)); + BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out)); + BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out)); + BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out)); + BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out)); + BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out)); + BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout)); + BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out)); + BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out)); + BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out)); + BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out)); + BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out)); + BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out)); + BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out)); + BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out)); + BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout)); + BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout)); + BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout)); + BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout)); + BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout)); + BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout)); + BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout)); + BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout)); + BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout)); + BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout)); + BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout)); + BUFBA TCIC_buf( .A(TCICin), .Z(TCICout)); + BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout)); + BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out)); + BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out)); + BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out)); + BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out)); + BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out)); + BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out)); + BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out)); + BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out)); + BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout)); + BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout)); + BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout)); + BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout)); + BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout)); + BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout)); + BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out)); + BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out)); + BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out)); + BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out)); + BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out)); + BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out)); + BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out)); + BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out)); + BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out)); + BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out)); + BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out)); + BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out)); + BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out)); + BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout)); + BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout)); + BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout)); + BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout)); + BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout)); + BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout)); + BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout)); + BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout)); + BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout)); + BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout)); + BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout)); + BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout)); + BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout)); + BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout)); + BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout)); + BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout)); + BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out)); + BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out)); + BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out)); + BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out)); + BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out)); + BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out)); + BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out)); + BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out)); + BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout)); + BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout)); + BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout)); + BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout)); + BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout)); + BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout)); + BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout)); + + specify + (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO2out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO3out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO4out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO5out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO6out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO7out) = (0:0:0,0:0:0); + (WBCLKIin => WBACKOout) = (0:0:0,0:0:0); + $setuphold + (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly); + $setuphold + (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly); + $setuphold + (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly); + $setuphold + (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly); + $setuphold + (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly); + $setuphold + (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly); + $setuphold + (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly); + $setuphold + (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly); + $setuphold + (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly); + $setuphold + (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly); + $setuphold + (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly); + $setuphold + (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly); + $setuphold + (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly); + $setuphold + (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly); + $setuphold + (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly); + $setuphold + (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly); + $setuphold + (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly); + $setuphold + (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly); + $setuphold + (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly); + $setuphold + (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly); + $width (posedge WBCLKIin, 0:0:0); + $width (negedge WBCLKIin, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html new file mode 100644 index 0000000..63b2b29 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html @@ -0,0 +1,14 @@ + 
    Setting log file to '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
+(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v'
+(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v'
+INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E'
+INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v(1,1-831,10) (VERI-9000) elaborating module 'RAM2E'
+INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    \ No newline at end of file diff --git a/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior b/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior new file mode 100644 index 0000000..14f4acc --- /dev/null +++ b/CPLD/LCMXO2-1200HC/impl1/ram2e_lcmxo2_1200hc_impl1.ior @@ -0,0 +1,120 @@ +Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2E +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2E +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: 6 +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2e_lcmxo2_1200hc_impl1.ncd. +Design name: RAM2E +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-1200HC +Package: TQFP100 +Performance: M +Package Status: Final Version 1.44. +Performance Hardware Data Status: Final Version 34.4. +// Design: RAM2E +// Package: TQFP100 +// ncd File: ram2e_lcmxo2_1200hc_impl1.ncd +// Version: Diamond (64-bit) 3.12.1.454 +// Written on Thu Sep 21 05:35:11 2023 +// M: Minimum Performance Grade +// iotiming RAM2E_LCMXO2_1200HC_impl1.ncd RAM2E_LCMXO2_1200HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-1200HC/promote.xml + +I/O Timing Report (All units are in ns) + +Worst Case Results across Performance Grades (M, 6, 5, 4): + +// Input Setup and Hold Times + +Port Clock Edge Setup Performance_Grade Hold Performance_Grade +---------------------------------------------------------------------- +Ain[0] C14M R -0.231 M 2.350 4 +Ain[1] C14M R 1.429 4 0.543 4 +Ain[2] C14M R 1.518 4 0.412 4 +Ain[3] C14M R -0.231 M 2.350 4 +Ain[4] C14M R 0.212 4 1.560 4 +Ain[5] C14M R 0.742 4 1.110 4 +Ain[6] C14M R 0.469 4 1.329 4 +Ain[7] C14M R 1.416 4 0.531 4 +Din[0] C14M R 8.327 4 1.958 4 +Din[1] C14M R 5.826 4 2.521 4 +Din[2] C14M R 6.539 4 2.135 4 +Din[3] C14M R 5.849 4 2.648 4 +Din[4] C14M R 7.061 4 2.095 4 +Din[5] C14M R 6.295 4 2.894 4 +Din[6] C14M R 4.991 4 2.892 4 +Din[7] C14M R 6.416 4 2.971 4 +PHI1 C14M R 1.151 4 4.842 4 +RD[0] C14M F -0.266 M 3.107 4 +RD[1] C14M F -0.248 M 3.183 4 +RD[2] C14M F -0.105 M 2.610 4 +RD[3] C14M F -0.243 M 3.107 4 +RD[4] C14M F 0.103 4 2.201 4 +RD[5] C14M F -0.092 M 2.192 4 +RD[6] C14M F -0.084 M 1.756 4 +RD[7] C14M F -0.092 M 2.661 4 +nC07X C14M R -0.316 M 2.625 4 +nEN80 C14M R 5.220 4 0.032 M +nWE C14M R -0.093 M 2.033 4 +nWE80 C14M R 1.630 4 0.329 6 + + +// Clock to Output Delay + +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +------------------------------------------------------------------------ +BA[0] C14M R 10.424 4 3.355 M +BA[1] C14M R 10.424 4 3.355 M +CKE C14M R 10.424 4 3.355 M +DQMH C14M R 10.404 4 3.362 M +DQML C14M R 10.404 4 3.362 M +Dout[0] C14M F 10.750 4 3.634 M +Dout[1] C14M F 10.750 4 3.634 M +Dout[2] C14M F 10.739 4 3.628 M +Dout[3] C14M F 10.750 4 3.634 M +Dout[4] C14M F 10.739 4 3.628 M +Dout[5] C14M F 10.739 4 3.628 M +Dout[6] C14M F 10.750 4 3.634 M +Dout[7] C14M F 10.750 4 3.634 M +LED C14M R 21.299 4 8.576 M +RA[0] C14M R 12.236 4 3.758 M +RA[10] C14M R 10.490 4 3.360 M +RA[11] C14M R 10.424 4 3.355 M +RA[1] C14M R 10.490 4 3.360 M +RA[2] C14M R 10.490 4 3.360 M +RA[3] C14M R 11.808 4 3.656 M +RA[4] C14M R 10.490 4 3.360 M +RA[5] C14M R 10.490 4 3.360 M +RA[6] C14M R 10.490 4 3.360 M +RA[7] C14M R 10.490 4 3.360 M +RA[8] C14M R 10.490 4 3.360 M +RA[9] C14M R 10.490 4 3.360 M +Vout[0] C14M F 11.348 4 3.872 M +Vout[1] C14M F 11.434 4 3.871 M +Vout[2] C14M F 11.348 4 3.872 M +Vout[3] C14M F 11.434 4 3.871 M +Vout[4] C14M F 11.348 4 3.872 M +Vout[5] C14M F 11.348 4 3.872 M +Vout[6] C14M F 11.434 4 3.871 M +Vout[7] C14M F 11.434 4 3.871 M +nCAS C14M R 10.424 4 3.355 M +nCS C14M R 10.424 4 3.355 M +nDOE C14M R 14.217 4 4.353 M +nRAS C14M R 10.424 4 3.355 M +nRWE C14M R 10.424 4 3.355 M +WARNING: you must also run trce with hold speed: 4 +WARNING: you must also run trce with hold speed: 6 +WARNING: you must also run trce with setup speed: M diff --git a/CPLD/LCMXO2-1200HC/msg_file.log b/CPLD/LCMXO2-1200HC/msg_file.log new file mode 100644 index 0000000..e3ee81e --- /dev/null +++ b/CPLD/LCMXO2-1200HC/msg_file.log @@ -0,0 +1,29 @@ +SCUBA, Version Diamond (64-bit) 3.12.1.454 +Wed Sep 20 04:45:58 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 321 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 1200 + Circuit name : REFB + Module type : efb + Module Version : 1.2 + Ports : + Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] + Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq + I/O buffer : not inserted + EDIF output : REFB.edn + Verilog output : REFB.v + Verilog template : REFB_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : REFB.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + diff --git a/CPLD/LCMXO2-1200HC/promote.xml b/CPLD/LCMXO2-1200HC/promote.xml new file mode 100644 index 0000000..fc0beb9 --- /dev/null +++ b/CPLD/LCMXO2-1200HC/promote.xml @@ -0,0 +1,3 @@ + + + diff --git a/CPLD/LCMXO2-1200HC/reportview.xml b/CPLD/LCMXO2-1200HC/reportview.xml new file mode 100644 index 0000000..145f9dd --- /dev/null +++ b/CPLD/LCMXO2-1200HC/reportview.xml @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/.setting.ini b/CPLD/LCMXO2-640HC/.setting.ini new file mode 100644 index 0000000..7a1e629 --- /dev/null +++ b/CPLD/LCMXO2-640HC/.setting.ini @@ -0,0 +1,4 @@ +[General] +PAR.auto_tasks=PARTrace, IOTiming +Map.auto_tasks=MapTrace, MapVerilogSimFile +Export.auto_tasks=IBIS, TimingSimFileVlg, Bitgen, Jedecgen diff --git a/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf b/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf new file mode 100644 index 0000000..7165bc8 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf @@ -0,0 +1,20 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC1.sty b/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC1.sty new file mode 100644 index 0000000..feec63c --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC1.sty @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html b/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html new file mode 100644 index 0000000..decf099 --- /dev/null +++ b/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC_tcl.html @@ -0,0 +1,70 @@ + +Lattice TCL Log + + +
    pn230921045933
+#Start recording tcl command: 9/21/2023 04:58:25
+#Project Location: //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC; Project name: RAM2E_LCMXO2_640HC
+prj_project open "//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf"
+prj_run Export -impl impl1 -forceAll
+#Stop recording: 9/21/2023 04:59:33
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    + + diff --git a/CPLD/LCMXO2-640HC/REFB.edn b/CPLD/LCMXO2-640HC/REFB.edn new file mode 100644 index 0000000..3040a1d --- /dev/null +++ b/CPLD/LCMXO2-640HC/REFB.edn @@ -0,0 +1,550 @@ +(edif REFB + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2023 9 20 4 17 14) + (program "SCUBA" (version "Diamond (64-bit) 3.12.1.454")))) + (comment "C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 ") + (library ORCLIB + (edifLevel 0) + (technology + (numberDefinition)) + (cell VHI + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell VLO + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port Z + (direction OUTPUT))))) + (cell EFB + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port WBCLKI + (direction INPUT)) + (port WBRSTI + (direction INPUT)) + (port WBCYCI + (direction INPUT)) + (port WBSTBI + (direction INPUT)) + (port WBWEI + (direction INPUT)) + (port WBADRI7 + (direction INPUT)) + (port WBADRI6 + (direction INPUT)) + (port WBADRI5 + (direction INPUT)) + (port WBADRI4 + (direction INPUT)) + (port WBADRI3 + (direction INPUT)) + (port WBADRI2 + (direction INPUT)) + (port WBADRI1 + (direction INPUT)) + (port WBADRI0 + (direction INPUT)) + (port WBDATI7 + (direction INPUT)) + (port WBDATI6 + (direction INPUT)) + (port WBDATI5 + (direction INPUT)) + (port WBDATI4 + (direction INPUT)) + (port WBDATI3 + (direction INPUT)) + (port WBDATI2 + (direction INPUT)) + (port WBDATI1 + (direction INPUT)) + (port WBDATI0 + (direction INPUT)) + (port PLL0DATI7 + (direction INPUT)) + (port PLL0DATI6 + (direction INPUT)) + (port PLL0DATI5 + (direction INPUT)) + (port PLL0DATI4 + (direction INPUT)) + (port PLL0DATI3 + (direction INPUT)) + (port PLL0DATI2 + (direction INPUT)) + (port PLL0DATI1 + (direction INPUT)) + (port PLL0DATI0 + (direction INPUT)) + (port PLL0ACKI + (direction INPUT)) + (port PLL1DATI7 + (direction INPUT)) + (port PLL1DATI6 + (direction INPUT)) + (port PLL1DATI5 + (direction INPUT)) + (port PLL1DATI4 + (direction INPUT)) + (port PLL1DATI3 + (direction INPUT)) + (port PLL1DATI2 + (direction INPUT)) + (port PLL1DATI1 + (direction INPUT)) + (port PLL1DATI0 + (direction INPUT)) + (port PLL1ACKI + (direction INPUT)) + (port I2C1SCLI + (direction INPUT)) + (port I2C1SDAI + (direction INPUT)) + (port I2C2SCLI + (direction INPUT)) + (port I2C2SDAI + (direction INPUT)) + (port SPISCKI + (direction INPUT)) + (port SPIMISOI + (direction INPUT)) + (port SPIMOSII + (direction INPUT)) + (port SPISCSN + (direction INPUT)) + (port TCCLKI + (direction INPUT)) + (port TCRSTN + (direction INPUT)) + (port TCIC + (direction INPUT)) + (port UFMSN + (direction INPUT)) + (port WBDATO7 + (direction OUTPUT)) + (port WBDATO6 + (direction OUTPUT)) + (port WBDATO5 + (direction OUTPUT)) + (port WBDATO4 + (direction OUTPUT)) + (port WBDATO3 + (direction OUTPUT)) + (port WBDATO2 + (direction OUTPUT)) + (port WBDATO1 + (direction OUTPUT)) + (port WBDATO0 + (direction OUTPUT)) + (port WBACKO + (direction OUTPUT)) + (port PLLCLKO + (direction OUTPUT)) + (port PLLRSTO + (direction OUTPUT)) + (port PLL0STBO + (direction OUTPUT)) + (port PLL1STBO + (direction OUTPUT)) + (port PLLWEO + (direction OUTPUT)) + (port PLLADRO4 + (direction OUTPUT)) + (port PLLADRO3 + (direction OUTPUT)) + (port PLLADRO2 + (direction OUTPUT)) + (port PLLADRO1 + (direction OUTPUT)) + (port PLLADRO0 + (direction OUTPUT)) + (port PLLDATO7 + (direction OUTPUT)) + (port PLLDATO6 + (direction OUTPUT)) + (port PLLDATO5 + (direction OUTPUT)) + (port PLLDATO4 + (direction OUTPUT)) + (port PLLDATO3 + (direction OUTPUT)) + (port PLLDATO2 + (direction OUTPUT)) + (port PLLDATO1 + (direction OUTPUT)) + (port PLLDATO0 + (direction OUTPUT)) + (port I2C1SCLO + (direction OUTPUT)) + (port I2C1SCLOEN + (direction OUTPUT)) + (port I2C1SDAO + (direction OUTPUT)) + (port I2C1SDAOEN + (direction OUTPUT)) + (port I2C2SCLO + (direction OUTPUT)) + (port I2C2SCLOEN + (direction OUTPUT)) + (port I2C2SDAO + (direction OUTPUT)) + (port I2C2SDAOEN + (direction OUTPUT)) + (port I2C1IRQO + (direction OUTPUT)) + (port I2C2IRQO + (direction OUTPUT)) + (port SPISCKO + (direction OUTPUT)) + (port SPISCKEN + (direction OUTPUT)) + (port SPIMISOO + (direction OUTPUT)) + (port SPIMISOEN + (direction OUTPUT)) + (port SPIMOSIO + (direction OUTPUT)) + (port SPIMOSIEN + (direction OUTPUT)) + (port SPIMCSN7 + (direction OUTPUT)) + (port SPIMCSN6 + (direction OUTPUT)) + (port SPIMCSN5 + (direction OUTPUT)) + (port SPIMCSN4 + (direction OUTPUT)) + (port SPIMCSN3 + (direction OUTPUT)) + (port SPIMCSN2 + (direction OUTPUT)) + (port SPIMCSN1 + (direction OUTPUT)) + (port SPIMCSN0 + (direction OUTPUT)) + (port SPICSNEN + (direction OUTPUT)) + (port SPIIRQO + (direction OUTPUT)) + (port TCINT + (direction OUTPUT)) + (port TCOC + (direction OUTPUT)) + (port WBCUFMIRQ + (direction OUTPUT)) + (port CFGWAKE + (direction OUTPUT)) + (port CFGSTDBY + (direction OUTPUT))))) + (cell REFB + (cellType GENERIC) + (view view1 + (viewType NETLIST) + (interface + (port wb_clk_i + (direction INPUT)) + (port wb_rst_i + (direction INPUT)) + (port wb_cyc_i + (direction INPUT)) + (port wb_stb_i + (direction INPUT)) + (port wb_we_i + (direction INPUT)) + (port (array (rename wb_adr_i "wb_adr_i(7:0)") 8) + (direction INPUT)) + (port (array (rename wb_dat_i "wb_dat_i(7:0)") 8) + (direction INPUT)) + (port (array (rename wb_dat_o "wb_dat_o(7:0)") 8) + (direction OUTPUT)) + (port wb_ack_o + (direction OUTPUT)) + (port wbc_ufm_irq + (direction OUTPUT))) + (property NGD_DRC_MASK (integer 1)) + (contents + (instance scuba_vhi_inst + (viewRef view1 + (cellRef VHI))) + (instance scuba_vlo_inst + (viewRef view1 + (cellRef VLO))) + (instance EFBInst_0 + (viewRef view1 + (cellRef EFB)) + (property UFM_INIT_FILE_FORMAT + (string "HEX")) + (property UFM_INIT_FILE_NAME + (string "../RAM2E-LCMXO2.mem")) + (property UFM_INIT_ALL_ZEROS + (string "DISABLED")) + (property UFM_INIT_START_PAGE + (string "190")) + (property UFM_INIT_PAGES + (string "1")) + (property DEV_DENSITY + (string "640L")) + (property EFB_UFM + (string "ENABLED")) + (property TC_ICAPTURE + (string "DISABLED")) + (property TC_OVERFLOW + (string "DISABLED")) + (property TC_ICR_INT + (string "OFF")) + (property TC_OCR_INT + (string "OFF")) + (property TC_OV_INT + (string "OFF")) + (property TC_TOP_SEL + (string "OFF")) + (property TC_RESETN + (string "ENABLED")) + (property TC_OC_MODE + (string "TOGGLE")) + (property TC_OCR_SET + (string "32767")) + (property TC_TOP_SET + (string "65535")) + (property GSR + (string "ENABLED")) + (property TC_CCLK_SEL + (string "1")) + (property TC_MODE + (string "CTCM")) + (property TC_SCLK_SEL + (string "PCLOCK")) + (property EFB_TC_PORTMODE + (string "WB")) + (property EFB_TC + (string "DISABLED")) + (property SPI_WAKEUP + (string "DISABLED")) + (property SPI_INTR_RXOVR + (string "DISABLED")) + (property SPI_INTR_TXOVR + (string "DISABLED")) + (property SPI_INTR_RXRDY + (string "DISABLED")) + (property SPI_INTR_TXRDY + (string "DISABLED")) + (property SPI_SLAVE_HANDSHAKE + (string "DISABLED")) + (property SPI_PHASE_ADJ + (string "DISABLED")) + (property SPI_CLK_INV + (string "DISABLED")) + (property SPI_LSB_FIRST + (string "DISABLED")) + (property SPI_CLK_DIVIDER + (string "1")) + (property SPI_MODE + (string "MASTER")) + (property EFB_SPI + (string "DISABLED")) + (property I2C2_WAKEUP + (string "DISABLED")) + (property I2C2_GEN_CALL + (string "DISABLED")) + (property I2C2_CLK_DIVIDER + (string "1")) + (property I2C2_BUS_PERF + (string "100kHz")) + (property I2C2_SLAVE_ADDR + (string "0b1000010")) + (property I2C2_ADDRESSING + (string "7BIT")) + (property EFB_I2C2 + (string "DISABLED")) + (property I2C1_WAKEUP + (string "DISABLED")) + (property I2C1_GEN_CALL + (string "DISABLED")) + (property I2C1_CLK_DIVIDER + (string "1")) + (property I2C1_BUS_PERF + (string "100kHz")) + (property I2C1_SLAVE_ADDR + (string "0b1000001")) + (property I2C1_ADDRESSING + (string "7BIT")) + (property EFB_I2C1 + (string "DISABLED")) + (property EFB_WB_CLK_FREQ + (string "14.4"))) + (net scuba_vhi + (joined + (portRef Z (instanceRef scuba_vhi_inst)) + (portRef UFMSN (instanceRef EFBInst_0)))) + (net scuba_vlo + (joined + (portRef Z (instanceRef scuba_vlo_inst)) + (portRef PLL1DATI7 (instanceRef EFBInst_0)) + (portRef PLL1DATI6 (instanceRef EFBInst_0)) + (portRef PLL1DATI5 (instanceRef EFBInst_0)) + (portRef PLL1DATI4 (instanceRef EFBInst_0)) + (portRef PLL1DATI3 (instanceRef EFBInst_0)) + (portRef PLL1DATI2 (instanceRef EFBInst_0)) + (portRef PLL1DATI1 (instanceRef EFBInst_0)) + (portRef PLL1DATI0 (instanceRef EFBInst_0)) + (portRef PLL1ACKI (instanceRef EFBInst_0)) + (portRef PLL0DATI7 (instanceRef EFBInst_0)) + (portRef PLL0DATI6 (instanceRef EFBInst_0)) + (portRef PLL0DATI5 (instanceRef EFBInst_0)) + (portRef PLL0DATI4 (instanceRef EFBInst_0)) + (portRef PLL0DATI3 (instanceRef EFBInst_0)) + (portRef PLL0DATI2 (instanceRef EFBInst_0)) + (portRef PLL0DATI1 (instanceRef EFBInst_0)) + (portRef PLL0DATI0 (instanceRef EFBInst_0)) + (portRef PLL0ACKI (instanceRef EFBInst_0)) + (portRef TCIC (instanceRef EFBInst_0)) + (portRef TCRSTN (instanceRef EFBInst_0)) + (portRef TCCLKI (instanceRef EFBInst_0)) + (portRef SPISCSN (instanceRef EFBInst_0)) + (portRef SPIMOSII (instanceRef EFBInst_0)) + (portRef SPIMISOI (instanceRef EFBInst_0)) + (portRef SPISCKI (instanceRef EFBInst_0)) + (portRef I2C2SDAI (instanceRef EFBInst_0)) + (portRef I2C2SCLI (instanceRef EFBInst_0)) + (portRef I2C1SDAI (instanceRef EFBInst_0)) + (portRef I2C1SCLI (instanceRef EFBInst_0)))) + (net wbc_ufm_irq + (joined + (portRef wbc_ufm_irq) + (portRef WBCUFMIRQ (instanceRef EFBInst_0)))) + (net wb_ack_o + (joined + (portRef wb_ack_o) + (portRef WBACKO (instanceRef EFBInst_0)))) + (net wb_dat_o7 + (joined + (portRef (member wb_dat_o 0)) + (portRef WBDATO7 (instanceRef EFBInst_0)))) + (net wb_dat_o6 + (joined + (portRef (member wb_dat_o 1)) + (portRef WBDATO6 (instanceRef EFBInst_0)))) + (net wb_dat_o5 + (joined + (portRef (member wb_dat_o 2)) + (portRef WBDATO5 (instanceRef EFBInst_0)))) + (net wb_dat_o4 + (joined + (portRef (member wb_dat_o 3)) + (portRef WBDATO4 (instanceRef EFBInst_0)))) + (net wb_dat_o3 + (joined + (portRef (member wb_dat_o 4)) + (portRef WBDATO3 (instanceRef EFBInst_0)))) + (net wb_dat_o2 + (joined + (portRef (member wb_dat_o 5)) + (portRef WBDATO2 (instanceRef EFBInst_0)))) + (net wb_dat_o1 + (joined + (portRef (member wb_dat_o 6)) + (portRef WBDATO1 (instanceRef EFBInst_0)))) + (net wb_dat_o0 + (joined + (portRef (member wb_dat_o 7)) + (portRef WBDATO0 (instanceRef EFBInst_0)))) + (net wb_dat_i7 + (joined + (portRef (member wb_dat_i 0)) + (portRef WBDATI7 (instanceRef EFBInst_0)))) + (net wb_dat_i6 + (joined + (portRef (member wb_dat_i 1)) + (portRef WBDATI6 (instanceRef EFBInst_0)))) + (net wb_dat_i5 + (joined + (portRef (member wb_dat_i 2)) + (portRef WBDATI5 (instanceRef EFBInst_0)))) + (net wb_dat_i4 + (joined + (portRef (member wb_dat_i 3)) + (portRef WBDATI4 (instanceRef EFBInst_0)))) + (net wb_dat_i3 + (joined + (portRef (member wb_dat_i 4)) + (portRef WBDATI3 (instanceRef EFBInst_0)))) + (net wb_dat_i2 + (joined + (portRef (member wb_dat_i 5)) + (portRef WBDATI2 (instanceRef EFBInst_0)))) + (net wb_dat_i1 + (joined + (portRef (member wb_dat_i 6)) + (portRef WBDATI1 (instanceRef EFBInst_0)))) + (net wb_dat_i0 + (joined + (portRef (member wb_dat_i 7)) + (portRef WBDATI0 (instanceRef EFBInst_0)))) + (net wb_adr_i7 + (joined + (portRef (member wb_adr_i 0)) + (portRef WBADRI7 (instanceRef EFBInst_0)))) + (net wb_adr_i6 + (joined + (portRef (member wb_adr_i 1)) + (portRef WBADRI6 (instanceRef EFBInst_0)))) + (net wb_adr_i5 + (joined + (portRef (member wb_adr_i 2)) + (portRef WBADRI5 (instanceRef EFBInst_0)))) + (net wb_adr_i4 + (joined + (portRef (member wb_adr_i 3)) + (portRef WBADRI4 (instanceRef EFBInst_0)))) + (net wb_adr_i3 + (joined + (portRef (member wb_adr_i 4)) + (portRef WBADRI3 (instanceRef EFBInst_0)))) + (net wb_adr_i2 + (joined + (portRef (member wb_adr_i 5)) + (portRef WBADRI2 (instanceRef EFBInst_0)))) + (net wb_adr_i1 + (joined + (portRef (member wb_adr_i 6)) + (portRef WBADRI1 (instanceRef EFBInst_0)))) + (net wb_adr_i0 + (joined + (portRef (member wb_adr_i 7)) + (portRef WBADRI0 (instanceRef EFBInst_0)))) + (net wb_we_i + (joined + (portRef wb_we_i) + (portRef WBWEI (instanceRef EFBInst_0)))) + (net wb_stb_i + (joined + (portRef wb_stb_i) + (portRef WBSTBI (instanceRef EFBInst_0)))) + (net wb_cyc_i + (joined + (portRef wb_cyc_i) + (portRef WBCYCI (instanceRef EFBInst_0)))) + (net wb_rst_i + (joined + (portRef wb_rst_i) + (portRef WBRSTI (instanceRef EFBInst_0)))) + (net wb_clk_i + (joined + (portRef wb_clk_i) + (portRef WBCLKI (instanceRef EFBInst_0)))))))) + (design REFB + (cellRef REFB + (libraryRef ORCLIB))) +) diff --git a/CPLD/LCMXO2-640HC/REFB.ipx b/CPLD/LCMXO2-640HC/REFB.ipx new file mode 100644 index 0000000..07d8d58 --- /dev/null +++ b/CPLD/LCMXO2-640HC/REFB.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/CPLD/LCMXO2-640HC/REFB.lpc b/CPLD/LCMXO2-640HC/REFB.lpc new file mode 100644 index 0000000..6bd84ca --- /dev/null +++ b/CPLD/LCMXO2-640HC/REFB.lpc @@ -0,0 +1,141 @@ +[Device] +Family=machxo2 +PartType=LCMXO2-640HC +PartName=LCMXO2-640HC-4TG100C +SpeedGrade=4 +Package=TQFP100 +OperatingCondition=COM +Status=S + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=EFB +CoreRevision=1.2 +ModuleName=REFB +SourceFormat=Verilog HDL +ParameterFileVersion=1.0 +Date=09/20/2023 +Time=04:17:14 + +[Parameters] +Verilog=1 +VHDL=0 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +freq= +i2c1=0 +i2c1config=0 +i2c1_addr=7-Bit Addressing +i2c1_ce=0 +i2c1_freq=100 +i2c1_sa=10000 +i2c1_we=0 +i2c2=0 +i2c2_addr=7-Bit Addressing +i2c2_ce=0 +i2c2_freq=100 +i2c2_sa=10000 +i2c2_we=0 +ufm_addr=7-Bit Addressing +ufm_sa=10000 +pll=0 +pll_cnt=1 +spi=0 +spi_clkinv=0 +spi_cs=1 +spi_en=0 +spi_freq=1 +spi_lsb=0 +spi_mode=Slave +spi_ib=0 +spi_ph=0 +spi_hs=0 +spi_rxo=0 +spi_rxr=0 +spi_txo=0 +spi_txr=0 +spi_we=0 +static_tc=Static +tc=0 +tc_clkinv=Positive +tc_ctr=1 +tc_div=1 +tc_ipcap=0 +tc_mode=CTCM +tc_ocr=32767 +tc_oflow=1 +tc_o=TOGGLE +tc_opcomp=0 +tc_osc=0 +tc_sa_oflow=0 +tc_top=65535 +ufm=1 +ufm0=0 +ufm1=0 +ufm2=0 +ufm3=0 +ufm_cfg0=0 +ufm_cfg1=0 +wb_clk_freq=14.4 +ufm_usage=SHARED_EBR_TAG +ufm_ebr=190 +ufm_remain= +mem_size=1 +ufm_start= +ufm_init=mem +memfile=../RAM2E-LCMXO2.mem +ufm_dt=hex +ufm0_ebr= +mem_size0=1 +ufm0_init=0 +memfile0= +ufm0_dt=hex +ufm1_ebr= +mem_size1=1 +ufm1_init=0 +memfile1= +ufm1_dt=hex +ufm2_ebr= +mem_size2=1 +ufm2_init=0 +memfile2= +ufm2_dt=hex +ufm3_ebr= +mem_size3=1 +ufm3_init=0 +memfile3= +ufm3_dt=hex +ufm_cfg0_ebr= +mem_size_cfg0=1 +ufm_cfg0_init=0 +memfile_cfg0= +ufm_cfg0_dt=hex +ufm_cfg1_ebr= +mem_size_cfg1=1 +ufm_cfg1_init=0 +memfile_cfg1= +ufm_cfg1_dt=hex +wb=1 +boot_option=Internal +efb_ufm=0 +boot_option_internal=Single Boot +internal_ufm0=0 +internal_ufm1=0 +efb_ufm_boot= +tamperdr=0 +t_pwd=0 +t_lockflash=0 +t_manmode=0 +t_jtagport=0 +t_sspiport=0 +t_sic2port=0 +t_wbport=0 +t_portlock=0 + +[Command] +cmd_line= -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 diff --git a/CPLD/LCMXO2-640HC/REFB.naf b/CPLD/LCMXO2-640HC/REFB.naf new file mode 100644 index 0000000..5c239f5 --- /dev/null +++ b/CPLD/LCMXO2-640HC/REFB.naf @@ -0,0 +1,31 @@ +wb_clk_i i +wb_rst_i i +wb_cyc_i i +wb_stb_i i +wb_we_i i +wb_adr_i[7] i +wb_adr_i[6] i +wb_adr_i[5] i +wb_adr_i[4] i +wb_adr_i[3] i +wb_adr_i[2] i +wb_adr_i[1] i +wb_adr_i[0] i +wb_dat_i[7] i +wb_dat_i[6] i +wb_dat_i[5] i +wb_dat_i[4] i +wb_dat_i[3] i +wb_dat_i[2] i +wb_dat_i[1] i +wb_dat_i[0] i +wb_dat_o[7] o +wb_dat_o[6] o +wb_dat_o[5] o +wb_dat_o[4] o +wb_dat_o[3] o +wb_dat_o[2] o +wb_dat_o[1] o +wb_dat_o[0] o +wb_ack_o o +wbc_ufm_irq o diff --git a/CPLD/LCMXO2-640HC/REFB.sort b/CPLD/LCMXO2-640HC/REFB.sort new file mode 100644 index 0000000..96fe0d5 --- /dev/null +++ b/CPLD/LCMXO2-640HC/REFB.sort @@ -0,0 +1 @@ +REFB.v diff --git a/CPLD/LCMXO2-640HC/REFB.srp b/CPLD/LCMXO2-640HC/REFB.srp new file mode 100644 index 0000000..95501ab --- /dev/null +++ b/CPLD/LCMXO2-640HC/REFB.srp @@ -0,0 +1,26 @@ +SCUBA, Version Diamond (64-bit) 3.12.1.454 +Wed Sep 20 04:17:14 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + + Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 + Circuit name : REFB + Module type : efb + Module Version : 1.2 + Ports : + Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] + Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq + I/O buffer : not inserted + EDIF output : REFB.edn + Verilog output : REFB.v + Verilog template : REFB_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : REFB.srp + Element Usage : + EFB : 1 + Estimated Resource Usage: diff --git a/CPLD/LCMXO2-640HC/REFB.sym b/CPLD/LCMXO2-640HC/REFB.sym new file mode 100644 index 0000000000000000000000000000000000000000..6588d30b2bc7e6a6518bfbc7efc6f7cfc3b4c069 GIT binary patch literal 466 zcmYk2F-XHu5QhJ23u;9u;?Th%Lnd*^AP6E3VlrxwilAtkq!vOejcGNwIEzzoa27`q zaTKTG;OOAwn90%E(f_?rYv9Pockk}qy@y@!D>FW%q7YW8DF)VLQ-CE|rOB}XbAvFG z2A2t2C%hJZf_JA!)Zd(bh)xjH$1O)G8lK7GjfJU%`rK~i)NSX;!U$fwpdr?AH1U} Ezqu<`l>h($ literal 0 HcmV?d00001 diff --git a/CPLD/LCMXO2-640HC/REFB.v b/CPLD/LCMXO2-640HC/REFB.v new file mode 100644 index 0000000..ff75724 --- /dev/null +++ b/CPLD/LCMXO2-640HC/REFB.v @@ -0,0 +1,113 @@ +/* Verilog netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 */ +/* Module Version: 1.2 */ +/* C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 */ +/* Wed Sep 20 04:17:14 2023 */ + + +`timescale 1 ns / 1 ps +module REFB (wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i, + wb_dat_i, wb_dat_o, wb_ack_o, wbc_ufm_irq)/* synthesis NGD_DRC_MASK=1 */; + input wire wb_clk_i; + input wire wb_rst_i; + input wire wb_cyc_i; + input wire wb_stb_i; + input wire wb_we_i; + input wire [7:0] wb_adr_i; + input wire [7:0] wb_dat_i; + output wire [7:0] wb_dat_o; + output wire wb_ack_o; + output wire wbc_ufm_irq; + + wire scuba_vhi; + wire scuba_vlo; + + VHI scuba_vhi_inst (.Z(scuba_vhi)); + + VLO scuba_vlo_inst (.Z(scuba_vlo)); + + defparam EFBInst_0.UFM_INIT_FILE_FORMAT = "HEX" ; + defparam EFBInst_0.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem" ; + defparam EFBInst_0.UFM_INIT_ALL_ZEROS = "DISABLED" ; + defparam EFBInst_0.UFM_INIT_START_PAGE = 190 ; + defparam EFBInst_0.UFM_INIT_PAGES = 1 ; + defparam EFBInst_0.DEV_DENSITY = "640L" ; + defparam EFBInst_0.EFB_UFM = "ENABLED" ; + defparam EFBInst_0.TC_ICAPTURE = "DISABLED" ; + defparam EFBInst_0.TC_OVERFLOW = "DISABLED" ; + defparam EFBInst_0.TC_ICR_INT = "OFF" ; + defparam EFBInst_0.TC_OCR_INT = "OFF" ; + defparam EFBInst_0.TC_OV_INT = "OFF" ; + defparam EFBInst_0.TC_TOP_SEL = "OFF" ; + defparam EFBInst_0.TC_RESETN = "ENABLED" ; + defparam EFBInst_0.TC_OC_MODE = "TOGGLE" ; + defparam EFBInst_0.TC_OCR_SET = 32767 ; + defparam EFBInst_0.TC_TOP_SET = 65535 ; + defparam EFBInst_0.GSR = "ENABLED" ; + defparam EFBInst_0.TC_CCLK_SEL = 1 ; + defparam EFBInst_0.TC_MODE = "CTCM" ; + defparam EFBInst_0.TC_SCLK_SEL = "PCLOCK" ; + defparam EFBInst_0.EFB_TC_PORTMODE = "WB" ; + defparam EFBInst_0.EFB_TC = "DISABLED" ; + defparam EFBInst_0.SPI_WAKEUP = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_RXOVR = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_TXOVR = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_RXRDY = "DISABLED" ; + defparam EFBInst_0.SPI_INTR_TXRDY = "DISABLED" ; + defparam EFBInst_0.SPI_SLAVE_HANDSHAKE = "DISABLED" ; + defparam EFBInst_0.SPI_PHASE_ADJ = "DISABLED" ; + defparam EFBInst_0.SPI_CLK_INV = "DISABLED" ; + defparam EFBInst_0.SPI_LSB_FIRST = "DISABLED" ; + defparam EFBInst_0.SPI_CLK_DIVIDER = 1 ; + defparam EFBInst_0.SPI_MODE = "MASTER" ; + defparam EFBInst_0.EFB_SPI = "DISABLED" ; + defparam EFBInst_0.I2C2_WAKEUP = "DISABLED" ; + defparam EFBInst_0.I2C2_GEN_CALL = "DISABLED" ; + defparam EFBInst_0.I2C2_CLK_DIVIDER = 1 ; + defparam EFBInst_0.I2C2_BUS_PERF = "100kHz" ; + defparam EFBInst_0.I2C2_SLAVE_ADDR = "0b1000010" ; + defparam EFBInst_0.I2C2_ADDRESSING = "7BIT" ; + defparam EFBInst_0.EFB_I2C2 = "DISABLED" ; + defparam EFBInst_0.I2C1_WAKEUP = "DISABLED" ; + defparam EFBInst_0.I2C1_GEN_CALL = "DISABLED" ; + defparam EFBInst_0.I2C1_CLK_DIVIDER = 1 ; + defparam EFBInst_0.I2C1_BUS_PERF = "100kHz" ; + defparam EFBInst_0.I2C1_SLAVE_ADDR = "0b1000001" ; + defparam EFBInst_0.I2C1_ADDRESSING = "7BIT" ; + defparam EFBInst_0.EFB_I2C1 = "DISABLED" ; + defparam EFBInst_0.EFB_WB_CLK_FREQ = "14.4" ; + EFB EFBInst_0 (.WBCLKI(wb_clk_i), .WBRSTI(wb_rst_i), .WBCYCI(wb_cyc_i), + .WBSTBI(wb_stb_i), .WBWEI(wb_we_i), .WBADRI7(wb_adr_i[7]), .WBADRI6(wb_adr_i[6]), + .WBADRI5(wb_adr_i[5]), .WBADRI4(wb_adr_i[4]), .WBADRI3(wb_adr_i[3]), + .WBADRI2(wb_adr_i[2]), .WBADRI1(wb_adr_i[1]), .WBADRI0(wb_adr_i[0]), + .WBDATI7(wb_dat_i[7]), .WBDATI6(wb_dat_i[6]), .WBDATI5(wb_dat_i[5]), + .WBDATI4(wb_dat_i[4]), .WBDATI3(wb_dat_i[3]), .WBDATI2(wb_dat_i[2]), + .WBDATI1(wb_dat_i[1]), .WBDATI0(wb_dat_i[0]), .PLL0DATI7(scuba_vlo), + .PLL0DATI6(scuba_vlo), .PLL0DATI5(scuba_vlo), .PLL0DATI4(scuba_vlo), + .PLL0DATI3(scuba_vlo), .PLL0DATI2(scuba_vlo), .PLL0DATI1(scuba_vlo), + .PLL0DATI0(scuba_vlo), .PLL0ACKI(scuba_vlo), .PLL1DATI7(scuba_vlo), + .PLL1DATI6(scuba_vlo), .PLL1DATI5(scuba_vlo), .PLL1DATI4(scuba_vlo), + .PLL1DATI3(scuba_vlo), .PLL1DATI2(scuba_vlo), .PLL1DATI1(scuba_vlo), + .PLL1DATI0(scuba_vlo), .PLL1ACKI(scuba_vlo), .I2C1SCLI(scuba_vlo), + .I2C1SDAI(scuba_vlo), .I2C2SCLI(scuba_vlo), .I2C2SDAI(scuba_vlo), + .SPISCKI(scuba_vlo), .SPIMISOI(scuba_vlo), .SPIMOSII(scuba_vlo), + .SPISCSN(scuba_vlo), .TCCLKI(scuba_vlo), .TCRSTN(scuba_vlo), .TCIC(scuba_vlo), + .UFMSN(scuba_vhi), .WBDATO7(wb_dat_o[7]), .WBDATO6(wb_dat_o[6]), + .WBDATO5(wb_dat_o[5]), .WBDATO4(wb_dat_o[4]), .WBDATO3(wb_dat_o[3]), + .WBDATO2(wb_dat_o[2]), .WBDATO1(wb_dat_o[1]), .WBDATO0(wb_dat_o[0]), + .WBACKO(wb_ack_o), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), .PLL1STBO(), + .PLLWEO(), .PLLADRO4(), .PLLADRO3(), .PLLADRO2(), .PLLADRO1(), .PLLADRO0(), + .PLLDATO7(), .PLLDATO6(), .PLLDATO5(), .PLLDATO4(), .PLLDATO3(), + .PLLDATO2(), .PLLDATO1(), .PLLDATO0(), .I2C1SCLO(), .I2C1SCLOEN(), + .I2C1SDAO(), .I2C1SDAOEN(), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAO(), + .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKO(), .SPISCKEN(), + .SPIMISOO(), .SPIMISOEN(), .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN7(), + .SPIMCSN6(), .SPIMCSN5(), .SPIMCSN4(), .SPIMCSN3(), .SPIMCSN2(), + .SPIMCSN1(), .SPIMCSN0(), .SPICSNEN(), .SPIIRQO(), .TCINT(), .TCOC(), + .WBCUFMIRQ(wbc_ufm_irq), .CFGWAKE(), .CFGSTDBY()); + + + + // exemplar begin + // exemplar end + +endmodule diff --git a/CPLD/LCMXO2-640HC/REFB_generate.log b/CPLD/LCMXO2-640HC/REFB_generate.log new file mode 100644 index 0000000..3c32a89 --- /dev/null +++ b/CPLD/LCMXO2-640HC/REFB_generate.log @@ -0,0 +1,44 @@ +Starting process: Module + +Starting process: + +SCUBA, Version Diamond (64-bit) 3.12.1.454 +Wed Sep 20 04:17:14 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 + Circuit name : REFB + Module type : efb + Module Version : 1.2 + Ports : + Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] + Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq + I/O buffer : not inserted + EDIF output : REFB.edn + Verilog output : REFB.v + Verilog template : REFB_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : REFB.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + +File: REFB.lpc created. + + +End process: completed successfully. + + +Total Warnings: 0 + +Total Errors: 0 + + diff --git a/CPLD/LCMXO2-640HC/REFB_tmpl.v b/CPLD/LCMXO2-640HC/REFB_tmpl.v new file mode 100644 index 0000000..4f87825 --- /dev/null +++ b/CPLD/LCMXO2-640HC/REFB_tmpl.v @@ -0,0 +1,8 @@ +/* Verilog module instantiation template generated by SCUBA Diamond (64-bit) 3.12.1.454 */ +/* Module Version: 1.2 */ +/* Wed Sep 20 04:17:14 2023 */ + +/* parameterized module instance */ +REFB __ (.wb_clk_i( ), .wb_rst_i( ), .wb_cyc_i( ), .wb_stb_i( ), + .wb_we_i( ), .wb_adr_i( ), .wb_dat_i( ), .wb_dat_o( ), .wb_ack_o( ), + .wbc_ufm_irq( )); diff --git a/CPLD/LCMXO2-640HC/_math_real.vhd b/CPLD/LCMXO2-640HC/_math_real.vhd new file mode 100644 index 0000000..e1215d8 --- /dev/null +++ b/CPLD/LCMXO2-640HC/_math_real.vhd @@ -0,0 +1,2574 @@ + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. +-- +-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package defines a standard for designers to use in +-- describing VHDL models that make use of common REAL constants +-- and common REAL elementary mathematical functions. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076- +-- 1993. +-- +-- Notes: +-- No declarations or definitions shall be included in, or +-- excluded from, this package. +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to provide a guideline for implementations to +-- verify their implementation of MATH_REAL. Tool developers may +-- choose to implement the package body in the most efficient +-- manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package MATH_REAL is + constant CopyRightNotice: STRING + := "Copyright 1996 IEEE. All rights reserved."; + + -- + -- Constant Definitions + -- + constant MATH_E : REAL := 2.71828_18284_59045_23536; + -- Value of e + constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160; + -- Value of 1/e + constant MATH_PI : REAL := 3.14159_26535_89793_23846; + -- Value of pi + constant MATH_2_PI : REAL := 6.28318_53071_79586_47693; + -- Value of 2*pi + constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154; + -- Value of 1/pi + constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923; + -- Value of pi/2 + constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615; + -- Value of pi/3 + constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962; + -- Value of pi/4 + constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769; + -- Value 3*pi/2 + constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942; + -- Natural log of 2 + constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402; + -- Natural log of 10 + constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074; + -- Log base 2 of e + constant MATH_LOG10_OF_E: REAL := 0.43429_44819_03251_82765; + -- Log base 10 of e + constant MATH_SQRT_2: REAL := 1.41421_35623_73095_04880; + -- square root of 2 + constant MATH_1_OVER_SQRT_2: REAL := 0.70710_67811_86547_52440; + -- square root of 1/2 + constant MATH_SQRT_PI: REAL := 1.77245_38509_05516_02730; + -- square root of pi + constant MATH_DEG_TO_RAD: REAL := 0.01745_32925_19943_29577; + -- Conversion factor from degree to radian + constant MATH_RAD_TO_DEG: REAL := 57.29577_95130_82320_87680; + -- Conversion factor from radian to degree + + -- + -- Function Declarations + -- + function SIGN (X: in REAL ) return REAL; + -- Purpose: + -- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0 + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIGN(X)) <= 1.0 + -- Notes: + -- None + + function CEIL (X : in REAL ) return REAL; + -- Purpose: + -- Returns smallest INTEGER value (as REAL) not less than X + -- Special values: + -- None + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CEIL(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function FLOOR (X : in REAL ) return REAL; + -- Purpose: + -- Returns largest INTEGER value (as REAL) not greater than X + -- Special values: + -- FLOOR(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- FLOOR(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function ROUND (X : in REAL ) return REAL; + -- Purpose: + -- Rounds X to the nearest integer value (as real). If X is + -- halfway between two integers, rounding is away from 0.0 + -- Special values: + -- ROUND(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ROUND(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function TRUNC (X : in REAL ) return REAL; + -- Purpose: + -- Truncates X towards 0.0 and returns truncated value + -- Special values: + -- TRUNC(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- TRUNC(X) is mathematically unbounded + -- Notes: + -- a) Implementations have to support at least the domain + -- ABS(X) < REAL(INTEGER'HIGH) + + function "MOD" (X, Y: in REAL ) return REAL; + -- Purpose: + -- Returns floating point modulus of X/Y, with the same sign as + -- Y, and absolute value less than the absolute value of Y, and + -- for some INTEGER value N the result satisfies the relation + -- X = Y*N + MOD(X,Y) + -- Special values: + -- None + -- Domain: + -- X in REAL; Y in REAL and Y /= 0.0 + -- Error conditions: + -- Error if Y = 0.0 + -- Range: + -- ABS(MOD(X,Y)) < ABS(Y) + -- Notes: + -- None + + function REALMAX (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically larger of X and Y + -- Special values: + -- REALMAX(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMAX(X,Y) is mathematically unbounded + -- Notes: + -- None + + function REALMIN (X, Y : in REAL ) return REAL; + -- Purpose: + -- Returns the algebraically smaller of X and Y + -- Special values: + -- REALMIN(X,Y) = X when X = Y + -- Domain: + -- X in REAL; Y in REAL + -- Error conditions: + -- None + -- Range: + -- REALMIN(X,Y) is mathematically unbounded + -- Notes: + -- None + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE; variable X:out REAL); + -- Purpose: + -- Returns, in X, a pseudo-random number with uniform + -- distribution in the open interval (0.0, 1.0). + -- Special values: + -- None + -- Domain: + -- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398 + -- Error conditions: + -- Error if SEED1 or SEED2 outside of valid domain + -- Range: + -- 0.0 < X < 1.0 + -- Notes: + -- a) The semantics for this function are described by the + -- algorithm published by Pierre L'Ecuyer in "Communications + -- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774. + -- The algorithm is based on the combination of two + -- multiplicative linear congruential generators for 32-bit + -- platforms. + -- + -- b) Before the first call to UNIFORM, the seed values + -- (SEED1, SEED2) have to be initialized to values in the range + -- [1, 2147483562] and [1, 2147483398] respectively. The + -- seed values are modified after each call to UNIFORM. + -- + -- c) This random number generator is portable for 32-bit + -- computers, and it has a period of ~2.30584*(10**18) for each + -- set of seed values. + -- + -- d) For information on spectral tests for the algorithm, refer + -- to the L'Ecuyer article. + + function SQRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns square root of X + -- Special values: + -- SQRT(0.0) = 0.0 + -- SQRT(1.0) = 1.0 + -- Domain: + -- X >= 0.0 + -- Error conditions: + -- Error if X < 0.0 + -- Range: + -- SQRT(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of SQRT is + -- approximately given by: + -- SQRT(X) <= SQRT(REAL'HIGH) + + function CBRT (X : in REAL ) return REAL; + -- Purpose: + -- Returns cube root of X + -- Special values: + -- CBRT(0.0) = 0.0 + -- CBRT(1.0) = 1.0 + -- CBRT(-1.0) = -1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- CBRT(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of CBRT is approximately given by: + -- ABS(CBRT(X)) <= CBRT(REAL'HIGH) + + function "**" (X : in INTEGER; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0 + -- 0**Y = 0.0; Y > 0.0 + -- X**1.0 = REAL(X); X >= 0 + -- 1**Y = 1.0 + -- Domain: + -- X > 0 + -- X = 0 for Y > 0.0 + -- X < 0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0 and Y /= 0.0 + -- Error if X = 0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function "**" (X : in REAL; Y : in REAL) return REAL; + -- Purpose: + -- Returns Y power of X ==> X**Y + -- Special values: + -- X**0.0 = 1.0; X /= 0.0 + -- 0.0**Y = 0.0; Y > 0.0 + -- X**1.0 = X; X >= 0.0 + -- 1.0**Y = 1.0 + -- Domain: + -- X > 0.0 + -- X = 0.0 for Y > 0.0 + -- X < 0.0 for Y = 0.0 + -- Error conditions: + -- Error if X < 0.0 and Y /= 0.0 + -- Error if X = 0.0 and Y <= 0.0 + -- Range: + -- X**Y >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range for "**" is + -- approximately given by: + -- X**Y <= REAL'HIGH + + function EXP (X : in REAL ) return REAL; + -- Purpose: + -- Returns e**X; where e = MATH_E + -- Special values: + -- EXP(0.0) = 1.0 + -- EXP(1.0) = MATH_E + -- EXP(-1.0) = MATH_1_OVER_E + -- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH) + -- Domain: + -- X in REAL such that EXP(X) <= REAL'HIGH + -- Error conditions: + -- Error if X > LOG(REAL'HIGH) + -- Range: + -- EXP(X) >= 0.0 + -- Notes: + -- a) The usable domain of EXP is approximately given by: + -- X <= LOG(REAL'HIGH) + + function LOG (X : in REAL ) return REAL; + -- Purpose: + -- Returns natural logarithm of X + -- Special values: + -- LOG(1.0) = 0.0 + -- LOG(MATH_E) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG is approximately given by: + -- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH) + + function LOG2 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 2 of X + -- Special values: + -- LOG2(1.0) = 0.0 + -- LOG2(2.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG2(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG2 is approximately given by: + -- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH) + + function LOG10 (X : in REAL ) return REAL; + -- Purpose: + -- Returns logarithm base 10 of X + -- Special values: + -- LOG10(1.0) = 0.0 + -- LOG10(10.0) = 1.0 + -- Domain: + -- X > 0.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Range: + -- LOG10(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of LOG10 is approximately given by: + -- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH) + + function LOG (X: in REAL; BASE: in REAL) return REAL; + -- Purpose: + -- Returns logarithm base BASE of X + -- Special values: + -- LOG(1.0, BASE) = 0.0 + -- LOG(BASE, BASE) = 1.0 + -- Domain: + -- X > 0.0 + -- BASE > 0.0 + -- BASE /= 1.0 + -- Error conditions: + -- Error if X <= 0.0 + -- Error if BASE <= 0.0 + -- Error if BASE = 1.0 + -- Range: + -- LOG(X, BASE) is mathematically unbounded + -- Notes: + -- a) When BASE > 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE) + -- b) When 0.0 < BASE < 1.0, the reachable range of LOG is + -- approximately given by: + -- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE) + + function SIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns sine of X; X in radians + -- Special values: + -- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(SIN(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function COS ( X : in REAL ) return REAL; + -- Purpose: + -- Returns cosine of X; X in radians + -- Special values: + -- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an + -- INTEGER + -- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER + -- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(COS(X)) <= 1.0 + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function TAN (X : in REAL ) return REAL; + -- Purpose: + -- Returns tangent of X; X in radians + -- Special values: + -- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER + -- Domain: + -- X in REAL and + -- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER + -- Error conditions: + -- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an + -- INTEGER + -- Range: + -- TAN(X) is mathematically unbounded + -- Notes: + -- a) For larger values of ABS(X), degraded accuracy is allowed. + + function ARCSIN (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse sine of X + -- Special values: + -- ARCSIN(0.0) = 0.0 + -- ARCSIN(1.0) = MATH_PI_OVER_2 + -- ARCSIN(-1.0) = -MATH_PI_OVER_2 + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- ABS(ARCSIN(X) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCCOS (X : in REAL ) return REAL; + -- Purpose: + -- Returns inverse cosine of X + -- Special values: + -- ARCCOS(1.0) = 0.0 + -- ARCCOS(0.0) = MATH_PI_OVER_2 + -- ARCCOS(-1.0) = MATH_PI + -- Domain: + -- ABS(X) <= 1.0 + -- Error conditions: + -- Error if ABS(X) > 1.0 + -- Range: + -- 0.0 <= ARCCOS(X) <= MATH_PI + -- Notes: + -- None + + function ARCTAN (Y : in REAL) return REAL; + -- Purpose: + -- Returns the value of the angle in radians of the point + -- (1.0, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0) = 0.0 + -- Domain: + -- Y in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2 + -- Notes: + -- None + + function ARCTAN (Y : in REAL; X : in REAL) return REAL; + -- Purpose: + -- Returns the principal value of the angle in radians of + -- the point (X, Y), which is in rectangular coordinates + -- Special values: + -- ARCTAN(0.0, X) = 0.0 if X > 0.0 + -- ARCTAN(0.0, X) = MATH_PI if X < 0.0 + -- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0 + -- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0 + -- Domain: + -- Y in REAL + -- X in REAL, X /= 0.0 when Y = 0.0 + -- Error conditions: + -- Error if X = 0.0 and Y = 0.0 + -- Range: + -- -MATH_PI < ARCTAN(Y,X) <= MATH_PI + -- Notes: + -- None + + function SINH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic sine of X + -- Special values: + -- SINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- SINH(X) is mathematically unbounded + -- Notes: + -- a) The usable domain of SINH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + + function COSH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic cosine of X + -- Special values: + -- COSH(0.0) = 1.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- COSH(X) >= 1.0 + -- Notes: + -- a) The usable domain of COSH is approximately given by: + -- ABS(X) <= LOG(REAL'HIGH) + + function TANH (X : in REAL) return REAL; + -- Purpose: + -- Returns hyperbolic tangent of X + -- Special values: + -- TANH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ABS(TANH(X)) <= 1.0 + -- Notes: + -- None + + function ARCSINH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic sine of X + -- Special values: + -- ARCSINH(0.0) = 0.0 + -- Domain: + -- X in REAL + -- Error conditions: + -- None + -- Range: + -- ARCSINH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCSINH is approximately given by: + -- ABS(ARCSINH(X)) <= LOG(REAL'HIGH) + + function ARCCOSH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic cosine of X + -- Special values: + -- ARCCOSH(1.0) = 0.0 + -- Domain: + -- X >= 1.0 + -- Error conditions: + -- Error if X < 1.0 + -- Range: + -- ARCCOSH(X) >= 0.0 + -- Notes: + -- a) The upper bound of the reachable range of ARCCOSH is + -- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH) + + function ARCTANH (X : in REAL) return REAL; + -- Purpose: + -- Returns inverse hyperbolic tangent of X + -- Special values: + -- ARCTANH(0.0) = 0.0 + -- Domain: + -- ABS(X) < 1.0 + -- Error conditions: + -- Error if ABS(X) >= 1.0 + -- Range: + -- ARCTANH(X) is mathematically unbounded + -- Notes: + -- a) The reachable range of ARCTANH is approximately given by: + -- ABS(ARCTANH(X)) < LOG(REAL'HIGH) + +end MATH_REAL; + + + +------------------------------------------------------------------------ +-- +-- Copyright 1996 by IEEE. All rights reserved. + +-- This source file is an informative part of IEEE Std 1076.2-1996, IEEE Standard +-- VHDL Mathematical Packages. This source file may not be copied, sold, or +-- included with software that is sold without written permission from the IEEE +-- Standards Department. This source file may be used to implement this standard +-- and may be distributed in compiled form in any manner so long as the +-- compiled form does not allow direct decompilation of the original source file. +-- This source file may be copied for individual use between licensed users. +-- This source file is provided on an AS IS basis. The IEEE disclaims ANY +-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY +-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source +-- file shall indemnify and hold IEEE harmless from any damages or liability +-- arising out of the use thereof. + +-- +-- Title: Standard VHDL Mathematical Packages (IEEE Std 1076.2-1996, +-- MATH_REAL) +-- +-- Library: This package shall be compiled into a library +-- symbolically named IEEE. +-- +-- Developers: IEEE DASC VHDL Mathematical Packages Working Group +-- +-- Purpose: This package body is a nonnormative implementation of the +-- functionality defined in the MATH_REAL package declaration. +-- +-- Limitation: The values generated by the functions in this package may +-- vary from platform to platform, and the precision of results +-- is only guaranteed to be the minimum required by IEEE Std 1076 +-- -1993. +-- +-- Notes: +-- The "package declaration" defines the types, subtypes, and +-- declarations of MATH_REAL. +-- The standard mathematical definition and conventional meaning +-- of the mathematical functions that are part of this standard +-- represent the formal semantics of the implementation of the +-- MATH_REAL package declaration. The purpose of the MATH_REAL +-- package body is to clarify such semantics and provide a +-- guideline for implementations to verify their implementation +-- of MATH_REAL. Tool developers may choose to implement +-- the package body in the most efficient manner available to them. +-- +-- ----------------------------------------------------------------------------- +-- Version : 1.5 +-- Date : 24 July 1996 +-- ----------------------------------------------------------------------------- + +package body MATH_REAL is + + -- + -- Local Constants for Use in the Package Body Only + -- + constant MATH_E_P2 : REAL := 7.38905_60989_30650; -- e**2 + constant MATH_E_P10 : REAL := 22026.46579_48067_17; -- e**10 + constant MATH_EIGHT_PI : REAL := 25.13274_12287_18345_90770_115; --8*pi + constant MAX_ITER: INTEGER := 27; -- Maximum precision factor for cordic + constant MAX_COUNT: INTEGER := 150; -- Maximum count for number of tries + constant BASE_EPS: REAL := 0.00001; -- Factor for convergence criteria + constant KC : REAL := 6.0725293500888142e-01; -- Constant for cordic + + -- + -- Local Type Declarations for Cordic Operations + -- + type REAL_VECTOR is array (NATURAL range <>) of REAL; + type NATURAL_VECTOR is array (NATURAL range <>) of NATURAL; + subtype REAL_VECTOR_N is REAL_VECTOR (0 to MAX_ITER); + subtype REAL_ARR_2 is REAL_VECTOR (0 to 1); + subtype REAL_ARR_3 is REAL_VECTOR (0 to 2); + subtype QUADRANT is INTEGER range 0 to 3; + type CORDIC_MODE_TYPE is (ROTATION, VECTORING); + + -- + -- Auxiliary Functions for Cordic Algorithms + -- + function POWER_OF_2_SERIES (D : in NATURAL_VECTOR; INITIAL_VALUE : in REAL; + NUMBER_OF_VALUES : in NATURAL) return REAL_VECTOR is + -- Description: + -- Returns power of two for a vector of values + -- Notes: + -- None + -- + variable V : REAL_VECTOR (0 to NUMBER_OF_VALUES); + variable TEMP : REAL := INITIAL_VALUE; + variable FLAG : BOOLEAN := TRUE; + begin + for I in 0 to NUMBER_OF_VALUES loop + V(I) := TEMP; + for P in D'RANGE loop + if I = D(P) then + FLAG := FALSE; + exit; + end if; + end loop; + if FLAG then + TEMP := TEMP/2.0; + end if; + FLAG := TRUE; + end loop; + return V; + end POWER_OF_2_SERIES; + + + constant TWO_AT_MINUS : REAL_VECTOR := POWER_OF_2_SERIES( + NATURAL_VECTOR'(100, 90),1.0, + MAX_ITER); + + constant EPSILON : REAL_VECTOR_N := ( + 7.8539816339744827e-01, + 4.6364760900080606e-01, + 2.4497866312686413e-01, + 1.2435499454676144e-01, + 6.2418809995957351e-02, + 3.1239833430268277e-02, + 1.5623728620476830e-02, + 7.8123410601011116e-03, + 3.9062301319669717e-03, + 1.9531225164788189e-03, + 9.7656218955931937e-04, + 4.8828121119489829e-04, + 2.4414062014936175e-04, + 1.2207031189367021e-04, + 6.1035156174208768e-05, + 3.0517578115526093e-05, + 1.5258789061315760e-05, + 7.6293945311019699e-06, + 3.8146972656064960e-06, + 1.9073486328101870e-06, + 9.5367431640596080e-07, + 4.7683715820308876e-07, + 2.3841857910155801e-07, + 1.1920928955078067e-07, + 5.9604644775390553e-08, + 2.9802322387695303e-08, + 1.4901161193847654e-08, + 7.4505805969238281e-09 + ); + + function CORDIC ( X0 : in REAL; + Y0 : in REAL; + Z0 : in REAL; + N : in NATURAL; -- Precision factor + CORDIC_MODE : in CORDIC_MODE_TYPE -- Rotation (Z -> 0) + -- or vectoring (Y -> 0) + ) return REAL_ARR_3 is + -- Description: + -- Compute cordic values + -- Notes: + -- None + variable X : REAL := X0; + variable Y : REAL := Y0; + variable Z : REAL := Z0; + variable X_TEMP : REAL; + begin + if CORDIC_MODE = ROTATION then + for K in 0 to N loop + X_TEMP := X; + if ( Z >= 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + else + for K in 0 to N loop + X_TEMP := X; + if ( Y < 0.0) then + X := X - Y * TWO_AT_MINUS(K); + Y := Y + X_TEMP * TWO_AT_MINUS(K); + Z := Z - EPSILON(K); + else + X := X + Y * TWO_AT_MINUS(K); + Y := Y - X_TEMP * TWO_AT_MINUS(K); + Z := Z + EPSILON(K); + end if; + end loop; + end if; + return REAL_ARR_3'(X, Y, Z); + end CORDIC; + + -- + -- Bodies for Global Mathematical Functions Start Here + -- + function SIGN (X: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- None + begin + if ( X > 0.0 ) then + return 1.0; + elsif ( X < 0.0 ) then + return -1.0; + else + return 0.0; + end if; + end SIGN; + + function CEIL (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is X <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS(X) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD >= X then + return RD; + else + return RD + 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD <= X then + return RD + 1.0; + else + return RD; + end if; + end if; + end CEIL; + + function FLOOR (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) No conversion to an INTEGER type is expected, so truncate + -- cannot overflow for large arguments + -- b) The domain supported by this function is ABS(X) <= LARGE + -- c) Returns X if ABS(X) >= LARGE + + constant LARGE: REAL := REAL(INTEGER'HIGH); + variable RD: REAL; + + begin + if ABS( X ) >= LARGE then + return X; + end if; + + RD := REAL ( INTEGER(X)); + if RD = X then + return X; + end if; + + if X > 0.0 then + if RD <= X then + return RD; + else + return RD - 1.0; + end if; + elsif X = 0.0 then + return 0.0; + else + if RD >= X then + return RD - 1.0; + else + return RD; + end if; + end if; + end FLOOR; + + function ROUND (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X + 0.5) if X > 0 + -- c) Returns CEIL(X - 0.5) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X + 0.5); + elsif X < 0.0 then + return CEIL( X - 0.5); + else + return 0.0; + end if; + end ROUND; + + function TRUNC (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 if X = 0.0 + -- b) Returns FLOOR(X) if X > 0 + -- c) Returns CEIL(X) if X < 0 + + begin + if X > 0.0 then + return FLOOR(X); + elsif X < 0.0 then + return CEIL( X); + else + return 0.0; + end if; + end TRUNC; + + + + + function "MOD" (X, Y: in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable XNEGATIVE : BOOLEAN := X < 0.0; + variable YNEGATIVE : BOOLEAN := Y < 0.0; + variable VALUE : REAL; + begin + -- Check validity of input arguments + if (Y = 0.0) then + assert FALSE + report "MOD(X, 0.0) is undefined" + severity ERROR; + return 0.0; + end if; + + -- Compute value + if ( XNEGATIVE ) then + if ( YNEGATIVE ) then + VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + end if; + else + if ( YNEGATIVE ) then + VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); + else + VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); + end if; + end if; + + return VALUE; + end "MOD"; + + + function REALMAX (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMAX(X,Y) = X when X = Y + -- + begin + if X >= Y then + return X; + else + return Y; + end if; + end REALMAX; + + function REALMIN (X, Y : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) REALMIN(X,Y) = X when X = Y + -- + begin + if X <= Y then + return X; + else + return Y; + end if; + end REALMIN; + + + procedure UNIFORM(variable SEED1,SEED2:inout POSITIVE;variable X:out REAL) + is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + -- + variable Z, K: INTEGER; + variable TSEED1 : INTEGER := INTEGER'(SEED1); + variable TSEED2 : INTEGER := INTEGER'(SEED2); + begin + -- Check validity of arguments + if SEED1 > 2147483562 then + assert FALSE + report "SEED1 > 2147483562 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + if SEED2 > 2147483398 then + assert FALSE + report "SEED2 > 2147483398 in UNIFORM" + severity ERROR; + X := 0.0; + return; + end if; + + -- Compute new seed values and pseudo-random number + K := TSEED1/53668; + TSEED1 := 40014 * (TSEED1 - K * 53668) - K * 12211; + + if TSEED1 < 0 then + TSEED1 := TSEED1 + 2147483563; + end if; + + K := TSEED2/52774; + TSEED2 := 40692 * (TSEED2 - K * 52774) - K * 3791; + + if TSEED2 < 0 then + TSEED2 := TSEED2 + 2147483399; + end if; + + Z := TSEED1 - TSEED2; + if Z < 1 then + Z := Z + 2147483562; + end if; + + -- Get output values + SEED1 := POSITIVE'(TSEED1); + SEED2 := POSITIVE'(TSEED2); + X := REAL(Z)*4.656613e-10; + end UNIFORM; + + + + function SQRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = 0.5*[F(n) + x/F(n)] + -- b) Returns 0.0 on error + -- + + constant EPS : REAL := BASE_EPS*BASE_EPS; -- Convergence factor + + variable INIVAL: REAL; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + -- Check validity of argument + if ( X < 0.0 ) then + assert FALSE + report "X < 0.0 in SQRT(X)" + severity ERROR; + return 0.0; + end if; + + -- Get the square root for special cases + if X = 0.0 then + return 0.0; + else + if ( X = 1.0 ) then + return 1.0; + end if; + end if; + + -- Get the square root for general cases + INIVAL := EXP(LOG(X)*(0.5)); -- Mathematically correct but imprecise + OLDVAL := INIVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + + -- Check for relative and absolute error and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT) ) loop + OLDVAL := NEWVAL; + NEWVAL := (X/OLDVAL + OLDVAL)*0.5; + COUNT := COUNT + 1; + end loop; + return NEWVAL; + end SQRT; + + function CBRT (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Uses the Newton-Raphson approximation: + -- F(n+1) = (1/3)*[2*F(n) + x/F(n)**2]; + -- + constant EPS : REAL := BASE_EPS*BASE_EPS; + + variable INIVAL: REAL; + variable XLOCAL : REAL := X; + variable NEGATIVE : BOOLEAN := X < 0.0; + variable OLDVAL : REAL ; + variable NEWVAL : REAL ; + variable COUNT : INTEGER := 1; + + begin + + -- Compute root for special cases + if X = 0.0 then + return 0.0; + elsif ( X = 1.0 ) then + return 1.0; + else + if X = -1.0 then + return -1.0; + end if; + end if; + + -- Compute root for general cases + if NEGATIVE then + XLOCAL := -X; + end if; + + INIVAL := EXP(LOG(XLOCAL)/(3.0)); -- Mathematically correct but + -- imprecise + OLDVAL := INIVAL; + NEWVAL := (XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL -OLDVAL)/NEWVAL) > EPS ) OR + (ABS(NEWVAL - OLDVAL) > EPS ) ) AND + ( COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + NEWVAL :=(XLOCAL/(OLDVAL*OLDVAL) + 2.0*OLDVAL)/3.0; + COUNT := COUNT + 1; + end loop; + + if NEGATIVE then + NEWVAL := -NEWVAL; + end if; + + return NEWVAL; + end CBRT; + + function "**" (X : in INTEGER; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (REAL(X)); + end if; + + -- Get value for general case + return EXP (Y * LOG (REAL(X))); + end "**"; + + function "**" (X : in REAL; Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error condition + + begin + -- Check validity of argument + if ( ( X < 0.0 ) and ( Y /= 0.0 ) ) then + assert FALSE + report "X < 0.0 and Y /= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + if ( ( X = 0.0 ) and ( Y <= 0.0 ) ) then + assert FALSE + report "X = 0.0 and Y <= 0.0 in X**Y" + severity ERROR; + return 0.0; + end if; + + -- Get value for special cases + if ( X = 0.0 and Y > 0.0 ) then + return 0.0; + end if; + + if ( X = 1.0 ) then + return 1.0; + end if; + + if ( Y = 0.0 and X /= 0.0 ) then + return 1.0; + end if; + + if ( Y = 1.0) then + return (X); + end if; + + -- Get value for general case + return EXP (Y * LOG (X)); + end "**"; + + function EXP (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) This function computes the exponential using the following + -- series: + -- exp(x) = 1 + x + x**2/2! + x**3/3! + ... ; |x| < 1.0 + -- and reduces argument X to take advantage of exp(x+y) = + -- exp(x)*exp(y) + -- + -- b) This implementation limits X to be less than LOG(REAL'HIGH) + -- to avoid overflow. Returns REAL'HIGH when X reaches that + -- limit + -- + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS;-- Precision criteria + + variable RECIPROCAL: BOOLEAN := X < 0.0;-- Check sign of argument + variable XLOCAL : REAL := ABS(X); -- Use positive value + variable OLDVAL: REAL ; + variable COUNT: INTEGER ; + variable NEWVAL: REAL ; + variable LAST_TERM: REAL ; + variable FACTOR : REAL := 1.0; + + begin + -- Compute value for special cases + if X = 0.0 then + return 1.0; + end if; + + if XLOCAL = 1.0 then + if RECIPROCAL then + return MATH_1_OVER_E; + else + return MATH_E; + end if; + end if; + + if XLOCAL = 2.0 then + if RECIPROCAL then + return 1.0/MATH_E_P2; + else + return MATH_E_P2; + end if; + end if; + + if XLOCAL = 10.0 then + if RECIPROCAL then + return 1.0/MATH_E_P10; + else + return MATH_E_P10; + end if; + end if; + + if XLOCAL > LOG(REAL'HIGH) then + if RECIPROCAL then + return 0.0; + else + assert FALSE + report "X > LOG(REAL'HIGH) in EXP(X)" + severity NOTE; + return REAL'HIGH; + end if; + end if; + + -- Reduce argument to ABS(X) < 1.0 + while XLOCAL > 10.0 loop + XLOCAL := XLOCAL - 10.0; + FACTOR := FACTOR*MATH_E_P10; + end loop; + + while XLOCAL > 1.0 loop + XLOCAL := XLOCAL - 1.0; + FACTOR := FACTOR*MATH_E; + end loop; + + -- Compute value for case 0 < XLOCAL < 1 + OLDVAL := 1.0; + LAST_TERM := XLOCAL; + NEWVAL:= OLDVAL + LAST_TERM; + COUNT := 2; + + -- Check for relative and absolute errors and max count + while ( ( (ABS((NEWVAL - OLDVAL)/NEWVAL) > EPS) OR + (ABS(NEWVAL - OLDVAL) > EPS) ) AND + (COUNT < MAX_COUNT ) ) loop + OLDVAL := NEWVAL; + LAST_TERM := LAST_TERM*(XLOCAL / (REAL(COUNT))); + NEWVAL := OLDVAL + LAST_TERM; + COUNT := COUNT + 1; + end loop; + + -- Compute final value using exp(x+y) = exp(x)*exp(y) + NEWVAL := NEWVAL*FACTOR; + + if RECIPROCAL then + NEWVAL := 1.0/NEWVAL; + end if; + + return NEWVAL; + end EXP; + + + -- + -- Auxiliary Functions to Compute LOG + -- + function ILOGB(X: in REAL) return INTEGER IS + -- Description: + -- Returns n such that -1 <= ABS(X)/2^n < 2 + -- Notes: + -- None + + variable N: INTEGER := 0; + variable Y: REAL := ABS(X); + + begin + if(Y = 1.0 or Y = 0.0) then + return 0; + end if; + + if( Y > 1.0) then + while Y >= 2.0 loop + Y := Y/2.0; + N := N+1; + end loop; + return N; + end if; + + -- O < Y < 1 + while Y < 1.0 loop + Y := Y*2.0; + N := N -1; + end loop; + return N; + end ILOGB; + + function LDEXP(X: in REAL; N: in INTEGER) RETURN REAL IS + -- Description: + -- Returns X*2^n + -- Notes: + -- None + begin + return X*(2.0 ** N); + end LDEXP; + + function LOG (X : in REAL ) return REAL IS + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- + -- Notes: + -- a) Returns REAL'LOW on error + -- + -- Copyright (c) 1992 Regents of the University of California. + -- All rights reserved. + -- + -- Redistribution and use in source and binary forms, with or without + -- modification, are permitted provided that the following conditions + -- are met: + -- 1. Redistributions of source code must retain the above copyright + -- notice, this list of conditions and the following disclaimer. + -- 2. Redistributions in binary form must reproduce the above copyright + -- notice, this list of conditions and the following disclaimer in the + -- documentation and/or other materials provided with the distribution. + -- 3. All advertising materials mentioning features or use of this + -- software must display the following acknowledgement: + -- This product includes software developed by the University of + -- California, Berkeley and its contributors. + -- 4. Neither the name of the University nor the names of its + -- contributors may be used to endorse or promote products derived + -- from this software without specific prior written permission. + -- + -- THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' + -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + -- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR + -- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + -- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + -- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + -- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY + -- OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + -- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE + -- USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + -- DAMAGE. + -- + -- NOTE: This VHDL version was generated using the C version of the + -- original function by the IEEE VHDL Mathematical Package + -- Working Group (CS/JT) + + constant N: INTEGER := 128; + + -- Table of log(Fj) = logF_head[j] + logF_tail[j], for Fj = 1+j/128. + -- Used for generation of extend precision logarithms. + -- The constant 35184372088832 is 2^45, so the divide is exact. + -- It ensures correct reading of logF_head, even for inaccurate + -- decimal-to-binary conversion routines. (Everybody gets the + -- right answer for INTEGERs less than 2^53.) + -- Values for LOG(F) were generated using error < 10^-57 absolute + -- with the bc -l package. + + type REAL_VECTOR is array (NATURAL range <>) of REAL; + + constant A1:REAL := 0.08333333333333178827; + constant A2:REAL := 0.01250000000377174923; + constant A3:REAL := 0.002232139987919447809; + constant A4:REAL := 0.0004348877777076145742; + + constant LOGF_HEAD: REAL_VECTOR(0 TO N) := ( + 0.0, + 0.007782140442060381246, + 0.015504186535963526694, + 0.023167059281547608406, + 0.030771658666765233647, + 0.038318864302141264488, + 0.045809536031242714670, + 0.053244514518837604555, + 0.060624621816486978786, + 0.067950661908525944454, + 0.075223421237524235039, + 0.082443669210988446138, + 0.089612158689760690322, + 0.096729626458454731618, + 0.103796793681567578460, + 0.110814366340264314203, + 0.117783035656430001836, + 0.124703478501032805070, + 0.131576357788617315236, + 0.138402322859292326029, + 0.145182009844575077295, + 0.151916042025732167530, + 0.158605030176659056451, + 0.165249572895390883786, + 0.171850256926518341060, + 0.178407657472689606947, + 0.184922338493834104156, + 0.191394852999565046047, + 0.197825743329758552135, + 0.204215541428766300668, + 0.210564769107350002741, + 0.216873938300523150246, + 0.223143551314024080056, + 0.229374101064877322642, + 0.235566071312860003672, + 0.241719936886966024758, + 0.247836163904594286577, + 0.253915209980732470285, + 0.259957524436686071567, + 0.265963548496984003577, + 0.271933715484010463114, + 0.277868451003087102435, + 0.283768173130738432519, + 0.289633292582948342896, + 0.295464212893421063199, + 0.301261330578199704177, + 0.307025035294827830512, + 0.312755710004239517729, + 0.318453731118097493890, + 0.324119468654316733591, + 0.329753286372579168528, + 0.335355541920762334484, + 0.340926586970454081892, + 0.346466767346100823488, + 0.351976423156884266063, + 0.357455888922231679316, + 0.362905493689140712376, + 0.368325561158599157352, + 0.373716409793814818840, + 0.379078352934811846353, + 0.384411698910298582632, + 0.389716751140440464951, + 0.394993808240542421117, + 0.400243164127459749579, + 0.405465108107819105498, + 0.410659924985338875558, + 0.415827895143593195825, + 0.420969294644237379543, + 0.426084395310681429691, + 0.431173464818130014464, + 0.436236766774527495726, + 0.441274560805140936281, + 0.446287102628048160113, + 0.451274644139630254358, + 0.456237433481874177232, + 0.461175715122408291790, + 0.466089729924533457960, + 0.470979715219073113985, + 0.475845904869856894947, + 0.480688529345570714212, + 0.485507815781602403149, + 0.490303988045525329653, + 0.495077266798034543171, + 0.499827869556611403822, + 0.504556010751912253908, + 0.509261901790523552335, + 0.513945751101346104405, + 0.518607764208354637958, + 0.523248143765158602036, + 0.527867089620485785417, + 0.532464798869114019908, + 0.537041465897345915436, + 0.541597282432121573947, + 0.546132437597407260909, + 0.550647117952394182793, + 0.555141507540611200965, + 0.559615787935399566777, + 0.564070138285387656651, + 0.568504735352689749561, + 0.572919753562018740922, + 0.577315365035246941260, + 0.581691739635061821900, + 0.586049045003164792433, + 0.590387446602107957005, + 0.594707107746216934174, + 0.599008189645246602594, + 0.603290851438941899687, + 0.607555250224322662688, + 0.611801541106615331955, + 0.616029877215623855590, + 0.620240409751204424537, + 0.624433288012369303032, + 0.628608659422752680256, + 0.632766669570628437213, + 0.636907462236194987781, + 0.641031179420679109171, + 0.645137961373620782978, + 0.649227946625615004450, + 0.653301272011958644725, + 0.657358072709030238911, + 0.661398482245203922502, + 0.665422632544505177065, + 0.669430653942981734871, + 0.673422675212350441142, + 0.677398823590920073911, + 0.681359224807238206267, + 0.685304003098281100392, + 0.689233281238557538017, + 0.693147180560117703862); + + constant LOGF_TAIL: REAL_VECTOR(0 TO N) := ( + 0.0, + -0.00000000000000543229938420049, + 0.00000000000000172745674997061, + -0.00000000000001323017818229233, + -0.00000000000001154527628289872, + -0.00000000000000466529469958300, + 0.00000000000005148849572685810, + -0.00000000000002532168943117445, + -0.00000000000005213620639136504, + -0.00000000000001819506003016881, + 0.00000000000006329065958724544, + 0.00000000000008614512936087814, + -0.00000000000007355770219435028, + 0.00000000000009638067658552277, + 0.00000000000007598636597194141, + 0.00000000000002579999128306990, + -0.00000000000004654729747598444, + -0.00000000000007556920687451336, + 0.00000000000010195735223708472, + -0.00000000000017319034406422306, + -0.00000000000007718001336828098, + 0.00000000000010980754099855238, + -0.00000000000002047235780046195, + -0.00000000000008372091099235912, + 0.00000000000014088127937111135, + 0.00000000000012869017157588257, + 0.00000000000017788850778198106, + 0.00000000000006440856150696891, + 0.00000000000016132822667240822, + -0.00000000000007540916511956188, + -0.00000000000000036507188831790, + 0.00000000000009120937249914984, + 0.00000000000018567570959796010, + -0.00000000000003149265065191483, + -0.00000000000009309459495196889, + 0.00000000000017914338601329117, + -0.00000000000001302979717330866, + 0.00000000000023097385217586939, + 0.00000000000023999540484211737, + 0.00000000000015393776174455408, + -0.00000000000036870428315837678, + 0.00000000000036920375082080089, + -0.00000000000009383417223663699, + 0.00000000000009433398189512690, + 0.00000000000041481318704258568, + -0.00000000000003792316480209314, + 0.00000000000008403156304792424, + -0.00000000000034262934348285429, + 0.00000000000043712191957429145, + -0.00000000000010475750058776541, + -0.00000000000011118671389559323, + 0.00000000000037549577257259853, + 0.00000000000013912841212197565, + 0.00000000000010775743037572640, + 0.00000000000029391859187648000, + -0.00000000000042790509060060774, + 0.00000000000022774076114039555, + 0.00000000000010849569622967912, + -0.00000000000023073801945705758, + 0.00000000000015761203773969435, + 0.00000000000003345710269544082, + -0.00000000000041525158063436123, + 0.00000000000032655698896907146, + -0.00000000000044704265010452446, + 0.00000000000034527647952039772, + -0.00000000000007048962392109746, + 0.00000000000011776978751369214, + -0.00000000000010774341461609578, + 0.00000000000021863343293215910, + 0.00000000000024132639491333131, + 0.00000000000039057462209830700, + -0.00000000000026570679203560751, + 0.00000000000037135141919592021, + -0.00000000000017166921336082431, + -0.00000000000028658285157914353, + -0.00000000000023812542263446809, + 0.00000000000006576659768580062, + -0.00000000000028210143846181267, + 0.00000000000010701931762114254, + 0.00000000000018119346366441110, + 0.00000000000009840465278232627, + -0.00000000000033149150282752542, + -0.00000000000018302857356041668, + -0.00000000000016207400156744949, + 0.00000000000048303314949553201, + -0.00000000000071560553172382115, + 0.00000000000088821239518571855, + -0.00000000000030900580513238244, + -0.00000000000061076551972851496, + 0.00000000000035659969663347830, + 0.00000000000035782396591276383, + -0.00000000000046226087001544578, + 0.00000000000062279762917225156, + 0.00000000000072838947272065741, + 0.00000000000026809646615211673, + -0.00000000000010960825046059278, + 0.00000000000002311949383800537, + -0.00000000000058469058005299247, + -0.00000000000002103748251144494, + -0.00000000000023323182945587408, + -0.00000000000042333694288141916, + -0.00000000000043933937969737844, + 0.00000000000041341647073835565, + 0.00000000000006841763641591466, + 0.00000000000047585534004430641, + 0.00000000000083679678674757695, + -0.00000000000085763734646658640, + 0.00000000000021913281229340092, + -0.00000000000062242842536431148, + -0.00000000000010983594325438430, + 0.00000000000065310431377633651, + -0.00000000000047580199021710769, + -0.00000000000037854251265457040, + 0.00000000000040939233218678664, + 0.00000000000087424383914858291, + 0.00000000000025218188456842882, + -0.00000000000003608131360422557, + -0.00000000000050518555924280902, + 0.00000000000078699403323355317, + -0.00000000000067020876961949060, + 0.00000000000016108575753932458, + 0.00000000000058527188436251509, + -0.00000000000035246757297904791, + -0.00000000000018372084495629058, + 0.00000000000088606689813494916, + 0.00000000000066486268071468700, + 0.00000000000063831615170646519, + 0.00000000000025144230728376072, + -0.00000000000017239444525614834); + + variable M, J:INTEGER; + variable F1, F2, G, Q, U, U2, V: REAL; + variable ZERO: REAL := 0.0;--Made variable so no constant folding occurs + variable ONE: REAL := 1.0; --Made variable so no constant folding occurs + + -- double logb(), ldexp(); + + variable U1:REAL; + + begin + + -- Check validity of argument + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = MATH_E ) then + return 1.0; + end if; + + -- Argument reduction: 1 <= g < 2; x/2^m = g; + -- y = F*(1 + f/F) for |f| <= 2^-8 + + M := ILOGB(X); + G := LDEXP(X, -M); + J := INTEGER(REAL(N)*(G-1.0)); -- C code adds 0.5 for rounding + F1 := (1.0/REAL(N)) * REAL(J) + 1.0; --F1*128 is an INTEGER in [128,512] + F2 := G - F1; + + -- Approximate expansion for log(1+f2/F1) ~= u + q + G := 1.0/(2.0*F1+F2); + U := 2.0*F2*G; + V := U*U; + Q := U*V*(A1 + V*(A2 + V*(A3 + V*A4))); + + -- Case 1: u1 = u rounded to 2^-43 absolute. Since u < 2^-8, + -- u1 has at most 35 bits, and F1*u1 is exact, as F1 has < 8 bits. + -- It also adds exactly to |m*log2_hi + log_F_head[j] | < 750. + -- + if ( J /= 0 or M /= 0) then + U1 := U + 513.0; + U1 := U1 - 513.0; + + -- Case 2: |1-x| < 1/256. The m- and j- dependent terms are zero + -- u1 = u to 24 bits. + -- + else + U1 := U; + --TRUNC(U1); --In c this is u1 = (double) (float) (u1) + end if; + + U2 := (2.0*(F2 - F1*U1) - U1*F2) * G; + -- u1 + u2 = 2f/(2F+f) to extra precision. + + -- log(x) = log(2^m*F1*(1+f2/F1)) = + -- (m*log2_hi+LOGF_HEAD(j)+u1) + (m*log2_lo+LOGF_TAIL(j)+q); + -- (exact) + (tiny) + + U1 := U1 + REAL(M)*LOGF_HEAD(N) + LOGF_HEAD(J); -- Exact + U2 := (U2 + LOGF_TAIL(J)) + Q; -- Tiny + U2 := U2 + LOGF_TAIL(N)*REAL(M); + return (U1 + U2); + end LOG; + + + function LOG2 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG2(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 2.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG2_OF_E*LOG(X) ); + end LOG2; + + + function LOG10 (X: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG10(X)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = 10.0 ) then + return 1.0; + end if; + + -- Compute value for general case + return ( MATH_LOG10_OF_E*LOG(X) ); + end LOG10; + + + function LOG (X: in REAL; BASE: in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns REAL'LOW on error + begin + -- Check validity of arguments + if ( X <= 0.0 ) then + assert FALSE + report "X <= 0.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + if ( BASE <= 0.0 or BASE = 1.0 ) then + assert FALSE + report "BASE <= 0.0 or BASE = 1.0 in LOG(X, BASE)" + severity ERROR; + return(REAL'LOW); + end if; + + -- Compute value for special cases + if ( X = 1.0 ) then + return 0.0; + end if; + + if ( X = BASE ) then + return 1.0; + end if; + + -- Compute value for general case + return ( LOG(X)/LOG(BASE)); + end LOG; + + + function SIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) SIN(-X) = -SIN(X) + -- b) SIN(X) = X if ABS(X) < EPS + -- c) SIN(X) = X - X**3/3! if EPS < ABS(X) < BASE_EPS + -- d) SIN(MATH_PI_OVER_2 - X) = COS(X) + -- e) COS(X) = 1.0 - 0.5*X**2 if ABS(X) < EPS + -- f) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in SIN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI or XLOCAL = MATH_PI then + return 0.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 then + if NEGATIVE then + return -1.0; + else + return 1.0; + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + if NEGATIVE then + return 1.0; + else + return -1.0; + end if; + end if; + + if XLOCAL < EPS then + if NEGATIVE then + return -XLOCAL; + else + return XLOCAL; + end if; + else + if XLOCAL < BASE_EPS then + TEMP := XLOCAL - (XLOCAL*XLOCAL*XLOCAL)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := MATH_2_PI - XLOCAL; + if ABS(TEMP) < EPS then + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if ABS(TEMP) < BASE_EPS then + TEMP := TEMP - (TEMP*TEMP*TEMP)/6.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return -TEMP; + else + return TEMP; + end if; + end if; + end if; + + TEMP := ABS(MATH_3_PI_OVER_2 - XLOCAL); + if TEMP < EPS then + TEMP := 1.0 - TEMP*TEMP*0.5; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + else + if TEMP < BASE_EPS then + TEMP := 1.0 -TEMP*TEMP*0.5 + TEMP*TEMP*TEMP*TEMP/24.0; + if NEGATIVE then + return TEMP; + else + return -TEMP; + end if; + end if; + end if; + + -- Compute value for general cases + if ((XLOCAL < MATH_PI_OVER_2 ) and (XLOCAL > 0.0)) then + VALUE:= CORDIC( KC, 0.0, x, 27, ROTATION)(1); + end if; + + N := INTEGER ( FLOOR(XLOCAL/MATH_PI_OVER_2)); + case QUADRANT( N mod 4) is + when 0 => + VALUE := CORDIC( KC, 0.0, XLOCAL, 27, ROTATION)(1); + when 1 => + VALUE := CORDIC( KC, 0.0, XLOCAL - MATH_PI_OVER_2, 27, + ROTATION)(0); + when 2 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_PI, 27, ROTATION)(1); + when 3 => + VALUE := -CORDIC( KC, 0.0, XLOCAL - MATH_3_PI_OVER_2, 27, + ROTATION)(0); + end case; + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end SIN; + + + function COS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) COS(-X) = COS(X) + -- b) COS(X) = SIN(MATH_PI_OVER_2 - X) + -- c) COS(MATH_PI + X) = -COS(X) + -- d) COS(X) = 1.0 - X*X/2.0 if ABS(X) < EPS + -- e) COS(X) = 1.0 - 0.5*X**2 + (X**4)/4! if + -- EPS< ABS(X) MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in COS(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_2_PI then + return 1.0; + end if; + + if XLOCAL = MATH_PI then + return -1.0; + end if; + + if XLOCAL = MATH_PI_OVER_2 or XLOCAL = MATH_3_PI_OVER_2 then + return 0.0; + end if; + + TEMP := ABS(XLOCAL); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS(XLOCAL -MATH_2_PI); + if ( TEMP < EPS) then + return (1.0 - 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (1.0 -0.5*TEMP*TEMP + TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + TEMP := ABS (XLOCAL - MATH_PI); + if TEMP < EPS then + return (-1.0 + 0.5*TEMP*TEMP); + else + if (TEMP < BASE_EPS) then + return (-1.0 +0.5*TEMP*TEMP - TEMP*TEMP*TEMP*TEMP/24.0); + end if; + end if; + + -- Compute value for general cases + return SIN(MATH_PI_OVER_2 - XLOCAL); + end COS; + + function TAN (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) TAN(0.0) = 0.0 + -- b) TAN(-X) = -TAN(X) + -- c) Returns REAL'LOW on error if X < 0.0 + -- d) Returns REAL'HIGH on error if X > 0.0 + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X) ; + variable VALUE: REAL; + variable TEMP : REAL; + + begin + -- Make 0.0 <= XLOCAL <= MATH_2_PI + if XLOCAL > MATH_2_PI then + TEMP := FLOOR(XLOCAL/MATH_2_PI); + XLOCAL := XLOCAL - TEMP*MATH_2_PI; + end if; + + if XLOCAL < 0.0 then + assert FALSE + report "XLOCAL <= 0.0 after reduction in TAN(X)" + severity ERROR; + XLOCAL := -XLOCAL; + end if; + + -- Check validity of argument + if XLOCAL = MATH_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'LOW); + else + return(REAL'HIGH); + end if; + end if; + + if XLOCAL = MATH_3_PI_OVER_2 then + assert FALSE + report "X is a multiple of MATH_3_PI_OVER_2 in TAN(X)" + severity ERROR; + if NEGATIVE then + return(REAL'HIGH); + else + return(REAL'LOW); + end if; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 or XLOCAL = MATH_PI then + return 0.0; + end if; + + -- Compute value for general cases + VALUE := SIN(XLOCAL)/COS(XLOCAL); + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TAN; + + function ARCSIN (X : in REAL ) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCSIN(-X) = -ARCSIN(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of arguments + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCSIN(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + elsif XLOCAL = 1.0 then + if NEGATIVE then + return -MATH_PI_OVER_2; + else + return MATH_PI_OVER_2; + end if; + end if; + + -- Compute value for general cases + if XLOCAL < 0.9 then + VALUE := ARCTAN(XLOCAL/(SQRT(1.0 - XLOCAL*XLOCAL))); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCSIN; + + function ARCCOS (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCCOS(-X) = MATH_PI - ARCCOS(X) + -- b) Returns X on error + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable VALUE : REAL; + + begin + -- Check validity of argument + if XLOCAL > 1.0 then + assert FALSE + report "ABS(X) > 1.0 in ARCCOS(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + elsif X = 0.0 then + return MATH_PI_OVER_2; + elsif X = -1.0 then + return MATH_PI; + end if; + + -- Compute value for general cases + if XLOCAL > 0.9 then + VALUE := ARCTAN(SQRT(1.0 - XLOCAL*XLOCAL)/XLOCAL); + else + VALUE := MATH_PI_OVER_2 - ARCTAN(XLOCAL/SQRT(1.0 - XLOCAL*XLOCAL)); + end if; + + + if NEGATIVE then + VALUE := MATH_PI - VALUE; + end if; + + return VALUE; + end ARCCOS; + + + function ARCTAN (Y : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) ARCTAN(-Y) = -ARCTAN(Y) + -- b) ARCTAN(Y) = -ARCTAN(1.0/Y) + MATH_PI_OVER_2 for |Y| > 1.0 + -- c) ARCTAN(Y) = Y for |Y| < EPS + + constant EPS : REAL := BASE_EPS*BASE_EPS*BASE_EPS; + + variable NEGATIVE : BOOLEAN := Y < 0.0; + variable RECIPROCAL : BOOLEAN; + variable YLOCAL : REAL := ABS(Y); + variable VALUE : REAL; + + begin + -- Make argument |Y| <=1.0 + if YLOCAL > 1.0 then + YLOCAL := 1.0/YLOCAL; + RECIPROCAL := TRUE; + else + RECIPROCAL := FALSE; + end if; + + -- Compute value for special cases + if YLOCAL = 0.0 then + if RECIPROCAL then + if NEGATIVE then + return (-MATH_PI_OVER_2); + else + return (MATH_PI_OVER_2); + end if; + else + return 0.0; + end if; + end if; + + if YLOCAL < EPS then + if NEGATIVE then + if RECIPROCAL then + return (-MATH_PI_OVER_2 + YLOCAL); + else + return -YLOCAL; + end if; + else + if RECIPROCAL then + return (MATH_PI_OVER_2 - YLOCAL); + else + return YLOCAL; + end if; + end if; + end if; + + -- Compute value for general cases + VALUE := CORDIC( 1.0, YLOCAL, 0.0, 27, VECTORING )(2); + + if RECIPROCAL then + VALUE := MATH_PI_OVER_2 - VALUE; + end if; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function ARCTAN (Y : in REAL; X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns 0.0 on error + + variable YLOCAL : REAL; + variable VALUE : REAL; + begin + + -- Check validity of arguments + if (Y = 0.0 and X = 0.0 ) then + assert FALSE report + "ARCTAN(0.0, 0.0) is undetermined" + severity ERROR; + return 0.0; + end if; + + -- Compute value for special cases + if Y = 0.0 then + if X > 0.0 then + return 0.0; + else + return MATH_PI; + end if; + end if; + + if X = 0.0 then + if Y > 0.0 then + return MATH_PI_OVER_2; + else + return -MATH_PI_OVER_2; + end if; + end if; + + + -- Compute value for general cases + YLOCAL := ABS(Y/X); + + VALUE := ARCTAN(YLOCAL); + + if X < 0.0 then + VALUE := MATH_PI - VALUE; + end if; + + if Y < 0.0 then + VALUE := -VALUE; + end if; + + return VALUE; + end ARCTAN; + + + function SINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/2.0 + -- b) SINH(-X) = SINH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)*0.5; + + if NEGATIVE then + VALUE := -VALUE; + end if; + + return VALUE; + end SINH; + + function COSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) + EXP(-X))/2.0 + -- b) COSH(-X) = COSH(X) + + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 1.0; + end if; + + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP + 1.0/TEMP)*0.5; + + return VALUE; + end COSH; + + function TANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (EXP(X) - EXP(-X))/(EXP(X) + EXP(-X)) + -- b) TANH(-X) = -TANH(X) + + variable NEGATIVE : BOOLEAN := X < 0.0; + variable XLOCAL : REAL := ABS(X); + variable TEMP : REAL; + variable VALUE : REAL; + + begin + -- Compute value for special cases + if XLOCAL = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + TEMP := EXP(XLOCAL); + VALUE := (TEMP - 1.0/TEMP)/(TEMP + 1.0/TEMP); + + if NEGATIVE then + return -VALUE; + else + return VALUE; + end if; + end TANH; + + function ARCSINH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X + 1.0)) + + begin + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X + 1.0)) ); + end ARCSINH; + + + + function ARCCOSH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns LOG( X + SQRT( X*X - 1.0)); X >= 1.0 + -- b) Returns X on error + + begin + -- Check validity of arguments + if X < 1.0 then + assert FALSE + report "X < 1.0 in ARCCOSH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 1.0 then + return 0.0; + end if; + + -- Compute value for general cases + return ( LOG( X + SQRT( X*X - 1.0))); + end ARCCOSH; + + function ARCTANH (X : in REAL) return REAL is + -- Description: + -- See function declaration in IEEE Std 1076.2-1996 + -- Notes: + -- a) Returns (LOG( (1.0 + X)/(1.0 - X)))/2.0 ; | X | < 1.0 + -- b) Returns X on error + begin + -- Check validity of arguments + if ABS(X) >= 1.0 then + assert FALSE + report "ABS(X) >= 1.0 in ARCTANH(X)" + severity ERROR; + return X; + end if; + + -- Compute value for special cases + if X = 0.0 then + return 0.0; + end if; + + -- Compute value for general cases + return( 0.5*LOG( (1.0+X)/(1.0-X) ) ); + end ARCTANH; + +end MATH_REAL; diff --git a/CPLD/LCMXO2-640HC/generate_core.tcl b/CPLD/LCMXO2-640HC/generate_core.tcl new file mode 100644 index 0000000..47f429b --- /dev/null +++ b/CPLD/LCMXO2-640HC/generate_core.tcl @@ -0,0 +1,100 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +proc GetCmdLine {lpcfile} { + global Para + + if [catch {open $lpcfile r} fileid] { + puts "Cannot open $para_file file!" + exit -1 + } + + seek $fileid 0 start + set default_match 0 + while {[gets $fileid line] >= 0} { + if {[string first "\[Command\]" $line] == 0} { + set default_match 1 + continue + } + if {[string first "\[" $line] == 0} { + set default_match 0 + } + if {$default_match == 1} { + if [regexp {([^=]*)=(.*)} $line match parameter value] { + if [regexp {([ |\t]*;)} $parameter match] {continue} + if [regexp {(.*)[ |\t]*;} $value match temp] { + set Para($parameter) $temp + } else { + set Para($parameter) $value + } + } + } + } + set default_match 0 + close $fileid + + return $Para(cmd_line) +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" + +set scuba "$Para(FPGAPath)/scuba" +set modulename "REFB" +set lang "verilog" +set lpcfile "$Para(sbp_path)/$modulename.lpc" +set arch "xo2c00" +set cmd_line [GetCmdLine $lpcfile] +set fdcfile "$Para(sbp_path)/$modulename.fdc" +if {[file exists $fdcfile] == 0} { + append scuba " " $cmd_line +} else { + append scuba " " $cmd_line " " -fdc " " \"$fdcfile\" +} +set Para(result) [catch {eval exec "$scuba"} msg] +#puts $msg diff --git a/CPLD/LCMXO2-640HC/generate_ngd.tcl b/CPLD/LCMXO2-640HC/generate_ngd.tcl new file mode 100644 index 0000000..d6ce2af --- /dev/null +++ b/CPLD/LCMXO2-640HC/generate_ngd.tcl @@ -0,0 +1,74 @@ +#!/usr/local/bin/wish + +proc GetPlatform {} { + global tcl_platform + + set cpu $tcl_platform(machine) + + switch $cpu { + intel - + i*86* { + set cpu ix86 + } + x86_64 { + if {$tcl_platform(wordSize) == 4} { + set cpu ix86 + } + } + } + + switch $tcl_platform(platform) { + windows { + if {$cpu == "amd64"} { + # Do not check wordSize, win32-x64 is an IL32P64 platform. + set cpu x86_64 + } + if {$cpu == "x86_64"} { + return "nt64" + } else { + return "nt" + } + } + unix { + if {$tcl_platform(os) == "Linux"} { + if {$cpu == "x86_64"} { + return "lin64" + } else { + return "lin" + } + } else { + return "sol" + } + } + } + return "nt" +} + +set platformpath [GetPlatform] +set Para(sbp_path) [file dirname [info script]] +set Para(install_dir) $env(TOOLRTF) +set Para(FPGAPath) "[file join $Para(install_dir) ispfpga bin $platformpath]" +set Para(bin_dir) "[file join $Para(install_dir) bin $platformpath]" + +set Para(ModuleName) "REFB" +set Para(Module) "EFB" +set Para(libname) machxo2 +set Para(arch_name) xo2c00 +set Para(PartType) "LCMXO2-640HC" + +set Para(tech_syn) machxo2 +set Para(tech_cae) machxo2 +set Para(Package) "TQFP100" +set Para(SpeedGrade) "4" +set Para(FMax) "100" +set fdcfile "$Para(sbp_path)/$Para(ModuleName).fdc" + +#edif2ngd +set edif2ngd "$Para(FPGAPath)/edif2ngd" +set Para(result) [catch {eval exec $edif2ngd -l $Para(libname) -d $Para(PartType) -nopropwarn $Para(ModuleName).edn $Para(ModuleName).ngo} msg] +#puts $msg + +#ngdbuild +set ngdbuild "$Para(FPGAPath)/ngdbuild" +set Para(result) [catch {eval exec $ngdbuild -addiobuf -dt -a $Para(arch_name) $Para(ModuleName).ngo $Para(ModuleName).ngd} msg] +#puts $msg diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt new file mode 100644 index 0000000..feef941 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.alt @@ -0,0 +1,78 @@ +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation * +NOTE All Rights Reserved * +NOTE DATE CREATED: Thu Sep 21 05:35:24 2023 * +NOTE DESIGN NAME: RAM2E * +NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100 * +NOTE PIN ASSIGNMENTS * +NOTE PINS RD[0] : 36 : inout * +NOTE PINS LED : 35 : out * +NOTE PINS C14M : 62 : in * +NOTE PINS DQMH : 49 : out * +NOTE PINS DQML : 48 : out * +NOTE PINS RD[7] : 43 : inout * +NOTE PINS RD[6] : 42 : inout * +NOTE PINS RD[5] : 41 : inout * +NOTE PINS RD[4] : 40 : inout * +NOTE PINS RD[3] : 39 : inout * +NOTE PINS RD[2] : 38 : inout * +NOTE PINS RD[1] : 37 : inout * +NOTE PINS RA[11] : 59 : out * +NOTE PINS RA[10] : 64 : out * +NOTE PINS RA[9] : 63 : out * +NOTE PINS RA[8] : 65 : out * +NOTE PINS RA[7] : 67 : out * +NOTE PINS RA[6] : 69 : out * +NOTE PINS RA[5] : 71 : out * +NOTE PINS RA[4] : 75 : out * +NOTE PINS RA[3] : 74 : out * +NOTE PINS RA[2] : 70 : out * +NOTE PINS RA[1] : 68 : out * +NOTE PINS RA[0] : 66 : out * +NOTE PINS BA[1] : 60 : out * +NOTE PINS BA[0] : 58 : out * +NOTE PINS nRWE : 51 : out * +NOTE PINS nCAS : 52 : out * +NOTE PINS nRAS : 54 : out * +NOTE PINS nCS : 57 : out * +NOTE PINS CKE : 53 : out * +NOTE PINS nVOE : 10 : out * +NOTE PINS Vout[7] : 12 : out * +NOTE PINS Vout[6] : 14 : out * +NOTE PINS Vout[5] : 16 : out * +NOTE PINS Vout[4] : 19 : out * +NOTE PINS Vout[3] : 13 : out * +NOTE PINS Vout[2] : 17 : out * +NOTE PINS Vout[1] : 15 : out * +NOTE PINS Vout[0] : 18 : out * +NOTE PINS nDOE : 20 : out * +NOTE PINS Dout[7] : 32 : out * +NOTE PINS Dout[6] : 31 : out * +NOTE PINS Dout[5] : 21 : out * +NOTE PINS Dout[4] : 24 : out * +NOTE PINS Dout[3] : 28 : out * +NOTE PINS Dout[2] : 25 : out * +NOTE PINS Dout[1] : 27 : out * +NOTE PINS Dout[0] : 30 : out * +NOTE PINS Din[7] : 87 : in * +NOTE PINS Din[6] : 88 : in * +NOTE PINS Din[5] : 99 : in * +NOTE PINS Din[4] : 1 : in * +NOTE PINS Din[3] : 9 : in * +NOTE PINS Din[2] : 98 : in * +NOTE PINS Din[1] : 97 : in * +NOTE PINS Din[0] : 96 : in * +NOTE PINS Ain[7] : 8 : in * +NOTE PINS Ain[6] : 86 : in * +NOTE PINS Ain[5] : 84 : in * +NOTE PINS Ain[4] : 78 : in * +NOTE PINS Ain[3] : 4 : in * +NOTE PINS Ain[2] : 7 : in * +NOTE PINS Ain[1] : 2 : in * +NOTE PINS Ain[0] : 3 : in * +NOTE PINS nC07X : 34 : in * +NOTE PINS nEN80 : 82 : in * +NOTE PINS nWE80 : 83 : in * +NOTE PINS nWE : 29 : in * +NOTE PINS PHI1 : 85 : in * +NOTE CONFIGURATION MODE: NONE * +NOTE COMPRESSION: on * diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.areasrr b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.areasrr new file mode 100644 index 0000000..9749d2a --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.areasrr @@ -0,0 +1,41 @@ +---------------------------------------------------------------------- +Report for cell RAM2E.verilog + +Register bits: 111 of 640 (17%) +PIC Latch: 0 +I/O cells: 70 + Cell usage: + cell count Res Usage(%) + BB 8 100.0 + CCU2D 9 100.0 + EFB 1 100.0 + FD1P3AX 48 100.0 + FD1P3IX 1 100.0 + FD1S3AX 22 100.0 + FD1S3IX 4 100.0 + GSR 1 100.0 + IB 22 100.0 + IFS1P3DX 1 100.0 + INV 1 100.0 + OB 40 100.0 + OFS1P3BX 6 100.0 + OFS1P3DX 27 100.0 + OFS1P3IX 2 100.0 + ORCALUT4 221 100.0 + PUR 1 100.0 + VHI 2 100.0 + VLO 2 100.0 +SUB MODULES + REFB 1 100.0 + + TOTAL 420 +---------------------------------------------------------------------- +Report for cell REFB.netlist + Instance path: ufmefb + Cell usage: + cell count Res Usage(%) + EFB 1 100.0 + VHI 1 50.0 + VLO 1 50.0 + + TOTAL 3 diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn new file mode 100644 index 0000000..0abdd18 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.bgn @@ -0,0 +1,86 @@ +BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454 +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Thu Sep 21 05:35:20 2023 + + +Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -jedec -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf + +Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd. +Design name: RAM2E +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Reading Preference File from RAM2E_LCMXO2_640HC_impl1.prf. + +Preference Summary: ++---------------------------------+---------------------------------+ +| Preference | Current Setting | ++---------------------------------+---------------------------------+ +| RamCfg | Reset** | ++---------------------------------+---------------------------------+ +| MCCLK_FREQ | 2.08** | ++---------------------------------+---------------------------------+ +| CONFIG_SECURE | OFF** | ++---------------------------------+---------------------------------+ +| INBUF | ON** | ++---------------------------------+---------------------------------+ +| JTAG_PORT | ENABLE** | ++---------------------------------+---------------------------------+ +| SDM_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| SLAVE_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MASTER_SPI_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| I2C_PORT | DISABLE** | ++---------------------------------+---------------------------------+ +| MUX_CONFIGURATION_PORTS | DISABLE** | ++---------------------------------+---------------------------------+ +| CONFIGURATION | CFG** | ++---------------------------------+---------------------------------+ +| COMPRESS_CONFIG | ON** | ++---------------------------------+---------------------------------+ +| MY_ASSP | OFF** | ++---------------------------------+---------------------------------+ +| ONE_TIME_PROGRAM | OFF** | ++---------------------------------+---------------------------------+ +| ENABLE_TRANSFR | DISABLE** | ++---------------------------------+---------------------------------+ +| SHAREDEBRINIT | DISABLE** | ++---------------------------------+---------------------------------+ +| BACKGROUND_RECONFIG | OFF** | ++---------------------------------+---------------------------------+ + * Default setting. + ** The specified setting matches the default setting. + + +Creating bit map... + +Bitstream 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(timeStamp 2023 9 21 5 34 43) + (author "Synopsys, Inc.") + (program "Synplify Pro" (version "R-2021.03L-SP1, mapper map202103lat, Build 070R")) + ) + ) + (library LUCENT + (edifLevel 0) + (technology (numberDefinition )) + (cell CCU2D (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A0 (direction INPUT)) + (port B0 (direction INPUT)) + (port C0 (direction INPUT)) + (port D0 (direction INPUT)) + (port A1 (direction INPUT)) + (port B1 (direction INPUT)) + (port C1 (direction INPUT)) + (port D1 (direction INPUT)) + (port CIN (direction INPUT)) + (port COUT (direction OUTPUT)) + (port S0 (direction OUTPUT)) + (port S1 (direction OUTPUT)) + ) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0000")) + (property INIT0 (string "0000")) + ) + ) + (cell BB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port B (direction INOUT)) + (port I (direction INPUT)) + (port T (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell OB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell IB (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port I (direction INPUT)) + (port O (direction OUTPUT)) + ) + ) + ) + (cell FD1S3IX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1S3AX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1P3IX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port CK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3IX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3DX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell IFS1P3DX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port CD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell OFS1P3BX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port SCLK (direction INPUT)) + (port PD (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell FD1P3AX (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port D (direction INPUT)) + (port SP (direction INPUT)) + (port CK (direction INPUT)) + (port Q (direction OUTPUT)) + ) + ) + ) + (cell ORCALUT4 (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port B (direction INPUT)) + (port C (direction INPUT)) + (port D (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell GSR (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port GSR (direction INPUT)) + ) + ) + ) + (cell INV (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port A (direction INPUT)) + (port Z (direction OUTPUT)) + ) + ) + ) + (cell VHI (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + (cell VLO (cellType GENERIC) + (view PRIM (viewType NETLIST) + (interface + (port Z (direction OUTPUT)) + ) + ) + ) + ) + (library work + (edifLevel 0) + (technology (numberDefinition )) + (cell EFB (cellType GENERIC) + (view verilog (viewType NETLIST) + (interface + (port WBCLKI (direction INPUT)) + (port WBRSTI (direction INPUT)) + (port WBCYCI (direction INPUT)) + (port WBSTBI (direction INPUT)) + (port WBWEI (direction INPUT)) + (port WBADRI7 (direction INPUT)) + (port WBADRI6 (direction INPUT)) + (port WBADRI5 (direction INPUT)) + (port WBADRI4 (direction INPUT)) + (port WBADRI3 (direction INPUT)) + (port WBADRI2 (direction INPUT)) + (port WBADRI1 (direction INPUT)) + (port WBADRI0 (direction INPUT)) + (port WBDATI7 (direction INPUT)) + (port WBDATI6 (direction INPUT)) + (port WBDATI5 (direction INPUT)) + (port WBDATI4 (direction INPUT)) + (port WBDATI3 (direction INPUT)) + (port WBDATI2 (direction INPUT)) + (port WBDATI1 (direction INPUT)) + (port WBDATI0 (direction INPUT)) + (port PLL0DATI7 (direction INPUT)) + (port PLL0DATI6 (direction INPUT)) + (port PLL0DATI5 (direction INPUT)) + (port PLL0DATI4 (direction INPUT)) + (port PLL0DATI3 (direction INPUT)) + (port PLL0DATI2 (direction INPUT)) + (port PLL0DATI1 (direction INPUT)) + (port PLL0DATI0 (direction INPUT)) + (port PLL0ACKI (direction INPUT)) + (port PLL1DATI7 (direction INPUT)) + (port PLL1DATI6 (direction INPUT)) + (port PLL1DATI5 (direction INPUT)) + (port PLL1DATI4 (direction INPUT)) + (port PLL1DATI3 (direction INPUT)) + (port PLL1DATI2 (direction INPUT)) + (port PLL1DATI1 (direction INPUT)) + (port PLL1DATI0 (direction INPUT)) + (port PLL1ACKI (direction INPUT)) + (port I2C1SCLI (direction INPUT)) + (port I2C1SDAI (direction INPUT)) + (port I2C2SCLI (direction INPUT)) + (port I2C2SDAI (direction INPUT)) + (port SPISCKI (direction INPUT)) + (port SPIMISOI (direction INPUT)) + (port SPIMOSII (direction INPUT)) + (port SPISCSN (direction INPUT)) + (port TCCLKI (direction INPUT)) + (port TCRSTN (direction INPUT)) + (port TCIC (direction INPUT)) + (port UFMSN (direction INPUT)) + (port WBDATO7 (direction OUTPUT)) + (port WBDATO6 (direction OUTPUT)) + (port WBDATO5 (direction OUTPUT)) + (port WBDATO4 (direction OUTPUT)) + (port WBDATO3 (direction OUTPUT)) + (port WBDATO2 (direction OUTPUT)) + (port WBDATO1 (direction OUTPUT)) + (port WBDATO0 (direction OUTPUT)) + (port WBACKO (direction OUTPUT)) + (port PLLCLKO (direction OUTPUT)) + (port PLLRSTO (direction OUTPUT)) + (port PLL0STBO (direction OUTPUT)) + (port PLL1STBO (direction OUTPUT)) + (port PLLWEO (direction OUTPUT)) + (port PLLADRO4 (direction OUTPUT)) + (port PLLADRO3 (direction OUTPUT)) + (port PLLADRO2 (direction OUTPUT)) + (port PLLADRO1 (direction OUTPUT)) + (port PLLADRO0 (direction OUTPUT)) + (port PLLDATO7 (direction OUTPUT)) + (port PLLDATO6 (direction OUTPUT)) + (port PLLDATO5 (direction OUTPUT)) + (port PLLDATO4 (direction OUTPUT)) + (port PLLDATO3 (direction OUTPUT)) + (port PLLDATO2 (direction OUTPUT)) + (port PLLDATO1 (direction OUTPUT)) + (port PLLDATO0 (direction OUTPUT)) + (port I2C1SCLO (direction OUTPUT)) + (port I2C1SCLOEN (direction OUTPUT)) + (port I2C1SDAO (direction OUTPUT)) + (port I2C1SDAOEN (direction OUTPUT)) + (port I2C2SCLO (direction OUTPUT)) + (port I2C2SCLOEN (direction OUTPUT)) + (port I2C2SDAO (direction OUTPUT)) + (port I2C2SDAOEN (direction OUTPUT)) + (port I2C1IRQO (direction OUTPUT)) + (port I2C2IRQO (direction OUTPUT)) + (port SPISCKO (direction OUTPUT)) + (port SPISCKEN (direction OUTPUT)) + (port SPIMISOO (direction OUTPUT)) + (port SPIMISOEN (direction OUTPUT)) + (port SPIMOSIO (direction OUTPUT)) + (port SPIMOSIEN (direction OUTPUT)) + (port SPIMCSN0 (direction OUTPUT)) + (port SPIMCSN1 (direction OUTPUT)) + (port SPIMCSN2 (direction OUTPUT)) + (port SPIMCSN3 (direction OUTPUT)) + (port SPIMCSN4 (direction OUTPUT)) + (port SPIMCSN5 (direction OUTPUT)) + (port SPIMCSN6 (direction OUTPUT)) + (port SPIMCSN7 (direction OUTPUT)) + (port SPICSNEN (direction OUTPUT)) + (port SPIIRQO (direction OUTPUT)) + (port TCINT (direction OUTPUT)) + (port TCOC (direction OUTPUT)) + (port WBCUFMIRQ (direction OUTPUT)) + (port CFGWAKE (direction OUTPUT)) + (port CFGSTDBY (direction OUTPUT)) + ) + (property TC_ICAPTURE (string "DISABLED")) + (property TC_OVERFLOW (string "DISABLED")) + (property TC_ICR_INT (string "OFF")) + (property TC_OCR_INT (string "OFF")) + (property TC_OV_INT (string "OFF")) + (property TC_TOP_SEL (string "OFF")) + (property TC_RESETN (string "ENABLED")) + (property TC_OC_MODE (string "TOGGLE")) + (property TC_OCR_SET (integer 32767)) + (property TC_TOP_SET (integer 65535)) + (property GSR (string "ENABLED")) + (property TC_CCLK_SEL (integer 1)) + (property TC_SCLK_SEL (string "PCLOCK")) + (property TC_MODE (string "CTCM")) + (property SPI_WAKEUP (string "DISABLED")) + (property SPI_INTR_RXOVR (string "DISABLED")) + (property SPI_INTR_TXOVR (string "DISABLED")) + (property SPI_INTR_RXRDY (string "DISABLED")) + (property SPI_INTR_TXRDY (string "DISABLED")) + (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) + (property SPI_PHASE_ADJ (string "DISABLED")) + (property SPI_CLK_INV (string "DISABLED")) + (property SPI_LSB_FIRST (string "DISABLED")) + (property SPI_CLK_DIVIDER (integer 1)) + (property SPI_MODE (string "MASTER")) + (property I2C2_WAKEUP (string "DISABLED")) + (property I2C1_WAKEUP (string "DISABLED")) + (property I2C2_GEN_CALL (string "DISABLED")) + (property I2C1_GEN_CALL (string "DISABLED")) + (property I2C2_CLK_DIVIDER (integer 1)) + (property I2C1_CLK_DIVIDER (integer 1)) + (property I2C2_BUS_PERF (string "100kHz")) + (property I2C1_BUS_PERF (string "100kHz")) + (property I2C2_SLAVE_ADDR (string "0b1000010")) + (property I2C1_SLAVE_ADDR (string "0b1000001")) + (property I2C2_ADDRESSING (string "7BIT")) + (property I2C1_ADDRESSING (string "7BIT")) + (property UFM_INIT_FILE_FORMAT (string "HEX")) + (property UFM_INIT_FILE_NAME (string "../RAM2E-LCMXO2.mem")) + (property UFM_INIT_ALL_ZEROS (string "DISABLED")) + (property UFM_INIT_START_PAGE (integer 190)) + (property UFM_INIT_PAGES (integer 1)) + (property DEV_DENSITY (string "640L")) + (property EFB_WB_CLK_FREQ (string "14.4")) + (property EFB_UFM (string "ENABLED")) + (property EFB_TC_PORTMODE (string "WB")) + (property EFB_TC (string "DISABLED")) + (property EFB_SPI (string "DISABLED")) + (property EFB_I2C2 (string "DISABLED")) + (property EFB_I2C1 (string "DISABLED")) + (property orig_inst_of (string "EFB")) + ) + ) + (cell REFB (cellType GENERIC) + (view netlist (viewType NETLIST) + (interface + (port (array (rename wb_dato "wb_dato[7:0]") 8) (direction OUTPUT)) + (port (array (rename wb_dati "wb_dati[7:0]") 8) (direction INPUT)) + (port (array (rename wb_adr "wb_adr[7:0]") 8) (direction INPUT)) + (port wb_ack (direction OUTPUT)) + (port wb_we (direction INPUT)) + (port wb_cyc_stb (direction INPUT)) + (port wb_rst (direction INPUT)) + (port C14M_c (direction INPUT)) + ) + (contents + (instance EFBInst_0 (viewRef verilog (cellRef EFB)) + (property UFM_INIT_FILE_FORMAT (string "HEX")) + (property UFM_INIT_FILE_NAME (string "../RAM2E-LCMXO2.mem")) + (property UFM_INIT_ALL_ZEROS (string "DISABLED")) + (property UFM_INIT_START_PAGE (integer 190)) + (property UFM_INIT_PAGES (integer 1)) + (property DEV_DENSITY (string "640L")) + (property EFB_UFM (string "ENABLED")) + (property TC_ICAPTURE (string "DISABLED")) + (property TC_OVERFLOW (string "DISABLED")) + (property TC_ICR_INT (string "OFF")) + (property TC_OCR_INT (string "OFF")) + (property TC_OV_INT (string "OFF")) + (property TC_TOP_SEL (string "OFF")) + (property TC_RESETN (string "ENABLED")) + (property TC_OC_MODE (string "TOGGLE")) + (property TC_OCR_SET (integer 32767)) + (property TC_TOP_SET (integer 65535)) + (property GSR (string "ENABLED")) + (property TC_CCLK_SEL (integer 1)) + (property TC_MODE (string "CTCM")) + (property TC_SCLK_SEL (string "PCLOCK")) + (property EFB_TC_PORTMODE (string "WB")) + (property EFB_TC (string "DISABLED")) + (property SPI_WAKEUP (string "DISABLED")) + (property SPI_INTR_RXOVR (string "DISABLED")) + (property SPI_INTR_TXOVR (string "DISABLED")) + (property SPI_INTR_RXRDY (string "DISABLED")) + (property SPI_INTR_TXRDY (string "DISABLED")) + (property SPI_SLAVE_HANDSHAKE (string "DISABLED")) + (property SPI_PHASE_ADJ (string "DISABLED")) + (property SPI_CLK_INV (string "DISABLED")) + (property SPI_LSB_FIRST (string "DISABLED")) + (property SPI_CLK_DIVIDER (integer 1)) + (property SPI_MODE (string "MASTER")) + (property EFB_SPI (string "DISABLED")) + (property I2C2_WAKEUP (string "DISABLED")) + (property I2C2_GEN_CALL (string "DISABLED")) + (property I2C2_CLK_DIVIDER (integer 1)) + (property I2C2_BUS_PERF (string "100kHz")) + (property I2C2_SLAVE_ADDR (string "0b1000010")) + (property I2C2_ADDRESSING (string "7BIT")) + (property EFB_I2C2 (string "DISABLED")) + (property I2C1_WAKEUP (string "DISABLED")) + (property I2C1_GEN_CALL (string "DISABLED")) + (property I2C1_CLK_DIVIDER (integer 1)) + (property I2C1_BUS_PERF (string "100kHz")) + (property I2C1_SLAVE_ADDR (string "0b1000001")) + (property I2C1_ADDRESSING (string "7BIT")) + (property EFB_I2C1 (string "DISABLED")) + (property EFB_WB_CLK_FREQ (string "14.4")) + ) + (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) + (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) + (net C14M_c (joined + (portRef C14M_c) + (portRef WBCLKI (instanceRef EFBInst_0)) + )) + (net wb_rst (joined + (portRef wb_rst) + (portRef WBRSTI (instanceRef EFBInst_0)) + )) + (net wb_cyc_stb (joined + (portRef wb_cyc_stb) + (portRef WBSTBI (instanceRef EFBInst_0)) + (portRef WBCYCI (instanceRef EFBInst_0)) + )) + (net wb_we (joined + (portRef wb_we) + (portRef WBWEI (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_7 "wb_adr[7]") (joined + (portRef (member wb_adr 0)) + (portRef WBADRI7 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_6 "wb_adr[6]") (joined + (portRef (member wb_adr 1)) + (portRef WBADRI6 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_5 "wb_adr[5]") (joined + (portRef (member wb_adr 2)) + (portRef WBADRI5 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_4 "wb_adr[4]") (joined + (portRef (member wb_adr 3)) + (portRef WBADRI4 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_3 "wb_adr[3]") (joined + (portRef (member wb_adr 4)) + (portRef WBADRI3 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_2 "wb_adr[2]") (joined + (portRef (member wb_adr 5)) + (portRef WBADRI2 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_1 "wb_adr[1]") (joined + (portRef (member wb_adr 6)) + (portRef WBADRI1 (instanceRef EFBInst_0)) + )) + (net (rename wb_adr_0 "wb_adr[0]") (joined + (portRef (member wb_adr 7)) + (portRef WBADRI0 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_7 "wb_dati[7]") (joined + (portRef (member wb_dati 0)) + (portRef WBDATI7 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_6 "wb_dati[6]") (joined + (portRef (member wb_dati 1)) + (portRef WBDATI6 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_5 "wb_dati[5]") (joined + (portRef (member wb_dati 2)) + (portRef WBDATI5 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_4 "wb_dati[4]") (joined + (portRef (member wb_dati 3)) + (portRef WBDATI4 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_3 "wb_dati[3]") (joined + (portRef (member wb_dati 4)) + (portRef WBDATI3 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_2 "wb_dati[2]") (joined + (portRef (member wb_dati 5)) + (portRef WBDATI2 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_1 "wb_dati[1]") (joined + (portRef (member wb_dati 6)) + (portRef WBDATI1 (instanceRef EFBInst_0)) + )) + (net (rename wb_dati_0 "wb_dati[0]") (joined + (portRef (member wb_dati 7)) + (portRef WBDATI0 (instanceRef EFBInst_0)) + )) + (net GND (joined + (portRef Z (instanceRef GND)) + (portRef TCIC (instanceRef EFBInst_0)) + (portRef TCRSTN (instanceRef EFBInst_0)) + (portRef TCCLKI (instanceRef EFBInst_0)) + (portRef SPISCSN (instanceRef EFBInst_0)) + (portRef SPIMOSII (instanceRef EFBInst_0)) + (portRef SPIMISOI (instanceRef EFBInst_0)) + (portRef SPISCKI (instanceRef EFBInst_0)) + (portRef I2C2SDAI (instanceRef EFBInst_0)) + (portRef I2C2SCLI (instanceRef EFBInst_0)) + (portRef I2C1SDAI (instanceRef EFBInst_0)) + (portRef I2C1SCLI (instanceRef EFBInst_0)) + (portRef PLL1ACKI (instanceRef EFBInst_0)) + (portRef PLL1DATI0 (instanceRef EFBInst_0)) + (portRef PLL1DATI1 (instanceRef EFBInst_0)) + (portRef PLL1DATI2 (instanceRef EFBInst_0)) + (portRef PLL1DATI3 (instanceRef EFBInst_0)) + (portRef PLL1DATI4 (instanceRef EFBInst_0)) + (portRef PLL1DATI5 (instanceRef EFBInst_0)) + (portRef PLL1DATI6 (instanceRef EFBInst_0)) + (portRef PLL1DATI7 (instanceRef EFBInst_0)) + (portRef PLL0ACKI (instanceRef EFBInst_0)) + (portRef PLL0DATI0 (instanceRef EFBInst_0)) + (portRef PLL0DATI1 (instanceRef EFBInst_0)) + (portRef PLL0DATI2 (instanceRef EFBInst_0)) + (portRef PLL0DATI3 (instanceRef EFBInst_0)) + (portRef PLL0DATI4 (instanceRef EFBInst_0)) + (portRef PLL0DATI5 (instanceRef EFBInst_0)) + (portRef PLL0DATI6 (instanceRef EFBInst_0)) + (portRef PLL0DATI7 (instanceRef EFBInst_0)) + )) + (net VCC (joined + (portRef Z (instanceRef VCC)) + (portRef UFMSN (instanceRef EFBInst_0)) + )) + (net (rename wb_dato_7 "wb_dato[7]") (joined + (portRef WBDATO7 (instanceRef EFBInst_0)) + (portRef (member wb_dato 0)) + )) + (net (rename wb_dato_6 "wb_dato[6]") (joined + (portRef WBDATO6 (instanceRef EFBInst_0)) + (portRef (member wb_dato 1)) + )) + (net (rename wb_dato_5 "wb_dato[5]") (joined + (portRef WBDATO5 (instanceRef EFBInst_0)) + (portRef (member wb_dato 2)) + )) + (net (rename wb_dato_4 "wb_dato[4]") (joined + (portRef WBDATO4 (instanceRef EFBInst_0)) + (portRef (member wb_dato 3)) + )) + (net (rename wb_dato_3 "wb_dato[3]") (joined + (portRef WBDATO3 (instanceRef EFBInst_0)) + (portRef (member wb_dato 4)) + )) + (net (rename wb_dato_2 "wb_dato[2]") (joined + (portRef WBDATO2 (instanceRef EFBInst_0)) + (portRef (member wb_dato 5)) + )) + (net (rename wb_dato_1 "wb_dato[1]") (joined + (portRef WBDATO1 (instanceRef EFBInst_0)) + (portRef (member wb_dato 6)) + )) + (net (rename wb_dato_0 "wb_dato[0]") (joined + (portRef WBDATO0 (instanceRef EFBInst_0)) + (portRef (member wb_dato 7)) + )) + (net wb_ack (joined + (portRef WBACKO (instanceRef EFBInst_0)) + (portRef wb_ack) + )) + (net PLLCLKO (joined + (portRef PLLCLKO (instanceRef EFBInst_0)) + )) + (net PLLRSTO (joined + (portRef PLLRSTO (instanceRef EFBInst_0)) + )) + (net PLL0STBO (joined + (portRef PLL0STBO (instanceRef EFBInst_0)) + )) + (net PLL1STBO (joined + (portRef PLL1STBO (instanceRef EFBInst_0)) + )) + (net PLLWEO (joined + (portRef PLLWEO (instanceRef EFBInst_0)) + )) + (net PLLADRO4 (joined + (portRef PLLADRO4 (instanceRef EFBInst_0)) + )) + (net PLLADRO3 (joined + (portRef PLLADRO3 (instanceRef EFBInst_0)) + )) + (net PLLADRO2 (joined + (portRef PLLADRO2 (instanceRef EFBInst_0)) + )) + (net PLLADRO1 (joined + (portRef PLLADRO1 (instanceRef EFBInst_0)) + )) + (net PLLADRO0 (joined + (portRef PLLADRO0 (instanceRef EFBInst_0)) + )) + (net PLLDATO7 (joined + (portRef PLLDATO7 (instanceRef EFBInst_0)) + )) + (net PLLDATO6 (joined + (portRef PLLDATO6 (instanceRef EFBInst_0)) + )) + (net PLLDATO5 (joined + (portRef PLLDATO5 (instanceRef EFBInst_0)) + )) + (net PLLDATO4 (joined + (portRef PLLDATO4 (instanceRef EFBInst_0)) + )) + (net PLLDATO3 (joined + (portRef PLLDATO3 (instanceRef EFBInst_0)) + )) + (net PLLDATO2 (joined + (portRef PLLDATO2 (instanceRef EFBInst_0)) + )) + (net PLLDATO1 (joined + (portRef PLLDATO1 (instanceRef EFBInst_0)) + )) + (net PLLDATO0 (joined + (portRef PLLDATO0 (instanceRef EFBInst_0)) + )) + (net I2C1SCLO (joined + (portRef I2C1SCLO (instanceRef EFBInst_0)) + )) + (net I2C1SCLOEN (joined + (portRef I2C1SCLOEN (instanceRef EFBInst_0)) + )) + (net I2C1SDAO (joined + (portRef I2C1SDAO (instanceRef EFBInst_0)) + )) + (net I2C1SDAOEN (joined + (portRef I2C1SDAOEN (instanceRef EFBInst_0)) + )) + (net I2C2SCLO (joined + (portRef I2C2SCLO (instanceRef EFBInst_0)) + )) + (net I2C2SCLOEN (joined + (portRef I2C2SCLOEN (instanceRef EFBInst_0)) + )) + (net I2C2SDAO (joined + (portRef I2C2SDAO (instanceRef EFBInst_0)) + )) + (net I2C2SDAOEN (joined + (portRef I2C2SDAOEN (instanceRef EFBInst_0)) + )) + (net I2C1IRQO (joined + (portRef I2C1IRQO (instanceRef EFBInst_0)) + )) + (net I2C2IRQO (joined + (portRef I2C2IRQO (instanceRef EFBInst_0)) + )) + (net SPISCKO (joined + (portRef SPISCKO (instanceRef EFBInst_0)) + )) + (net SPISCKEN (joined + (portRef SPISCKEN (instanceRef EFBInst_0)) + )) + (net SPIMISOO (joined + (portRef SPIMISOO (instanceRef EFBInst_0)) + )) + (net SPIMISOEN (joined + (portRef SPIMISOEN (instanceRef EFBInst_0)) + )) + (net SPIMOSIO (joined + (portRef SPIMOSIO (instanceRef EFBInst_0)) + )) + (net SPIMOSIEN (joined + (portRef SPIMOSIEN (instanceRef EFBInst_0)) + )) + (net SPIMCSN0 (joined + (portRef SPIMCSN0 (instanceRef EFBInst_0)) + )) + (net SPIMCSN1 (joined + (portRef SPIMCSN1 (instanceRef EFBInst_0)) + )) + (net SPIMCSN2 (joined + (portRef SPIMCSN2 (instanceRef EFBInst_0)) + )) + (net SPIMCSN3 (joined + (portRef SPIMCSN3 (instanceRef EFBInst_0)) + )) + (net SPIMCSN4 (joined + (portRef SPIMCSN4 (instanceRef EFBInst_0)) + )) + (net SPIMCSN5 (joined + (portRef SPIMCSN5 (instanceRef EFBInst_0)) + )) + (net SPIMCSN6 (joined + (portRef SPIMCSN6 (instanceRef EFBInst_0)) + )) + (net SPIMCSN7 (joined + (portRef SPIMCSN7 (instanceRef EFBInst_0)) + )) + (net SPICSNEN (joined + (portRef SPICSNEN (instanceRef EFBInst_0)) + )) + (net SPIIRQO (joined + (portRef SPIIRQO (instanceRef EFBInst_0)) + )) + (net TCINT (joined + (portRef TCINT (instanceRef EFBInst_0)) + )) + (net TCOC (joined + (portRef TCOC (instanceRef EFBInst_0)) + )) + (net wbc_ufm_irq (joined + (portRef WBCUFMIRQ (instanceRef EFBInst_0)) + )) + (net CFGWAKE (joined + (portRef CFGWAKE (instanceRef EFBInst_0)) + )) + (net CFGSTDBY (joined + (portRef CFGSTDBY (instanceRef EFBInst_0)) + )) + ) + (property NGD_DRC_MASK (integer 1)) + (property orig_inst_of (string "REFB")) + ) + ) + (cell RAM2E (cellType GENERIC) + (view verilog (viewType NETLIST) + (interface + (port C14M (direction INPUT)) + (port PHI1 (direction INPUT)) + (port LED (direction OUTPUT)) + (port nWE (direction INPUT)) + (port nWE80 (direction INPUT)) + (port nEN80 (direction INPUT)) + (port nC07X (direction INPUT)) + (port (array (rename ain "Ain[7:0]") 8) (direction INPUT)) + (port (array (rename din "Din[7:0]") 8) (direction INPUT)) + (port (array (rename dout "Dout[7:0]") 8) (direction OUTPUT)) + (port nDOE (direction OUTPUT)) + (port (array (rename vout "Vout[7:0]") 8) (direction OUTPUT)) + (port nVOE (direction OUTPUT)) + (port CKE (direction OUTPUT)) + (port nCS (direction OUTPUT)) + (port nRAS (direction OUTPUT)) + (port nCAS (direction OUTPUT)) + (port nRWE (direction OUTPUT)) + (port (array (rename ba "BA[1:0]") 2) (direction OUTPUT)) + (port (array (rename ra "RA[11:0]") 12) (direction OUTPUT)) + (port (array (rename rd "RD[7:0]") 8) (direction INOUT)) + (port DQML (direction OUTPUT)) + (port DQMH (direction OUTPUT)) + ) + (contents + (instance VCC (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) ) + (instance GND (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) ) + (instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT))) + ) + (instance (rename S_RNII9DO1_2_1 "S_RNII9DO1_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) + ) + (instance (rename S_RNII9DO1_0_1 "S_RNII9DO1_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B+!A)))")) + ) + (instance (rename wb_dati_7_0_2_RNO_3 "wb_dati_7_0_2_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance DQML_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance (rename wb_adr_RNO_3_1 "wb_adr_RNO_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B !A))")) + ) + (instance CKE_6_iv_i_0_1_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !A+C (!B !A))")) + ) + (instance (rename FS_RNIOD6E_1_8 "FS_RNIOD6E_1[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B !A)))")) + ) + (instance (rename wb_adr_RNO_2_1 "wb_adr_RNO_2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !A+C (!B !A+B A))")) + ) + (instance (rename FS_RNI9FGA_1 "FS_RNI9FGA[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) + (instance (rename S_RNII9DO1_1 "S_RNII9DO1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance (rename un1_RWMask_0_sqmuxa_1_i_0_RNO_0 "un1_RWMask_0_sqmuxa_1_i_0_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance (rename wb_dati_7_0_0_RNO_7 "wb_dati_7_0_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance wb_we_RNO_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A))+D (!B A))")) + ) + (instance wb_reqc_1_RNIRU4M1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B A)))")) + ) + (instance (rename FS_RNIOD6E_0_8 "FS_RNIOD6E_0[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance (rename RA_42_0_RNO_10 "RA_42_0_RNO[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A))+D (!C (!B A)))")) + ) + (instance (rename FS_RNIOD6E_8 "FS_RNIOD6E[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B A)+D (!C (B A)+C (B !A)))")) + ) + (instance (rename S_RNII9DO1_3_1 "S_RNII9DO1_3[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) + ) + (instance (rename FS_RNI5OOF1_15 "FS_RNI5OOF1[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance (rename BA_0io_RNO_0 "BA_0io_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) + ) + (instance (rename BA_0io_RNO_1 "BA_0io_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) + ) + (instance nCAS_0io_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B A)+D (C+(!B A)))")) + ) + (instance wb_we_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B+A)+D (!C (!B+A)+C (!B A)))")) + ) + (instance DOEEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B A)+D (!C (B A)+C A))")) + ) + (instance wb_req_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance (rename FS_RNIK5632_15 "FS_RNIK5632[15]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B !A)))")) + ) + (instance DQMH_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C+(!B+!A)))")) + ) + (instance (rename CmdTout_RNO_2 "CmdTout_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A+C (!B A+B !A)))")) + ) + (instance wb_cyc_stb_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B+A)))")) + ) + (instance (rename wb_dati_7_0_a2_5_RNIC22J_4 "wb_dati_7_0_a2_5_RNIC22J[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance nCS_6_u_i_a2_4_RNI3A062 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B A))")) + ) + (instance nCS_6_u_i_a2_4_RNICJKD2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance wb_reqc_1_RNIEO5C1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) + ) + (instance Ready_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance (rename Vout_0__CN "Vout_0_.CN") (viewRef PRIM (cellRef INV (libraryRef LUCENT))) ) + (instance PHI1reg_0io (viewRef PRIM (cellRef IFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nRWE_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nRAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nCS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance nCAS_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Vout_0io_0 "Vout_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Vout_0io_1 "Vout_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Vout_0io_2 "Vout_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Vout_0io_3 "Vout_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Vout_0io_4 "Vout_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Vout_0io_5 "Vout_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Vout_0io_6 "Vout_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Vout_0io_7 "Vout_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RA_0io_1 "RA_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RA_0io_2 "RA_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RA_0io_4 "RA_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RA_0io_5 "RA_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RA_0io_6 "RA_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RA_0io_7 "RA_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RA_0io_8 "RA_0io[8]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RA_0io_9 "RA_0io[9]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RA_0io_10 "RA_0io[10]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename RA_0io_11 "RA_0io[11]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Dout_0io_0 "Dout_0io[0]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Dout_0io_1 "Dout_0io[1]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Dout_0io_2 "Dout_0io[2]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Dout_0io_3 "Dout_0io[3]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Dout_0io_4 "Dout_0io[4]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Dout_0io_5 "Dout_0io[5]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Dout_0io_6 "Dout_0io[6]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename Dout_0io_7 "Dout_0io[7]") (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance DQML_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance DQMH_0io (viewRef PRIM (cellRef OFS1P3BX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance CKE_0io (viewRef PRIM (cellRef OFS1P3DX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename BA_0io_0 "BA_0io[0]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance (rename BA_0io_1 "BA_0io[1]") (viewRef PRIM (cellRef OFS1P3IX (libraryRef LUCENT))) + (property IOB (string "FALSE")) + ) + (instance wb_we (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance wb_rst (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance wb_req (viewRef PRIM (cellRef FD1P3IX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_0 "wb_dati[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_1 "wb_dati[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_2 "wb_dati[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_3 "wb_dati[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_4 "wb_dati[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_5 "wb_dati[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_6 "wb_dati[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_dati_7 "wb_dati[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance wb_cyc_stb (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_0 "wb_adr[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_1 "wb_adr[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_2 "wb_adr[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_3 "wb_adr[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_4 "wb_adr[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_5 "wb_adr[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_6 "wb_adr[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename wb_adr_7 "wb_adr[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename S_0 "S[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename S_1 "S[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename S_2 "S[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename S_3 "S[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance Ready (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance RWSel (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWMask_0 "RWMask[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWMask_1 "RWMask[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWMask_2 "RWMask[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWMask_3 "RWMask[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWMask_4 "RWMask[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWMask_5 "RWMask[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWMask_6 "RWMask[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWMask_7 "RWMask[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWBank_0 "RWBank[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWBank_1 "RWBank[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWBank_2 "RWBank[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWBank_3 "RWBank[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWBank_4 "RWBank[4]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWBank_5 "RWBank[5]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWBank_6 "RWBank[6]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RWBank_7 "RWBank[7]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RA_0 "RA[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename RA_3 "RA[3]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance LEDEN (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename FS_0 "FS[0]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_1 "FS[1]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_2 "FS[2]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_3 "FS[3]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_4 "FS[4]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_5 "FS[5]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_6 "FS[6]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_7 "FS[7]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_8 "FS[8]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_9 "FS[9]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_10 "FS[10]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_11 "FS[11]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_12 "FS[12]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_13 "FS[13]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_14 "FS[14]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename FS_15 "FS[15]") (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance DOEEN (viewRef PRIM (cellRef FD1S3AX (libraryRef LUCENT))) + ) + (instance (rename CmdTout_0 "CmdTout[0]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename CmdTout_1 "CmdTout[1]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename CmdTout_2 "CmdTout[2]") (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdSetRWBankFFMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdSetRWBankFFLED (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdRWMaskSet (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdLEDSet (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdLEDGet (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdExecMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance CmdBitbangMXO2 (viewRef PRIM (cellRef FD1P3AX (libraryRef LUCENT))) + ) + (instance (rename CS_0 "CS[0]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance (rename CS_1 "CS[1]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance (rename CS_2 "CS[2]") (viewRef PRIM (cellRef FD1S3IX (libraryRef LUCENT))) + ) + (instance DQMH_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance DQML_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RD_pad_7 "RD_pad[7]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_6 "RD_pad[6]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_5 "RD_pad[5]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_4 "RD_pad[4]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_3 "RD_pad[3]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_2 "RD_pad[2]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_1 "RD_pad[1]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RD_pad_0 "RD_pad[0]") (viewRef PRIM (cellRef BB (libraryRef LUCENT))) ) + (instance (rename RA_pad_11 "RA_pad[11]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_10 "RA_pad[10]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_9 "RA_pad[9]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_8 "RA_pad[8]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_7 "RA_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_6 "RA_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_5 "RA_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_4 "RA_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_3 "RA_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_2 "RA_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_1 "RA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename RA_pad_0 "RA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename BA_pad_1 "BA_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename BA_pad_0 "BA_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRWE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nCAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nRAS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nCS_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance CKE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nVOE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Vout_pad_7 "Vout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Vout_pad_6 "Vout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Vout_pad_5 "Vout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Vout_pad_4 "Vout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Vout_pad_3 "Vout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Vout_pad_2 "Vout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Vout_pad_1 "Vout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Vout_pad_0 "Vout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance nDOE_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_7 "Dout_pad[7]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_6 "Dout_pad[6]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_5 "Dout_pad[5]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_4 "Dout_pad[4]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_3 "Dout_pad[3]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_2 "Dout_pad[2]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_1 "Dout_pad[1]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Dout_pad_0 "Dout_pad[0]") (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance (rename Din_pad_7 "Din_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Din_pad_6 "Din_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Din_pad_5 "Din_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Din_pad_4 "Din_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Din_pad_3 "Din_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Din_pad_2 "Din_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Din_pad_1 "Din_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Din_pad_0 "Din_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Ain_pad_7 "Ain_pad[7]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Ain_pad_6 "Ain_pad[6]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Ain_pad_5 "Ain_pad[5]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Ain_pad_4 "Ain_pad[4]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Ain_pad_3 "Ain_pad[3]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Ain_pad_2 "Ain_pad[2]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Ain_pad_1 "Ain_pad[1]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance (rename Ain_pad_0 "Ain_pad[0]") (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nC07X_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nEN80_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nWE80_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance nWE_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance LED_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) ) + (instance PHI1_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) + ) + (instance C14M_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) ) + (instance un1_CS_0_sqmuxa_0_0_2_RNIQS7F (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C !B)+D (!C (!B !A)))")) + ) + (instance nCAS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(!B+A))+D A)")) + ) + (instance nRWE_r_0_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(!B+A)))")) + ) + (instance nCS_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance nRAS_2_iv_i (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A)+C !A)")) + ) + (instance (rename wb_dati_7_0_5 "wb_dati_7_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C A+C (B+A)))")) + ) + (instance (rename wb_dati_7_0_2 "wb_dati_7_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C A+C (B+A)))")) + ) + (instance (rename wb_dati_7_0_7 "wb_dati_7_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance (rename wb_adr_7_0_0 "wb_adr_7_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C B+C (B+A)))")) + ) + (instance (rename wb_dati_7_0_6 "wb_dati_7_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B A))")) + ) + (instance (rename wb_dati_7_0_4 "wb_dati_7_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance (rename wb_dati_7_0_3 "wb_dati_7_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C+(B+A))")) + ) + (instance (rename RA_42_0_10 "RA_42_0[10]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C B+C (B+!A)))")) + ) + (instance un1_CS_0_sqmuxa_0_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(B A)))")) + ) + (instance un1_CS_0_sqmuxa_0_0_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance (rename CS_RNO_2 "CS_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (!B A+B !A))")) + ) + (instance nCS_6_u_i_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C A+C (B+A)))")) + ) + (instance (rename wb_dati_7_0_1 "wb_dati_7_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C A+C (B+A)))")) + ) + (instance un1_CS_0_sqmuxa_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D C+D (C+(B A)))")) + ) + (instance (rename wb_dati_7_0_1_6 "wb_dati_7_0_1[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B+A)+D (C+(B+A)))")) + ) + (instance (rename wb_dati_7_0_2_3 "wb_dati_7_0_2[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B !A))+D (B !A))")) + ) + (instance (rename wb_adr_7_0_4_0 "wb_adr_7_0_4[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance (rename CS_RNO_0 "CS_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A+B A)+C A)")) + ) + (instance CmdSetRWBankFFLED_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A)+C B)")) + ) + (instance CmdExecMXO2_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A+C (B+A))+D (C B))")) + ) + (instance CmdRWMaskSet_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A+C (B+A))+D (C B))")) + ) + (instance CmdBitbangMXO2_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A+C (B+A))+D (C B))")) + ) + (instance CmdLEDSet_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A)+C B)")) + ) + (instance (rename un1_LEDEN_0_sqmuxa_1_i_0_0 "un1_LEDEN_0_sqmuxa_1_i_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B A)+D (C+(B A)))")) + ) + (instance wb_cyc_stb_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) + ) + (instance (rename un1_RWMask_0_sqmuxa_1_i_0_0 "un1_RWMask_0_sqmuxa_1_i_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B A)+D (C+(B A)))")) + ) + (instance (rename wb_dati_7_0_0 "wb_dati_7_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) + ) + (instance (rename wb_adr_7_0_a2_0_0 "wb_adr_7_0_a2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B+A)+C B))")) + ) + (instance (rename wb_dati_7_0_a2_4 "wb_dati_7_0_a2[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B !A))+D (B !A))")) + ) + (instance (rename wb_dati_7_0_RNO_7 "wb_dati_7_0_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A))+D C)")) + ) + (instance (rename wb_dati_7_0_a2_3_4 "wb_dati_7_0_a2_3[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance (rename wb_dati_7_0_a2_7 "wb_dati_7_0_a2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)+C (B A)))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A))")) + ) + (instance (rename wb_dati_7_0_o2_0_2 "wb_dati_7_0_o2_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C A+C (B+A)))")) + ) + (instance (rename wb_dati_7_0_0_3 "wb_dati_7_0_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B A)+D (C+(B A)))")) + ) + (instance (rename wb_dati_7_0_0_4 "wb_dati_7_0_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B A)+D (C+(B A)))")) + ) + (instance DQML_0io_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B+!A)+D (!C !B+C (!B+!A)))")) + ) + (instance CmdSetRWBankFFMXO2_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A+C (B+A))+D (C B))")) + ) + (instance CmdSetRWBankFFLED_4_u_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance CmdLEDGet_4_u_0_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A+C (B+A))+D (C B))")) + ) + (instance (rename wb_dati_7_0_a2_5_4 "wb_dati_7_0_a2_5[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B A))")) + ) + (instance nCS_6_u_i_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance CKE_6_iv_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C A+C (B+A))+D A)")) + ) + (instance wb_we_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (B !A)))")) + ) + (instance (rename wb_adr_RNO_1 "wb_adr_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C B+C (B+A)))")) + ) + (instance (rename wb_adr_7_0_a2_2_0 "wb_adr_7_0_a2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance (rename wb_dati_7_0_a2_6 "wb_dati_7_0_a2[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A+B A)))")) + ) + (instance (rename un1_LEDEN13_2_i_0_0 "un1_LEDEN13_2_i_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B+A)+D (C+(B+A)))")) + ) + (instance (rename wb_dati_7_0_a2_1_7 "wb_dati_7_0_a2_1[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B !A)))")) + ) + (instance (rename wb_adr_7_0_a2_1_0 "wb_adr_7_0_a2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B+!A)))")) + ) + (instance (rename wb_dati_7_0_a2_1 "wb_dati_7_0_a2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance Ready_0_sqmuxa_0_a2_6_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance CmdLEDSet_4_u_0_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_4_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance (rename wb_dati_7_0_0_1 "wb_dati_7_0_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) + ) + (instance (rename wb_dati_7_0_0_7 "wb_dati_7_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C B)+D (!C A+C (B+A)))")) + ) + (instance (rename wb_adr_7_0_0_0 "wb_adr_7_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C A)+D (!C B+C (B+A)))")) + ) + (instance (rename wb_adr_7_0_1_0 "wb_adr_7_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A))+D B)")) + ) + (instance (rename S_RNO_2 "S_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)+C (B !A))+D (!C (!B !A)+C !A))")) + ) + (instance (rename un1_LEDEN13_2_i_a2_0_0 "un1_LEDEN13_2_i_a2_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A))+D (C !B))")) + ) + (instance (rename S_RNII9DO1_1_1 "S_RNII9DO1_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A+B A)+C (B A))+D (!C (!B A)+C B))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B !A)))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_1_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_3_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance (rename wb_adr_RNO_1_1 "wb_adr_RNO_1[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A))+D (!C A+C (!B A)))")) + ) + (instance wb_we_RNO_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) + ) + (instance wb_we_RNO_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B+A)))")) + ) + (instance CmdBitbangMXO2_RNI8CSO1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B+A)))")) + ) + (instance (rename RA_0io_RNO_8 "RA_0io_RNO[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (B !A)+D (C !A))")) + ) + (instance (rename RA_0io_RNO_9 "RA_0io_RNO[9]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C !B+C (!B A)))")) + ) + (instance (rename S_RNO_1 "S_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)+C !A))")) + ) + (instance (rename S_RNO_3 "S_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A))+D !A)")) + ) + (instance un1_CS_0_sqmuxa_0_0_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C (!B A)))")) + ) + (instance CmdSetRWBankFFLED_4_u_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance wb_req_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B !A)))")) + ) + (instance CKE_6_iv_i_a2_3 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B A)))")) + ) + (instance (rename un1_LEDEN13_2_i_o2_2_0 "un1_LEDEN13_2_i_o2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(B+A)))")) + ) + (instance (rename S_s_0_0 "S_s_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(!C A+C (!B+A)))")) + ) + (instance (rename CS_RNO_0_2 "CS_RNO_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_4_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B !A)))")) + ) + (instance CKE_6_iv_i_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C B+C (!B A))+D (!C+(!B A)))")) + ) + (instance Ready_0_sqmuxa_0_a2_6_a2_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance nCS_6_u_i_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)+C (!B !A))+D (!C (!B A)))")) + ) + (instance (rename wb_adr_7_0_a2_0_0_0 "wb_adr_7_0_a2_0_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A))+D (!C (!B A)+C !B))")) + ) + (instance (rename CmdTout_RNO_1 "CmdTout_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A+B !A))")) + ) + (instance (rename RA_RNO_3 "RA_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C A)")) + ) + (instance (rename RA_0io_RNO_4 "RA_0io_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C A)")) + ) + (instance (rename RA_0io_RNO_6 "RA_0io_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C A)")) + ) + (instance (rename RA_0io_RNO_7 "RA_0io_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C A)")) + ) + (instance (rename RA_RNO_0 "RA_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C A)")) + ) + (instance (rename RA_0io_RNO_1 "RA_0io_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C A)")) + ) + (instance (rename RA_0io_RNO_2 "RA_0io_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C A)")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_10 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B !A))")) + ) + (instance (rename RWBank_5_0_4 "RWBank_5_0[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A)+C B)")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_5 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C+(!B+!A)))")) + ) + (instance nCAS_s_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance (rename wb_dati_7_0_o2_1 "wb_dati_7_0_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A))+D (!C (B A)))")) + ) + (instance (rename RWBank_5_0_2 "RWBank_5_0[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A)+C B)")) + ) + (instance (rename RWBank_5_0_3 "RWBank_5_0[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A)+C B)")) + ) + (instance (rename RWBank_5_0_5 "RWBank_5_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A)+C B)")) + ) + (instance (rename RWBank_5_0_6 "RWBank_5_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A)+C B)")) + ) + (instance (rename RWBank_5_0_0_7 "RWBank_5_0_0[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C B+C (B+A))")) + ) + (instance (rename RWBank_5_0_1 "RWBank_5_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A)+C B)")) + ) + (instance (rename RWBank_5_0_0 "RWBank_5_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B+A)+C B)")) + ) + (instance nRWE_r_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!B A)+D (!C (!B A)+C !B))")) + ) + (instance nDOE_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(B+!A))")) + ) + (instance (rename RA_0io_RNO_11 "RA_0io_RNO[11]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A)))")) + ) + (instance RWSel_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance wb_we_RNO_4 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A)))")) + ) + (instance nCS_6_u_i_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B !A)))")) + ) + (instance (rename wb_adr_RNO_0_1 "wb_adr_RNO_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B A)))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_15 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (!B A)))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_2_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (!B A)))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_1_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B !A)))")) + ) + (instance (rename S_s_0_1_0 "S_s_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C !A)+D (!C !A+C (B+!A)))")) + ) + (instance CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B !A))")) + ) + (instance CmdLEDGet_4_u_0_0_a2_0_2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)))")) + ) + (instance (rename wb_dati_7_0_a2_2_0_1 "wb_dati_7_0_a2_2_0[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance (rename un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0 "un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (!B !A)))")) + ) + (instance (rename wb_dati_7_0_a2_1_0_0 "wb_dati_7_0_a2_1_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B A)+C (!B A)))")) + ) + (instance (rename RWMask_RNO_6 "RWMask_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A)+C (!B+!A))")) + ) + (instance (rename RWMask_RNO_5 "RWMask_RNO[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A)+C (!B+!A))")) + ) + (instance (rename RWMask_RNO_4 "RWMask_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A)+C (!B+!A))")) + ) + (instance (rename RWMask_RNO_3 "RWMask_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A)+C (!B+!A))")) + ) + (instance (rename RWMask_RNO_2 "RWMask_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A)+C (!B+!A))")) + ) + (instance (rename RWMask_RNO_1 "RWMask_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A)+C (!B+!A))")) + ) + (instance (rename RWMask_RNO_0 "RWMask_RNO[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B !A)+C (!B+!A))")) + ) + (instance (rename un1_wb_adr_0_sqmuxa_2_0_1_0 "un1_wb_adr_0_sqmuxa_2_0_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+!A)+D (!C+!B))")) + ) + (instance (rename wb_adr_RNO_2 "wb_adr_RNO[2]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename wb_adr_RNO_3 "wb_adr_RNO[3]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance (rename wb_adr_RNO_7 "wb_adr_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_7 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance wb_req_RNO_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance (rename RA_42_i_o2_8 "RA_42_i_o2[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(B+A))")) + ) + (instance nRAS_2_iv_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A)+C (!B !A))")) + ) + (instance Vout3_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B !A)))")) + ) + (instance (rename RA_42_3_0_5 "RA_42_3_0[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B+A)+C A)")) + ) + (instance (rename wb_dati_7_0_a2_0_2_7 "wb_dati_7_0_a2_0_2[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (!C (B+!A)))")) + ) + (instance (rename wb_dati_7_0_a2_0_0_6 "wb_dati_7_0_a2_0_0[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) + ) + (instance LED_pad_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+!A)")) + ) + (instance nWE80_pad_RNI3ICD (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance (rename RWBank_5_0_o2_0 "RWBank_5_0_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C+B)+D (C+(B+A)))")) + ) + (instance (rename SZ0Z_1 "S_1") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B A))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_1_6 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) + ) + (instance (rename wb_adr_7_0_a2_5_0_0 "wb_adr_7_0_a2_5_0[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) + ) + (instance CmdBitbangMXO2_4_u_0_0_a2_0_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B !A))")) + ) + (instance Ready_0_sqmuxa_0_a2_6_a2_2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance nCS_6_u_i_a2_1_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (!B A)))")) + ) + (instance (rename wb_adr_RNO_4 "wb_adr_RNO[4]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !B+C A)")) + ) + (instance (rename wb_adr_RNO_6 "wb_adr_RNO[6]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !B+C A)")) + ) + (instance (rename wb_adr_RNO_5 "wb_adr_RNO[5]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C !B+C A)")) + ) + (instance LEDEN_RNO (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+A))")) + ) + (instance (rename RWMask_RNO_7 "RWMask_RNO[7]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A)+C (!B+A))")) + ) + (instance (rename CmdTout_3_0_a2_0 "CmdTout_3_0_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_11 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_12 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_13 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance nCS_6_u_i_o2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance (rename un1_LEDEN13_2_i_o2_0 "un1_LEDEN13_2_i_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance (rename wb_adr_7_0_o2_0 "wb_adr_7_0_o2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance (rename S_RNINI6S_1 "S_RNINI6S[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance (rename S_r_i_o2_1 "S_r_i_o2[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance (rename FS_RNI9Q57_13 "FS_RNI9Q57[13]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+A)")) + ) + (instance (rename wb_adr_7_0_o2_2_0 "wb_adr_7_0_o2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B+!A)")) + ) + (instance (rename FS_RNIJ9MH_14 "FS_RNIJ9MH[14]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance (rename wb_dati_7_0_a2_1_0 "wb_dati_7_0_a2_1[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B A)")) + ) + (instance wb_rst8_0_a2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!B !A)")) + ) + (instance wb_reqc_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(B+A)")) + ) + (instance CmdBitbangMXO2_4_u_0_0_a2_1 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B A))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_16 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (!B !A))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_17 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (B A))")) + ) + (instance un1_nCS61_1_0_a2_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B A)))")) + ) + (instance (rename FS_RNI6JJA_8 "FS_RNI6JJA[8]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C+(!B+!A))")) + ) + (instance un1_CS_0_sqmuxa_0_0_a2_3_0 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D (C (B A)))")) + ) + (instance (rename CS_RNO_1 "CS_RNO[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D A+D (!C (!B !A+B A)+C A))")) + ) + (instance (rename wb_dati_7_0_a2_5_1 "wb_dati_7_0_a2_5[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(C (!B !A))")) + ) + (instance nCS_6_u_i_o2 (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(D+(C+(!B !A)))")) + ) + (instance (rename un1_LEDEN13_2_i_a2_0 "un1_LEDEN13_2_i_a2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (C (B+A)))")) + ) + (instance (rename wb_dati_7_0_a2_2_0 "wb_dati_7_0_a2_2[0]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!D (!C (B !A)))")) + ) + (instance (rename wb_dati_7_0_a2_6_1 "wb_dati_7_0_a2_6[1]") (viewRef PRIM (cellRef ORCALUT4 (libraryRef LUCENT))) + (property lut_function (string "(!C (B A))")) + ) + (instance (rename FS_s_0_15 "FS_s_0[15]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x5002")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_13 "FS_cry_0[13]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_11 "FS_cry_0[11]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_9 "FS_cry_0[9]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_7 "FS_cry_0[7]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_5 "FS_cry_0[5]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_3 "FS_cry_0[3]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_1 "FS_cry_0[1]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance (rename FS_cry_0_0 "FS_cry_0[0]") (viewRef PRIM (cellRef CCU2D (libraryRef LUCENT))) + (property INIT0 (string "0x300A")) + (property INJECT1_1 (string "NO")) + (property INJECT1_0 (string "NO")) + (property INIT1 (string "0x300A")) + ) + (instance ufmefb (viewRef netlist (cellRef REFB)) + ) + (net wb_rst (joined + (portRef Q (instanceRef wb_rst)) + (portRef wb_rst (instanceRef ufmefb)) + )) + (net wb_cyc_stb (joined + (portRef Q (instanceRef wb_cyc_stb)) + (portRef wb_cyc_stb (instanceRef ufmefb)) + )) + (net wb_we (joined + (portRef Q (instanceRef wb_we)) + (portRef wb_we (instanceRef ufmefb)) + )) + (net (rename wb_adr_0 "wb_adr[0]") (joined + (portRef Q (instanceRef wb_adr_0)) + (portRef (member wb_adr 7) (instanceRef ufmefb)) + (portRef C (instanceRef wb_dati_7_0_0)) + )) + (net (rename wb_adr_1 "wb_adr[1]") (joined + (portRef Q (instanceRef wb_adr_1)) + (portRef (member wb_adr 6) (instanceRef ufmefb)) + (portRef C (instanceRef wb_dati_7_0_0_1)) + )) + (net (rename wb_adr_2 "wb_adr[2]") (joined + (portRef Q (instanceRef wb_adr_2)) + (portRef (member wb_adr 5) (instanceRef ufmefb)) + (portRef C (instanceRef wb_dati_7_0_2)) + )) + (net (rename wb_adr_3 "wb_adr[3]") (joined + (portRef Q (instanceRef wb_adr_3)) + (portRef (member wb_adr 4) (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_7_0_0_3)) + )) + (net (rename wb_adr_4 "wb_adr[4]") (joined + (portRef Q (instanceRef wb_adr_4)) + (portRef (member wb_adr 3) (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_7_0_0_4)) + )) + (net (rename wb_adr_5 "wb_adr[5]") (joined + (portRef Q (instanceRef wb_adr_5)) + (portRef (member wb_adr 2) (instanceRef ufmefb)) + (portRef C (instanceRef wb_dati_7_0_5)) + )) + (net (rename wb_adr_6 "wb_adr[6]") (joined + (portRef Q (instanceRef wb_adr_6)) + (portRef (member wb_adr 1) (instanceRef ufmefb)) + (portRef D (instanceRef wb_dati_7_0_1_6)) + )) + (net (rename wb_adr_7 "wb_adr[7]") (joined + (portRef Q (instanceRef wb_adr_7)) + (portRef (member wb_adr 0) (instanceRef ufmefb)) + (portRef C (instanceRef wb_dati_7_0_0_7)) + )) + (net (rename wb_dati_0 "wb_dati[0]") (joined + (portRef Q (instanceRef wb_dati_0)) + (portRef (member wb_dati 7) (instanceRef ufmefb)) + )) + (net (rename wb_dati_1 "wb_dati[1]") (joined + (portRef Q (instanceRef wb_dati_1)) + (portRef (member wb_dati 6) (instanceRef ufmefb)) + )) + (net (rename wb_dati_2 "wb_dati[2]") (joined + (portRef Q (instanceRef wb_dati_2)) + (portRef (member wb_dati 5) (instanceRef ufmefb)) + )) + (net (rename wb_dati_3 "wb_dati[3]") (joined + (portRef Q (instanceRef wb_dati_3)) + (portRef (member wb_dati 4) (instanceRef ufmefb)) + )) + (net (rename wb_dati_4 "wb_dati[4]") (joined + (portRef Q (instanceRef wb_dati_4)) + (portRef (member wb_dati 3) (instanceRef ufmefb)) + )) + (net (rename wb_dati_5 "wb_dati[5]") (joined + (portRef Q (instanceRef wb_dati_5)) + (portRef (member wb_dati 2) (instanceRef ufmefb)) + )) + (net (rename wb_dati_6 "wb_dati[6]") (joined + (portRef Q (instanceRef wb_dati_6)) + (portRef (member wb_dati 1) (instanceRef ufmefb)) + )) + (net (rename wb_dati_7 "wb_dati[7]") (joined + (portRef Q (instanceRef wb_dati_7)) + (portRef (member wb_dati 0) (instanceRef ufmefb)) + )) + (net (rename wb_dato_0 "wb_dato[0]") (joined + (portRef (member wb_dato 7) (instanceRef ufmefb)) + (portRef C (instanceRef LEDEN_RNO)) + (portRef C (instanceRef RWMask_RNO_0)) + )) + (net (rename wb_dato_1 "wb_dato[1]") (joined + (portRef (member wb_dato 6) (instanceRef ufmefb)) + (portRef C (instanceRef RWMask_RNO_1)) + )) + (net (rename wb_dato_2 "wb_dato[2]") (joined + (portRef (member wb_dato 5) (instanceRef ufmefb)) + (portRef C (instanceRef RWMask_RNO_2)) + )) + (net (rename wb_dato_3 "wb_dato[3]") (joined + (portRef (member wb_dato 4) (instanceRef ufmefb)) + (portRef C (instanceRef RWMask_RNO_3)) + )) + (net (rename wb_dato_4 "wb_dato[4]") (joined + (portRef (member wb_dato 3) (instanceRef ufmefb)) + (portRef C (instanceRef RWMask_RNO_4)) + )) + (net (rename wb_dato_5 "wb_dato[5]") (joined + (portRef (member wb_dato 2) (instanceRef ufmefb)) + (portRef C (instanceRef RWMask_RNO_5)) + )) + (net (rename wb_dato_6 "wb_dato[6]") (joined + (portRef (member wb_dato 1) (instanceRef ufmefb)) + (portRef C (instanceRef RWMask_RNO_6)) + )) + (net (rename wb_dato_7 "wb_dato[7]") (joined + (portRef (member wb_dato 0) (instanceRef ufmefb)) + (portRef C (instanceRef RWMask_RNO_7)) + )) + (net wb_ack (joined + (portRef wb_ack (instanceRef ufmefb)) + (portRef A (instanceRef un1_LEDEN13_2_i_a2_0)) + (portRef B (instanceRef un1_LEDEN13_2_i_o2_0)) + (portRef D (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0)) + (portRef C (instanceRef wb_cyc_stb_RNO_0)) + (portRef A (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0)) + )) + (net (rename S_2 "S[2]") (joined + (portRef Q (instanceRef S_2)) + (portRef B (instanceRef FS_RNIJ9MH_14)) + (portRef A (instanceRef S_r_i_o2_1)) + (portRef C (instanceRef wb_adr_RNO_5)) + (portRef C (instanceRef wb_adr_RNO_6)) + (portRef C (instanceRef wb_adr_RNO_4)) + (portRef C (instanceRef nCS_6_u_i_a2_1_0)) + (portRef C (instanceRef Vout3_0_a2)) + (portRef B (instanceRef nRAS_2_iv_0_a2_0)) + (portRef B (instanceRef RA_42_i_o2_8)) + (portRef B (instanceRef wb_adr_RNO_7)) + (portRef B (instanceRef wb_adr_RNO_3)) + (portRef B (instanceRef wb_adr_RNO_2)) + (portRef C (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0)) + (portRef C (instanceRef S_s_0_1_0)) + (portRef B (instanceRef RA_0io_RNO_11)) + (portRef B (instanceRef nCS_6_u_i_0)) + (portRef B (instanceRef CKE_6_iv_i_0_1)) + (portRef C (instanceRef S_RNO_3)) + (portRef B (instanceRef RA_0io_RNO_9)) + (portRef B (instanceRef CmdBitbangMXO2_RNI8CSO1)) + (portRef B (instanceRef wb_we_RNO_0)) + (portRef D (instanceRef wb_we_RNO_2)) + (portRef C (instanceRef S_RNII9DO1_1_1)) + (portRef C (instanceRef S_RNO_2)) + (portRef C (instanceRef wb_adr_7_0_0_0)) + (portRef B (instanceRef wb_dati_7_0_0_7)) + (portRef B (instanceRef wb_dati_7_0_0_1)) + (portRef C (instanceRef wb_adr_RNO_1)) + (portRef C (instanceRef wb_dati_7_0_0_4)) + (portRef C (instanceRef wb_dati_7_0_0_3)) + (portRef B (instanceRef wb_dati_7_0_0)) + (portRef C (instanceRef wb_dati_7_0_1_6)) + (portRef B (instanceRef wb_dati_7_0_2)) + (portRef B (instanceRef wb_dati_7_0_5)) + (portRef CD (instanceRef wb_req)) + (portRef C (instanceRef wb_reqc_1_RNIEO5C1)) + (portRef D (instanceRef wb_req_RNO_0)) + (portRef B (instanceRef DOEEN_RNO)) + (portRef C (instanceRef BA_0io_RNO_1)) + (portRef C (instanceRef BA_0io_RNO_0)) + (portRef D (instanceRef FS_RNI5OOF1_15)) + (portRef C (instanceRef S_RNII9DO1_3_1)) + (portRef C (instanceRef RA_42_0_RNO_10)) + (portRef B (instanceRef wb_reqc_1_RNIRU4M1)) + (portRef B (instanceRef S_RNII9DO1_1)) + (portRef B (instanceRef DQML_0io_RNO_0)) + (portRef A (instanceRef S_RNII9DO1_0_1)) + (portRef B (instanceRef S_RNII9DO1_2_1)) + )) + (net RWSel (joined + (portRef Q (instanceRef RWSel)) + (portRef C (instanceRef un1_LEDEN13_2_i_a2_0)) + (portRef B (instanceRef CmdTout_3_0_a2_0)) + (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_7)) + (portRef B (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0)) + (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_5)) + (portRef C (instanceRef CmdTout_RNO_1)) + (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4)) + (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_2)) + (portRef D (instanceRef CmdLEDGet_4_u_0_0_0)) + (portRef D (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0)) + (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_1)) + (portRef C (instanceRef CmdLEDSet_4_u_0_0_0)) + (portRef D (instanceRef CmdBitbangMXO2_4_u_0_0_0)) + (portRef D (instanceRef CmdRWMaskSet_4_u_0_0_0)) + (portRef D (instanceRef CmdExecMXO2_4_u_0_0_0)) + (portRef C (instanceRef CmdSetRWBankFFLED_4_u_0_0_0)) + (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_0)) + (portRef D (instanceRef CmdTout_RNO_2)) + (portRef A (instanceRef wb_reqc_1_RNIRU4M1)) + )) + (net (rename S_0 "S[0]") (joined + (portRef Q (instanceRef S_0)) + (portRef A (instanceRef wb_reqc_1)) + (portRef A (instanceRef S_RNINI6S_1)) + (portRef B (instanceRef nCS_6_u_i_a2_1_0)) + (portRef B (instanceRef RA_42_3_0_5)) + (portRef A (instanceRef Vout3_0_a2)) + (portRef A (instanceRef S_s_0_1_0)) + (portRef B (instanceRef nCS_6_u_i_a2_0)) + (portRef C (instanceRef nRWE_r_0)) + (portRef B (instanceRef RA_0io_RNO_2)) + (portRef B (instanceRef RA_0io_RNO_1)) + (portRef B (instanceRef RA_RNO_0)) + (portRef B (instanceRef RA_0io_RNO_7)) + (portRef B (instanceRef RA_0io_RNO_6)) + (portRef B (instanceRef RA_0io_RNO_4)) + (portRef B (instanceRef RA_RNO_3)) + (portRef B (instanceRef S_s_0_0)) + (portRef D (instanceRef RA_0io_RNO_8)) + (portRef A (instanceRef S_RNII9DO1_1_1)) + (portRef C (instanceRef nRAS_2_iv_i)) + (portRef C (instanceRef DQMH_0io_RNO)) + (portRef D (instanceRef DOEEN_RNO)) + (portRef C (instanceRef nCAS_0io_RNO_0)) + (portRef A (instanceRef S_RNII9DO1_3_1)) + (portRef A (instanceRef RA_42_0_RNO_10)) + (portRef D (instanceRef S_RNII9DO1_1)) + (portRef C (instanceRef CKE_6_iv_i_0_1_RNO)) + (portRef D (instanceRef DQML_0io_RNO_0)) + (portRef D (instanceRef S_RNII9DO1_0_1)) + (portRef D (instanceRef S_RNII9DO1_2_1)) + )) + (net (rename S_1 "S[1]") (joined + (portRef Q (instanceRef S_1)) + (portRef B (instanceRef wb_reqc_1)) + (portRef B (instanceRef S_RNINI6S_1)) + (portRef B (instanceRef Vout3_0_a2)) + (portRef A (instanceRef nRAS_2_iv_0_a2_0)) + (portRef A (instanceRef RA_42_i_o2_8)) + (portRef B (instanceRef S_s_0_1_0)) + (portRef C (instanceRef nCS_6_u_i_a2_0)) + (portRef A (instanceRef nCS_6_u_i_0)) + (portRef C (instanceRef S_s_0_0)) + (portRef B (instanceRef S_RNII9DO1_1_1)) + (portRef C (instanceRef DOEEN_RNO)) + (portRef D (instanceRef BA_0io_RNO_1)) + (portRef D (instanceRef BA_0io_RNO_0)) + (portRef D (instanceRef S_RNII9DO1_3_1)) + (portRef D (instanceRef RA_42_0_RNO_10)) + (portRef C (instanceRef S_RNII9DO1_1)) + (portRef B (instanceRef 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(portRef C (instanceRef wb_reqc_1_RNIRU4M1)) + (portRef A (instanceRef S_RNII9DO1_1)) + (portRef A (instanceRef DQML_0io_RNO_0)) + (portRef B (instanceRef S_RNII9DO1_0_1)) + (portRef A (instanceRef S_RNII9DO1_2_1)) + )) + (net (rename FS_0 "FS[0]") (joined + (portRef Q (instanceRef FS_0)) + (portRef A1 (instanceRef FS_cry_0_0)) + (portRef A (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0)) + (portRef A (instanceRef un1_LEDEN13_2_i_a2_0_0)) + (portRef A (instanceRef nCS_6_u_i_a2_4)) + (portRef B (instanceRef wb_cyc_stb_RNO_0)) + )) + (net (rename FS_8 "FS[8]") (joined + (portRef Q (instanceRef FS_8)) + (portRef A1 (instanceRef FS_cry_0_7)) + (portRef A (instanceRef wb_dati_7_0_a2_2_0)) + (portRef C (instanceRef FS_RNI6JJA_8)) + (portRef A (instanceRef wb_adr_7_0_o2_2_0)) + (portRef A (instanceRef wb_dati_7_0_a2_0_0_6)) + (portRef A (instanceRef wb_dati_7_0_a2_0_2_7)) + (portRef A (instanceRef wb_adr_7_0_1_0)) + (portRef A (instanceRef wb_adr_7_0_a2_2_0)) + (portRef A (instanceRef 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(instanceRef FS_RNIOD6E_0_8)) + (portRef D (instanceRef wb_dati_7_0_0_RNO_7)) + (portRef D (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0)) + (portRef A (instanceRef wb_adr_RNO_2_1)) + (portRef D (instanceRef FS_RNIOD6E_1_8)) + (portRef C (instanceRef wb_adr_RNO_3_1)) + (portRef D (instanceRef wb_dati_7_0_2_RNO_3)) + )) + (net (rename FS_11 "FS[11]") (joined + (portRef Q (instanceRef FS_11)) + (portRef A0 (instanceRef FS_cry_0_11)) + (portRef A (instanceRef FS_RNI6JJA_8)) + (portRef B (instanceRef wb_adr_7_0_o2_0)) + (portRef C (instanceRef wb_dati_7_0_a2_0_0_6)) + (portRef D (instanceRef wb_dati_7_0_a2_0_2_7)) + (portRef A (instanceRef wb_req_RNO_1)) + (portRef B (instanceRef wb_dati_7_0_a2_1_0_0)) + (portRef A (instanceRef wb_adr_RNO_0_1)) + (portRef C (instanceRef wb_dati_7_0_o2_1)) + (portRef A (instanceRef wb_adr_7_0_a2_0_0_0)) + (portRef A (instanceRef wb_adr_7_0_a2_1_0)) + (portRef B (instanceRef wb_dati_7_0_a2_5_4)) + (portRef C (instanceRef wb_dati_7_0_a2_3_4)) + (portRef C (instanceRef wb_adr_7_0_a2_0_0)) + (portRef A (instanceRef FS_RNIOD6E_8)) + (portRef D (instanceRef FS_RNIOD6E_0_8)) + (portRef B (instanceRef wb_we_RNO_3)) + (portRef C (instanceRef FS_RNIOD6E_1_8)) + (portRef C (instanceRef wb_dati_7_0_2_RNO_3)) + )) + (net (rename FS_12 "FS[12]") (joined + (portRef Q (instanceRef FS_12)) + (portRef A1 (instanceRef FS_cry_0_11)) + (portRef A (instanceRef wb_dati_7_0_a2_6_1)) + (portRef B (instanceRef wb_dati_7_0_a2_1_0)) + (portRef A (instanceRef FS_RNI9Q57_13)) + (portRef C (instanceRef wb_adr_7_0_a2_5_0_0)) + (portRef B (instanceRef wb_req_RNO_1)) + (portRef A (instanceRef wb_dati_7_0_a2_2_0_1)) + (portRef B (instanceRef wb_adr_RNO_0_1)) + (portRef B (instanceRef wb_we_RNO_4)) + (portRef B (instanceRef wb_adr_7_0_a2_0_0_0)) + (portRef A (instanceRef wb_dati_7_0_a2_1)) + (portRef B (instanceRef wb_adr_7_0_a2_1_0)) + (portRef B (instanceRef wb_dati_7_0_a2_6)) + (portRef B (instanceRef wb_dati_7_0_a2_7)) + (portRef A (instanceRef wb_dati_7_0_a2_4)) + (portRef A (instanceRef wb_dati_7_0_2_3)) + (portRef C (instanceRef wb_dati_7_0_a2_5_RNIC22J_4)) + (portRef A (instanceRef wb_we_RNO_1)) + (portRef D (instanceRef wb_we_RNO_3)) + (portRef C (instanceRef wb_dati_7_0_0_RNO_7)) + (portRef C (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0)) + (portRef B (instanceRef wb_adr_RNO_3_1)) + )) + (net (rename FS_13 "FS[13]") (joined + (portRef Q (instanceRef FS_13)) + (portRef A0 (instanceRef FS_cry_0_13)) + (portRef C (instanceRef wb_dati_7_0_a2_6_1)) + (portRef B (instanceRef FS_RNI9Q57_13)) + (portRef C (instanceRef wb_req_RNO_1)) + (portRef C (instanceRef wb_dati_7_0_a2_1_0_0)) + (portRef B (instanceRef wb_dati_7_0_a2_2_0_1)) + (portRef D (instanceRef wb_dati_7_0_o2_1)) + (portRef C (instanceRef wb_adr_7_0_a2_0_0_0)) + (portRef A (instanceRef CKE_6_iv_i_a2_3)) + (portRef A (instanceRef wb_we_RNO)) + (portRef C (instanceRef wb_dati_7_0_a2_7)) + (portRef A (instanceRef wb_adr_7_0_0)) + (portRef B (instanceRef wb_dati_7_0_a2_5_RNIC22J_4)) + (portRef A (instanceRef FS_RNIK5632_15)) + (portRef C (instanceRef wb_we_RNO_3)) + (portRef B (instanceRef wb_dati_7_0_0_RNO_7)) + (portRef A (instanceRef wb_adr_RNO_3_1)) + )) + (net (rename FS_15 "FS[15]") (joined + (portRef Q (instanceRef FS_15)) + (portRef A0 (instanceRef FS_s_0_15)) + (portRef B (instanceRef wb_dati_7_0_a2_2_0)) + (portRef C (instanceRef wb_dati_7_0_a2_5_1)) + (portRef B (instanceRef wb_rst8_0_a2)) + (portRef A (instanceRef nCS_6_u_i_a2_1_0)) + (portRef A (instanceRef un1_wb_adr_0_sqmuxa_2_0_1_0)) + (portRef B (instanceRef CKE_6_iv_i_0)) + (portRef C (instanceRef nCS_6_u_i_a2_4_RNI3A062)) + (portRef B (instanceRef FS_RNIK5632_15)) + (portRef A (instanceRef wb_req_RNO_0)) + (portRef A (instanceRef FS_RNI5OOF1_15)) + )) + (net PHI1reg (joined + (portRef Q (instanceRef PHI1reg_0io)) + (portRef B (instanceRef SZ0Z_1)) + )) + (net (rename FS_14 "FS[14]") (joined + (portRef Q (instanceRef FS_14)) + (portRef A1 (instanceRef FS_cry_0_13)) + (portRef D (instanceRef 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FS_RNI9FGA_1)) + )) + (net (rename FS_1 "FS[1]") (joined + (portRef Q (instanceRef FS_1)) + (portRef A0 (instanceRef FS_cry_0_1)) + (portRef D (instanceRef un1_nCS61_1_0_a2_0)) + (portRef B (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0)) + (portRef C (instanceRef FS_RNI9FGA_1)) + )) + (net (rename FS_3 "FS[3]") (joined + (portRef Q (instanceRef FS_3)) + (portRef A0 (instanceRef FS_cry_0_3)) + (portRef B (instanceRef un1_nCS61_1_0_a2_0)) + (portRef A (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4)) + (portRef A (instanceRef FS_RNI9FGA_1)) + )) + (net (rename FS_7 "FS[7]") (joined + (portRef Q (instanceRef FS_7)) + (portRef A0 (instanceRef FS_cry_0_7)) + (portRef B (instanceRef un1_LEDEN13_2_i_o2_2_0)) + (portRef B (instanceRef Ready_0_sqmuxa_0_a2_6_a2)) + (portRef C (instanceRef nCS_6_u_i_a2_4)) + )) + (net (rename FS_5 "FS[5]") (joined + (portRef Q (instanceRef FS_5)) + (portRef A0 (instanceRef FS_cry_0_5)) + (portRef B (instanceRef nCS_6_u_i_o2)) + (portRef A (instanceRef un1_nCS61_1_0_a2_0)) + (portRef B (instanceRef nCS_6_u_i_o2_0)) + (portRef B (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4)) + )) + (net (rename FS_4 "FS[4]") (joined + (portRef Q (instanceRef FS_4)) + (portRef A1 (instanceRef FS_cry_0_3)) + (portRef D (instanceRef nCS_6_u_i_o2)) + (portRef A (instanceRef nCS_6_u_i_o2_0)) + (portRef D (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0)) + (portRef A (instanceRef nCAS_s_i_o2)) + (portRef A (instanceRef nRWE_r_0_RNO)) + )) + (net (rename RWBank_6 "RWBank[6]") (joined + (portRef Q (instanceRef RWBank_6)) + (portRef C (instanceRef DQML_0io_RNO)) + (portRef A (instanceRef DQMH_0io_RNO)) + )) + (net (rename RWMask_0 "RWMask[0]") (joined + (portRef Q (instanceRef RWMask_0)) + (portRef C (instanceRef RWBank_5_0_0)) + )) + (net (rename RWMask_1 "RWMask[1]") (joined + (portRef Q (instanceRef RWMask_1)) + (portRef C (instanceRef RWBank_5_0_1)) + )) + (net (rename RWMask_2 "RWMask[2]") (joined + (portRef Q (instanceRef RWMask_2)) + (portRef C (instanceRef RWBank_5_0_2)) + )) + (net (rename RWMask_3 "RWMask[3]") (joined + (portRef Q (instanceRef RWMask_3)) + (portRef C (instanceRef RWBank_5_0_3)) + )) + (net (rename RWMask_4 "RWMask[4]") (joined + (portRef Q (instanceRef RWMask_4)) + (portRef C (instanceRef RWBank_5_0_4)) + )) + (net (rename RWMask_5 "RWMask[5]") (joined + (portRef Q (instanceRef RWMask_5)) + (portRef C (instanceRef RWBank_5_0_5)) + )) + (net (rename RWMask_6 "RWMask[6]") (joined + (portRef Q (instanceRef RWMask_6)) + (portRef C (instanceRef RWBank_5_0_6)) + )) + (net (rename CS_0 "CS[0]") (joined + (portRef Q (instanceRef CS_0)) + (portRef D (instanceRef CS_RNO_1)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_10)) + (portRef A (instanceRef CS_RNO_0_2)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_1)) + (portRef A (instanceRef CS_RNO_0)) + )) + (net (rename CS_1 "CS[1]") (joined + (portRef Q (instanceRef CS_1)) + (portRef A (instanceRef CS_RNO_1)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_15)) + (portRef A (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_1)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_4)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_0)) + (portRef A (instanceRef CS_RNO_2)) + )) + (net (rename CS_2 "CS[2]") (joined + (portRef Q (instanceRef CS_2)) + (portRef B (instanceRef CmdSetRWBankFFLED_4_u_0_0_a2_1)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_o2_0)) + (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2)) + (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4)) + (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_4)) + (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_0)) + (portRef B (instanceRef CS_RNO_2)) + )) + (net CmdExecMXO2 (joined + (portRef Q (instanceRef CmdExecMXO2)) + (portRef B (instanceRef un1_LEDEN13_2_i_a2_0)) + (portRef A (instanceRef wb_we_RNO_0)) + (portRef A (instanceRef wb_cyc_stb_RNO)) + (portRef A (instanceRef CmdExecMXO2_4_u_0_0_0)) + )) + (net DOEEN (joined + (portRef Q (instanceRef DOEEN)) + (portRef A (instanceRef nDOE_pad_RNO)) + )) + (net LEDEN (joined + (portRef Q (instanceRef LEDEN)) + (portRef D (instanceRef RWBank_5_0_o2_0)) + (portRef A (instanceRef LED_pad_RNO)) + )) + (net CmdLEDGet (joined + (portRef Q (instanceRef CmdLEDGet)) + (portRef A (instanceRef RWBank_5_0_o2_0)) + (portRef A (instanceRef CmdLEDGet_4_u_0_0_0)) + )) + (net CO0_1 (joined + (portRef Q (instanceRef CmdTout_0)) + (portRef A (instanceRef CmdTout_3_0_a2_0)) + (portRef A (instanceRef un1_CS_0_sqmuxa_0_0_a2_5)) + (portRef A (instanceRef CmdTout_RNO_1)) + (portRef C (instanceRef CmdTout_RNO_2)) + )) + (net (rename CmdTout_1 "CmdTout[1]") (joined + (portRef Q (instanceRef CmdTout_1)) + (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_a2_5)) + (portRef B (instanceRef CmdTout_RNO_1)) + (portRef B (instanceRef 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(portRef Q (instanceRef RWMask_7)) + (portRef C (instanceRef RWBank_5_0_0_7)) + )) + (net Vout3 (joined + (portRef Z (instanceRef Vout3_0_a2)) + (portRef SP (instanceRef Vout_0io_7)) + (portRef SP (instanceRef Vout_0io_6)) + (portRef SP (instanceRef Vout_0io_5)) + (portRef SP (instanceRef Vout_0io_4)) + (portRef SP (instanceRef Vout_0io_3)) + (portRef SP (instanceRef Vout_0io_2)) + (portRef SP (instanceRef Vout_0io_1)) + (portRef SP (instanceRef Vout_0io_0)) + (portRef A (instanceRef nCAS_0io_RNO_0)) + )) + (net CmdSetRWBankFFLED (joined + (portRef Q (instanceRef CmdSetRWBankFFLED)) + (portRef B (instanceRef RWBank_5_0_o2_0)) + (portRef A (instanceRef CmdSetRWBankFFLED_4_u_0_0_0)) + )) + (net CmdSetRWBankFFMXO2 (joined + (portRef Q (instanceRef CmdSetRWBankFFMXO2)) + (portRef C (instanceRef RWBank_5_0_o2_0)) + (portRef A (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0)) + )) + (net wb_req (joined + (portRef Q (instanceRef wb_req)) + (portRef D (instanceRef un1_LEDEN13_2_i_a2_0_0)) + )) + (net LEDEN13 (joined + (portRef Z (instanceRef wb_reqc_1_RNIRU4M1)) + (portRef B (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0)) + (portRef B (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0)) + (portRef SP (instanceRef RWBank_7)) + (portRef SP (instanceRef RWBank_6)) + (portRef SP (instanceRef RWBank_5)) + (portRef SP (instanceRef RWBank_4)) + (portRef SP (instanceRef RWBank_3)) + (portRef SP (instanceRef RWBank_2)) + (portRef SP (instanceRef RWBank_1)) + (portRef SP (instanceRef RWBank_0)) + )) + (net (rename RWBank_5_0 "RWBank_5[0]") (joined + (portRef Z (instanceRef RWBank_5_0_0)) + (portRef D (instanceRef RWBank_0)) + )) + (net (rename RWBank_5_1 "RWBank_5[1]") (joined + (portRef Z (instanceRef RWBank_5_0_1)) + (portRef D (instanceRef RWBank_1)) + )) + (net (rename RWBank_5_2 "RWBank_5[2]") (joined + (portRef Z (instanceRef RWBank_5_0_2)) + (portRef D (instanceRef RWBank_2)) + )) + (net (rename RWBank_5_3 "RWBank_5[3]") (joined + (portRef Z (instanceRef RWBank_5_0_3)) + (portRef D (instanceRef RWBank_3)) + )) + (net (rename RWBank_5_5 "RWBank_5[5]") (joined + (portRef Z (instanceRef RWBank_5_0_5)) + (portRef D (instanceRef RWBank_5)) + )) + (net (rename RWBank_5_6 "RWBank_5[6]") (joined + (portRef Z (instanceRef RWBank_5_0_6)) + (portRef D (instanceRef RWBank_6)) + )) + (net (rename RWBank_5_7 "RWBank_5[7]") (joined + (portRef Z (instanceRef RWBank_5_0_0_7)) + (portRef D (instanceRef RWBank_7)) + )) + (net (rename RWBank_0 "RWBank[0]") (joined + (portRef Q (instanceRef RWBank_0)) + (portRef B (instanceRef RA_0io_RNO_8)) + )) + (net (rename RWBank_1 "RWBank[1]") (joined + (portRef Q (instanceRef RWBank_1)) + (portRef A (instanceRef RA_0io_RNO_9)) + )) + (net (rename RWBank_2 "RWBank[2]") (joined + (portRef Q (instanceRef RWBank_2)) + (portRef C (instanceRef RA_42_0_10)) + )) + (net (rename RWBank_3 "RWBank[3]") (joined + (portRef Q (instanceRef RWBank_3)) + (portRef A (instanceRef RA_0io_RNO_11)) + )) + (net (rename RWBank_4 "RWBank[4]") (joined + (portRef Q (instanceRef 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wb_reqc_1 (joined + (portRef Z (instanceRef wb_reqc_1)) + (portRef D (instanceRef RA_0io_RNO_11)) + (portRef D (instanceRef CKE_6_iv_i_0_1)) + (portRef D (instanceRef wb_req_RNO)) + (portRef D (instanceRef S_RNO_1)) + (portRef D (instanceRef RA_0io_RNO_9)) + (portRef D (instanceRef CmdBitbangMXO2_RNI8CSO1)) + (portRef D (instanceRef wb_we_RNO_0)) + (portRef A (instanceRef wb_reqc_1_RNIEO5C1)) + (portRef B (instanceRef wb_req_RNO_0)) + (portRef B (instanceRef FS_RNI5OOF1_15)) + (portRef D (instanceRef wb_reqc_1_RNIRU4M1)) + )) + (net CKE_6_iv_i_a2_0 (joined + (portRef Z (instanceRef CKE_6_iv_i_0_1_RNO)) + (portRef A (instanceRef CKE_6_iv_i_0_1)) + )) + (net wb_adr_7_5_214_a2_2_0 (joined + (portRef Z (instanceRef wb_adr_RNO_3_1)) + (portRef D (instanceRef wb_adr_RNO_1_1)) + )) + (net DQML_s_i_a2_0 (joined + (portRef Z (instanceRef DQML_0io_RNO_0)) + (portRef A (instanceRef DQML_0io_RNO)) + )) + (net un1_CS_0_sqmuxa_0_0_a2_2_2 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_2)) + (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4)) + )) + (net un1_CS_0_sqmuxa_0_0_a2_2_4 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_2_4)) + (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_2)) + )) + (net un1_CS_0_sqmuxa_0_0_a2_1_2 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_2)) + (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4)) + )) + (net un1_CS_0_sqmuxa_0_0_a2_1_4 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_4)) + (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_1)) + )) + (net (rename S_s_0_1_0 "S_s_0_1[0]") (joined + (portRef Z (instanceRef S_s_0_1_0)) + (portRef D (instanceRef S_s_0_0)) + )) + (net un1_CS_0_sqmuxa_0_0_a2_1 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_1_6)) + (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_2)) + )) + (net un1_CS_0_sqmuxa_0_0_a2_3_0 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_0)) + (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2)) + )) + (net un1_CS_0_sqmuxa_0_0_a2_3_2 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_3_2)) + (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F)) + )) + (net un1_CS_0_sqmuxa_0_0_a2_4_2 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_2)) + (portRef D (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4)) + )) + (net un1_CS_0_sqmuxa_0_0_a2_4_4 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_a2_4_4)) + (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_a2_4)) + )) + (net CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0 (joined + (portRef Z (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0)) + (portRef B (instanceRef CmdSetRWBankFFMXO2_4_u_0_0_0)) + )) + (net wb_adr_7_5_214_0_1 (joined + (portRef Z (instanceRef wb_adr_RNO_1_1)) + (portRef D (instanceRef wb_adr_RNO_1)) + )) + (net CmdLEDGet_4_u_0_0_a2_0_2 (joined + (portRef Z (instanceRef CmdLEDGet_4_u_0_0_a2_0_2)) + (portRef B (instanceRef CmdLEDGet_4_u_0_0_0)) + )) + (net wb_we_7_iv_0_0_0_1 (joined + (portRef Z (instanceRef wb_we_RNO_2)) + (portRef D (instanceRef wb_we_RNO)) + )) + (net (rename wb_adr_7_0_a2_5_0_0 "wb_adr_7_0_a2_5_0[0]") (joined + (portRef Z (instanceRef wb_adr_7_0_a2_5_0_0)) + (portRef D (instanceRef wb_adr_7_0_1_0)) + )) + (net (rename wb_adr_7_0_a2_0_0 "wb_adr_7_0_a2_0[0]") (joined + (portRef Z (instanceRef wb_adr_7_0_a2_0_0_0)) + (portRef D (instanceRef wb_adr_7_0_0_0)) + )) + (net (rename wb_dati_7_0_a2_4_0_7 "wb_dati_7_0_a2_4_0[7]") (joined + (portRef Z (instanceRef wb_dati_7_0_0_RNO_7)) + (portRef D (instanceRef wb_dati_7_0_0_7)) + )) + (net (rename wb_dati_7_0_a2_2_0_1 "wb_dati_7_0_a2_2_0[1]") (joined + (portRef Z (instanceRef wb_dati_7_0_a2_2_0_1)) + (portRef D (instanceRef wb_dati_7_0_0_1)) + )) + (net CmdBitbangMXO2_4_u_0_0_a2_0_1 (joined + (portRef Z (instanceRef CmdBitbangMXO2_4_u_0_0_a2_0_1)) + (portRef B (instanceRef CmdBitbangMXO2_4_u_0_0_0)) + )) + (net CKE_6_iv_i_0_1 (joined + (portRef Z (instanceRef CKE_6_iv_i_0_1)) + (portRef A (instanceRef CKE_6_iv_i_0)) + )) + (net (rename un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0 "un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0]") (joined + (portRef Z (instanceRef un1_LEDEN_0_sqmuxa_1_i_a2_0_1_0)) + (portRef D (instanceRef un1_LEDEN_0_sqmuxa_1_i_0_0)) + )) + (net (rename wb_dati_7_0_a2_1_0 "wb_dati_7_0_a2_1[0]") (joined + (portRef Z (instanceRef wb_dati_7_0_a2_1_0_0)) + (portRef D (instanceRef wb_dati_7_0_0)) + )) + (net (rename un1_RWMask_0_sqmuxa_1_i_a2_0_1_0 "un1_RWMask_0_sqmuxa_1_i_a2_0_1[0]") (joined + (portRef Z (instanceRef un1_RWMask_0_sqmuxa_1_i_0_RNO_0)) + (portRef D (instanceRef un1_RWMask_0_sqmuxa_1_i_0_0)) + )) + (net Ready_0_sqmuxa_0_a2_6_a2_2 (joined + (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_6_a2_2_0)) + (portRef D (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4)) + )) + (net Ready_0_sqmuxa_0_a2_6_a2_4 (joined + (portRef Z (instanceRef Ready_0_sqmuxa_0_a2_6_a2_4)) + (portRef D (instanceRef Ready_0_sqmuxa_0_a2_6_a2)) + )) + (net nCS_6_u_i_a2_1 (joined + (portRef Z (instanceRef nCS_6_u_i_a2_1_0)) + (portRef D (instanceRef nCS_6_u_i_1)) + )) + (net (rename wb_dati_7_0_a2_2_1_3 "wb_dati_7_0_a2_2_1[3]") (joined + (portRef Z (instanceRef wb_dati_7_0_2_RNO_3)) + (portRef D (instanceRef wb_dati_7_0_2_3)) + )) + (net un1_CS_0_sqmuxa_0_0_0 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_0)) + (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_2)) + )) + (net un1_CS_0_sqmuxa_0_0_2 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_2)) + (portRef B (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F)) + )) + (net un1_CS_0_sqmuxa_0_0_3 (joined + (portRef Z (instanceRef un1_CS_0_sqmuxa_0_0_3)) + (portRef C (instanceRef un1_CS_0_sqmuxa_0_0_2_RNIQS7F)) + )) + (net (rename wb_dati_7_0_0_1 "wb_dati_7_0_0[1]") (joined + (portRef Z (instanceRef wb_dati_7_0_0_1)) + (portRef D (instanceRef wb_dati_7_0_1)) + )) + (net (rename wb_dati_7_0_o2_0_2 "wb_dati_7_0_o2_0[2]") (joined + (portRef Z (instanceRef wb_dati_7_0_o2_0_2)) + (portRef D (instanceRef wb_dati_7_0_2)) + (portRef D (instanceRef wb_dati_7_0_5)) + )) + (net nCAS_s_i_tz_0 (joined + (portRef Z (instanceRef nCAS_0io_RNO_0)) + (portRef D (instanceRef nCAS_0io_RNO)) + )) + (net (rename wb_dati_7_0_1_6 "wb_dati_7_0_1[6]") (joined + (portRef Z (instanceRef wb_dati_7_0_1_6)) + (portRef C (instanceRef wb_dati_7_0_6)) + )) + (net (rename wb_dati_7_0_0_7 "wb_dati_7_0_0[7]") (joined + (portRef Z (instanceRef wb_dati_7_0_0_7)) + (portRef D (instanceRef wb_dati_7_0_7)) + )) + (net (rename wb_dati_7_0_0_3 "wb_dati_7_0_0[3]") (joined + (portRef Z (instanceRef wb_dati_7_0_0_3)) + (portRef B (instanceRef wb_dati_7_0_3)) + )) + (net (rename wb_dati_7_0_2_3 "wb_dati_7_0_2[3]") (joined + (portRef Z (instanceRef wb_dati_7_0_2_3)) + (portRef C (instanceRef wb_dati_7_0_3)) + )) + (net nCS_6_u_i_0 (joined + (portRef Z (instanceRef nCS_6_u_i_0)) + (portRef B (instanceRef nCS_0io_RNO)) + )) + (net (rename wb_adr_7_0_0_0 "wb_adr_7_0_0[0]") (joined + (portRef Z (instanceRef wb_adr_7_0_0_0)) + (portRef C (instanceRef wb_adr_7_0_4_0)) + )) + (net (rename wb_adr_7_0_1_0 "wb_adr_7_0_1[0]") (joined + (portRef Z (instanceRef wb_adr_7_0_1_0)) + (portRef D (instanceRef wb_adr_7_0_4_0)) + )) + (net (rename wb_adr_7_0_4_0 "wb_adr_7_0_4[0]") (joined + (portRef Z (instanceRef wb_adr_7_0_4_0)) + (portRef D (instanceRef wb_adr_7_0_0)) + )) + (net (rename wb_dati_7_0_0_4 "wb_dati_7_0_0[4]") (joined + (portRef Z (instanceRef wb_dati_7_0_0_4)) + (portRef D (instanceRef wb_dati_7_0_4)) + )) + (net (rename FS_cry_0_S0_0 "FS_cry_0_S0[0]") (joined + (portRef S0 (instanceRef FS_cry_0_0)) + )) + (net (rename FS_s_0_S1_15 "FS_s_0_S1[15]") (joined + (portRef S1 (instanceRef FS_s_0_15)) + )) + (net (rename FS_s_0_COUT_15 "FS_s_0_COUT[15]") (joined + (portRef COUT (instanceRef FS_s_0_15)) + )) + (net (rename Dout_0__CN "Dout_0_.CN") (joined + (portRef Z (instanceRef Vout_0__CN)) + (portRef SCLK (instanceRef Dout_0io_7)) + (portRef SCLK (instanceRef Dout_0io_6)) + (portRef SCLK (instanceRef Dout_0io_5)) + (portRef SCLK (instanceRef Dout_0io_4)) + (portRef SCLK (instanceRef Dout_0io_3)) + (portRef SCLK (instanceRef Dout_0io_2)) + (portRef SCLK (instanceRef Dout_0io_1)) + (portRef SCLK (instanceRef Dout_0io_0)) + (portRef SCLK (instanceRef Vout_0io_7)) + (portRef SCLK (instanceRef Vout_0io_6)) + (portRef SCLK (instanceRef Vout_0io_5)) + (portRef SCLK (instanceRef Vout_0io_4)) + (portRef SCLK (instanceRef Vout_0io_3)) + (portRef SCLK (instanceRef Vout_0io_2)) + (portRef SCLK (instanceRef Vout_0io_1)) + (portRef SCLK (instanceRef Vout_0io_0)) + )) + (net VCC (joined + (portRef Z (instanceRef VCC)) + (portRef B0 (instanceRef FS_cry_0_0)) + (portRef SP (instanceRef BA_0io_1)) + (portRef SP (instanceRef BA_0io_0)) + (portRef SP (instanceRef CKE_0io)) + (portRef SP (instanceRef DQMH_0io)) + (portRef SP (instanceRef DQML_0io)) + (portRef SP (instanceRef RA_0io_11)) + (portRef SP (instanceRef RA_0io_10)) + (portRef SP (instanceRef RA_0io_9)) + (portRef SP (instanceRef RA_0io_8)) + (portRef SP (instanceRef nCAS_0io)) + (portRef SP (instanceRef nCS_0io)) + (portRef SP (instanceRef nRAS_0io)) + (portRef SP (instanceRef nRWE_0io)) + (portRef SP (instanceRef PHI1reg_0io)) + (portRef GSR (instanceRef GSR_INST)) + )) + (net GND (joined + (portRef Z (instanceRef GND)) + (portRef D1 (instanceRef FS_cry_0_0)) + (portRef C1 (instanceRef FS_cry_0_0)) + (portRef B1 (instanceRef FS_cry_0_0)) + (portRef D0 (instanceRef FS_cry_0_0)) + (portRef C0 (instanceRef FS_cry_0_0)) + (portRef A0 (instanceRef FS_cry_0_0)) + (portRef D1 (instanceRef FS_cry_0_1)) + (portRef C1 (instanceRef FS_cry_0_1)) + (portRef B1 (instanceRef FS_cry_0_1)) + (portRef D0 (instanceRef FS_cry_0_1)) + (portRef C0 (instanceRef FS_cry_0_1)) + (portRef B0 (instanceRef FS_cry_0_1)) + (portRef D1 (instanceRef FS_cry_0_3)) + (portRef C1 (instanceRef FS_cry_0_3)) + (portRef B1 (instanceRef FS_cry_0_3)) + (portRef D0 (instanceRef FS_cry_0_3)) + (portRef C0 (instanceRef FS_cry_0_3)) + (portRef B0 (instanceRef FS_cry_0_3)) + (portRef D1 (instanceRef FS_cry_0_5)) + (portRef C1 (instanceRef FS_cry_0_5)) + (portRef B1 (instanceRef FS_cry_0_5)) + (portRef D0 (instanceRef FS_cry_0_5)) + (portRef C0 (instanceRef FS_cry_0_5)) + (portRef B0 (instanceRef FS_cry_0_5)) + (portRef D1 (instanceRef FS_cry_0_7)) + (portRef C1 (instanceRef FS_cry_0_7)) + (portRef B1 (instanceRef FS_cry_0_7)) + (portRef D0 (instanceRef FS_cry_0_7)) + (portRef C0 (instanceRef FS_cry_0_7)) + (portRef B0 (instanceRef FS_cry_0_7)) + (portRef D1 (instanceRef FS_cry_0_9)) + (portRef C1 (instanceRef FS_cry_0_9)) + (portRef B1 (instanceRef FS_cry_0_9)) + (portRef D0 (instanceRef FS_cry_0_9)) + (portRef C0 (instanceRef FS_cry_0_9)) + (portRef B0 (instanceRef FS_cry_0_9)) + (portRef D1 (instanceRef FS_cry_0_11)) + (portRef C1 (instanceRef FS_cry_0_11)) + (portRef B1 (instanceRef FS_cry_0_11)) + (portRef D0 (instanceRef FS_cry_0_11)) + (portRef C0 (instanceRef FS_cry_0_11)) + (portRef B0 (instanceRef FS_cry_0_11)) + (portRef D1 (instanceRef FS_cry_0_13)) + (portRef C1 (instanceRef FS_cry_0_13)) + (portRef B1 (instanceRef FS_cry_0_13)) + (portRef D0 (instanceRef FS_cry_0_13)) + (portRef C0 (instanceRef FS_cry_0_13)) + (portRef B0 (instanceRef FS_cry_0_13)) + (portRef D1 (instanceRef FS_s_0_15)) + (portRef C1 (instanceRef FS_s_0_15)) + (portRef B1 (instanceRef FS_s_0_15)) + (portRef A1 (instanceRef FS_s_0_15)) + (portRef D0 (instanceRef FS_s_0_15)) + (portRef C0 (instanceRef FS_s_0_15)) + (portRef B0 (instanceRef FS_s_0_15)) + (portRef CD (instanceRef CKE_0io)) + (portRef PD (instanceRef DQMH_0io)) + (portRef PD (instanceRef DQML_0io)) + (portRef CD (instanceRef Dout_0io_7)) + (portRef CD (instanceRef Dout_0io_6)) + (portRef CD (instanceRef Dout_0io_5)) + (portRef CD (instanceRef Dout_0io_4)) + (portRef CD (instanceRef Dout_0io_3)) + (portRef CD (instanceRef Dout_0io_2)) + (portRef CD (instanceRef Dout_0io_1)) + (portRef CD (instanceRef Dout_0io_0)) + (portRef CD (instanceRef RA_0io_11)) + (portRef CD (instanceRef RA_0io_10)) + (portRef CD (instanceRef RA_0io_9)) + (portRef CD (instanceRef RA_0io_8)) + (portRef CD (instanceRef RA_0io_7)) + (portRef CD (instanceRef RA_0io_6)) + (portRef CD (instanceRef RA_0io_5)) + (portRef CD (instanceRef RA_0io_4)) + (portRef CD (instanceRef RA_0io_2)) + (portRef CD (instanceRef RA_0io_1)) + (portRef CD (instanceRef Vout_0io_7)) + (portRef CD (instanceRef Vout_0io_6)) + (portRef CD (instanceRef Vout_0io_5)) + (portRef CD (instanceRef Vout_0io_4)) + (portRef CD (instanceRef Vout_0io_3)) + (portRef CD (instanceRef Vout_0io_2)) + (portRef CD (instanceRef Vout_0io_1)) + (portRef CD (instanceRef Vout_0io_0)) + (portRef PD (instanceRef nCAS_0io)) + (portRef PD (instanceRef nCS_0io)) + (portRef PD (instanceRef nRAS_0io)) + (portRef PD (instanceRef nRWE_0io)) + (portRef CD (instanceRef PHI1reg_0io)) + )) + (net C14M_c (joined + (portRef O (instanceRef C14M_pad)) + (portRef C14M_c (instanceRef ufmefb)) + (portRef CK (instanceRef CS_2)) + (portRef CK (instanceRef CS_1)) + (portRef CK (instanceRef CS_0)) + (portRef CK (instanceRef CmdBitbangMXO2)) + (portRef CK (instanceRef CmdExecMXO2)) + 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a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.jed b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.jed new file mode 100644 index 0000000..12342e4 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.jed @@ -0,0 +1,1441 @@ +* +NOTE Diamond (64-bit) 3.12.1.454 JEDEC Compatible Fuse File.* +NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation.* +NOTE All Rights Reserved.* +NOTE DATE CREATED: Thu Sep 21 05:35:21 2023* +NOTE DESIGN NAME: RAM2E_LCMXO2_640HC_impl1.ncd* +NOTE DEVICE NAME: LCMXO2-640HC-4TQFP100* +NOTE JEDEC FILE STATUS: Final Version 1.95* +NOTE PIN ASSIGNMENTS* +NOTE PINS RD[0] : 36 : inout* +NOTE PINS LED : 35 : out* +NOTE PINS C14M : 62 : in* +NOTE PINS DQMH : 49 : out* +NOTE PINS DQML : 48 : out* +NOTE PINS RD[7] : 43 : inout* +NOTE PINS RD[6] : 42 : inout* +NOTE PINS RD[5] : 41 : inout* +NOTE PINS RD[4] : 40 : inout* +NOTE PINS RD[3] : 39 : inout* +NOTE PINS RD[2] : 38 : inout* +NOTE PINS RD[1] : 37 : inout* +NOTE PINS RA[11] : 59 : out* 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+00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +* +NOTE TAG DATA* +L171648 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +* +C91ED* +NOTE FEATURE_ROW* +E0000000000000000000000000000000000000000000000000000000000000000 +0000010001100000* +NOTE User Electronic Signature Data* +UH00000000* +362B diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.mrp b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.mrp new file mode 100644 index 0000000..9c54f98 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.mrp @@ -0,0 +1,468 @@ + + Lattice Mapping Report File for Design Module 'RAM2E' + + +Design Information +------------------ + +Command line: map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial + RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr + RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC + loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify. + lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset + //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml +Target Vendor: LATTICE +Target Device: LCMXO2-640HCTQFP100 +Target Performance: 4 +Mapper: xo2c00, version: Diamond (64-bit) 3.12.1.454 +Mapped on: 09/21/23 05:34:46 + +Design Summary +-------------- + + Number of registers: 111 out of 877 (13%) + PFU registers: 75 out of 640 (12%) + PIO registers: 36 out of 237 (15%) + Number of SLICEs: 120 out of 320 (38%) + SLICEs as Logic/ROM: 120 out of 320 (38%) + SLICEs as RAM: 0 out of 240 (0%) + SLICEs as Carry: 9 out of 320 (3%) + Number of LUT4s: 239 out of 640 (37%) + Number used as logic LUTs: 221 + Number used as distributed RAM: 0 + Number used as ripple logic: 18 + Number used as shift registers: 0 + Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%) + Number of block RAMs: 0 out of 2 (0%) + Number of GSRs: 0 out of 1 (0%) + EFB used : Yes + JTAG used : No + Readback used : No + Oscillator used : No + Startup used : No + POR : On + Bandgap : On + Number of Power Controller: 0 out of 1 (0%) + Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) + Number of DCCA: 0 out of 8 (0%) + Number of DCMA: 0 out of 2 (0%) + Notes:- + 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of + distributed RAMs) + 2*(Number of ripple logic) + 2. Number of logic LUT4s does not include count of distributed RAM and + ripple logic. + Number of clocks: 1 + Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M ) + Number of Clock Enables: 11 + Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs + Net N_576_i: 17 loads, 9 LSLICEs + Net LEDEN13: 4 loads, 4 LSLICEs + Net nCS61: 1 loads, 1 LSLICEs + Net Vout3: 8 loads, 0 LSLICEs + Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs + + Page 1 + + + + +Design: RAM2E Date: 09/21/23 05:34:46 + +Design Summary (cont) +--------------------- + Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs + Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs + Net N_104: 1 loads, 1 LSLICEs + Net N_88: 4 loads, 4 LSLICEs + Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs + Number of LSRs: 5 + Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs + Net S[2]: 1 loads, 1 LSLICEs + Net N_566_i: 2 loads, 0 LSLICEs + Net wb_rst: 1 loads, 0 LSLICEs + Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs + Number of nets driven by tri-state buffers: 0 + Top 10 highest fanout non-clock nets: + Net S[2]: 48 loads + Net S[3]: 48 loads + Net S[0]: 30 loads + Net FS[12]: 22 loads + Net FS[9]: 21 loads + Net S[1]: 21 loads + Net FS[10]: 20 loads + Net FS[11]: 19 loads + Net RWSel: 19 loads + Net FS[13]: 17 loads + + + + + Number of warnings: 1 + Number of errors: 0 + + +Design Errors/Warnings +---------------------- + +WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will + temporarily disable certain features of the device including Power + Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port. + Functionality is restored after the Flash Memory (UFM/Configuration) + Interface is disabled using Disable Configuration Interface command 0x26 + followed by Bypass command 0xFF. + +IO (PIO) Attributes +------------------- + ++---------------------+-----------+-----------+------------+ +| IO Name | Direction | Levelmode | IO | +| | | IO_TYPE | Register | ++---------------------+-----------+-----------+------------+ +| RD[0] | BIDIR | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| LED | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| C14M | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| DQMH | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ + + Page 2 + + + + +Design: RAM2E Date: 09/21/23 05:34:46 + +IO (PIO) Attributes (cont) +-------------------------- +| DQML | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RD[7] | BIDIR | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RD[6] | BIDIR | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RD[5] | BIDIR | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RD[4] | BIDIR | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RD[3] | BIDIR | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RD[2] | BIDIR | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RD[1] | BIDIR | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[11] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[10] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[9] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[8] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[7] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[6] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[5] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[4] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[3] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| RA[2] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[1] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| RA[0] | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| BA[1] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| BA[0] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| nRWE | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| nCAS | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| nRAS | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| nCS | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| CKE | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| nVOE | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ + + Page 3 + + + + +Design: RAM2E Date: 09/21/23 05:34:46 + +IO (PIO) Attributes (cont) +-------------------------- +| Vout[7] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Vout[6] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Vout[5] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Vout[4] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Vout[3] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Vout[2] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Vout[1] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Vout[0] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| nDOE | OUTPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Dout[7] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Dout[6] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Dout[5] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Dout[4] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Dout[3] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Dout[2] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Dout[1] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Dout[0] | OUTPUT | LVCMOS33 | OUT | ++---------------------+-----------+-----------+------------+ +| Din[7] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Din[6] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Din[5] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Din[4] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Din[3] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Din[2] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Din[1] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Din[0] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Ain[7] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Ain[6] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Ain[5] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ + + Page 4 + + + + +Design: RAM2E Date: 09/21/23 05:34:46 + +IO (PIO) Attributes (cont) +-------------------------- +| Ain[4] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Ain[3] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Ain[2] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Ain[1] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| Ain[0] | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nC07X | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nEN80 | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nWE80 | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| nWE | INPUT | LVCMOS33 | | ++---------------------+-----------+-----------+------------+ +| PHI1 | INPUT | LVCMOS33 | IN | ++---------------------+-----------+-----------+------------+ + +Removed logic +------------- + +Block GSR_INST undriven or does not drive anything - clipped. +Signal Dout_0_.CN was merged into signal C14M_c +Signal GND undriven or does not drive anything - clipped. +Signal ufmefb/VCC undriven or does not drive anything - clipped. +Signal ufmefb/GND undriven or does not drive anything - clipped. +Signal FS_s_0_S1[15] undriven or does not drive anything - clipped. +Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped. +Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped. +Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped. +Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped. +Signal ufmefb/TCOC undriven or does not drive anything - clipped. +Signal ufmefb/TCINT undriven or does not drive anything - clipped. +Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped. +Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped. +Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped. +Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped. +Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped. +Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped. +Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped. +Signal ufmefb/SPISCKO undriven or does not drive anything - clipped. +Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped. +Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped. +Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped. + + Page 5 + + + + +Design: RAM2E Date: 09/21/23 05:34:46 + +Removed logic (cont) +-------------------- +Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped. +Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped. +Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped. +Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped. +Signal ufmefb/PLLWEO undriven or does not drive anything - clipped. +Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped. +Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped. +Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped. +Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped. +Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped. +Signal N_1 undriven or does not drive anything - clipped. +Block Vout_0_.CN was optimized away. +Block GND was optimized away. +Block ufmefb/VCC was optimized away. +Block ufmefb/GND was optimized away. + + + +Embedded Functional Block Connection Summary +-------------------------------------------- + + Desired WISHBONE clock frequency: 14.4 MHz + Clock source: C14M_c + Reset source: wb_rst + Functions mode: + I2C #1 (Primary) Function: DISABLED + I2C #2 (Secondary) Function: DISABLED + SPI Function: DISABLED + Timer/Counter Function: DISABLED + Timer/Counter Mode: WB + UFM Connection: ENABLED + PLL0 Connection: DISABLED + PLL1 Connection: DISABLED + I2C Function Summary: + -------------------- + None + SPI Function Summary: + -------------------- + None + Timer/Counter Function Summary: + ------------------------------ + + Page 6 + + + + +Design: RAM2E Date: 09/21/23 05:34:46 + +Embedded Functional Block Connection Summary (cont) +--------------------------------------------------- + None + UFM Function Summary: + -------------------- + UFM Utilization: General Purpose Flash Memory + Initialized UFM Pages: 1 Pages (1*128 Bits) + Available General + Purpose Flash Memory: 191 Pages (191*128 Bits) + + EBR Blocks with Unique + Initialization Data: 0 + + WID EBR Instance + --- ------------ + + +ASIC Components +--------------- + +Instance Name: ufmefb/EFBInst_0 + Type: EFB + +Run Time and Memory Usage +------------------------- + + Total CPU Time: 0 secs + Total REAL Time: 0 secs + Peak Memory Usage: 58 MB + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Page 7 + + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. + Copyright (c) 1995 AT&T Corp. All rights reserved. + Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. + Copyright (c) 2001 Agere Systems All rights reserved. + Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights + reserved. diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad new file mode 100644 index 0000000..938b7ba --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.pad @@ -0,0 +1,287 @@ +PAD Specification File +*************************** + +PART TYPE: LCMXO2-640HC +Performance Grade: 4 +PACKAGE: TQFP100 +Package Status: Final Version 1.39 + +Thu Sep 21 05:35:00 2023 + +Pinout by Port Name: ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +| Port Name | Pin/Bank | Buffer Type | Site | PG Enable | BC Enable | Properties | ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ +| Ain[0] | 3/3 | LVCMOS33_IN | PL2C | | | CLAMP:ON HYSTERESIS:SMALL | +| Ain[1] | 2/3 | LVCMOS33_IN | PL2B | | | CLAMP:ON HYSTERESIS:SMALL | +| Ain[2] | 7/3 | LVCMOS33_IN | PL3A | | | CLAMP:ON HYSTERESIS:SMALL | +| Ain[3] | 4/3 | LVCMOS33_IN | PL2D | | | CLAMP:ON HYSTERESIS:SMALL | +| Ain[4] | 78/0 | LVCMOS33_IN | PT11A | | | CLAMP:ON HYSTERESIS:SMALL | +| Ain[5] | 84/0 | LVCMOS33_IN | PT10A | | | CLAMP:ON HYSTERESIS:SMALL | +| Ain[6] | 86/0 | LVCMOS33_IN | PT9C | | | CLAMP:ON HYSTERESIS:SMALL | +| Ain[7] | 8/3 | LVCMOS33_IN | PL3B | | | CLAMP:ON HYSTERESIS:SMALL | +| BA[0] | 58/1 | LVCMOS33_OUT | PR6C | | | DRIVE:4mA SLEW:SLOW | +| BA[1] | 60/1 | LVCMOS33_OUT | PR6A | | | DRIVE:4mA SLEW:SLOW | +| C14M | 62/1 | LVCMOS33_IN | PR5D | | | CLAMP:ON HYSTERESIS:SMALL | +| CKE | 53/1 | LVCMOS33_OUT | PR7B | | | DRIVE:4mA SLEW:SLOW | +| DQMH | 49/2 | LVCMOS33_OUT | PB14D | | | DRIVE:4mA SLEW:SLOW | +| DQML | 48/2 | LVCMOS33_OUT | PB14C | | | DRIVE:4mA SLEW:SLOW | +| Din[0] | 96/0 | LVCMOS33_IN | PT6D | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[1] | 97/0 | LVCMOS33_IN | PT6C | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[2] | 98/0 | LVCMOS33_IN | PT6B | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[3] | 9/3 | LVCMOS33_IN | PL3C | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[4] | 1/3 | LVCMOS33_IN | PL2A | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[5] | 99/0 | LVCMOS33_IN | PT6A | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[6] | 88/0 | LVCMOS33_IN | PT9A | | | CLAMP:ON HYSTERESIS:SMALL | +| Din[7] | 87/0 | LVCMOS33_IN | PT9B | | | CLAMP:ON HYSTERESIS:SMALL | +| Dout[0] | 30/2 | LVCMOS33_OUT | PB4D | | | DRIVE:4mA SLEW:FAST | +| Dout[1] | 27/2 | LVCMOS33_OUT | PB4A | | | DRIVE:4mA SLEW:FAST | +| Dout[2] | 25/3 | LVCMOS33_OUT | PL7D | | | DRIVE:4mA SLEW:FAST | +| Dout[3] | 28/2 | LVCMOS33_OUT | PB4B | | | DRIVE:4mA SLEW:FAST | +| Dout[4] | 24/3 | LVCMOS33_OUT | PL7C | | | DRIVE:4mA SLEW:FAST | +| Dout[5] | 21/3 | LVCMOS33_OUT | PL7B | | | DRIVE:4mA SLEW:FAST | +| Dout[6] | 31/2 | LVCMOS33_OUT | PB6A | | | DRIVE:4mA SLEW:FAST | +| Dout[7] | 32/2 | LVCMOS33_OUT | PB6B | | | DRIVE:4mA SLEW:FAST | +| LED | 35/2 | LVCMOS33_OUT | PB6D | | | DRIVE:4mA SLEW:SLOW | +| PHI1 | 85/0 | LVCMOS33_IN | PT9D | | | CLAMP:ON HYSTERESIS:SMALL | +| RA[0] | 66/1 | LVCMOS33_OUT | PR3D | | | DRIVE:4mA SLEW:SLOW | +| RA[10] | 64/1 | LVCMOS33_OUT | PR5B | | | DRIVE:4mA SLEW:SLOW | +| RA[11] | 59/1 | LVCMOS33_OUT | PR6B | | | DRIVE:4mA SLEW:SLOW | +| RA[1] | 68/1 | LVCMOS33_OUT | PR3B | | | DRIVE:4mA SLEW:SLOW | +| RA[2] | 70/1 | LVCMOS33_OUT | PR2D | | | DRIVE:4mA SLEW:SLOW | +| RA[3] | 74/1 | LVCMOS33_OUT | PR2B | | | DRIVE:4mA SLEW:SLOW | +| RA[4] | 75/1 | LVCMOS33_OUT | PR2A | | | DRIVE:4mA SLEW:SLOW | +| RA[5] | 71/1 | LVCMOS33_OUT | PR2C | | | DRIVE:4mA SLEW:SLOW | +| RA[6] | 69/1 | LVCMOS33_OUT | PR3A | | | DRIVE:4mA SLEW:SLOW | +| RA[7] | 67/1 | LVCMOS33_OUT | PR3C | | | DRIVE:4mA SLEW:SLOW | +| RA[8] | 65/1 | LVCMOS33_OUT | PR5A | | | DRIVE:4mA SLEW:SLOW | +| RA[9] | 63/1 | LVCMOS33_OUT | PR5C | | | DRIVE:4mA SLEW:SLOW | +| RD[0] | 36/2 | LVCMOS33_BIDI | PB10A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[1] | 37/2 | LVCMOS33_BIDI | PB10B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[2] | 38/2 | LVCMOS33_BIDI | PB10C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[3] | 39/2 | LVCMOS33_BIDI | PB10D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[4] | 40/2 | LVCMOS33_BIDI | PB12A | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[5] | 41/2 | LVCMOS33_BIDI | PB12B | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[6] | 42/2 | LVCMOS33_BIDI | PB12C | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| RD[7] | 43/2 | LVCMOS33_BIDI | PB12D | | | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW | +| Vout[0] | 18/3 | LVCMOS33_OUT | PL6C | | | DRIVE:4mA SLEW:SLOW | +| Vout[1] | 15/3 | LVCMOS33_OUT | PL5D | | | DRIVE:4mA SLEW:SLOW | +| Vout[2] | 17/3 | LVCMOS33_OUT | PL6B | | | DRIVE:4mA SLEW:SLOW | +| Vout[3] | 13/3 | LVCMOS33_OUT | PL5B | | | DRIVE:4mA SLEW:SLOW | +| Vout[4] | 19/3 | LVCMOS33_OUT | PL6D | | | DRIVE:4mA SLEW:SLOW | +| Vout[5] | 16/3 | LVCMOS33_OUT | PL6A | | | DRIVE:4mA SLEW:SLOW | +| Vout[6] | 14/3 | LVCMOS33_OUT | PL5C | | | DRIVE:4mA SLEW:SLOW | +| Vout[7] | 12/3 | LVCMOS33_OUT | PL5A | | | DRIVE:4mA SLEW:SLOW | +| nC07X | 34/2 | LVCMOS33_IN | PB6C | | | CLAMP:ON HYSTERESIS:SMALL | +| nCAS | 52/1 | LVCMOS33_OUT | PR7C | | | DRIVE:4mA SLEW:SLOW | +| nCS | 57/1 | LVCMOS33_OUT | PR6D | | | DRIVE:4mA SLEW:SLOW | +| nDOE | 20/3 | LVCMOS33_OUT | PL7A | | | DRIVE:4mA SLEW:SLOW | +| nEN80 | 82/0 | LVCMOS33_IN | PT10C | | | CLAMP:ON HYSTERESIS:SMALL | +| nRAS | 54/1 | LVCMOS33_OUT | PR7A | | | DRIVE:4mA SLEW:SLOW | +| nRWE | 51/1 | LVCMOS33_OUT | PR7D | | | DRIVE:4mA SLEW:SLOW | +| nVOE | 10/3 | LVCMOS33_OUT | PL3D | | | DRIVE:4mA SLEW:SLOW | +| nWE | 29/2 | LVCMOS33_IN | PB4C | | | CLAMP:ON HYSTERESIS:SMALL | +| nWE80 | 83/0 | LVCMOS33_IN | PT10B | | | CLAMP:ON HYSTERESIS:SMALL | ++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+ + +Vccio by Bank: ++------+-------+ +| Bank | Vccio | ++------+-------+ +| 0 | 3.3V | +| 1 | 3.3V | +| 2 | 3.3V | +| 3 | 3.3V | ++------+-------+ + +Vref by Bank: ++------+-----+-----------------+---------+ +| Vref | Pin | Bank # / Vref # | Load(s) | ++------+-----+-----------------+---------+ ++------+-----+-----------------+---------+ + +Pinout by Pin Number: ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| Pin/Bank | Pin Info | Preference | Buffer Type | Site | Dual Function | PG Enable | BC Enable | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ +| 1/3 | Din[4] | LOCATED | LVCMOS33_IN | PL2A | | | | +| 2/3 | Ain[1] | LOCATED | LVCMOS33_IN | PL2B | | | | +| 3/3 | Ain[0] | LOCATED | LVCMOS33_IN | PL2C | PCLKT3_2 | | | +| 4/3 | Ain[3] | LOCATED | LVCMOS33_IN | PL2D | PCLKC3_2 | | | +| 7/3 | Ain[2] | LOCATED | LVCMOS33_IN | PL3A | | | | +| 8/3 | Ain[7] | LOCATED | LVCMOS33_IN | PL3B | | | | +| 9/3 | Din[3] | LOCATED | LVCMOS33_IN | PL3C | | | | +| 10/3 | nVOE | LOCATED | LVCMOS33_OUT | PL3D | | | | +| 12/3 | Vout[7] | LOCATED | LVCMOS33_OUT | PL5A | PCLKT3_1 | | | +| 13/3 | Vout[3] | LOCATED | LVCMOS33_OUT | PL5B | PCLKC3_1 | | | +| 14/3 | Vout[6] | LOCATED | LVCMOS33_OUT | PL5C | | | | +| 15/3 | Vout[1] | LOCATED | LVCMOS33_OUT | PL5D | | | | +| 16/3 | Vout[5] | LOCATED | LVCMOS33_OUT | PL6A | | | | +| 17/3 | Vout[2] | LOCATED | LVCMOS33_OUT | PL6B | | | | +| 18/3 | Vout[0] | LOCATED | LVCMOS33_OUT | PL6C | | | | +| 19/3 | Vout[4] | LOCATED | LVCMOS33_OUT | PL6D | | | | +| 20/3 | nDOE | LOCATED | LVCMOS33_OUT | PL7A | PCLKT3_0 | | | +| 21/3 | Dout[5] | LOCATED | LVCMOS33_OUT | PL7B | PCLKC3_0 | | | +| 24/3 | Dout[4] | LOCATED | LVCMOS33_OUT | PL7C | | | | +| 25/3 | Dout[2] | LOCATED | LVCMOS33_OUT | PL7D | | | | +| 27/2 | Dout[1] | LOCATED | LVCMOS33_OUT | PB4A | CSSPIN | | | +| 28/2 | Dout[3] | LOCATED | LVCMOS33_OUT | PB4B | | | | +| 29/2 | nWE | LOCATED | LVCMOS33_IN | PB4C | | | | +| 30/2 | Dout[0] | LOCATED | LVCMOS33_OUT | PB4D | | | | +| 31/2 | Dout[6] | LOCATED | LVCMOS33_OUT | PB6A | MCLK/CCLK | | | +| 32/2 | Dout[7] | LOCATED | LVCMOS33_OUT | PB6B | SO/SPISO | | | +| 34/2 | nC07X | LOCATED | LVCMOS33_IN | PB6C | PCLKT2_0 | | | +| 35/2 | LED | LOCATED | LVCMOS33_OUT | PB6D | PCLKC2_0 | | | +| 36/2 | RD[0] | LOCATED | LVCMOS33_BIDI | PB10A | | | | +| 37/2 | RD[1] | LOCATED | LVCMOS33_BIDI | PB10B | | | | +| 38/2 | RD[2] | LOCATED | LVCMOS33_BIDI | PB10C | PCLKT2_1 | | | +| 39/2 | RD[3] | LOCATED | LVCMOS33_BIDI | PB10D | PCLKC2_1 | | | +| 40/2 | RD[4] | LOCATED | LVCMOS33_BIDI | PB12A | | | | +| 41/2 | RD[5] | LOCATED | LVCMOS33_BIDI | PB12B | | | | +| 42/2 | RD[6] | LOCATED | LVCMOS33_BIDI | PB12C | | | | +| 43/2 | RD[7] | LOCATED | LVCMOS33_BIDI | PB12D | | | | +| 45/2 | unused, PULL:DOWN | | | PB14A | | | | +| 47/2 | unused, PULL:DOWN | | | PB14B | | | | +| 48/2 | DQML | LOCATED | LVCMOS33_OUT | PB14C | SN | | | +| 49/2 | DQMH | LOCATED | LVCMOS33_OUT | PB14D | SI/SISPI | | | +| 51/1 | nRWE | LOCATED | LVCMOS33_OUT | PR7D | | | | +| 52/1 | nCAS | LOCATED | LVCMOS33_OUT | PR7C | | | | +| 53/1 | CKE | LOCATED | LVCMOS33_OUT | PR7B | | | | +| 54/1 | nRAS | LOCATED | LVCMOS33_OUT | PR7A | | | | +| 57/1 | nCS | LOCATED | LVCMOS33_OUT | PR6D | | | | +| 58/1 | BA[0] | LOCATED | LVCMOS33_OUT | PR6C | | | | +| 59/1 | RA[11] | LOCATED | LVCMOS33_OUT | PR6B | | | | +| 60/1 | BA[1] | LOCATED | LVCMOS33_OUT | PR6A | | | | +| 62/1 | C14M | LOCATED | LVCMOS33_IN | PR5D | PCLKC1_0 | | | +| 63/1 | RA[9] | LOCATED | LVCMOS33_OUT | PR5C | PCLKT1_0 | | | +| 64/1 | RA[10] | LOCATED | LVCMOS33_OUT | PR5B | | | | +| 65/1 | RA[8] | LOCATED | LVCMOS33_OUT | PR5A | | | | +| 66/1 | RA[0] | LOCATED | LVCMOS33_OUT | PR3D | | | | +| 67/1 | RA[7] | LOCATED | LVCMOS33_OUT | PR3C | | | | +| 68/1 | RA[1] | LOCATED | LVCMOS33_OUT | PR3B | | | | +| 69/1 | RA[6] | LOCATED | LVCMOS33_OUT | PR3A | | | | +| 70/1 | RA[2] | LOCATED | LVCMOS33_OUT | PR2D | | | | +| 71/1 | RA[5] | LOCATED | LVCMOS33_OUT | PR2C | | | | +| 74/1 | RA[3] | LOCATED | LVCMOS33_OUT | PR2B | | | | +| 75/1 | RA[4] | LOCATED | LVCMOS33_OUT | PR2A | | | | +| 76/0 | unused, PULL:DOWN | | | PT11D | DONE | | | +| 77/0 | unused, PULL:DOWN | | | PT11C | INITN | | | +| 78/0 | Ain[4] | LOCATED | LVCMOS33_IN | PT11A | | | | +| 81/0 | unused, PULL:DOWN | | | PT10D | PROGRAMN | | | +| 82/0 | nEN80 | LOCATED | LVCMOS33_IN | PT10C | JTAGENB | | | +| 83/0 | nWE80 | LOCATED | LVCMOS33_IN | PT10B | | | | +| 84/0 | Ain[5] | LOCATED | LVCMOS33_IN | PT10A | | | | +| 85/0 | PHI1 | LOCATED | LVCMOS33_IN | PT9D | SDA/PCLKC0_0 | | | +| 86/0 | Ain[6] | LOCATED | LVCMOS33_IN | PT9C | SCL/PCLKT0_0 | | | +| 87/0 | Din[7] | LOCATED | LVCMOS33_IN | PT9B | PCLKC0_1 | | | +| 88/0 | Din[6] | LOCATED | LVCMOS33_IN | PT9A | PCLKT0_1 | | | +| 90/0 | Reserved: sysCONFIG | | | PT7D | TMS | | | +| 91/0 | Reserved: sysCONFIG | | | PT7C | TCK | | | +| 94/0 | Reserved: sysCONFIG | | | PT7B | TDI | | | +| 95/0 | Reserved: sysCONFIG | | | PT7A | TDO | | | +| 96/0 | Din[0] | LOCATED | LVCMOS33_IN | PT6D | | | | +| 97/0 | Din[1] | LOCATED | LVCMOS33_IN | PT6C | | | | +| 98/0 | Din[2] | LOCATED | LVCMOS33_IN | PT6B | | | | +| 99/0 | Din[5] | LOCATED | LVCMOS33_IN | PT6A | | | | +| PT11B/0 | unused, PULL:DOWN | | | PT11B | | | | ++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+ + +sysCONFIG Pins: ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode | ++----------+--------------------+--------------------+----------+-------------+-------------------+ +| PT7D | TMS | JTAG_PORT=ENABLE | 90/0 | | PULLUP | +| PT7C | TCK/TEST_CLK | JTAG_PORT=ENABLE | 91/0 | | NO pull up/down | +| PT7B | TDI/MD7 | JTAG_PORT=ENABLE | 94/0 | | PULLUP | +| PT7A | TDO | JTAG_PORT=ENABLE | 95/0 | | PULLUP | ++----------+--------------------+--------------------+----------+-------------+-------------------+ + +Dedicated sysCONFIG Pins: + + +List of All Pins' Locate Preferences Based on Final Placement After PAR +to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): + +LOCATE COMP "Ain[0]" SITE "3"; +LOCATE COMP "Ain[1]" SITE "2"; +LOCATE COMP "Ain[2]" SITE "7"; +LOCATE COMP "Ain[3]" SITE "4"; +LOCATE COMP "Ain[4]" SITE "78"; +LOCATE COMP "Ain[5]" SITE "84"; +LOCATE COMP "Ain[6]" SITE "86"; +LOCATE COMP "Ain[7]" SITE "8"; +LOCATE COMP "BA[0]" SITE "58"; +LOCATE COMP "BA[1]" SITE "60"; +LOCATE COMP "C14M" SITE "62"; +LOCATE COMP "CKE" SITE "53"; +LOCATE COMP "DQMH" SITE "49"; +LOCATE COMP "DQML" SITE "48"; +LOCATE COMP "Din[0]" SITE "96"; +LOCATE COMP "Din[1]" SITE "97"; +LOCATE COMP "Din[2]" SITE "98"; +LOCATE COMP "Din[3]" SITE "9"; +LOCATE COMP "Din[4]" SITE "1"; +LOCATE COMP "Din[5]" SITE "99"; +LOCATE COMP "Din[6]" SITE "88"; +LOCATE COMP "Din[7]" SITE "87"; +LOCATE COMP "Dout[0]" SITE "30"; +LOCATE COMP "Dout[1]" SITE "27"; +LOCATE COMP "Dout[2]" SITE "25"; +LOCATE COMP "Dout[3]" SITE "28"; +LOCATE COMP "Dout[4]" SITE "24"; +LOCATE COMP "Dout[5]" SITE "21"; +LOCATE COMP "Dout[6]" SITE "31"; +LOCATE COMP "Dout[7]" SITE "32"; +LOCATE COMP "LED" SITE "35"; +LOCATE COMP "PHI1" SITE "85"; +LOCATE COMP "RA[0]" SITE "66"; +LOCATE COMP "RA[10]" SITE "64"; +LOCATE COMP "RA[11]" SITE "59"; +LOCATE COMP "RA[1]" SITE "68"; +LOCATE COMP "RA[2]" SITE "70"; +LOCATE COMP "RA[3]" SITE "74"; +LOCATE COMP "RA[4]" SITE "75"; +LOCATE COMP "RA[5]" SITE "71"; +LOCATE COMP "RA[6]" SITE "69"; +LOCATE COMP "RA[7]" SITE "67"; +LOCATE COMP "RA[8]" SITE "65"; +LOCATE COMP "RA[9]" SITE "63"; +LOCATE COMP "RD[0]" SITE "36"; +LOCATE COMP "RD[1]" SITE "37"; +LOCATE COMP "RD[2]" SITE "38"; +LOCATE COMP "RD[3]" SITE "39"; +LOCATE COMP "RD[4]" SITE "40"; +LOCATE COMP "RD[5]" SITE "41"; +LOCATE COMP "RD[6]" SITE "42"; +LOCATE COMP "RD[7]" SITE "43"; +LOCATE COMP "Vout[0]" SITE "18"; +LOCATE COMP "Vout[1]" SITE "15"; +LOCATE COMP "Vout[2]" SITE "17"; +LOCATE COMP "Vout[3]" SITE "13"; +LOCATE COMP "Vout[4]" SITE "19"; +LOCATE COMP "Vout[5]" SITE "16"; +LOCATE COMP "Vout[6]" SITE "14"; +LOCATE COMP "Vout[7]" SITE "12"; +LOCATE COMP "nC07X" SITE "34"; +LOCATE COMP "nCAS" SITE "52"; +LOCATE COMP "nCS" SITE "57"; +LOCATE COMP "nDOE" SITE "20"; +LOCATE COMP "nEN80" SITE "82"; +LOCATE COMP "nRAS" SITE "54"; +LOCATE COMP "nRWE" SITE "51"; +LOCATE COMP "nVOE" SITE "10"; +LOCATE COMP "nWE" SITE "29"; +LOCATE COMP "nWE80" SITE "83"; + + + + + +PAR: Place And Route Diamond (64-bit) 3.12.1.454. +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. +Thu Sep 21 05:35:04 2023 + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf new file mode 100644 index 0000000..77b562e --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.prf @@ -0,0 +1,127 @@ +SCHEMATIC START ; +# map: version Diamond (64-bit) 3.12.1.454 -- WARNING: Map write only section -- Thu Sep 21 05:34:47 2023 + +SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE BACKGROUND_RECONFIG=OFF INBUF=ON ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "LED" SITE "35" ; +LOCATE COMP "C14M" SITE "62" ; +LOCATE COMP "DQMH" SITE "49" ; +LOCATE COMP "DQML" SITE "48" ; +LOCATE COMP "RD[7]" SITE "43" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[7]" SITE "67" ; +LOCATE COMP "RA[6]" SITE "69" ; +LOCATE COMP "RA[5]" SITE "71" ; +LOCATE COMP "RA[4]" SITE "75" ; +LOCATE COMP "RA[3]" SITE "74" ; +LOCATE COMP "RA[2]" SITE "70" ; +LOCATE COMP "RA[1]" SITE "68" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "BA[1]" SITE "60" ; +LOCATE COMP "BA[0]" SITE "58" ; +LOCATE COMP "nRWE" SITE "51" ; +LOCATE COMP "nCAS" SITE "52" ; +LOCATE COMP "nRAS" SITE "54" ; +LOCATE COMP "nCS" SITE "57" ; +LOCATE COMP "CKE" SITE "53" ; +LOCATE COMP "nVOE" SITE "10" ; +LOCATE COMP "Vout[7]" SITE "12" ; +LOCATE COMP "Vout[6]" SITE "14" ; +LOCATE COMP "Vout[5]" SITE "16" ; +LOCATE COMP "Vout[4]" SITE "19" ; +LOCATE COMP "Vout[3]" SITE "13" ; +LOCATE COMP "Vout[2]" SITE "17" ; +LOCATE COMP "Vout[1]" SITE "15" ; +LOCATE COMP "Vout[0]" SITE "18" ; +LOCATE COMP "nDOE" SITE "20" ; +LOCATE COMP "Dout[7]" SITE "32" ; +LOCATE COMP "Dout[6]" SITE "31" ; +LOCATE COMP "Dout[5]" SITE "21" ; +LOCATE COMP "Dout[4]" SITE "24" ; +LOCATE COMP "Dout[3]" SITE "28" ; +LOCATE COMP "Dout[2]" SITE "25" ; +LOCATE COMP "Dout[1]" SITE "27" ; +LOCATE COMP "Dout[0]" SITE "30" ; +LOCATE COMP "Din[7]" SITE "87" ; +LOCATE COMP "Din[6]" SITE "88" ; +LOCATE COMP "Din[5]" SITE "99" ; +LOCATE COMP "Din[4]" SITE "1" ; +LOCATE COMP "Din[3]" SITE "9" ; +LOCATE COMP "Din[2]" SITE "98" ; +LOCATE COMP "Din[1]" SITE "97" ; +LOCATE COMP "Din[0]" SITE "96" ; +LOCATE COMP "Ain[7]" SITE "8" ; +LOCATE COMP "Ain[6]" SITE "86" ; +LOCATE COMP "Ain[5]" SITE "84" ; +LOCATE COMP "Ain[4]" SITE "78" ; +LOCATE COMP "Ain[3]" SITE "4" ; +LOCATE COMP "Ain[2]" SITE "7" ; +LOCATE COMP "Ain[1]" SITE "2" ; +LOCATE COMP "Ain[0]" SITE "3" ; +LOCATE COMP "nC07X" SITE "34" ; +LOCATE COMP "nEN80" SITE "82" ; +LOCATE COMP "nWE80" SITE "83" ; +LOCATE COMP "nWE" SITE "29" ; +LOCATE COMP "PHI1" SITE "85" ; +FREQUENCY PORT "C14M" 14.300000 MHz ; +SCHEMATIC END ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +OUTPUT PORT "LED" LOAD 100.000000 pF ; +OUTPUT PORT "BA[1]" LOAD 5.000000 pF ; +OUTPUT PORT "BA[0]" LOAD 5.000000 pF ; +OUTPUT PORT "CKE" LOAD 5.000000 pF ; +OUTPUT PORT "DQMH" LOAD 5.000000 pF ; +OUTPUT PORT "DQML" LOAD 5.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 5.000000 pF ; +OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[3]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ; +OUTPUT PORT "nCAS" LOAD 5.000000 pF ; +OUTPUT PORT "nCS" LOAD 5.000000 pF ; +OUTPUT PORT "nDOE" LOAD 10.000000 pF ; +OUTPUT PORT "nRAS" LOAD 5.000000 pF ; +OUTPUT PORT "nRWE" LOAD 5.000000 pF ; +OUTPUT PORT "nVOE" LOAD 10.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[7]" LOAD 9.000000 pF ; +COMMERCIAL ; diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr new file mode 100644 index 0000000..dd1963b --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.srr @@ -0,0 +1,690 @@ +#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021 +#install: C:\lscc\diamond\3.12\synpbase +#OS: Windows 8 6.2 +#Hostname: ZANEMACWIN11 + +# Thu Sep 21 05:34:32 2023 + +#Implementation: impl1 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps) +@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps) +@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work) +@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work) +Verilog syntax check successful! + +Compiler output is up to date. No re-compile necessary + +Selecting top level module RAM2E +@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work. +Running optimization stage 1 on VHI ....... +Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work. +Running optimization stage 1 on VLO ....... +Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB) +@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work. +Running optimization stage 1 on EFB ....... +Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) +@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work. +Running optimization stage 1 on REFB ....... +Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB) +@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work. +Running optimization stage 1 on RAM2E ....... +Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB) +Running optimization stage 2 on RAM2E ....... +Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) +Running optimization stage 2 on REFB ....... +Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) +Running optimization stage 2 on EFB ....... +Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) +Running optimization stage 2 on VLO ....... +Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) +Running optimization stage 2 on VHI ....... +Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB) + +At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Thu Sep 21 05:34:32 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Thu Sep 21 05:34:33 2023 + +###########################################################] + +For a summary of runtime and memory usage for all design units, please see file: +========================================================== +@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv + +@END + +At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Thu Sep 21 05:34:33 2023 + +###########################################################] +###########################################################[ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @ + +@N|Running in 64-bit mode +File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling + +At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime + +Process completed successfully. +# Thu Sep 21 05:34:34 2023 + +###########################################################] +# Thu Sep 21 05:34:34 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) + + +Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB) + +Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc +@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt +See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt" +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB) + +@N: FX493 |Applying initial value "0" on instance PHI1reg. +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. +@N: FX493 |Applying initial value "0" on instance DOEEN. +@N: FX493 |Applying initial value "0" on instance RWSel. +@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0]. +@N: FX493 |Applying initial value "1" on instance DQMH. +@N: FX493 |Applying initial value "0" on instance Ready. +@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2. +@N: FX493 |Applying initial value "0" on instance CmdExecMXO2. +@N: FX493 |Applying initial value "0" on instance CmdLEDGet. +@N: FX493 |Applying initial value "0" on instance CmdLEDSet. +@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet. +@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED. +@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2. +@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP. +@N: FX493 |Applying initial value "1" on instance nRWE. +@N: FX493 |Applying initial value "0" on instance LEDEN. +@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0]. +@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP. +@N: FX493 |Applying initial value "0000" on instance S[3:0]. +@N: FX493 |Applying initial value "1" on instance DQML. +@N: FX493 |Applying initial value "0" on instance CKE. +@N: FX493 |Applying initial value "1" on instance nCS. +@N: FX493 |Applying initial value "1" on instance nRAS. +@N: FX493 |Applying initial value "1" on instance nCAS. + +Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB) + + +Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) + + +Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB) + + +Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) + +@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E + +Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) + + + +Clock Summary +****************** + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------- +0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111 + +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +======================================================================================== + + + +Clock Load Summary +*********************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +---------------------------------------------------------------------------------------- +C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv) + +System 0 - - - - +======================================================================================== + +ICG Latch Removal Summary: +Number of ICG latches removed: 0 +Number of ICG latches not removed: 0 +For details review file gcc_ICG_report.rpt + + +@S |Clock Optimization Summary + + + +#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[ + +1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s) +0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s) +0 instances converted, 0 sequential instances remain driven by gated/generated clocks + +=========================== Non-Gated/Non-Generated Clocks ============================ +Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance +--------------------------------------------------------------------------------------- +@KP:ckid0_0 C14M port 111 nCAS +======================================================================================= + + +##### END OF CLOCK OPTIMIZATION REPORT ###### + +@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. +Finished Pre Mapping Phase. + +Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB) + + +Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) + + +Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) + +Pre-mapping successful! + +At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB) + +Process took 0h:00m:02s realtime, 0h:00m:01s cputime +# Thu Sep 21 05:34:37 2023 + +###########################################################] +# Thu Sep 21 05:34:37 2023 + + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 +Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct 6 2021 11:12:38, @ + + +Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB) + +@N: MF916 |Option synthesis_strategy=base is enabled. +@N: MF248 |Running in 64-bit mode. +@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) + +Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) + + +Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB) + + +Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB) + + +Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB) + + + +Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB) + +@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. +@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit. + +Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB) + +@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0] +@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. + +Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB) + + +Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) + + +Available hyper_sources - for debug and ip models + None Found + + +Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB) + + +Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB) + + +Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB) + + +Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB) + + +Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB) + + +Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB) + +Pass CPU time Worst Slack Luts / Registers +------------------------------------------------------------ + 1 0h:00m:02s 29.35ns 222 / 111 + +Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB) + +@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute. + +Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB) + + +Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB) + +Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm + +Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 206MB peak: 206MB) + +Writing EDIF Netlist and constraint files +@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi +@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF + +Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB) + + +Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB) + + +Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB) + +@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) +@N: MT615 |Found clock C14M with period 69.84ns + + +##### START OF TIMING REPORT #####[ +# Timing report written on Thu Sep 21 05:34:43 2023 +# + + +Top view: RAM2E +Requested Frequency: 14.3 MHz +Wire load mode: top +Paths requested: 5 +Constraint File(s): \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc + +@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. + +@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock. + + + +Performance Summary +******************* + + +Worst slack in design: 31.782 + + Requested Estimated Requested Estimated Clock Clock +Starting Clock Frequency Frequency Period Period Slack Type Group +------------------------------------------------------------------------------------------------------------------- +C14M 14.3 MHz 131.4 MHz 69.841 7.610 31.782 declared default_clkgroup +System 100.0 MHz NA 10.000 NA 67.088 system system_clkgroup +=================================================================================================================== +Estimated period and frequency reported as NA means no slack depends directly on the clock waveform + + + + + +Clock Relationships +******************* + +Clocks | rise to rise | fall to fall | rise to fall | fall to rise +---------------------------------------------------------------------------------------------------------- +Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack +---------------------------------------------------------------------------------------------------------- +System C14M | 69.841 67.088 | No paths - | No paths - | No paths - +C14M System | 69.841 68.797 | No paths - | No paths - | No paths - +C14M C14M | 69.841 62.231 | No paths - | 34.920 31.782 | No paths - +========================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + + +Interface Information +********************* + +No IO constraint found + + + +==================================== +Detailed Report for Clock: C14M +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------- +S[2] C14M FD1S3AX Q S[2] 1.350 31.782 +S[3] C14M FD1S3AX Q S[3] 1.350 31.782 +S[0] C14M FD1S3AX Q S[0] 1.312 31.820 +S[1] C14M FD1S3AX Q S[1] 1.280 31.852 +FS[9] C14M FD1S3AX Q FS[9] 1.284 62.425 +FS[11] C14M FD1S3AX Q FS[11] 1.276 62.433 +FS[8] C14M FD1S3AX Q FS[8] 1.260 62.449 +FS[12] C14M FD1S3AX Q FS[12] 1.288 62.525 +FS[10] C14M FD1S3AX Q FS[10] 1.280 62.533 +RWSel C14M FD1P3AX Q RWSel 1.276 63.482 +============================================================================ + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------- +Dout_0io[0] C14M OFS1P3DX SP N_576_i 34.449 31.782 +Dout_0io[1] C14M OFS1P3DX SP N_576_i 34.449 31.782 +Dout_0io[2] C14M OFS1P3DX SP N_576_i 34.449 31.782 +Dout_0io[3] C14M OFS1P3DX SP N_576_i 34.449 31.782 +Dout_0io[4] C14M OFS1P3DX SP N_576_i 34.449 31.782 +Dout_0io[5] C14M OFS1P3DX SP N_576_i 34.449 31.782 +Dout_0io[6] C14M OFS1P3DX SP N_576_i 34.449 31.782 +Dout_0io[7] C14M OFS1P3DX SP N_576_i 34.449 31.782 +Vout_0io[0] C14M OFS1P3DX SP Vout3 34.449 31.826 +Vout_0io[1] C14M OFS1P3DX SP Vout3 34.449 31.826 +================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 34.920 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 34.449 + + - Propagation time: 2.667 + - Clock delay at starting point: 0.000 (ideal) + = Slack (critical) : 31.782 + + Number of logic level(s): 1 + Starting point: S[2] / Q + Ending point: Dout_0io[0] / SP + The start point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK + The end point is clocked by C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +---------------------------------------------------------------------------------- +S[2] FD1S3AX Q Out 1.350 1.350 r - +S[2] Net - - - - 48 +S_RNII9DO1_2[1] ORCALUT4 B In 0.000 1.350 r - +S_RNII9DO1_2[1] ORCALUT4 Z Out 1.317 2.667 r - +N_576_i Net - - - - 18 +Dout_0io[0] OFS1P3DX SP In 0.000 2.667 r - +================================================================================== + + + + +==================================== +Detailed Report for Clock: System +==================================== + + + +Starting Points with Worst Slack +******************************** + + Starting Arrival +Instance Reference Type Pin Net Time Slack + Clock +----------------------------------------------------------------------------------------- +ufmefb.EFBInst_0 System EFB WBACKO wb_ack 0.000 67.088 +ufmefb.EFBInst_0 System EFB WBDATO0 wb_dato[0] 0.000 69.313 +ufmefb.EFBInst_0 System EFB WBDATO1 wb_dato[1] 0.000 69.313 +ufmefb.EFBInst_0 System EFB WBDATO2 wb_dato[2] 0.000 69.313 +ufmefb.EFBInst_0 System EFB WBDATO3 wb_dato[3] 0.000 69.313 +ufmefb.EFBInst_0 System EFB WBDATO4 wb_dato[4] 0.000 69.313 +ufmefb.EFBInst_0 System EFB WBDATO5 wb_dato[5] 0.000 69.313 +ufmefb.EFBInst_0 System EFB WBDATO6 wb_dato[6] 0.000 69.313 +ufmefb.EFBInst_0 System EFB WBDATO7 wb_dato[7] 0.000 69.313 +========================================================================================= + + +Ending Points with Worst Slack +****************************** + + Starting Required +Instance Reference Type Pin Net Time Slack + Clock +---------------------------------------------------------------------------------------------------- +RWMask[0] System FD1P3AX SP N_88 69.369 67.088 +RWMask[1] System FD1P3AX SP N_88 69.369 67.088 +RWMask[2] System FD1P3AX SP N_88 69.369 67.088 +RWMask[3] System FD1P3AX SP N_88 69.369 67.088 +RWMask[4] System FD1P3AX SP N_88 69.369 67.088 +RWMask[5] System FD1P3AX SP N_88 69.369 67.088 +RWMask[6] System FD1P3AX SP N_88 69.369 67.088 +RWMask[7] System FD1P3AX SP N_88 69.369 67.088 +LEDEN System FD1P3AX SP un1_LEDEN_0_sqmuxa_1_i_0[0] 69.369 67.736 +wb_cyc_stb System FD1P3AX SP N_104 69.369 67.736 +==================================================================================================== + + + +Worst Path Information +*********************** + + +Path information for path number 1: + Requested Period: 69.841 + - Setup time: 0.472 + + Clock delay at ending point: 0.000 (ideal) + = Required time: 69.369 + + - Propagation time: 2.282 + - Clock delay at starting point: 0.000 (ideal) + - Estimated clock delay at start point: -0.000 + = Slack (non-critical) : 67.088 + + Number of logic level(s): 2 + Starting point: ufmefb.EFBInst_0 / WBACKO + Ending point: RWMask[0] / SP + The start point is clocked by System [rising] + The end point is clocked by C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK + +Instance / Net Pin Pin Arrival No. of +Name Type Name Dir Delay Time Fan Out(s) +------------------------------------------------------------------------------------------------------ +ufmefb.EFBInst_0 EFB WBACKO Out 0.000 0.000 r - +wb_ack Net - - - - 5 +un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 A In 0.000 0.000 r - +un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ORCALUT4 Z Out 1.017 1.017 r - +un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] Net - - - - 1 +un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 D In 0.000 1.017 r - +un1_RWMask_0_sqmuxa_1_i_0[0] ORCALUT4 Z Out 1.265 2.282 r - +N_88 Net - - - - 8 +RWMask[0] FD1P3AX SP In 0.000 2.282 r - +====================================================================================================== + + + +##### END OF TIMING REPORT #####] + +Timing exceptions that could not be applied + +Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB) + + +Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB) + +--------------------------------------- +Resource Usage Report +Part: lcmxo2_640hc-4 + +Register bits: 111 of 640 (17%) +PIC Latch: 0 +I/O cells: 70 + + +Details: +BB: 8 +CCU2D: 9 +EFB: 1 +FD1P3AX: 48 +FD1P3IX: 1 +FD1S3AX: 22 +FD1S3IX: 4 +GSR: 1 +IB: 22 +IFS1P3DX: 1 +INV: 1 +OB: 40 +OFS1P3BX: 6 +OFS1P3DX: 27 +OFS1P3IX: 2 +ORCALUT4: 221 +PUR: 1 +VHI: 2 +VLO: 2 +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 77MB peak: 211MB) + +Process took 0h:00m:06s realtime, 0h:00m:04s cputime +# Thu Sep 21 05:34:44 2023 + +###########################################################] diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.tw1 b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.tw1 new file mode 100644 index 0000000..9f9184a --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.tw1 @@ -0,0 +1,215 @@ + +Loading design for application trce from file ram2e_lcmxo2_640hc_impl1_map.ncd. +Design name: RAM2E +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Thu Sep 21 05:34:48 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf +Design file: ram2e_lcmxo2_640hc_impl1_map.ncd +Preference file: ram2e_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; + 1491 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 58.471ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[11] (from C14M_c +) + Destination: FF Data in nRWE_0io (to C14M_c +) + + Delay: 11.306ns (30.3% logic, 69.7% route), 7 logic levels. + + Constraint Details: + + 11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets + 69.930ns delay constraint less + 0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns + + Physical Path Details: + + Data path SLICE_3 to nRWE_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 SLICE_3.CLK to SLICE_3.Q0 SLICE_3 (from C14M_c) +ROUTE 19 e 1.234 SLICE_3.Q0 to SLICE_64.A1 FS[11] +CTOF_DEL --- 0.495 SLICE_64.A1 to SLICE_64.F1 SLICE_64 +ROUTE 4 e 1.234 SLICE_64.F1 to SLICE_97.D0 N_577 +CTOF_DEL --- 0.495 SLICE_97.D0 to SLICE_97.F0 SLICE_97 +ROUTE 3 e 1.234 SLICE_97.F0 to SLICE_75.D1 N_489 +CTOF_DEL --- 0.495 SLICE_75.D1 to SLICE_75.F1 SLICE_75 +ROUTE 3 e 0.480 SLICE_75.F1 to SLICE_75.A0 N_628 +CTOF_DEL --- 0.495 SLICE_75.A0 to SLICE_75.F0 SLICE_75 +ROUTE 2 e 1.234 SLICE_75.F0 to SLICE_71.C1 N_640 +CTOF_DEL --- 0.495 SLICE_71.C1 to SLICE_71.F1 SLICE_71 +ROUTE 1 e 1.234 SLICE_71.F1 to SLICE_115.A0 un1_nCS61_1_i +CTOF_DEL --- 0.495 SLICE_115.A0 to SLICE_115.F0 SLICE_115 +ROUTE 1 e 1.234 SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c) + -------- + 11.306 (30.3% logic, 69.7% route), 7 logic levels. + +Report: 87.268MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 87.268 MHz| 7 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 1 clocks: + +Clock Domain: C14M_c Source: C14M.PAD Loads: 84 + Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; + + +Timing summary (Setup): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Thu Sep 21 05:34:48 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf +Design file: ram2e_lcmxo2_640hc_impl1_map.ncd +Preference file: ram2e_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,M +Report level: verbose report, limited to 1 item per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; + 1491 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.447ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[0] (from C14M_c +) + Destination: FF Data in FS[0] (to C14M_c +) + + Delay: 0.434ns (53.9% logic, 46.1% route), 2 logic levels. + + Constraint Details: + + 0.434ns physical path delay SLICE_0 to SLICE_0 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 SLICE_0.CLK to SLICE_0.Q1 SLICE_0 (from C14M_c) +ROUTE 5 e 0.199 SLICE_0.Q1 to SLICE_0.A1 FS[0] +CTOF_DEL --- 0.101 SLICE_0.A1 to SLICE_0.F1 SLICE_0 +ROUTE 1 e 0.001 SLICE_0.F1 to SLICE_0.DI1 FS_s[0] (to C14M_c) + -------- + 0.434 (53.9% logic, 46.1% route), 2 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 2 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 1 clocks: + +Clock Domain: C14M_c Source: C14M.PAD Loads: 84 + Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr new file mode 100644 index 0000000..8f602e5 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1.twr @@ -0,0 +1,1121 @@ + +Loading design for application trce from file ram2e_lcmxo2_640hc_impl1.ncd. +Design name: RAM2E +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 4 +Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga. +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Setup and Hold Report + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454 +Thu Sep 21 05:35:07 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf +Design file: ram2e_lcmxo2_640hc_impl1.ncd +Preference file: ram2e_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,4 +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; + 1491 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 57.366ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[11] (from C14M_c +) + Destination: FF Data in nRWE_0io (to C14M_c +) + + Delay: 12.584ns (27.2% logic, 72.8% route), 7 logic levels. + + Constraint Details: + + 12.584ns physical path delay SLICE_3 to nRWE_MGIOL meets + 69.930ns delay constraint less + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 69.950ns) by 57.366ns + + Physical Path Details: + + Data path SLICE_3 to nRWE_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c) +ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11] +CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64 +ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577 +CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97 +ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489 +CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75 +ROUTE 3 0.453 R3C9C.F1 to R3C9C.C0 N_628 +CTOF_DEL --- 0.495 R3C9C.C0 to R3C9C.F0 SLICE_75 +ROUTE 2 0.993 R3C9C.F0 to R5C9A.A1 N_640 +CTOF_DEL --- 0.495 R5C9A.A1 to R5C9A.F1 SLICE_71 +ROUTE 1 0.623 R5C9A.F1 to R5C10B.D0 un1_nCS61_1_i +CTOF_DEL --- 0.495 R5C10B.D0 to R5C10B.F0 SLICE_115 +ROUTE 1 2.192 R5C10B.F0 to IOL_R7D.OPOS nRWE_r_0 (to C14M_c) + -------- + 12.584 (27.2% logic, 72.8% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to nRWE_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.243 62.PADDI to IOL_R7D.CLK C14M_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 57.494ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[11] (from C14M_c +) + Destination: FF Data in nRAS_0io (to C14M_c +) + + Delay: 12.456ns (23.5% logic, 76.5% route), 6 logic levels. + + Constraint Details: + + 12.456ns physical path delay SLICE_3 to nRAS_MGIOL meets + 69.930ns delay constraint less + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 69.950ns) by 57.494ns + + Physical Path Details: + + Data path SLICE_3 to nRAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c) +ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11] +CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64 +ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577 +CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97 +ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489 +CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75 +ROUTE 3 1.003 R3C9C.F1 to R3C10D.A0 N_628 +CTOF_DEL --- 0.495 R3C10D.A0 to R3C10D.F0 SLICE_83 +ROUTE 2 1.505 R3C10D.F0 to R5C10A.A0 N_559_1 +CTOF_DEL --- 0.495 R5C10A.A0 to R5C10A.F0 SLICE_80 +ROUTE 1 2.120 R5C10A.F0 to IOL_R7A.OPOS nRAS_2_iv_i (to C14M_c) + -------- + 12.456 (23.5% logic, 76.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to nRAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.243 62.PADDI to IOL_R7A.CLK C14M_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 57.502ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[11] (from C14M_c +) + Destination: FF Data in nRWE_0io (to C14M_c +) + + Delay: 12.448ns (23.5% logic, 76.5% route), 6 logic levels. + + Constraint Details: + + 12.448ns physical path delay SLICE_3 to nRWE_MGIOL meets + 69.930ns delay constraint less + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 69.950ns) by 57.502ns + + Physical Path Details: + + Data path SLICE_3 to nRWE_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c) +ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11] +CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64 +ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577 +CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97 +ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489 +CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75 +ROUTE 3 0.710 R3C9C.F1 to R3C9B.B0 N_628 +CTOF_DEL --- 0.495 R3C9B.B0 to R3C9B.F0 SLICE_76 +ROUTE 3 1.718 R3C9B.F0 to R5C10B.C0 nCAS_0_sqmuxa +CTOF_DEL --- 0.495 R5C10B.C0 to R5C10B.F0 SLICE_115 +ROUTE 1 2.192 R5C10B.F0 to IOL_R7D.OPOS nRWE_r_0 (to C14M_c) + -------- + 12.448 (23.5% logic, 76.5% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to nRWE_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.243 62.PADDI to IOL_R7D.CLK C14M_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 57.921ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[11] (from C14M_c +) + Destination: FF Data in nCS_0io (to C14M_c +) + + Delay: 12.029ns (24.3% logic, 75.7% route), 6 logic levels. + + Constraint Details: + + 12.029ns physical path delay SLICE_3 to nCS_MGIOL meets + 69.930ns delay constraint less + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 69.950ns) by 57.921ns + + Physical Path Details: + + Data path SLICE_3 to nCS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c) +ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11] +CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64 +ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577 +CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97 +ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489 +CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75 +ROUTE 3 1.003 R3C9C.F1 to R3C10D.A0 N_628 +CTOF_DEL --- 0.495 R3C10D.A0 to R3C10D.F0 SLICE_83 +ROUTE 2 1.505 R3C10D.F0 to R6C10A.A0 N_559_1 +CTOF_DEL --- 0.495 R6C10A.A0 to R6C10A.F0 SLICE_79 +ROUTE 1 1.693 R6C10A.F0 to IOL_R6D.OPOS N_559_i (to C14M_c) + -------- + 12.029 (24.3% logic, 75.7% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to nCS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.243 62.PADDI to IOL_R6D.CLK C14M_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 58.106ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[11] (from C14M_c +) + Destination: FF Data in nCAS_0io (to C14M_c +) + + Delay: 11.844ns (24.7% logic, 75.3% route), 6 logic levels. + + Constraint Details: + + 11.844ns physical path delay SLICE_3 to nCAS_MGIOL meets + 69.930ns delay constraint less + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 69.950ns) by 58.106ns + + Physical Path Details: + + Data path SLICE_3 to nCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c) +ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11] +CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64 +ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577 +CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97 +ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489 +CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75 +ROUTE 3 0.710 R3C9C.F1 to R3C9B.B0 N_628 +CTOF_DEL --- 0.495 R3C9B.B0 to R3C9B.F0 SLICE_76 +ROUTE 3 1.511 R3C9B.F0 to R5C9C.A0 nCAS_0_sqmuxa +CTOF_DEL --- 0.495 R5C9C.A0 to R5C9C.F0 SLICE_78 +ROUTE 1 1.795 R5C9C.F0 to IOL_R7C.OPOS N_561_i (to C14M_c) + -------- + 11.844 (24.7% logic, 75.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to nCAS_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.243 62.PADDI to IOL_R7C.CLK C14M_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 58.447ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[11] (from C14M_c +) + Destination: FF Data in RA_0io[10] (to C14M_c +) + + Delay: 11.503ns (25.4% logic, 74.6% route), 6 logic levels. + + Constraint Details: + + 11.503ns physical path delay SLICE_3 to RA[10]_MGIOL meets + 69.930ns delay constraint less + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 69.950ns) by 58.447ns + + Physical Path Details: + + Data path SLICE_3 to RA[10]_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c) +ROUTE 19 2.765 R2C8C.Q0 to R2C6A.A1 FS[11] +CTOF_DEL --- 0.495 R2C6A.A1 to R2C6A.F1 SLICE_64 +ROUTE 4 0.791 R2C6A.F1 to R3C6A.C0 N_577 +CTOF_DEL --- 0.495 R3C6A.C0 to R3C6A.F0 SLICE_97 +ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489 +CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75 +ROUTE 3 0.710 R3C9C.F1 to R3C9B.B0 N_628 +CTOF_DEL --- 0.495 R3C9B.B0 to R3C9B.F0 SLICE_76 +ROUTE 3 1.170 R3C9B.F0 to R5C9D.D1 nCAS_0_sqmuxa +CTOF_DEL --- 0.495 R5C9D.D1 to R5C9D.F1 SLICE_69 +ROUTE 1 1.795 R5C9D.F1 to IOL_R5B.OPOS RA_42[10] (to C14M_c) + -------- + 11.503 (25.4% logic, 74.6% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to RA[10]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.243 62.PADDI to IOL_R5B.CLK C14M_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 58.587ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q S[2] (from C14M_c +) + Destination: FF Data in wb_adr[0] (to C14M_c +) + + Delay: 11.177ns (26.2% logic, 73.8% route), 6 logic levels. + + Constraint Details: + + 11.177ns physical path delay SLICE_34 to SLICE_35 meets + 69.930ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.587ns + + Physical Path Details: + + Data path SLICE_34 to SLICE_35: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C9C.CLK to R4C9C.Q0 SLICE_34 (from C14M_c) +ROUTE 48 1.873 R4C9C.Q0 to R6C9B.B0 S[2] +CTOF_DEL --- 0.495 R6C9B.B0 to R6C9B.F0 SLICE_47 +ROUTE 7 2.435 R6C9B.F0 to R4C5B.B0 S_RNII9DO1[1] +CTOF_DEL --- 0.495 R4C5B.B0 to R4C5B.F0 SLICE_73 +ROUTE 8 1.931 R4C5B.F0 to R4C4C.D0 N_455 +CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_89 +ROUTE 1 0.626 R4C4C.F0 to R4C4A.D0 N_378 +CTOF_DEL --- 0.495 R4C4A.D0 to R4C4A.F0 SLICE_85 +ROUTE 1 1.385 R4C4A.F0 to R2C4B.D0 wb_adr_7_0_4[0] +CTOF_DEL --- 0.495 R2C4B.D0 to R2C4B.F0 SLICE_35 +ROUTE 1 0.000 R2C4B.F0 to R2C4B.DI0 wb_adr_7[0] (to C14M_c) + -------- + 11.177 (26.2% logic, 73.8% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_34: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R4C9C.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to SLICE_35: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R2C4B.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 58.757ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[12] (from C14M_c +) + Destination: FF Data in nRWE_0io (to C14M_c +) + + Delay: 11.193ns (30.6% logic, 69.4% route), 7 logic levels. + + Constraint Details: + + 11.193ns physical path delay SLICE_3 to nRWE_MGIOL meets + 69.930ns delay constraint less + -0.173ns skew and + 0.153ns DO_SET requirement (totaling 69.950ns) by 58.757ns + + Physical Path Details: + + Data path SLICE_3 to nRWE_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R2C8C.CLK to R2C8C.Q1 SLICE_3 (from C14M_c) +ROUTE 22 1.463 R2C8C.Q1 to R3C6A.A1 FS[12] +CTOF_DEL --- 0.495 R3C6A.A1 to R3C6A.F1 SLICE_97 +ROUTE 2 0.702 R3C6A.F1 to R3C6A.B0 N_456 +CTOF_DEL --- 0.495 R3C6A.B0 to R3C6A.F0 SLICE_97 +ROUTE 3 1.345 R3C6A.F0 to R3C9C.B1 N_489 +CTOF_DEL --- 0.495 R3C9C.B1 to R3C9C.F1 SLICE_75 +ROUTE 3 0.453 R3C9C.F1 to R3C9C.C0 N_628 +CTOF_DEL --- 0.495 R3C9C.C0 to R3C9C.F0 SLICE_75 +ROUTE 2 0.993 R3C9C.F0 to R5C9A.A1 N_640 +CTOF_DEL --- 0.495 R5C9A.A1 to R5C9A.F1 SLICE_71 +ROUTE 1 0.623 R5C9A.F1 to R5C10B.D0 un1_nCS61_1_i +CTOF_DEL --- 0.495 R5C10B.D0 to R5C10B.F0 SLICE_115 +ROUTE 1 2.192 R5C10B.F0 to IOL_R7D.OPOS nRWE_r_0 (to C14M_c) + -------- + 11.193 (30.6% logic, 69.4% route), 7 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R2C8C.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to nRWE_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.243 62.PADDI to IOL_R7D.CLK C14M_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 58.784ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q S[0] (from C14M_c +) + Destination: FF Data in wb_adr[0] (to C14M_c +) + + Delay: 10.980ns (26.7% logic, 73.3% route), 6 logic levels. + + Constraint Details: + + 10.980ns physical path delay SLICE_33 to SLICE_35 meets + 69.930ns delay constraint less + 0.000ns skew and + 0.166ns DIN_SET requirement (totaling 69.764ns) by 58.784ns + + Physical Path Details: + + Data path SLICE_33 to SLICE_35: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C9D.CLK to R4C9D.Q0 SLICE_33 (from C14M_c) +ROUTE 30 1.676 R4C9D.Q0 to R6C9B.C0 S[0] +CTOF_DEL --- 0.495 R6C9B.C0 to R6C9B.F0 SLICE_47 +ROUTE 7 2.435 R6C9B.F0 to R4C5B.B0 S_RNII9DO1[1] +CTOF_DEL --- 0.495 R4C5B.B0 to R4C5B.F0 SLICE_73 +ROUTE 8 1.931 R4C5B.F0 to R4C4C.D0 N_455 +CTOF_DEL --- 0.495 R4C4C.D0 to R4C4C.F0 SLICE_89 +ROUTE 1 0.626 R4C4C.F0 to R4C4A.D0 N_378 +CTOF_DEL --- 0.495 R4C4A.D0 to R4C4A.F0 SLICE_85 +ROUTE 1 1.385 R4C4A.F0 to R2C4B.D0 wb_adr_7_0_4[0] +CTOF_DEL --- 0.495 R2C4B.D0 to R2C4B.F0 SLICE_35 +ROUTE 1 0.000 R2C4B.F0 to R2C4B.DI0 wb_adr_7[0] (to C14M_c) + -------- + 10.980 (26.7% logic, 73.3% route), 6 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R4C9D.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to SLICE_35: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R2C4B.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 29.415ns (weighted slack = 58.830ns) + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q S[0] (from C14M_c +) + Destination: FF Data in Dout_0io[0] (to C14M_c -) + + Delay: 5.676ns (16.7% logic, 83.3% route), 2 logic levels. + + Constraint Details: + + 5.676ns physical path delay SLICE_33 to Dout[0]_MGIOL meets + 34.965ns delay constraint less + -0.173ns skew and + 0.047ns CE_SET requirement (totaling 35.091ns) by 29.415ns + + Physical Path Details: + + Data path SLICE_33 to Dout[0]_MGIOL: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.452 R4C9D.CLK to R4C9D.Q0 SLICE_33 (from C14M_c) +ROUTE 30 1.881 R4C9D.Q0 to R6C8A.A1 S[0] +CTOF_DEL --- 0.495 R6C8A.A1 to R6C8A.F1 SLICE_20 +ROUTE 17 2.848 R6C8A.F1 to IOL_B4D.CE N_576_i (to C14M_c) + -------- + 5.676 (16.7% logic, 83.3% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_33: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.070 62.PADDI to R4C9D.CLK C14M_c + -------- + 3.070 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to Dout[0]_MGIOL: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 3.243 62.PADDI to IOL_B4D.CLK C14M_c + -------- + 3.243 (0.0% logic, 100.0% route), 0 logic levels. + +Report: 79.592MHz is the maximum frequency for this preference. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY PORT "C14M" 14.300000 MHz ; | 14.300 MHz| 79.592 MHz| 7 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 1 clocks: + +Clock Domain: C14M_c Source: C14M.PAD Loads: 84 + Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; + + +Timing summary (Setup): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage) + +-------------------------------------------------------------------------------- +Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454 +Thu Sep 21 05:35:07 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +Report Information +------------------ +Command line: trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf +Design file: ram2e_lcmxo2_640hc_impl1.ncd +Preference file: ram2e_lcmxo2_640hc_impl1.prf +Device,speed: LCMXO2-640HC,m +Report level: verbose report, limited to 10 items per preference +-------------------------------------------------------------------------------- + +BLOCK ASYNCPATHS +BLOCK RESETPATHS +-------------------------------------------------------------------------------- + + + +================================================================================ +Preference: FREQUENCY PORT "C14M" 14.300000 MHz ; + 1491 items scored, 0 timing errors detected. +-------------------------------------------------------------------------------- + + +Passed: The following path meets requirements by 0.346ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_dati[3] (from C14M_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to C14M_c +) + + Delay: 0.305ns (43.6% logic, 56.4% route), 1 logic levels. + + Constraint Details: + + 0.305ns physical path delay SLICE_41 to ufmefb/EFBInst_0 meets + -0.095ns WBDATI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.041ns) by 0.346ns + + Physical Path Details: + + Data path SLICE_41 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C3B.CLK to R2C3B.Q1 SLICE_41 (from C14M_c) +ROUTE 1 0.172 R2C3B.Q1 to EFB.WBDATI3 wb_dati[3] (to C14M_c) + -------- + 0.305 (43.6% logic, 56.4% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_41: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R2C3B.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.113 62.PADDI to EFB.WBCLKI C14M_c + -------- + 1.113 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.348ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q wb_dati[4] (from C14M_c +) + Destination: EFB Port ufmefb/EFBInst_0(ASIC) (to C14M_c +) + + Delay: 0.305ns (43.6% logic, 56.4% route), 1 logic levels. + + Constraint Details: + + 0.305ns physical path delay SLICE_42 to ufmefb/EFBInst_0 meets + -0.097ns WBDATI_HLD and + 0.000ns delay constraint less + -0.054ns skew requirement (totaling -0.043ns) by 0.348ns + + Physical Path Details: + + Data path SLICE_42 to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C3D.CLK to R2C3D.Q0 SLICE_42 (from C14M_c) +ROUTE 1 0.172 R2C3D.Q0 to EFB.WBDATI4 wb_dati[4] (to C14M_c) + -------- + 0.305 (43.6% logic, 56.4% route), 1 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_42: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R2C3D.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to ufmefb/EFBInst_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.113 62.PADDI to EFB.WBCLKI C14M_c + -------- + 1.113 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[0] (from C14M_c +) + Destination: FF Data in FS[0] (to C14M_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_0 to SLICE_0 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_0 to SLICE_0: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C7A.CLK to R2C7A.Q1 SLICE_0 (from C14M_c) +ROUTE 5 0.132 R2C7A.Q1 to R2C7A.A1 FS[0] +CTOF_DEL --- 0.101 R2C7A.A1 to R2C7A.F1 SLICE_0 +ROUTE 1 0.000 R2C7A.F1 to R2C7A.DI1 FS_s[0] (to C14M_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R2C7A.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to SLICE_0: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R2C7A.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdBitbangMXO2 (from C14M_c +) + Destination: FF Data in CmdBitbangMXO2 (to C14M_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_12 to SLICE_12 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_12 to SLICE_12: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R4C6C.CLK to R4C6C.Q0 SLICE_12 (from C14M_c) +ROUTE 2 0.132 R4C6C.Q0 to R4C6C.A0 CmdBitbangMXO2 +CTOF_DEL --- 0.101 R4C6C.A0 to R4C6C.F0 SLICE_12 +ROUTE 1 0.000 R4C6C.F0 to R4C6C.DI0 CmdBitbangMXO2_4 (to C14M_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_12: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R4C6C.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to SLICE_12: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R4C6C.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdLEDSet (from C14M_c +) + Destination: FF Data in CmdLEDSet (to C14M_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_15 to SLICE_15 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_15 to SLICE_15: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C5B.CLK to R5C5B.Q0 SLICE_15 (from C14M_c) +ROUTE 2 0.132 R5C5B.Q0 to R5C5B.A0 CmdLEDSet +CTOF_DEL --- 0.101 R5C5B.A0 to R5C5B.F0 SLICE_15 +ROUTE 1 0.000 R5C5B.F0 to R5C5B.DI0 CmdLEDSet_4 (to C14M_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R5C5B.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to SLICE_15: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R5C5B.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdRWMaskSet (from C14M_c +) + Destination: FF Data in CmdRWMaskSet (to C14M_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_16 to SLICE_16 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_16 to SLICE_16: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R5C5C.CLK to R5C5C.Q0 SLICE_16 (from C14M_c) +ROUTE 2 0.132 R5C5C.Q0 to R5C5C.A0 CmdRWMaskSet +CTOF_DEL --- 0.101 R5C5C.A0 to R5C5C.F0 SLICE_16 +ROUTE 1 0.000 R5C5C.F0 to R5C5C.DI0 CmdRWMaskSet_4 (to C14M_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R5C5C.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to SLICE_16: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R5C5C.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdSetRWBankFFLED (from C14M_c +) + Destination: FF Data in CmdSetRWBankFFLED (to C14M_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_17 to SLICE_17 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_17 to SLICE_17: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C5C.CLK to R6C5C.Q0 SLICE_17 (from C14M_c) +ROUTE 2 0.132 R6C5C.Q0 to R6C5C.A0 CmdSetRWBankFFLED +CTOF_DEL --- 0.101 R6C5C.A0 to R6C5C.F0 SLICE_17 +ROUTE 1 0.000 R6C5C.F0 to R6C5C.DI0 CmdSetRWBankFFLED_4 (to C14M_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R6C5C.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to SLICE_17: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R6C5C.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q CmdSetRWBankFFMXO2 (from C14M_c +) + Destination: FF Data in CmdSetRWBankFFMXO2 (to C14M_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_18 to SLICE_18 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_18 to SLICE_18: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R6C6D.CLK to R6C6D.Q0 SLICE_18 (from C14M_c) +ROUTE 2 0.132 R6C6D.Q0 to R6C6D.A0 CmdSetRWBankFFMXO2 +CTOF_DEL --- 0.101 R6C6D.A0 to R6C6D.F0 SLICE_18 +ROUTE 1 0.000 R6C6D.F0 to R6C6D.DI0 CmdSetRWBankFFMXO2_4 (to C14M_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R6C6D.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to SLICE_18: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R6C6D.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q FS[11] (from C14M_c +) + Destination: FF Data in FS[11] (to C14M_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_3 to SLICE_3 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_3 to SLICE_3: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C8C.CLK to R2C8C.Q0 SLICE_3 (from C14M_c) +ROUTE 19 0.132 R2C8C.Q0 to R2C8C.A0 FS[11] +CTOF_DEL --- 0.101 R2C8C.A0 to R2C8C.F0 SLICE_3 +ROUTE 1 0.000 R2C8C.F0 to R2C8C.DI0 FS_s[11] (to C14M_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R2C8C.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to SLICE_3: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R2C8C.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + +Passed: The following path meets requirements by 0.379ns + + Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) + + Source: FF Q Ready (from C14M_c +) + Destination: FF Data in Ready (to C14M_c +) + + Delay: 0.366ns (63.9% logic, 36.1% route), 2 logic levels. + + Constraint Details: + + 0.366ns physical path delay SLICE_32 to SLICE_32 meets + -0.013ns DIN_HLD and + 0.000ns delay constraint less + 0.000ns skew requirement (totaling -0.013ns) by 0.379ns + + Physical Path Details: + + Data path SLICE_32 to SLICE_32: + + Name Fanout Delay (ns) Site Resource +REG_DEL --- 0.133 R2C9C.CLK to R2C9C.Q0 SLICE_32 (from C14M_c) +ROUTE 2 0.132 R2C9C.Q0 to R2C9C.A0 Ready +CTOF_DEL --- 0.101 R2C9C.A0 to R2C9C.F0 SLICE_32 +ROUTE 1 0.000 R2C9C.F0 to R2C9C.DI0 N_876_0 (to C14M_c) + -------- + 0.366 (63.9% logic, 36.1% route), 2 logic levels. + + Clock Skew Details: + + Source Clock Path C14M to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R2C9C.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + + Destination Clock Path C14M to SLICE_32: + + Name Fanout Delay (ns) Site Resource +ROUTE 84 1.059 62.PADDI to R2C9C.CLK C14M_c + -------- + 1.059 (0.0% logic, 100.0% route), 0 logic levels. + +Report Summary +-------------- +---------------------------------------------------------------------------- +Preference(MIN Delays) | Constraint| Actual|Levels +---------------------------------------------------------------------------- + | | | +FREQUENCY PORT "C14M" 14.300000 MHz ; | -| -| 1 + | | | +---------------------------------------------------------------------------- + + +All preferences were met. + + +Clock Domains Analysis +------------------------ + +Found 1 clocks: + +Clock Domain: C14M_c Source: C14M.PAD Loads: 84 + Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ; + + +Timing summary (Hold): +--------------- + +Timing errors: 0 Score: 0 +Cumulative negative slack: 0 + +Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage) + + + +Timing summary (Setup and Hold): +--------------- + +Timing errors: 0 (setup), 0 (hold) +Score: 0 (setup), 0 (hold) +Cumulative negative slack: 0 (0+0) +-------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------- + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html new file mode 100644 index 0000000..b99737b --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_bgn.html @@ -0,0 +1,142 @@ + +Bitgen Report + + +
    BITGEN: Bitstream Generator Diamond (64-bit) 3.12.1.454
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Sep 21 05:35:15 2023
+
+
+Command: bitgen -g RamCfg:Reset -path //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC -w -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+
+Loading design for application Bitgen from file RAM2E_LCMXO2_640HC_impl1.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application Bitgen from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+
+Running DRC.
+DRC detected 0 errors and 0 warnings.
+Reading Preference File from RAM2E_LCMXO2_640HC_impl1.prf.
+
+
+Preference Summary:
+
++---------------------------------+---------------------------------+
+|  Preference                     |  Current Setting                |
++---------------------------------+---------------------------------+
+|                         RamCfg  |                        Reset**  |
++---------------------------------+---------------------------------+
+|                     MCCLK_FREQ  |                         2.08**  |
++---------------------------------+---------------------------------+
+|                  CONFIG_SECURE  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                          INBUF  |                           ON**  |
++---------------------------------+---------------------------------+
+|                      JTAG_PORT  |                       ENABLE**  |
++---------------------------------+---------------------------------+
+|                       SDM_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                 SLAVE_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                MASTER_SPI_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                       I2C_PORT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  CONFIGURATION  |                          CFG**  |
++---------------------------------+---------------------------------+
+|                COMPRESS_CONFIG  |                           ON**  |
++---------------------------------+---------------------------------+
+|                        MY_ASSP  |                          OFF**  |
++---------------------------------+---------------------------------+
+|               ONE_TIME_PROGRAM  |                          OFF**  |
++---------------------------------+---------------------------------+
+|                 ENABLE_TRANSFR  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|                  SHAREDEBRINIT  |                      DISABLE**  |
++---------------------------------+---------------------------------+
+|            BACKGROUND_RECONFIG  |                          OFF**  |
++---------------------------------+---------------------------------+
+ *  Default setting.
+ ** The specified setting matches the default setting.
+
+
+Creating bit map...
+ 
+Bitstream Status: Final           Version 1.95.
+ 
+Saving bit stream in "RAM2E_LCMXO2_640HC_impl1.bit".
+Total CPU Time: 4 secs 
+Total REAL Time: 5 secs 
+Peak Memory Usage: 267 MB
+
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    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt new file mode 100644 index 0000000..0d70461 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_cck.rpt @@ -0,0 +1,152 @@ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 + +# Written on Thu Sep 21 05:34:37 2023 + +##### DESIGN INFO ####################################################### + +Top View: "RAM2E" +Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc" + + + + +##### SUMMARY ############################################################ + +Found 0 issues in 0 out of 1 constraints + + +##### DETAILS ############################################################ + + + +Clock Relationships +******************* + +Starting Ending | rise to rise | fall to fall | rise to fall | fall to rise +----------------------------------------------------------------------------------------------------------------------------------- +System C14M | 69.841 | No paths | No paths | No paths +C14M System | 69.841 | No paths | No paths | No paths +C14M C14M | 69.841 | No paths | 34.920 | No paths +=================================================================================================================================== + Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. + 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. + + +Unconstrained Start/End Points +****************************** + +p:Ain[0] +p:Ain[1] +p:Ain[2] +p:Ain[3] +p:Ain[4] +p:Ain[5] +p:Ain[6] +p:Ain[7] +p:BA[0] +p:BA[1] +p:CKE +p:DQMH +p:DQML +p:Din[0] +p:Din[1] +p:Din[2] +p:Din[3] +p:Din[4] +p:Din[5] +p:Din[6] +p:Din[7] +p:Dout[0] +p:Dout[1] +p:Dout[2] +p:Dout[3] +p:Dout[4] +p:Dout[5] +p:Dout[6] +p:Dout[7] +p:LED +p:PHI1 +p:RA[0] +p:RA[1] +p:RA[2] +p:RA[3] +p:RA[4] +p:RA[5] +p:RA[6] +p:RA[7] +p:RA[8] +p:RA[9] +p:RA[10] +p:RA[11] +p:RD[0] (bidir end point) +p:RD[0] (bidir start point) +p:RD[1] (bidir end point) +p:RD[1] (bidir start point) +p:RD[2] (bidir end point) +p:RD[2] (bidir start point) +p:RD[3] (bidir end point) +p:RD[3] (bidir start point) +p:RD[4] (bidir end point) +p:RD[4] (bidir start point) +p:RD[5] (bidir end point) +p:RD[5] (bidir start point) +p:RD[6] (bidir end point) +p:RD[6] (bidir start point) +p:RD[7] (bidir end point) +p:RD[7] (bidir start point) +p:Vout[0] +p:Vout[1] +p:Vout[2] +p:Vout[3] +p:Vout[4] +p:Vout[5] +p:Vout[6] +p:Vout[7] +p:nC07X +p:nCAS +p:nCS +p:nDOE +p:nEN80 +p:nRAS +p:nRWE +p:nVOE +p:nWE +p:nWE80 + + +Inapplicable constraints +************************ + +(none) + + +Applicable constraints with issues +********************************** + +(none) + + +Constraints with matching wildcard expressions +********************************************** + +(none) + + +Library Report +************** + + +# End of Constraint Checker Report diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_iotiming.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_iotiming.html new file mode 100644 index 0000000..d93cff5 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_iotiming.html @@ -0,0 +1,183 @@ + +I/O Timing Report + + +
    I/O Timing Report
+Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 5
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 6
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: M
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+// Design: RAM2E
+// Package: TQFP100
+// ncd File: ram2e_lcmxo2_640hc_impl1.ncd
+// Version: Diamond (64-bit) 3.12.1.454
+// Written on Thu Sep 21 05:35:10 2023
+// M: Minimum Performance Grade
+// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
+
+I/O Timing Report (All units are in ns)
+
+Worst Case Results across Performance Grades (M, 6, 5, 4):
+
+// Input Setup and Hold Times
+
+Port   Clock Edge  Setup Performance_Grade  Hold Performance_Grade
+----------------------------------------------------------------------
+Ain[0] C14M  R     0.502      4       0.868     4
+Ain[1] C14M  R     2.364      4      -0.126     M
+Ain[2] C14M  R     2.421      4      -0.129     M
+Ain[3] C14M  R     0.574      4       0.786     4
+Ain[4] C14M  R     1.452      4       0.140     M
+Ain[5] C14M  R     2.076      4      -0.039     M
+Ain[6] C14M  R     1.515      4       0.124     M
+Ain[7] C14M  R     2.270      4      -0.095     M
+Din[0] C14M  R     9.252      4       1.162     4
+Din[1] C14M  R     8.868      4       0.657     4
+Din[2] C14M  R     8.368      4       0.864     4
+Din[3] C14M  R     8.749      4       1.339     4
+Din[4] C14M  R     9.095      4       0.770     4
+Din[5] C14M  R     8.195      4       1.176     4
+Din[6] C14M  R     6.162      4       0.760     4
+Din[7] C14M  R     7.060      4       1.093     4
+PHI1   C14M  R     2.045      4       3.047     4
+RD[0]  C14M  F     0.267      4       0.866     4
+RD[1]  C14M  F     0.173      4       1.383     4
+RD[2]  C14M  F     0.924      4       1.018     4
+RD[3]  C14M  F     0.267      4       0.866     4
+RD[4]  C14M  F     0.173      4       0.937     4
+RD[5]  C14M  F     0.267      4       0.866     4
+RD[6]  C14M  F     0.766      4       0.866     4
+RD[7]  C14M  F     0.267      4       1.312     4
+nC07X  C14M  R     0.077      4       1.144     4
+nEN80  C14M  R     6.415      4      -0.286     M
+nWE    C14M  R     0.691      4       0.684     4
+nWE80  C14M  R     2.845      4      -0.260     M
+
+
+// Clock to Output Delay
+
+Port    Clock Edge  Max_Delay Performance_Grade  Min_Delay Performance_Grade
+------------------------------------------------------------------------
+BA[0]   C14M  R     8.629         4        2.885          M
+BA[1]   C14M  R     8.629         4        2.885          M
+CKE     C14M  R     8.629         4        2.885          M
+DQMH    C14M  R     8.609         4        2.892          M
+DQML    C14M  R     8.609         4        2.892          M
+Dout[0] C14M  F     8.955         4        3.164          M
+Dout[1] C14M  F     8.955         4        3.164          M
+Dout[2] C14M  F     8.944         4        3.158          M
+Dout[3] C14M  F     8.955         4        3.164          M
+Dout[4] C14M  F     8.944         4        3.158          M
+Dout[5] C14M  F     8.944         4        3.158          M
+Dout[6] C14M  F     8.955         4        3.164          M
+Dout[7] C14M  F     8.955         4        3.164          M
+LED     C14M  R    19.941         4        8.191          M
+RA[0]   C14M  R    10.013         4        3.186          M
+RA[10]  C14M  R     8.629         4        2.885          M
+RA[11]  C14M  R     8.629         4        2.885          M
+RA[1]   C14M  R     8.695         4        2.890          M
+RA[2]   C14M  R     8.695         4        2.890          M
+RA[3]   C14M  R    10.013         4        3.186          M
+RA[4]   C14M  R     8.695         4        2.890          M
+RA[5]   C14M  R     8.695         4        2.890          M
+RA[6]   C14M  R     8.695         4        2.890          M
+RA[7]   C14M  R     8.695         4        2.890          M
+RA[8]   C14M  R     8.629         4        2.885          M
+RA[9]   C14M  R     8.629         4        2.885          M
+Vout[0] C14M  F     9.553         4        3.402          M
+Vout[1] C14M  F     9.553         4        3.402          M
+Vout[2] C14M  F     9.553         4        3.402          M
+Vout[3] C14M  F     9.553         4        3.402          M
+Vout[4] C14M  F     9.553         4        3.402          M
+Vout[5] C14M  F     9.553         4        3.402          M
+Vout[6] C14M  F     9.553         4        3.402          M
+Vout[7] C14M  F     9.553         4        3.402          M
+nCAS    C14M  R     8.629         4        2.885          M
+nCS     C14M  R     8.629         4        2.885          M
+nDOE    C14M  R    11.976         4        3.776          M
+nRAS    C14M  R     8.629         4        2.885          M
+nRWE    C14M  R     8.629         4        2.885          M
+WARNING: you must also run trce with hold speed: 4
+
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    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf new file mode 100644 index 0000000..85e4f67 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.sdf @@ -0,0 +1,4852 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2E") + (DATE "Thu Sep 21 05:34:50 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + 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(CELLTYPE "Ain_3_") + (INSTANCE Ain\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain3 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain3) (3330:3330:3330)) + (WIDTH (negedge Ain3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_2_") + (INSTANCE Ain\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain2 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain2) (3330:3330:3330)) + (WIDTH (negedge Ain2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_1_") + (INSTANCE Ain\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain1) (3330:3330:3330)) + (WIDTH (negedge Ain1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_0_") + (INSTANCE Ain\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain0) (3330:3330:3330)) + (WIDTH (negedge Ain0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nC07X") + (INSTANCE nC07X_I) + (DELAY + (ABSOLUTE + (IOPATH nC07X PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nC07X) (3330:3330:3330)) + (WIDTH (negedge nC07X) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nEN80") + (INSTANCE nEN80_I) + (DELAY + (ABSOLUTE + (IOPATH nEN80 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nEN80) (3330:3330:3330)) + (WIDTH (negedge nEN80) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nWE80") + (INSTANCE nWE80_I) + (DELAY + (ABSOLUTE + (IOPATH nWE80 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nWE80) (3330:3330:3330)) + (WIDTH (negedge nWE80) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nWE") + (INSTANCE nWE_I) + (DELAY + (ABSOLUTE + (IOPATH nWE PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nWE) (3330:3330:3330)) + (WIDTH (negedge nWE) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "PHI1") + (INSTANCE PHI1_I) + (DELAY + (ABSOLUTE + (IOPATH PHI1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI1) (3330:3330:3330)) + (WIDTH (negedge PHI1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "PHI1_MGIOL") + (INSTANCE PHI1_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "EFB_Buffer_Block") + (INSTANCE ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20) + (DELAY + (ABSOLUTE + (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278)) + (IOPATH WBCLKIin WBDATO1out (947:3204:5461)(947:3204:5461)) + (IOPATH WBCLKIin WBDATO2out (955:3211:5468)(955:3211:5468)) + (IOPATH WBCLKIin WBDATO3out (910:3173:5436)(910:3173:5436)) + (IOPATH WBCLKIin WBDATO4out (944:3217:5491)(944:3217:5491)) + (IOPATH WBCLKIin WBDATO5out (917:3672:6428)(917:3672:6428)) + (IOPATH WBCLKIin WBDATO6out (926:3191:5457)(926:3191:5457)) + (IOPATH WBCLKIin WBDATO7out (939:3201:5464)(939:3201:5464)) + (IOPATH WBCLKIin WBACKOout (903:1623:2343)(903:1623:2343)) + ) + ) + (TIMINGCHECK + (SETUPHOLD WBRSTIin (posedge WBCLKIin) (3138:3170:3203)(-3138:-1966:-794)) + (SETUPHOLD WBCYCIin (posedge WBCLKIin) (2616:2649:2682)(-2616:-1558:-501)) + (SETUPHOLD WBSTBIin (posedge WBCLKIin) (2605:2637:2670)(-2605:-1494:-384)) + (SETUPHOLD WBWEIin (posedge WBCLKIin) (1409:1442:1475)(-1409:-837:-266)) + (SETUPHOLD WBADRI0in (posedge WBCLKIin) (2058:2123:2188)(-2058:-1191:-324)) + (SETUPHOLD WBADRI1in (posedge WBCLKIin) (2068:2104:2140)(-2068:-1234:-401)) + (SETUPHOLD WBADRI2in (posedge WBCLKIin) (1928:1993:2058)(-1928:-1110:-292)) + (SETUPHOLD WBADRI3in (posedge WBCLKIin) (2167:2196:2226)(-2167:-1264:-361)) + (SETUPHOLD WBADRI4in (posedge WBCLKIin) (2072:2101:2130)(-2072:-1198:-324)) + (SETUPHOLD WBADRI5in (posedge WBCLKIin) (1611:1640:1670)(-1611:-950:-289)) + (SETUPHOLD WBADRI6in (posedge WBCLKIin) (2532:2564:2597)(-2532:-1380:-229)) + (SETUPHOLD WBADRI7in (posedge WBCLKIin) (2519:2551:2584)(-2519:-1377:-235)) + (SETUPHOLD WBDATI0in (posedge WBCLKIin) (1057:1262:1467)(-1037:-712:-388)) + (SETUPHOLD WBDATI1in (posedge WBCLKIin) (1114:1338:1563)(-1108:-785:-462)) + (SETUPHOLD WBDATI2in (posedge WBCLKIin) (916:1076:1237)(-912:-636:-360)) + (SETUPHOLD WBDATI3in (posedge WBCLKIin) (1145:1359:1573)(-1115:-782:-449)) + (SETUPHOLD WBDATI4in (posedge WBCLKIin) (1192:1400:1609)(-1176:-820:-464)) + (SETUPHOLD WBDATI5in (posedge WBCLKIin) (1027:1222:1418)(-1000:-706:-413)) + (SETUPHOLD WBDATI6in (posedge WBCLKIin) (1034:1248:1463)(-1034:-756:-479)) + (SETUPHOLD WBDATI7in (posedge WBCLKIin) (528:614:701)(-528:-398:-268)) + ) + (TIMINGCHECK + (WIDTH (posedge WBCLKIin) (4887:4887:4887)) + (WIDTH (negedge WBCLKIin) (4887:4887:4887)) + ) + ) + (CELL + (CELLTYPE "RAM2E") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_39/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_52/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_75/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/Q1 SLICE_119/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_0/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_1/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_2/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_3/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_4/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_5/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_6/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_7/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_9/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_11/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_13/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_14/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_15/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_16/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_17/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_23/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_24/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_25/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_26/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_27/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_28/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_29/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_30/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_31/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_32/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_33/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_39/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_44/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_45/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_46/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI DQMH_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI DQML_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[11\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[10\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[9\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[8\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[7\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[6\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[5\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[4\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[2\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI RA\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI BA\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI BA\[0\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI nRWE_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI nCAS_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI nRAS_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI nCS_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI CKE_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Vout\[7\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Vout\[6\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Vout\[5\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Vout\[4\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Vout\[3\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Vout\[2\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Vout\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Vout\[0\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Dout\[7\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Dout\[6\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Dout\[5\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Dout\[4\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Dout\[3\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Dout\[2\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Dout\[1\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI Dout\[0\]_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI PHI1_MGIOL/CLK (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_45/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_51/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_53/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_56/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_72/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_73/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_75/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_83/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_86/B1 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(INTERCONNECT SLICE_63/F0 SLICE_63/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_63/F0 SLICE_76/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_55/F1 SLICE_83/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F1 SLICE_56/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F1 SLICE_85/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F1 SLICE_88/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F1 SLICE_92/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F1 SLICE_109/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_56/F1 SLICE_109/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_58/F0 SLICE_58/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/F0 SLICE_58/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_70/F0 SLICE_70/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_58/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_68/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_70/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_73/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_84/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_89/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_114/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F0 SLICE_114/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F0 SLICE_59/A1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_59/F1 DQML_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_60/F0 SLICE_60/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_60/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_64/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_95/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F1 SLICE_97/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_60/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_88/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_105/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_88/F1 SLICE_105/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F0 SLICE_61/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F0 SLICE_88/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F0 SLICE_114/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_61/F1 SLICE_109/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_62/F0 SLICE_62/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_64/F0 SLICE_114/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_65/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F1 SLICE_84/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_65/F0 SLICE_109/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_66/F0 SLICE_95/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_69/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_78/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_76/F0 SLICE_115/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F0 SLICE_69/B1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_69/F1 RA\[10\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_71/C1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F0 SLICE_78/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_71/F1 SLICE_115/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_119/F0 SLICE_72/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_116/F1 SLICE_73/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_116/F1 SLICE_92/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_73/F1 SLICE_85/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 SLICE_75/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 SLICE_76/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_75/F1 SLICE_83/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F0 SLICE_77/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_82/F0 SLICE_77/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F0 SLICE_77/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F1 SLICE_78/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_78/F0 nCAS_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F1 SLICE_79/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_79/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F0 SLICE_80/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_79/F0 nCS_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_80/F0 nRAS_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_81/F1 SLICE_81/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F0 SLICE_82/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F0 SLICE_82/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_83/F1 SLICE_83/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_112/F1 SLICE_83/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_84/F1 SLICE_84/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_108/F1 SLICE_85/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_85/F1 SLICE_85/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F0 SLICE_85/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_89/F0 SLICE_85/B0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_105/F1 SLICE_86/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_98/F0 SLICE_87/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_87/F1 SLICE_87/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_90/F1 SLICE_90/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_99/F0 SLICE_91/D1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_91/F1 SLICE_91/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_92/F1 SLICE_92/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_93/F1 SLICE_93/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_94/F1 SLICE_94/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_95/F1 SLICE_95/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_96/F0 RA\[8\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 SLICE_97/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_97/F1 SLICE_116/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_118/F1 SLICE_98/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_118/F1 SLICE_99/C0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 BA\[1\]_MGIOL/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_101/F1 BA\[0\]_MGIOL/LSR (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_102/F0 BA\[0\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_103/F1 RA\[11\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_107/F0 BA\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_110/F1 RA\[9\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Ain\[5\]_I/PADDI SLICE_111/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Ain\[4\]_I/PADDI SLICE_111/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_111/F0 RA\[4\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_111/F1 RA\[5\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Ain\[6\]_I/PADDI SLICE_112/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_112/F0 RA\[6\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT Ain\[2\]_I/PADDI SLICE_113/A1 (0:0:0)(0:0:0)) + (INTERCONNECT Ain\[7\]_I/PADDI SLICE_113/A0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_113/F0 RA\[7\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_113/F1 RA\[2\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT nWE80_I/PADDI SLICE_115/B1 (0:0:0)(0:0:0)) + (INTERCONNECT nWE80_I/PADDI SLICE_115/D0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F0 nRWE_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F1 RD\[0\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F1 RD\[7\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F1 RD\[6\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F1 RD\[5\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F1 RD\[4\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F1 RD\[3\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F1 RD\[2\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_115/F1 RD\[1\]_I/PADDT (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_117/F0 LED_I/PADDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_I/PADDI Vout\[0\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_MGIOL/OPOS (0:0:0)(0:0:0)) + (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[9\]_MGIOL/IOLDO RA\[9\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[8\]_MGIOL/IOLDO RA\[8\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[7\]_MGIOL/IOLDO RA\[7\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[6\]_MGIOL/IOLDO RA\[6\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[5\]_MGIOL/IOLDO RA\[5\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[4\]_MGIOL/IOLDO RA\[4\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[2\]_MGIOL/IOLDO RA\[2\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT RA\[1\]_MGIOL/IOLDO RA\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nCAS_MGIOL/IOLDO nCAS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nRAS_MGIOL/IOLDO nRAS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT nCS_MGIOL/IOLDO nCS_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT CKE_MGIOL/IOLDO CKE_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[4\]_MGIOL/IOLDO Vout\[4\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[3\]_MGIOL/IOLDO Vout\[3\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[7\]_MGIOL/IOLDO Dout\[7\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[6\]_MGIOL/IOLDO Dout\[6\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[5\]_MGIOL/IOLDO Dout\[5\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[4\]_MGIOL/IOLDO Dout\[4\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[3\]_MGIOL/IOLDO Dout\[3\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[2\]_MGIOL/IOLDO Dout\[2\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[1\]_MGIOL/IOLDO Dout\[1\]_I/IOLDO (0:0:0)(0:0:0)) + (INTERCONNECT Dout\[0\]_MGIOL/IOLDO Dout\[0\]_I/IOLDO (0:0:0)(0:0:0)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo new file mode 100644 index 0000000..6a9b257 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mapvo.vo @@ -0,0 +1,5908 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_mapvo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd +// Netlist created on Thu Sep 21 05:34:46 2023 +// Netlist written on Thu Sep 21 05:34:50 2023 +// Design is for device LCMXO2-640HC +// Design is for package TQFP100 +// Design is for performance grade 4 + +`timescale 1 ns / 1 ps + +module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, + Vout, nVOE, CKE, nCS, nRAS, nCAS, nRWE, BA, RA, RD, DQML, DQMH ); + input C14M, PHI1, nWE, nWE80, nEN80, nC07X; + input [7:0] Ain; + input [7:0] Din; + output LED; + output [7:0] Dout; + output nDOE; + output [7:0] Vout; + output nVOE, CKE, nCS, nRAS, nCAS, nRWE; + output [1:0] BA; + output [11:0] RA; + output DQML, DQMH; + inout [7:0] RD; + wire \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , + \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , + \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , + \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , + \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , + \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , + \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , Ready, + PHI1reg, PHI1_c, RWSel, CO0_1, \CmdTout_3[0] , N_576_i, S_1, \CS[0] , + N_461, \S_RNII9DO1_0[1] , \CS[1] , N_511_i, N_504_i, + un1_CS_0_sqmuxa_i, N_637, \CS[2] , N_510_i, \Din_c[3] , \Din_c[2] , + \Din_c[0] , N_643, CmdBitbangMXO2_4_u_0_0_a2_0_1, CmdBitbangMXO2, + CmdBitbangMXO2_4, \Din_c[7] , \Din_c[5] , N_629, CmdExecMXO2, + CmdExecMXO2_4, N_466, N_478, \Din_c[4] , \Din_c[1] , N_476, + CmdLEDGet_4_u_0_0_a2_0_2, CmdLEDGet, CmdLEDGet_4, N_626, N_605, + CmdLEDSet, CmdLEDSet_4, CmdRWMaskSet, CmdRWMaskSet_4, N_401, + CmdSetRWBankFFLED, CmdSetRWBankFFLED_4, N_474, + CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0, CmdSetRWBankFFMXO2, + CmdSetRWBankFFMXO2_4, \CmdTout[1] , \CmdTout[2] , N_556_i, N_555_i, + \S[0] , \S[1] , \S[2] , \S[3] , N_6_i, DOEEN, \Ain_c[1] , + \wb_dato[0] , LEDEN_RNO, \un1_LEDEN_0_sqmuxa_1_i_0[0] , LEDEN, + N_558_i, \Ain_c[3] , \Ain_c[0] , N_552_i, N_127_i, \S_RNII9DO1_1[1] , + \RA_c[0] , \RA_c[3] , \RWMask[1] , N_591, \RWMask[0] , \RWBank_5[1] , + \RWBank_5[0] , LEDEN13, \RWBank[0] , \RWBank[1] , \RWMask[3] , + \RWMask[2] , \RWBank_5[3] , \RWBank_5[2] , \RWBank[2] , \RWBank[3] , + \RWMask[5] , \RWMask[4] , \RWBank_5[5] , \RWBank_5[4] , \RWBank[4] , + \RWBank[5] , \RWMask[7] , \RWMask[6] , \Din_c[6] , \RWBank_5[7] , + \RWBank_5[6] , \RWBank[6] , \RWBank[7] , \wb_dato[1] , N_291_i, + N_292_i, N_88, \wb_dato[3] , \wb_dato[2] , N_289_i, N_290_i, + \wb_dato[5] , \wb_dato[4] , N_287_i, N_288_i, \wb_dato[7] , + \wb_dato[6] , N_285, N_286_i, nWE_c, nEN80_c, nC07X_c, RWSel_2, nCS61, + nDOE_c, Ready_0_sqmuxa_0_a2_6_a2_4, N_489, Ready_0_sqmuxa, N_876_0, + wb_reqc_1, N_575, N_572, \S_s_0_1[0] , N_133_i, \S_s_0[0] , N_129_i, + N_131_i, wb_adr_7_5_214_0_1, N_388, \wb_adr_7_0_4[0] , N_642, N_376, + \wb_adr_RNO[1] , \wb_adr_7[0] , \un1_wb_adr_0_sqmuxa_2_i[0] , + \wb_adr[0] , \wb_adr[1] , N_41_i, N_43_i, \wb_adr[2] , \wb_adr[3] , + N_295, N_294, \wb_adr[4] , \wb_adr[5] , N_39_i, N_296, \wb_adr[6] , + \wb_adr[7] , wb_ack, N_300, N_395, wb_cyc_stb_RNO, N_104, wb_cyc_stb, + \wb_dati_7_0_0[1] , N_627, N_621, N_336, \wb_dati_7_0_a2_1[0] , N_484, + \wb_dati_7[1] , \wb_dati_7[0] , \wb_dati[0] , \wb_dati[1] , + \wb_dati_7_0_2[3] , \wb_dati_7_0_0[3] , \wb_dati_7_0_o2_0[2] , N_345, + \wb_dati_7[3] , \wb_dati_7[2] , \wb_dati[2] , \wb_dati[3] , + \wb_dati_7_0_0[4] , N_349, N_346, \wb_dati_7[5] , \wb_dati_7[4] , + \wb_dati[4] , \wb_dati[5] , \wb_dati_7_0_0[7] , \wb_dati_7_0_RNO[7] , + N_424, N_422, \wb_dati_7_0_1[6] , \wb_dati_7[7] , \wb_dati_7[6] , + \wb_dati[6] , \wb_dati[7] , N_397, wb_reqc_i, wb_adr_0_sqmuxa_i, + wb_req, wb_rst8, \S_RNII9DO1[1] , wb_rst, N_586, wb_we_7_iv_0_0_0_1, + N_584, N_475, wb_we_RNO, \un1_wb_cyc_stb_0_sqmuxa_1_i[0] , wb_we, + N_255, N_358_i, N_635, N_254, Vout3, nCAS_s_i_tz_0, + un1_CS_0_sqmuxa_0_0_a2_1_4, N_327, un1_CS_0_sqmuxa_0_0_0, + \wb_dati_7_0_a2_0_1[7] , N_579, CKE_6_iv_i_a2_0, CKE_6_iv_i_0_1, + CKE_6_iv_i_0, N_449, N_365, N_364, \un1_wb_adr_0_sqmuxa_2_1[0] , + N_623, N_616, N_279, N_633, N_264, N_570, N_452, + \wb_dati_7_0_a2_2_1[3] , N_644, N_455, DQML_s_i_a2_0, N_28_i, + wb_adr_7_5_214_a2_2_0, N_577, N_569, N_634, \wb_dati_7_0_a2_2_0[1] , + N_265_i, \un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] , \wb_dati_7_0_a2_0[6] , + \wb_dati_7_0_a2_4_0[7] , N_393, nCAS_0_sqmuxa, N_639, \RA_42[10] , + N_640, un1_nCS61_1_i, Ready_0_sqmuxa_0_a2_6_a2_2, N_562, N_377, N_628, + un1_CS_0_sqmuxa_0_0_a2_3_2, un1_CS_0_sqmuxa_0_0_3, + un1_CS_0_sqmuxa_0_0_2, N_567, N_561_i, nCS_6_u_i_0, N_559_1, N_559_i, + nRAS_2_iv_i, un1_CS_0_sqmuxa_0_0_a2_1, N_330, N_328, nCS_6_u_i_a2_1, + N_429, N_351, \wb_adr_7_0_a2_5_0[0] , \wb_adr_7_0_1[0] , + \wb_adr_7_0_0[0] , N_378, \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] , + un1_CS_0_sqmuxa_0_0_a2_4_2, un1_CS_0_sqmuxa_0_0_a2_4_4, N_565, + un1_CS_0_sqmuxa_0_0_a2_2_2, un1_CS_0_sqmuxa_0_0_a2_2_4, + \wb_adr_7_0_a2_0[0] , un1_CS_0_sqmuxa_0_0_a2_1_2, + un1_CS_0_sqmuxa_0_0_a2_3_0, N_394, N_49_i, N_456, N_477, N_566_i, + \BA_4[0] , \RA_42[11] , \BA_4[1] , N_59_i, \Ain_c[5] , \Ain_c[4] , + N_551_i, \RA_42_3_0[5] , \Ain_c[6] , N_550_i, \Ain_c[2] , \Ain_c[7] , + N_549_i, N_553_i, nWE80_c, nRWE_r_0, RDOE_i, LED_c, \RD_in[0] , + DQMH_c, DQML_c, \RD_in[7] , \RD_in[6] , \RD_in[5] , \RD_in[4] , + \RD_in[3] , \RD_in[2] , \RD_in[1] , \RA_c[11] , \RA_c[10] , \RA_c[9] , + \RA_c[8] , \RA_c[7] , \RA_c[6] , \RA_c[5] , \RA_c[4] , \RA_c[2] , + \RA_c[1] , \BA_c[1] , \BA_c[0] , nRWE_c, nCAS_c, nRAS_c, nCS_c, CKE_c, + \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , \Vout_c[4] , \Vout_c[3] , + \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , \Dout_c[7] , \Dout_c[6] , + \Dout_c[5] , \Dout_c[4] , \Dout_c[3] , \Dout_c[2] , \Dout_c[1] , + \Dout_c[0] , VCCI; + + SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), + .Q1(\FS[0] ), .FCO(\FS_cry[0] )); + SLICE_1 SLICE_1( .A0(\FS[15] ), .DI0(\FS_s[15] ), .CLK(C14M_c), + .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), .Q0(\FS[15] )); + SLICE_2 SLICE_2( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), + .DI0(\FS_s[13] ), .CLK(C14M_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), + .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] )); + SLICE_3 SLICE_3( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), + .DI0(\FS_s[11] ), .CLK(C14M_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), + .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] )); + SLICE_4 SLICE_4( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), + .DI0(\FS_s[9] ), .CLK(C14M_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), + .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] )); + SLICE_5 SLICE_5( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), + .DI0(\FS_s[7] ), .CLK(C14M_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), + .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] )); + SLICE_6 SLICE_6( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), + .DI0(\FS_s[5] ), .CLK(C14M_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), + .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] )); + SLICE_7 SLICE_7( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), + .DI0(\FS_s[3] ), .CLK(C14M_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), + .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] )); + SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), + .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), + .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); + SLICE_9 SLICE_9( .C1(Ready), .B1(PHI1reg), .A1(PHI1_c), .B0(RWSel), + .A0(CO0_1), .DI0(\CmdTout_3[0] ), .CE(N_576_i), .CLK(C14M_c), + .F0(\CmdTout_3[0] ), .Q0(CO0_1), .F1(S_1)); + SLICE_10 SLICE_10( .D1(\CS[0] ), .C1(N_461), .B1(\S_RNII9DO1_0[1] ), + .A1(\CS[1] ), .C0(\S_RNII9DO1_0[1] ), .B0(N_461), .A0(\CS[0] ), + .DI1(N_511_i), .DI0(N_504_i), .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), + .F0(N_504_i), .Q0(\CS[0] ), .F1(N_511_i), .Q1(\CS[1] )); + SLICE_11 SLICE_11( .C1(\S_RNII9DO1_0[1] ), .B1(N_461), .A1(\CS[0] ), + .C0(N_637), .B0(\CS[2] ), .A0(\CS[1] ), .DI0(N_510_i), + .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_510_i), .Q0(\CS[2] ), + .F1(N_637)); + SLICE_12 SLICE_12( .C1(\Din_c[3] ), .B1(\Din_c[2] ), .A1(\Din_c[0] ), + .D0(RWSel), .C0(N_643), .B0(CmdBitbangMXO2_4_u_0_0_a2_0_1), + .A0(CmdBitbangMXO2), .DI0(CmdBitbangMXO2_4), .CE(N_576_i), .CLK(C14M_c), + .F0(CmdBitbangMXO2_4), .Q0(CmdBitbangMXO2), + .F1(CmdBitbangMXO2_4_u_0_0_a2_0_1)); + SLICE_13 SLICE_13( .C1(RWSel), .B1(\Din_c[7] ), .A1(\Din_c[5] ), .D0(RWSel), + .C0(N_643), .B0(N_629), .A0(CmdExecMXO2), .DI0(CmdExecMXO2_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdExecMXO2_4), .Q0(CmdExecMXO2), + .F1(N_466)); + SLICE_14 SLICE_14( .D1(N_478), .C1(\Din_c[4] ), .B1(\Din_c[1] ), + .A1(\Din_c[0] ), .D0(RWSel), .C0(N_476), .B0(CmdLEDGet_4_u_0_0_a2_0_2), + .A0(CmdLEDGet), .DI0(CmdLEDGet_4), .CE(N_576_i), .CLK(C14M_c), + .F0(CmdLEDGet_4), .Q0(CmdLEDGet), .F1(CmdLEDGet_4_u_0_0_a2_0_2)); + SLICE_15 SLICE_15( .D1(N_626), .C1(N_476), .B1(\Din_c[4] ), .A1(\Din_c[1] ), + .C0(RWSel), .B0(N_605), .A0(CmdLEDSet), .DI0(CmdLEDSet_4), .CE(N_576_i), + .CLK(C14M_c), .F0(CmdLEDSet_4), .Q0(CmdLEDSet), .F1(N_605)); + SLICE_16 SLICE_16( .C1(\Din_c[1] ), .B1(\Din_c[4] ), .A1(N_476), .D0(RWSel), + .C0(N_643), .B0(N_626), .A0(CmdRWMaskSet), .DI0(CmdRWMaskSet_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdRWMaskSet_4), .Q0(CmdRWMaskSet), + .F1(N_643)); + SLICE_17 SLICE_17( .D1(N_626), .C1(N_476), .B1(\Din_c[4] ), .A1(\Din_c[1] ), + .C0(RWSel), .B0(N_401), .A0(CmdSetRWBankFFLED), .DI0(CmdSetRWBankFFLED_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdSetRWBankFFLED_4), + .Q0(CmdSetRWBankFFLED), .F1(N_401)); + SLICE_18 SLICE_18( .C1(N_474), .B1(\CS[2] ), .A1(\CS[1] ), .D0(RWSel), + .C0(N_476), .B0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), + .A0(CmdSetRWBankFFMXO2), .DI0(CmdSetRWBankFFMXO2_4), .CE(N_576_i), + .CLK(C14M_c), .F0(CmdSetRWBankFFMXO2_4), .Q0(CmdSetRWBankFFMXO2), + .F1(N_476)); + SLICE_19 SLICE_19( .D1(RWSel), .C1(CO0_1), .B1(\CmdTout[1] ), + .A1(\CmdTout[2] ), .C0(RWSel), .B0(\CmdTout[1] ), .A0(CO0_1), + .DI1(N_556_i), .DI0(N_555_i), .CE(N_576_i), .CLK(C14M_c), .F0(N_555_i), + .Q0(\CmdTout[1] ), .F1(N_556_i), .Q1(\CmdTout[2] )); + SLICE_20 SLICE_20( .D1(\S[0] ), .C1(\S[1] ), .B1(\S[2] ), .A1(\S[3] ), + .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), .DI0(N_6_i), + .CLK(C14M_c), .F0(N_6_i), .Q0(DOEEN), .F1(N_576_i)); + SLICE_21 SLICE_21( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[1] ), + .C0(\wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), .DI0(LEDEN_RNO), + .CE(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .CLK(C14M_c), .F0(LEDEN_RNO), + .Q0(LEDEN), .F1(N_558_i)); + SLICE_22 SLICE_22( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[3] ), .C0(\S[3] ), + .B0(\S[0] ), .A0(\Ain_c[0] ), .DI1(N_552_i), .DI0(N_127_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c), .F0(N_127_i), .Q0(\RA_c[0] ), + .F1(N_552_i), .Q1(\RA_c[3] )); + SLICE_23 SLICE_23( .C1(\RWMask[1] ), .B1(N_591), .A1(\Din_c[1] ), + .C0(\RWMask[0] ), .B0(N_591), .A0(\Din_c[0] ), .DI1(\RWBank_5[1] ), + .DI0(\RWBank_5[0] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[0] ), + .Q0(\RWBank[0] ), .F1(\RWBank_5[1] ), .Q1(\RWBank[1] )); + SLICE_24 SLICE_24( .C1(\RWMask[3] ), .B1(N_591), .A1(\Din_c[3] ), + .C0(\RWMask[2] ), .B0(N_591), .A0(\Din_c[2] ), .DI1(\RWBank_5[3] ), + .DI0(\RWBank_5[2] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[2] ), + .Q0(\RWBank[2] ), .F1(\RWBank_5[3] ), .Q1(\RWBank[3] )); + SLICE_25 SLICE_25( .C1(\RWMask[5] ), .B1(N_591), .A1(\Din_c[5] ), + .C0(\RWMask[4] ), .B0(N_591), .A0(\Din_c[4] ), .DI1(\RWBank_5[5] ), + .DI0(\RWBank_5[4] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[4] ), + .Q0(\RWBank[4] ), .F1(\RWBank_5[5] ), .Q1(\RWBank[5] )); + SLICE_26 SLICE_26( .C1(\RWMask[7] ), .B1(N_591), .A1(\Din_c[7] ), + .C0(\RWMask[6] ), .B0(N_591), .A0(\Din_c[6] ), .DI1(\RWBank_5[7] ), + .DI0(\RWBank_5[6] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[6] ), + .Q0(\RWBank[6] ), .F1(\RWBank_5[7] ), .Q1(\RWBank[7] )); + SLICE_27 SLICE_27( .C1(\wb_dato[1] ), .B1(\S[3] ), .A1(\Din_c[1] ), + .C0(\wb_dato[0] ), .B0(\S[3] ), .A0(\Din_c[0] ), .DI1(N_291_i), + .DI0(N_292_i), .CE(N_88), .CLK(C14M_c), .F0(N_292_i), .Q0(\RWMask[0] ), + .F1(N_291_i), .Q1(\RWMask[1] )); + SLICE_28 SLICE_28( .C1(\wb_dato[3] ), .B1(\S[3] ), .A1(\Din_c[3] ), + .C0(\wb_dato[2] ), .B0(\S[3] ), .A0(\Din_c[2] ), .DI1(N_289_i), + .DI0(N_290_i), .CE(N_88), .CLK(C14M_c), .F0(N_290_i), .Q0(\RWMask[2] ), + .F1(N_289_i), .Q1(\RWMask[3] )); + SLICE_29 SLICE_29( .C1(\wb_dato[5] ), .B1(\S[3] ), .A1(\Din_c[5] ), + .C0(\wb_dato[4] ), .B0(\S[3] ), .A0(\Din_c[4] ), .DI1(N_287_i), + .DI0(N_288_i), .CE(N_88), .CLK(C14M_c), .F0(N_288_i), .Q0(\RWMask[4] ), + .F1(N_287_i), .Q1(\RWMask[5] )); + SLICE_30 SLICE_30( .C1(\wb_dato[7] ), .B1(\S[3] ), .A1(\Din_c[7] ), + .C0(\wb_dato[6] ), .B0(\S[3] ), .A0(\Din_c[6] ), .DI1(N_285), + .DI0(N_286_i), .CE(N_88), .CLK(C14M_c), .F0(N_286_i), .Q0(\RWMask[6] ), + .F1(N_285), .Q1(\RWMask[7] )); + SLICE_31 SLICE_31( .C1(nWE_c), .B1(nEN80_c), .A1(DOEEN), .D0(nWE_c), + .C0(nC07X_c), .B0(\RA_c[3] ), .A0(\RA_c[0] ), .DI0(RWSel_2), .CE(nCS61), + .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(nDOE_c)); + SLICE_32 SLICE_32( .D1(Ready_0_sqmuxa_0_a2_6_a2_4), .C1(N_489), .B1(\FS[7] ), + .A1(\FS[6] ), .B0(Ready), .A0(Ready_0_sqmuxa), .DI0(N_876_0), .CLK(C14M_c), + .F0(N_876_0), .Q0(Ready), .F1(Ready_0_sqmuxa)); + SLICE_33 SLICE_33( .D1(wb_reqc_1), .C1(N_575), .B1(N_572), .A1(S_1), + .D0(\S_s_0_1[0] ), .C0(\S[1] ), .B0(\S[0] ), .A0(S_1), .DI1(N_133_i), + .DI0(\S_s_0[0] ), .CLK(C14M_c), .F0(\S_s_0[0] ), .Q0(\S[0] ), .F1(N_133_i), + .Q1(\S[1] )); + SLICE_34 SLICE_34( .D1(\S[3] ), .C1(\S[2] ), .B1(N_575), .A1(S_1), + .D0(\S[3] ), .C0(\S[2] ), .B0(N_575), .A0(S_1), .DI1(N_129_i), + .DI0(N_131_i), .CLK(C14M_c), .F0(N_131_i), .Q0(\S[2] ), .F1(N_129_i), + .Q1(\S[3] )); + SLICE_35 SLICE_35( .D1(wb_adr_7_5_214_0_1), .C1(\S[2] ), .B1(N_388), + .A1(\Din_c[1] ), .D0(\wb_adr_7_0_4[0] ), .C0(N_642), .B0(N_376), + .A0(\FS[13] ), .DI1(\wb_adr_RNO[1] ), .DI0(\wb_adr_7[0] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_adr_7[0] ), + .Q0(\wb_adr[0] ), .F1(\wb_adr_RNO[1] ), .Q1(\wb_adr[1] )); + SLICE_36 SLICE_36( .B1(\S[2] ), .A1(\Din_c[3] ), .B0(\S[2] ), + .A0(\Din_c[2] ), .DI1(N_41_i), .DI0(N_43_i), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_43_i), + .Q0(\wb_adr[2] ), .F1(N_41_i), .Q1(\wb_adr[3] )); + SLICE_37 SLICE_37( .C1(\S[2] ), .B1(\FS[14] ), .A1(\Din_c[5] ), .C0(\S[2] ), + .B0(\FS[14] ), .A0(\Din_c[4] ), .DI1(N_295), .DI0(N_294), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_294), + .Q0(\wb_adr[4] ), .F1(N_295), .Q1(\wb_adr[5] )); + SLICE_38 SLICE_38( .B1(\S[2] ), .A1(\Din_c[7] ), .C0(\S[2] ), .B0(\FS[14] ), + .A0(\Din_c[6] ), .DI1(N_39_i), .DI0(N_296), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_296), + .Q0(\wb_adr[6] ), .F1(N_39_i), .Q1(\wb_adr[7] )); + SLICE_39 SLICE_39( .D1(\FS[14] ), .C1(wb_ack), .B1(\FS[0] ), .A1(N_300), + .C0(\S[3] ), .B0(N_395), .A0(CmdExecMXO2), .DI0(wb_cyc_stb_RNO), + .CE(N_104), .CLK(C14M_c), .F0(wb_cyc_stb_RNO), .Q0(wb_cyc_stb), .F1(N_395)); + SLICE_40 SLICE_40( .D1(\wb_dati_7_0_0[1] ), .C1(N_627), .B1(N_621), + .A1(N_336), .D0(\wb_dati_7_0_a2_1[0] ), .C0(\wb_adr[0] ), .B0(\S[2] ), + .A0(N_484), .DI1(\wb_dati_7[1] ), .DI0(\wb_dati_7[0] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[0] ), + .Q0(\wb_dati[0] ), .F1(\wb_dati_7[1] ), .Q1(\wb_dati[1] )); + SLICE_41 SLICE_41( .C1(\wb_dati_7_0_2[3] ), .B1(\wb_dati_7_0_0[3] ), + .A1(N_336), .D0(\wb_dati_7_0_o2_0[2] ), .C0(\wb_adr[2] ), .B0(\S[2] ), + .A0(N_345), .DI1(\wb_dati_7[3] ), .DI0(\wb_dati_7[2] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[2] ), + .Q0(\wb_dati[2] ), .F1(\wb_dati_7[3] ), .Q1(\wb_dati[3] )); + SLICE_42 SLICE_42( .D1(\wb_dati_7_0_o2_0[2] ), .C1(\wb_adr[5] ), .B1(\S[2] ), + .A1(N_345), .D0(\wb_dati_7_0_0[4] ), .C0(N_349), .B0(N_346), .A0(N_345), + .DI1(\wb_dati_7[5] ), .DI0(\wb_dati_7[4] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[4] ), + .Q0(\wb_dati[4] ), .F1(\wb_dati_7[5] ), .Q1(\wb_dati[5] )); + SLICE_43 SLICE_43( .D1(\wb_dati_7_0_0[7] ), .C1(\wb_dati_7_0_RNO[7] ), + .B1(N_424), .A1(N_422), .C0(\wb_dati_7_0_1[6] ), .B0(N_627), .A0(N_621), + .DI1(\wb_dati_7[7] ), .DI0(\wb_dati_7[6] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[6] ), + .Q0(\wb_dati[6] ), .F1(\wb_dati_7[7] ), .Q1(\wb_dati[7] )); + SLICE_44 SLICE_44( .C1(\FS[13] ), .B1(\FS[12] ), .A1(\FS[11] ), + .D0(wb_reqc_1), .C0(\S[3] ), .B0(N_397), .A0(\FS[14] ), .DI0(wb_reqc_i), + .CE(wb_adr_0_sqmuxa_i), .LSR(\S[2] ), .CLK(C14M_c), .F0(wb_reqc_i), + .Q0(wb_req), .F1(N_397)); + SLICE_45 SLICE_45( .B1(wb_ack), .A1(\FS[14] ), .B0(\FS[15] ), .A0(\FS[14] ), + .DI0(wb_rst8), .LSR(\S_RNII9DO1[1] ), .CLK(C14M_c), .F0(wb_rst8), + .Q0(wb_rst), .F1(N_586)); + SLICE_46 SLICE_46( .D1(\FS[8] ), .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[12] ), + .D0(wb_we_7_iv_0_0_0_1), .C0(N_584), .B0(N_475), .A0(\FS[13] ), + .DI0(wb_we_RNO), .CE(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), .CLK(C14M_c), + .F0(wb_we_RNO), .Q0(wb_we), .F1(N_584)); + SLICE_47 SLICE_47( .D1(N_255), .C1(\S[0] ), .B1(\S_RNII9DO1[1] ), + .A1(\RWBank[6] ), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), + .F0(\S_RNII9DO1[1] ), .F1(N_358_i)); + SLICE_48 SLICE_48( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[1] ), .A1(\S[0] ), + .D0(N_635), .C0(\S[0] ), .B0(N_254), .A0(Vout3), .F0(nCAS_s_i_tz_0), + .F1(Vout3)); + SLICE_49 SLICE_49( .D1(un1_CS_0_sqmuxa_0_0_a2_1_4), .C1(RWSel), + .B1(\Din_c[6] ), .A1(\CS[0] ), .D0(RWSel), .C0(N_327), .B0(\CS[2] ), + .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_0), .F1(N_327)); + SLICE_50 SLICE_50( .D1(\FS[11] ), .C1(\FS[10] ), .B1(\FS[9] ), .A1(\FS[8] ), + .D0(\wb_dati_7_0_a2_0_1[7] ), .C0(N_621), .B0(N_579), .A0(\FS[9] ), + .F0(\wb_dati_7_0_RNO[7] ), .F1(\wb_dati_7_0_a2_0_1[7] )); + SLICE_51 SLICE_51( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), + .A1(CKE_6_iv_i_a2_0), .D0(\S[3] ), .C0(N_489), .B0(\FS[15] ), + .A0(CKE_6_iv_i_0_1), .F0(CKE_6_iv_i_0), .F1(CKE_6_iv_i_0_1)); + SLICE_52 SLICE_52( .D1(wb_req), .C1(N_449), .B1(N_300), .A1(\FS[0] ), + .D0(N_586), .C0(N_449), .B0(N_365), .A0(N_364), .F0(N_104), .F1(N_365)); + SLICE_53 SLICE_53( .D1(\S[3] ), .C1(\S[2] ), .B1(RWSel), .A1(\FS[15] ), + .D0(wb_reqc_1), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .B0(\S[2] ), + .A0(CmdExecMXO2), .F0(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), + .F1(\un1_wb_adr_0_sqmuxa_2_1[0] )); + SLICE_54 SLICE_54( .D1(\Din_c[2] ), .C1(\Din_c[1] ), .B1(\Din_c[0] ), + .A1(\CS[1] ), .D0(N_623), .C0(N_616), .B0(\Din_c[1] ), .A0(\CS[2] ), + .F0(N_279), .F1(N_623)); + SLICE_55 SLICE_55( .D1(\FS[4] ), .C1(N_633), .B1(\FS[5] ), .A1(N_264), + .D0(\FS[1] ), .C0(\FS[2] ), .B0(\FS[3] ), .A0(\FS[5] ), .F0(N_633), + .F1(N_570)); + SLICE_56 SLICE_56( .C1(\FS[15] ), .B1(\S_RNII9DO1[1] ), .A1(\FS[14] ), + .C0(\FS[13] ), .B0(N_452), .A0(\FS[12] ), .F0(N_621), .F1(N_452)); + SLICE_57 SLICE_57( .D1(\S_RNII9DO1_0[1] ), .C1(RWSel), .B1(CmdExecMXO2), + .A1(wb_ack), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[3] ), .A0(\S[2] ), + .F0(\S_RNII9DO1_0[1] ), .F1(N_364)); + SLICE_58 SLICE_58( .D1(\wb_dati_7_0_a2_2_1[3] ), .C1(N_644), .B1(N_455), + .A1(\FS[12] ), .D0(\FS[10] ), .C0(\FS[11] ), .B0(\FS[8] ), .A0(\FS[9] ), + .F0(\wb_dati_7_0_a2_2_1[3] ), .F1(\wb_dati_7_0_2[3] )); + SLICE_59 SLICE_59( .D1(nCS61), .C1(\RWBank[6] ), .B1(\S_RNII9DO1[1] ), + .A1(DQML_s_i_a2_0), .D0(\S[0] ), .C0(\S[1] ), .B0(\S[2] ), .A0(\S[3] ), + .F0(DQML_s_i_a2_0), .F1(N_28_i)); + SLICE_60 SLICE_60( .D1(wb_adr_7_5_214_a2_2_0), .C1(N_577), .B1(N_569), + .A1(N_475), .C0(\FS[10] ), .B0(\FS[12] ), .A0(\FS[13] ), + .F0(wb_adr_7_5_214_a2_2_0), .F1(wb_adr_7_5_214_0_1)); + SLICE_61 SLICE_61( .C1(N_634), .B1(\FS[13] ), .A1(\FS[12] ), .D0(\FS[10] ), + .C0(\FS[11] ), .B0(\FS[8] ), .A0(\FS[9] ), .F0(N_634), + .F1(\wb_dati_7_0_a2_2_0[1] )); + SLICE_62 SLICE_62( .D1(N_475), .C1(N_265_i), .B1(\FS[12] ), .A1(\FS[11] ), + .C0(\FS[8] ), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_265_i), .F1(N_388)); + SLICE_63 SLICE_63( .D1(N_264), .C1(N_254), .B1(\FS[7] ), .A1(\FS[6] ), + .C0(\FS[1] ), .B0(\FS[2] ), .A0(\FS[3] ), .F0(N_264), .F1(N_300)); + SLICE_64 SLICE_64( .C1(\FS[8] ), .B1(\FS[9] ), .A1(\FS[11] ), .D0(\FS[10] ), + .C0(\FS[12] ), .B0(N_577), .A0(wb_ack), + .F0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .F1(N_577)); + SLICE_65 SLICE_65( .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[10] ), + .C0(\FS[12] ), .B0(\FS[13] ), .A0(\wb_dati_7_0_a2_0[6] ), + .F0(\wb_dati_7_0_a2_4_0[7] ), .F1(\wb_dati_7_0_a2_0[6] )); + SLICE_66 SLICE_66( .B1(\S[2] ), .A1(\FS[14] ), .D0(\FS[12] ), .C0(\FS[13] ), + .B0(\FS[11] ), .A0(N_475), .F0(N_393), .F1(N_475)); + SLICE_67 SLICE_67( .B1(\S[1] ), .A1(\S[0] ), .D0(wb_reqc_1), .C0(\S[3] ), + .B0(\S[2] ), .A0(RWSel), .F0(LEDEN13), .F1(wb_reqc_1)); + SLICE_68 SLICE_68( .D1(\wb_adr[3] ), .C1(\S[2] ), .B1(N_627), .A1(N_455), + .D0(\FS[11] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[10] ), .F0(N_627), + .F1(\wb_dati_7_0_0[3] )); + SLICE_69 SLICE_69( .D1(nCAS_0_sqmuxa), .C1(\RWBank[2] ), .B1(N_639), + .A1(N_255), .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), .F0(N_639), + .F1(\RA_42[10] )); + SLICE_70 SLICE_70( .D1(N_644), .C1(N_627), .B1(N_455), .A1(\FS[12] ), + .D0(\FS[8] ), .C0(\FS[9] ), .B0(\FS[10] ), .A0(\FS[11] ), .F0(N_644), + .F1(N_345)); + SLICE_71 SLICE_71( .D1(nCS61), .C1(N_640), .B1(N_633), .A1(\FS[4] ), + .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\S[0] ), .F0(nCS61), + .F1(un1_nCS61_1_i)); + SLICE_72 SLICE_72( .D1(Ready_0_sqmuxa_0_a2_6_a2_2), .C1(N_449), .B1(\FS[5] ), + .A1(\FS[3] ), .D0(\S[2] ), .C0(\S[3] ), .B0(wb_reqc_1), .A0(\FS[15] ), + .F0(N_449), .F1(Ready_0_sqmuxa_0_a2_6_a2_4)); + SLICE_73 SLICE_73( .D1(N_562), .C1(N_455), .B1(\FS[12] ), .A1(\FS[11] ), + .D0(\FS[14] ), .C0(\S_RNII9DO1[1] ), .B0(\FS[15] ), .A0(\FS[13] ), + .F0(N_455), .F1(N_377)); + SLICE_74 SLICE_74( .C1(N_484), .B1(\FS[11] ), .A1(\FS[9] ), .D0(\FS[10] ), + .C0(\FS[12] ), .B0(\FS[13] ), .A0(N_642), .F0(N_346), .F1(N_642)); + SLICE_75 SLICE_75( .D1(N_489), .C1(\FS[7] ), .B1(\FS[6] ), .A1(\FS[0] ), + .C0(\FS[15] ), .B0(\S_RNII9DO1[1] ), .A0(N_628), .F0(N_640), .F1(N_628)); + SLICE_76 SLICE_76( .B1(\FS[5] ), .A1(\FS[4] ), .D0(N_449), .C0(N_628), + .B0(N_254), .A0(N_264), .F0(nCAS_0_sqmuxa), .F1(N_254)); + SLICE_77 SLICE_77( .C1(N_466), .B1(\Din_c[6] ), .A1(\CS[0] ), + .D0(un1_CS_0_sqmuxa_0_0_a2_3_2), .C0(un1_CS_0_sqmuxa_0_0_3), + .B0(un1_CS_0_sqmuxa_0_0_2), .A0(N_474), .F0(un1_CS_0_sqmuxa_i), .F1(N_474)); + SLICE_78 SLICE_78( .B1(N_633), .A1(\FS[4] ), .D0(nCAS_s_i_tz_0), .C0(N_640), + .B0(N_567), .A0(nCAS_0_sqmuxa), .F0(N_561_i), .F1(N_567)); + SLICE_79 SLICE_79( .D1(nEN80_c), .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), + .B0(nCS_6_u_i_0), .A0(N_559_1), .F0(N_559_i), .F1(nCS_6_u_i_0)); + SLICE_80 SLICE_80( .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), .C0(\S[0] ), + .B0(N_635), .A0(N_559_1), .F0(nRAS_2_iv_i), .F1(N_635)); + SLICE_81 SLICE_81( .D1(\Din_c[6] ), .C1(\Din_c[4] ), .B1(\Din_c[3] ), + .A1(\CS[0] ), .D0(un1_CS_0_sqmuxa_0_0_a2_1), .C0(un1_CS_0_sqmuxa_0_0_0), + .B0(N_466), .A0(N_279), .F0(un1_CS_0_sqmuxa_0_0_2), + .F1(un1_CS_0_sqmuxa_0_0_a2_1)); + SLICE_82 SLICE_82( .D1(RWSel), .C1(\CmdTout[2] ), .B1(\CmdTout[1] ), + .A1(CO0_1), .D0(\S_RNII9DO1_0[1] ), .C0(N_461), .B0(N_330), .A0(N_328), + .F0(un1_CS_0_sqmuxa_0_0_3), .F1(N_461)); + SLICE_83 SLICE_83( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[0] ), .A1(\FS[15] ), + .D0(nCS_6_u_i_a2_1), .C0(N_628), .B0(N_570), .A0(N_429), .F0(N_559_1), + .F1(nCS_6_u_i_a2_1)); + SLICE_84 SLICE_84( .D1(\wb_dati_7_0_a2_0[6] ), .C1(N_455), .B1(\FS[12] ), + .A1(\FS[10] ), .D0(\wb_adr[6] ), .C0(\S[2] ), .B0(N_351), .A0(N_346), + .F0(\wb_dati_7_0_1[6] ), .F1(N_351)); + SLICE_85 SLICE_85( .D1(\wb_adr_7_0_a2_5_0[0] ), .C1(N_579), .B1(N_452), + .A1(\FS[8] ), .D0(\wb_adr_7_0_1[0] ), .C0(\wb_adr_7_0_0[0] ), .B0(N_378), + .A0(N_377), .F0(\wb_adr_7_0_4[0] ), .F1(\wb_adr_7_0_1[0] )); + SLICE_86 SLICE_86( .D1(\FS[14] ), .C1(\S_RNII9DO1[1] ), .B1(\FS[15] ), + .A1(\FS[8] ), .D0(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ), .C0(N_484), + .B0(LEDEN13), .A0(CmdLEDSet), .F0(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), + .F1(N_484)); + SLICE_87 SLICE_87( .D1(un1_CS_0_sqmuxa_0_0_a2_4_2), .C1(RWSel), + .B1(\Din_c[6] ), .A1(\CS[0] ), .C0(un1_CS_0_sqmuxa_0_0_a2_4_4), + .B0(\CS[2] ), .A0(\CS[1] ), .F0(N_330), .F1(un1_CS_0_sqmuxa_0_0_a2_4_4)); + SLICE_88 SLICE_88( .B1(\FS[13] ), .A1(\FS[12] ), .D0(N_634), .C0(N_569), + .B0(N_452), .A0(N_336), .F0(\wb_dati_7_0_o2_0[2] ), .F1(N_569)); + SLICE_89 SLICE_89( .B1(\FS[11] ), .A1(\FS[10] ), .D0(N_579), .C0(N_455), + .B0(\FS[9] ), .A0(\FS[8] ), .F0(N_378), .F1(N_579)); + SLICE_90 SLICE_90( .D1(\FS[13] ), .C1(\FS[11] ), .B1(\FS[10] ), .A1(\FS[9] ), + .C0(N_565), .B0(N_484), .A0(\FS[12] ), .F0(N_336), .F1(N_565)); + SLICE_91 SLICE_91( .D1(un1_CS_0_sqmuxa_0_0_a2_2_2), .C1(\Din_c[6] ), + .B1(\CS[2] ), .A1(\CS[0] ), .C0(un1_CS_0_sqmuxa_0_0_a2_2_4), .B0(RWSel), + .A0(\Din_c[7] ), .F0(N_328), .F1(un1_CS_0_sqmuxa_0_0_a2_2_4)); + SLICE_92 SLICE_92( .D1(N_562), .C1(\FS[13] ), .B1(\FS[12] ), .A1(\FS[11] ), + .D0(\wb_adr_7_0_a2_0[0] ), .C0(\S[2] ), .B0(N_452), .A0(\Din_c[0] ), + .F0(\wb_adr_7_0_0[0] ), .F1(\wb_adr_7_0_a2_0[0] )); + SLICE_93 SLICE_93( .D1(N_616), .C1(\Din_c[5] ), .B1(\Din_c[4] ), + .A1(\Din_c[1] ), .D0(un1_CS_0_sqmuxa_0_0_a2_1_2), .C0(\Din_c[7] ), + .B0(\Din_c[3] ), .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_a2_1_4), + .F1(un1_CS_0_sqmuxa_0_0_a2_1_2)); + SLICE_94 SLICE_94( .D1(\Din_c[3] ), .C1(\Din_c[2] ), .B1(\Din_c[0] ), + .A1(\Din_c[1] ), .D0(un1_CS_0_sqmuxa_0_0_a2_3_0), .C0(\Din_c[4] ), + .B0(\CS[2] ), .A0(\CS[1] ), .F0(un1_CS_0_sqmuxa_0_0_a2_3_2), + .F1(un1_CS_0_sqmuxa_0_0_a2_3_0)); + SLICE_95 SLICE_95( .D1(N_577), .C1(N_475), .B1(\FS[12] ), .A1(\FS[10] ), + .D0(\S[2] ), .C0(N_394), .B0(N_393), .A0(\Din_c[0] ), + .F0(wb_we_7_iv_0_0_0_1), .F1(N_394)); + SLICE_96 SLICE_96( .C1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), .D0(\S[0] ), + .C0(\RWBank[7] ), .B0(\RWBank[0] ), .A0(N_255), .F0(N_49_i), .F1(N_255)); + SLICE_97 SLICE_97( .B1(\FS[12] ), .A1(\FS[10] ), .D0(N_577), .C0(N_456), + .B0(\FS[14] ), .A0(\FS[13] ), .F0(N_489), .F1(N_456)); + SLICE_98 SLICE_98( .C1(\Din_c[2] ), .B1(\Din_c[3] ), .A1(\Din_c[0] ), + .D0(N_626), .C0(N_477), .B0(\Din_c[7] ), .A0(\Din_c[5] ), + .F0(un1_CS_0_sqmuxa_0_0_a2_4_2), .F1(N_626)); + SLICE_99 SLICE_99( .B1(\Din_c[3] ), .A1(\Din_c[2] ), .D0(N_478), .C0(N_477), + .B0(\Din_c[5] ), .A0(\Din_c[0] ), .F0(un1_CS_0_sqmuxa_0_0_a2_2_2), + .F1(N_478)); + SLICE_100 SLICE_100( .C1(\Din_c[0] ), .B1(\Din_c[2] ), .A1(\Din_c[3] ), + .C0(N_629), .B0(\Din_c[4] ), .A0(\Din_c[1] ), + .F0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), .F1(N_629)); + SLICE_101 SLICE_101( .D1(\S[2] ), .C1(\S[3] ), .B1(\S[1] ), .A1(\S[0] ), + .D0(\S[3] ), .C0(\S[2] ), .B0(\S[1] ), .A0(\S[0] ), .F0(\S_RNII9DO1_1[1] ), + .F1(N_566_i)); + SLICE_102 SLICE_102( .D1(\S[3] ), .C1(\S[2] ), .B1(\S[1] ), .A1(\S[0] ), + .D0(\S[1] ), .C0(\S[2] ), .B0(\S[3] ), .A0(\RWBank[4] ), .F0(\BA_4[0] ), + .F1(\S_s_0_1[0] )); + SLICE_103 SLICE_103( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), + .A1(\RWBank[3] ), .D0(\S[2] ), .C0(\S[3] ), .B0(wb_reqc_1), .A0(\FS[15] ), + .F0(wb_adr_0_sqmuxa_i), .F1(\RA_42[11] )); + SLICE_104 SLICE_104( .D1(N_621), .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[8] ), + .D0(N_621), .C0(\FS[11] ), .B0(\FS[10] ), .A0(\FS[9] ), .F0(N_376), + .F1(N_349)); + SLICE_105 SLICE_105( .D1(wb_ack), .C1(N_579), .B1(N_569), .A1(\FS[9] ), + .D0(N_579), .C0(N_569), .B0(N_484), .A0(\FS[9] ), .F0(N_424), + .F1(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] )); + SLICE_106 SLICE_106( .B1(\S[1] ), .A1(\S[0] ), .C0(\S[0] ), .B0(\S[1] ), + .A0(nEN80_c), .F0(CKE_6_iv_i_a2_0), .F1(N_575)); + SLICE_107 SLICE_107( .B1(\S[3] ), .A1(\S[2] ), .D0(\S[1] ), .C0(\S[2] ), + .B0(\S[3] ), .A0(\RWBank[5] ), .F0(\BA_4[1] ), .F1(N_572)); + SLICE_108 SLICE_108( .C1(\FS[12] ), .B1(\FS[10] ), .A1(\FS[9] ), .D0(N_642), + .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ), .F0(N_422), + .F1(\wb_adr_7_0_a2_5_0[0] )); + SLICE_109 SLICE_109( .D1(\wb_dati_7_0_a2_4_0[7] ), .C1(\wb_adr[7] ), + .B1(\S[2] ), .A1(N_452), .D0(\wb_dati_7_0_a2_2_0[1] ), .C0(\wb_adr[1] ), + .B0(\S[2] ), .A0(N_452), .F0(\wb_dati_7_0_0[1] ), .F1(\wb_dati_7_0_0[7] )); + SLICE_110 SLICE_110( .D1(wb_reqc_1), .C1(\S[3] ), .B1(\S[2] ), + .A1(\RWBank[1] ), .D0(wb_reqc_1), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), + .B0(\S[2] ), .A0(CmdBitbangMXO2), .F0(\un1_wb_adr_0_sqmuxa_2_i[0] ), + .F1(N_59_i)); + SLICE_111 SLICE_111( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[5] ), .C0(\S[3] ), + .B0(\S[0] ), .A0(\Ain_c[4] ), .F0(N_551_i), .F1(\RA_42_3_0[5] )); + SLICE_112 SLICE_112( .D1(\S[3] ), .C1(\S[1] ), .B1(\S[0] ), .A1(N_254), + .C0(\S[3] ), .B0(\S[0] ), .A0(\Ain_c[6] ), .F0(N_550_i), .F1(N_429)); + SLICE_113 SLICE_113( .C1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[2] ), .C0(\S[3] ), + .B0(\S[0] ), .A0(\Ain_c[7] ), .F0(N_549_i), .F1(N_553_i)); + SLICE_114 SLICE_114( .D1(\wb_adr[4] ), .C1(\S[2] ), .B1(N_634), .A1(N_455), + .D0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .C0(N_455), .B0(LEDEN13), + .A0(CmdRWMaskSet), .F0(N_88), .F1(\wb_dati_7_0_0[4] )); + SLICE_115 SLICE_115( .B1(nWE80_c), .A1(nEN80_c), .D0(nWE80_c), .C0(\S[0] ), + .B0(nCAS_0_sqmuxa), .A0(un1_nCS61_1_i), .F0(nRWE_r_0), .F1(RDOE_i)); + SLICE_116 SLICE_116( .B1(\FS[9] ), .A1(\FS[8] ), .D0(N_456), .C0(\FS[13] ), + .B0(\FS[11] ), .A0(\FS[9] ), .F0(\wb_dati_7_0_a2_1[0] ), .F1(N_562)); + SLICE_117 SLICE_117( .D1(LEDEN), .C1(CmdSetRWBankFFMXO2), + .B1(CmdSetRWBankFFLED), .A1(CmdLEDGet), .B0(nEN80_c), .A0(LEDEN), + .F0(LED_c), .F1(N_591)); + SLICE_118 SLICE_118( .B1(\Din_c[4] ), .A1(\Din_c[1] ), .B0(\Din_c[2] ), + .A0(\Din_c[0] ), .F0(N_616), .F1(N_477)); + SLICE_119 SLICE_119( .D0(\FS[4] ), .C0(\FS[2] ), .B0(\FS[1] ), .A0(\FS[0] ), + .F0(Ready_0_sqmuxa_0_a2_6_a2_2)); + RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(\Din_c[0] ), + .RD0(RD[0])); + LED LED_I( .PADDO(LED_c), .LED(LED)); + C14M C14M_I( .PADDI(C14M_c), .C14M(C14M)); + DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH)); + DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_358_i), .CLK(C14M_c)); + DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML)); + DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_28_i), .CLK(C14M_c)); + RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(\Din_c[7] ), + .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(\Din_c[6] ), + .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(\Din_c[5] ), + .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(\Din_c[4] ), + .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(\Din_c[3] ), + .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(\Din_c[2] ), + .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(\Din_c[1] ), + .RD1(RD[1])); + RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11])); + RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(\RA_42[11] ), + .CLK(C14M_c)); + RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10])); + RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(\RA_42[10] ), + .CLK(C14M_c)); + RA_9_ \RA[9]_I ( .IOLDO(\RA_c[9] ), .RA9(RA[9])); + RA_9__MGIOL \RA[9]_MGIOL ( .IOLDO(\RA_c[9] ), .OPOS(N_59_i), .CLK(C14M_c)); + RA_8_ \RA[8]_I ( .IOLDO(\RA_c[8] ), .RA8(RA[8])); + RA_8__MGIOL \RA[8]_MGIOL ( .IOLDO(\RA_c[8] ), .OPOS(N_49_i), .CLK(C14M_c)); + RA_7_ \RA[7]_I ( .IOLDO(\RA_c[7] ), .RA7(RA[7])); + RA_7__MGIOL \RA[7]_MGIOL ( .IOLDO(\RA_c[7] ), .OPOS(N_549_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_6_ \RA[6]_I ( .IOLDO(\RA_c[6] ), .RA6(RA[6])); + RA_6__MGIOL \RA[6]_MGIOL ( .IOLDO(\RA_c[6] ), .OPOS(N_550_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_5_ \RA[5]_I ( .IOLDO(\RA_c[5] ), .RA5(RA[5])); + RA_5__MGIOL \RA[5]_MGIOL ( .IOLDO(\RA_c[5] ), .OPOS(\RA_42_3_0[5] ), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_4_ \RA[4]_I ( .IOLDO(\RA_c[4] ), .RA4(RA[4])); + RA_4__MGIOL \RA[4]_MGIOL ( .IOLDO(\RA_c[4] ), .OPOS(N_551_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .IOLDO(\RA_c[2] ), .RA2(RA[2])); + RA_2__MGIOL \RA[2]_MGIOL ( .IOLDO(\RA_c[2] ), .OPOS(N_553_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_1_ \RA[1]_I ( .IOLDO(\RA_c[1] ), .RA1(RA[1])); + RA_1__MGIOL \RA[1]_MGIOL ( .IOLDO(\RA_c[1] ), .OPOS(N_558_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0])); + BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1])); + BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), + .LSR(N_566_i), .CLK(C14M_c)); + BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0])); + BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), + .LSR(N_566_i), .CLK(C14M_c)); + nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE)); + nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(nRWE_r_0), .CLK(C14M_c)); + nCAS nCAS_I( .IOLDO(nCAS_c), .nCAS(nCAS)); + nCAS_MGIOL nCAS_MGIOL( .IOLDO(nCAS_c), .OPOS(N_561_i), .CLK(C14M_c)); + nRAS nRAS_I( .IOLDO(nRAS_c), .nRAS(nRAS)); + nRAS_MGIOL nRAS_MGIOL( .IOLDO(nRAS_c), .OPOS(nRAS_2_iv_i), .CLK(C14M_c)); + nCS nCS_I( .IOLDO(nCS_c), .nCS(nCS)); + nCS_MGIOL nCS_MGIOL( .IOLDO(nCS_c), .OPOS(N_559_i), .CLK(C14M_c)); + CKE CKE_I( .IOLDO(CKE_c), .CKE(CKE)); + CKE_MGIOL CKE_MGIOL( .IOLDO(CKE_c), .OPOS(CKE_6_iv_i_0), .CLK(C14M_c)); + nVOE nVOE_I( .PADDO(PHI1_c), .nVOE(nVOE)); + Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7])); + Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_6_ \Vout[6]_I ( .IOLDO(\Vout_c[6] ), .Vout6(Vout[6])); + Vout_6__MGIOL \Vout[6]_MGIOL ( .IOLDO(\Vout_c[6] ), .OPOS(\RD_in[6] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_5_ \Vout[5]_I ( .IOLDO(\Vout_c[5] ), .Vout5(Vout[5])); + Vout_5__MGIOL \Vout[5]_MGIOL ( .IOLDO(\Vout_c[5] ), .OPOS(\RD_in[5] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_4_ \Vout[4]_I ( .IOLDO(\Vout_c[4] ), .Vout4(Vout[4])); + Vout_4__MGIOL \Vout[4]_MGIOL ( .IOLDO(\Vout_c[4] ), .OPOS(\RD_in[4] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_3_ \Vout[3]_I ( .IOLDO(\Vout_c[3] ), .Vout3(Vout[3])); + Vout_3__MGIOL \Vout[3]_MGIOL ( .IOLDO(\Vout_c[3] ), .OPOS(\RD_in[3] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_2_ \Vout[2]_I ( .IOLDO(\Vout_c[2] ), .Vout2(Vout[2])); + Vout_2__MGIOL \Vout[2]_MGIOL ( .IOLDO(\Vout_c[2] ), .OPOS(\RD_in[2] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_1_ \Vout[1]_I ( .IOLDO(\Vout_c[1] ), .Vout1(Vout[1])); + Vout_1__MGIOL \Vout[1]_MGIOL ( .IOLDO(\Vout_c[1] ), .OPOS(\RD_in[1] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_0_ \Vout[0]_I ( .IOLDO(\Vout_c[0] ), .Vout0(Vout[0])); + Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), + .CE(Vout3), .CLK(C14M_c)); + nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE)); + Dout_7_ \Dout[7]_I ( .IOLDO(\Dout_c[7] ), .Dout7(Dout[7])); + Dout_7__MGIOL \Dout[7]_MGIOL ( .IOLDO(\Dout_c[7] ), .OPOS(\RD_in[7] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_6_ \Dout[6]_I ( .IOLDO(\Dout_c[6] ), .Dout6(Dout[6])); + Dout_6__MGIOL \Dout[6]_MGIOL ( .IOLDO(\Dout_c[6] ), .OPOS(\RD_in[6] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_5_ \Dout[5]_I ( .IOLDO(\Dout_c[5] ), .Dout5(Dout[5])); + Dout_5__MGIOL \Dout[5]_MGIOL ( .IOLDO(\Dout_c[5] ), .OPOS(\RD_in[5] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_4_ \Dout[4]_I ( .IOLDO(\Dout_c[4] ), .Dout4(Dout[4])); + Dout_4__MGIOL \Dout[4]_MGIOL ( .IOLDO(\Dout_c[4] ), .OPOS(\RD_in[4] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_3_ \Dout[3]_I ( .IOLDO(\Dout_c[3] ), .Dout3(Dout[3])); + Dout_3__MGIOL \Dout[3]_MGIOL ( .IOLDO(\Dout_c[3] ), .OPOS(\RD_in[3] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_2_ \Dout[2]_I ( .IOLDO(\Dout_c[2] ), .Dout2(Dout[2])); + Dout_2__MGIOL \Dout[2]_MGIOL ( .IOLDO(\Dout_c[2] ), .OPOS(\RD_in[2] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_1_ \Dout[1]_I ( .IOLDO(\Dout_c[1] ), .Dout1(Dout[1])); + Dout_1__MGIOL \Dout[1]_MGIOL ( .IOLDO(\Dout_c[1] ), .OPOS(\RD_in[1] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_0_ \Dout[0]_I ( .IOLDO(\Dout_c[0] ), .Dout0(Dout[0])); + Dout_0__MGIOL \Dout[0]_MGIOL ( .IOLDO(\Dout_c[0] ), .OPOS(\RD_in[0] ), + .CE(N_576_i), .CLK(C14M_c)); + Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0])); + Ain_7_ \Ain[7]_I ( .PADDI(\Ain_c[7] ), .Ain7(Ain[7])); + Ain_6_ \Ain[6]_I ( .PADDI(\Ain_c[6] ), .Ain6(Ain[6])); + Ain_5_ \Ain[5]_I ( .PADDI(\Ain_c[5] ), .Ain5(Ain[5])); + Ain_4_ \Ain[4]_I ( .PADDI(\Ain_c[4] ), .Ain4(Ain[4])); + Ain_3_ \Ain[3]_I ( .PADDI(\Ain_c[3] ), .Ain3(Ain[3])); + Ain_2_ \Ain[2]_I ( .PADDI(\Ain_c[2] ), .Ain2(Ain[2])); + Ain_1_ \Ain[1]_I ( .PADDI(\Ain_c[1] ), .Ain1(Ain[1])); + Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0])); + nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X)); + nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80)); + nWE80 nWE80_I( .PADDI(nWE80_c), .nWE80(nWE80)); + nWE nWE_I( .PADDI(nWE_c), .nWE(nWE)); + PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1)); + PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1reg)); + ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), .WBRSTI(wb_rst), + .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), + .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), + .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), + .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), + .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), + .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), + .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), + .WBDATO2(\wb_dato[2] ), .WBDATO3(\wb_dato[3] ), .WBDATO4(\wb_dato[4] ), + .WBDATO5(\wb_dato[5] ), .WBDATO6(\wb_dato[6] ), .WBDATO7(\wb_dato[7] ), + .WBACKO(wb_ack)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); +endmodule + +module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly; + + vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h000A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20001 \FS_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5002; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_9 ( input C1, B1, A1, B0, A0, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut4 S_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40003 \CmdTout_3_0_a2[0] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40003 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_10 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40004 \CS_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 \CS_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0006 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40004 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA9AA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA9A9) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_11 ( input C1, B1, A1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40007 \CS_RNO_0[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 \CS_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0006 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6C6C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_12 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40009 CmdBitbangMXO2_4_u_0_0_a2_0_1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 CmdBitbangMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdBitbangMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_13 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 un1_CS_0_sqmuxa_0_0_a2_7( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 CmdExecMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdExecMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40012 CmdLEDGet_4_u_0_0_a2_0_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40010 CmdLEDGet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_15 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40013 CmdLEDSet_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40014 CmdLEDSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCECE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_16 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40007 CmdBitbangMXO2_4_u_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 CmdRWMaskSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_17 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40015 CmdSetRWBankFFLED_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40014 CmdSetRWBankFFLED_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_18 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 CmdSetRWBankFFLED_4_u_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 CmdSetRWBankFFMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre CmdSetRWBankFFMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_19 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40016 \CmdTout_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40017 \CmdTout_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CmdTout[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h006A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0606) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40018 \S_RNII9DO1_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40019 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre DOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_21 ( input C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40020 \RA_0io_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40021 LEDEN_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA8A8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hB8B8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_22 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40020 \RA_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 \RA_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_23 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40014 \RWBank_5_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \RWBank_5_0[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_24 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40014 \RWBank_5_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \RWBank_5_0[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_25 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40014 \RWBank_5_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \RWBank_5_0[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_26 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40022 \RWBank_5_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40014 \RWBank_5_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_27 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40023 \RWMask_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40023 \RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7474) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_28 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40023 \RWMask_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40023 \RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_29 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40023 \RWMask_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40023 \RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_30 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40021 \RWMask_RNO[7] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40023 \RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40024 nDOE_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 RWSel_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDFDF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input D1, C1, B1, A1, B0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40026 Ready_0_sqmuxa_0_a2_6_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40027 Ready_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output + F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40028 \S_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40029 \S_s_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFBA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output + F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40030 \S_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40031 \S_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \S[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5510) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5141) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40032 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40032 \wb_adr_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input B1, A1, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40033 \wb_adr_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40033 \wb_adr_RNO[2] ( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_37 ( input C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40034 \wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 \wb_adr_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_38 ( input B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40033 \wb_adr_RNO[7] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40034 \wb_adr_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_39 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40035 wb_cyc_stb_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40022 wb_cyc_stb_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h000E) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40036 \wb_dati_7_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 \wb_dati_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_41 ( input C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \wb_dati_7_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40036 \wb_dati_7_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40036 \wb_dati_7_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 \wb_dati_7_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_43 ( input D1, C1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40039 \wb_dati_7_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40040 \wb_dati_7_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_44 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40011 wb_req_RNO_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40041 wb_req_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_45 ( input B1, A1, B0, A0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40027 \un1_LEDEN13_2_i_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40003 wb_rst8_0_a2( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + vmuxregsre0006 wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40042 wb_we_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40043 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF40) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40044 DQMH_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 \S_RNII9DO1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40045 Vout3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 nCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40015 un1_CS_0_sqmuxa_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40047 un1_CS_0_sqmuxa_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40048 \wb_dati_7_0_a2_0_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40049 \wb_dati_7_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0D00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40050 CKE_6_iv_i_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40051 CKE_6_iv_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2F2C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40052 \un1_LEDEN13_2_i_a2_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40053 \un1_LEDEN13_2_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40054 \un1_wb_adr_0_sqmuxa_2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40055 wb_we_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3FF5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40056 un1_CS_0_sqmuxa_0_0_a2_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40057 un1_CS_0_sqmuxa_0_0_o2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40058 nCS_6_u_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 un1_nCS61_1_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF1) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_56 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40059 \wb_dati_7_0_a2_5[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40060 \wb_dati_7_0_a2_6[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0808) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40061 \un1_LEDEN13_2_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40062 \S_RNII9DO1_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40063 \wb_dati_7_0_2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 \wb_dati_7_0_2_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4440) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40064 DQML_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40065 DQML_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7377) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_60 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40066 \wb_adr_RNO_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40009 \wb_adr_RNO_3[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2A20) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_61 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40011 \wb_dati_7_0_a2_2_0[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40067 \FS_RNIOD6E_1[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40068 \wb_adr_RNO_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40069 \wb_adr_RNO_2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9595) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40039 \un1_LEDEN13_2_i_o2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40038 \FS_RNI9FGA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40070 \FS_RNI6JJA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40013 \un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40007 \wb_dati_7_0_a2_0_0[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 \wb_dati_7_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_66 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40003 \FS_RNIJ9MH[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40071 wb_we_RNO_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 wb_reqc_1( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 wb_reqc_1_RNIRU4M1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40073 \wb_dati_7_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40015 \FS_RNIOD6E_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40074 \RA_42_0[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40075 \RA_42_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0208) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40063 \wb_dati_7_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40076 \FS_RNIOD6E[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40076 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40077 nRWE_r_0_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 \S_RNII9DO1_3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00BF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40026 Ready_0_sqmuxa_0_a2_6_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40025 \FS_RNI5OOF1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40078 \wb_adr_7_0_a2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40067 \FS_RNIK5632[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40078 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut4 \wb_dati_7_0_a2_5[4] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 \wb_dati_7_0_a2_5_RNIC22J[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_75 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40015 nCS_6_u_i_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 nCS_6_u_i_a2_4_RNI3A062( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_76 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 nCS_6_u_i_o2_0( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 nCS_6_u_i_a2_4_RNICJKD2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_77 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40009 un1_CS_0_sqmuxa_0_0_a2_10( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40079 un1_CS_0_sqmuxa_0_0_2_RNIQS7F( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40079 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0103) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 nCAS_s_i_o2( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40080 nCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40080 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAABF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40081 nCS_6_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40003 nCS_0io_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0212) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40082 nRAS_2_iv_0_a2_0( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40083 nRAS_2_iv_i( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40082 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1212) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40083 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40018 un1_CS_0_sqmuxa_0_0_a2_1_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40047 un1_CS_0_sqmuxa_0_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40084 un1_CS_0_sqmuxa_0_0_a2_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 un1_CS_0_sqmuxa_0_0_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40084 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h007F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40025 nCS_6_u_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40085 nCS_6_u_i_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40085 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40086 \wb_dati_7_0_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40053 \wb_dati_7_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40086 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h9000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40087 \wb_adr_7_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 \wb_adr_7_0_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40087 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40067 \wb_dati_7_0_a2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 \un1_LEDEN_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40013 un1_CS_0_sqmuxa_0_0_a2_4_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 un1_CS_0_sqmuxa_0_0_a2_4( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_88 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40088 \FS_RNI9Q57[13] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40085 \wb_dati_7_0_o2_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40088 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 \wb_adr_7_0_o2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 \wb_adr_7_0_a2_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40089 \wb_dati_7_0_o2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 \wb_dati_7_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40089 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_91 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40015 un1_CS_0_sqmuxa_0_0_a2_2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40011 un1_CS_0_sqmuxa_0_0_a2_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40090 \wb_adr_7_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40091 \wb_adr_7_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40090 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3210) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40091 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40092 un1_CS_0_sqmuxa_0_0_a2_1_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40068 un1_CS_0_sqmuxa_0_0_a2_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40092 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40026 un1_CS_0_sqmuxa_0_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40065 un1_CS_0_sqmuxa_0_0_a2_3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40056 wb_we_RNO_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40093 wb_we_RNO_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40093 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40094 \RA_42_i_o2[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40095 \RA_0io_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40094 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEFEF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40095 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5044) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_97 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40033 \wb_dati_7_0_a2_1[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40072 CKE_6_iv_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_98 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40096 un1_CS_0_sqmuxa_0_0_a2_16( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 un1_CS_0_sqmuxa_0_0_a2_4_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40096 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0101) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_99 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40003 un1_CS_0_sqmuxa_0_0_a2_12( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40013 un1_CS_0_sqmuxa_0_0_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_100 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40011 un1_CS_0_sqmuxa_0_0_a2_17( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40009 CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0( .A(A0), .B(B0), .C(C0), .D(GNDI), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40097 wb_reqc_1_RNIEO5C1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40098 \S_RNII9DO1_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40097 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40098 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC289) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40099 \S_s_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40018 \BA_0io_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40099 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD550) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40056 \RA_0io_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40039 wb_req_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40065 \wb_dati_7_0_a2_3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40100 \wb_adr_7_0_a2_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40100 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCE00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40101 \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40045 \wb_dati_7_0_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40101 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_106 ( input B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40102 \S_RNINI6S[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40103 CKE_6_iv_i_0_1_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40103 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_107 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40102 \S_r_i_o2[1] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 \BA_0io_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_108 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40007 \wb_adr_7_0_a2_5_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 \wb_dati_7_0_a2[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40104 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40037 \wb_dati_7_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40037 \wb_dati_7_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40105 \RA_0io_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40055 CmdBitbangMXO2_RNI8CSO1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40105 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0023) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_111 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40106 \RA_42_3_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 \RA_0io_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40106 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hABAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_112 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40107 nCS_6_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40020 \RA_0io_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40107 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40020 \RA_0io_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40020 \RA_0io_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40073 \wb_dati_7_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 \un1_RWMask_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40027 nWE80_pad_RNI3ICD( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40108 nRWE_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40108 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3222) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_116 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40102 \wb_adr_7_0_o2_2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40109 \wb_dati_7_0_a2_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40109 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_117 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40093 \RWBank_5_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40110 LED_pad_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40110 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hDDDD) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_118 ( input B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40003 un1_CS_0_sqmuxa_0_0_a2_11( .A(A1), .B(B1), .C(GNDI), .D(GNDI), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40033 un1_CS_0_sqmuxa_0_0_a2_13( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_119 ( input D0, C0, B0, A0, output F0 ); + + lut40026 Ready_0_sqmuxa_0_a2_6_a2_2_0( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module xo2iobuf ( input I, T, output Z, PAD, input PADI ); + + IB INST1( .I(PADI), .O(Z)); + OBW INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module LED ( input PADDO, output LED ); + + xo2iobuf0111 LED_pad( .I(PADDO), .PAD(LED)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0111 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module C14M ( output PADDI, input C14M ); + + xo2iobuf0112 C14M_pad( .Z(PADDI), .PAD(C14M)); + + specify + (C14M => PADDI) = (0:0:0,0:0:0); + $width (posedge C14M, 0:0:0); + $width (negedge C14M, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0112 ( output Z, input PAD ); + + IB INST1( .I(PAD), .O(Z)); +endmodule + +module DQMH ( input IOLDO, output DQMH ); + + xo2iobuf0111 DQMH_pad( .I(IOLDO), .PAD(DQMH)); + + specify + (IOLDO => DQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module DQMH_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre DQMH_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre ( input D0, SP, CK, LSR, output Q ); + + FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module DQML ( input IOLDO, output DQML ); + + xo2iobuf0111 DQML_pad( .I(IOLDO), .PAD(DQML)); + + specify + (IOLDO => DQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module DQML_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre DQML_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + xo2iobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + xo2iobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + xo2iobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + xo2iobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + xo2iobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + xo2iobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RA_11_ ( input IOLDO, output RA11 ); + + xo2iobuf0111 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); + + specify + (IOLDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0113 \RA_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0113 ( input D0, SP, CK, LSR, output Q ); + + FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module RA_10_ ( input IOLDO, output RA10 ); + + xo2iobuf0111 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); + + specify + (IOLDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0113 \RA_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_9_ ( input IOLDO, output RA9 ); + + xo2iobuf0111 \RA_pad[9] ( .I(IOLDO), .PAD(RA9)); + + specify + (IOLDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0113 \RA_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_8_ ( input IOLDO, output RA8 ); + + xo2iobuf0111 \RA_pad[8] ( .I(IOLDO), .PAD(RA8)); + + specify + (IOLDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0113 \RA_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_7_ ( input IOLDO, output RA7 ); + + xo2iobuf0111 \RA_pad[7] ( .I(IOLDO), .PAD(RA7)); + + specify + (IOLDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_6_ ( input IOLDO, output RA6 ); + + xo2iobuf0111 \RA_pad[6] ( .I(IOLDO), .PAD(RA6)); + + specify + (IOLDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_5_ ( input IOLDO, output RA5 ); + + xo2iobuf0111 \RA_pad[5] ( .I(IOLDO), .PAD(RA5)); + + specify + (IOLDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_4_ ( input IOLDO, output RA4 ); + + xo2iobuf0111 \RA_pad[4] ( .I(IOLDO), .PAD(RA4)); + + specify + (IOLDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + + xo2iobuf0111 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input IOLDO, output RA2 ); + + xo2iobuf0111 \RA_pad[2] ( .I(IOLDO), .PAD(RA2)); + + specify + (IOLDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_1_ ( input IOLDO, output RA1 ); + + xo2iobuf0111 \RA_pad[1] ( .I(IOLDO), .PAD(RA1)); + + specify + (IOLDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \RA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + + xo2iobuf0111 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_1_ ( input IOLDO, output BA1 ); + + xo2iobuf0111 \BA_pad[1] ( .I(IOLDO), .PAD(BA1)); + + specify + (IOLDO => BA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); + wire VCCI, OPOS_dly, CLK_dly, LSR_dly; + + mfflsre0114 \BA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_dly), .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0114 ( input D0, SP, CK, LSR, output Q ); + + FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module BA_0_ ( input IOLDO, output BA0 ); + + xo2iobuf0111 \BA_pad[0] ( .I(IOLDO), .PAD(BA0)); + + specify + (IOLDO => BA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); + wire VCCI, OPOS_dly, CLK_dly, LSR_dly; + + mfflsre0114 \BA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_dly), .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRWE ( input IOLDO, output nRWE ); + + xo2iobuf0111 nRWE_pad( .I(IOLDO), .PAD(nRWE)); + + specify + (IOLDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nCAS ( input IOLDO, output nCAS ); + + xo2iobuf0111 nCAS_pad( .I(IOLDO), .PAD(nCAS)); + + specify + (IOLDO => nCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nCAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRAS ( input IOLDO, output nRAS ); + + xo2iobuf0111 nRAS_pad( .I(IOLDO), .PAD(nRAS)); + + specify + (IOLDO => nRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nCS ( input IOLDO, output nCS ); + + xo2iobuf0111 nCS_pad( .I(IOLDO), .PAD(nCS)); + + specify + (IOLDO => nCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nCS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CKE ( input IOLDO, output CKE ); + + xo2iobuf0111 CKE_pad( .I(IOLDO), .PAD(CKE)); + + specify + (IOLDO => CKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CKE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0113 CKE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nVOE ( input PADDO, output nVOE ); + + xo2iobuf0111 nVOE_pad( .I(PADDO), .PAD(nVOE)); + + specify + (PADDO => nVOE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_7_ ( input IOLDO, output Vout7 ); + + xo2iobuf0111 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7)); + + specify + (IOLDO => Vout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module Vout_6_ ( input IOLDO, output Vout6 ); + + xo2iobuf0111 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6)); + + specify + (IOLDO => Vout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_5_ ( input IOLDO, output Vout5 ); + + xo2iobuf0111 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5)); + + specify + (IOLDO => Vout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_4_ ( input IOLDO, output Vout4 ); + + xo2iobuf0111 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4)); + + specify + (IOLDO => Vout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_3_ ( input IOLDO, output Vout3 ); + + xo2iobuf0111 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3)); + + specify + (IOLDO => Vout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_2_ ( input IOLDO, output Vout2 ); + + xo2iobuf0111 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2)); + + specify + (IOLDO => Vout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_1_ ( input IOLDO, output Vout1 ); + + xo2iobuf0111 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1)); + + specify + (IOLDO => Vout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_0_ ( input IOLDO, output Vout0 ); + + xo2iobuf0111 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0)); + + specify + (IOLDO => Vout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module nDOE ( input PADDO, output nDOE ); + + xo2iobuf0111 nDOE_pad( .I(PADDO), .PAD(nDOE)); + + specify + (PADDO => nDOE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input IOLDO, output Dout7 ); + + xo2iobuf0115 \Dout_pad[7] ( .I(IOLDO), .PAD(Dout7)); + + specify + (IOLDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0115 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module Dout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_6_ ( input IOLDO, output Dout6 ); + + xo2iobuf0115 \Dout_pad[6] ( .I(IOLDO), .PAD(Dout6)); + + specify + (IOLDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_5_ ( input IOLDO, output Dout5 ); + + xo2iobuf0115 \Dout_pad[5] ( .I(IOLDO), .PAD(Dout5)); + + specify + (IOLDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_4_ ( input IOLDO, output Dout4 ); + + xo2iobuf0115 \Dout_pad[4] ( .I(IOLDO), .PAD(Dout4)); + + specify + (IOLDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_3_ ( input IOLDO, output Dout3 ); + + xo2iobuf0115 \Dout_pad[3] ( .I(IOLDO), .PAD(Dout3)); + + specify + (IOLDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_2_ ( input IOLDO, output Dout2 ); + + xo2iobuf0115 \Dout_pad[2] ( .I(IOLDO), .PAD(Dout2)); + + specify + (IOLDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_1_ ( input IOLDO, output Dout1 ); + + xo2iobuf0115 \Dout_pad[1] ( .I(IOLDO), .PAD(Dout1)); + + specify + (IOLDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_0_ ( input IOLDO, output Dout0 ); + + xo2iobuf0115 \Dout_pad[0] ( .I(IOLDO), .PAD(Dout0)); + + specify + (IOLDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0113 \Dout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + xo2iobuf0112 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + xo2iobuf0112 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + xo2iobuf0112 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + xo2iobuf0112 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + xo2iobuf0112 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + xo2iobuf0112 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + xo2iobuf0112 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + xo2iobuf0112 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module Ain_7_ ( output PADDI, input Ain7 ); + + xo2iobuf0112 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7)); + + specify + (Ain7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain7, 0:0:0); + $width (negedge Ain7, 0:0:0); + endspecify + +endmodule + +module Ain_6_ ( output PADDI, input Ain6 ); + + xo2iobuf0112 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6)); + + specify + (Ain6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain6, 0:0:0); + $width (negedge Ain6, 0:0:0); + endspecify + +endmodule + +module Ain_5_ ( output PADDI, input Ain5 ); + + xo2iobuf0112 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5)); + + specify + (Ain5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain5, 0:0:0); + $width (negedge Ain5, 0:0:0); + endspecify + +endmodule + +module Ain_4_ ( output PADDI, input Ain4 ); + + xo2iobuf0112 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4)); + + specify + (Ain4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain4, 0:0:0); + $width (negedge Ain4, 0:0:0); + endspecify + +endmodule + +module Ain_3_ ( output PADDI, input Ain3 ); + + xo2iobuf0112 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3)); + + specify + (Ain3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain3, 0:0:0); + $width (negedge Ain3, 0:0:0); + endspecify + +endmodule + +module Ain_2_ ( output PADDI, input Ain2 ); + + xo2iobuf0112 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2)); + + specify + (Ain2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain2, 0:0:0); + $width (negedge Ain2, 0:0:0); + endspecify + +endmodule + +module Ain_1_ ( output PADDI, input Ain1 ); + + xo2iobuf0112 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1)); + + specify + (Ain1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain1, 0:0:0); + $width (negedge Ain1, 0:0:0); + endspecify + +endmodule + +module Ain_0_ ( output PADDI, input Ain0 ); + + xo2iobuf0112 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0)); + + specify + (Ain0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain0, 0:0:0); + $width (negedge Ain0, 0:0:0); + endspecify + +endmodule + +module nC07X ( output PADDI, input nC07X ); + + xo2iobuf0112 nC07X_pad( .Z(PADDI), .PAD(nC07X)); + + specify + (nC07X => PADDI) = (0:0:0,0:0:0); + $width (posedge nC07X, 0:0:0); + $width (negedge nC07X, 0:0:0); + endspecify + +endmodule + +module nEN80 ( output PADDI, input nEN80 ); + + xo2iobuf0112 nEN80_pad( .Z(PADDI), .PAD(nEN80)); + + specify + (nEN80 => PADDI) = (0:0:0,0:0:0); + $width (posedge nEN80, 0:0:0); + $width (negedge nEN80, 0:0:0); + endspecify + +endmodule + +module nWE80 ( output PADDI, input nWE80 ); + + xo2iobuf0112 nWE80_pad( .Z(PADDI), .PAD(nWE80)); + + specify + (nWE80 => PADDI) = (0:0:0,0:0:0); + $width (posedge nWE80, 0:0:0); + $width (negedge nWE80, 0:0:0); + endspecify + +endmodule + +module nWE ( output PADDI, input nWE ); + + xo2iobuf0112 nWE_pad( .Z(PADDI), .PAD(nWE)); + + specify + (nWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nWE, 0:0:0); + $width (negedge nWE, 0:0:0); + endspecify + +endmodule + +module PHI1 ( output PADDI, input PHI1 ); + + xo2iobuf0112 PHI1_pad( .Z(PADDI), .PAD(PHI1)); + + specify + (PHI1 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI1, 0:0:0); + $width (negedge PHI1, 0:0:0); + endspecify + +endmodule + +module PHI1_MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre PHI1reg_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module smuxlregsre ( input D0, SP, CK, LSR, output Q ); + + IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, + WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, + WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output + WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, + WBACKO ); + wire VCCI, GNDI; + + EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), + .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), + .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), + .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), + .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), + .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), + .WBDATO1(WBDATO1), .WBDATO2(WBDATO2), .WBDATO3(WBDATO3), .WBDATO4(WBDATO4), + .WBDATO5(WBDATO5), .WBDATO6(WBDATO6), .WBDATO7(WBDATO7), .WBACKO(WBACKO), + .WBCUFMIRQ(), .UFMSN(VCCI), .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), + .I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), + .I2C2SCLI(GNDI), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), + .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), + .SPISCKEN(), .SPIMISOI(GNDI), .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), + .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), + .SPIMCSN3(), .SPIMCSN4(), .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), + .SPICSNEN(), .SPISCSN(GNDI), .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), + .TCIC(GNDI), .TCINT(), .TCOC(), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), + .PLL1STBO(), .PLLWEO(), .PLLADRO0(), .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), + .PLLADRO4(), .PLLDATO0(), .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), + .PLLDATO4(), .PLLDATO5(), .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), + .PLL0DATI1(GNDI), .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), + .PLL0DATI5(GNDI), .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), + .PLL1DATI0(GNDI), .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), + .PLL1DATI4(GNDI), .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), + .PLL1ACKI(GNDI)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); +endmodule + +module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, + WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, + WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, + WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, + WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output + I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input + I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, + I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, + input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output + SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, + SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, + input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, + PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, + PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, + PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, + PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, + PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI ); + wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, + WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, + WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, + WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, + WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, + PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, + PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, + PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, + PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, + I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, + SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, + UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, + WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, + PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, + PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, + PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, + PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, + I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, + I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, + I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, + SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, + SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, + SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, + CFGWAKE_buf, CFGSTDBY_buf; + + EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), + .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), + .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), + .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), + .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), + .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), + .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), + .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), + .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), + .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), + .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), + .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), + .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), + .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), + .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), + .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), + .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), + .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), + .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), + .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), + .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), + .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), + .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), + .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), + .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), + .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), + .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), + .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), + .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), + .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), + .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), + .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), + .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), + .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), + .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), + .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), + .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), + .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), + .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), + .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), + .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), + .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf)); + defparam INST10.DEV_DENSITY = "640L"; + defparam INST10.EFB_I2C1 = "DISABLED"; + defparam INST10.EFB_I2C2 = "DISABLED"; + defparam INST10.EFB_SPI = "DISABLED"; + defparam INST10.EFB_TC = "DISABLED"; + defparam INST10.EFB_TC_PORTMODE = "WB"; + defparam INST10.EFB_UFM = "ENABLED"; + defparam INST10.EFB_WB_CLK_FREQ = "14.4"; + defparam INST10.GSR = "ENABLED"; + defparam INST10.I2C1_ADDRESSING = "7BIT"; + defparam INST10.I2C1_BUS_PERF = "100kHz"; + defparam INST10.I2C1_CLK_DIVIDER = 1; + defparam INST10.I2C1_GEN_CALL = "DISABLED"; + defparam INST10.I2C1_SLAVE_ADDR = "0b1000001"; + defparam INST10.I2C1_WAKEUP = "DISABLED"; + defparam INST10.I2C2_ADDRESSING = "7BIT"; + defparam INST10.I2C2_BUS_PERF = "100kHz"; + defparam INST10.I2C2_CLK_DIVIDER = 1; + defparam INST10.I2C2_GEN_CALL = "DISABLED"; + defparam INST10.I2C2_SLAVE_ADDR = "0b1000010"; + defparam INST10.I2C2_WAKEUP = "DISABLED"; + defparam INST10.SPI_CLK_DIVIDER = 1; + defparam INST10.SPI_CLK_INV = "DISABLED"; + defparam INST10.SPI_INTR_RXOVR = "DISABLED"; + defparam INST10.SPI_INTR_RXRDY = "DISABLED"; + defparam INST10.SPI_INTR_TXOVR = "DISABLED"; + defparam INST10.SPI_INTR_TXRDY = "DISABLED"; + defparam INST10.SPI_LSB_FIRST = "DISABLED"; + defparam INST10.SPI_MODE = "MASTER"; + defparam INST10.SPI_PHASE_ADJ = "DISABLED"; + defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED"; + defparam INST10.SPI_WAKEUP = "DISABLED"; + defparam INST10.TC_CCLK_SEL = 1; + defparam INST10.TC_ICAPTURE = "DISABLED"; + defparam INST10.TC_ICR_INT = "OFF"; + defparam INST10.TC_MODE = "CTCM"; + defparam INST10.TC_OCR_INT = "OFF"; + defparam INST10.TC_OCR_SET = 32767; + defparam INST10.TC_OC_MODE = "TOGGLE"; + defparam INST10.TC_OVERFLOW = "DISABLED"; + defparam INST10.TC_OV_INT = "OFF"; + defparam INST10.TC_RESETN = "ENABLED"; + defparam INST10.TC_SCLK_SEL = "PCLOCK"; + defparam INST10.TC_TOP_SEL = "OFF"; + defparam INST10.TC_TOP_SET = 65535; + defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED"; + defparam INST10.UFM_INIT_FILE_FORMAT = "HEX"; + defparam INST10.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem"; + defparam INST10.UFM_INIT_PAGES = 1; + defparam INST10.UFM_INIT_START_PAGE = 190; + EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), + .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), + .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), + .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), + .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), + .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), + .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), + .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), + .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), + .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), + .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), + .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), + .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), + .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), + .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), + .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), + .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), + .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), + .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), + .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), + .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), + .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), + .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), + .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), + .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), + .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), + .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), + .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), + .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), + .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), + .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), + .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), + .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), + .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), + .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), + .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), + .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), + .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), + .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), + .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), + .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), + .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), + .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), + .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), + .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), + .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), + .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), + .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), + .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), + .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), + .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), + .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), + .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), + .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), + .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), + .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), + .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), + .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), + .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), + .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), + .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), + .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), + .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), + .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), + .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), + .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), + .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), + .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), + .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), + .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), + .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), + .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), + .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), + .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), + .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), + .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), + .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), + .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), + .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), + .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), + .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), + .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), + .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), + .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), + .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), + .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), + .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), + .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), + .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), + .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), + .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), + .CFGSTDBYin(CFGSTDBY_buf)); +endmodule + +module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, + output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, + output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output + WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output + WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output + WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output + WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output + WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output + WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output + WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output + WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output + PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, + output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input + PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, + input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output + PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, + output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input + PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, + input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output + PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, + output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input + I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, + input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, + input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, + input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, + input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input + TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input + WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input + WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input + WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input + WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input + WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input + PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, + input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, + input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, + input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, + input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, + input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, + input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, + input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, + input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output + I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, + output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input + I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, + input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output + I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, + output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, + output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input + SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, + input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output + SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, + output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, + output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, + output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, + output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, + output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, + output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin ); + wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, + WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, + WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, + WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, + WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly; + + BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout)); + BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout)); + BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout)); + BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout)); + BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout)); + BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out)); + BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out)); + BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out)); + BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out)); + BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out)); + BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out)); + BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out)); + BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out)); + BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out)); + BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out)); + BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out)); + BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out)); + BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out)); + BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out)); + BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out)); + BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out)); + BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out)); + BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out)); + BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out)); + BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out)); + BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out)); + BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out)); + BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out)); + BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out)); + BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout)); + BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out)); + BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out)); + BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out)); + BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out)); + BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out)); + BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out)); + BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out)); + BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out)); + BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout)); + BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout)); + BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout)); + BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout)); + BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout)); + BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout)); + BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout)); + BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout)); + BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout)); + BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout)); + BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout)); + BUFBA TCIC_buf( .A(TCICin), .Z(TCICout)); + BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout)); + BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out)); + BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out)); + BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out)); + BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out)); + BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out)); + BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out)); + BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out)); + BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out)); + BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout)); + BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout)); + BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout)); + BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout)); + BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout)); + BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout)); + BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out)); + BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out)); + BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out)); + BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out)); + BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out)); + BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out)); + BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out)); + BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out)); + BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out)); + BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out)); + BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out)); + BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out)); + BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out)); + BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout)); + BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout)); + BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout)); + BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout)); + BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout)); + BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout)); + BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout)); + BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout)); + BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout)); + BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout)); + BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout)); + BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout)); + BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout)); + BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout)); + BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout)); + BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout)); + BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out)); + BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out)); + BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out)); + BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out)); + BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out)); + BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out)); + BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out)); + BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out)); + BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout)); + BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout)); + BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout)); + BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout)); + BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout)); + BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout)); + BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout)); + + specify + (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO2out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO3out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO4out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO5out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO6out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO7out) = (0:0:0,0:0:0); + (WBCLKIin => WBACKOout) = (0:0:0,0:0:0); + $setuphold + (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly); + $setuphold + (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly); + $setuphold + (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly); + $setuphold + (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly); + $setuphold + (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly); + $setuphold + (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly); + $setuphold + (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly); + $setuphold + (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly); + $setuphold + (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly); + $setuphold + (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly); + $setuphold + (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly); + $setuphold + (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly); + $setuphold + (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly); + $setuphold + (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly); + $setuphold + (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly); + $setuphold + (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly); + $setuphold + (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly); + $setuphold + (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly); + $setuphold + (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly); + $setuphold + (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly); + $width (posedge WBCLKIin, 0:0:0); + $width (negedge WBCLKIin, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html new file mode 100644 index 0000000..506e8ec --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_mrp.html @@ -0,0 +1,485 @@ + +Project Summary + + +
    
+            Lattice Mapping Report File for Design Module 'RAM2E'
+
+
+
+Design Information
+
+Command line:   map -a MachXO2 -p LCMXO2-640HC -t TQFP100 -s 4 -oc Commercial
+     RAM2E_LCMXO2_640HC_impl1.ngd -o RAM2E_LCMXO2_640HC_impl1_map.ncd -pr
+     RAM2E_LCMXO2_640HC_impl1.prf -mp RAM2E_LCMXO2_640HC_impl1.mrp -lpf //Mac/iC
+     loud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.
+     lpf -lpf //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.lpf -c 0 -gui -msgset
+     //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml 
+Target Vendor:  LATTICE
+Target Device:  LCMXO2-640HCTQFP100
+Target Performance:   4
+Mapper:  xo2c00,  version:  Diamond (64-bit) 3.12.1.454
+Mapped on:  09/21/23  05:34:46
+
+
+Design Summary
+   Number of registers:    111 out of   877 (13%)
+      PFU registers:           75 out of   640 (12%)
+      PIO registers:           36 out of   237 (15%)
+   Number of SLICEs:       120 out of   320 (38%)
+      SLICEs as Logic/ROM:    120 out of   320 (38%)
+      SLICEs as RAM:            0 out of   240 (0%)
+      SLICEs as Carry:          9 out of   320 (3%)
+   Number of LUT4s:        239 out of   640 (37%)
+      Number used as logic LUTs:        221
+      Number used as distributed RAM:     0
+      Number used as ripple logic:       18
+      Number used as shift registers:     0
+   Number of PIO sites used: 70 + 4(JTAG) out of 79 (94%)
+   Number of block RAMs:  0 out of 2 (0%)
+   Number of GSRs:        0 out of 1 (0%)
+   EFB used :        Yes
+   JTAG used :       No
+   Readback used :   No
+   Oscillator used : No
+   Startup used :    No
+   POR :             On
+   Bandgap :         On
+   Number of Power Controller:  0 out of 1 (0%)
+   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
+   Number of DCCA:  0 out of 8 (0%)
+   Number of DCMA:  0 out of 2 (0%)
+   Notes:-
+      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
+     distributed RAMs) + 2*(Number of ripple logic)
+      2. Number of logic LUT4s does not include count of distributed RAM and
+     ripple logic.
+   Number of clocks:  1
+     Net C14M_c: 84 loads, 68 rising, 16 falling (Driver: PIO C14M )
+   Number of Clock Enables:  11
+     Net wb_adr_0_sqmuxa_i: 1 loads, 1 LSLICEs
+     Net N_576_i: 17 loads, 9 LSLICEs
+     Net LEDEN13: 4 loads, 4 LSLICEs
+     Net nCS61: 1 loads, 1 LSLICEs
+     Net Vout3: 8 loads, 0 LSLICEs
+     Net S_RNII9DO1_1[1]: 7 loads, 1 LSLICEs
+
+     Net un1_wb_cyc_stb_0_sqmuxa_1_i[0]: 1 loads, 1 LSLICEs
+     Net un1_wb_adr_0_sqmuxa_2_i[0]: 8 loads, 8 LSLICEs
+     Net N_104: 1 loads, 1 LSLICEs
+     Net N_88: 4 loads, 4 LSLICEs
+     Net un1_LEDEN_0_sqmuxa_1_i_0[0]: 1 loads, 1 LSLICEs
+   Number of LSRs:  5
+     Net un1_CS_0_sqmuxa_i: 2 loads, 2 LSLICEs
+     Net S[2]: 1 loads, 1 LSLICEs
+     Net N_566_i: 2 loads, 0 LSLICEs
+     Net wb_rst: 1 loads, 0 LSLICEs
+     Net S_RNII9DO1[1]: 1 loads, 1 LSLICEs
+   Number of nets driven by tri-state buffers:  0
+   Top 10 highest fanout non-clock nets:
+     Net S[2]: 48 loads
+     Net S[3]: 48 loads
+     Net S[0]: 30 loads
+     Net FS[12]: 22 loads
+     Net FS[9]: 21 loads
+     Net S[1]: 21 loads
+     Net FS[10]: 20 loads
+     Net FS[11]: 19 loads
+     Net RWSel: 19 loads
+     Net FS[13]: 17 loads
+
+
+
+
+   Number of warnings:  1
+   Number of errors:    0
+     
+
+
+
+
+Design Errors/Warnings
+
+WARNING - map: UFM was enabled in EFB: Enabling the configuration interface will
+     temporarily disable certain features of the device including Power
+     Controller, GSR, Hardened User SPI Port, Hardened Primary User I2C Port.
+     Functionality is restored after the Flash Memory (UFM/Configuration)
+     Interface is disabled using Disable Configuration Interface command 0x26
+     followed by Bypass command 0xFF. 
+
+
+
+IO (PIO) Attributes
+
++---------------------+-----------+-----------+------------+
+| IO Name             | Direction | Levelmode | IO         |
+|                     |           |  IO_TYPE  | Register   |
++---------------------+-----------+-----------+------------+
+| RD[0]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| LED                 | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| C14M                | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| DQMH                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+
+| DQML                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RD[7]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[6]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[5]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[4]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[3]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[2]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RD[1]               | BIDIR     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[11]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[10]              | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[9]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[8]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[7]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[6]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[5]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[4]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[3]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| RA[2]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[1]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| RA[0]               | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| BA[1]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| BA[0]               | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRWE                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nCAS                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nRAS                | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nCS                 | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| CKE                 | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nVOE                | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+
+| Vout[7]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[6]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[5]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[4]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[3]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[2]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[1]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Vout[0]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| nDOE                | OUTPUT    | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Dout[7]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[6]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[5]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[4]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[3]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[2]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[1]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Dout[0]             | OUTPUT    | LVCMOS33  | OUT        |
++---------------------+-----------+-----------+------------+
+| Din[7]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[6]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[5]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[4]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[3]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[2]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[1]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Din[0]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[7]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[6]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[5]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+
+| Ain[4]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[3]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[2]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[1]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| Ain[0]              | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nC07X               | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nEN80               | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nWE80               | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| nWE                 | INPUT     | LVCMOS33  |            |
++---------------------+-----------+-----------+------------+
+| PHI1                | INPUT     | LVCMOS33  | IN         |
++---------------------+-----------+-----------+------------+
+
+
+
+Removed logic
+
+Block GSR_INST undriven or does not drive anything - clipped.
+Signal Dout_0_.CN was merged into signal C14M_c
+Signal GND undriven or does not drive anything - clipped.
+Signal ufmefb/VCC undriven or does not drive anything - clipped.
+Signal ufmefb/GND undriven or does not drive anything - clipped.
+Signal FS_s_0_S1[15] undriven or does not drive anything - clipped.
+Signal FS_s_0_COUT[15] undriven or does not drive anything - clipped.
+Signal ufmefb/CFGSTDBY undriven or does not drive anything - clipped.
+Signal ufmefb/CFGWAKE undriven or does not drive anything - clipped.
+Signal ufmefb/wbc_ufm_irq undriven or does not drive anything - clipped.
+Signal ufmefb/TCOC undriven or does not drive anything - clipped.
+Signal ufmefb/TCINT undriven or does not drive anything - clipped.
+Signal ufmefb/SPIIRQO undriven or does not drive anything - clipped.
+Signal ufmefb/SPICSNEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN7 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN6 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN5 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN4 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN3 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN2 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN1 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMCSN0 undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMOSIEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMOSIO undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMISOEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPIMISOO undriven or does not drive anything - clipped.
+Signal ufmefb/SPISCKEN undriven or does not drive anything - clipped.
+Signal ufmefb/SPISCKO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2IRQO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1IRQO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SDAOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SDAO undriven or does not drive anything - clipped.
+
+Signal ufmefb/I2C2SCLOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C2SCLO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SDAOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SDAO undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SCLOEN undriven or does not drive anything - clipped.
+Signal ufmefb/I2C1SCLO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO1 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO2 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO3 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO4 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO5 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO6 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLDATO7 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO0 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO1 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO2 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO3 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLADRO4 undriven or does not drive anything - clipped.
+Signal ufmefb/PLLWEO undriven or does not drive anything - clipped.
+Signal ufmefb/PLL1STBO undriven or does not drive anything - clipped.
+Signal ufmefb/PLL0STBO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLRSTO undriven or does not drive anything - clipped.
+Signal ufmefb/PLLCLKO undriven or does not drive anything - clipped.
+Signal FS_cry_0_S0[0] undriven or does not drive anything - clipped.
+Signal N_1 undriven or does not drive anything - clipped.
+Block Vout_0_.CN was optimized away.
+Block GND was optimized away.
+Block ufmefb/VCC was optimized away.
+Block ufmefb/GND was optimized away.
+
+     
+
+
+
+Embedded Functional Block Connection Summary
+
+   Desired WISHBONE clock frequency: 14.4 MHz
+   Clock source:                     C14M_c
+   Reset source:                     wb_rst
+   Functions mode:
+      I2C #1 (Primary) Function:     DISABLED
+      I2C #2 (Secondary) Function:   DISABLED
+      SPI Function:                  DISABLED
+      Timer/Counter Function:        DISABLED
+      Timer/Counter Mode:            WB
+      UFM Connection:                ENABLED
+      PLL0 Connection:               DISABLED
+      PLL1 Connection:               DISABLED
+   I2C Function Summary:
+   --------------------
+      None
+   SPI Function Summary:
+   --------------------
+      None
+   Timer/Counter Function Summary:
+   ------------------------------
+
+      None
+   UFM Function Summary:
+   --------------------
+      UFM Utilization:        General Purpose Flash Memory
+      Initialized UFM Pages:  1 Pages (1*128 Bits)
+      Available General
+      Purpose Flash Memory:   191 Pages (191*128 Bits)
+
+           EBR Blocks with Unique
+      Initialization Data:    0
+
+           WID		EBR Instance
+      ---		------------
+
+
+
+
+ASIC Components
+---------------
+
+Instance Name: ufmefb/EFBInst_0
+         Type: EFB
+
+
+
+Run Time and Memory Usage
+-------------------------
+
+   Total CPU Time: 0 secs  
+   Total REAL Time: 0 secs  
+   Peak Memory Usage: 58 MB
+        
+
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+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+     Copyright (c) 1995 AT&T Corp.   All rights reserved.
+     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+     Copyright (c) 2001 Agere Systems   All rights reserved.
+     Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights
+     reserved.
+
+
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+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html new file mode 100644 index 0000000..64c8bcb --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_pad.html @@ -0,0 +1,352 @@ + +PAD Specification File + + +
    PAD Specification File
+***************************
+
+PART TYPE:        LCMXO2-640HC
+Performance Grade:      4
+PACKAGE:          TQFP100
+Package Status:                     Final          Version 1.39
+
+Thu Sep 21 05:35:00 2023
+
+Pinout by Port Name:
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| Port Name | Pin/Bank | Buffer Type   | Site  | PG Enable | BC Enable | Properties                                                 |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+| Ain[0]    | 3/3      | LVCMOS33_IN   | PL2C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[1]    | 2/3      | LVCMOS33_IN   | PL2B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[2]    | 7/3      | LVCMOS33_IN   | PL3A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[3]    | 4/3      | LVCMOS33_IN   | PL2D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[4]    | 78/0     | LVCMOS33_IN   | PT11A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[5]    | 84/0     | LVCMOS33_IN   | PT10A |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[6]    | 86/0     | LVCMOS33_IN   | PT9C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Ain[7]    | 8/3      | LVCMOS33_IN   | PL3B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| BA[0]     | 58/1     | LVCMOS33_OUT  | PR6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| BA[1]     | 60/1     | LVCMOS33_OUT  | PR6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| C14M      | 62/1     | LVCMOS33_IN   | PR5D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| CKE       | 53/1     | LVCMOS33_OUT  | PR7B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| DQMH      | 49/2     | LVCMOS33_OUT  | PB14D |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| DQML      | 48/2     | LVCMOS33_OUT  | PB14C |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Din[0]    | 96/0     | LVCMOS33_IN   | PT6D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[1]    | 97/0     | LVCMOS33_IN   | PT6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[2]    | 98/0     | LVCMOS33_IN   | PT6B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[3]    | 9/3      | LVCMOS33_IN   | PL3C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[4]    | 1/3      | LVCMOS33_IN   | PL2A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[5]    | 99/0     | LVCMOS33_IN   | PT6A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[6]    | 88/0     | LVCMOS33_IN   | PT9A  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Din[7]    | 87/0     | LVCMOS33_IN   | PT9B  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| Dout[0]   | 30/2     | LVCMOS33_OUT  | PB4D  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[1]   | 27/2     | LVCMOS33_OUT  | PB4A  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[2]   | 25/3     | LVCMOS33_OUT  | PL7D  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[3]   | 28/2     | LVCMOS33_OUT  | PB4B  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[4]   | 24/3     | LVCMOS33_OUT  | PL7C  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[5]   | 21/3     | LVCMOS33_OUT  | PL7B  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[6]   | 31/2     | LVCMOS33_OUT  | PB6A  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| Dout[7]   | 32/2     | LVCMOS33_OUT  | PB6B  |           |           | DRIVE:4mA SLEW:FAST                                        |
+| LED       | 35/2     | LVCMOS33_OUT  | PB6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| PHI1      | 85/0     | LVCMOS33_IN   | PT9D  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| RA[0]     | 66/1     | LVCMOS33_OUT  | PR3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[10]    | 64/1     | LVCMOS33_OUT  | PR5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[11]    | 59/1     | LVCMOS33_OUT  | PR6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[1]     | 68/1     | LVCMOS33_OUT  | PR3B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[2]     | 70/1     | LVCMOS33_OUT  | PR2D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[3]     | 74/1     | LVCMOS33_OUT  | PR2B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[4]     | 75/1     | LVCMOS33_OUT  | PR2A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[5]     | 71/1     | LVCMOS33_OUT  | PR2C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[6]     | 69/1     | LVCMOS33_OUT  | PR3A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[7]     | 67/1     | LVCMOS33_OUT  | PR3C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[8]     | 65/1     | LVCMOS33_OUT  | PR5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RA[9]     | 63/1     | LVCMOS33_OUT  | PR5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| RD[0]     | 36/2     | LVCMOS33_BIDI | PB10A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[1]     | 37/2     | LVCMOS33_BIDI | PB10B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[2]     | 38/2     | LVCMOS33_BIDI | PB10C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[3]     | 39/2     | LVCMOS33_BIDI | PB10D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[4]     | 40/2     | LVCMOS33_BIDI | PB12A |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[5]     | 41/2     | LVCMOS33_BIDI | PB12B |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[6]     | 42/2     | LVCMOS33_BIDI | PB12C |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| RD[7]     | 43/2     | LVCMOS33_BIDI | PB12D |           |           | DRIVE:4mA PULL:KEEPER CLAMP:ON HYSTERESIS:SMALL SLEW:SLOW  |
+| Vout[0]   | 18/3     | LVCMOS33_OUT  | PL6C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[1]   | 15/3     | LVCMOS33_OUT  | PL5D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[2]   | 17/3     | LVCMOS33_OUT  | PL6B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[3]   | 13/3     | LVCMOS33_OUT  | PL5B  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[4]   | 19/3     | LVCMOS33_OUT  | PL6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[5]   | 16/3     | LVCMOS33_OUT  | PL6A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[6]   | 14/3     | LVCMOS33_OUT  | PL5C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| Vout[7]   | 12/3     | LVCMOS33_OUT  | PL5A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nC07X     | 34/2     | LVCMOS33_IN   | PB6C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nCAS      | 52/1     | LVCMOS33_OUT  | PR7C  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nCS       | 57/1     | LVCMOS33_OUT  | PR6D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nDOE      | 20/3     | LVCMOS33_OUT  | PL7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nEN80     | 82/0     | LVCMOS33_IN   | PT10C |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nRAS      | 54/1     | LVCMOS33_OUT  | PR7A  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nRWE      | 51/1     | LVCMOS33_OUT  | PR7D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nVOE      | 10/3     | LVCMOS33_OUT  | PL3D  |           |           | DRIVE:4mA SLEW:SLOW                                        |
+| nWE       | 29/2     | LVCMOS33_IN   | PB4C  |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
+| nWE80     | 83/0     | LVCMOS33_IN   | PT10B |           |           | CLAMP:ON HYSTERESIS:SMALL                                  |
++-----------+----------+---------------+-------+-----------+-----------+------------------------------------------------------------+
+
+Vccio by Bank:
++------+-------+
+| Bank | Vccio |
++------+-------+
+| 0    | 3.3V  |
+| 1    | 3.3V  |
+| 2    | 3.3V  |
+| 3    | 3.3V  |
++------+-------+
+
+
+Vref by Bank:
++------+-----+-----------------+---------+
+| Vref | Pin | Bank # / Vref # | Load(s) |
++------+-----+-----------------+---------+
++------+-----+-----------------+---------+
+
+Pinout by Pin Number:
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| Pin/Bank | Pin Info              | Preference | Buffer Type   | Site  | Dual Function | PG Enable | BC Enable |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+| 1/3      | Din[4]                | LOCATED    | LVCMOS33_IN   | PL2A  |               |           |           |
+| 2/3      | Ain[1]                | LOCATED    | LVCMOS33_IN   | PL2B  |               |           |           |
+| 3/3      | Ain[0]                | LOCATED    | LVCMOS33_IN   | PL2C  | PCLKT3_2      |           |           |
+| 4/3      | Ain[3]                | LOCATED    | LVCMOS33_IN   | PL2D  | PCLKC3_2      |           |           |
+| 7/3      | Ain[2]                | LOCATED    | LVCMOS33_IN   | PL3A  |               |           |           |
+| 8/3      | Ain[7]                | LOCATED    | LVCMOS33_IN   | PL3B  |               |           |           |
+| 9/3      | Din[3]                | LOCATED    | LVCMOS33_IN   | PL3C  |               |           |           |
+| 10/3     | nVOE                  | LOCATED    | LVCMOS33_OUT  | PL3D  |               |           |           |
+| 12/3     | Vout[7]               | LOCATED    | LVCMOS33_OUT  | PL5A  | PCLKT3_1      |           |           |
+| 13/3     | Vout[3]               | LOCATED    | LVCMOS33_OUT  | PL5B  | PCLKC3_1      |           |           |
+| 14/3     | Vout[6]               | LOCATED    | LVCMOS33_OUT  | PL5C  |               |           |           |
+| 15/3     | Vout[1]               | LOCATED    | LVCMOS33_OUT  | PL5D  |               |           |           |
+| 16/3     | Vout[5]               | LOCATED    | LVCMOS33_OUT  | PL6A  |               |           |           |
+| 17/3     | Vout[2]               | LOCATED    | LVCMOS33_OUT  | PL6B  |               |           |           |
+| 18/3     | Vout[0]               | LOCATED    | LVCMOS33_OUT  | PL6C  |               |           |           |
+| 19/3     | Vout[4]               | LOCATED    | LVCMOS33_OUT  | PL6D  |               |           |           |
+| 20/3     | nDOE                  | LOCATED    | LVCMOS33_OUT  | PL7A  | PCLKT3_0      |           |           |
+| 21/3     | Dout[5]               | LOCATED    | LVCMOS33_OUT  | PL7B  | PCLKC3_0      |           |           |
+| 24/3     | Dout[4]               | LOCATED    | LVCMOS33_OUT  | PL7C  |               |           |           |
+| 25/3     | Dout[2]               | LOCATED    | LVCMOS33_OUT  | PL7D  |               |           |           |
+| 27/2     | Dout[1]               | LOCATED    | LVCMOS33_OUT  | PB4A  | CSSPIN        |           |           |
+| 28/2     | Dout[3]               | LOCATED    | LVCMOS33_OUT  | PB4B  |               |           |           |
+| 29/2     | nWE                   | LOCATED    | LVCMOS33_IN   | PB4C  |               |           |           |
+| 30/2     | Dout[0]               | LOCATED    | LVCMOS33_OUT  | PB4D  |               |           |           |
+| 31/2     | Dout[6]               | LOCATED    | LVCMOS33_OUT  | PB6A  | MCLK/CCLK     |           |           |
+| 32/2     | Dout[7]               | LOCATED    | LVCMOS33_OUT  | PB6B  | SO/SPISO      |           |           |
+| 34/2     | nC07X                 | LOCATED    | LVCMOS33_IN   | PB6C  | PCLKT2_0      |           |           |
+| 35/2     | LED                   | LOCATED    | LVCMOS33_OUT  | PB6D  | PCLKC2_0      |           |           |
+| 36/2     | RD[0]                 | LOCATED    | LVCMOS33_BIDI | PB10A |               |           |           |
+| 37/2     | RD[1]                 | LOCATED    | LVCMOS33_BIDI | PB10B |               |           |           |
+| 38/2     | RD[2]                 | LOCATED    | LVCMOS33_BIDI | PB10C | PCLKT2_1      |           |           |
+| 39/2     | RD[3]                 | LOCATED    | LVCMOS33_BIDI | PB10D | PCLKC2_1      |           |           |
+| 40/2     | RD[4]                 | LOCATED    | LVCMOS33_BIDI | PB12A |               |           |           |
+| 41/2     | RD[5]                 | LOCATED    | LVCMOS33_BIDI | PB12B |               |           |           |
+| 42/2     | RD[6]                 | LOCATED    | LVCMOS33_BIDI | PB12C |               |           |           |
+| 43/2     | RD[7]                 | LOCATED    | LVCMOS33_BIDI | PB12D |               |           |           |
+| 45/2     |     unused, PULL:DOWN |            |               | PB14A |               |           |           |
+| 47/2     |     unused, PULL:DOWN |            |               | PB14B |               |           |           |
+| 48/2     | DQML                  | LOCATED    | LVCMOS33_OUT  | PB14C | SN            |           |           |
+| 49/2     | DQMH                  | LOCATED    | LVCMOS33_OUT  | PB14D | SI/SISPI      |           |           |
+| 51/1     | nRWE                  | LOCATED    | LVCMOS33_OUT  | PR7D  |               |           |           |
+| 52/1     | nCAS                  | LOCATED    | LVCMOS33_OUT  | PR7C  |               |           |           |
+| 53/1     | CKE                   | LOCATED    | LVCMOS33_OUT  | PR7B  |               |           |           |
+| 54/1     | nRAS                  | LOCATED    | LVCMOS33_OUT  | PR7A  |               |           |           |
+| 57/1     | nCS                   | LOCATED    | LVCMOS33_OUT  | PR6D  |               |           |           |
+| 58/1     | BA[0]                 | LOCATED    | LVCMOS33_OUT  | PR6C  |               |           |           |
+| 59/1     | RA[11]                | LOCATED    | LVCMOS33_OUT  | PR6B  |               |           |           |
+| 60/1     | BA[1]                 | LOCATED    | LVCMOS33_OUT  | PR6A  |               |           |           |
+| 62/1     | C14M                  | LOCATED    | LVCMOS33_IN   | PR5D  | PCLKC1_0      |           |           |
+| 63/1     | RA[9]                 | LOCATED    | LVCMOS33_OUT  | PR5C  | PCLKT1_0      |           |           |
+| 64/1     | RA[10]                | LOCATED    | LVCMOS33_OUT  | PR5B  |               |           |           |
+| 65/1     | RA[8]                 | LOCATED    | LVCMOS33_OUT  | PR5A  |               |           |           |
+| 66/1     | RA[0]                 | LOCATED    | LVCMOS33_OUT  | PR3D  |               |           |           |
+| 67/1     | RA[7]                 | LOCATED    | LVCMOS33_OUT  | PR3C  |               |           |           |
+| 68/1     | RA[1]                 | LOCATED    | LVCMOS33_OUT  | PR3B  |               |           |           |
+| 69/1     | RA[6]                 | LOCATED    | LVCMOS33_OUT  | PR3A  |               |           |           |
+| 70/1     | RA[2]                 | LOCATED    | LVCMOS33_OUT  | PR2D  |               |           |           |
+| 71/1     | RA[5]                 | LOCATED    | LVCMOS33_OUT  | PR2C  |               |           |           |
+| 74/1     | RA[3]                 | LOCATED    | LVCMOS33_OUT  | PR2B  |               |           |           |
+| 75/1     | RA[4]                 | LOCATED    | LVCMOS33_OUT  | PR2A  |               |           |           |
+| 76/0     |     unused, PULL:DOWN |            |               | PT11D | DONE          |           |           |
+| 77/0     |     unused, PULL:DOWN |            |               | PT11C | INITN         |           |           |
+| 78/0     | Ain[4]                | LOCATED    | LVCMOS33_IN   | PT11A |               |           |           |
+| 81/0     |     unused, PULL:DOWN |            |               | PT10D | PROGRAMN      |           |           |
+| 82/0     | nEN80                 | LOCATED    | LVCMOS33_IN   | PT10C | JTAGENB       |           |           |
+| 83/0     | nWE80                 | LOCATED    | LVCMOS33_IN   | PT10B |               |           |           |
+| 84/0     | Ain[5]                | LOCATED    | LVCMOS33_IN   | PT10A |               |           |           |
+| 85/0     | PHI1                  | LOCATED    | LVCMOS33_IN   | PT9D  | SDA/PCLKC0_0  |           |           |
+| 86/0     | Ain[6]                | LOCATED    | LVCMOS33_IN   | PT9C  | SCL/PCLKT0_0  |           |           |
+| 87/0     | Din[7]                | LOCATED    | LVCMOS33_IN   | PT9B  | PCLKC0_1      |           |           |
+| 88/0     | Din[6]                | LOCATED    | LVCMOS33_IN   | PT9A  | PCLKT0_1      |           |           |
+| 90/0     | Reserved: sysCONFIG   |            |               | PT7D  | TMS           |           |           |
+| 91/0     | Reserved: sysCONFIG   |            |               | PT7C  | TCK           |           |           |
+| 94/0     | Reserved: sysCONFIG   |            |               | PT7B  | TDI           |           |           |
+| 95/0     | Reserved: sysCONFIG   |            |               | PT7A  | TDO           |           |           |
+| 96/0     | Din[0]                | LOCATED    | LVCMOS33_IN   | PT6D  |               |           |           |
+| 97/0     | Din[1]                | LOCATED    | LVCMOS33_IN   | PT6C  |               |           |           |
+| 98/0     | Din[2]                | LOCATED    | LVCMOS33_IN   | PT6B  |               |           |           |
+| 99/0     | Din[5]                | LOCATED    | LVCMOS33_IN   | PT6A  |               |           |           |
+| PT11B/0  |     unused, PULL:DOWN |            |               | PT11B |               |           |           |
++----------+-----------------------+------------+---------------+-------+---------------+-----------+-----------+
+
+sysCONFIG Pins:
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| Pad Name | sysCONFIG Pin Name | sysCONFIG Settings | Pin/Bank | Buffer Type | Config Pull Mode  |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+| PT7D     | TMS                | JTAG_PORT=ENABLE   | 90/0     |             | PULLUP            |
+| PT7C     | TCK/TEST_CLK       | JTAG_PORT=ENABLE   | 91/0     |             | NO pull up/down   |
+| PT7B     | TDI/MD7            | JTAG_PORT=ENABLE   | 94/0     |             | PULLUP            |
+| PT7A     | TDO                | JTAG_PORT=ENABLE   | 95/0     |             | PULLUP            |
++----------+--------------------+--------------------+----------+-------------+-------------------+
+
+Dedicated sysCONFIG Pins:
+
+
+List of All Pins' Locate Preferences Based on Final Placement After PAR 
+to Help Users Lock Down ALL the Pins Easily (by Simply Copy & Paste): 
+
+LOCATE  COMP  "Ain[0]"  SITE  "3";
+LOCATE  COMP  "Ain[1]"  SITE  "2";
+LOCATE  COMP  "Ain[2]"  SITE  "7";
+LOCATE  COMP  "Ain[3]"  SITE  "4";
+LOCATE  COMP  "Ain[4]"  SITE  "78";
+LOCATE  COMP  "Ain[5]"  SITE  "84";
+LOCATE  COMP  "Ain[6]"  SITE  "86";
+LOCATE  COMP  "Ain[7]"  SITE  "8";
+LOCATE  COMP  "BA[0]"  SITE  "58";
+LOCATE  COMP  "BA[1]"  SITE  "60";
+LOCATE  COMP  "C14M"  SITE  "62";
+LOCATE  COMP  "CKE"  SITE  "53";
+LOCATE  COMP  "DQMH"  SITE  "49";
+LOCATE  COMP  "DQML"  SITE  "48";
+LOCATE  COMP  "Din[0]"  SITE  "96";
+LOCATE  COMP  "Din[1]"  SITE  "97";
+LOCATE  COMP  "Din[2]"  SITE  "98";
+LOCATE  COMP  "Din[3]"  SITE  "9";
+LOCATE  COMP  "Din[4]"  SITE  "1";
+LOCATE  COMP  "Din[5]"  SITE  "99";
+LOCATE  COMP  "Din[6]"  SITE  "88";
+LOCATE  COMP  "Din[7]"  SITE  "87";
+LOCATE  COMP  "Dout[0]"  SITE  "30";
+LOCATE  COMP  "Dout[1]"  SITE  "27";
+LOCATE  COMP  "Dout[2]"  SITE  "25";
+LOCATE  COMP  "Dout[3]"  SITE  "28";
+LOCATE  COMP  "Dout[4]"  SITE  "24";
+LOCATE  COMP  "Dout[5]"  SITE  "21";
+LOCATE  COMP  "Dout[6]"  SITE  "31";
+LOCATE  COMP  "Dout[7]"  SITE  "32";
+LOCATE  COMP  "LED"  SITE  "35";
+LOCATE  COMP  "PHI1"  SITE  "85";
+LOCATE  COMP  "RA[0]"  SITE  "66";
+LOCATE  COMP  "RA[10]"  SITE  "64";
+LOCATE  COMP  "RA[11]"  SITE  "59";
+LOCATE  COMP  "RA[1]"  SITE  "68";
+LOCATE  COMP  "RA[2]"  SITE  "70";
+LOCATE  COMP  "RA[3]"  SITE  "74";
+LOCATE  COMP  "RA[4]"  SITE  "75";
+LOCATE  COMP  "RA[5]"  SITE  "71";
+LOCATE  COMP  "RA[6]"  SITE  "69";
+LOCATE  COMP  "RA[7]"  SITE  "67";
+LOCATE  COMP  "RA[8]"  SITE  "65";
+LOCATE  COMP  "RA[9]"  SITE  "63";
+LOCATE  COMP  "RD[0]"  SITE  "36";
+LOCATE  COMP  "RD[1]"  SITE  "37";
+LOCATE  COMP  "RD[2]"  SITE  "38";
+LOCATE  COMP  "RD[3]"  SITE  "39";
+LOCATE  COMP  "RD[4]"  SITE  "40";
+LOCATE  COMP  "RD[5]"  SITE  "41";
+LOCATE  COMP  "RD[6]"  SITE  "42";
+LOCATE  COMP  "RD[7]"  SITE  "43";
+LOCATE  COMP  "Vout[0]"  SITE  "18";
+LOCATE  COMP  "Vout[1]"  SITE  "15";
+LOCATE  COMP  "Vout[2]"  SITE  "17";
+LOCATE  COMP  "Vout[3]"  SITE  "13";
+LOCATE  COMP  "Vout[4]"  SITE  "19";
+LOCATE  COMP  "Vout[5]"  SITE  "16";
+LOCATE  COMP  "Vout[6]"  SITE  "14";
+LOCATE  COMP  "Vout[7]"  SITE  "12";
+LOCATE  COMP  "nC07X"  SITE  "34";
+LOCATE  COMP  "nCAS"  SITE  "52";
+LOCATE  COMP  "nCS"  SITE  "57";
+LOCATE  COMP  "nDOE"  SITE  "20";
+LOCATE  COMP  "nEN80"  SITE  "82";
+LOCATE  COMP  "nRAS"  SITE  "54";
+LOCATE  COMP  "nRWE"  SITE  "51";
+LOCATE  COMP  "nVOE"  SITE  "10";
+LOCATE  COMP  "nWE"  SITE  "29";
+LOCATE  COMP  "nWE80"  SITE  "83";
+
+
+
+
+
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Sep 21 05:35:04 2023
+
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+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html new file mode 100644 index 0000000..1dd7442 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_par.html @@ -0,0 +1,295 @@ + +Place & Route Report + + +
    PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+Thu Sep 21 05:34:51 2023
+
+C:/lscc/diamond/3.12/ispfpga\bin\nt64\par -f RAM2E_LCMXO2_640HC_impl1.p2t
+RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir
+RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset
+//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml
+
+
+Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
+
+Cost Table Summary
+Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
+Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
+----------   --------     -----        ------       -----------  -----------  ----         ------
+5_1   *      0            57.366       0            0.346        0            15           Completed
+* : Design saved.
+
+Total (real) run time for 1-seed: 15 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Lattice Place and Route Report for Design "RAM2E_LCMXO2_640HC_impl1_map.ncd"
+Thu Sep 21 05:34:51 2023
+
+
+Best Par Run
+PAR: Place And Route Diamond (64-bit) 3.12.1.454.
+Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd RAM2E_LCMXO2_640HC_impl1.prf
+Preference file: RAM2E_LCMXO2_640HC_impl1.prf.
+Placement level-cost: 5-1.
+Routing Iterations: 6
+
+Loading design for application par from file RAM2E_LCMXO2_640HC_impl1_map.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application par from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+License checked out.
+
+
+Ignore Preference Error(s):  True
+
+Device utilization summary:
+
+   PIO (prelim)   70+4(JTAG)/80      93% used
+                  70+4(JTAG)/79      94% bonded
+   IOLOGIC           36/80           45% used
+
+   SLICE            120/320          37% used
+
+   EFB                1/1           100% used
+
+
+Number of Signals: 395
+Number of Connections: 1126
+
+Pin Constraint Summary:
+   70 out of 70 pins locked (100% locked).
+
+The following 1 signal is selected to use the primary clock routing resources:
+    C14M_c (driver: C14M, clk load #: 84)
+
+WARNING - par: Signal "C14M_c" is selected to use Primary clock resources. However, its driver comp "C14M" is located at "62", which is not a dedicated pin for connecting to Primary clock resources. General routing has to be used to route this signal, and it might suffer from excessive delay or skew.
+
+The following 1 signal is selected to use the secondary clock routing resources:
+    N_576_i (driver: SLICE_20, clk load #: 0, sr load #: 0, ce load #: 17)
+
+No signal is selected as Global Set/Reset.
+Starting Placer Phase 0.
+............
+Finished Placer Phase 0.  REAL time: 0 secs 
+
+Starting Placer Phase 1.
+.....................
+Placer score = 63243.
+Finished Placer Phase 1.  REAL time: 8 secs 
+
+Starting Placer Phase 2.
+.
+Placer score =  62715
+Finished Placer Phase 2.  REAL time: 8 secs 
+
+
+
+Clock Report
+
+Global Clock Resources:
+  CLK_PIN    : 0 out of 8 (0%)
+  General PIO: 1 out of 80 (1%)
+  DCM        : 0 out of 2 (0%)
+  DCC        : 0 out of 8 (0%)
+
+Global Clocks:
+  PRIMARY "C14M_c" from comp "C14M" on PIO site "62 (PR5D)", clk load = 84
+  SECONDARY "N_576_i" from F1 on comp "SLICE_20" on site "R6C8A", clk load = 0, ce load = 17, sr load = 0
+
+  PRIMARY  : 1 out of 8 (12%)
+  SECONDARY: 1 out of 8 (12%)
+
+
+
+
+I/O Usage Summary (final):
+   70 + 4(JTAG) out of 80 (92.5%) PIO sites used.
+   70 + 4(JTAG) out of 79 (93.7%) bonded PIO sites used.
+   Number of PIO comps: 70; differential: 0.
+   Number of Vref pins used: 0.
+
+I/O Bank Usage Summary:
++----------+----------------+------------+-----------+
+| I/O Bank | Usage          | Bank Vccio | Bank Vref |
++----------+----------------+------------+-----------+
+| 0        | 12 / 19 ( 63%) | 3.3V       | -         |
+| 1        | 20 / 20 (100%) | 3.3V       | -         |
+| 2        | 18 / 20 ( 90%) | 3.3V       | -         |
+| 3        | 20 / 20 (100%) | 3.3V       | -         |
++----------+----------------+------------+-----------+
+
+Total placer CPU time: 8 secs 
+
+Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+0 connections routed; 1126 unrouted.
+Starting router resource preassignment
+WARNING - par: The driver of primary clock net C14M_c is not placed on one of the sites dedicated for primary clocks. This primary clock will be routed to an H-spine through general routing resource and might suffer from excessive delay or skew.
+
+Completed router resource preassignment. Real time: 13 secs 
+
+Start NBR router at 05:35:04 09/21/23
+
+*****************************************************************
+Info: NBR allows conflicts(one node used by more than one signal)
+      in the earlier iterations. In each iteration, it tries to  
+      solve the conflicts while keeping the critical connections 
+      routed as short as possible. The routing process is said to
+      be completed when no conflicts exist and all connections   
+      are routed.                                                
+Note: NBR uses a different method to calculate timing slacks. The
+      worst slack and total negative slack may not be the same as
+      that in TRCE report. You should always run TRCE to verify  
+      your design.                                               
+*****************************************************************
+
+Start NBR special constraint process at 05:35:05 09/21/23
+
+Start NBR section for initial routing at 05:35:05 09/21/23
+Level 4, iteration 1
+14(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs 
+
+Info: Initial congestion level at 75% usage is 0
+Info: Initial congestion area  at 75% usage is 0 (0.00%)
+
+Start NBR section for normal routing at 05:35:05 09/21/23
+Level 4, iteration 1
+4(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs 
+Level 4, iteration 2
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs 
+
+Start NBR section for setup/hold timing optimization with effort level 3 at 05:35:05 09/21/23
+
+Start NBR section for re-routing at 05:35:05 09/21/23
+Level 4, iteration 1
+0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; 
+Estimated worst slack/total negative slack<setup>: 57.366ns/0.000ns; real time: 14 secs 
+
+Start NBR section for post-routing at 05:35:05 09/21/23
+
+End NBR router with 0 unrouted connection
+
+NBR Summary
+-----------
+  Number of unrouted connections : 0 (0.00%)
+  Number of connections with timing violations : 0 (0.00%)
+  Estimated worst slack<setup> : 57.366ns
+  Timing score<setup> : 0
+-----------
+Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
+
+
+
+Total CPU time 14 secs 
+Total REAL time: 15 secs 
+Completely routed.
+End of route.  1126 routed (100.00%); 0 unrouted.
+
+Hold time timing score: 0, hold timing errors: 0
+
+Timing score: 0 
+
+Dumping design to file RAM2E_LCMXO2_640HC_impl1.dir/5_1.ncd.
+
+
+All signals are completely routed.
+
+
+PAR_SUMMARY::Run status = Completed
+PAR_SUMMARY::Number of unrouted conns = 0
+PAR_SUMMARY::Worst  slack<setup/<ns>> = 57.366
+PAR_SUMMARY::Timing score<setup/<ns>> = 0.000
+PAR_SUMMARY::Worst  slack<hold /<ns>> = 0.346
+PAR_SUMMARY::Timing score<hold /<ns>> = 0.000
+PAR_SUMMARY::Number of errors = 0
+
+Total CPU  time to completion: 15 secs 
+Total REAL time to completion: 15 secs 
+
+par done!
+
+Note: user must run 'Trace' for timing closure signoff.
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
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    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt new file mode 100644 index 0000000..1e28830 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_scck.rpt @@ -0,0 +1,51 @@ + +Copyright (C) 1994-2021 Synopsys, Inc. +This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. +and may only be used pursuant to the terms and conditions of a written license agreement +with Synopsys, Inc. All other use, reproduction, modification, or distribution of the +Synopsys software or the associated documentation is strictly prohibited. +Tool: Synplify Pro (R) +Build: R-2021.03L-SP1 +Install: C:\lscc\diamond\3.12\synpbase +OS: Windows 6.2 + +Hostname: ZANEMACWIN11 + +Implementation : impl1 + +# Written on Thu Sep 21 05:34:35 2023 + +##### FILES SYNTAX CHECKED ############################################## +Constraint File(s): "\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc" + +#Run constraint checker to find more issues with constraints. +######################################################################### + + + +No issues found in constraint syntax. + + + +Clock Summary +************* + + Start Requested Requested Clock Clock Clock +Level Clock Frequency Period Type Group Load +---------------------------------------------------------------------------------------- +0 - C14M 14.3 MHz 69.841 declared default_clkgroup 111 + +0 - System 100.0 MHz 10.000 system system_clkgroup 0 +======================================================================================== + + +Clock Load Summary +****************** + + Clock Source Clock Pin Non-clock Pin Non-clock Pin +Clock Load Pin Seq Example Seq Example Comb Example +---------------------------------------------------------------------------------------- +C14M 111 C14M(port) wb_rst.C - un1_C14M.I[0](inv) + +System 0 - - - - +======================================================================================== diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html new file mode 100644 index 0000000..0aea46c --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_summary.html @@ -0,0 +1,83 @@ + +Project Summary + + +
    
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    RAM2E_LCMXO2_640HC project summary
    Module Name:RAM2E_LCMXO2_640HCSynthesis:SynplifyPro
    Implementation Name:impl1Strategy Name:Strategy1
    Last Process:JEDEC FileState:Passed
    Target Device:LCMXO2-640HC-4TG100CDevice Family:MachXO2
    Device Type:LCMXO2-640HCPackage Type:TQFP100
    Performance grade:4Operating conditions:COM
    Logic preference file:RAM2E-LCMXO2.lpf
    Physical Preference file:impl1/RAM2E_LCMXO2_640HC_impl1.prf
    Product Version:3.12.1.454Patch Version:
    Updated:2023/09/21 05:35:24
    Implementation Location://Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1
    Project File://Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/RAM2E_LCMXO2_640HC.ldf
    
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    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html new file mode 100644 index 0000000..e39a6e5 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_synplify.html @@ -0,0 +1,755 @@ + +Synthesis Report + + +
    Synthesis Report
+#Build: Synplify Pro (R) R-2021.03L-SP1, Build 093R, Aug 10 2021
+#install: C:\lscc\diamond\3.12\synpbase
+#OS: Windows 8 6.2
+#Hostname: ZANEMACWIN11
+
+# Thu Sep 21 05:34:32 2023
+
+#Implementation: impl1
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys HDL Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Verilog Compiler, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\lucent\pmi_def.v" (library work)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
+@I::"C:\lscc\diamond\3.12\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
+@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v" (library work)
+@I::"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v" (library work)
+Verilog syntax check successful!
+
+Compiler output is up to date.  No re-compile necessary
+
+Selecting top level module RAM2E
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI in library work.
+Running optimization stage 1 on VHI .......
+Finished optimization stage 1 on VHI (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO in library work.
+Running optimization stage 1 on VLO .......
+Finished optimization stage 1 on VLO (CPU Time 0h:00m:00s, Memory Used current: 98MB peak: 99MB)
+@N: CG364 :"C:\lscc\diamond\3.12\synpbase\lib\lucent\machxo2.v":1800:7:1800:9|Synthesizing module EFB in library work.
+Running optimization stage 1 on EFB .......
+Finished optimization stage 1 on EFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\REFB.v":8:7:8:10|Synthesizing module REFB in library work.
+Running optimization stage 1 on REFB .......
+Finished optimization stage 1 on REFB (CPU Time 0h:00m:00s, Memory Used current: 99MB peak: 99MB)
+@N: CG364 :"\\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E-LCMXO2.v":1:7:1:11|Synthesizing module RAM2E in library work.
+Running optimization stage 1 on RAM2E .......
+Finished optimization stage 1 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 101MB)
+Running optimization stage 2 on RAM2E .......
+Finished optimization stage 2 on RAM2E (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Running optimization stage 2 on REFB .......
+Finished optimization stage 2 on REFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Running optimization stage 2 on EFB .......
+Finished optimization stage 2 on EFB (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Running optimization stage 2 on VLO .......
+Finished optimization stage 2 on VLO (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+Running optimization stage 2 on VHI .......
+Finished optimization stage 2 on VHI (CPU Time 0h:00m:00s, Memory Used current: 101MB peak: 102MB)
+
+At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 97MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Sep 21 05:34:32 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Sep 21 05:34:33 2023
+
+###########################################################]
+
+For a summary of runtime and memory usage for all design units, please see file:
+==========================================================
+@L: A:\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.rt.csv
+
+@END
+
+At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 30MB peak: 31MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Sep 21 05:34:33 2023
+
+###########################################################]
+###########################################################[
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Synopsys Netlist Linker, Version comp202103synp2, Build 093R, Built Aug 10 2021 09:15:36, @
+
+@N|Running in 64-bit mode
+File \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 99MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+
+Process completed successfully.
+# Thu Sep 21 05:34:34 2023
+
+###########################################################]
+# Thu Sep 21 05:34:34 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Pre-mapping, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+
+
+Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 132MB peak: 140MB)
+
+Reading constraint file: \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
+@L: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt 
+See clock summary report "\\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1_scck.rpt"
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 149MB peak: 149MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 150MB peak: 151MB)
+
+@N: FX493 |Applying initial value "0" on instance PHI1reg.
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+@N: FX493 |Applying initial value "0" on instance DOEEN.
+@N: FX493 |Applying initial value "0" on instance RWSel.
+@N: FX493 |Applying initial value "00000000" on instance RWBank[7:0].
+@N: FX493 |Applying initial value "1" on instance DQMH.
+@N: FX493 |Applying initial value "0" on instance Ready.
+@N: FX493 |Applying initial value "0" on instance CmdBitbangMXO2.
+@N: FX493 |Applying initial value "0" on instance CmdExecMXO2.
+@N: FX493 |Applying initial value "0" on instance CmdLEDGet.
+@N: FX493 |Applying initial value "0" on instance CmdLEDSet.
+@N: FX493 |Applying initial value "0" on instance CmdRWMaskSet.
+@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFLED.
+@N: FX493 |Applying initial value "0" on instance CmdSetRWBankFFMXO2.
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":375:4:375:9|Initial value on register nRWE is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "1" on instance nRWE.
+@N: FX493 |Applying initial value "0" on instance LEDEN.
+@N: FX493 |Applying initial value "00000000" on instance RWMask[7:0].
+@A: FX681 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Initial value on register S[3:0] is non-zero which can prevent the register from being packed into a block RAM or DSP.
+@N: FX493 |Applying initial value "0000" on instance S[3:0].
+@N: FX493 |Applying initial value "1" on instance DQML.
+@N: FX493 |Applying initial value "0" on instance CKE.
+@N: FX493 |Applying initial value "1" on instance nCS.
+@N: FX493 |Applying initial value "1" on instance nRAS.
+@N: FX493 |Applying initial value "1" on instance nCAS.
+
+Starting clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 181MB peak: 181MB)
+
+
+Finished clock optimization phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+
+Starting clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 182MB peak: 182MB)
+
+
+Finished clock optimization report phase (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+@N: FX1184 |Applying syn_allowed_resources blockrams=2 on top level netlist RAM2E 
+
+Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+
+Clock Summary
+******************
+
+          Start      Requested     Requested     Clock        Clock                Clock
+Level     Clock      Frequency     Period        Type         Group                Load 
+----------------------------------------------------------------------------------------
+0 -       C14M       14.3 MHz      69.841        declared     default_clkgroup     111  
+                                                                                        
+0 -       System     100.0 MHz     10.000        system       system_clkgroup      0    
+========================================================================================
+
+
+
+Clock Load Summary
+***********************
+
+           Clock     Source         Clock Pin       Non-clock Pin     Non-clock Pin     
+Clock      Load      Pin            Seq Example     Seq Example       Comb Example      
+----------------------------------------------------------------------------------------
+C14M       111       C14M(port)     wb_rst.C        -                 un1_C14M.I[0](inv)
+                                                                                        
+System     0         -              -               -                 -                 
+========================================================================================
+
+ICG Latch Removal Summary:
+Number of ICG latches removed: 0
+Number of ICG latches not removed:	0
+For details review file gcc_ICG_report.rpt
+
+
+@S |Clock Optimization Summary
+
+
+
+#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[
+
+1 non-gated/non-generated clock tree(s) driving 111 clock pin(s) of sequential element(s)
+0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
+0 instances converted, 0 sequential instances remain driven by gated/generated clocks
+
+=========================== Non-Gated/Non-Generated Clocks ============================
+Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
+---------------------------------------------------------------------------------------
+@KP:ckid0_0       C14M                port                   111        nCAS           
+=======================================================================================
+
+
+##### END OF CLOCK OPTIMIZATION REPORT ######
+
+@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
+Finished Pre Mapping Phase.
+
+Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 182MB peak: 182MB)
+
+
+Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+
+
+Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+
+Pre-mapping successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 99MB peak: 185MB)
+
+Process took 0h:00m:02s realtime, 0h:00m:01s cputime
+# Thu Sep 21 05:34:37 2023
+
+###########################################################]
+# Thu Sep 21 05:34:37 2023
+
+
+Copyright (C) 1994-2021 Synopsys, Inc.
+This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
+and may only be used pursuant to the terms and conditions of a written license agreement
+with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
+Synopsys software or the associated documentation is strictly prohibited.
+Tool: Synplify Pro (R)
+Build: R-2021.03L-SP1
+Install: C:\lscc\diamond\3.12\synpbase
+OS: Windows 6.2
+
+Hostname: ZANEMACWIN11
+
+Implementation : impl1
+Synopsys Lattice Technology Mapper, Version map202103lat, Build 070R, Built Oct  6 2021 11:12:38, @
+
+
+Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 128MB peak: 128MB)
+
+@N: MF916 |Option synthesis_strategy=base is enabled. 
+@N: MF248 |Running in 64-bit mode.
+@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
+
+Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 129MB peak: 140MB)
+
+
+Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 143MB)
+
+
+Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 147MB)
+
+
+
+Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 179MB peak: 179MB)
+
+@W: FA239 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|ROM DOEEN_2 (in view: work.RAM2E(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
+@N: MO106 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":376:8:376:9|Found ROM DOEEN_2 (in view: work.RAM2E(verilog)) with 16 words by 1 bit.
+
+Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 183MB)
+
+@N: MO231 :"\\mac\icloud\repos\ram2e\cpld\ram2e-lcmxo2.v":102:4:102:9|Found counter in view:work.RAM2E(verilog) instance FS[15:0] 
+@W: FX474 |User-specified initial value defined for some sequential elements which can prevent optimum synthesis results from being achieved. 
+
+Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 186MB)
+
+
+Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)
+
+
+Available hyper_sources - for debug and ip models
+	None Found
+
+
+Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+
+Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+
+Finished Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+
+Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+
+Finished preparing to map (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 189MB peak: 189MB)
+
+
+Finished technology mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+
+Pass		 CPU time		Worst Slack		Luts / Registers
+------------------------------------------------------------
+   1		0h:00m:02s		    29.35ns		 222 /       111
+
+Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 205MB peak: 205MB)
+
+@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.  
+
+Finished restoring hierarchy (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 206MB peak: 206MB)
+
+
+Start Writing Netlists (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 206MB)
+
+Writing Analyst data base \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\synwork\RAM2E_LCMXO2_640HC_impl1_m.srm
+
+Finished Writing Netlist Databases (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 206MB peak: 206MB)
+
+Writing EDIF Netlist and constraint files
+@N: FX1056 |Writing EDF file: \\Mac\iCloud\Repos\RAM2E\CPLD\LCMXO2-640HC\impl1\RAM2E_LCMXO2_640HC_impl1.edi
+@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF 
+
+Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
+
+
+Finished Writing Netlists (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 211MB peak: 211MB)
+
+
+Start final timing analysis (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 209MB peak: 211MB)
+
+@W: MT246 :"\\mac\icloud\repos\ram2e\cpld\lcmxo2-640hc\refb.v":78:8:78:16|Blackbox EFB is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
+@N: MT615 |Found clock C14M with period 69.84ns 
+
+
+##### START OF TIMING REPORT #####[
+# Timing report written on Thu Sep 21 05:34:43 2023
+#
+
+
+Top view:               RAM2E
+Requested Frequency:    14.3 MHz
+Wire load mode:         top
+Paths requested:        5
+Constraint File(s):    \\Mac\iCloud\Repos\RAM2E\CPLD\RAM2E.sdc
+                       
+@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
+
+@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
+
+
+
+Performance Summary
+*******************
+
+
+Worst slack in design: 31.782
+
+                   Requested     Estimated     Requested     Estimated                Clock        Clock           
+Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group           
+-------------------------------------------------------------------------------------------------------------------
+C14M               14.3 MHz      131.4 MHz     69.841        7.610         31.782     declared     default_clkgroup
+System             100.0 MHz     NA            10.000        NA            67.088     system       system_clkgroup 
+===================================================================================================================
+Estimated period and frequency reported as NA means no slack depends directly on the clock waveform
+
+
+
+
+
+Clock Relationships
+*******************
+
+Clocks            |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise 
+----------------------------------------------------------------------------------------------------------
+Starting  Ending  |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack
+----------------------------------------------------------------------------------------------------------
+System    C14M    |  69.841      67.088  |  No paths    -      |  No paths    -       |  No paths    -    
+C14M      System  |  69.841      68.797  |  No paths    -      |  No paths    -       |  No paths    -    
+C14M      C14M    |  69.841      62.231  |  No paths    -      |  34.920      31.782  |  No paths    -    
+==========================================================================================================
+ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
+       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
+
+
+
+Interface Information 
+*********************
+
+No IO constraint found
+
+
+
+====================================
+Detailed Report for Clock: C14M
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+             Starting                                     Arrival           
+Instance     Reference     Type        Pin     Net        Time        Slack 
+             Clock                                                          
+----------------------------------------------------------------------------
+S[2]         C14M          FD1S3AX     Q       S[2]       1.350       31.782
+S[3]         C14M          FD1S3AX     Q       S[3]       1.350       31.782
+S[0]         C14M          FD1S3AX     Q       S[0]       1.312       31.820
+S[1]         C14M          FD1S3AX     Q       S[1]       1.280       31.852
+FS[9]        C14M          FD1S3AX     Q       FS[9]      1.284       62.425
+FS[11]       C14M          FD1S3AX     Q       FS[11]     1.276       62.433
+FS[8]        C14M          FD1S3AX     Q       FS[8]      1.260       62.449
+FS[12]       C14M          FD1S3AX     Q       FS[12]     1.288       62.525
+FS[10]       C14M          FD1S3AX     Q       FS[10]     1.280       62.533
+RWSel        C14M          FD1P3AX     Q       RWSel      1.276       63.482
+============================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+                Starting                                       Required           
+Instance        Reference     Type         Pin     Net         Time         Slack 
+                Clock                                                             
+----------------------------------------------------------------------------------
+Dout_0io[0]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[1]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[2]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[3]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[4]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[5]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[6]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Dout_0io[7]     C14M          OFS1P3DX     SP      N_576_i     34.449       31.782
+Vout_0io[0]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
+Vout_0io[1]     C14M          OFS1P3DX     SP      Vout3       34.449       31.826
+==================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      34.920
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         34.449
+
+    - Propagation time:                      2.667
+    - Clock delay at starting point:         0.000 (ideal)
+    = Slack (critical) :                     31.782
+
+    Number of logic level(s):                1
+    Starting point:                          S[2] / Q
+    Ending point:                            Dout_0io[0] / SP
+    The start point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
+    The end   point is clocked by            C14M [falling] (rise=0.000 fall=34.920 period=69.841) on pin SCLK
+
+Instance / Net                   Pin      Pin               Arrival     No. of    
+Name                Type         Name     Dir     Delay     Time        Fan Out(s)
+----------------------------------------------------------------------------------
+S[2]                FD1S3AX      Q        Out     1.350     1.350 r     -         
+S[2]                Net          -        -       -         -           48        
+S_RNII9DO1_2[1]     ORCALUT4     B        In      0.000     1.350 r     -         
+S_RNII9DO1_2[1]     ORCALUT4     Z        Out     1.317     2.667 r     -         
+N_576_i             Net          -        -       -         -           18        
+Dout_0io[0]         OFS1P3DX     SP       In      0.000     2.667 r     -         
+==================================================================================
+
+
+
+
+====================================
+Detailed Report for Clock: System
+====================================
+
+
+
+Starting Points with Worst Slack
+********************************
+
+                     Starting                                          Arrival           
+Instance             Reference     Type     Pin         Net            Time        Slack 
+                     Clock                                                               
+-----------------------------------------------------------------------------------------
+ufmefb.EFBInst_0     System        EFB      WBACKO      wb_ack         0.000       67.088
+ufmefb.EFBInst_0     System        EFB      WBDATO0     wb_dato[0]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO1     wb_dato[1]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO2     wb_dato[2]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO3     wb_dato[3]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO4     wb_dato[4]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO5     wb_dato[5]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO6     wb_dato[6]     0.000       69.313
+ufmefb.EFBInst_0     System        EFB      WBDATO7     wb_dato[7]     0.000       69.313
+=========================================================================================
+
+
+Ending Points with Worst Slack
+******************************
+
+               Starting                                                          Required           
+Instance       Reference     Type        Pin     Net                             Time         Slack 
+               Clock                                                                                
+----------------------------------------------------------------------------------------------------
+RWMask[0]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[1]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[2]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[3]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[4]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[5]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[6]      System        FD1P3AX     SP      N_88                            69.369       67.088
+RWMask[7]      System        FD1P3AX     SP      N_88                            69.369       67.088
+LEDEN          System        FD1P3AX     SP      un1_LEDEN_0_sqmuxa_1_i_0[0]     69.369       67.736
+wb_cyc_stb     System        FD1P3AX     SP      N_104                           69.369       67.736
+====================================================================================================
+
+
+
+Worst Path Information
+***********************
+
+
+Path information for path number 1: 
+      Requested Period:                      69.841
+    - Setup time:                            0.472
+    + Clock delay at ending point:           0.000 (ideal)
+    = Required time:                         69.369
+
+    - Propagation time:                      2.282
+    - Clock delay at starting point:         0.000 (ideal)
+    - Estimated clock delay at start point:  -0.000
+    = Slack (non-critical) :                 67.088
+
+    Number of logic level(s):                2
+    Starting point:                          ufmefb.EFBInst_0 / WBACKO
+    Ending point:                            RWMask[0] / SP
+    The start point is clocked by            System [rising]
+    The end   point is clocked by            C14M [rising] (rise=0.000 fall=34.920 period=69.841) on pin CK
+
+Instance / Net                                     Pin        Pin               Arrival     No. of    
+Name                                  Type         Name       Dir     Delay     Time        Fan Out(s)
+------------------------------------------------------------------------------------------------------
+ufmefb.EFBInst_0                      EFB          WBACKO     Out     0.000     0.000 r     -         
+wb_ack                                Net          -          -       -         -           5         
+un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     A          In      0.000     0.000 r     -         
+un1_RWMask_0_sqmuxa_1_i_0_RNO[0]      ORCALUT4     Z          Out     1.017     1.017 r     -         
+un1_RWMask_0_sqmuxa_1_i_a2_0_1[0]     Net          -          -       -         -           1         
+un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     D          In      0.000     1.017 r     -         
+un1_RWMask_0_sqmuxa_1_i_0[0]          ORCALUT4     Z          Out     1.265     2.282 r     -         
+N_88                                  Net          -          -       -         -           8         
+RWMask[0]                             FD1P3AX      SP         In      0.000     2.282 r     -         
+======================================================================================================
+
+
+
+##### END OF TIMING REPORT #####]
+
+Timing exceptions that could not be applied
+
+Finished final timing analysis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+
+
+Finished timing report (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 210MB peak: 211MB)
+
+---------------------------------------
+Resource Usage Report
+Part: lcmxo2_640hc-4
+
+Register bits: 111 of 640 (17%)
+PIC Latch:       0
+I/O cells:       70
+
+
+Details:
+BB:             8
+CCU2D:          9
+EFB:            1
+FD1P3AX:        48
+FD1P3IX:        1
+FD1S3AX:        22
+FD1S3IX:        4
+GSR:            1
+IB:             22
+IFS1P3DX:       1
+INV:            1
+OB:             40
+OFS1P3BX:       6
+OFS1P3DX:       27
+OFS1P3IX:       2
+ORCALUT4:       221
+PUR:            1
+VHI:            2
+VLO:            2
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:04s; Memory used current: 77MB peak: 211MB)
+
+Process took 0h:00m:06s realtime, 0h:00m:04s cputime
+# Thu Sep 21 05:34:44 2023
+
+###########################################################]
+
+
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+
    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html new file mode 100644 index 0000000..266503b --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_tw1.html @@ -0,0 +1,289 @@ + +Lattice Map TRACE Report + + +
    Map TRACE Report
+
+Loading design for application trce from file ram2e_lcmxo2_640hc_impl1_map.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Thu Sep 21 05:34:48 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Design file:     ram2e_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2e_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1491 items scored, 0 timing errors detected.
+Report:   87.268MHz is the maximum frequency for this preference.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
+            1491 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 58.471ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[11]  (from C14M_c +)
+   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+
+   Delay:              11.306ns  (30.3% logic, 69.7% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.306ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     69.930ns delay constraint less
+      0.153ns DO_SET requirement (totaling 69.777ns) by 58.471ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452    SLICE_3.CLK to     SLICE_3.Q0 SLICE_3 (from C14M_c)
+ROUTE        19   e 1.234     SLICE_3.Q0 to    SLICE_64.A1 FS[11]
+CTOF_DEL    ---     0.495    SLICE_64.A1 to    SLICE_64.F1 SLICE_64
+ROUTE         4   e 1.234    SLICE_64.F1 to    SLICE_97.D0 N_577
+CTOF_DEL    ---     0.495    SLICE_97.D0 to    SLICE_97.F0 SLICE_97
+ROUTE         3   e 1.234    SLICE_97.F0 to    SLICE_75.D1 N_489
+CTOF_DEL    ---     0.495    SLICE_75.D1 to    SLICE_75.F1 SLICE_75
+ROUTE         3   e 0.480    SLICE_75.F1 to    SLICE_75.A0 N_628
+CTOF_DEL    ---     0.495    SLICE_75.A0 to    SLICE_75.F0 SLICE_75
+ROUTE         2   e 1.234    SLICE_75.F0 to    SLICE_71.C1 N_640
+CTOF_DEL    ---     0.495    SLICE_71.C1 to    SLICE_71.F1 SLICE_71
+ROUTE         1   e 1.234    SLICE_71.F1 to   SLICE_115.A0 un1_nCS61_1_i
+CTOF_DEL    ---     0.495   SLICE_115.A0 to   SLICE_115.F0 SLICE_115
+ROUTE         1   e 1.234   SLICE_115.F0 to *WE_MGIOL.OPOS nRWE_r_0 (to C14M_c)
+                  --------
+                   11.306   (30.3% logic, 69.7% route), 7 logic levels.
+
+Report:   87.268MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   87.268 MHz|   7  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 1 clocks:
+
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Thu Sep 21 05:34:48 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o RAM2E_LCMXO2_640HC_impl1.tw1 -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1_map.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Design file:     ram2e_lcmxo2_640hc_impl1_map.ncd
+Preference file: ram2e_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,M
+Report level:    verbose report, limited to 1 item per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1491 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
+            1491 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[0]  (from C14M_c +)
+   Destination:    FF         Data in        FS[0]  (to C14M_c +)
+
+   Delay:               0.434ns  (53.9% logic, 46.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.434ns physical path delay SLICE_0 to SLICE_0 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint requirement (totaling -0.013ns) by 0.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133    SLICE_0.CLK to     SLICE_0.Q1 SLICE_0 (from C14M_c)
+ROUTE         5   e 0.199     SLICE_0.Q1 to     SLICE_0.A1 FS[0]
+CTOF_DEL    ---     0.101     SLICE_0.A1 to     SLICE_0.F1 SLICE_0
+ROUTE         1   e 0.001     SLICE_0.F1 to    SLICE_0.DI1 FS_s[0] (to C14M_c)
+                  --------
+                    0.434   (53.9% logic, 46.1% route), 2 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   2  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 1 clocks:
+
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
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    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html new file mode 100644 index 0000000..a7358ba --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_twr.html @@ -0,0 +1,1195 @@ + +Lattice TRACE Report + + +
    Place & Route TRACE Report
+
+Loading design for application trce from file ram2e_lcmxo2_640hc_impl1.ncd.
+Design name: RAM2E
+NCD version: 3.3
+Vendor:      LATTICE
+Device:      LCMXO2-640HC
+Package:     TQFP100
+Performance: 4
+Loading device for application trce from file 'xo2c640.nph' in environment: C:/lscc/diamond/3.12/ispfpga.
+Package Status:                     Final          Version 1.39.
+Performance Hardware Data Status:   Final          Version 34.4.
+Setup and Hold Report
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.12.1.454
+Thu Sep 21 05:35:07 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Design file:     ram2e_lcmxo2_640hc_impl1.ncd
+Preference file: ram2e_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,4
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1491 items scored, 0 timing errors detected.
+Report:   79.592MHz is the maximum frequency for this preference.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
+            1491 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 57.366ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[11]  (from C14M_c +)
+   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+
+   Delay:              12.584ns  (27.2% logic, 72.8% route), 7 logic levels.
+
+ Constraint Details:
+
+     12.584ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     69.930ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 69.950ns) by 57.366ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
+ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
+CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
+ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
+CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
+ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
+CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
+ROUTE         3     0.453       R3C9C.F1 to       R3C9C.C0 N_628
+CTOF_DEL    ---     0.495       R3C9C.C0 to       R3C9C.F0 SLICE_75
+ROUTE         2     0.993       R3C9C.F0 to       R5C9A.A1 N_640
+CTOF_DEL    ---     0.495       R5C9A.A1 to       R5C9A.F1 SLICE_71
+ROUTE         1     0.623       R5C9A.F1 to      R5C10B.D0 un1_nCS61_1_i
+CTOF_DEL    ---     0.495      R5C10B.D0 to      R5C10B.F0 SLICE_115
+ROUTE         1     2.192      R5C10B.F0 to   IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
+                  --------
+                   12.584   (27.2% logic, 72.8% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.243       62.PADDI to    IOL_R7D.CLK C14M_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 57.494ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[11]  (from C14M_c +)
+   Destination:    FF         Data in        nRAS_0io  (to C14M_c +)
+
+   Delay:              12.456ns  (23.5% logic, 76.5% route), 6 logic levels.
+
+ Constraint Details:
+
+     12.456ns physical path delay SLICE_3 to nRAS_MGIOL meets
+     69.930ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 69.950ns) by 57.494ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to nRAS_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
+ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
+CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
+ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
+CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
+ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
+CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
+ROUTE         3     1.003       R3C9C.F1 to      R3C10D.A0 N_628
+CTOF_DEL    ---     0.495      R3C10D.A0 to      R3C10D.F0 SLICE_83
+ROUTE         2     1.505      R3C10D.F0 to      R5C10A.A0 N_559_1
+CTOF_DEL    ---     0.495      R5C10A.A0 to      R5C10A.F0 SLICE_80
+ROUTE         1     2.120      R5C10A.F0 to   IOL_R7A.OPOS nRAS_2_iv_i (to C14M_c)
+                  --------
+                   12.456   (23.5% logic, 76.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to nRAS_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.243       62.PADDI to    IOL_R7A.CLK C14M_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 57.502ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[11]  (from C14M_c +)
+   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+
+   Delay:              12.448ns  (23.5% logic, 76.5% route), 6 logic levels.
+
+ Constraint Details:
+
+     12.448ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     69.930ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 69.950ns) by 57.502ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
+ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
+CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
+ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
+CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
+ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
+CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
+ROUTE         3     0.710       R3C9C.F1 to       R3C9B.B0 N_628
+CTOF_DEL    ---     0.495       R3C9B.B0 to       R3C9B.F0 SLICE_76
+ROUTE         3     1.718       R3C9B.F0 to      R5C10B.C0 nCAS_0_sqmuxa
+CTOF_DEL    ---     0.495      R5C10B.C0 to      R5C10B.F0 SLICE_115
+ROUTE         1     2.192      R5C10B.F0 to   IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
+                  --------
+                   12.448   (23.5% logic, 76.5% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.243       62.PADDI to    IOL_R7D.CLK C14M_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 57.921ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[11]  (from C14M_c +)
+   Destination:    FF         Data in        nCS_0io  (to C14M_c +)
+
+   Delay:              12.029ns  (24.3% logic, 75.7% route), 6 logic levels.
+
+ Constraint Details:
+
+     12.029ns physical path delay SLICE_3 to nCS_MGIOL meets
+     69.930ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 69.950ns) by 57.921ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to nCS_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
+ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
+CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
+ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
+CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
+ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
+CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
+ROUTE         3     1.003       R3C9C.F1 to      R3C10D.A0 N_628
+CTOF_DEL    ---     0.495      R3C10D.A0 to      R3C10D.F0 SLICE_83
+ROUTE         2     1.505      R3C10D.F0 to      R6C10A.A0 N_559_1
+CTOF_DEL    ---     0.495      R6C10A.A0 to      R6C10A.F0 SLICE_79
+ROUTE         1     1.693      R6C10A.F0 to   IOL_R6D.OPOS N_559_i (to C14M_c)
+                  --------
+                   12.029   (24.3% logic, 75.7% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to nCS_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.243       62.PADDI to    IOL_R6D.CLK C14M_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.106ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[11]  (from C14M_c +)
+   Destination:    FF         Data in        nCAS_0io  (to C14M_c +)
+
+   Delay:              11.844ns  (24.7% logic, 75.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.844ns physical path delay SLICE_3 to nCAS_MGIOL meets
+     69.930ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 69.950ns) by 58.106ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to nCAS_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
+ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
+CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
+ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
+CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
+ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
+CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
+ROUTE         3     0.710       R3C9C.F1 to       R3C9B.B0 N_628
+CTOF_DEL    ---     0.495       R3C9B.B0 to       R3C9B.F0 SLICE_76
+ROUTE         3     1.511       R3C9B.F0 to       R5C9C.A0 nCAS_0_sqmuxa
+CTOF_DEL    ---     0.495       R5C9C.A0 to       R5C9C.F0 SLICE_78
+ROUTE         1     1.795       R5C9C.F0 to   IOL_R7C.OPOS N_561_i (to C14M_c)
+                  --------
+                   11.844   (24.7% logic, 75.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to nCAS_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.243       62.PADDI to    IOL_R7C.CLK C14M_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.447ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[11]  (from C14M_c +)
+   Destination:    FF         Data in        RA_0io[10]  (to C14M_c +)
+
+   Delay:              11.503ns  (25.4% logic, 74.6% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.503ns physical path delay SLICE_3 to RA[10]_MGIOL meets
+     69.930ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 69.950ns) by 58.447ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to RA[10]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
+ROUTE        19     2.765       R2C8C.Q0 to       R2C6A.A1 FS[11]
+CTOF_DEL    ---     0.495       R2C6A.A1 to       R2C6A.F1 SLICE_64
+ROUTE         4     0.791       R2C6A.F1 to       R3C6A.C0 N_577
+CTOF_DEL    ---     0.495       R3C6A.C0 to       R3C6A.F0 SLICE_97
+ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
+CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
+ROUTE         3     0.710       R3C9C.F1 to       R3C9B.B0 N_628
+CTOF_DEL    ---     0.495       R3C9B.B0 to       R3C9B.F0 SLICE_76
+ROUTE         3     1.170       R3C9B.F0 to       R5C9D.D1 nCAS_0_sqmuxa
+CTOF_DEL    ---     0.495       R5C9D.D1 to       R5C9D.F1 SLICE_69
+ROUTE         1     1.795       R5C9D.F1 to   IOL_R5B.OPOS RA_42[10] (to C14M_c)
+                  --------
+                   11.503   (25.4% logic, 74.6% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to RA[10]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.243       62.PADDI to    IOL_R5B.CLK C14M_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.587ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[2]  (from C14M_c +)
+   Destination:    FF         Data in        wb_adr[0]  (to C14M_c +)
+
+   Delay:              11.177ns  (26.2% logic, 73.8% route), 6 logic levels.
+
+ Constraint Details:
+
+     11.177ns physical path delay SLICE_34 to SLICE_35 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.587ns
+
+ Physical Path Details:
+
+      Data path SLICE_34 to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C9C.CLK to       R4C9C.Q0 SLICE_34 (from C14M_c)
+ROUTE        48     1.873       R4C9C.Q0 to       R6C9B.B0 S[2]
+CTOF_DEL    ---     0.495       R6C9B.B0 to       R6C9B.F0 SLICE_47
+ROUTE         7     2.435       R6C9B.F0 to       R4C5B.B0 S_RNII9DO1[1]
+CTOF_DEL    ---     0.495       R4C5B.B0 to       R4C5B.F0 SLICE_73
+ROUTE         8     1.931       R4C5B.F0 to       R4C4C.D0 N_455
+CTOF_DEL    ---     0.495       R4C4C.D0 to       R4C4C.F0 SLICE_89
+ROUTE         1     0.626       R4C4C.F0 to       R4C4A.D0 N_378
+CTOF_DEL    ---     0.495       R4C4A.D0 to       R4C4A.F0 SLICE_85
+ROUTE         1     1.385       R4C4A.F0 to       R2C4B.D0 wb_adr_7_0_4[0]
+CTOF_DEL    ---     0.495       R2C4B.D0 to       R2C4B.F0 SLICE_35
+ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 wb_adr_7[0] (to C14M_c)
+                  --------
+                   11.177   (26.2% logic, 73.8% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_34:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R4C9C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R2C4B.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.757ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[12]  (from C14M_c +)
+   Destination:    FF         Data in        nRWE_0io  (to C14M_c +)
+
+   Delay:              11.193ns  (30.6% logic, 69.4% route), 7 logic levels.
+
+ Constraint Details:
+
+     11.193ns physical path delay SLICE_3 to nRWE_MGIOL meets
+     69.930ns delay constraint less
+     -0.173ns skew and
+      0.153ns DO_SET requirement (totaling 69.950ns) by 58.757ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R2C8C.CLK to       R2C8C.Q1 SLICE_3 (from C14M_c)
+ROUTE        22     1.463       R2C8C.Q1 to       R3C6A.A1 FS[12]
+CTOF_DEL    ---     0.495       R3C6A.A1 to       R3C6A.F1 SLICE_97
+ROUTE         2     0.702       R3C6A.F1 to       R3C6A.B0 N_456
+CTOF_DEL    ---     0.495       R3C6A.B0 to       R3C6A.F0 SLICE_97
+ROUTE         3     1.345       R3C6A.F0 to       R3C9C.B1 N_489
+CTOF_DEL    ---     0.495       R3C9C.B1 to       R3C9C.F1 SLICE_75
+ROUTE         3     0.453       R3C9C.F1 to       R3C9C.C0 N_628
+CTOF_DEL    ---     0.495       R3C9C.C0 to       R3C9C.F0 SLICE_75
+ROUTE         2     0.993       R3C9C.F0 to       R5C9A.A1 N_640
+CTOF_DEL    ---     0.495       R5C9A.A1 to       R5C9A.F1 SLICE_71
+ROUTE         1     0.623       R5C9A.F1 to      R5C10B.D0 un1_nCS61_1_i
+CTOF_DEL    ---     0.495      R5C10B.D0 to      R5C10B.F0 SLICE_115
+ROUTE         1     2.192      R5C10B.F0 to   IOL_R7D.OPOS nRWE_r_0 (to C14M_c)
+                  --------
+                   11.193   (30.6% logic, 69.4% route), 7 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R2C8C.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to nRWE_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.243       62.PADDI to    IOL_R7D.CLK C14M_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 58.784ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        wb_adr[0]  (to C14M_c +)
+
+   Delay:              10.980ns  (26.7% logic, 73.3% route), 6 logic levels.
+
+ Constraint Details:
+
+     10.980ns physical path delay SLICE_33 to SLICE_35 meets
+     69.930ns delay constraint less
+      0.000ns skew and
+      0.166ns DIN_SET requirement (totaling 69.764ns) by 58.784ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C9D.CLK to       R4C9D.Q0 SLICE_33 (from C14M_c)
+ROUTE        30     1.676       R4C9D.Q0 to       R6C9B.C0 S[0]
+CTOF_DEL    ---     0.495       R6C9B.C0 to       R6C9B.F0 SLICE_47
+ROUTE         7     2.435       R6C9B.F0 to       R4C5B.B0 S_RNII9DO1[1]
+CTOF_DEL    ---     0.495       R4C5B.B0 to       R4C5B.F0 SLICE_73
+ROUTE         8     1.931       R4C5B.F0 to       R4C4C.D0 N_455
+CTOF_DEL    ---     0.495       R4C4C.D0 to       R4C4C.F0 SLICE_89
+ROUTE         1     0.626       R4C4C.F0 to       R4C4A.D0 N_378
+CTOF_DEL    ---     0.495       R4C4A.D0 to       R4C4A.F0 SLICE_85
+ROUTE         1     1.385       R4C4A.F0 to       R2C4B.D0 wb_adr_7_0_4[0]
+CTOF_DEL    ---     0.495       R2C4B.D0 to       R2C4B.F0 SLICE_35
+ROUTE         1     0.000       R2C4B.F0 to      R2C4B.DI0 wb_adr_7[0] (to C14M_c)
+                  --------
+                   10.980   (26.7% logic, 73.3% route), 6 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R4C9D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_35:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R2C4B.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 29.415ns (weighted slack = 58.830ns)
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              S[0]  (from C14M_c +)
+   Destination:    FF         Data in        Dout_0io[0]  (to C14M_c -)
+
+   Delay:               5.676ns  (16.7% logic, 83.3% route), 2 logic levels.
+
+ Constraint Details:
+
+      5.676ns physical path delay SLICE_33 to Dout[0]_MGIOL meets
+     34.965ns delay constraint less
+     -0.173ns skew and
+      0.047ns CE_SET requirement (totaling 35.091ns) by 29.415ns
+
+ Physical Path Details:
+
+      Data path SLICE_33 to Dout[0]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.452      R4C9D.CLK to       R4C9D.Q0 SLICE_33 (from C14M_c)
+ROUTE        30     1.881       R4C9D.Q0 to       R6C8A.A1 S[0]
+CTOF_DEL    ---     0.495       R6C8A.A1 to       R6C8A.F1 SLICE_20
+ROUTE        17     2.848       R6C8A.F1 to     IOL_B4D.CE N_576_i (to C14M_c)
+                  --------
+                    5.676   (16.7% logic, 83.3% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_33:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.070       62.PADDI to      R4C9D.CLK C14M_c
+                  --------
+                    3.070   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to Dout[0]_MGIOL:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     3.243       62.PADDI to    IOL_B4D.CLK C14M_c
+                  --------
+                    3.243   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report:   79.592MHz is the maximum frequency for this preference.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference                              |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |   14.300 MHz|   79.592 MHz|   7  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 1 clocks:
+
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
+
+
+Timing summary (Setup):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+
+--------------------------------------------------------------------------------
+Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.12.1.454
+Thu Sep 21 05:35:07 2023
+
+Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
+Copyright (c) 1995 AT&T Corp.   All rights reserved.
+Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
+Copyright (c) 2001 Agere Systems   All rights reserved.
+Copyright (c) 2002-2020 Lattice Semiconductor Corporation,  All rights reserved.
+
+Report Information
+------------------
+Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o RAM2E_LCMXO2_640HC_impl1.twr -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf 
+Design file:     ram2e_lcmxo2_640hc_impl1.ncd
+Preference file: ram2e_lcmxo2_640hc_impl1.prf
+Device,speed:    LCMXO2-640HC,m
+Report level:    verbose report, limited to 10 items per preference
+--------------------------------------------------------------------------------
+
+Preference Summary
+
+
  • FREQUENCY PORT "C14M" 14.300000 MHz (0 errors)
    •             1491 items scored, 0 timing errors detected.
+
+BLOCK ASYNCPATHS
+BLOCK RESETPATHS
+--------------------------------------------------------------------------------
+
+
+
+================================================================================
+Preference: FREQUENCY PORT "C14M" 14.300000 MHz ;
+            1491 items scored, 0 timing errors detected.
+--------------------------------------------------------------------------------
+
+
+Passed: The following path meets requirements by 0.346ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              wb_dati[3]  (from C14M_c +)
+   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
+
+   Delay:               0.305ns  (43.6% logic, 56.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.305ns physical path delay SLICE_41 to ufmefb/EFBInst_0 meets
+     -0.095ns WBDATI_HLD and
+      0.000ns delay constraint less
+     -0.054ns skew requirement (totaling -0.041ns) by 0.346ns
+
+ Physical Path Details:
+
+      Data path SLICE_41 to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C3B.CLK to       R2C3B.Q1 SLICE_41 (from C14M_c)
+ROUTE         1     0.172       R2C3B.Q1 to    EFB.WBDATI3 wb_dati[3] (to C14M_c)
+                  --------
+                    0.305   (43.6% logic, 56.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_41:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R2C3B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.113       62.PADDI to     EFB.WBCLKI C14M_c
+                  --------
+                    1.113   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.348ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              wb_dati[4]  (from C14M_c +)
+   Destination:    EFB        Port           ufmefb/EFBInst_0(ASIC)  (to C14M_c +)
+
+   Delay:               0.305ns  (43.6% logic, 56.4% route), 1 logic levels.
+
+ Constraint Details:
+
+      0.305ns physical path delay SLICE_42 to ufmefb/EFBInst_0 meets
+     -0.097ns WBDATI_HLD and
+      0.000ns delay constraint less
+     -0.054ns skew requirement (totaling -0.043ns) by 0.348ns
+
+ Physical Path Details:
+
+      Data path SLICE_42 to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C3D.CLK to       R2C3D.Q0 SLICE_42 (from C14M_c)
+ROUTE         1     0.172       R2C3D.Q0 to    EFB.WBDATI4 wb_dati[4] (to C14M_c)
+                  --------
+                    0.305   (43.6% logic, 56.4% route), 1 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_42:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R2C3D.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to ufmefb/EFBInst_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.113       62.PADDI to     EFB.WBCLKI C14M_c
+                  --------
+                    1.113   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[0]  (from C14M_c +)
+   Destination:    FF         Data in        FS[0]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_0 to SLICE_0 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_0 to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C7A.CLK to       R2C7A.Q1 SLICE_0 (from C14M_c)
+ROUTE         5     0.132       R2C7A.Q1 to       R2C7A.A1 FS[0]
+CTOF_DEL    ---     0.101       R2C7A.A1 to       R2C7A.F1 SLICE_0
+ROUTE         1     0.000       R2C7A.F1 to      R2C7A.DI1 FS_s[0] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R2C7A.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_0:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R2C7A.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdBitbangMXO2  (from C14M_c +)
+   Destination:    FF         Data in        CmdBitbangMXO2  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_12 to SLICE_12 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_12 to SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R4C6C.CLK to       R4C6C.Q0 SLICE_12 (from C14M_c)
+ROUTE         2     0.132       R4C6C.Q0 to       R4C6C.A0 CmdBitbangMXO2
+CTOF_DEL    ---     0.101       R4C6C.A0 to       R4C6C.F0 SLICE_12
+ROUTE         1     0.000       R4C6C.F0 to      R4C6C.DI0 CmdBitbangMXO2_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R4C6C.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_12:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R4C6C.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdLEDSet  (from C14M_c +)
+   Destination:    FF         Data in        CmdLEDSet  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_15 to SLICE_15 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_15 to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C5B.CLK to       R5C5B.Q0 SLICE_15 (from C14M_c)
+ROUTE         2     0.132       R5C5B.Q0 to       R5C5B.A0 CmdLEDSet
+CTOF_DEL    ---     0.101       R5C5B.A0 to       R5C5B.F0 SLICE_15
+ROUTE         1     0.000       R5C5B.F0 to      R5C5B.DI0 CmdLEDSet_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R5C5B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_15:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R5C5B.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdRWMaskSet  (from C14M_c +)
+   Destination:    FF         Data in        CmdRWMaskSet  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_16 to SLICE_16 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_16 to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R5C5C.CLK to       R5C5C.Q0 SLICE_16 (from C14M_c)
+ROUTE         2     0.132       R5C5C.Q0 to       R5C5C.A0 CmdRWMaskSet
+CTOF_DEL    ---     0.101       R5C5C.A0 to       R5C5C.F0 SLICE_16
+ROUTE         1     0.000       R5C5C.F0 to      R5C5C.DI0 CmdRWMaskSet_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R5C5C.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_16:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R5C5C.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdSetRWBankFFLED  (from C14M_c +)
+   Destination:    FF         Data in        CmdSetRWBankFFLED  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_17 to SLICE_17 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_17 to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C5C.CLK to       R6C5C.Q0 SLICE_17 (from C14M_c)
+ROUTE         2     0.132       R6C5C.Q0 to       R6C5C.A0 CmdSetRWBankFFLED
+CTOF_DEL    ---     0.101       R6C5C.A0 to       R6C5C.F0 SLICE_17
+ROUTE         1     0.000       R6C5C.F0 to      R6C5C.DI0 CmdSetRWBankFFLED_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R6C5C.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_17:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R6C5C.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              CmdSetRWBankFFMXO2  (from C14M_c +)
+   Destination:    FF         Data in        CmdSetRWBankFFMXO2  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_18 to SLICE_18 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_18 to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R6C6D.CLK to       R6C6D.Q0 SLICE_18 (from C14M_c)
+ROUTE         2     0.132       R6C6D.Q0 to       R6C6D.A0 CmdSetRWBankFFMXO2
+CTOF_DEL    ---     0.101       R6C6D.A0 to       R6C6D.F0 SLICE_18
+ROUTE         1     0.000       R6C6D.F0 to      R6C6D.DI0 CmdSetRWBankFFMXO2_4 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R6C6D.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_18:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R6C6D.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              FS[11]  (from C14M_c +)
+   Destination:    FF         Data in        FS[11]  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_3 to SLICE_3 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_3 to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C8C.CLK to       R2C8C.Q0 SLICE_3 (from C14M_c)
+ROUTE        19     0.132       R2C8C.Q0 to       R2C8C.A0 FS[11]
+CTOF_DEL    ---     0.101       R2C8C.A0 to       R2C8C.F0 SLICE_3
+ROUTE         1     0.000       R2C8C.F0 to      R2C8C.DI0 FS_s[11] (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R2C8C.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_3:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R2C8C.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+
+Passed: The following path meets requirements by 0.379ns
+
+ Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
+
+   Source:         FF         Q              Ready  (from C14M_c +)
+   Destination:    FF         Data in        Ready  (to C14M_c +)
+
+   Delay:               0.366ns  (63.9% logic, 36.1% route), 2 logic levels.
+
+ Constraint Details:
+
+      0.366ns physical path delay SLICE_32 to SLICE_32 meets
+     -0.013ns DIN_HLD and
+      0.000ns delay constraint less
+      0.000ns skew requirement (totaling -0.013ns) by 0.379ns
+
+ Physical Path Details:
+
+      Data path SLICE_32 to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+REG_DEL     ---     0.133      R2C9C.CLK to       R2C9C.Q0 SLICE_32 (from C14M_c)
+ROUTE         2     0.132       R2C9C.Q0 to       R2C9C.A0 Ready
+CTOF_DEL    ---     0.101       R2C9C.A0 to       R2C9C.F0 SLICE_32
+ROUTE         1     0.000       R2C9C.F0 to      R2C9C.DI0 N_876_0 (to C14M_c)
+                  --------
+                    0.366   (63.9% logic, 36.1% route), 2 logic levels.
+
+ Clock Skew Details: 
+
+      Source Clock Path C14M to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R2C9C.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+      Destination Clock Path C14M to SLICE_32:
+
+   Name    Fanout   Delay (ns)          Site               Resource
+ROUTE        84     1.059       62.PADDI to      R2C9C.CLK C14M_c
+                  --------
+                    1.059   (0.0% logic, 100.0% route), 0 logic levels.
+
+Report Summary
+--------------
+----------------------------------------------------------------------------
+Preference(MIN Delays)                  |   Constraint|       Actual|Levels
+----------------------------------------------------------------------------
+                                        |             |             |
+FREQUENCY PORT "C14M" 14.300000 MHz ;   |            -|            -|   1  
+                                        |             |             |
+----------------------------------------------------------------------------
+
+
+All preferences were met.
+
+
+Clock Domains Analysis
+------------------------
+
+Found 1 clocks:
+
+Clock Domain: C14M_c   Source: C14M.PAD   Loads: 84
+   Covered under: FREQUENCY PORT "C14M" 14.300000 MHz ;
+
+
+Timing summary (Hold):
+---------------
+
+Timing errors: 0  Score: 0
+Cumulative negative slack: 0
+
+Constraints cover 1491 paths, 1 nets, and 933 connections (82.86% coverage)
+
+
+
+Timing summary (Setup and Hold):
+---------------
+
+Timing errors: 0 (setup), 0 (hold)
+Score: 0 (setup), 0 (hold)
+Cumulative negative slack: 0 (0+0)
+--------------------------------------------------------------------------------
+
+--------------------------------------------------------------------------------
+
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    + + diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf new file mode 100644 index 0000000..5fa7701 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.sdf @@ -0,0 +1,4946 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "RAM2E") + (DATE "Thu Sep 21 05:35:15 2023") + (VENDOR "Lattice") + (PROGRAM "ldbanno") + (VERSION "Diamond (64-bit) 3.12.1.454") + (DIVIDER /) + (VOLTAGE 1.26:1.20:1.14) + (PROCESS "default") + (TEMPERATURE -40:25:85) + (TIMESCALE 1ps) + (CELL + (CELLTYPE "SLICE_0") + (INSTANCE SLICE_0) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_1") + (INSTANCE SLICE_1) + (DELAY + (ABSOLUTE + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_2") + (INSTANCE SLICE_2) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_3") + (INSTANCE SLICE_3) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_4") + (INSTANCE SLICE_4) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_5") + (INSTANCE SLICE_5) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_6") + (INSTANCE SLICE_6) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_7") + (INSTANCE SLICE_7) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_8") + (INSTANCE SLICE_8) + (DELAY + (ABSOLUTE + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 FCO (718:803:889)(718:803:889)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F1 (718:803:889)(718:803:889)) + (IOPATH A0 FCO (827:925:1023)(827:925:1023)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + (IOPATH FCI F0 (473:529:585)(473:529:585)) + (IOPATH FCI F1 (519:581:643)(519:581:643)) + (IOPATH FCI FCO (130:146:162)(130:146:162)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_9") + (INSTANCE SLICE_9) + (DELAY + (ABSOLUTE + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_10") + (INSTANCE SLICE_10) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + (IOPATH CLK Q1 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI1 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_11") + (INSTANCE SLICE_11) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD LSR (posedge CLK) (225:249:274)(-225:-183:-141)) + ) + (TIMINGCHECK + (WIDTH (posedge LSR) (4000:4000:4000)) + (WIDTH (negedge LSR) (4000:4000:4000)) + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_12") + (INSTANCE SLICE_12) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_13") + (INSTANCE SLICE_13) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_14") + (INSTANCE SLICE_14) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH B0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_15") + (INSTANCE SLICE_15) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH C1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 (367:431:495)(367:431:495)) + (IOPATH C0 F0 (367:431:495)(367:431:495)) + (IOPATH A0 F0 (367:431:495)(367:431:495)) + (IOPATH CLK Q0 (392:422:452)(392:422:452)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI0 (posedge CLK) (130:148:166)(-34:-22:-11)) + (SETUPHOLD CE (posedge CLK) (229:255:282)(-99:-89:-79)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1250:1250:1250)) + (WIDTH (negedge CLK) (1250:1250:1250)) + ) + ) + (CELL + (CELLTYPE "SLICE_16") + (INSTANCE SLICE_16) + (DELAY + (ABSOLUTE + (IOPATH D1 F1 (367:431:495)(367:431:495)) + (IOPATH B1 F1 (367:431:495)(367:431:495)) + (IOPATH A1 F1 (367:431:495)(367:431:495)) + (IOPATH D0 F0 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Dout\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH IOLDO Dout1 (3725:3847:3970)(3725:3847:3970)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_1__MGIOL") + (INSTANCE Dout\[1\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IOLDO (546:556:567)(546:556:567)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + (TIMINGCHECK + (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86)) + (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36)) + ) + ) + (CELL + (CELLTYPE "Dout_0_") + (INSTANCE Dout\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH IOLDO Dout0 (3725:3847:3970)(3725:3847:3970)) + ) + ) + ) + (CELL + (CELLTYPE "Dout_0__MGIOL") + (INSTANCE Dout\[0\]_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IOLDO (546:556:567)(546:556:567)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + (TIMINGCHECK + (SETUPHOLD OPOS (negedge CLK) (153:153:153)(-86:-86:-86)) + (SETUPHOLD CE (negedge CLK) (47:47:47)(-36:-36:-36)) + ) + ) + (CELL + (CELLTYPE "Din_7_") + (INSTANCE Din\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din7 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din7) (3330:3330:3330)) + (WIDTH (negedge Din7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_6_") + (INSTANCE Din\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din6 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din6) (3330:3330:3330)) + (WIDTH (negedge Din6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_5_") + (INSTANCE Din\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din5 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din5) (3330:3330:3330)) + (WIDTH (negedge Din5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_4_") + (INSTANCE Din\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din4 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din4) (3330:3330:3330)) + (WIDTH (negedge Din4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_3_") + (INSTANCE Din\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din3 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din3) (3330:3330:3330)) + (WIDTH (negedge Din3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_2_") + (INSTANCE Din\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din2 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din2) (3330:3330:3330)) + (WIDTH (negedge Din2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_1_") + (INSTANCE Din\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din1) (3330:3330:3330)) + (WIDTH (negedge Din1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Din_0_") + (INSTANCE Din\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Din0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Din0) (3330:3330:3330)) + (WIDTH (negedge Din0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_7_") + (INSTANCE Ain\[7\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain7 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain7) (3330:3330:3330)) + (WIDTH (negedge Ain7) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_6_") + (INSTANCE Ain\[6\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain6 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain6) (3330:3330:3330)) + (WIDTH (negedge Ain6) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_5_") + (INSTANCE Ain\[5\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain5 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain5) (3330:3330:3330)) + (WIDTH (negedge Ain5) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_4_") + (INSTANCE Ain\[4\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain4 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain4) (3330:3330:3330)) + (WIDTH (negedge Ain4) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_3_") + (INSTANCE Ain\[3\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain3 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain3) (3330:3330:3330)) + (WIDTH (negedge Ain3) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_2_") + (INSTANCE Ain\[2\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain2 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain2) (3330:3330:3330)) + (WIDTH (negedge Ain2) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_1_") + (INSTANCE Ain\[1\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain1) (3330:3330:3330)) + (WIDTH (negedge Ain1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "Ain_0_") + (INSTANCE Ain\[0\]_I) + (DELAY + (ABSOLUTE + (IOPATH Ain0 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge Ain0) (3330:3330:3330)) + (WIDTH (negedge Ain0) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nC07X") + (INSTANCE nC07X_I) + (DELAY + (ABSOLUTE + (IOPATH nC07X PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nC07X) (3330:3330:3330)) + (WIDTH (negedge nC07X) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nEN80") + (INSTANCE nEN80_I) + (DELAY + (ABSOLUTE + (IOPATH nEN80 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nEN80) (3330:3330:3330)) + (WIDTH (negedge nEN80) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nWE80") + (INSTANCE nWE80_I) + (DELAY + (ABSOLUTE + (IOPATH nWE80 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nWE80) (3330:3330:3330)) + (WIDTH (negedge nWE80) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "nWE") + (INSTANCE nWE_I) + (DELAY + (ABSOLUTE + (IOPATH nWE PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge nWE) (3330:3330:3330)) + (WIDTH (negedge nWE) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "PHI1") + (INSTANCE PHI1_I) + (DELAY + (ABSOLUTE + (IOPATH PHI1 PADDI (1007:1069:1132)(1007:1069:1132)) + ) + ) + (TIMINGCHECK + (WIDTH (posedge PHI1) (3330:3330:3330)) + (WIDTH (negedge PHI1) (3330:3330:3330)) + ) + ) + (CELL + (CELLTYPE "PHI1_MGIOL") + (INSTANCE PHI1_MGIOL) + (DELAY + (ABSOLUTE + (IOPATH CLK IN (577:577:577)(577:577:577)) + ) + ) + (TIMINGCHECK + (SETUPHOLD DI (posedge CLK) (595:595:595)(223:223:223)) + ) + (TIMINGCHECK + (WIDTH (posedge CLK) (1855:1855:1855)) + (WIDTH (negedge CLK) (1855:1855:1855)) + ) + ) + (CELL + (CELLTYPE "EFB_Buffer_Block") + (INSTANCE ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20) + (DELAY + (ABSOLUTE + (IOPATH WBCLKIin WBDATO0out (978:3628:6278)(978:3628:6278)) + (IOPATH WBCLKIin WBDATO1out (947:3204:5461)(947:3204:5461)) + (IOPATH WBCLKIin WBDATO2out (955:3211:5468)(955:3211:5468)) + (IOPATH WBCLKIin WBDATO3out (910:3173:5436)(910:3173:5436)) + (IOPATH WBCLKIin WBDATO4out (944:3217:5491)(944:3217:5491)) + (IOPATH WBCLKIin WBDATO5out (917:3672:6428)(917:3672:6428)) + (IOPATH WBCLKIin WBDATO6out (926:3191:5457)(926:3191:5457)) + (IOPATH WBCLKIin WBDATO7out (939:3201:5464)(939:3201:5464)) + (IOPATH WBCLKIin WBACKOout (903:1623:2343)(903:1623:2343)) + ) + ) + (TIMINGCHECK + (SETUPHOLD WBRSTIin (posedge WBCLKIin) (3138:3170:3203)(-3138:-1966:-794)) + (SETUPHOLD WBCYCIin (posedge WBCLKIin) (2616:2649:2682)(-2616:-1558:-501)) + (SETUPHOLD WBSTBIin (posedge WBCLKIin) (2605:2637:2670)(-2605:-1494:-384)) + (SETUPHOLD WBWEIin (posedge WBCLKIin) (1409:1442:1475)(-1409:-837:-266)) + (SETUPHOLD WBADRI0in (posedge WBCLKIin) (2058:2123:2188)(-2058:-1191:-324)) + (SETUPHOLD WBADRI1in (posedge WBCLKIin) (2068:2104:2140)(-2068:-1234:-401)) + (SETUPHOLD WBADRI2in (posedge WBCLKIin) (1928:1993:2058)(-1928:-1110:-292)) + (SETUPHOLD WBADRI3in (posedge WBCLKIin) (2167:2196:2226)(-2167:-1264:-361)) + (SETUPHOLD WBADRI4in (posedge WBCLKIin) (2072:2101:2130)(-2072:-1198:-324)) + (SETUPHOLD WBADRI5in (posedge WBCLKIin) (1611:1640:1670)(-1611:-950:-289)) + (SETUPHOLD WBADRI6in (posedge WBCLKIin) (2532:2564:2597)(-2532:-1380:-229)) + (SETUPHOLD WBADRI7in (posedge WBCLKIin) (2519:2551:2584)(-2519:-1377:-235)) + (SETUPHOLD WBDATI0in (posedge WBCLKIin) (1057:1262:1467)(-1037:-712:-388)) + (SETUPHOLD WBDATI1in (posedge WBCLKIin) (1114:1338:1563)(-1108:-785:-462)) + (SETUPHOLD WBDATI2in (posedge WBCLKIin) (916:1076:1237)(-912:-636:-360)) + (SETUPHOLD WBDATI3in (posedge WBCLKIin) (1145:1359:1573)(-1115:-782:-449)) + (SETUPHOLD WBDATI4in (posedge WBCLKIin) (1192:1400:1609)(-1176:-820:-464)) + (SETUPHOLD WBDATI5in (posedge WBCLKIin) (1027:1222:1418)(-1000:-706:-413)) + (SETUPHOLD WBDATI6in (posedge WBCLKIin) (1034:1248:1463)(-1034:-756:-479)) + (SETUPHOLD WBDATI7in (posedge WBCLKIin) (528:614:701)(-528:-398:-268)) + ) + (TIMINGCHECK + (WIDTH (posedge WBCLKIin) (4887:4887:4887)) + (WIDTH (negedge WBCLKIin) (4887:4887:4887)) + ) + ) + (CELL + (CELLTYPE "RAM2E") + (INSTANCE ) + (DELAY + (ABSOLUTE + (INTERCONNECT SLICE_0/Q1 SLICE_0/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_0/Q1 SLICE_39/D1 (805:898:992)(805:898:992)) + (INTERCONNECT SLICE_0/Q1 SLICE_52/C1 (816:964:1113)(816:964:1113)) + (INTERCONNECT SLICE_0/Q1 SLICE_75/C1 (1180:1360:1540)(1180:1360:1540)) + (INTERCONNECT SLICE_0/Q1 SLICE_119/C0 (805:952:1100)(805:952:1100)) + (INTERCONNECT SLICE_0/F1 SLICE_0/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT C14M_I/PADDI SLICE_0/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_1/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_2/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_2/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_3/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_3/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_4/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_4/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_5/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_5/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_6/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_6/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_7/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_7/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_8/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_9/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_10/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_11/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_12/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_13/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_14/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_15/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_16/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_17/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_18/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_19/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_20/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_21/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_22/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_23/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_23/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_24/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_24/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_25/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_25/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_26/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_26/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_27/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_27/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_28/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_28/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_29/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_29/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_30/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_30/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_31/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_32/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_33/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_33/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_34/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_35/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_36/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_37/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_38/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_39/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_40/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_41/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_42/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_43/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_44/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_45/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI SLICE_46/CLK (2666:2868:3070)(2666:2868:3070)) + (INTERCONNECT C14M_I/PADDI DQMH_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI DQML_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI RA\[11\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI RA\[10\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI RA\[9\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI RA\[8\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI RA\[7\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI RA\[6\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI RA\[5\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI RA\[4\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI RA\[2\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI RA\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI BA\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI BA\[0\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI nRWE_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI nCAS_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI nRAS_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI nCS_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI CKE_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Vout\[7\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Vout\[6\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Vout\[5\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Vout\[4\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Vout\[3\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Vout\[2\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Vout\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Vout\[0\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Dout\[7\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Dout\[6\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Dout\[5\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Dout\[4\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Dout\[3\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Dout\[2\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Dout\[1\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI Dout\[0\]_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI PHI1_MGIOL/CLK (2813:3028:3243)(2813:3028:3243)) + (INTERCONNECT C14M_I/PADDI + ufmefb\/EFBInst_0/ufmefb\/EFBInst_0_EFB/INST20/WBCLKIin (2813:3028:3243) + (2813:3028:3243)) + (INTERCONNECT SLICE_0/FCO SLICE_8/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_1/Q0 SLICE_1/A0 (483:579:675)(483:579:675)) + (INTERCONNECT SLICE_1/Q0 SLICE_45/B0 (1154:1318:1482)(1154:1318:1482)) + (INTERCONNECT SLICE_1/Q0 SLICE_51/A0 (1090:1255:1421)(1090:1255:1421)) + (INTERCONNECT SLICE_1/Q0 SLICE_53/C1 (1293:1476:1659)(1293:1476:1659)) + (INTERCONNECT SLICE_1/Q0 SLICE_56/A1 (1824:2054:2284)(1824:2054:2284)) + (INTERCONNECT SLICE_1/Q0 SLICE_72/B0 (769:896:1023)(769:896:1023)) + (INTERCONNECT SLICE_1/Q0 SLICE_73/A0 (1824:2054:2284)(1824:2054:2284)) + (INTERCONNECT SLICE_1/Q0 SLICE_75/A0 (763:893:1024)(763:893:1024)) + (INTERCONNECT SLICE_1/Q0 SLICE_83/D1 (1244:1375:1507)(1244:1375:1507)) + (INTERCONNECT SLICE_1/Q0 SLICE_86/D1 (1609:1772:1935)(1609:1772:1935)) + (INTERCONNECT SLICE_1/Q0 SLICE_103/C0 (928:1079:1231)(928:1079:1231)) + (INTERCONNECT SLICE_1/F0 SLICE_1/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/FCO SLICE_1/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/Q1 SLICE_2/A1 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_2/Q1 SLICE_37/B1 (1059:1223:1388)(1059:1223:1388)) + (INTERCONNECT SLICE_2/Q1 SLICE_37/B0 (1059:1223:1388)(1059:1223:1388)) + (INTERCONNECT SLICE_2/Q1 SLICE_38/C0 (1155:1341:1528)(1155:1341:1528)) + (INTERCONNECT SLICE_2/Q1 SLICE_39/C1 (557:674:792)(557:674:792)) + (INTERCONNECT SLICE_2/Q1 SLICE_44/D0 (546:608:671)(546:608:671)) + (INTERCONNECT SLICE_2/Q1 SLICE_45/C1 (813:963:1113)(813:963:1113)) + (INTERCONNECT SLICE_2/Q1 SLICE_45/C0 (813:963:1113)(813:963:1113)) + (INTERCONNECT SLICE_2/Q1 SLICE_56/D1 (1192:1321:1450)(1192:1321:1450)) + (INTERCONNECT SLICE_2/Q1 SLICE_66/B1 (1059:1223:1388)(1059:1223:1388)) + (INTERCONNECT SLICE_2/Q1 SLICE_73/C0 (1203:1387:1571)(1203:1387:1571)) + (INTERCONNECT SLICE_2/Q1 SLICE_86/B1 (1761:1993:2225)(1761:1993:2225)) + (INTERCONNECT SLICE_2/Q1 SLICE_97/D0 (910:1004:1098)(910:1004:1098)) + (INTERCONNECT SLICE_2/Q0 SLICE_2/A0 (483:579:675)(483:579:675)) + (INTERCONNECT SLICE_2/Q0 SLICE_35/A0 (1202:1373:1544)(1202:1373:1544)) + (INTERCONNECT SLICE_2/Q0 SLICE_44/A1 (1074:1238:1402)(1074:1238:1402)) + (INTERCONNECT SLICE_2/Q0 SLICE_46/D0 (543:607:671)(543:607:671)) + (INTERCONNECT SLICE_2/Q0 SLICE_56/A0 (1217:1389:1562)(1217:1389:1562)) + (INTERCONNECT SLICE_2/Q0 SLICE_60/A0 (1566:1768:1971)(1566:1768:1971)) + (INTERCONNECT SLICE_2/Q0 SLICE_61/D1 (1007:1114:1221)(1007:1114:1221)) + (INTERCONNECT SLICE_2/Q0 SLICE_65/A0 (1202:1373:1544)(1202:1373:1544)) + (INTERCONNECT SLICE_2/Q0 SLICE_66/D0 (543:607:671)(543:607:671)) + (INTERCONNECT SLICE_2/Q0 SLICE_73/D0 (1007:1114:1221)(1007:1114:1221)) + (INTERCONNECT SLICE_2/Q0 SLICE_74/A0 (1202:1373:1544)(1202:1373:1544)) + (INTERCONNECT SLICE_2/Q0 SLICE_88/A1 (1587:1791:1996)(1587:1791:1996)) + (INTERCONNECT SLICE_2/Q0 SLICE_90/A1 (2366:2646:2926)(2366:2646:2926)) + (INTERCONNECT SLICE_2/Q0 SLICE_92/C1 (1018:1180:1342)(1018:1180:1342)) + (INTERCONNECT SLICE_2/Q0 SLICE_97/A0 (1581:1785:1989)(1581:1785:1989)) + (INTERCONNECT SLICE_2/Q0 SLICE_108/C0 (1715:1944:2173)(1715:1944:2173)) + (INTERCONNECT SLICE_2/Q0 SLICE_116/A0 (2366:2646:2926)(2366:2646:2926)) + (INTERCONNECT SLICE_2/F1 SLICE_2/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_2/F0 SLICE_2/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/FCO SLICE_2/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/Q1 SLICE_3/A1 (481:575:669)(481:575:669)) + (INTERCONNECT SLICE_3/Q1 SLICE_44/C1 (552:669:786)(552:669:786)) + (INTERCONNECT SLICE_3/Q1 SLICE_46/A1 (776:906:1036)(776:906:1036)) + (INTERCONNECT SLICE_3/Q1 SLICE_56/C0 (1280:1460:1640)(1280:1460:1640)) + (INTERCONNECT SLICE_3/Q1 SLICE_58/D1 (1351:1491:1632)(1351:1491:1632)) + (INTERCONNECT SLICE_3/Q1 SLICE_60/C0 (972:1126:1280)(972:1126:1280)) + (INTERCONNECT SLICE_3/Q1 SLICE_61/B1 (1583:1783:1983)(1583:1783:1983)) + (INTERCONNECT SLICE_3/Q1 SLICE_62/C1 (972:1126:1280)(972:1126:1280)) + (INTERCONNECT SLICE_3/Q1 SLICE_64/A0 (776:906:1036)(776:906:1036)) + (INTERCONNECT SLICE_3/Q1 SLICE_65/C0 (972:1126:1280)(972:1126:1280)) + (INTERCONNECT SLICE_3/Q1 SLICE_66/A0 (776:906:1036)(776:906:1036)) + (INTERCONNECT SLICE_3/Q1 SLICE_70/D1 (1351:1491:1632)(1351:1491:1632)) + (INTERCONNECT SLICE_3/Q1 SLICE_73/B1 (1583:1783:1983)(1583:1783:1983)) + (INTERCONNECT SLICE_3/Q1 SLICE_74/C0 (972:1126:1280)(972:1126:1280)) + (INTERCONNECT SLICE_3/Q1 SLICE_84/C1 (972:1126:1280)(972:1126:1280)) + (INTERCONNECT SLICE_3/Q1 SLICE_88/D1 (1336:1467:1599)(1336:1467:1599)) + (INTERCONNECT SLICE_3/Q1 SLICE_90/A0 (1551:1748:1946)(1551:1748:1946)) + (INTERCONNECT SLICE_3/Q1 SLICE_92/A1 (1551:1748:1946)(1551:1748:1946)) + (INTERCONNECT SLICE_3/Q1 SLICE_95/A1 (776:906:1036)(776:906:1036)) + (INTERCONNECT SLICE_3/Q1 SLICE_97/A1 (1140:1301:1463)(1140:1301:1463)) + (INTERCONNECT SLICE_3/Q1 SLICE_108/B1 (1578:1777:1977)(1578:1777:1977)) + (INTERCONNECT SLICE_3/Q1 SLICE_108/B0 (1578:1777:1977)(1578:1777:1977)) + (INTERCONNECT SLICE_3/Q0 SLICE_3/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_3/Q0 SLICE_44/D1 (866:961:1056)(866:961:1056)) + (INTERCONNECT SLICE_3/Q0 SLICE_50/A1 (1498:1688:1879)(1498:1688:1879)) + (INTERCONNECT SLICE_3/Q0 SLICE_58/A0 (2248:2503:2759)(2248:2503:2759)) + (INTERCONNECT SLICE_3/Q0 SLICE_61/D0 (1673:1831:1990)(1673:1831:1990)) + (INTERCONNECT SLICE_3/Q0 SLICE_62/A1 (1883:2107:2331)(1883:2107:2331)) + (INTERCONNECT SLICE_3/Q0 SLICE_64/A1 (2253:2509:2765)(2253:2509:2765)) + (INTERCONNECT SLICE_3/Q0 SLICE_65/C1 (1674:1886:2099)(1674:1886:2099)) + (INTERCONNECT SLICE_3/Q0 SLICE_66/C0 (2381:2661:2942)(2381:2661:2942)) + (INTERCONNECT SLICE_3/Q0 SLICE_68/B0 (2655:2945:3236)(2655:2945:3236)) + (INTERCONNECT SLICE_3/Q0 SLICE_70/A0 (2248:2503:2759)(2248:2503:2759)) + (INTERCONNECT SLICE_3/Q0 SLICE_73/A1 (1498:1688:1879)(1498:1688:1879)) + (INTERCONNECT SLICE_3/Q0 SLICE_74/C1 (2001:2248:2496)(2001:2248:2496)) + (INTERCONNECT SLICE_3/Q0 SLICE_89/A1 (1498:1688:1879)(1498:1688:1879)) + (INTERCONNECT SLICE_3/Q0 SLICE_90/C1 (1684:1897:2111)(1684:1897:2111)) + (INTERCONNECT SLICE_3/Q0 SLICE_92/D1 (2458:2692:2927)(2458:2692:2927)) + (INTERCONNECT SLICE_3/Q0 SLICE_104/D1 (2413:2635:2858)(2413:2635:2858)) + (INTERCONNECT SLICE_3/Q0 SLICE_104/D0 (2413:2635:2858)(2413:2635:2858)) + (INTERCONNECT SLICE_3/Q0 SLICE_116/D0 (2785:3054:3324)(2785:3054:3324)) + (INTERCONNECT SLICE_3/F1 SLICE_3/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_3/F0 SLICE_3/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/FCO SLICE_3/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/Q1 SLICE_4/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_4/Q1 SLICE_46/B1 (796:925:1055)(796:925:1055)) + (INTERCONNECT SLICE_4/Q1 SLICE_50/C1 (1345:1529:1714)(1345:1529:1714)) + (INTERCONNECT SLICE_4/Q1 SLICE_58/D0 (1329:1458:1587)(1329:1458:1587)) + (INTERCONNECT SLICE_4/Q1 SLICE_60/D0 (954:1050:1147)(954:1050:1147)) + (INTERCONNECT SLICE_4/Q1 SLICE_61/A0 (1534:1728:1922)(1534:1728:1922)) + (INTERCONNECT SLICE_4/Q1 SLICE_62/D0 (954:1050:1147)(954:1050:1147)) + (INTERCONNECT SLICE_4/Q1 SLICE_64/B0 (796:925:1055)(796:925:1055)) + (INTERCONNECT SLICE_4/Q1 SLICE_65/D0 (954:1050:1147)(954:1050:1147)) + (INTERCONNECT SLICE_4/Q1 SLICE_68/C0 (1710:1926:2142)(1710:1926:2142)) + (INTERCONNECT SLICE_4/Q1 SLICE_70/D0 (1329:1458:1587)(1329:1458:1587)) + (INTERCONNECT SLICE_4/Q1 SLICE_74/D0 (954:1050:1147)(954:1050:1147)) + (INTERCONNECT SLICE_4/Q1 SLICE_84/D1 (954:1050:1147)(954:1050:1147)) + (INTERCONNECT SLICE_4/Q1 SLICE_89/D1 (1334:1463:1593)(1334:1463:1593)) + (INTERCONNECT SLICE_4/Q1 SLICE_90/D1 (1324:1452:1581)(1324:1452:1581)) + (INTERCONNECT SLICE_4/Q1 SLICE_95/B1 (796:925:1055)(796:925:1055)) + (INTERCONNECT SLICE_4/Q1 SLICE_97/D1 (918:1011:1104)(918:1011:1104)) + (INTERCONNECT SLICE_4/Q1 SLICE_104/A0 (1909:2135:2362)(1909:2135:2362)) + (INTERCONNECT SLICE_4/Q1 SLICE_108/A1 (1544:1739:1934)(1544:1739:1934)) + (INTERCONNECT SLICE_4/Q1 SLICE_108/A0 (1544:1739:1934)(1544:1739:1934)) + (INTERCONNECT SLICE_4/Q0 SLICE_4/A0 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_4/Q0 SLICE_46/C1 (892:1043:1195)(892:1043:1195)) + (INTERCONNECT SLICE_4/Q0 SLICE_50/B1 (1556:1751:1947)(1556:1751:1947)) + (INTERCONNECT SLICE_4/Q0 SLICE_50/B0 (1556:1751:1947)(1556:1751:1947)) + (INTERCONNECT SLICE_4/Q0 SLICE_58/C0 (1355:1549:1743)(1355:1549:1743)) + (INTERCONNECT SLICE_4/Q0 SLICE_61/B0 (1546:1740:1935)(1546:1740:1935)) + (INTERCONNECT SLICE_4/Q0 SLICE_62/B0 (1171:1333:1495)(1171:1333:1495)) + (INTERCONNECT SLICE_4/Q0 SLICE_64/B1 (796:925:1055)(796:925:1055)) + (INTERCONNECT SLICE_4/Q0 SLICE_65/B1 (1171:1333:1495)(1171:1333:1495)) + (INTERCONNECT SLICE_4/Q0 SLICE_68/D0 (1349:1488:1628)(1349:1488:1628)) + (INTERCONNECT SLICE_4/Q0 SLICE_70/C0 (1355:1549:1743)(1355:1549:1743)) + (INTERCONNECT SLICE_4/Q0 SLICE_74/B1 (1171:1333:1495)(1171:1333:1495)) + (INTERCONNECT SLICE_4/Q0 SLICE_89/B0 (1556:1751:1947)(1556:1751:1947)) + (INTERCONNECT SLICE_4/Q0 SLICE_90/B1 (1546:1740:1935)(1546:1740:1935)) + (INTERCONNECT SLICE_4/Q0 SLICE_104/B1 (1591:1798:2006)(1591:1798:2006)) + (INTERCONNECT SLICE_4/Q0 SLICE_104/B0 (1591:1798:2006)(1591:1798:2006)) + (INTERCONNECT SLICE_4/Q0 SLICE_105/B1 (1546:1740:1935)(1546:1740:1935)) + (INTERCONNECT SLICE_4/Q0 SLICE_105/B0 (1546:1740:1935)(1546:1740:1935)) + (INTERCONNECT SLICE_4/Q0 SLICE_108/C1 (1652:1869:2087)(1652:1869:2087)) + (INTERCONNECT SLICE_4/Q0 SLICE_116/B1 (1556:1751:1947)(1556:1751:1947)) + (INTERCONNECT SLICE_4/Q0 SLICE_116/B0 (1556:1751:1947)(1556:1751:1947)) + (INTERCONNECT SLICE_4/F1 SLICE_4/DI1 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_4/F0 SLICE_4/DI0 (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/FCO SLICE_4/FCI (0:0:0)(0:0:0)) + (INTERCONNECT SLICE_5/Q1 SLICE_5/A1 (479:571:663)(479:571:663)) + (INTERCONNECT SLICE_5/Q1 SLICE_46/D1 (871:966:1062)(871:966:1062)) + (INTERCONNECT SLICE_5/Q1 SLICE_50/D1 (1641:1803:1966)(1641:1803:1966)) + (INTERCONNECT SLICE_5/Q1 SLICE_58/B0 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CKE_MGIOL/OPOS (1891:2056:2222)(1891:2056:2222)) + (INTERCONNECT SLICE_72/F0 SLICE_52/D1 (800:891:982)(800:891:982)) + (INTERCONNECT SLICE_72/F0 SLICE_52/D0 (800:891:982)(800:891:982)) + (INTERCONNECT SLICE_72/F0 SLICE_72/C1 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_72/F0 SLICE_76/C0 (546:664:783)(546:664:783)) + (INTERCONNECT SLICE_52/F1 SLICE_52/B0 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_57/F1 SLICE_52/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_53/F1 SLICE_53/C0 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_53/F1 SLICE_110/D0 (860:955:1051)(860:955:1051)) + (INTERCONNECT SLICE_54/F1 SLICE_54/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_118/F0 SLICE_54/B0 (767:891:1015)(767:891:1015)) + (INTERCONNECT SLICE_118/F0 SLICE_93/D1 (525:581:637)(525:581:637)) + (INTERCONNECT SLICE_54/F0 SLICE_81/B0 (1099:1259:1420)(1099:1259:1420)) + (INTERCONNECT SLICE_55/F0 SLICE_55/D1 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_55/F0 SLICE_71/C1 (550:666:782)(550:666:782)) + (INTERCONNECT SLICE_55/F0 SLICE_78/A1 (749:875:1002)(749:875:1002)) + (INTERCONNECT SLICE_63/F0 SLICE_55/C1 (536:650:764)(536:650:764)) + (INTERCONNECT SLICE_63/F0 SLICE_63/C1 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_63/F0 SLICE_76/A0 (735:859:984)(735:859:984)) + (INTERCONNECT SLICE_55/F1 SLICE_83/D0 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_56/F1 SLICE_56/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_56/F1 SLICE_85/B1 (772:902:1032)(772:902:1032)) + (INTERCONNECT SLICE_56/F1 SLICE_88/C0 (1249:1437:1625)(1249:1437:1625)) + (INTERCONNECT SLICE_56/F1 SLICE_92/D0 (525:584:643)(525:584:643)) + (INTERCONNECT SLICE_56/F1 SLICE_109/B1 (1480:1681:1882)(1480:1681:1882)) + (INTERCONNECT SLICE_56/F1 SLICE_109/B0 (1480:1681:1882)(1480:1681:1882)) + (INTERCONNECT SLICE_58/F0 SLICE_58/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_73/F0 SLICE_58/B1 (1166:1328:1491)(1166:1328:1491)) + (INTERCONNECT SLICE_73/F0 SLICE_68/B1 (1161:1323:1485)(1161:1323:1485)) + (INTERCONNECT SLICE_73/F0 SLICE_70/B1 (1166:1328:1491)(1166:1328:1491)) + (INTERCONNECT SLICE_73/F0 SLICE_73/C1 (280:362:445)(280:362:445)) + (INTERCONNECT SLICE_73/F0 SLICE_84/B1 (1166:1328:1491)(1166:1328:1491)) + (INTERCONNECT SLICE_73/F0 SLICE_89/D0 (1610:1770:1931)(1610:1770:1931)) + (INTERCONNECT SLICE_73/F0 SLICE_114/B1 (1118:1283:1448)(1118:1283:1448)) + (INTERCONNECT SLICE_73/F0 SLICE_114/D0 (549:611:673)(549:611:673)) + (INTERCONNECT SLICE_70/F0 SLICE_58/A1 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_70/F0 SLICE_70/A1 (479:572:665)(479:572:665)) + (INTERCONNECT SLICE_59/F0 SLICE_59/A1 (476:566:656)(476:566:656)) + (INTERCONNECT SLICE_59/F1 DQML_MGIOL/OPOS (1772:1946:2120)(1772:1946:2120)) + (INTERCONNECT SLICE_60/F0 SLICE_60/D1 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_88/F1 SLICE_60/C1 (807:955:1104)(807:955:1104)) + (INTERCONNECT SLICE_88/F1 SLICE_88/A0 (737:864:992)(737:864:992)) + (INTERCONNECT SLICE_88/F1 SLICE_105/D1 (273:306:340)(273:306:340)) + (INTERCONNECT SLICE_88/F1 SLICE_105/D0 (527:589:651)(527:589:651)) + (INTERCONNECT SLICE_64/F1 SLICE_60/B1 (515:616:718)(515:616:718)) + (INTERCONNECT SLICE_64/F1 SLICE_64/D0 (527:589:651)(527:589:651)) + (INTERCONNECT SLICE_64/F1 SLICE_95/C1 (538:655:772)(538:655:772)) + (INTERCONNECT SLICE_64/F1 SLICE_97/C0 (548:669:791)(548:669:791)) + (INTERCONNECT SLICE_61/F0 SLICE_61/C1 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_61/F0 SLICE_88/B0 (1211:1381:1552)(1211:1381:1552)) + (INTERCONNECT SLICE_61/F0 SLICE_114/C1 (536:650:764)(536:650:764)) + (INTERCONNECT SLICE_61/F1 SLICE_109/A0 (1067:1225:1383)(1067:1225:1383)) + (INTERCONNECT SLICE_62/F0 SLICE_62/D1 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_64/F0 SLICE_114/B0 (1031:1183:1336)(1031:1183:1336)) + (INTERCONNECT SLICE_65/F1 SLICE_65/B0 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_65/F1 SLICE_84/A1 (733:854:976)(733:854:976)) + (INTERCONNECT SLICE_65/F0 SLICE_109/A1 (740:863:986)(740:863:986)) + (INTERCONNECT SLICE_66/F0 SLICE_95/D0 (266:290:315)(266:290:315)) + (INTERCONNECT SLICE_76/F0 SLICE_69/D1 (975:1072:1170)(975:1072:1170)) + (INTERCONNECT SLICE_76/F0 SLICE_78/A0 (1185:1348:1511)(1185:1348:1511)) + (INTERCONNECT SLICE_76/F0 SLICE_115/C0 (1350:1534:1718)(1350:1534:1718)) + (INTERCONNECT SLICE_69/F0 SLICE_69/C1 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_69/F1 RA\[10\]_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795)) + (INTERCONNECT SLICE_75/F0 SLICE_71/A1 (746:869:993)(746:869:993)) + (INTERCONNECT SLICE_75/F0 SLICE_78/C0 (547:660:773)(547:660:773)) + (INTERCONNECT SLICE_71/F1 SLICE_115/D0 (523:573:623)(523:573:623)) + (INTERCONNECT SLICE_119/F0 SLICE_72/B1 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_116/F1 SLICE_73/D1 (523:579:635)(523:579:635)) + (INTERCONNECT SLICE_116/F1 SLICE_92/B1 (765:889:1013)(765:889:1013)) + (INTERCONNECT SLICE_73/F1 SLICE_85/C0 (534:639:744)(534:639:744)) + (INTERCONNECT SLICE_75/F1 SLICE_75/C0 (282:367:453)(282:367:453)) + (INTERCONNECT SLICE_75/F1 SLICE_76/B0 (513:611:710)(513:611:710)) + (INTERCONNECT SLICE_75/F1 SLICE_83/A0 (745:874:1003)(745:874:1003)) + (INTERCONNECT SLICE_82/F0 SLICE_77/D0 (530:587:645)(530:587:645)) + (INTERCONNECT SLICE_81/F0 SLICE_77/C0 (531:639:747)(531:639:747)) + (INTERCONNECT SLICE_94/F0 SLICE_77/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_78/F1 SLICE_78/D0 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_78/F0 nCAS_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795)) + (INTERCONNECT SLICE_79/F1 SLICE_79/B0 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_83/F0 SLICE_79/A0 (1180:1342:1505)(1180:1342:1505)) + (INTERCONNECT SLICE_83/F0 SLICE_80/A0 (1180:1342:1505)(1180:1342:1505)) + (INTERCONNECT SLICE_79/F0 nCS_MGIOL/OPOS (1408:1550:1693)(1408:1550:1693)) + (INTERCONNECT SLICE_80/F0 nRAS_MGIOL/OPOS (1772:1946:2120)(1772:1946:2120)) + (INTERCONNECT SLICE_81/F1 SLICE_81/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_91/F0 SLICE_82/C0 (534:639:744)(534:639:744)) + (INTERCONNECT SLICE_87/F0 SLICE_82/B0 (765:883:1001)(765:883:1001)) + (INTERCONNECT SLICE_83/F1 SLICE_83/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_112/F1 SLICE_83/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_84/F1 SLICE_84/A0 (730:848:967)(730:848:967)) + (INTERCONNECT SLICE_108/F1 SLICE_85/D1 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_89/F0 SLICE_85/D0 (520:573:626)(520:573:626)) + (INTERCONNECT SLICE_85/F1 SLICE_85/B0 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_92/F0 SLICE_85/A0 (740:863:986)(740:863:986)) + (INTERCONNECT SLICE_105/F1 SLICE_86/A0 (733:848:964)(733:848:964)) + (INTERCONNECT SLICE_98/F0 SLICE_87/C1 (541:653:766)(541:653:766)) + (INTERCONNECT SLICE_87/F1 SLICE_87/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_90/F1 SLICE_90/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_99/F0 SLICE_91/A1 (1067:1225:1383)(1067:1225:1383)) + (INTERCONNECT SLICE_91/F1 SLICE_91/B0 (762:883:1004)(762:883:1004)) + (INTERCONNECT SLICE_92/F1 SLICE_92/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_93/F1 SLICE_93/B0 (508:600:693)(508:600:693)) + (INTERCONNECT SLICE_94/F1 SLICE_94/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_95/F1 SLICE_95/C0 (277:356:436)(277:356:436)) + (INTERCONNECT SLICE_96/F0 RA\[8\]_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795)) + (INTERCONNECT SLICE_97/F1 SLICE_97/B0 (511:606:702)(511:606:702)) + (INTERCONNECT SLICE_97/F1 SLICE_116/C0 (803:945:1088)(803:945:1088)) + (INTERCONNECT SLICE_118/F1 SLICE_98/D0 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_118/F1 SLICE_99/D0 (269:296:324)(269:296:324)) + (INTERCONNECT SLICE_101/F1 BA\[1\]_MGIOL/LSR (1884:2059:2234)(1884:2059:2234)) + (INTERCONNECT SLICE_101/F1 BA\[0\]_MGIOL/LSR (1884:2059:2234)(1884:2059:2234)) + (INTERCONNECT SLICE_102/F0 BA\[0\]_MGIOL/OPOS (1854:2023:2192)(1854:2023:2192)) + (INTERCONNECT SLICE_103/F1 RA\[11\]_MGIOL/OPOS (1891:2056:2222)(1891:2056:2222)) + (INTERCONNECT SLICE_107/F0 BA\[1\]_MGIOL/OPOS (1772:1946:2120)(1772:1946:2120)) + (INTERCONNECT SLICE_110/F1 RA\[9\]_MGIOL/OPOS (1527:1661:1795)(1527:1661:1795)) + (INTERCONNECT Ain\[5\]_I/PADDI SLICE_111/A1 (2376:2598:2820)(2376:2598:2820)) + (INTERCONNECT Ain\[4\]_I/PADDI SLICE_111/A0 (1904:2092:2281)(1904:2092:2281)) + (INTERCONNECT SLICE_111/F0 RA\[4\]_MGIOL/OPOS (1011:1111:1211)(1011:1111:1211)) + (INTERCONNECT SLICE_111/F1 RA\[5\]_MGIOL/OPOS (1081:1188:1296)(1081:1188:1296)) + (INTERCONNECT Ain\[6\]_I/PADDI SLICE_112/C0 (1530:1696:1862)(1530:1696:1862)) + (INTERCONNECT SLICE_112/F0 RA\[6\]_MGIOL/OPOS (1408:1550:1693)(1408:1550:1693)) + (INTERCONNECT Ain\[2\]_I/PADDI SLICE_113/B1 (2262:2486:2711)(2262:2486:2711)) + (INTERCONNECT Ain\[7\]_I/PADDI SLICE_113/B0 (2262:2486:2711)(2262:2486:2711)) + (INTERCONNECT SLICE_113/F0 RA\[7\]_MGIOL/OPOS (1337:1468:1599)(1337:1468:1599)) + (INTERCONNECT SLICE_113/F1 RA\[2\]_MGIOL/OPOS (1483:1616:1750)(1483:1616:1750)) + (INTERCONNECT nWE80_I/PADDI SLICE_115/A1 (2242:2467:2693)(2242:2467:2693)) + (INTERCONNECT nWE80_I/PADDI SLICE_115/A0 (2242:2467:2693)(2242:2467:2693)) + (INTERCONNECT SLICE_115/F0 nRWE_MGIOL/OPOS (1854:2023:2192)(1854:2023:2192)) + (INTERCONNECT SLICE_115/F1 RD\[0\]_I/PADDT (1279:1424:1569)(1279:1424:1569)) + (INTERCONNECT SLICE_115/F1 RD\[7\]_I/PADDT (1057:1170:1284)(1057:1170:1284)) + (INTERCONNECT SLICE_115/F1 RD\[6\]_I/PADDT (1057:1170:1284)(1057:1170:1284)) + (INTERCONNECT SLICE_115/F1 RD\[5\]_I/PADDT (1759:1941:2123)(1759:1941:2123)) + (INTERCONNECT SLICE_115/F1 RD\[4\]_I/PADDT (1759:1941:2123)(1759:1941:2123)) + (INTERCONNECT SLICE_115/F1 RD\[3\]_I/PADDT (688:769:851)(688:769:851)) + (INTERCONNECT SLICE_115/F1 RD\[2\]_I/PADDT (688:769:851)(688:769:851)) + (INTERCONNECT SLICE_115/F1 RD\[1\]_I/PADDT (1279:1424:1569)(1279:1424:1569)) + (INTERCONNECT SLICE_117/F0 LED_I/PADDO (936:1038:1140)(936:1038:1140)) + (INTERCONNECT RD\[0\]_I/PADDI Vout\[0\]_MGIOL/OPOS (2416:2609:2802) + (2416:2609:2802)) + (INTERCONNECT RD\[0\]_I/PADDI Dout\[0\]_MGIOL/OPOS (2416:2609:2802) + (2416:2609:2802)) + (INTERCONNECT DQMH_MGIOL/IOLDO DQMH_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT DQML_MGIOL/IOLDO DQML_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT RD\[7\]_I/PADDI Vout\[7\]_MGIOL/OPOS (2416:2609:2802) + (2416:2609:2802)) + (INTERCONNECT RD\[7\]_I/PADDI Dout\[7\]_MGIOL/OPOS (1970:2136:2303) + (1970:2136:2303)) + (INTERCONNECT RD\[6\]_I/PADDI Vout\[6\]_MGIOL/OPOS (2862:3081:3301) + (2862:3081:3301)) + (INTERCONNECT RD\[6\]_I/PADDI Dout\[6\]_MGIOL/OPOS (2416:2609:2802) + (2416:2609:2802)) + (INTERCONNECT RD\[5\]_I/PADDI Vout\[5\]_MGIOL/OPOS (2416:2609:2802) + (2416:2609:2802)) + (INTERCONNECT RD\[5\]_I/PADDI Dout\[5\]_MGIOL/OPOS (2416:2609:2802) + (2416:2609:2802)) + (INTERCONNECT RD\[4\]_I/PADDI Vout\[4\]_MGIOL/OPOS (2345:2526:2708) + (2345:2526:2708)) + (INTERCONNECT RD\[4\]_I/PADDI Dout\[4\]_MGIOL/OPOS (2345:2526:2708) + (2345:2526:2708)) + (INTERCONNECT RD\[3\]_I/PADDI Vout\[3\]_MGIOL/OPOS (2416:2609:2802) + (2416:2609:2802)) + (INTERCONNECT RD\[3\]_I/PADDI Dout\[3\]_MGIOL/OPOS (2416:2609:2802) + (2416:2609:2802)) + (INTERCONNECT RD\[2\]_I/PADDI Vout\[2\]_MGIOL/OPOS (2264:2449:2635) + (2264:2449:2635)) + (INTERCONNECT RD\[2\]_I/PADDI Dout\[2\]_MGIOL/OPOS (2955:3207:3459) + (2955:3207:3459)) + (INTERCONNECT RD\[1\]_I/PADDI Vout\[1\]_MGIOL/OPOS (2345:2526:2708) + (2345:2526:2708)) + (INTERCONNECT RD\[1\]_I/PADDI Dout\[1\]_MGIOL/OPOS (1899:2054:2209) + (1899:2054:2209)) + (INTERCONNECT RA\[11\]_MGIOL/IOLDO RA\[11\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RA\[10\]_MGIOL/IOLDO RA\[10\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RA\[9\]_MGIOL/IOLDO RA\[9\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RA\[8\]_MGIOL/IOLDO RA\[8\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT RA\[7\]_MGIOL/IOLDO RA\[7\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[6\]_MGIOL/IOLDO RA\[6\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[5\]_MGIOL/IOLDO RA\[5\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[4\]_MGIOL/IOLDO RA\[4\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[2\]_MGIOL/IOLDO RA\[2\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT RA\[1\]_MGIOL/IOLDO RA\[1\]_I/IOLDO (25:77:129)(25:77:129)) + (INTERCONNECT BA\[1\]_MGIOL/IOLDO BA\[1\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT BA\[0\]_MGIOL/IOLDO BA\[0\]_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nRWE_MGIOL/IOLDO nRWE_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nCAS_MGIOL/IOLDO nCAS_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nRAS_MGIOL/IOLDO nRAS_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT nCS_MGIOL/IOLDO nCS_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT CKE_MGIOL/IOLDO CKE_I/IOLDO (9:36:63)(9:36:63)) + (INTERCONNECT Vout\[7\]_MGIOL/IOLDO Vout\[7\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Vout\[6\]_MGIOL/IOLDO Vout\[6\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Vout\[5\]_MGIOL/IOLDO Vout\[5\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Vout\[4\]_MGIOL/IOLDO Vout\[4\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Vout\[3\]_MGIOL/IOLDO Vout\[3\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Vout\[2\]_MGIOL/IOLDO Vout\[2\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Vout\[1\]_MGIOL/IOLDO Vout\[1\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Vout\[0\]_MGIOL/IOLDO Vout\[0\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Dout\[7\]_MGIOL/IOLDO Dout\[7\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT Dout\[6\]_MGIOL/IOLDO Dout\[6\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT Dout\[5\]_MGIOL/IOLDO Dout\[5\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Dout\[4\]_MGIOL/IOLDO Dout\[4\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Dout\[3\]_MGIOL/IOLDO Dout\[3\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT Dout\[2\]_MGIOL/IOLDO Dout\[2\]_I/IOLDO (11:21:32)(11:21:32)) + (INTERCONNECT Dout\[1\]_MGIOL/IOLDO Dout\[1\]_I/IOLDO (30:36:43)(30:36:43)) + (INTERCONNECT Dout\[0\]_MGIOL/IOLDO Dout\[0\]_I/IOLDO (30:36:43)(30:36:43)) + ) + ) + ) +) diff --git a/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo new file mode 100644 index 0000000..1248ac1 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/RAM2E_LCMXO2_640HC_impl1_vo.vo @@ -0,0 +1,6339 @@ + +// Verilog netlist produced by program ldbanno, Version Diamond (64-bit) 3.12.1.454 + +// ldbanno -n Verilog -o RAM2E_LCMXO2_640HC_impl1_vo.vo -w -neg -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml RAM2E_LCMXO2_640HC_impl1.ncd +// Netlist created on Thu Sep 21 05:34:46 2023 +// Netlist written on Thu Sep 21 05:35:15 2023 +// Design is for device LCMXO2-640HC +// Design is for package TQFP100 +// Design is for performance grade 4 + +`timescale 1 ns / 1 ps + +module RAM2E ( C14M, PHI1, LED, nWE, nWE80, nEN80, nC07X, Ain, Din, Dout, nDOE, + Vout, nVOE, CKE, nCS, nRAS, nCAS, nRWE, BA, RA, RD, DQML, DQMH ); + input C14M, PHI1, nWE, nWE80, nEN80, nC07X; + input [7:0] Ain; + input [7:0] Din; + output LED; + output [7:0] Dout; + output nDOE; + output [7:0] Vout; + output nVOE, CKE, nCS, nRAS, nCAS, nRWE; + output [1:0] BA; + output [11:0] RA; + output DQML, DQMH; + inout [7:0] RD; + wire \FS[0] , \FS_s[0] , C14M_c, \FS_cry[0] , \FS[15] , \FS_s[15] , + \FS_cry[14] , \FS[14] , \FS[13] , \FS_s[14] , \FS_s[13] , + \FS_cry[12] , \FS[12] , \FS[11] , \FS_s[12] , \FS_s[11] , + \FS_cry[10] , \FS[10] , \FS[9] , \FS_s[10] , \FS_s[9] , \FS_cry[8] , + \FS[8] , \FS[7] , \FS_s[8] , \FS_s[7] , \FS_cry[6] , \FS[6] , \FS[5] , + \FS_s[6] , \FS_s[5] , \FS_cry[4] , \FS[4] , \FS[3] , \FS_s[4] , + \FS_s[3] , \FS_cry[2] , \FS[2] , \FS[1] , \FS_s[2] , \FS_s[1] , + PHI1_c, PHI1reg, Ready, RWSel, CO0_1, \CmdTout_3[0] , N_576_i, S_1, + \S_RNII9DO1_0[1] , N_461, \CS[0] , \CS[1] , N_511_i, N_504_i, + un1_CS_0_sqmuxa_i, N_637, \CS[2] , N_510_i, \Din_c[0] , \Din_c[2] , + \Din_c[3] , CmdBitbangMXO2_4_u_0_0_a2_0_1, N_643, CmdBitbangMXO2, + CmdBitbangMXO2_4, \Din_c[7] , \Din_c[5] , N_629, CmdExecMXO2, + CmdExecMXO2_4, N_466, \Din_c[1] , \Din_c[4] , N_478, + CmdLEDGet_4_u_0_0_a2_0_2, N_476, CmdLEDGet, CmdLEDGet_4, N_626, N_605, + CmdLEDSet, CmdLEDSet_4, CmdRWMaskSet, CmdRWMaskSet_4, N_401, + CmdSetRWBankFFLED, CmdSetRWBankFFLED_4, N_474, + CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0, CmdSetRWBankFFMXO2, + CmdSetRWBankFFMXO2_4, \CmdTout[1] , \CmdTout[2] , N_556_i, N_555_i, + \S[2] , \S[1] , \S[3] , \S[0] , N_6_i, DOEEN, \Ain_c[1] , + \wb_dato[0] , LEDEN_RNO, \un1_LEDEN_0_sqmuxa_1_i_0[0] , LEDEN, + N_558_i, \Ain_c[3] , \Ain_c[0] , N_552_i, N_127_i, \S_RNII9DO1_1[1] , + \RA_c[0] , \RA_c[3] , N_591, \RWMask[1] , \RWMask[0] , \RWBank_5[1] , + \RWBank_5[0] , LEDEN13, \RWBank[0] , \RWBank[1] , \RWMask[3] , + \RWMask[2] , \RWBank_5[3] , \RWBank_5[2] , \RWBank[2] , \RWBank[3] , + \RWMask[5] , \RWMask[4] , \RWBank_5[5] , \RWBank_5[4] , \RWBank[4] , + \RWBank[5] , \RWMask[7] , \Din_c[6] , \RWMask[6] , \RWBank_5[7] , + \RWBank_5[6] , \RWBank[6] , \RWBank[7] , \wb_dato[1] , N_291_i, + N_292_i, N_88, \wb_dato[3] , \wb_dato[2] , N_289_i, N_290_i, + \wb_dato[5] , \wb_dato[4] , N_287_i, N_288_i, \wb_dato[7] , + \wb_dato[6] , N_285, N_286_i, nEN80_c, nWE_c, nC07X_c, RWSel_2, nCS61, + nDOE_c, N_489, Ready_0_sqmuxa_0_a2_6_a2_4, Ready_0_sqmuxa, N_876_0, + N_572, N_575, wb_reqc_1, \S_s_0_1[0] , N_133_i, \S_s_0[0] , N_129_i, + N_131_i, N_388, wb_adr_7_5_214_0_1, \wb_adr_7_0_4[0] , N_376, N_642, + \wb_adr_RNO[1] , \wb_adr_7[0] , \un1_wb_adr_0_sqmuxa_2_i[0] , + \wb_adr[0] , \wb_adr[1] , N_41_i, N_43_i, \wb_adr[2] , \wb_adr[3] , + N_295, N_294, \wb_adr[4] , \wb_adr[5] , N_39_i, N_296, \wb_adr[6] , + \wb_adr[7] , wb_ack, N_300, N_395, wb_cyc_stb_RNO, N_104, wb_cyc_stb, + N_336, N_627, N_621, \wb_dati_7_0_0[1] , \wb_dati_7_0_a2_1[0] , N_484, + \wb_dati_7[1] , \wb_dati_7[0] , \wb_dati[0] , \wb_dati[1] , + \wb_dati_7_0_2[3] , \wb_dati_7_0_0[3] , \wb_dati_7_0_o2_0[2] , N_345, + \wb_dati_7[3] , \wb_dati_7[2] , \wb_dati[2] , \wb_dati[3] , N_346, + N_349, \wb_dati_7_0_0[4] , \wb_dati_7[5] , \wb_dati_7[4] , + \wb_dati[4] , \wb_dati[5] , \wb_dati_7_0_RNO[7] , N_424, + \wb_dati_7_0_0[7] , N_422, \wb_dati_7_0_1[6] , \wb_dati_7[7] , + \wb_dati_7[6] , \wb_dati[6] , \wb_dati[7] , N_397, wb_reqc_i, + wb_adr_0_sqmuxa_i, wb_req, wb_rst8, \S_RNII9DO1[1] , wb_rst, N_586, + N_584, N_475, wb_we_7_iv_0_0_0_1, wb_we_RNO, + \un1_wb_cyc_stb_0_sqmuxa_1_i[0] , wb_we, N_255, N_358_i, N_254, Vout3, + N_635, nCAS_s_i_tz_0, un1_CS_0_sqmuxa_0_0_a2_1_4, N_327, + un1_CS_0_sqmuxa_0_0_0, \wb_dati_7_0_a2_0_1[7] , N_579, + CKE_6_iv_i_a2_0, CKE_6_iv_i_0_1, CKE_6_iv_i_0, N_449, N_365, N_364, + \un1_wb_adr_0_sqmuxa_2_1[0] , N_623, N_616, N_279, N_633, N_264, + N_570, N_452, \wb_dati_7_0_a2_2_1[3] , N_455, N_644, DQML_s_i_a2_0, + N_28_i, wb_adr_7_5_214_a2_2_0, N_569, N_577, N_634, + \wb_dati_7_0_a2_2_0[1] , N_265_i, \un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] , + \wb_dati_7_0_a2_0[6] , \wb_dati_7_0_a2_4_0[7] , N_393, nCAS_0_sqmuxa, + N_639, \RA_42[10] , N_640, un1_nCS61_1_i, Ready_0_sqmuxa_0_a2_6_a2_2, + N_562, N_377, N_628, un1_CS_0_sqmuxa_0_0_3, un1_CS_0_sqmuxa_0_0_2, + un1_CS_0_sqmuxa_0_0_a2_3_2, N_567, N_561_i, nCS_6_u_i_0, N_559_1, + N_559_i, nRAS_2_iv_i, un1_CS_0_sqmuxa_0_0_a2_1, N_328, N_330, + nCS_6_u_i_a2_1, N_429, N_351, \wb_adr_7_0_a2_5_0[0] , N_378, + \wb_adr_7_0_1[0] , \wb_adr_7_0_0[0] , + \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] , un1_CS_0_sqmuxa_0_0_a2_4_2, + un1_CS_0_sqmuxa_0_0_a2_4_4, N_565, un1_CS_0_sqmuxa_0_0_a2_2_2, + un1_CS_0_sqmuxa_0_0_a2_2_4, \wb_adr_7_0_a2_0[0] , + un1_CS_0_sqmuxa_0_0_a2_1_2, un1_CS_0_sqmuxa_0_0_a2_3_0, N_394, N_49_i, + N_456, N_477, N_566_i, \BA_4[0] , \RA_42[11] , \BA_4[1] , N_59_i, + \Ain_c[5] , \Ain_c[4] , N_551_i, \RA_42_3_0[5] , \Ain_c[6] , N_550_i, + \Ain_c[2] , \Ain_c[7] , N_549_i, N_553_i, nWE80_c, nRWE_r_0, RDOE_i, + LED_c, \RD_in[0] , DQMH_c, DQML_c, \RD_in[7] , \RD_in[6] , \RD_in[5] , + \RD_in[4] , \RD_in[3] , \RD_in[2] , \RD_in[1] , \RA_c[11] , + \RA_c[10] , \RA_c[9] , \RA_c[8] , \RA_c[7] , \RA_c[6] , \RA_c[5] , + \RA_c[4] , \RA_c[2] , \RA_c[1] , \BA_c[1] , \BA_c[0] , nRWE_c, nCAS_c, + nRAS_c, nCS_c, CKE_c, \Vout_c[7] , \Vout_c[6] , \Vout_c[5] , + \Vout_c[4] , \Vout_c[3] , \Vout_c[2] , \Vout_c[1] , \Vout_c[0] , + \Dout_c[7] , \Dout_c[6] , \Dout_c[5] , \Dout_c[4] , \Dout_c[3] , + \Dout_c[2] , \Dout_c[1] , \Dout_c[0] , VCCI; + + SLICE_0 SLICE_0( .A1(\FS[0] ), .DI1(\FS_s[0] ), .CLK(C14M_c), .F1(\FS_s[0] ), + .Q1(\FS[0] ), .FCO(\FS_cry[0] )); + SLICE_1 SLICE_1( .A0(\FS[15] ), .DI0(\FS_s[15] ), .CLK(C14M_c), + .FCI(\FS_cry[14] ), .F0(\FS_s[15] ), .Q0(\FS[15] )); + SLICE_2 SLICE_2( .A1(\FS[14] ), .A0(\FS[13] ), .DI1(\FS_s[14] ), + .DI0(\FS_s[13] ), .CLK(C14M_c), .FCI(\FS_cry[12] ), .F0(\FS_s[13] ), + .Q0(\FS[13] ), .F1(\FS_s[14] ), .Q1(\FS[14] ), .FCO(\FS_cry[14] )); + SLICE_3 SLICE_3( .A1(\FS[12] ), .A0(\FS[11] ), .DI1(\FS_s[12] ), + .DI0(\FS_s[11] ), .CLK(C14M_c), .FCI(\FS_cry[10] ), .F0(\FS_s[11] ), + .Q0(\FS[11] ), .F1(\FS_s[12] ), .Q1(\FS[12] ), .FCO(\FS_cry[12] )); + SLICE_4 SLICE_4( .A1(\FS[10] ), .A0(\FS[9] ), .DI1(\FS_s[10] ), + .DI0(\FS_s[9] ), .CLK(C14M_c), .FCI(\FS_cry[8] ), .F0(\FS_s[9] ), + .Q0(\FS[9] ), .F1(\FS_s[10] ), .Q1(\FS[10] ), .FCO(\FS_cry[10] )); + SLICE_5 SLICE_5( .A1(\FS[8] ), .A0(\FS[7] ), .DI1(\FS_s[8] ), + .DI0(\FS_s[7] ), .CLK(C14M_c), .FCI(\FS_cry[6] ), .F0(\FS_s[7] ), + .Q0(\FS[7] ), .F1(\FS_s[8] ), .Q1(\FS[8] ), .FCO(\FS_cry[8] )); + SLICE_6 SLICE_6( .A1(\FS[6] ), .A0(\FS[5] ), .DI1(\FS_s[6] ), + .DI0(\FS_s[5] ), .CLK(C14M_c), .FCI(\FS_cry[4] ), .F0(\FS_s[5] ), + .Q0(\FS[5] ), .F1(\FS_s[6] ), .Q1(\FS[6] ), .FCO(\FS_cry[6] )); + SLICE_7 SLICE_7( .A1(\FS[4] ), .A0(\FS[3] ), .DI1(\FS_s[4] ), + .DI0(\FS_s[3] ), .CLK(C14M_c), .FCI(\FS_cry[2] ), .F0(\FS_s[3] ), + .Q0(\FS[3] ), .F1(\FS_s[4] ), .Q1(\FS[4] ), .FCO(\FS_cry[4] )); + SLICE_8 SLICE_8( .A1(\FS[2] ), .A0(\FS[1] ), .DI1(\FS_s[2] ), + .DI0(\FS_s[1] ), .CLK(C14M_c), .FCI(\FS_cry[0] ), .F0(\FS_s[1] ), + .Q0(\FS[1] ), .F1(\FS_s[2] ), .Q1(\FS[2] ), .FCO(\FS_cry[2] )); + SLICE_9 SLICE_9( .C1(PHI1_c), .B1(PHI1reg), .A1(Ready), .D0(RWSel), + .A0(CO0_1), .DI0(\CmdTout_3[0] ), .CE(N_576_i), .CLK(C14M_c), + .F0(\CmdTout_3[0] ), .Q0(CO0_1), .F1(S_1)); + SLICE_10 SLICE_10( .D1(\S_RNII9DO1_0[1] ), .C1(N_461), .B1(\CS[0] ), + .A1(\CS[1] ), .D0(\S_RNII9DO1_0[1] ), .C0(N_461), .A0(\CS[0] ), + .DI1(N_511_i), .DI0(N_504_i), .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), + .F0(N_504_i), .Q0(\CS[0] ), .F1(N_511_i), .Q1(\CS[1] )); + SLICE_11 SLICE_11( .D1(\CS[0] ), .C1(N_461), .B1(\S_RNII9DO1_0[1] ), + .C0(N_637), .B0(\CS[1] ), .A0(\CS[2] ), .DI0(N_510_i), + .LSR(un1_CS_0_sqmuxa_i), .CLK(C14M_c), .F0(N_510_i), .Q0(\CS[2] ), + .F1(N_637)); + SLICE_12 SLICE_12( .D1(\Din_c[0] ), .B1(\Din_c[2] ), .A1(\Din_c[3] ), + .D0(RWSel), .C0(CmdBitbangMXO2_4_u_0_0_a2_0_1), .B0(N_643), + .A0(CmdBitbangMXO2), .DI0(CmdBitbangMXO2_4), .CE(N_576_i), .CLK(C14M_c), + .F0(CmdBitbangMXO2_4), .Q0(CmdBitbangMXO2), + .F1(CmdBitbangMXO2_4_u_0_0_a2_0_1)); + SLICE_13 SLICE_13( .D1(RWSel), .C1(\Din_c[7] ), .A1(\Din_c[5] ), .D0(N_643), + .C0(RWSel), .B0(N_629), .A0(CmdExecMXO2), .DI0(CmdExecMXO2_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdExecMXO2_4), .Q0(CmdExecMXO2), + .F1(N_466)); + SLICE_14 SLICE_14( .D1(\Din_c[0] ), .C1(\Din_c[1] ), .B1(\Din_c[4] ), + .A1(N_478), .D0(CmdLEDGet_4_u_0_0_a2_0_2), .C0(N_476), .B0(CmdLEDGet), + .A0(RWSel), .DI0(CmdLEDGet_4), .CE(N_576_i), .CLK(C14M_c), + .F0(CmdLEDGet_4), .Q0(CmdLEDGet), .F1(CmdLEDGet_4_u_0_0_a2_0_2)); + SLICE_15 SLICE_15( .D1(\Din_c[4] ), .C1(N_626), .B1(N_476), .A1(\Din_c[1] ), + .D0(RWSel), .C0(N_605), .A0(CmdLEDSet), .DI0(CmdLEDSet_4), .CE(N_576_i), + .CLK(C14M_c), .F0(CmdLEDSet_4), .Q0(CmdLEDSet), .F1(N_605)); + SLICE_16 SLICE_16( .D1(\Din_c[4] ), .B1(\Din_c[1] ), .A1(N_476), .D0(RWSel), + .C0(N_643), .B0(N_626), .A0(CmdRWMaskSet), .DI0(CmdRWMaskSet_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdRWMaskSet_4), .Q0(CmdRWMaskSet), + .F1(N_643)); + SLICE_17 SLICE_17( .D1(\Din_c[4] ), .C1(N_476), .B1(\Din_c[1] ), .A1(N_626), + .D0(RWSel), .C0(N_401), .A0(CmdSetRWBankFFLED), .DI0(CmdSetRWBankFFLED_4), + .CE(N_576_i), .CLK(C14M_c), .F0(CmdSetRWBankFFLED_4), + .Q0(CmdSetRWBankFFLED), .F1(N_401)); + SLICE_18 SLICE_18( .D1(N_474), .C1(\CS[1] ), .A1(\CS[2] ), .D0(RWSel), + .C0(N_476), .B0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), + .A0(CmdSetRWBankFFMXO2), .DI0(CmdSetRWBankFFMXO2_4), .CE(N_576_i), + .CLK(C14M_c), .F0(CmdSetRWBankFFMXO2_4), .Q0(CmdSetRWBankFFMXO2), + .F1(N_476)); + SLICE_19 SLICE_19( .D1(\CmdTout[1] ), .C1(\CmdTout[2] ), .B1(CO0_1), + .A1(RWSel), .D0(\CmdTout[1] ), .B0(CO0_1), .A0(RWSel), .DI1(N_556_i), + .DI0(N_555_i), .CE(N_576_i), .CLK(C14M_c), .F0(N_555_i), .Q0(\CmdTout[1] ), + .F1(N_556_i), .Q1(\CmdTout[2] )); + SLICE_20 SLICE_20( .D1(\S[2] ), .C1(\S[1] ), .B1(\S[3] ), .A1(\S[0] ), + .D0(\S[2] ), .C0(\S[1] ), .B0(\S[3] ), .A0(\S[0] ), .DI0(N_6_i), + .CLK(C14M_c), .F0(N_6_i), .Q0(DOEEN), .F1(N_576_i)); + SLICE_21 SLICE_21( .C1(\S[0] ), .B1(\Ain_c[1] ), .A1(\S[3] ), + .D0(\Din_c[0] ), .B0(\wb_dato[0] ), .A0(\S[3] ), .DI0(LEDEN_RNO), + .CE(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .CLK(C14M_c), .F0(LEDEN_RNO), + .Q0(LEDEN), .F1(N_558_i)); + SLICE_22 SLICE_22( .D1(\S[0] ), .C1(\Ain_c[3] ), .A1(\S[3] ), .D0(\S[0] ), + .C0(\Ain_c[0] ), .A0(\S[3] ), .DI1(N_552_i), .DI0(N_127_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c), .F0(N_127_i), .Q0(\RA_c[0] ), + .F1(N_552_i), .Q1(\RA_c[3] )); + SLICE_23 SLICE_23( .D1(N_591), .C1(\RWMask[1] ), .A1(\Din_c[1] ), .D0(N_591), + .C0(\RWMask[0] ), .A0(\Din_c[0] ), .DI1(\RWBank_5[1] ), + .DI0(\RWBank_5[0] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[0] ), + .Q0(\RWBank[0] ), .F1(\RWBank_5[1] ), .Q1(\RWBank[1] )); + SLICE_24 SLICE_24( .C1(\RWMask[3] ), .B1(\Din_c[3] ), .A1(N_591), + .D0(\Din_c[2] ), .B0(\RWMask[2] ), .A0(N_591), .DI1(\RWBank_5[3] ), + .DI0(\RWBank_5[2] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[2] ), + .Q0(\RWBank[2] ), .F1(\RWBank_5[3] ), .Q1(\RWBank[3] )); + SLICE_25 SLICE_25( .C1(\RWMask[5] ), .B1(\Din_c[5] ), .A1(N_591), + .D0(\RWMask[4] ), .C0(\Din_c[4] ), .A0(N_591), .DI1(\RWBank_5[5] ), + .DI0(\RWBank_5[4] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[4] ), + .Q0(\RWBank[4] ), .F1(\RWBank_5[5] ), .Q1(\RWBank[5] )); + SLICE_26 SLICE_26( .D1(\Din_c[7] ), .C1(\RWMask[7] ), .A1(N_591), + .C0(\Din_c[6] ), .B0(\RWMask[6] ), .A0(N_591), .DI1(\RWBank_5[7] ), + .DI0(\RWBank_5[6] ), .CE(LEDEN13), .CLK(C14M_c), .F0(\RWBank_5[6] ), + .Q0(\RWBank[6] ), .F1(\RWBank_5[7] ), .Q1(\RWBank[7] )); + SLICE_27 SLICE_27( .D1(\Din_c[1] ), .C1(\wb_dato[1] ), .A1(\S[3] ), + .C0(\wb_dato[0] ), .B0(\Din_c[0] ), .A0(\S[3] ), .DI1(N_291_i), + .DI0(N_292_i), .CE(N_88), .CLK(C14M_c), .F0(N_292_i), .Q0(\RWMask[0] ), + .F1(N_291_i), .Q1(\RWMask[1] )); + SLICE_28 SLICE_28( .D1(\wb_dato[3] ), .B1(\Din_c[3] ), .A1(\S[3] ), + .C0(\wb_dato[2] ), .B0(\Din_c[2] ), .A0(\S[3] ), .DI1(N_289_i), + .DI0(N_290_i), .CE(N_88), .CLK(C14M_c), .F0(N_290_i), .Q0(\RWMask[2] ), + .F1(N_289_i), .Q1(\RWMask[3] )); + SLICE_29 SLICE_29( .D1(\wb_dato[5] ), .C1(\Din_c[5] ), .A1(\S[3] ), + .C0(\wb_dato[4] ), .B0(\Din_c[4] ), .A0(\S[3] ), .DI1(N_287_i), + .DI0(N_288_i), .CE(N_88), .CLK(C14M_c), .F0(N_288_i), .Q0(\RWMask[4] ), + .F1(N_287_i), .Q1(\RWMask[5] )); + SLICE_30 SLICE_30( .D1(\wb_dato[7] ), .C1(\Din_c[7] ), .A1(\S[3] ), + .C0(\wb_dato[6] ), .B0(\Din_c[6] ), .A0(\S[3] ), .DI1(N_285), + .DI0(N_286_i), .CE(N_88), .CLK(C14M_c), .F0(N_286_i), .Q0(\RWMask[6] ), + .F1(N_285), .Q1(\RWMask[7] )); + SLICE_31 SLICE_31( .C1(nEN80_c), .B1(nWE_c), .A1(DOEEN), .D0(nC07X_c), + .C0(\RA_c[0] ), .B0(nWE_c), .A0(\RA_c[3] ), .DI0(RWSel_2), .CE(nCS61), + .CLK(C14M_c), .F0(RWSel_2), .Q0(RWSel), .F1(nDOE_c)); + SLICE_32 SLICE_32( .D1(\FS[6] ), .C1(\FS[7] ), .B1(N_489), + .A1(Ready_0_sqmuxa_0_a2_6_a2_4), .C0(Ready_0_sqmuxa), .A0(Ready), + .DI0(N_876_0), .CLK(C14M_c), .F0(N_876_0), .Q0(Ready), .F1(Ready_0_sqmuxa)); + SLICE_33 SLICE_33( .D1(N_572), .C1(N_575), .B1(S_1), .A1(wb_reqc_1), + .D0(\S_s_0_1[0] ), .C0(\S[1] ), .B0(S_1), .A0(\S[0] ), .DI1(N_133_i), + .DI0(\S_s_0[0] ), .CLK(C14M_c), .F0(\S_s_0[0] ), .Q0(\S[0] ), .F1(N_133_i), + .Q1(\S[1] )); + SLICE_34 SLICE_34( .D1(N_575), .C1(\S[2] ), .B1(S_1), .A1(\S[3] ), + .D0(N_575), .C0(\S[3] ), .B0(S_1), .A0(\S[2] ), .DI1(N_129_i), + .DI0(N_131_i), .CLK(C14M_c), .F0(N_131_i), .Q0(\S[2] ), .F1(N_129_i), + .Q1(\S[3] )); + SLICE_35 SLICE_35( .D1(N_388), .C1(\Din_c[1] ), .B1(\S[2] ), + .A1(wb_adr_7_5_214_0_1), .D0(\wb_adr_7_0_4[0] ), .C0(N_376), .B0(N_642), + .A0(\FS[13] ), .DI1(\wb_adr_RNO[1] ), .DI0(\wb_adr_7[0] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_adr_7[0] ), + .Q0(\wb_adr[0] ), .F1(\wb_adr_RNO[1] ), .Q1(\wb_adr[1] )); + SLICE_36 SLICE_36( .C1(\Din_c[3] ), .B1(\S[2] ), .C0(\Din_c[2] ), + .B0(\S[2] ), .DI1(N_41_i), .DI0(N_43_i), .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), + .CLK(C14M_c), .F0(N_43_i), .Q0(\wb_adr[2] ), .F1(N_41_i), .Q1(\wb_adr[3] )); + SLICE_37 SLICE_37( .C1(\S[2] ), .B1(\FS[14] ), .A1(\Din_c[5] ), + .D0(\Din_c[4] ), .C0(\S[2] ), .B0(\FS[14] ), .DI1(N_295), .DI0(N_294), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_294), + .Q0(\wb_adr[4] ), .F1(N_295), .Q1(\wb_adr[5] )); + SLICE_38 SLICE_38( .C1(\Din_c[7] ), .B1(\S[2] ), .D0(\Din_c[6] ), + .C0(\FS[14] ), .B0(\S[2] ), .DI1(N_39_i), .DI0(N_296), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(N_296), + .Q0(\wb_adr[6] ), .F1(N_39_i), .Q1(\wb_adr[7] )); + SLICE_39 SLICE_39( .D1(\FS[0] ), .C1(\FS[14] ), .B1(wb_ack), .A1(N_300), + .C0(N_395), .B0(\S[3] ), .A0(CmdExecMXO2), .DI0(wb_cyc_stb_RNO), + .CE(N_104), .CLK(C14M_c), .F0(wb_cyc_stb_RNO), .Q0(wb_cyc_stb), .F1(N_395)); + SLICE_40 SLICE_40( .D1(N_336), .C1(N_627), .B1(N_621), + .A1(\wb_dati_7_0_0[1] ), .D0(\wb_dati_7_0_a2_1[0] ), .C0(\S[2] ), + .B0(\wb_adr[0] ), .A0(N_484), .DI1(\wb_dati_7[1] ), .DI0(\wb_dati_7[0] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[0] ), + .Q0(\wb_dati[0] ), .F1(\wb_dati_7[1] ), .Q1(\wb_dati[1] )); + SLICE_41 SLICE_41( .D1(\wb_dati_7_0_2[3] ), .B1(\wb_dati_7_0_0[3] ), + .A1(N_336), .D0(\wb_dati_7_0_o2_0[2] ), .C0(N_345), .B0(\S[2] ), + .A0(\wb_adr[2] ), .DI1(\wb_dati_7[3] ), .DI0(\wb_dati_7[2] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[2] ), + .Q0(\wb_dati[2] ), .F1(\wb_dati_7[3] ), .Q1(\wb_dati[3] )); + SLICE_42 SLICE_42( .D1(\wb_dati_7_0_o2_0[2] ), .C1(N_345), .B1(\S[2] ), + .A1(\wb_adr[5] ), .D0(N_346), .C0(N_349), .B0(N_345), + .A0(\wb_dati_7_0_0[4] ), .DI1(\wb_dati_7[5] ), .DI0(\wb_dati_7[4] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[4] ), + .Q0(\wb_dati[4] ), .F1(\wb_dati_7[5] ), .Q1(\wb_dati[5] )); + SLICE_43 SLICE_43( .D1(\wb_dati_7_0_RNO[7] ), .C1(N_424), + .B1(\wb_dati_7_0_0[7] ), .A1(N_422), .D0(\wb_dati_7_0_1[6] ), .C0(N_621), + .A0(N_627), .DI1(\wb_dati_7[7] ), .DI0(\wb_dati_7[6] ), + .CE(\un1_wb_adr_0_sqmuxa_2_i[0] ), .CLK(C14M_c), .F0(\wb_dati_7[6] ), + .Q0(\wb_dati[6] ), .F1(\wb_dati_7[7] ), .Q1(\wb_dati[7] )); + SLICE_44 SLICE_44( .D1(\FS[11] ), .C1(\FS[12] ), .A1(\FS[13] ), + .D0(\FS[14] ), .C0(wb_reqc_1), .B0(\S[3] ), .A0(N_397), .DI0(wb_reqc_i), + .CE(wb_adr_0_sqmuxa_i), .LSR(\S[2] ), .CLK(C14M_c), .F0(wb_reqc_i), + .Q0(wb_req), .F1(N_397)); + SLICE_45 SLICE_45( .C1(\FS[14] ), .B1(wb_ack), .C0(\FS[14] ), .B0(\FS[15] ), + .DI0(wb_rst8), .LSR(\S_RNII9DO1[1] ), .CLK(C14M_c), .F0(wb_rst8), + .Q0(wb_rst), .F1(N_586)); + SLICE_46 SLICE_46( .D1(\FS[8] ), .C1(\FS[9] ), .B1(\FS[10] ), .A1(\FS[12] ), + .D0(\FS[13] ), .C0(N_584), .B0(N_475), .A0(wb_we_7_iv_0_0_0_1), + .DI0(wb_we_RNO), .CE(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), .CLK(C14M_c), + .F0(wb_we_RNO), .Q0(wb_we), .F1(N_584)); + SLICE_47 SLICE_47( .D1(N_255), .C1(\S_RNII9DO1[1] ), .B1(\RWBank[6] ), + .A1(\S[0] ), .D0(\S[3] ), .C0(\S[0] ), .B0(\S[2] ), .A0(\S[1] ), + .F0(\S_RNII9DO1[1] ), .F1(N_358_i)); + SLICE_48 SLICE_48( .D1(\S[2] ), .C1(\S[1] ), .B1(\S[0] ), .A1(\S[3] ), + .D0(N_254), .C0(Vout3), .B0(N_635), .A0(\S[0] ), .F0(nCAS_s_i_tz_0), + .F1(Vout3)); + SLICE_49 SLICE_49( .D1(un1_CS_0_sqmuxa_0_0_a2_1_4), .C1(\CS[0] ), + .B1(\Din_c[6] ), .A1(RWSel), .D0(\CS[1] ), .C0(N_327), .B0(\CS[2] ), + .A0(RWSel), .F0(un1_CS_0_sqmuxa_0_0_0), .F1(N_327)); + SLICE_50 SLICE_50( .D1(\FS[8] ), .C1(\FS[10] ), .B1(\FS[9] ), .A1(\FS[11] ), + .D0(\wb_dati_7_0_a2_0_1[7] ), .C0(N_579), .B0(\FS[9] ), .A0(N_621), + .F0(\wb_dati_7_0_RNO[7] ), .F1(\wb_dati_7_0_a2_0_1[7] )); + SLICE_51 SLICE_51( .D1(\S[2] ), .C1(\S[3] ), .B1(wb_reqc_1), + .A1(CKE_6_iv_i_a2_0), .D0(N_489), .C0(\S[3] ), .B0(CKE_6_iv_i_0_1), + .A0(\FS[15] ), .F0(CKE_6_iv_i_0), .F1(CKE_6_iv_i_0_1)); + SLICE_52 SLICE_52( .D1(N_449), .C1(\FS[0] ), .B1(N_300), .A1(wb_req), + .D0(N_449), .C0(N_586), .B0(N_365), .A0(N_364), .F0(N_104), .F1(N_365)); + SLICE_53 SLICE_53( .D1(RWSel), .C1(\FS[15] ), .B1(\S[2] ), .A1(\S[3] ), + .D0(CmdExecMXO2), .C0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .B0(\S[2] ), + .A0(wb_reqc_1), .F0(\un1_wb_cyc_stb_0_sqmuxa_1_i[0] ), + .F1(\un1_wb_adr_0_sqmuxa_2_1[0] )); + SLICE_54 SLICE_54( .D1(\Din_c[1] ), .C1(\Din_c[0] ), .B1(\Din_c[2] ), + .A1(\CS[1] ), .D0(\Din_c[1] ), .C0(N_623), .B0(N_616), .A0(\CS[2] ), + .F0(N_279), .F1(N_623)); + SLICE_55 SLICE_55( .D1(N_633), .C1(N_264), .B1(\FS[5] ), .A1(\FS[4] ), + .D0(\FS[2] ), .C0(\FS[1] ), .B0(\FS[5] ), .A0(\FS[3] ), .F0(N_633), + .F1(N_570)); + SLICE_56 SLICE_56( .D1(\FS[14] ), .C1(\S_RNII9DO1[1] ), .A1(\FS[15] ), + .C0(\FS[12] ), .B0(N_452), .A0(\FS[13] ), .F0(N_621), .F1(N_452)); + SLICE_57 SLICE_57( .D1(\S_RNII9DO1_0[1] ), .C1(RWSel), .B1(wb_ack), + .A1(CmdExecMXO2), .D0(\S[2] ), .C0(\S[3] ), .B0(\S[0] ), .A0(\S[1] ), + .F0(\S_RNII9DO1_0[1] ), .F1(N_364)); + SLICE_58 SLICE_58( .D1(\FS[12] ), .C1(\wb_dati_7_0_a2_2_1[3] ), .B1(N_455), + .A1(N_644), .D0(\FS[10] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[11] ), + .F0(\wb_dati_7_0_a2_2_1[3] ), .F1(\wb_dati_7_0_2[3] )); + SLICE_59 SLICE_59( .D1(\RWBank[6] ), .C1(nCS61), .B1(\S_RNII9DO1[1] ), + .A1(DQML_s_i_a2_0), .D0(\S[3] ), .C0(\S[0] ), .B0(\S[1] ), .A0(\S[2] ), + .F0(DQML_s_i_a2_0), .F1(N_28_i)); + SLICE_60 SLICE_60( .D1(wb_adr_7_5_214_a2_2_0), .C1(N_569), .B1(N_577), + .A1(N_475), .D0(\FS[10] ), .C0(\FS[12] ), .A0(\FS[13] ), + .F0(wb_adr_7_5_214_a2_2_0), .F1(wb_adr_7_5_214_0_1)); + SLICE_61 SLICE_61( .D1(\FS[13] ), .C1(N_634), .B1(\FS[12] ), .D0(\FS[11] ), + .C0(\FS[8] ), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_634), + .F1(\wb_dati_7_0_a2_2_0[1] )); + SLICE_62 SLICE_62( .D1(N_265_i), .C1(\FS[12] ), .B1(N_475), .A1(\FS[11] ), + .D0(\FS[10] ), .B0(\FS[9] ), .A0(\FS[8] ), .F0(N_265_i), .F1(N_388)); + SLICE_63 SLICE_63( .D1(\FS[6] ), .C1(N_264), .B1(\FS[7] ), .A1(N_254), + .C0(\FS[1] ), .B0(\FS[3] ), .A0(\FS[2] ), .F0(N_264), .F1(N_300)); + SLICE_64 SLICE_64( .C1(\FS[8] ), .B1(\FS[9] ), .A1(\FS[11] ), .D0(N_577), + .C0(wb_ack), .B0(\FS[10] ), .A0(\FS[12] ), + .F0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), .F1(N_577)); + SLICE_65 SLICE_65( .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[10] ), + .C0(\FS[12] ), .B0(\wb_dati_7_0_a2_0[6] ), .A0(\FS[13] ), + .F0(\wb_dati_7_0_a2_4_0[7] ), .F1(\wb_dati_7_0_a2_0[6] )); + SLICE_66 SLICE_66( .B1(\FS[14] ), .A1(\S[2] ), .D0(\FS[13] ), .C0(\FS[11] ), + .B0(N_475), .A0(\FS[12] ), .F0(N_393), .F1(N_475)); + SLICE_67 SLICE_67( .D1(\S[1] ), .C1(\S[0] ), .D0(\S[3] ), .C0(wb_reqc_1), + .B0(RWSel), .A0(\S[2] ), .F0(LEDEN13), .F1(wb_reqc_1)); + SLICE_68 SLICE_68( .D1(\wb_adr[3] ), .C1(N_627), .B1(N_455), .A1(\S[2] ), + .D0(\FS[9] ), .C0(\FS[10] ), .B0(\FS[11] ), .A0(\FS[8] ), .F0(N_627), + .F1(\wb_dati_7_0_0[3] )); + SLICE_69 SLICE_69( .D1(nCAS_0_sqmuxa), .C1(N_639), .B1(\RWBank[2] ), + .A1(N_255), .D0(\S[0] ), .C0(\S[3] ), .B0(\S[2] ), .A0(\S[1] ), .F0(N_639), + .F1(\RA_42[10] )); + SLICE_70 SLICE_70( .D1(\FS[12] ), .C1(N_627), .B1(N_455), .A1(N_644), + .D0(\FS[10] ), .C0(\FS[9] ), .B0(\FS[8] ), .A0(\FS[11] ), .F0(N_644), + .F1(N_345)); + SLICE_71 SLICE_71( .D1(nCS61), .C1(N_633), .B1(\FS[4] ), .A1(N_640), + .D0(\S[1] ), .C0(\S[0] ), .B0(\S[3] ), .A0(\S[2] ), .F0(nCS61), + .F1(un1_nCS61_1_i)); + SLICE_72 SLICE_72( .D1(\FS[5] ), .C1(N_449), .B1(Ready_0_sqmuxa_0_a2_6_a2_2), + .A1(\FS[3] ), .D0(\S[3] ), .C0(wb_reqc_1), .B0(\FS[15] ), .A0(\S[2] ), + .F0(N_449), .F1(Ready_0_sqmuxa_0_a2_6_a2_4)); + SLICE_73 SLICE_73( .D1(N_562), .C1(N_455), .B1(\FS[12] ), .A1(\FS[11] ), + .D0(\FS[13] ), .C0(\FS[14] ), .B0(\S_RNII9DO1[1] ), .A0(\FS[15] ), + .F0(N_455), .F1(N_377)); + SLICE_74 SLICE_74( .D1(N_484), .C1(\FS[11] ), .B1(\FS[9] ), .D0(\FS[10] ), + .C0(\FS[12] ), .B0(N_642), .A0(\FS[13] ), .F0(N_346), .F1(N_642)); + SLICE_75 SLICE_75( .D1(\FS[7] ), .C1(\FS[0] ), .B1(N_489), .A1(\FS[6] ), + .C0(N_628), .B0(\S_RNII9DO1[1] ), .A0(\FS[15] ), .F0(N_640), .F1(N_628)); + SLICE_76 SLICE_76( .D1(\FS[4] ), .A1(\FS[5] ), .D0(N_254), .C0(N_449), + .B0(N_628), .A0(N_264), .F0(nCAS_0_sqmuxa), .F1(N_254)); + SLICE_77 SLICE_77( .D1(\CS[0] ), .C1(N_466), .A1(\Din_c[6] ), + .D0(un1_CS_0_sqmuxa_0_0_3), .C0(un1_CS_0_sqmuxa_0_0_2), .B0(N_474), + .A0(un1_CS_0_sqmuxa_0_0_a2_3_2), .F0(un1_CS_0_sqmuxa_i), .F1(N_474)); + SLICE_78 SLICE_78( .D1(\FS[4] ), .A1(N_633), .D0(N_567), .C0(N_640), + .B0(nCAS_s_i_tz_0), .A0(nCAS_0_sqmuxa), .F0(N_561_i), .F1(N_567)); + SLICE_79 SLICE_79( .D1(\S[3] ), .C1(nEN80_c), .B1(\S[2] ), .A1(\S[1] ), + .B0(nCS_6_u_i_0), .A0(N_559_1), .F0(N_559_i), .F1(nCS_6_u_i_0)); + SLICE_80 SLICE_80( .D1(\S[3] ), .B1(\S[1] ), .A1(\S[2] ), .C0(\S[0] ), + .B0(N_635), .A0(N_559_1), .F0(nRAS_2_iv_i), .F1(N_635)); + SLICE_81 SLICE_81( .D1(\CS[0] ), .C1(\Din_c[6] ), .B1(\Din_c[4] ), + .A1(\Din_c[3] ), .D0(un1_CS_0_sqmuxa_0_0_0), .C0(un1_CS_0_sqmuxa_0_0_a2_1), + .B0(N_279), .A0(N_466), .F0(un1_CS_0_sqmuxa_0_0_2), + .F1(un1_CS_0_sqmuxa_0_0_a2_1)); + SLICE_82 SLICE_82( .D1(CO0_1), .C1(RWSel), .B1(\CmdTout[1] ), + .A1(\CmdTout[2] ), .D0(N_461), .C0(N_328), .B0(N_330), + .A0(\S_RNII9DO1_0[1] ), .F0(un1_CS_0_sqmuxa_0_0_3), .F1(N_461)); + SLICE_83 SLICE_83( .D1(\FS[15] ), .C1(\S[0] ), .B1(\S[2] ), .A1(\S[3] ), + .D0(N_570), .C0(nCS_6_u_i_a2_1), .B0(N_429), .A0(N_628), .F0(N_559_1), + .F1(nCS_6_u_i_a2_1)); + SLICE_84 SLICE_84( .D1(\FS[10] ), .C1(\FS[12] ), .B1(N_455), + .A1(\wb_dati_7_0_a2_0[6] ), .D0(\wb_adr[6] ), .C0(N_346), .B0(\S[2] ), + .A0(N_351), .F0(\wb_dati_7_0_1[6] ), .F1(N_351)); + SLICE_85 SLICE_85( .D1(\wb_adr_7_0_a2_5_0[0] ), .C1(N_579), .B1(N_452), + .A1(\FS[8] ), .D0(N_378), .C0(N_377), .B0(\wb_adr_7_0_1[0] ), + .A0(\wb_adr_7_0_0[0] ), .F0(\wb_adr_7_0_4[0] ), .F1(\wb_adr_7_0_1[0] )); + SLICE_86 SLICE_86( .D1(\FS[15] ), .C1(\S_RNII9DO1[1] ), .B1(\FS[14] ), + .A1(\FS[8] ), .D0(CmdLEDSet), .C0(N_484), .B0(LEDEN13), + .A0(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ), + .F0(\un1_LEDEN_0_sqmuxa_1_i_0[0] ), .F1(N_484)); + SLICE_87 SLICE_87( .D1(RWSel), .C1(un1_CS_0_sqmuxa_0_0_a2_4_2), + .B1(\Din_c[6] ), .A1(\CS[0] ), .C0(un1_CS_0_sqmuxa_0_0_a2_4_4), + .B0(\CS[2] ), .A0(\CS[1] ), .F0(N_330), .F1(un1_CS_0_sqmuxa_0_0_a2_4_4)); + SLICE_88 SLICE_88( .D1(\FS[12] ), .A1(\FS[13] ), .D0(N_336), .C0(N_452), + .B0(N_634), .A0(N_569), .F0(\wb_dati_7_0_o2_0[2] ), .F1(N_569)); + SLICE_89 SLICE_89( .D1(\FS[10] ), .A1(\FS[11] ), .D0(N_455), .C0(\FS[8] ), + .B0(\FS[9] ), .A0(N_579), .F0(N_378), .F1(N_579)); + SLICE_90 SLICE_90( .D1(\FS[10] ), .C1(\FS[11] ), .B1(\FS[9] ), .A1(\FS[13] ), + .C0(N_565), .B0(N_484), .A0(\FS[12] ), .F0(N_336), .F1(N_565)); + SLICE_91 SLICE_91( .D1(\CS[0] ), .C1(\Din_c[6] ), .B1(\CS[2] ), + .A1(un1_CS_0_sqmuxa_0_0_a2_2_2), .C0(RWSel), + .B0(un1_CS_0_sqmuxa_0_0_a2_2_4), .A0(\Din_c[7] ), .F0(N_328), + .F1(un1_CS_0_sqmuxa_0_0_a2_2_4)); + SLICE_92 SLICE_92( .D1(\FS[11] ), .C1(\FS[13] ), .B1(N_562), .A1(\FS[12] ), + .D0(N_452), .C0(\wb_adr_7_0_a2_0[0] ), .B0(\S[2] ), .A0(\Din_c[0] ), + .F0(\wb_adr_7_0_0[0] ), .F1(\wb_adr_7_0_a2_0[0] )); + SLICE_93 SLICE_93( .D1(N_616), .C1(\Din_c[5] ), .B1(\Din_c[4] ), + .A1(\Din_c[1] ), .D0(\Din_c[7] ), .C0(\Din_c[3] ), + .B0(un1_CS_0_sqmuxa_0_0_a2_1_2), .A0(\CS[1] ), + .F0(un1_CS_0_sqmuxa_0_0_a2_1_4), .F1(un1_CS_0_sqmuxa_0_0_a2_1_2)); + SLICE_94 SLICE_94( .D1(\Din_c[3] ), .C1(\Din_c[0] ), .B1(\Din_c[2] ), + .A1(\Din_c[1] ), .D0(\CS[1] ), .C0(un1_CS_0_sqmuxa_0_0_a2_3_0), + .B0(\Din_c[4] ), .A0(\CS[2] ), .F0(un1_CS_0_sqmuxa_0_0_a2_3_2), + .F1(un1_CS_0_sqmuxa_0_0_a2_3_0)); + SLICE_95 SLICE_95( .D1(N_475), .C1(N_577), .B1(\FS[10] ), .A1(\FS[12] ), + .D0(N_393), .C0(N_394), .B0(\S[2] ), .A0(\Din_c[0] ), + .F0(wb_we_7_iv_0_0_0_1), .F1(N_394)); + SLICE_96 SLICE_96( .D1(\S[3] ), .B1(\S[2] ), .A1(\S[1] ), .D0(\RWBank[0] ), + .C0(N_255), .B0(\S[0] ), .A0(\RWBank[7] ), .F0(N_49_i), .F1(N_255)); + SLICE_97 SLICE_97( .D1(\FS[10] ), .A1(\FS[12] ), .D0(\FS[14] ), .C0(N_577), + .B0(N_456), .A0(\FS[13] ), .F0(N_489), .F1(N_456)); + SLICE_98 SLICE_98( .D1(\Din_c[0] ), .C1(\Din_c[3] ), .B1(\Din_c[2] ), + .D0(N_477), .C0(\Din_c[7] ), .B0(N_626), .A0(\Din_c[5] ), + .F0(un1_CS_0_sqmuxa_0_0_a2_4_2), .F1(N_626)); + SLICE_99 SLICE_99( .D1(\Din_c[3] ), .B1(\Din_c[2] ), .D0(N_477), .C0(N_478), + .B0(\Din_c[5] ), .A0(\Din_c[0] ), .F0(un1_CS_0_sqmuxa_0_0_a2_2_2), + .F1(N_478)); + SLICE_100 SLICE_100( .C1(\Din_c[3] ), .B1(\Din_c[0] ), .A1(\Din_c[2] ), + .D0(\Din_c[1] ), .C0(\Din_c[4] ), .B0(N_629), + .F0(CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0), .F1(N_629)); + SLICE_101 SLICE_101( .D1(\S[1] ), .C1(\S[0] ), .B1(\S[2] ), .A1(\S[3] ), + .D0(\S[1] ), .C0(\S[0] ), .B0(\S[2] ), .A0(\S[3] ), .F0(\S_RNII9DO1_1[1] ), + .F1(N_566_i)); + SLICE_102 SLICE_102( .D1(\S[2] ), .C1(\S[0] ), .B1(\S[1] ), .A1(\S[3] ), + .D0(\S[2] ), .C0(\RWBank[4] ), .B0(\S[1] ), .A0(\S[3] ), .F0(\BA_4[0] ), + .F1(\S_s_0_1[0] )); + SLICE_103 SLICE_103( .D1(\S[3] ), .C1(wb_reqc_1), .B1(\RWBank[3] ), + .A1(\S[2] ), .D0(\S[3] ), .C0(\FS[15] ), .B0(wb_reqc_1), .A0(\S[2] ), + .F0(wb_adr_0_sqmuxa_i), .F1(\RA_42[11] )); + SLICE_104 SLICE_104( .D1(\FS[11] ), .C1(N_621), .B1(\FS[9] ), .A1(\FS[8] ), + .D0(\FS[11] ), .C0(N_621), .B0(\FS[9] ), .A0(\FS[10] ), .F0(N_376), + .F1(N_349)); + SLICE_105 SLICE_105( .D1(N_569), .C1(wb_ack), .B1(\FS[9] ), .A1(N_579), + .D0(N_569), .C0(N_484), .B0(\FS[9] ), .A0(N_579), .F0(N_424), + .F1(\un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] )); + SLICE_106 SLICE_106( .C1(\S[1] ), .B1(\S[0] ), .C0(\S[1] ), .B0(\S[0] ), + .A0(nEN80_c), .F0(CKE_6_iv_i_a2_0), .F1(N_575)); + SLICE_107 SLICE_107( .D1(\S[3] ), .C1(\S[2] ), .D0(\S[3] ), .C0(\S[2] ), + .B0(\RWBank[5] ), .A0(\S[1] ), .F0(\BA_4[1] ), .F1(N_572)); + SLICE_108 SLICE_108( .C1(\FS[9] ), .B1(\FS[12] ), .A1(\FS[10] ), .D0(N_642), + .C0(\FS[13] ), .B0(\FS[12] ), .A0(\FS[10] ), .F0(N_422), + .F1(\wb_adr_7_0_a2_5_0[0] )); + SLICE_109 SLICE_109( .D1(\S[2] ), .C1(\wb_adr[7] ), .B1(N_452), + .A1(\wb_dati_7_0_a2_4_0[7] ), .D0(\S[2] ), .C0(\wb_adr[1] ), .B0(N_452), + .A0(\wb_dati_7_0_a2_2_0[1] ), .F0(\wb_dati_7_0_0[1] ), + .F1(\wb_dati_7_0_0[7] )); + SLICE_110 SLICE_110( .D1(\S[3] ), .C1(wb_reqc_1), .B1(\S[2] ), + .A1(\RWBank[1] ), .D0(\un1_wb_adr_0_sqmuxa_2_1[0] ), .C0(wb_reqc_1), + .B0(\S[2] ), .A0(CmdBitbangMXO2), .F0(\un1_wb_adr_0_sqmuxa_2_i[0] ), + .F1(N_59_i)); + SLICE_111 SLICE_111( .D1(\S[3] ), .B1(\S[0] ), .A1(\Ain_c[5] ), .D0(\S[3] ), + .B0(\S[0] ), .A0(\Ain_c[4] ), .F0(N_551_i), .F1(\RA_42_3_0[5] )); + SLICE_112 SLICE_112( .D1(\S[0] ), .C1(N_254), .B1(\S[1] ), .A1(\S[3] ), + .C0(\Ain_c[6] ), .B0(\S[0] ), .A0(\S[3] ), .F0(N_550_i), .F1(N_429)); + SLICE_113 SLICE_113( .C1(\S[0] ), .B1(\Ain_c[2] ), .A1(\S[3] ), .C0(\S[0] ), + .B0(\Ain_c[7] ), .A0(\S[3] ), .F0(N_549_i), .F1(N_553_i)); + SLICE_114 SLICE_114( .D1(\S[2] ), .C1(N_634), .B1(N_455), .A1(\wb_adr[4] ), + .D0(N_455), .C0(CmdRWMaskSet), .B0(\un1_RWMask_0_sqmuxa_1_i_a2_0_1[0] ), + .A0(LEDEN13), .F0(N_88), .F1(\wb_dati_7_0_0[4] )); + SLICE_115 SLICE_115( .B1(nEN80_c), .A1(nWE80_c), .D0(un1_nCS61_1_i), + .C0(nCAS_0_sqmuxa), .B0(\S[0] ), .A0(nWE80_c), .F0(nRWE_r_0), .F1(RDOE_i)); + SLICE_116 SLICE_116( .B1(\FS[9] ), .A1(\FS[8] ), .D0(\FS[11] ), .C0(N_456), + .B0(\FS[9] ), .A0(\FS[13] ), .F0(\wb_dati_7_0_a2_1[0] ), .F1(N_562)); + SLICE_117 SLICE_117( .D1(CmdSetRWBankFFMXO2), .C1(LEDEN), + .B1(CmdSetRWBankFFLED), .A1(CmdLEDGet), .C0(LEDEN), .A0(nEN80_c), + .F0(LED_c), .F1(N_591)); + SLICE_118 SLICE_118( .D1(\Din_c[4] ), .C1(\Din_c[1] ), .B0(\Din_c[2] ), + .A0(\Din_c[0] ), .F0(N_616), .F1(N_477)); + SLICE_119 SLICE_119( .D0(\FS[1] ), .C0(\FS[0] ), .B0(\FS[2] ), .A0(\FS[4] ), + .F0(Ready_0_sqmuxa_0_a2_6_a2_2)); + RD_0_ \RD[0]_I ( .PADDI(\RD_in[0] ), .PADDT(RDOE_i), .PADDO(\Din_c[0] ), + .RD0(RD[0])); + LED LED_I( .PADDO(LED_c), .LED(LED)); + C14M C14M_I( .PADDI(C14M_c), .C14M(C14M)); + DQMH DQMH_I( .IOLDO(DQMH_c), .DQMH(DQMH)); + DQMH_MGIOL DQMH_MGIOL( .IOLDO(DQMH_c), .OPOS(N_358_i), .CLK(C14M_c)); + DQML DQML_I( .IOLDO(DQML_c), .DQML(DQML)); + DQML_MGIOL DQML_MGIOL( .IOLDO(DQML_c), .OPOS(N_28_i), .CLK(C14M_c)); + RD_7_ \RD[7]_I ( .PADDI(\RD_in[7] ), .PADDT(RDOE_i), .PADDO(\Din_c[7] ), + .RD7(RD[7])); + RD_6_ \RD[6]_I ( .PADDI(\RD_in[6] ), .PADDT(RDOE_i), .PADDO(\Din_c[6] ), + .RD6(RD[6])); + RD_5_ \RD[5]_I ( .PADDI(\RD_in[5] ), .PADDT(RDOE_i), .PADDO(\Din_c[5] ), + .RD5(RD[5])); + RD_4_ \RD[4]_I ( .PADDI(\RD_in[4] ), .PADDT(RDOE_i), .PADDO(\Din_c[4] ), + .RD4(RD[4])); + RD_3_ \RD[3]_I ( .PADDI(\RD_in[3] ), .PADDT(RDOE_i), .PADDO(\Din_c[3] ), + .RD3(RD[3])); + RD_2_ \RD[2]_I ( .PADDI(\RD_in[2] ), .PADDT(RDOE_i), .PADDO(\Din_c[2] ), + .RD2(RD[2])); + RD_1_ \RD[1]_I ( .PADDI(\RD_in[1] ), .PADDT(RDOE_i), .PADDO(\Din_c[1] ), + .RD1(RD[1])); + RA_11_ \RA[11]_I ( .IOLDO(\RA_c[11] ), .RA11(RA[11])); + RA_11__MGIOL \RA[11]_MGIOL ( .IOLDO(\RA_c[11] ), .OPOS(\RA_42[11] ), + .CLK(C14M_c)); + RA_10_ \RA[10]_I ( .IOLDO(\RA_c[10] ), .RA10(RA[10])); + RA_10__MGIOL \RA[10]_MGIOL ( .IOLDO(\RA_c[10] ), .OPOS(\RA_42[10] ), + .CLK(C14M_c)); + RA_9_ \RA[9]_I ( .IOLDO(\RA_c[9] ), .RA9(RA[9])); + RA_9__MGIOL \RA[9]_MGIOL ( .IOLDO(\RA_c[9] ), .OPOS(N_59_i), .CLK(C14M_c)); + RA_8_ \RA[8]_I ( .IOLDO(\RA_c[8] ), .RA8(RA[8])); + RA_8__MGIOL \RA[8]_MGIOL ( .IOLDO(\RA_c[8] ), .OPOS(N_49_i), .CLK(C14M_c)); + RA_7_ \RA[7]_I ( .IOLDO(\RA_c[7] ), .RA7(RA[7])); + RA_7__MGIOL \RA[7]_MGIOL ( .IOLDO(\RA_c[7] ), .OPOS(N_549_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_6_ \RA[6]_I ( .IOLDO(\RA_c[6] ), .RA6(RA[6])); + RA_6__MGIOL \RA[6]_MGIOL ( .IOLDO(\RA_c[6] ), .OPOS(N_550_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_5_ \RA[5]_I ( .IOLDO(\RA_c[5] ), .RA5(RA[5])); + RA_5__MGIOL \RA[5]_MGIOL ( .IOLDO(\RA_c[5] ), .OPOS(\RA_42_3_0[5] ), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_4_ \RA[4]_I ( .IOLDO(\RA_c[4] ), .RA4(RA[4])); + RA_4__MGIOL \RA[4]_MGIOL ( .IOLDO(\RA_c[4] ), .OPOS(N_551_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_3_ \RA[3]_I ( .PADDO(\RA_c[3] ), .RA3(RA[3])); + RA_2_ \RA[2]_I ( .IOLDO(\RA_c[2] ), .RA2(RA[2])); + RA_2__MGIOL \RA[2]_MGIOL ( .IOLDO(\RA_c[2] ), .OPOS(N_553_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_1_ \RA[1]_I ( .IOLDO(\RA_c[1] ), .RA1(RA[1])); + RA_1__MGIOL \RA[1]_MGIOL ( .IOLDO(\RA_c[1] ), .OPOS(N_558_i), + .CE(\S_RNII9DO1_1[1] ), .CLK(C14M_c)); + RA_0_ \RA[0]_I ( .PADDO(\RA_c[0] ), .RA0(RA[0])); + BA_1_ \BA[1]_I ( .IOLDO(\BA_c[1] ), .BA1(BA[1])); + BA_1__MGIOL \BA[1]_MGIOL ( .IOLDO(\BA_c[1] ), .OPOS(\BA_4[1] ), + .LSR(N_566_i), .CLK(C14M_c)); + BA_0_ \BA[0]_I ( .IOLDO(\BA_c[0] ), .BA0(BA[0])); + BA_0__MGIOL \BA[0]_MGIOL ( .IOLDO(\BA_c[0] ), .OPOS(\BA_4[0] ), + .LSR(N_566_i), .CLK(C14M_c)); + nRWE nRWE_I( .IOLDO(nRWE_c), .nRWE(nRWE)); + nRWE_MGIOL nRWE_MGIOL( .IOLDO(nRWE_c), .OPOS(nRWE_r_0), .CLK(C14M_c)); + nCAS nCAS_I( .IOLDO(nCAS_c), .nCAS(nCAS)); + nCAS_MGIOL nCAS_MGIOL( .IOLDO(nCAS_c), .OPOS(N_561_i), .CLK(C14M_c)); + nRAS nRAS_I( .IOLDO(nRAS_c), .nRAS(nRAS)); + nRAS_MGIOL nRAS_MGIOL( .IOLDO(nRAS_c), .OPOS(nRAS_2_iv_i), .CLK(C14M_c)); + nCS nCS_I( .IOLDO(nCS_c), .nCS(nCS)); + nCS_MGIOL nCS_MGIOL( .IOLDO(nCS_c), .OPOS(N_559_i), .CLK(C14M_c)); + CKE CKE_I( .IOLDO(CKE_c), .CKE(CKE)); + CKE_MGIOL CKE_MGIOL( .IOLDO(CKE_c), .OPOS(CKE_6_iv_i_0), .CLK(C14M_c)); + nVOE nVOE_I( .PADDO(PHI1_c), .nVOE(nVOE)); + Vout_7_ \Vout[7]_I ( .IOLDO(\Vout_c[7] ), .Vout7(Vout[7])); + Vout_7__MGIOL \Vout[7]_MGIOL ( .IOLDO(\Vout_c[7] ), .OPOS(\RD_in[7] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_6_ \Vout[6]_I ( .IOLDO(\Vout_c[6] ), .Vout6(Vout[6])); + Vout_6__MGIOL \Vout[6]_MGIOL ( .IOLDO(\Vout_c[6] ), .OPOS(\RD_in[6] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_5_ \Vout[5]_I ( .IOLDO(\Vout_c[5] ), .Vout5(Vout[5])); + Vout_5__MGIOL \Vout[5]_MGIOL ( .IOLDO(\Vout_c[5] ), .OPOS(\RD_in[5] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_4_ \Vout[4]_I ( .IOLDO(\Vout_c[4] ), .Vout4(Vout[4])); + Vout_4__MGIOL \Vout[4]_MGIOL ( .IOLDO(\Vout_c[4] ), .OPOS(\RD_in[4] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_3_ \Vout[3]_I ( .IOLDO(\Vout_c[3] ), .Vout3(Vout[3])); + Vout_3__MGIOL \Vout[3]_MGIOL ( .IOLDO(\Vout_c[3] ), .OPOS(\RD_in[3] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_2_ \Vout[2]_I ( .IOLDO(\Vout_c[2] ), .Vout2(Vout[2])); + Vout_2__MGIOL \Vout[2]_MGIOL ( .IOLDO(\Vout_c[2] ), .OPOS(\RD_in[2] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_1_ \Vout[1]_I ( .IOLDO(\Vout_c[1] ), .Vout1(Vout[1])); + Vout_1__MGIOL \Vout[1]_MGIOL ( .IOLDO(\Vout_c[1] ), .OPOS(\RD_in[1] ), + .CE(Vout3), .CLK(C14M_c)); + Vout_0_ \Vout[0]_I ( .IOLDO(\Vout_c[0] ), .Vout0(Vout[0])); + Vout_0__MGIOL \Vout[0]_MGIOL ( .IOLDO(\Vout_c[0] ), .OPOS(\RD_in[0] ), + .CE(Vout3), .CLK(C14M_c)); + nDOE nDOE_I( .PADDO(nDOE_c), .nDOE(nDOE)); + Dout_7_ \Dout[7]_I ( .IOLDO(\Dout_c[7] ), .Dout7(Dout[7])); + Dout_7__MGIOL \Dout[7]_MGIOL ( .IOLDO(\Dout_c[7] ), .OPOS(\RD_in[7] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_6_ \Dout[6]_I ( .IOLDO(\Dout_c[6] ), .Dout6(Dout[6])); + Dout_6__MGIOL \Dout[6]_MGIOL ( .IOLDO(\Dout_c[6] ), .OPOS(\RD_in[6] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_5_ \Dout[5]_I ( .IOLDO(\Dout_c[5] ), .Dout5(Dout[5])); + Dout_5__MGIOL \Dout[5]_MGIOL ( .IOLDO(\Dout_c[5] ), .OPOS(\RD_in[5] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_4_ \Dout[4]_I ( .IOLDO(\Dout_c[4] ), .Dout4(Dout[4])); + Dout_4__MGIOL \Dout[4]_MGIOL ( .IOLDO(\Dout_c[4] ), .OPOS(\RD_in[4] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_3_ \Dout[3]_I ( .IOLDO(\Dout_c[3] ), .Dout3(Dout[3])); + Dout_3__MGIOL \Dout[3]_MGIOL ( .IOLDO(\Dout_c[3] ), .OPOS(\RD_in[3] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_2_ \Dout[2]_I ( .IOLDO(\Dout_c[2] ), .Dout2(Dout[2])); + Dout_2__MGIOL \Dout[2]_MGIOL ( .IOLDO(\Dout_c[2] ), .OPOS(\RD_in[2] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_1_ \Dout[1]_I ( .IOLDO(\Dout_c[1] ), .Dout1(Dout[1])); + Dout_1__MGIOL \Dout[1]_MGIOL ( .IOLDO(\Dout_c[1] ), .OPOS(\RD_in[1] ), + .CE(N_576_i), .CLK(C14M_c)); + Dout_0_ \Dout[0]_I ( .IOLDO(\Dout_c[0] ), .Dout0(Dout[0])); + Dout_0__MGIOL \Dout[0]_MGIOL ( .IOLDO(\Dout_c[0] ), .OPOS(\RD_in[0] ), + .CE(N_576_i), .CLK(C14M_c)); + Din_7_ \Din[7]_I ( .PADDI(\Din_c[7] ), .Din7(Din[7])); + Din_6_ \Din[6]_I ( .PADDI(\Din_c[6] ), .Din6(Din[6])); + Din_5_ \Din[5]_I ( .PADDI(\Din_c[5] ), .Din5(Din[5])); + Din_4_ \Din[4]_I ( .PADDI(\Din_c[4] ), .Din4(Din[4])); + Din_3_ \Din[3]_I ( .PADDI(\Din_c[3] ), .Din3(Din[3])); + Din_2_ \Din[2]_I ( .PADDI(\Din_c[2] ), .Din2(Din[2])); + Din_1_ \Din[1]_I ( .PADDI(\Din_c[1] ), .Din1(Din[1])); + Din_0_ \Din[0]_I ( .PADDI(\Din_c[0] ), .Din0(Din[0])); + Ain_7_ \Ain[7]_I ( .PADDI(\Ain_c[7] ), .Ain7(Ain[7])); + Ain_6_ \Ain[6]_I ( .PADDI(\Ain_c[6] ), .Ain6(Ain[6])); + Ain_5_ \Ain[5]_I ( .PADDI(\Ain_c[5] ), .Ain5(Ain[5])); + Ain_4_ \Ain[4]_I ( .PADDI(\Ain_c[4] ), .Ain4(Ain[4])); + Ain_3_ \Ain[3]_I ( .PADDI(\Ain_c[3] ), .Ain3(Ain[3])); + Ain_2_ \Ain[2]_I ( .PADDI(\Ain_c[2] ), .Ain2(Ain[2])); + Ain_1_ \Ain[1]_I ( .PADDI(\Ain_c[1] ), .Ain1(Ain[1])); + Ain_0_ \Ain[0]_I ( .PADDI(\Ain_c[0] ), .Ain0(Ain[0])); + nC07X nC07X_I( .PADDI(nC07X_c), .nC07X(nC07X)); + nEN80 nEN80_I( .PADDI(nEN80_c), .nEN80(nEN80)); + nWE80 nWE80_I( .PADDI(nWE80_c), .nWE80(nWE80)); + nWE nWE_I( .PADDI(nWE_c), .nWE(nWE)); + PHI1 PHI1_I( .PADDI(PHI1_c), .PHI1(PHI1)); + PHI1_MGIOL PHI1_MGIOL( .DI(PHI1_c), .CLK(C14M_c), .IN(PHI1reg)); + ufmefb_EFBInst_0 \ufmefb/EFBInst_0 ( .WBCLKI(C14M_c), .WBRSTI(wb_rst), + .WBCYCI(wb_cyc_stb), .WBSTBI(wb_cyc_stb), .WBWEI(wb_we), + .WBADRI0(\wb_adr[0] ), .WBADRI1(\wb_adr[1] ), .WBADRI2(\wb_adr[2] ), + .WBADRI3(\wb_adr[3] ), .WBADRI4(\wb_adr[4] ), .WBADRI5(\wb_adr[5] ), + .WBADRI6(\wb_adr[6] ), .WBADRI7(\wb_adr[7] ), .WBDATI0(\wb_dati[0] ), + .WBDATI1(\wb_dati[1] ), .WBDATI2(\wb_dati[2] ), .WBDATI3(\wb_dati[3] ), + .WBDATI4(\wb_dati[4] ), .WBDATI5(\wb_dati[5] ), .WBDATI6(\wb_dati[6] ), + .WBDATI7(\wb_dati[7] ), .WBDATO0(\wb_dato[0] ), .WBDATO1(\wb_dato[1] ), + .WBDATO2(\wb_dato[2] ), .WBDATO3(\wb_dato[3] ), .WBDATO4(\wb_dato[4] ), + .WBDATO5(\wb_dato[5] ), .WBDATO6(\wb_dato[6] ), .WBDATO7(\wb_dato[7] ), + .WBACKO(wb_ack)); + VHI VHI_INST( .Z(VCCI)); + PUR PUR_INST( .PUR(VCCI)); + GSR GSR_INST( .GSR(VCCI)); +endmodule + +module SLICE_0 ( input A1, DI1, CLK, output F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly; + + vmuxregsre \FS[0] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu2 \FS_cry_0[0] ( .A0(GNDI), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(GNDI), .S0(), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module vmuxregsre ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3DX INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module vcc ( output PWR1 ); + + VHI INST1( .Z(PWR1)); +endmodule + +module gnd ( output PWR0 ); + + VLO INST1( .Z(PWR0)); +endmodule + +module ccu2 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h000A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_1 ( input A0, DI0, CLK, FCI, output F0, Q0 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + vmuxregsre \FS[15] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + ccu20001 \FS_s_0[15] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(GNDI), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(), .CO1()); + + specify + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20001 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h5002; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_2 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[14] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[13] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[13] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module ccu20002 ( input A0, B0, C0, D0, A1, B1, C1, D1, CI, output S0, S1, CO1 ); + + CCU2D inst1( .CIN(CI), .A0(A0), .B0(B0), .C0(C0), .D0(D0), .A1(A1), .B1(B1), + .C1(C1), .D1(D1), .S0(S0), .S1(S1), .COUT(CO1)); + defparam inst1.INIT0 = 16'h300A; + defparam inst1.INIT1 = 16'h300A; + defparam inst1.INJECT1_0 = "NO"; + defparam inst1.INJECT1_1 = "NO"; +endmodule + +module SLICE_3 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[12] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[11] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[11] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_4 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[10] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[9] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[9] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_5 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[8] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[7] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[7] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_6 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[6] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[5] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[5] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_7 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[4] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[3] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[3] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_8 ( input A1, A0, DI1, DI0, CLK, FCI, output F0, Q0, F1, Q1, FCO ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + vmuxregsre \FS[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \FS[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + ccu20002 \FS_cry_0[1] ( .A0(A0), .B0(GNDI), .C0(GNDI), .D0(GNDI), .A1(A1), + .B1(GNDI), .C1(GNDI), .D1(GNDI), .CI(FCI), .S0(F0), .S1(F1), .CO1(FCO)); + + specify + (A1 => F1) = (0:0:0,0:0:0); + (A1 => FCO) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (A0 => F1) = (0:0:0,0:0:0); + (A0 => FCO) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + (FCI => F0) = (0:0:0,0:0:0); + (FCI => F1) = (0:0:0,0:0:0); + (FCI => FCO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module SLICE_9 ( input C1, B1, A1, D0, A0, DI0, CE, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut4 S_1( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40003 \CmdTout_3_0_a2[0] ( .A(A0), .B(GNDI), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre \CmdTout[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut4 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40003 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0055) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_10 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, LSR, CLK, + output F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, LSR_dly; + + lut40004 \CS_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40005 \CS_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre0006 \CS[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre0006 \CS[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40004 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAA6) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40005 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAA5) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module vmuxregsre0006 ( input D0, D1, SD, SP, CK, LSR, output Q ); + + FL1P3IY INST01( .D0(D0), .D1(D1), .SP(SP), .CK(CK), .SD(SD), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module SLICE_11 ( input D1, C1, B1, C0, B0, A0, DI0, LSR, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40007 \CS_RNO_0[2] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40008 \CS_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0006 \CS[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40007 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40008 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6A6A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_12 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40009 CmdBitbangMXO2_4_u_0_0_a2_0_1( .A(A1), .B(B1), .C(GNDI), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40010 CmdBitbangMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdBitbangMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40009 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0088) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40010 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_13 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40011 un1_CS_0_sqmuxa_0_0_a2_7( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40012 CmdExecMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdExecMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40011 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40012 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCE0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_14 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40013 CmdLEDGet_4_u_0_0_a2_0_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40014 CmdLEDGet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdLEDGet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40013 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40014 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF444) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_15 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40015 CmdLEDSet_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40016 CmdLEDSet_4_u_0_0_0( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdLEDSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40015 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40016 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_16 ( input D1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40017 CmdBitbangMXO2_4_u_0_0_a2_1( .A(A1), .B(B1), .C(GNDI), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 CmdRWMaskSet_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre CmdRWMaskSet( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40017 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40018 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0EA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_17 ( input D1, C1, B1, A1, D0, C0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40019 CmdSetRWBankFFLED_4_u_0_0_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40016 CmdSetRWBankFFLED_4_u_0_0_0( .A(A0), .B(GNDI), .C(C0), .D(D0), + .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre CmdSetRWBankFFLED( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40019 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_18 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40020 CmdSetRWBankFFLED_4_u_0_0_a2_1( .A(A1), .B(GNDI), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40018 CmdSetRWBankFFMXO2_4_u_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + vmuxregsre CmdSetRWBankFFMXO2( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), + .SP(CE_dly), .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40020 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_19 ( input D1, C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40021 \CmdTout_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40022 \CmdTout_RNO[1] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \CmdTout[2] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \CmdTout[1] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40021 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1450) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40022 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1144) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_20 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CLK, output F0, + Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly; + + lut40023 \S_RNII9DO1_2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40024 DOEEN_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre DOEEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40023 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40024 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_21 ( input C1, B1, A1, D0, B0, A0, DI0, CE, CLK, output F0, Q0, + F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40025 \RA_0io_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40026 LEDEN_RNO( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre LEDEN( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40025 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC8C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40026 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEE44) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_22 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40027 \RA_RNO[3] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40027 \RA_RNO[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RA[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RA[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40027 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_23 ( input D1, C1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40028 \RWBank_5_0[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40028 \RWBank_5_0[0] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RWBank[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40028 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_24 ( input C1, B1, A1, D0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 \RWBank_5_0[3] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40030 \RWBank_5_0[2] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + vmuxregsre \RWBank[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40029 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAEAE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40030 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBBAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_25 ( input C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40029 \RWBank_5_0[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40031 \RWBank_5_0[4] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \RWBank[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40031 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_26 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40032 \RWBank_5_0_0[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40033 \RWBank_5_0[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWBank[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWBank[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40032 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFAAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40033 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hBABA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_27 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40034 \RWMask_RNO[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 \RWMask_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40034 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h50FA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40035 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7272) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_28 ( input D1, B1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40036 \RWMask_RNO[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 \RWMask_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40036 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7722) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_29 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40037 \RWMask_RNO[5] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 \RWMask_RNO[4] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40037 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5F0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_30 ( input D1, C1, A1, C0, B0, A0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40038 \RWMask_RNO[7] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40035 \RWMask_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \RWMask[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \RWMask[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40038 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF5A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_31 ( input C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40039 nDOE_pad_RNO( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40040 RWSel_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre RWSel( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40039 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF7F7) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40040 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_32 ( input D1, C1, B1, A1, C0, A0, DI0, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly; + + lut40041 Ready_0_sqmuxa_0_a2_6_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40042 Ready_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre Ready( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40041 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40042 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFAFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_33 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output + F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40043 \S_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40044 \S_s_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \S[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \S[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40043 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2022) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40044 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFDC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_34 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CLK, output + F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly; + + lut40045 \S_RNO[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40046 \S_RNO[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \S[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \S[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40045 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2232) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40046 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2231) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_35 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40047 \wb_adr_RNO[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40048 \wb_adr_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_adr[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40047 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40048 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_36 ( input C1, B1, C0, B0, DI1, DI0, CE, CLK, output F0, Q0, F1, + Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40049 \wb_adr_RNO[3] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40049 \wb_adr_RNO[2] ( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre \wb_adr[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40049 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC0C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_37 ( input C1, B1, A1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, + Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40050 \wb_adr_RNO[5] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40051 \wb_adr_RNO[4] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40050 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA3A3) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40051 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_38 ( input C1, B1, D0, C0, B0, DI1, DI0, CE, CLK, output F0, Q0, + F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40049 \wb_adr_RNO[7] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40052 \wb_adr_RNO[6] ( .A(GNDI), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_adr[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_adr[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40052 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCF03) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_39 ( input D1, C1, B1, A1, C0, B0, A0, DI0, CE, CLK, output F0, + Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly; + + lut40053 wb_cyc_stb_RNO_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40054 wb_cyc_stb_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre wb_cyc_stb( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40053 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0302) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40054 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF8F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_40 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40055 \wb_dati_7_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40056 \wb_dati_7_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[1] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[0] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40055 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40056 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_41 ( input D1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40057 \wb_dati_7_0[3] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40058 \wb_dati_7_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[3] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[2] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40057 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40058 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_42 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI1, DI0, CE, CLK, + output F0, Q0, F1, Q1 ); + wire VCCI, GNDI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40058 \wb_dati_7_0[5] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40059 \wb_dati_7_0[4] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre \wb_dati[5] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[4] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40059 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_43 ( input D1, C1, B1, A1, D0, C0, A0, DI1, DI0, CE, CLK, output + F0, Q0, F1, Q1 ); + wire GNDI, VCCI, DI1_dly, CLK_dly, DI0_dly, CE_dly; + + lut40060 \wb_dati_7_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40061 \wb_dati_7_0[6] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + vmuxregsre \wb_dati[7] ( .D0(VCCI), .D1(DI1_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q1)); + vcc DRIVEVCC( .PWR1(VCCI)); + vmuxregsre \wb_dati[6] ( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + (CLK => Q1) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI1, 0:0:0, 0:0:0,,,, CLK_dly, DI1_dly); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40060 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40061 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_44 ( input D1, C1, A1, D0, C0, B0, A0, DI0, CE, LSR, CLK, output + F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, CE_dly, LSR_dly; + + lut40062 wb_req_RNO_1( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40063 wb_req_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre0006 wb_req( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40062 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40063 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_45 ( input C1, B1, C0, B0, DI0, LSR, CLK, output F0, Q0, F1 ); + wire GNDI, VCCI, DI0_dly, CLK_dly, LSR_dly; + + lut40064 \un1_LEDEN13_2_i_o2[0] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40065 wb_rst8_0_a2( .A(GNDI), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + vmuxregsre0006 wb_rst( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(VCCI), + .CK(CLK_dly), .LSR(LSR_dly), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge LSR, 0:0:0); + $width (negedge LSR, 0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40064 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFCFC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40065 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0303) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_46 ( input D1, C1, B1, A1, D0, C0, B0, A0, DI0, CE, CLK, output + F0, Q0, F1 ); + wire VCCI, GNDI, DI0_dly, CLK_dly, CE_dly; + + lut40066 wb_we_RNO_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40067 wb_we_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + vmuxregsre wb_we( .D0(VCCI), .D1(DI0_dly), .SD(VCCI), .SP(CE_dly), + .CK(CLK_dly), .LSR(GNDI), .Q(Q0)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + (CLK => Q0) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI0, 0:0:0, 0:0:0,,,, CLK_dly, DI0_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module lut40066 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2BBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40067 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAAEA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_47 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40068 DQMH_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40069 \S_RNII9DO1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40068 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40069 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_48 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40070 Vout3_0_a2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40071 nCAS_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40070 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40071 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h88F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_49 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40072 un1_CS_0_sqmuxa_0_0_a2_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40073 un1_CS_0_sqmuxa_0_0_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40072 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40073 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF8F0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_50 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40074 \wb_dati_7_0_a2_0_2[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40075 \wb_dati_7_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40074 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h080A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40075 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA02) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_51 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40076 CKE_6_iv_i_0_1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40077 CKE_6_iv_i_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40076 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0FAC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40077 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCECC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_52 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40078 \un1_LEDEN13_2_i_a2_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40079 \un1_LEDEN13_2_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40078 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2300) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40079 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_53 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40080 \un1_wb_adr_0_sqmuxa_2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40081 wb_we_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40080 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h67EF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40081 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0501) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_54 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40082 un1_CS_0_sqmuxa_0_0_a2_15( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40083 un1_CS_0_sqmuxa_0_0_o2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40082 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40083 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF0F8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_55 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40084 nCS_6_u_i_o2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40085 un1_nCS61_1_0_a2_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40084 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFAB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40085 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_56 ( input D1, C1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40086 \wb_dati_7_0_a2_5[1] ( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40087 \wb_dati_7_0_a2_6[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40086 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h000A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40087 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_57 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40088 \un1_LEDEN13_2_i_a2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40089 \S_RNII9DO1_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40088 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40089 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEFFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_58 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40090 \wb_dati_7_0_2[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40091 \wb_dati_7_0_2_RNO[3] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40090 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40091 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_59 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40092 DQML_0io_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40093 DQML_0io_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40092 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7737) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40093 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_60 ( input D1, C1, B1, A1, D0, C0, A0, output F0, F1 ); + wire GNDI; + + lut40094 \wb_adr_RNO_1[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40095 \wb_adr_RNO_3[1] ( .A(A0), .B(GNDI), .C(C0), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40094 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2A08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40095 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_61 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40096 \wb_dati_7_0_a2_2_0[1] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40097 \FS_RNIOD6E_1[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40096 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hC000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40097 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_62 ( input D1, C1, B1, A1, D0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40098 \wb_adr_RNO_0[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40099 \wb_adr_RNO_2[1] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40098 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40099 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8877) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_63 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40069 \un1_LEDEN13_2_i_o2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40100 \FS_RNI9FGA[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40100 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_64 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40101 \FS_RNI6JJA[8] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40102 \un1_RWMask_0_sqmuxa_1_i_0_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40101 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7F7F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40102 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_65 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40103 \wb_dati_7_0_a2_0_0[6] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 \wb_dati_7_0_0_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40103 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0202) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40104 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_66 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40105 \FS_RNIJ9MH[14] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40106 wb_we_RNO_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40105 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40106 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h080C) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_67 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40107 wb_reqc_1( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40108 wb_reqc_1_RNIRU4M1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40107 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40108 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_68 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40109 \wb_dati_7_0_0[3] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40110 \FS_RNIOD6E_0[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40109 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40110 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_69 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40111 \RA_42_0[10] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40112 \RA_42_0_RNO[10] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40111 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF4) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40112 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_70 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40113 \wb_dati_7_0_a2[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40114 \FS_RNIOD6E[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40113 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00C8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40114 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h6A00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_71 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40115 nRWE_r_0_RNO( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40116 \S_RNII9DO1_3[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40115 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00DF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40116 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_72 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40117 Ready_0_sqmuxa_0_a2_6_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40118 \FS_RNI5OOF1[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40117 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40118 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_73 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40119 \wb_adr_7_0_a2_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40120 \FS_RNIK5632[15] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40119 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00D0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40120 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0002) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_74 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40121 \wb_dati_7_0_a2_5[4] ( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40104 \wb_dati_7_0_a2_5_RNIC22J[4] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40121 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0C00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_75 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40110 nCS_6_u_i_a2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut4 nCS_6_u_i_a2_4_RNI3A062( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_76 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40122 nCS_6_u_i_o2_0( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40123 nCS_6_u_i_a2_4_RNICJKD2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40122 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFAA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40123 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0040) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_77 ( input D1, C1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40124 un1_CS_0_sqmuxa_0_0_a2_10( .A(A1), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40125 un1_CS_0_sqmuxa_0_0_2_RNIQS7F( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40124 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00A0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40125 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0007) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_78 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40122 nCAS_s_i_o2( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40126 nCAS_0io_RNO( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40126 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hABBB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_79 ( input D1, C1, B1, A1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40127 nCS_6_u_i_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40128 nCS_0io_RNO( .A(A0), .B(B0), .C(GNDI), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40127 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0122) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40128 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1111) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_80 ( input D1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40129 nRAS_2_iv_0_a2_0( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40130 nRAS_2_iv_i( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40129 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1144) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40130 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h5151) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_81 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40131 un1_CS_0_sqmuxa_0_0_a2_1_6( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40132 un1_CS_0_sqmuxa_0_0_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40131 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40132 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_82 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40133 un1_CS_0_sqmuxa_0_0_a2_5( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40134 un1_CS_0_sqmuxa_0_0_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40133 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h070F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40134 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_83 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40135 nCS_6_u_i_a2_1_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40136 nCS_6_u_i_1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40135 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40136 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECCC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_84 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40137 \wb_dati_7_0_a2[6] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40138 \wb_dati_7_0_1[6] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40137 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8008) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40138 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFEFA) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_85 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40139 \wb_adr_7_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40140 \wb_adr_7_0_4[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40139 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hCC08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40140 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFFE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_86 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40141 \wb_dati_7_0_a2_2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40142 \un1_LEDEN_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40141 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0100) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40142 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_87 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40143 un1_CS_0_sqmuxa_0_0_a2_4_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40144 un1_CS_0_sqmuxa_0_0_a2_4( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40143 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h2000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40144 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_88 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40145 \FS_RNI9Q57[13] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40146 \wb_dati_7_0_o2_0[2] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40145 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF55) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40146 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFF80) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_89 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40122 \wb_adr_7_0_o2[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40147 \wb_adr_7_0_a2_2[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40147 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_90 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40148 \wb_dati_7_0_o2[1] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40149 \wb_dati_7_0_a2[1] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40148 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0810) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40149 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_91 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40150 un1_CS_0_sqmuxa_0_0_a2_2_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40151 un1_CS_0_sqmuxa_0_0_a2_2( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40150 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40151 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_92 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40152 \wb_adr_7_0_a2_0_0[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40153 \wb_adr_7_0_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40152 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4450) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40153 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_93 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40154 un1_CS_0_sqmuxa_0_0_a2_1_2( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40098 un1_CS_0_sqmuxa_0_0_a2_1_4( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40154 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_94 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40155 un1_CS_0_sqmuxa_0_0_a2_3_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40093 un1_CS_0_sqmuxa_0_0_a2_3_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40155 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_95 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40156 wb_we_RNO_4( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40157 wb_we_RNO_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40156 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40157 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFF8) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_96 ( input D1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40158 \RA_42_i_o2[8] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40159 \RA_0io_RNO[8] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40158 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40159 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0B08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_97 ( input D1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40160 \wb_dati_7_0_a2_1[0] ( .A(A1), .B(GNDI), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40161 CKE_6_iv_i_a2_3( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40160 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA00) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40161 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0800) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_98 ( input D1, C1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40162 un1_CS_0_sqmuxa_0_0_a2_16( .A(GNDI), .B(B1), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40163 un1_CS_0_sqmuxa_0_0_a2_4_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40162 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0003) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40163 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0400) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_99 ( input D1, B1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40164 un1_CS_0_sqmuxa_0_0_a2_12( .A(GNDI), .B(B1), .C(GNDI), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40143 un1_CS_0_sqmuxa_0_0_a2_2_2( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40164 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0033) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_100 ( input C1, B1, A1, D0, C0, B0, output F0, F1 ); + wire GNDI; + + lut40165 un1_CS_0_sqmuxa_0_0_a2_17( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40166 CmdSetRWBankFFMXO2_4_u_0_0_a2_0_0( .A(GNDI), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40165 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40166 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h00C0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_101 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40167 wb_reqc_1_RNIEO5C1( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40168 \S_RNII9DO1_1[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40167 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0001) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40168 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hD821) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_102 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40169 \S_s_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40170 \BA_0io_RNO[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40169 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8F0A) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40170 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0020) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_103 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40156 \RA_0io_RNO[11] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40134 wb_req_RNO_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_104 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40171 \wb_dati_7_0_a2_3[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40172 \wb_adr_7_0_a2_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40171 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40172 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hA0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_105 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40173 \un1_LEDEN_0_sqmuxa_1_i_a2_0_1[0] ( .A(A1), .B(B1), .C(C1), .D(D1), + .Z(F1)); + lut40070 \wb_dati_7_0_a2_1[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40173 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_106 ( input C1, B1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40174 \S_RNINI6S[1] ( .A(GNDI), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40175 CKE_6_iv_i_0_1_RNO( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40174 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h3F3F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40175 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1515) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_107 ( input D1, C1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40176 \S_r_i_o2[1] ( .A(GNDI), .B(GNDI), .C(C1), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40023 \BA_0io_RNO[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40176 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0FFF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_108 ( input C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40177 \wb_adr_7_0_a2_5_0[0] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40178 \wb_dati_7_0_a2[7] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40177 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h1010) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40178 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8200) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_109 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40179 \wb_dati_7_0_0[7] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40179 \wb_dati_7_0_0[1] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40179 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hF888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_110 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40180 \RA_0io_RNO[9] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40181 CmdBitbangMXO2_RNI8CSO1( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40180 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0203) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40181 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h000B) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_111 ( input D1, B1, A1, D0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40182 \RA_42_3_0[5] ( .A(A1), .B(B1), .C(GNDI), .D(D1), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40183 \RA_0io_RNO[4] ( .A(A0), .B(B0), .C(GNDI), .D(D0), .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40182 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAABB) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40183 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAA88) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_112 ( input D1, C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40184 nCS_6_u_i_a2_0( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40185 \RA_0io_RNO[6] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40184 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0004) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40185 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hE0E0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_113 ( input C1, B1, A1, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40025 \RA_0io_RNO[2] ( .A(A1), .B(B1), .C(C1), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40025 \RA_0io_RNO[7] ( .A(A0), .B(B0), .C(C0), .D(GNDI), .Z(F0)); + + specify + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module SLICE_114 ( input D1, C1, B1, A1, D0, C0, B0, A0, output F0, F1 ); + + lut40186 \wb_dati_7_0_0[4] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40187 \un1_RWMask_0_sqmuxa_1_i_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40186 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEAC0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40187 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hECA0) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_115 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40188 nWE80_pad_RNI3ICD( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40189 nRWE_r_0( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40188 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hEEEE) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40189 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h0F08) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_116 ( input B1, A1, D0, C0, B0, A0, output F0, F1 ); + wire GNDI; + + lut40190 \wb_adr_7_0_o2_2[0] ( .A(A1), .B(B1), .C(GNDI), .D(GNDI), .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40191 \wb_dati_7_0_a2_1_0[0] ( .A(A0), .B(B0), .C(C0), .D(D0), .Z(F0)); + + specify + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40190 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h7777) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40191 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h4080) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_117 ( input D1, C1, B1, A1, C0, A0, output F0, F1 ); + wire GNDI; + + lut40192 \RWBank_5_0_o2[0] ( .A(A1), .B(B1), .C(C1), .D(D1), .Z(F1)); + lut40193 LED_pad_RNO( .A(A0), .B(GNDI), .C(C0), .D(GNDI), .Z(F0)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B1 => F1) = (0:0:0,0:0:0); + (A1 => F1) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40192 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hFFEC) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40193 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'hAFAF) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_118 ( input D1, C1, B0, A0, output F0, F1 ); + wire GNDI; + + lut40194 un1_CS_0_sqmuxa_0_0_a2_11( .A(GNDI), .B(GNDI), .C(C1), .D(D1), + .Z(F1)); + gnd DRIVEGND( .PWR0(GNDI)); + lut40195 un1_CS_0_sqmuxa_0_0_a2_13( .A(A0), .B(B0), .C(GNDI), .D(GNDI), + .Z(F0)); + + specify + (D1 => F1) = (0:0:0,0:0:0); + (C1 => F1) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40194 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h000F) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module lut40195 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8888) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module SLICE_119 ( input D0, C0, B0, A0, output F0 ); + + lut40196 Ready_0_sqmuxa_0_a2_6_a2_2_0( .A(A0), .B(B0), .C(C0), .D(D0), + .Z(F0)); + + specify + (D0 => F0) = (0:0:0,0:0:0); + (C0 => F0) = (0:0:0,0:0:0); + (B0 => F0) = (0:0:0,0:0:0); + (A0 => F0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module lut40196 ( input A, B, C, D, output Z ); + + ROM16X1A #(16'h8000) INST10( .AD0(A), .AD1(B), .AD2(C), .AD3(D), .DO0(Z)); +endmodule + +module RD_0_ ( output PADDI, input PADDT, PADDO, inout RD0 ); + + xo2iobuf \RD_pad[0] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD0), .PADI(RD0)); + + specify + (PADDT => RD0) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD0) = (0:0:0,0:0:0); + (RD0 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD0, 0:0:0); + $width (negedge RD0, 0:0:0); + endspecify + +endmodule + +module xo2iobuf ( input I, T, output Z, PAD, input PADI ); + + IB INST1( .I(PADI), .O(Z)); + OBW INST2( .I(I), .T(T), .O(PAD)); +endmodule + +module LED ( input PADDO, output LED ); + + xo2iobuf0197 LED_pad( .I(PADDO), .PAD(LED)); + + specify + (PADDO => LED) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0197 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module C14M ( output PADDI, input C14M ); + + xo2iobuf0198 C14M_pad( .Z(PADDI), .PAD(C14M)); + + specify + (C14M => PADDI) = (0:0:0,0:0:0); + $width (posedge C14M, 0:0:0); + $width (negedge C14M, 0:0:0); + endspecify + +endmodule + +module xo2iobuf0198 ( output Z, input PAD ); + + IB INST1( .I(PAD), .O(Z)); +endmodule + +module DQMH ( input IOLDO, output DQMH ); + + xo2iobuf0197 DQMH_pad( .I(IOLDO), .PAD(DQMH)); + + specify + (IOLDO => DQMH) = (0:0:0,0:0:0); + endspecify + +endmodule + +module DQMH_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre DQMH_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre ( input D0, SP, CK, LSR, output Q ); + + FD1P3BX INST01( .D(D0), .SP(SP), .CK(CK), .PD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module DQML ( input IOLDO, output DQML ); + + xo2iobuf0197 DQML_pad( .I(IOLDO), .PAD(DQML)); + + specify + (IOLDO => DQML) = (0:0:0,0:0:0); + endspecify + +endmodule + +module DQML_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre DQML_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RD_7_ ( output PADDI, input PADDT, PADDO, inout RD7 ); + + xo2iobuf \RD_pad[7] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD7), .PADI(RD7)); + + specify + (PADDT => RD7) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD7) = (0:0:0,0:0:0); + (RD7 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD7, 0:0:0); + $width (negedge RD7, 0:0:0); + endspecify + +endmodule + +module RD_6_ ( output PADDI, input PADDT, PADDO, inout RD6 ); + + xo2iobuf \RD_pad[6] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD6), .PADI(RD6)); + + specify + (PADDT => RD6) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD6) = (0:0:0,0:0:0); + (RD6 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD6, 0:0:0); + $width (negedge RD6, 0:0:0); + endspecify + +endmodule + +module RD_5_ ( output PADDI, input PADDT, PADDO, inout RD5 ); + + xo2iobuf \RD_pad[5] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD5), .PADI(RD5)); + + specify + (PADDT => RD5) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD5) = (0:0:0,0:0:0); + (RD5 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD5, 0:0:0); + $width (negedge RD5, 0:0:0); + endspecify + +endmodule + +module RD_4_ ( output PADDI, input PADDT, PADDO, inout RD4 ); + + xo2iobuf \RD_pad[4] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD4), .PADI(RD4)); + + specify + (PADDT => RD4) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD4) = (0:0:0,0:0:0); + (RD4 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD4, 0:0:0); + $width (negedge RD4, 0:0:0); + endspecify + +endmodule + +module RD_3_ ( output PADDI, input PADDT, PADDO, inout RD3 ); + + xo2iobuf \RD_pad[3] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD3), .PADI(RD3)); + + specify + (PADDT => RD3) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD3) = (0:0:0,0:0:0); + (RD3 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD3, 0:0:0); + $width (negedge RD3, 0:0:0); + endspecify + +endmodule + +module RD_2_ ( output PADDI, input PADDT, PADDO, inout RD2 ); + + xo2iobuf \RD_pad[2] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD2), .PADI(RD2)); + + specify + (PADDT => RD2) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD2) = (0:0:0,0:0:0); + (RD2 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD2, 0:0:0); + $width (negedge RD2, 0:0:0); + endspecify + +endmodule + +module RD_1_ ( output PADDI, input PADDT, PADDO, inout RD1 ); + + xo2iobuf \RD_pad[1] ( .I(PADDO), .T(PADDT), .Z(PADDI), .PAD(RD1), .PADI(RD1)); + + specify + (PADDT => RD1) = (0:0:0,0:0:0,0:0:0,0:0:0,0:0:0,0:0:0); + (PADDO => RD1) = (0:0:0,0:0:0); + (RD1 => PADDI) = (0:0:0,0:0:0); + $width (posedge RD1, 0:0:0); + $width (negedge RD1, 0:0:0); + endspecify + +endmodule + +module RA_11_ ( input IOLDO, output RA11 ); + + xo2iobuf0197 \RA_pad[11] ( .I(IOLDO), .PAD(RA11)); + + specify + (IOLDO => RA11) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_11__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0199 \RA_0io[11] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0199 ( input D0, SP, CK, LSR, output Q ); + + FD1P3DX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module RA_10_ ( input IOLDO, output RA10 ); + + xo2iobuf0197 \RA_pad[10] ( .I(IOLDO), .PAD(RA10)); + + specify + (IOLDO => RA10) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_10__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0199 \RA_0io[10] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_9_ ( input IOLDO, output RA9 ); + + xo2iobuf0197 \RA_pad[9] ( .I(IOLDO), .PAD(RA9)); + + specify + (IOLDO => RA9) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_9__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0199 \RA_0io[9] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_8_ ( input IOLDO, output RA8 ); + + xo2iobuf0197 \RA_pad[8] ( .I(IOLDO), .PAD(RA8)); + + specify + (IOLDO => RA8) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_8__MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0199 \RA_0io[8] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_7_ ( input IOLDO, output RA7 ); + + xo2iobuf0197 \RA_pad[7] ( .I(IOLDO), .PAD(RA7)); + + specify + (IOLDO => RA7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \RA_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_6_ ( input IOLDO, output RA6 ); + + xo2iobuf0197 \RA_pad[6] ( .I(IOLDO), .PAD(RA6)); + + specify + (IOLDO => RA6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \RA_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_5_ ( input IOLDO, output RA5 ); + + xo2iobuf0197 \RA_pad[5] ( .I(IOLDO), .PAD(RA5)); + + specify + (IOLDO => RA5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \RA_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_4_ ( input IOLDO, output RA4 ); + + xo2iobuf0197 \RA_pad[4] ( .I(IOLDO), .PAD(RA4)); + + specify + (IOLDO => RA4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \RA_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_3_ ( input PADDO, output RA3 ); + + xo2iobuf0197 \RA_pad[3] ( .I(PADDO), .PAD(RA3)); + + specify + (PADDO => RA3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2_ ( input IOLDO, output RA2 ); + + xo2iobuf0197 \RA_pad[2] ( .I(IOLDO), .PAD(RA2)); + + specify + (IOLDO => RA2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \RA_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_1_ ( input IOLDO, output RA1 ); + + xo2iobuf0197 \RA_pad[1] ( .I(IOLDO), .PAD(RA1)); + + specify + (IOLDO => RA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module RA_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \RA_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_dly), + .LSR(GNDI), .Q(IOLDO)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module RA_0_ ( input PADDO, output RA0 ); + + xo2iobuf0197 \RA_pad[0] ( .I(PADDO), .PAD(RA0)); + + specify + (PADDO => RA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_1_ ( input IOLDO, output BA1 ); + + xo2iobuf0197 \BA_pad[1] ( .I(IOLDO), .PAD(BA1)); + + specify + (IOLDO => BA1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_1__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); + wire VCCI, OPOS_dly, CLK_dly, LSR_dly; + + mfflsre0200 \BA_0io[1] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_dly), .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module mfflsre0200 ( input D0, SP, CK, LSR, output Q ); + + FD1P3IX INST01( .D(D0), .SP(SP), .CK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module BA_0_ ( input IOLDO, output BA0 ); + + xo2iobuf0197 \BA_pad[0] ( .I(IOLDO), .PAD(BA0)); + + specify + (IOLDO => BA0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module BA_0__MGIOL ( output IOLDO, input OPOS, LSR, CLK ); + wire VCCI, OPOS_dly, CLK_dly, LSR_dly; + + mfflsre0200 \BA_0io[0] ( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), + .LSR(LSR_dly), .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (posedge CLK, LSR, 0:0:0, 0:0:0,,,, CLK_dly, LSR_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRWE ( input IOLDO, output nRWE ); + + xo2iobuf0197 nRWE_pad( .I(IOLDO), .PAD(nRWE)); + + specify + (IOLDO => nRWE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRWE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nRWE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nCAS ( input IOLDO, output nCAS ); + + xo2iobuf0197 nCAS_pad( .I(IOLDO), .PAD(nCAS)); + + specify + (IOLDO => nCAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nCAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nCAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nRAS ( input IOLDO, output nRAS ); + + xo2iobuf0197 nRAS_pad( .I(IOLDO), .PAD(nRAS)); + + specify + (IOLDO => nRAS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nRAS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nRAS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nCS ( input IOLDO, output nCS ); + + xo2iobuf0197 nCS_pad( .I(IOLDO), .PAD(nCS)); + + specify + (IOLDO => nCS) = (0:0:0,0:0:0); + endspecify + +endmodule + +module nCS_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre nCS_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module CKE ( input IOLDO, output CKE ); + + xo2iobuf0197 CKE_pad( .I(IOLDO), .PAD(CKE)); + + specify + (IOLDO => CKE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module CKE_MGIOL ( output IOLDO, input OPOS, CLK ); + wire VCCI, GNDI, OPOS_dly, CLK_dly; + + mfflsre0199 CKE_0io( .D0(OPOS_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IOLDO)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $setuphold (posedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module nVOE ( input PADDO, output nVOE ); + + xo2iobuf0197 nVOE_pad( .I(PADDO), .PAD(nVOE)); + + specify + (PADDO => nVOE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_7_ ( input IOLDO, output Vout7 ); + + xo2iobuf0197 \Vout_pad[7] ( .I(IOLDO), .PAD(Vout7)); + + specify + (IOLDO => Vout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Vout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module inverter ( input I, output Z ); + + INV INST1( .A(I), .Z(Z)); +endmodule + +module Vout_6_ ( input IOLDO, output Vout6 ); + + xo2iobuf0197 \Vout_pad[6] ( .I(IOLDO), .PAD(Vout6)); + + specify + (IOLDO => Vout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Vout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_5_ ( input IOLDO, output Vout5 ); + + xo2iobuf0197 \Vout_pad[5] ( .I(IOLDO), .PAD(Vout5)); + + specify + (IOLDO => Vout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Vout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_4_ ( input IOLDO, output Vout4 ); + + xo2iobuf0197 \Vout_pad[4] ( .I(IOLDO), .PAD(Vout4)); + + specify + (IOLDO => Vout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Vout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_3_ ( input IOLDO, output Vout3 ); + + xo2iobuf0197 \Vout_pad[3] ( .I(IOLDO), .PAD(Vout3)); + + specify + (IOLDO => Vout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Vout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_2_ ( input IOLDO, output Vout2 ); + + xo2iobuf0197 \Vout_pad[2] ( .I(IOLDO), .PAD(Vout2)); + + specify + (IOLDO => Vout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Vout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_1_ ( input IOLDO, output Vout1 ); + + xo2iobuf0197 \Vout_pad[1] ( .I(IOLDO), .PAD(Vout1)); + + specify + (IOLDO => Vout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Vout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Vout_0_ ( input IOLDO, output Vout0 ); + + xo2iobuf0197 \Vout_pad[0] ( .I(IOLDO), .PAD(Vout0)); + + specify + (IOLDO => Vout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Vout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Vout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module nDOE ( input PADDO, output nDOE ); + + xo2iobuf0197 nDOE_pad( .I(PADDO), .PAD(nDOE)); + + specify + (PADDO => nDOE) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_7_ ( input IOLDO, output Dout7 ); + + xo2iobuf0201 \Dout_pad[7] ( .I(IOLDO), .PAD(Dout7)); + + specify + (IOLDO => Dout7) = (0:0:0,0:0:0); + endspecify + +endmodule + +module xo2iobuf0201 ( input I, output PAD ); + + OB INST5( .I(I), .O(PAD)); +endmodule + +module Dout_7__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Dout_0io[7] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_6_ ( input IOLDO, output Dout6 ); + + xo2iobuf0201 \Dout_pad[6] ( .I(IOLDO), .PAD(Dout6)); + + specify + (IOLDO => Dout6) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_6__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Dout_0io[6] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_5_ ( input IOLDO, output Dout5 ); + + xo2iobuf0201 \Dout_pad[5] ( .I(IOLDO), .PAD(Dout5)); + + specify + (IOLDO => Dout5) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_5__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Dout_0io[5] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_4_ ( input IOLDO, output Dout4 ); + + xo2iobuf0201 \Dout_pad[4] ( .I(IOLDO), .PAD(Dout4)); + + specify + (IOLDO => Dout4) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_4__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Dout_0io[4] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_3_ ( input IOLDO, output Dout3 ); + + xo2iobuf0201 \Dout_pad[3] ( .I(IOLDO), .PAD(Dout3)); + + specify + (IOLDO => Dout3) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_3__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Dout_0io[3] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_2_ ( input IOLDO, output Dout2 ); + + xo2iobuf0201 \Dout_pad[2] ( .I(IOLDO), .PAD(Dout2)); + + specify + (IOLDO => Dout2) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_2__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Dout_0io[2] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_1_ ( input IOLDO, output Dout1 ); + + xo2iobuf0201 \Dout_pad[1] ( .I(IOLDO), .PAD(Dout1)); + + specify + (IOLDO => Dout1) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_1__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Dout_0io[1] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Dout_0_ ( input IOLDO, output Dout0 ); + + xo2iobuf0201 \Dout_pad[0] ( .I(IOLDO), .PAD(Dout0)); + + specify + (IOLDO => Dout0) = (0:0:0,0:0:0); + endspecify + +endmodule + +module Dout_0__MGIOL ( output IOLDO, input OPOS, CE, CLK ); + wire CLK_NOTIN, GNDI, OPOS_dly, CLK_dly, CE_dly; + + mfflsre0199 \Dout_0io[0] ( .D0(OPOS_dly), .SP(CE_dly), .CK(CLK_NOTIN), + .LSR(GNDI), .Q(IOLDO)); + inverter CLK_INVERTERIN( .I(CLK_dly), .Z(CLK_NOTIN)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IOLDO) = (0:0:0,0:0:0); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + $setuphold (negedge CLK, OPOS, 0:0:0, 0:0:0,,,, CLK_dly, OPOS_dly); + $setuphold (negedge CLK, CE, 0:0:0, 0:0:0,,,, CLK_dly, CE_dly); + endspecify + +endmodule + +module Din_7_ ( output PADDI, input Din7 ); + + xo2iobuf0198 \Din_pad[7] ( .Z(PADDI), .PAD(Din7)); + + specify + (Din7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din7, 0:0:0); + $width (negedge Din7, 0:0:0); + endspecify + +endmodule + +module Din_6_ ( output PADDI, input Din6 ); + + xo2iobuf0198 \Din_pad[6] ( .Z(PADDI), .PAD(Din6)); + + specify + (Din6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din6, 0:0:0); + $width (negedge Din6, 0:0:0); + endspecify + +endmodule + +module Din_5_ ( output PADDI, input Din5 ); + + xo2iobuf0198 \Din_pad[5] ( .Z(PADDI), .PAD(Din5)); + + specify + (Din5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din5, 0:0:0); + $width (negedge Din5, 0:0:0); + endspecify + +endmodule + +module Din_4_ ( output PADDI, input Din4 ); + + xo2iobuf0198 \Din_pad[4] ( .Z(PADDI), .PAD(Din4)); + + specify + (Din4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din4, 0:0:0); + $width (negedge Din4, 0:0:0); + endspecify + +endmodule + +module Din_3_ ( output PADDI, input Din3 ); + + xo2iobuf0198 \Din_pad[3] ( .Z(PADDI), .PAD(Din3)); + + specify + (Din3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din3, 0:0:0); + $width (negedge Din3, 0:0:0); + endspecify + +endmodule + +module Din_2_ ( output PADDI, input Din2 ); + + xo2iobuf0198 \Din_pad[2] ( .Z(PADDI), .PAD(Din2)); + + specify + (Din2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din2, 0:0:0); + $width (negedge Din2, 0:0:0); + endspecify + +endmodule + +module Din_1_ ( output PADDI, input Din1 ); + + xo2iobuf0198 \Din_pad[1] ( .Z(PADDI), .PAD(Din1)); + + specify + (Din1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din1, 0:0:0); + $width (negedge Din1, 0:0:0); + endspecify + +endmodule + +module Din_0_ ( output PADDI, input Din0 ); + + xo2iobuf0198 \Din_pad[0] ( .Z(PADDI), .PAD(Din0)); + + specify + (Din0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Din0, 0:0:0); + $width (negedge Din0, 0:0:0); + endspecify + +endmodule + +module Ain_7_ ( output PADDI, input Ain7 ); + + xo2iobuf0198 \Ain_pad[7] ( .Z(PADDI), .PAD(Ain7)); + + specify + (Ain7 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain7, 0:0:0); + $width (negedge Ain7, 0:0:0); + endspecify + +endmodule + +module Ain_6_ ( output PADDI, input Ain6 ); + + xo2iobuf0198 \Ain_pad[6] ( .Z(PADDI), .PAD(Ain6)); + + specify + (Ain6 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain6, 0:0:0); + $width (negedge Ain6, 0:0:0); + endspecify + +endmodule + +module Ain_5_ ( output PADDI, input Ain5 ); + + xo2iobuf0198 \Ain_pad[5] ( .Z(PADDI), .PAD(Ain5)); + + specify + (Ain5 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain5, 0:0:0); + $width (negedge Ain5, 0:0:0); + endspecify + +endmodule + +module Ain_4_ ( output PADDI, input Ain4 ); + + xo2iobuf0198 \Ain_pad[4] ( .Z(PADDI), .PAD(Ain4)); + + specify + (Ain4 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain4, 0:0:0); + $width (negedge Ain4, 0:0:0); + endspecify + +endmodule + +module Ain_3_ ( output PADDI, input Ain3 ); + + xo2iobuf0198 \Ain_pad[3] ( .Z(PADDI), .PAD(Ain3)); + + specify + (Ain3 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain3, 0:0:0); + $width (negedge Ain3, 0:0:0); + endspecify + +endmodule + +module Ain_2_ ( output PADDI, input Ain2 ); + + xo2iobuf0198 \Ain_pad[2] ( .Z(PADDI), .PAD(Ain2)); + + specify + (Ain2 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain2, 0:0:0); + $width (negedge Ain2, 0:0:0); + endspecify + +endmodule + +module Ain_1_ ( output PADDI, input Ain1 ); + + xo2iobuf0198 \Ain_pad[1] ( .Z(PADDI), .PAD(Ain1)); + + specify + (Ain1 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain1, 0:0:0); + $width (negedge Ain1, 0:0:0); + endspecify + +endmodule + +module Ain_0_ ( output PADDI, input Ain0 ); + + xo2iobuf0198 \Ain_pad[0] ( .Z(PADDI), .PAD(Ain0)); + + specify + (Ain0 => PADDI) = (0:0:0,0:0:0); + $width (posedge Ain0, 0:0:0); + $width (negedge Ain0, 0:0:0); + endspecify + +endmodule + +module nC07X ( output PADDI, input nC07X ); + + xo2iobuf0198 nC07X_pad( .Z(PADDI), .PAD(nC07X)); + + specify + (nC07X => PADDI) = (0:0:0,0:0:0); + $width (posedge nC07X, 0:0:0); + $width (negedge nC07X, 0:0:0); + endspecify + +endmodule + +module nEN80 ( output PADDI, input nEN80 ); + + xo2iobuf0198 nEN80_pad( .Z(PADDI), .PAD(nEN80)); + + specify + (nEN80 => PADDI) = (0:0:0,0:0:0); + $width (posedge nEN80, 0:0:0); + $width (negedge nEN80, 0:0:0); + endspecify + +endmodule + +module nWE80 ( output PADDI, input nWE80 ); + + xo2iobuf0198 nWE80_pad( .Z(PADDI), .PAD(nWE80)); + + specify + (nWE80 => PADDI) = (0:0:0,0:0:0); + $width (posedge nWE80, 0:0:0); + $width (negedge nWE80, 0:0:0); + endspecify + +endmodule + +module nWE ( output PADDI, input nWE ); + + xo2iobuf0198 nWE_pad( .Z(PADDI), .PAD(nWE)); + + specify + (nWE => PADDI) = (0:0:0,0:0:0); + $width (posedge nWE, 0:0:0); + $width (negedge nWE, 0:0:0); + endspecify + +endmodule + +module PHI1 ( output PADDI, input PHI1 ); + + xo2iobuf0198 PHI1_pad( .Z(PADDI), .PAD(PHI1)); + + specify + (PHI1 => PADDI) = (0:0:0,0:0:0); + $width (posedge PHI1, 0:0:0); + $width (negedge PHI1, 0:0:0); + endspecify + +endmodule + +module PHI1_MGIOL ( input DI, CLK, output IN ); + wire VCCI, GNDI, DI_dly, CLK_dly; + + smuxlregsre PHI1reg_0io( .D0(DI_dly), .SP(VCCI), .CK(CLK_dly), .LSR(GNDI), + .Q(IN)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); + + specify + (CLK => IN) = (0:0:0,0:0:0); + $setuphold (posedge CLK, DI, 0:0:0, 0:0:0,,,, CLK_dly, DI_dly); + $width (posedge CLK, 0:0:0); + $width (negedge CLK, 0:0:0); + endspecify + +endmodule + +module smuxlregsre ( input D0, SP, CK, LSR, output Q ); + + IFS1P3DX INST01( .D(D0), .SP(SP), .SCLK(CK), .CD(LSR), .Q(Q)); + defparam INST01.GSR = "DISABLED"; +endmodule + +module ufmefb_EFBInst_0 ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, + WBADRI1, WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, + WBDATI1, WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output + WBDATO0, WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, + WBACKO ); + wire VCCI, GNDI; + + EFB_B \ufmefb/EFBInst_0_EFB ( .WBCLKI(WBCLKI), .WBRSTI(WBRSTI), + .WBCYCI(WBCYCI), .WBSTBI(WBSTBI), .WBWEI(WBWEI), .WBADRI0(WBADRI0), + .WBADRI1(WBADRI1), .WBADRI2(WBADRI2), .WBADRI3(WBADRI3), .WBADRI4(WBADRI4), + .WBADRI5(WBADRI5), .WBADRI6(WBADRI6), .WBADRI7(WBADRI7), .WBDATI0(WBDATI0), + .WBDATI1(WBDATI1), .WBDATI2(WBDATI2), .WBDATI3(WBDATI3), .WBDATI4(WBDATI4), + .WBDATI5(WBDATI5), .WBDATI6(WBDATI6), .WBDATI7(WBDATI7), .WBDATO0(WBDATO0), + .WBDATO1(WBDATO1), .WBDATO2(WBDATO2), .WBDATO3(WBDATO3), .WBDATO4(WBDATO4), + .WBDATO5(WBDATO5), .WBDATO6(WBDATO6), .WBDATO7(WBDATO7), .WBACKO(WBACKO), + .WBCUFMIRQ(), .UFMSN(VCCI), .CFGWAKE(), .CFGSTDBY(), .I2C1SCLI(GNDI), + .I2C1SCLO(), .I2C1SCLOEN(), .I2C1SDAI(GNDI), .I2C1SDAO(), .I2C1SDAOEN(), + .I2C2SCLI(GNDI), .I2C2SCLO(), .I2C2SCLOEN(), .I2C2SDAI(GNDI), .I2C2SDAO(), + .I2C2SDAOEN(), .I2C1IRQO(), .I2C2IRQO(), .SPISCKI(GNDI), .SPISCKO(), + .SPISCKEN(), .SPIMISOI(GNDI), .SPIMISOO(), .SPIMISOEN(), .SPIMOSII(GNDI), + .SPIMOSIO(), .SPIMOSIEN(), .SPIMCSN0(), .SPIMCSN1(), .SPIMCSN2(), + .SPIMCSN3(), .SPIMCSN4(), .SPIMCSN5(), .SPIMCSN6(), .SPIMCSN7(), + .SPICSNEN(), .SPISCSN(GNDI), .SPIIRQO(), .TCCLKI(GNDI), .TCRSTN(GNDI), + .TCIC(GNDI), .TCINT(), .TCOC(), .PLLCLKO(), .PLLRSTO(), .PLL0STBO(), + .PLL1STBO(), .PLLWEO(), .PLLADRO0(), .PLLADRO1(), .PLLADRO2(), .PLLADRO3(), + .PLLADRO4(), .PLLDATO0(), .PLLDATO1(), .PLLDATO2(), .PLLDATO3(), + .PLLDATO4(), .PLLDATO5(), .PLLDATO6(), .PLLDATO7(), .PLL0DATI0(GNDI), + .PLL0DATI1(GNDI), .PLL0DATI2(GNDI), .PLL0DATI3(GNDI), .PLL0DATI4(GNDI), + .PLL0DATI5(GNDI), .PLL0DATI6(GNDI), .PLL0DATI7(GNDI), .PLL0ACKI(GNDI), + .PLL1DATI0(GNDI), .PLL1DATI1(GNDI), .PLL1DATI2(GNDI), .PLL1DATI3(GNDI), + .PLL1DATI4(GNDI), .PLL1DATI5(GNDI), .PLL1DATI6(GNDI), .PLL1DATI7(GNDI), + .PLL1ACKI(GNDI)); + vcc DRIVEVCC( .PWR1(VCCI)); + gnd DRIVEGND( .PWR0(GNDI)); +endmodule + +module EFB_B ( input WBCLKI, WBRSTI, WBCYCI, WBSTBI, WBWEI, WBADRI0, WBADRI1, + WBADRI2, WBADRI3, WBADRI4, WBADRI5, WBADRI6, WBADRI7, WBDATI0, WBDATI1, + WBDATI2, WBDATI3, WBDATI4, WBDATI5, WBDATI6, WBDATI7, output WBDATO0, + WBDATO1, WBDATO2, WBDATO3, WBDATO4, WBDATO5, WBDATO6, WBDATO7, WBACKO, + WBCUFMIRQ, input UFMSN, output CFGWAKE, CFGSTDBY, input I2C1SCLI, output + I2C1SCLO, I2C1SCLOEN, input I2C1SDAI, output I2C1SDAO, I2C1SDAOEN, input + I2C2SCLI, output I2C2SCLO, I2C2SCLOEN, input I2C2SDAI, output I2C2SDAO, + I2C2SDAOEN, I2C1IRQO, I2C2IRQO, input SPISCKI, output SPISCKO, SPISCKEN, + input SPIMISOI, output SPIMISOO, SPIMISOEN, input SPIMOSII, output + SPIMOSIO, SPIMOSIEN, SPIMCSN0, SPIMCSN1, SPIMCSN2, SPIMCSN3, SPIMCSN4, + SPIMCSN5, SPIMCSN6, SPIMCSN7, SPICSNEN, input SPISCSN, output SPIIRQO, + input TCCLKI, TCRSTN, TCIC, output TCINT, TCOC, PLLCLKO, PLLRSTO, PLL0STBO, + PLL1STBO, PLLWEO, PLLADRO0, PLLADRO1, PLLADRO2, PLLADRO3, PLLADRO4, + PLLDATO0, PLLDATO1, PLLDATO2, PLLDATO3, PLLDATO4, PLLDATO5, PLLDATO6, + PLLDATO7, input PLL0DATI0, PLL0DATI1, PLL0DATI2, PLL0DATI3, PLL0DATI4, + PLL0DATI5, PLL0DATI6, PLL0DATI7, PLL0ACKI, PLL1DATI0, PLL1DATI1, PLL1DATI2, + PLL1DATI3, PLL1DATI4, PLL1DATI5, PLL1DATI6, PLL1DATI7, PLL1ACKI ); + wire WBCLKI_buf, WBRSTI_buf, WBCYCI_buf, WBSTBI_buf, WBWEI_buf, + WBADRI7_buf, WBADRI6_buf, WBADRI5_buf, WBADRI4_buf, WBADRI3_buf, + WBADRI2_buf, WBADRI1_buf, WBADRI0_buf, WBDATI7_buf, WBDATI6_buf, + WBDATI5_buf, WBDATI4_buf, WBDATI3_buf, WBDATI2_buf, WBDATI1_buf, + WBDATI0_buf, PLL0DATI7_buf, PLL0DATI6_buf, PLL0DATI5_buf, + PLL0DATI4_buf, PLL0DATI3_buf, PLL0DATI2_buf, PLL0DATI1_buf, + PLL0DATI0_buf, PLL0ACKI_buf, PLL1DATI7_buf, PLL1DATI6_buf, + PLL1DATI5_buf, PLL1DATI4_buf, PLL1DATI3_buf, PLL1DATI2_buf, + PLL1DATI1_buf, PLL1DATI0_buf, PLL1ACKI_buf, I2C1SCLI_buf, + I2C1SDAI_buf, I2C2SCLI_buf, I2C2SDAI_buf, SPISCKI_buf, SPIMISOI_buf, + SPIMOSII_buf, SPISCSN_buf, TCCLKI_buf, TCRSTN_buf, TCIC_buf, + UFMSN_buf, WBDATO7_buf, WBDATO6_buf, WBDATO5_buf, WBDATO4_buf, + WBDATO3_buf, WBDATO2_buf, WBDATO1_buf, WBDATO0_buf, WBACKO_buf, + PLLCLKO_buf, PLLRSTO_buf, PLL0STBO_buf, PLL1STBO_buf, PLLWEO_buf, + PLLADRO4_buf, PLLADRO3_buf, PLLADRO2_buf, PLLADRO1_buf, PLLADRO0_buf, + PLLDATO7_buf, PLLDATO6_buf, PLLDATO5_buf, PLLDATO4_buf, PLLDATO3_buf, + PLLDATO2_buf, PLLDATO1_buf, PLLDATO0_buf, I2C1SCLO_buf, + I2C1SCLOEN_buf, I2C1SDAO_buf, I2C1SDAOEN_buf, I2C2SCLO_buf, + I2C2SCLOEN_buf, I2C2SDAO_buf, I2C2SDAOEN_buf, I2C1IRQO_buf, + I2C2IRQO_buf, SPISCKO_buf, SPISCKEN_buf, SPIMISOO_buf, SPIMISOEN_buf, + SPIMOSIO_buf, SPIMOSIEN_buf, SPIMCSN0_buf, SPIMCSN1_buf, SPIMCSN2_buf, + SPIMCSN3_buf, SPIMCSN4_buf, SPIMCSN5_buf, SPIMCSN6_buf, SPIMCSN7_buf, + SPICSNEN_buf, SPIIRQO_buf, TCINT_buf, TCOC_buf, WBCUFMIRQ_buf, + CFGWAKE_buf, CFGSTDBY_buf; + + EFB INST10( .WBCLKI(WBCLKI_buf), .WBRSTI(WBRSTI_buf), .WBCYCI(WBCYCI_buf), + .WBSTBI(WBSTBI_buf), .WBWEI(WBWEI_buf), .WBADRI7(WBADRI7_buf), + .WBADRI6(WBADRI6_buf), .WBADRI5(WBADRI5_buf), .WBADRI4(WBADRI4_buf), + .WBADRI3(WBADRI3_buf), .WBADRI2(WBADRI2_buf), .WBADRI1(WBADRI1_buf), + .WBADRI0(WBADRI0_buf), .WBDATI7(WBDATI7_buf), .WBDATI6(WBDATI6_buf), + .WBDATI5(WBDATI5_buf), .WBDATI4(WBDATI4_buf), .WBDATI3(WBDATI3_buf), + .WBDATI2(WBDATI2_buf), .WBDATI1(WBDATI1_buf), .WBDATI0(WBDATI0_buf), + .PLL0DATI7(PLL0DATI7_buf), .PLL0DATI6(PLL0DATI6_buf), + .PLL0DATI5(PLL0DATI5_buf), .PLL0DATI4(PLL0DATI4_buf), + .PLL0DATI3(PLL0DATI3_buf), .PLL0DATI2(PLL0DATI2_buf), + .PLL0DATI1(PLL0DATI1_buf), .PLL0DATI0(PLL0DATI0_buf), + .PLL0ACKI(PLL0ACKI_buf), .PLL1DATI7(PLL1DATI7_buf), + .PLL1DATI6(PLL1DATI6_buf), .PLL1DATI5(PLL1DATI5_buf), + .PLL1DATI4(PLL1DATI4_buf), .PLL1DATI3(PLL1DATI3_buf), + .PLL1DATI2(PLL1DATI2_buf), .PLL1DATI1(PLL1DATI1_buf), + .PLL1DATI0(PLL1DATI0_buf), .PLL1ACKI(PLL1ACKI_buf), + .I2C1SCLI(I2C1SCLI_buf), .I2C1SDAI(I2C1SDAI_buf), .I2C2SCLI(I2C2SCLI_buf), + .I2C2SDAI(I2C2SDAI_buf), .SPISCKI(SPISCKI_buf), .SPIMISOI(SPIMISOI_buf), + .SPIMOSII(SPIMOSII_buf), .SPISCSN(SPISCSN_buf), .TCCLKI(TCCLKI_buf), + .TCRSTN(TCRSTN_buf), .TCIC(TCIC_buf), .UFMSN(UFMSN_buf), + .WBDATO7(WBDATO7_buf), .WBDATO6(WBDATO6_buf), .WBDATO5(WBDATO5_buf), + .WBDATO4(WBDATO4_buf), .WBDATO3(WBDATO3_buf), .WBDATO2(WBDATO2_buf), + .WBDATO1(WBDATO1_buf), .WBDATO0(WBDATO0_buf), .WBACKO(WBACKO_buf), + .PLLCLKO(PLLCLKO_buf), .PLLRSTO(PLLRSTO_buf), .PLL0STBO(PLL0STBO_buf), + .PLL1STBO(PLL1STBO_buf), .PLLWEO(PLLWEO_buf), .PLLADRO4(PLLADRO4_buf), + .PLLADRO3(PLLADRO3_buf), .PLLADRO2(PLLADRO2_buf), .PLLADRO1(PLLADRO1_buf), + .PLLADRO0(PLLADRO0_buf), .PLLDATO7(PLLDATO7_buf), .PLLDATO6(PLLDATO6_buf), + .PLLDATO5(PLLDATO5_buf), .PLLDATO4(PLLDATO4_buf), .PLLDATO3(PLLDATO3_buf), + .PLLDATO2(PLLDATO2_buf), .PLLDATO1(PLLDATO1_buf), .PLLDATO0(PLLDATO0_buf), + .I2C1SCLO(I2C1SCLO_buf), .I2C1SCLOEN(I2C1SCLOEN_buf), + .I2C1SDAO(I2C1SDAO_buf), .I2C1SDAOEN(I2C1SDAOEN_buf), + .I2C2SCLO(I2C2SCLO_buf), .I2C2SCLOEN(I2C2SCLOEN_buf), + .I2C2SDAO(I2C2SDAO_buf), .I2C2SDAOEN(I2C2SDAOEN_buf), + .I2C1IRQO(I2C1IRQO_buf), .I2C2IRQO(I2C2IRQO_buf), .SPISCKO(SPISCKO_buf), + .SPISCKEN(SPISCKEN_buf), .SPIMISOO(SPIMISOO_buf), + .SPIMISOEN(SPIMISOEN_buf), .SPIMOSIO(SPIMOSIO_buf), + .SPIMOSIEN(SPIMOSIEN_buf), .SPIMCSN0(SPIMCSN0_buf), + .SPIMCSN1(SPIMCSN1_buf), .SPIMCSN2(SPIMCSN2_buf), .SPIMCSN3(SPIMCSN3_buf), + .SPIMCSN4(SPIMCSN4_buf), .SPIMCSN5(SPIMCSN5_buf), .SPIMCSN6(SPIMCSN6_buf), + .SPIMCSN7(SPIMCSN7_buf), .SPICSNEN(SPICSNEN_buf), .SPIIRQO(SPIIRQO_buf), + .TCINT(TCINT_buf), .TCOC(TCOC_buf), .WBCUFMIRQ(WBCUFMIRQ_buf), + .CFGWAKE(CFGWAKE_buf), .CFGSTDBY(CFGSTDBY_buf)); + defparam INST10.DEV_DENSITY = "640L"; + defparam INST10.EFB_I2C1 = "DISABLED"; + defparam INST10.EFB_I2C2 = "DISABLED"; + defparam INST10.EFB_SPI = "DISABLED"; + defparam INST10.EFB_TC = "DISABLED"; + defparam INST10.EFB_TC_PORTMODE = "WB"; + defparam INST10.EFB_UFM = "ENABLED"; + defparam INST10.EFB_WB_CLK_FREQ = "14.4"; + defparam INST10.GSR = "ENABLED"; + defparam INST10.I2C1_ADDRESSING = "7BIT"; + defparam INST10.I2C1_BUS_PERF = "100kHz"; + defparam INST10.I2C1_CLK_DIVIDER = 1; + defparam INST10.I2C1_GEN_CALL = "DISABLED"; + defparam INST10.I2C1_SLAVE_ADDR = "0b1000001"; + defparam INST10.I2C1_WAKEUP = "DISABLED"; + defparam INST10.I2C2_ADDRESSING = "7BIT"; + defparam INST10.I2C2_BUS_PERF = "100kHz"; + defparam INST10.I2C2_CLK_DIVIDER = 1; + defparam INST10.I2C2_GEN_CALL = "DISABLED"; + defparam INST10.I2C2_SLAVE_ADDR = "0b1000010"; + defparam INST10.I2C2_WAKEUP = "DISABLED"; + defparam INST10.SPI_CLK_DIVIDER = 1; + defparam INST10.SPI_CLK_INV = "DISABLED"; + defparam INST10.SPI_INTR_RXOVR = "DISABLED"; + defparam INST10.SPI_INTR_RXRDY = "DISABLED"; + defparam INST10.SPI_INTR_TXOVR = "DISABLED"; + defparam INST10.SPI_INTR_TXRDY = "DISABLED"; + defparam INST10.SPI_LSB_FIRST = "DISABLED"; + defparam INST10.SPI_MODE = "MASTER"; + defparam INST10.SPI_PHASE_ADJ = "DISABLED"; + defparam INST10.SPI_SLAVE_HANDSHAKE = "DISABLED"; + defparam INST10.SPI_WAKEUP = "DISABLED"; + defparam INST10.TC_CCLK_SEL = 1; + defparam INST10.TC_ICAPTURE = "DISABLED"; + defparam INST10.TC_ICR_INT = "OFF"; + defparam INST10.TC_MODE = "CTCM"; + defparam INST10.TC_OCR_INT = "OFF"; + defparam INST10.TC_OCR_SET = 32767; + defparam INST10.TC_OC_MODE = "TOGGLE"; + defparam INST10.TC_OVERFLOW = "DISABLED"; + defparam INST10.TC_OV_INT = "OFF"; + defparam INST10.TC_RESETN = "ENABLED"; + defparam INST10.TC_SCLK_SEL = "PCLOCK"; + defparam INST10.TC_TOP_SEL = "OFF"; + defparam INST10.TC_TOP_SET = 65535; + defparam INST10.UFM_INIT_ALL_ZEROS = "DISABLED"; + defparam INST10.UFM_INIT_FILE_FORMAT = "HEX"; + defparam INST10.UFM_INIT_FILE_NAME = "../RAM2E-LCMXO2.mem"; + defparam INST10.UFM_INIT_PAGES = 1; + defparam INST10.UFM_INIT_START_PAGE = 190; + EFB_Buffer_Block INST20( .WBCLKIin(WBCLKI), .WBCLKIout(WBCLKI_buf), + .WBRSTIin(WBRSTI), .WBRSTIout(WBRSTI_buf), .WBCYCIin(WBCYCI), + .WBCYCIout(WBCYCI_buf), .WBSTBIin(WBSTBI), .WBSTBIout(WBSTBI_buf), + .WBWEIin(WBWEI), .WBWEIout(WBWEI_buf), .WBADRI7in(WBADRI7), + .WBADRI7out(WBADRI7_buf), .WBADRI6in(WBADRI6), .WBADRI6out(WBADRI6_buf), + .WBADRI5in(WBADRI5), .WBADRI5out(WBADRI5_buf), .WBADRI4in(WBADRI4), + .WBADRI4out(WBADRI4_buf), .WBADRI3in(WBADRI3), .WBADRI3out(WBADRI3_buf), + .WBADRI2in(WBADRI2), .WBADRI2out(WBADRI2_buf), .WBADRI1in(WBADRI1), + .WBADRI1out(WBADRI1_buf), .WBADRI0in(WBADRI0), .WBADRI0out(WBADRI0_buf), + .WBDATI7in(WBDATI7), .WBDATI7out(WBDATI7_buf), .WBDATI6in(WBDATI6), + .WBDATI6out(WBDATI6_buf), .WBDATI5in(WBDATI5), .WBDATI5out(WBDATI5_buf), + .WBDATI4in(WBDATI4), .WBDATI4out(WBDATI4_buf), .WBDATI3in(WBDATI3), + .WBDATI3out(WBDATI3_buf), .WBDATI2in(WBDATI2), .WBDATI2out(WBDATI2_buf), + .WBDATI1in(WBDATI1), .WBDATI1out(WBDATI1_buf), .WBDATI0in(WBDATI0), + .WBDATI0out(WBDATI0_buf), .PLL0DATI7in(PLL0DATI7), + .PLL0DATI7out(PLL0DATI7_buf), .PLL0DATI6in(PLL0DATI6), + .PLL0DATI6out(PLL0DATI6_buf), .PLL0DATI5in(PLL0DATI5), + .PLL0DATI5out(PLL0DATI5_buf), .PLL0DATI4in(PLL0DATI4), + .PLL0DATI4out(PLL0DATI4_buf), .PLL0DATI3in(PLL0DATI3), + .PLL0DATI3out(PLL0DATI3_buf), .PLL0DATI2in(PLL0DATI2), + .PLL0DATI2out(PLL0DATI2_buf), .PLL0DATI1in(PLL0DATI1), + .PLL0DATI1out(PLL0DATI1_buf), .PLL0DATI0in(PLL0DATI0), + .PLL0DATI0out(PLL0DATI0_buf), .PLL0ACKIin(PLL0ACKI), + .PLL0ACKIout(PLL0ACKI_buf), .PLL1DATI7in(PLL1DATI7), + .PLL1DATI7out(PLL1DATI7_buf), .PLL1DATI6in(PLL1DATI6), + .PLL1DATI6out(PLL1DATI6_buf), .PLL1DATI5in(PLL1DATI5), + .PLL1DATI5out(PLL1DATI5_buf), .PLL1DATI4in(PLL1DATI4), + .PLL1DATI4out(PLL1DATI4_buf), .PLL1DATI3in(PLL1DATI3), + .PLL1DATI3out(PLL1DATI3_buf), .PLL1DATI2in(PLL1DATI2), + .PLL1DATI2out(PLL1DATI2_buf), .PLL1DATI1in(PLL1DATI1), + .PLL1DATI1out(PLL1DATI1_buf), .PLL1DATI0in(PLL1DATI0), + .PLL1DATI0out(PLL1DATI0_buf), .PLL1ACKIin(PLL1ACKI), + .PLL1ACKIout(PLL1ACKI_buf), .I2C1SCLIin(I2C1SCLI), + .I2C1SCLIout(I2C1SCLI_buf), .I2C1SDAIin(I2C1SDAI), + .I2C1SDAIout(I2C1SDAI_buf), .I2C2SCLIin(I2C2SCLI), + .I2C2SCLIout(I2C2SCLI_buf), .I2C2SDAIin(I2C2SDAI), + .I2C2SDAIout(I2C2SDAI_buf), .SPISCKIin(SPISCKI), .SPISCKIout(SPISCKI_buf), + .SPIMISOIin(SPIMISOI), .SPIMISOIout(SPIMISOI_buf), .SPIMOSIIin(SPIMOSII), + .SPIMOSIIout(SPIMOSII_buf), .SPISCSNin(SPISCSN), .SPISCSNout(SPISCSN_buf), + .TCCLKIin(TCCLKI), .TCCLKIout(TCCLKI_buf), .TCRSTNin(TCRSTN), + .TCRSTNout(TCRSTN_buf), .TCICin(TCIC), .TCICout(TCIC_buf), .UFMSNin(UFMSN), + .UFMSNout(UFMSN_buf), .WBDATO7out(WBDATO7), .WBDATO7in(WBDATO7_buf), + .WBDATO6out(WBDATO6), .WBDATO6in(WBDATO6_buf), .WBDATO5out(WBDATO5), + .WBDATO5in(WBDATO5_buf), .WBDATO4out(WBDATO4), .WBDATO4in(WBDATO4_buf), + .WBDATO3out(WBDATO3), .WBDATO3in(WBDATO3_buf), .WBDATO2out(WBDATO2), + .WBDATO2in(WBDATO2_buf), .WBDATO1out(WBDATO1), .WBDATO1in(WBDATO1_buf), + .WBDATO0out(WBDATO0), .WBDATO0in(WBDATO0_buf), .WBACKOout(WBACKO), + .WBACKOin(WBACKO_buf), .PLLCLKOout(PLLCLKO), .PLLCLKOin(PLLCLKO_buf), + .PLLRSTOout(PLLRSTO), .PLLRSTOin(PLLRSTO_buf), .PLL0STBOout(PLL0STBO), + .PLL0STBOin(PLL0STBO_buf), .PLL1STBOout(PLL1STBO), + .PLL1STBOin(PLL1STBO_buf), .PLLWEOout(PLLWEO), .PLLWEOin(PLLWEO_buf), + .PLLADRO4out(PLLADRO4), .PLLADRO4in(PLLADRO4_buf), .PLLADRO3out(PLLADRO3), + .PLLADRO3in(PLLADRO3_buf), .PLLADRO2out(PLLADRO2), + .PLLADRO2in(PLLADRO2_buf), .PLLADRO1out(PLLADRO1), + .PLLADRO1in(PLLADRO1_buf), .PLLADRO0out(PLLADRO0), + .PLLADRO0in(PLLADRO0_buf), .PLLDATO7out(PLLDATO7), + .PLLDATO7in(PLLDATO7_buf), .PLLDATO6out(PLLDATO6), + .PLLDATO6in(PLLDATO6_buf), .PLLDATO5out(PLLDATO5), + .PLLDATO5in(PLLDATO5_buf), .PLLDATO4out(PLLDATO4), + .PLLDATO4in(PLLDATO4_buf), .PLLDATO3out(PLLDATO3), + .PLLDATO3in(PLLDATO3_buf), .PLLDATO2out(PLLDATO2), + .PLLDATO2in(PLLDATO2_buf), .PLLDATO1out(PLLDATO1), + .PLLDATO1in(PLLDATO1_buf), .PLLDATO0out(PLLDATO0), + .PLLDATO0in(PLLDATO0_buf), .I2C1SCLOout(I2C1SCLO), + .I2C1SCLOin(I2C1SCLO_buf), .I2C1SCLOENout(I2C1SCLOEN), + .I2C1SCLOENin(I2C1SCLOEN_buf), .I2C1SDAOout(I2C1SDAO), + .I2C1SDAOin(I2C1SDAO_buf), .I2C1SDAOENout(I2C1SDAOEN), + .I2C1SDAOENin(I2C1SDAOEN_buf), .I2C2SCLOout(I2C2SCLO), + .I2C2SCLOin(I2C2SCLO_buf), .I2C2SCLOENout(I2C2SCLOEN), + .I2C2SCLOENin(I2C2SCLOEN_buf), .I2C2SDAOout(I2C2SDAO), + .I2C2SDAOin(I2C2SDAO_buf), .I2C2SDAOENout(I2C2SDAOEN), + .I2C2SDAOENin(I2C2SDAOEN_buf), .I2C1IRQOout(I2C1IRQO), + .I2C1IRQOin(I2C1IRQO_buf), .I2C2IRQOout(I2C2IRQO), + .I2C2IRQOin(I2C2IRQO_buf), .SPISCKOout(SPISCKO), .SPISCKOin(SPISCKO_buf), + .SPISCKENout(SPISCKEN), .SPISCKENin(SPISCKEN_buf), .SPIMISOOout(SPIMISOO), + .SPIMISOOin(SPIMISOO_buf), .SPIMISOENout(SPIMISOEN), + .SPIMISOENin(SPIMISOEN_buf), .SPIMOSIOout(SPIMOSIO), + .SPIMOSIOin(SPIMOSIO_buf), .SPIMOSIENout(SPIMOSIEN), + .SPIMOSIENin(SPIMOSIEN_buf), .SPIMCSN0out(SPIMCSN0), + .SPIMCSN0in(SPIMCSN0_buf), .SPIMCSN1out(SPIMCSN1), + .SPIMCSN1in(SPIMCSN1_buf), .SPIMCSN2out(SPIMCSN2), + .SPIMCSN2in(SPIMCSN2_buf), .SPIMCSN3out(SPIMCSN3), + .SPIMCSN3in(SPIMCSN3_buf), .SPIMCSN4out(SPIMCSN4), + .SPIMCSN4in(SPIMCSN4_buf), .SPIMCSN5out(SPIMCSN5), + .SPIMCSN5in(SPIMCSN5_buf), .SPIMCSN6out(SPIMCSN6), + .SPIMCSN6in(SPIMCSN6_buf), .SPIMCSN7out(SPIMCSN7), + .SPIMCSN7in(SPIMCSN7_buf), .SPICSNENout(SPICSNEN), + .SPICSNENin(SPICSNEN_buf), .SPIIRQOout(SPIIRQO), .SPIIRQOin(SPIIRQO_buf), + .TCINTout(TCINT), .TCINTin(TCINT_buf), .TCOCout(TCOC), .TCOCin(TCOC_buf), + .WBCUFMIRQout(WBCUFMIRQ), .WBCUFMIRQin(WBCUFMIRQ_buf), + .CFGWAKEout(CFGWAKE), .CFGWAKEin(CFGWAKE_buf), .CFGSTDBYout(CFGSTDBY), + .CFGSTDBYin(CFGSTDBY_buf)); +endmodule + +module EFB_Buffer_Block ( input WBCLKIin, output WBCLKIout, input WBRSTIin, + output WBRSTIout, input WBCYCIin, output WBCYCIout, input WBSTBIin, + output WBSTBIout, input WBWEIin, output WBWEIout, input WBADRI7in, output + WBADRI7out, input WBADRI6in, output WBADRI6out, input WBADRI5in, output + WBADRI5out, input WBADRI4in, output WBADRI4out, input WBADRI3in, output + WBADRI3out, input WBADRI2in, output WBADRI2out, input WBADRI1in, output + WBADRI1out, input WBADRI0in, output WBADRI0out, input WBDATI7in, output + WBDATI7out, input WBDATI6in, output WBDATI6out, input WBDATI5in, output + WBDATI5out, input WBDATI4in, output WBDATI4out, input WBDATI3in, output + WBDATI3out, input WBDATI2in, output WBDATI2out, input WBDATI1in, output + WBDATI1out, input WBDATI0in, output WBDATI0out, input PLL0DATI7in, output + PLL0DATI7out, input PLL0DATI6in, output PLL0DATI6out, input PLL0DATI5in, + output PLL0DATI5out, input PLL0DATI4in, output PLL0DATI4out, input + PLL0DATI3in, output PLL0DATI3out, input PLL0DATI2in, output PLL0DATI2out, + input PLL0DATI1in, output PLL0DATI1out, input PLL0DATI0in, output + PLL0DATI0out, input PLL0ACKIin, output PLL0ACKIout, input PLL1DATI7in, + output PLL1DATI7out, input PLL1DATI6in, output PLL1DATI6out, input + PLL1DATI5in, output PLL1DATI5out, input PLL1DATI4in, output PLL1DATI4out, + input PLL1DATI3in, output PLL1DATI3out, input PLL1DATI2in, output + PLL1DATI2out, input PLL1DATI1in, output PLL1DATI1out, input PLL1DATI0in, + output PLL1DATI0out, input PLL1ACKIin, output PLL1ACKIout, input + I2C1SCLIin, output I2C1SCLIout, input I2C1SDAIin, output I2C1SDAIout, + input I2C2SCLIin, output I2C2SCLIout, input I2C2SDAIin, output I2C2SDAIout, + input SPISCKIin, output SPISCKIout, input SPIMISOIin, output SPIMISOIout, + input SPIMOSIIin, output SPIMOSIIout, input SPISCSNin, output SPISCSNout, + input TCCLKIin, output TCCLKIout, input TCRSTNin, output TCRSTNout, input + TCICin, output TCICout, input UFMSNin, output UFMSNout, WBDATO7out, input + WBDATO7in, output WBDATO6out, input WBDATO6in, output WBDATO5out, input + WBDATO5in, output WBDATO4out, input WBDATO4in, output WBDATO3out, input + WBDATO3in, output WBDATO2out, input WBDATO2in, output WBDATO1out, input + WBDATO1in, output WBDATO0out, input WBDATO0in, output WBACKOout, input + WBACKOin, output PLLCLKOout, input PLLCLKOin, output PLLRSTOout, input + PLLRSTOin, output PLL0STBOout, input PLL0STBOin, output PLL1STBOout, + input PLL1STBOin, output PLLWEOout, input PLLWEOin, output PLLADRO4out, + input PLLADRO4in, output PLLADRO3out, input PLLADRO3in, output PLLADRO2out, + input PLLADRO2in, output PLLADRO1out, input PLLADRO1in, output PLLADRO0out, + input PLLADRO0in, output PLLDATO7out, input PLLDATO7in, output PLLDATO6out, + input PLLDATO6in, output PLLDATO5out, input PLLDATO5in, output PLLDATO4out, + input PLLDATO4in, output PLLDATO3out, input PLLDATO3in, output PLLDATO2out, + input PLLDATO2in, output PLLDATO1out, input PLLDATO1in, output PLLDATO0out, + input PLLDATO0in, output I2C1SCLOout, input I2C1SCLOin, output + I2C1SCLOENout, input I2C1SCLOENin, output I2C1SDAOout, input I2C1SDAOin, + output I2C1SDAOENout, input I2C1SDAOENin, output I2C2SCLOout, input + I2C2SCLOin, output I2C2SCLOENout, input I2C2SCLOENin, output I2C2SDAOout, + input I2C2SDAOin, output I2C2SDAOENout, input I2C2SDAOENin, output + I2C1IRQOout, input I2C1IRQOin, output I2C2IRQOout, input I2C2IRQOin, + output SPISCKOout, input SPISCKOin, output SPISCKENout, input SPISCKENin, + output SPIMISOOout, input SPIMISOOin, output SPIMISOENout, input + SPIMISOENin, output SPIMOSIOout, input SPIMOSIOin, output SPIMOSIENout, + input SPIMOSIENin, output SPIMCSN0out, input SPIMCSN0in, output + SPIMCSN1out, input SPIMCSN1in, output SPIMCSN2out, input SPIMCSN2in, + output SPIMCSN3out, input SPIMCSN3in, output SPIMCSN4out, input SPIMCSN4in, + output SPIMCSN5out, input SPIMCSN5in, output SPIMCSN6out, input SPIMCSN6in, + output SPIMCSN7out, input SPIMCSN7in, output SPICSNENout, input SPICSNENin, + output SPIIRQOout, input SPIIRQOin, output TCINTout, input TCINTin, + output TCOCout, input TCOCin, output WBCUFMIRQout, input WBCUFMIRQin, + output CFGWAKEout, input CFGWAKEin, output CFGSTDBYout, input CFGSTDBYin ); + wire WBRSTIin_dly, WBCLKIin_dly, WBCYCIin_dly, WBSTBIin_dly, WBWEIin_dly, + WBADRI0in_dly, WBADRI1in_dly, WBADRI2in_dly, WBADRI3in_dly, + WBADRI4in_dly, WBADRI5in_dly, WBADRI6in_dly, WBADRI7in_dly, + WBDATI0in_dly, WBDATI1in_dly, WBDATI2in_dly, WBDATI3in_dly, + WBDATI4in_dly, WBDATI5in_dly, WBDATI6in_dly, WBDATI7in_dly; + + BUFBA WBCLKI_buf( .A(WBCLKIin_dly), .Z(WBCLKIout)); + BUFBA WBRSTI_buf( .A(WBRSTIin_dly), .Z(WBRSTIout)); + BUFBA WBCYCI_buf( .A(WBCYCIin_dly), .Z(WBCYCIout)); + BUFBA WBSTBI_buf( .A(WBSTBIin_dly), .Z(WBSTBIout)); + BUFBA WBWEI_buf( .A(WBWEIin_dly), .Z(WBWEIout)); + BUFBA WBADRI7_buf( .A(WBADRI7in_dly), .Z(WBADRI7out)); + BUFBA WBADRI6_buf( .A(WBADRI6in_dly), .Z(WBADRI6out)); + BUFBA WBADRI5_buf( .A(WBADRI5in_dly), .Z(WBADRI5out)); + BUFBA WBADRI4_buf( .A(WBADRI4in_dly), .Z(WBADRI4out)); + BUFBA WBADRI3_buf( .A(WBADRI3in_dly), .Z(WBADRI3out)); + BUFBA WBADRI2_buf( .A(WBADRI2in_dly), .Z(WBADRI2out)); + BUFBA WBADRI1_buf( .A(WBADRI1in_dly), .Z(WBADRI1out)); + BUFBA WBADRI0_buf( .A(WBADRI0in_dly), .Z(WBADRI0out)); + BUFBA WBDATI7_buf( .A(WBDATI7in_dly), .Z(WBDATI7out)); + BUFBA WBDATI6_buf( .A(WBDATI6in_dly), .Z(WBDATI6out)); + BUFBA WBDATI5_buf( .A(WBDATI5in_dly), .Z(WBDATI5out)); + BUFBA WBDATI4_buf( .A(WBDATI4in_dly), .Z(WBDATI4out)); + BUFBA WBDATI3_buf( .A(WBDATI3in_dly), .Z(WBDATI3out)); + BUFBA WBDATI2_buf( .A(WBDATI2in_dly), .Z(WBDATI2out)); + BUFBA WBDATI1_buf( .A(WBDATI1in_dly), .Z(WBDATI1out)); + BUFBA WBDATI0_buf( .A(WBDATI0in_dly), .Z(WBDATI0out)); + BUFBA PLL0DATI7_buf( .A(PLL0DATI7in), .Z(PLL0DATI7out)); + BUFBA PLL0DATI6_buf( .A(PLL0DATI6in), .Z(PLL0DATI6out)); + BUFBA PLL0DATI5_buf( .A(PLL0DATI5in), .Z(PLL0DATI5out)); + BUFBA PLL0DATI4_buf( .A(PLL0DATI4in), .Z(PLL0DATI4out)); + BUFBA PLL0DATI3_buf( .A(PLL0DATI3in), .Z(PLL0DATI3out)); + BUFBA PLL0DATI2_buf( .A(PLL0DATI2in), .Z(PLL0DATI2out)); + BUFBA PLL0DATI1_buf( .A(PLL0DATI1in), .Z(PLL0DATI1out)); + BUFBA PLL0DATI0_buf( .A(PLL0DATI0in), .Z(PLL0DATI0out)); + BUFBA PLL0ACKI_buf( .A(PLL0ACKIin), .Z(PLL0ACKIout)); + BUFBA PLL1DATI7_buf( .A(PLL1DATI7in), .Z(PLL1DATI7out)); + BUFBA PLL1DATI6_buf( .A(PLL1DATI6in), .Z(PLL1DATI6out)); + BUFBA PLL1DATI5_buf( .A(PLL1DATI5in), .Z(PLL1DATI5out)); + BUFBA PLL1DATI4_buf( .A(PLL1DATI4in), .Z(PLL1DATI4out)); + BUFBA PLL1DATI3_buf( .A(PLL1DATI3in), .Z(PLL1DATI3out)); + BUFBA PLL1DATI2_buf( .A(PLL1DATI2in), .Z(PLL1DATI2out)); + BUFBA PLL1DATI1_buf( .A(PLL1DATI1in), .Z(PLL1DATI1out)); + BUFBA PLL1DATI0_buf( .A(PLL1DATI0in), .Z(PLL1DATI0out)); + BUFBA PLL1ACKI_buf( .A(PLL1ACKIin), .Z(PLL1ACKIout)); + BUFBA I2C1SCLI_buf( .A(I2C1SCLIin), .Z(I2C1SCLIout)); + BUFBA I2C1SDAI_buf( .A(I2C1SDAIin), .Z(I2C1SDAIout)); + BUFBA I2C2SCLI_buf( .A(I2C2SCLIin), .Z(I2C2SCLIout)); + BUFBA I2C2SDAI_buf( .A(I2C2SDAIin), .Z(I2C2SDAIout)); + BUFBA SPISCKI_buf( .A(SPISCKIin), .Z(SPISCKIout)); + BUFBA SPIMISOI_buf( .A(SPIMISOIin), .Z(SPIMISOIout)); + BUFBA SPIMOSII_buf( .A(SPIMOSIIin), .Z(SPIMOSIIout)); + BUFBA SPISCSN_buf( .A(SPISCSNin), .Z(SPISCSNout)); + BUFBA TCCLKI_buf( .A(TCCLKIin), .Z(TCCLKIout)); + BUFBA TCRSTN_buf( .A(TCRSTNin), .Z(TCRSTNout)); + BUFBA TCIC_buf( .A(TCICin), .Z(TCICout)); + BUFBA UFMSN_buf( .A(UFMSNin), .Z(UFMSNout)); + BUFBA WBDATO7_buf( .A(WBDATO7in), .Z(WBDATO7out)); + BUFBA WBDATO6_buf( .A(WBDATO6in), .Z(WBDATO6out)); + BUFBA WBDATO5_buf( .A(WBDATO5in), .Z(WBDATO5out)); + BUFBA WBDATO4_buf( .A(WBDATO4in), .Z(WBDATO4out)); + BUFBA WBDATO3_buf( .A(WBDATO3in), .Z(WBDATO3out)); + BUFBA WBDATO2_buf( .A(WBDATO2in), .Z(WBDATO2out)); + BUFBA WBDATO1_buf( .A(WBDATO1in), .Z(WBDATO1out)); + BUFBA WBDATO0_buf( .A(WBDATO0in), .Z(WBDATO0out)); + BUFBA WBACKO_buf( .A(WBACKOin), .Z(WBACKOout)); + BUFBA PLLCLKO_buf( .A(PLLCLKOin), .Z(PLLCLKOout)); + BUFBA PLLRSTO_buf( .A(PLLRSTOin), .Z(PLLRSTOout)); + BUFBA PLL0STBO_buf( .A(PLL0STBOin), .Z(PLL0STBOout)); + BUFBA PLL1STBO_buf( .A(PLL1STBOin), .Z(PLL1STBOout)); + BUFBA PLLWEO_buf( .A(PLLWEOin), .Z(PLLWEOout)); + BUFBA PLLADRO4_buf( .A(PLLADRO4in), .Z(PLLADRO4out)); + BUFBA PLLADRO3_buf( .A(PLLADRO3in), .Z(PLLADRO3out)); + BUFBA PLLADRO2_buf( .A(PLLADRO2in), .Z(PLLADRO2out)); + BUFBA PLLADRO1_buf( .A(PLLADRO1in), .Z(PLLADRO1out)); + BUFBA PLLADRO0_buf( .A(PLLADRO0in), .Z(PLLADRO0out)); + BUFBA PLLDATO7_buf( .A(PLLDATO7in), .Z(PLLDATO7out)); + BUFBA PLLDATO6_buf( .A(PLLDATO6in), .Z(PLLDATO6out)); + BUFBA PLLDATO5_buf( .A(PLLDATO5in), .Z(PLLDATO5out)); + BUFBA PLLDATO4_buf( .A(PLLDATO4in), .Z(PLLDATO4out)); + BUFBA PLLDATO3_buf( .A(PLLDATO3in), .Z(PLLDATO3out)); + BUFBA PLLDATO2_buf( .A(PLLDATO2in), .Z(PLLDATO2out)); + BUFBA PLLDATO1_buf( .A(PLLDATO1in), .Z(PLLDATO1out)); + BUFBA PLLDATO0_buf( .A(PLLDATO0in), .Z(PLLDATO0out)); + BUFBA I2C1SCLO_buf( .A(I2C1SCLOin), .Z(I2C1SCLOout)); + BUFBA I2C1SCLOEN_buf( .A(I2C1SCLOENin), .Z(I2C1SCLOENout)); + BUFBA I2C1SDAO_buf( .A(I2C1SDAOin), .Z(I2C1SDAOout)); + BUFBA I2C1SDAOEN_buf( .A(I2C1SDAOENin), .Z(I2C1SDAOENout)); + BUFBA I2C2SCLO_buf( .A(I2C2SCLOin), .Z(I2C2SCLOout)); + BUFBA I2C2SCLOEN_buf( .A(I2C2SCLOENin), .Z(I2C2SCLOENout)); + BUFBA I2C2SDAO_buf( .A(I2C2SDAOin), .Z(I2C2SDAOout)); + BUFBA I2C2SDAOEN_buf( .A(I2C2SDAOENin), .Z(I2C2SDAOENout)); + BUFBA I2C1IRQO_buf( .A(I2C1IRQOin), .Z(I2C1IRQOout)); + BUFBA I2C2IRQO_buf( .A(I2C2IRQOin), .Z(I2C2IRQOout)); + BUFBA SPISCKO_buf( .A(SPISCKOin), .Z(SPISCKOout)); + BUFBA SPISCKEN_buf( .A(SPISCKENin), .Z(SPISCKENout)); + BUFBA SPIMISOO_buf( .A(SPIMISOOin), .Z(SPIMISOOout)); + BUFBA SPIMISOEN_buf( .A(SPIMISOENin), .Z(SPIMISOENout)); + BUFBA SPIMOSIO_buf( .A(SPIMOSIOin), .Z(SPIMOSIOout)); + BUFBA SPIMOSIEN_buf( .A(SPIMOSIENin), .Z(SPIMOSIENout)); + BUFBA SPIMCSN0_buf( .A(SPIMCSN0in), .Z(SPIMCSN0out)); + BUFBA SPIMCSN1_buf( .A(SPIMCSN1in), .Z(SPIMCSN1out)); + BUFBA SPIMCSN2_buf( .A(SPIMCSN2in), .Z(SPIMCSN2out)); + BUFBA SPIMCSN3_buf( .A(SPIMCSN3in), .Z(SPIMCSN3out)); + BUFBA SPIMCSN4_buf( .A(SPIMCSN4in), .Z(SPIMCSN4out)); + BUFBA SPIMCSN5_buf( .A(SPIMCSN5in), .Z(SPIMCSN5out)); + BUFBA SPIMCSN6_buf( .A(SPIMCSN6in), .Z(SPIMCSN6out)); + BUFBA SPIMCSN7_buf( .A(SPIMCSN7in), .Z(SPIMCSN7out)); + BUFBA SPICSNEN_buf( .A(SPICSNENin), .Z(SPICSNENout)); + BUFBA SPIIRQO_buf( .A(SPIIRQOin), .Z(SPIIRQOout)); + BUFBA TCINT_buf( .A(TCINTin), .Z(TCINTout)); + BUFBA TCOC_buf( .A(TCOCin), .Z(TCOCout)); + BUFBA WBCUFMIRQ_buf( .A(WBCUFMIRQin), .Z(WBCUFMIRQout)); + BUFBA CFGWAKE_buf( .A(CFGWAKEin), .Z(CFGWAKEout)); + BUFBA CFGSTDBY_buf( .A(CFGSTDBYin), .Z(CFGSTDBYout)); + + specify + (WBCLKIin => WBDATO0out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO1out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO2out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO3out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO4out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO5out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO6out) = (0:0:0,0:0:0); + (WBCLKIin => WBDATO7out) = (0:0:0,0:0:0); + (WBCLKIin => WBACKOout) = (0:0:0,0:0:0); + $setuphold + (posedge WBCLKIin, WBRSTIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBRSTIin_dly); + $setuphold + (posedge WBCLKIin, WBCYCIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBCYCIin_dly); + $setuphold + (posedge WBCLKIin, WBSTBIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBSTBIin_dly); + $setuphold + (posedge WBCLKIin, WBWEIin, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBWEIin_dly); + $setuphold + (posedge WBCLKIin, WBADRI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI0in_dly); + $setuphold + (posedge WBCLKIin, WBADRI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI1in_dly); + $setuphold + (posedge WBCLKIin, WBADRI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI2in_dly); + $setuphold + (posedge WBCLKIin, WBADRI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI3in_dly); + $setuphold + (posedge WBCLKIin, WBADRI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI4in_dly); + $setuphold + (posedge WBCLKIin, WBADRI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI5in_dly); + $setuphold + (posedge WBCLKIin, WBADRI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI6in_dly); + $setuphold + (posedge WBCLKIin, WBADRI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBADRI7in_dly); + $setuphold + (posedge WBCLKIin, WBDATI0in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI0in_dly); + $setuphold + (posedge WBCLKIin, WBDATI1in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI1in_dly); + $setuphold + (posedge WBCLKIin, WBDATI2in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI2in_dly); + $setuphold + (posedge WBCLKIin, WBDATI3in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI3in_dly); + $setuphold + (posedge WBCLKIin, WBDATI4in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI4in_dly); + $setuphold + (posedge WBCLKIin, WBDATI5in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI5in_dly); + $setuphold + (posedge WBCLKIin, WBDATI6in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI6in_dly); + $setuphold + (posedge WBCLKIin, WBDATI7in, 0:0:0, 0:0:0,,,, WBCLKIin_dly, WBDATI7in_dly); + $width (posedge WBCLKIin, 0:0:0); + $width (negedge WBCLKIin, 0:0:0); + endspecify + +endmodule diff --git a/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html new file mode 100644 index 0000000..639e926 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html @@ -0,0 +1,14 @@ + 
    Setting log file to '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/impl1/hdla_gen_hierarchy.html'.
+Starting: parse design source files
+(VERI-1482) Analyzing Verilog file 'C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v'
+(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v'
+(VERI-1482) Analyzing Verilog file '//Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/REFB.v'
+INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v(1,8-1,13) (VERI-1018) compiling module 'RAM2E'
+INFO - //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-LCMXO2.v(1,1-831,10) (VERI-9000) elaborating module 'RAM2E'
+INFO - //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/REFB.v(8,1-113,10) (VERI-9000) elaborating module 'REFB_uniq_1'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
+INFO - C:/lscc/diamond/3.12/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1800,1-1872,10) (VERI-9000) elaborating module 'EFB_uniq_1'
+Done: design load finished with (0) errors, and (0) warnings
+
+
    \ No newline at end of file diff --git a/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior b/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior new file mode 100644 index 0000000..0656e13 --- /dev/null +++ b/CPLD/LCMXO2-640HC/impl1/ram2e_lcmxo2_640hc_impl1.ior @@ -0,0 +1,118 @@ +Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd. +Design name: RAM2E +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 5 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd. +Design name: RAM2E +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: 6 +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +Loading design for application iotiming from file ram2e_lcmxo2_640hc_impl1.ncd. +Design name: RAM2E +NCD version: 3.3 +Vendor: LATTICE +Device: LCMXO2-640HC +Package: TQFP100 +Performance: M +Package Status: Final Version 1.39. +Performance Hardware Data Status: Final Version 34.4. +// Design: RAM2E +// Package: TQFP100 +// ncd File: ram2e_lcmxo2_640hc_impl1.ncd +// Version: Diamond (64-bit) 3.12.1.454 +// Written on Thu Sep 21 05:35:10 2023 +// M: Minimum Performance Grade +// iotiming RAM2E_LCMXO2_640HC_impl1.ncd RAM2E_LCMXO2_640HC_impl1.prf -gui -msgset //Mac/iCloud/Repos/RAM2E/CPLD/LCMXO2-640HC/promote.xml + +I/O Timing Report (All units are in ns) + +Worst Case Results across Performance Grades (M, 6, 5, 4): + +// Input Setup and Hold Times + +Port Clock Edge Setup Performance_Grade Hold Performance_Grade +---------------------------------------------------------------------- +Ain[0] C14M R 0.502 4 0.868 4 +Ain[1] C14M R 2.364 4 -0.126 M +Ain[2] C14M R 2.421 4 -0.129 M +Ain[3] C14M R 0.574 4 0.786 4 +Ain[4] C14M R 1.452 4 0.140 M +Ain[5] C14M R 2.076 4 -0.039 M +Ain[6] C14M R 1.515 4 0.124 M +Ain[7] C14M R 2.270 4 -0.095 M +Din[0] C14M R 9.252 4 1.162 4 +Din[1] C14M R 8.868 4 0.657 4 +Din[2] C14M R 8.368 4 0.864 4 +Din[3] C14M R 8.749 4 1.339 4 +Din[4] C14M R 9.095 4 0.770 4 +Din[5] C14M R 8.195 4 1.176 4 +Din[6] C14M R 6.162 4 0.760 4 +Din[7] C14M R 7.060 4 1.093 4 +PHI1 C14M R 2.045 4 3.047 4 +RD[0] C14M F 0.267 4 0.866 4 +RD[1] C14M F 0.173 4 1.383 4 +RD[2] C14M F 0.924 4 1.018 4 +RD[3] C14M F 0.267 4 0.866 4 +RD[4] C14M F 0.173 4 0.937 4 +RD[5] C14M F 0.267 4 0.866 4 +RD[6] C14M F 0.766 4 0.866 4 +RD[7] C14M F 0.267 4 1.312 4 +nC07X C14M R 0.077 4 1.144 4 +nEN80 C14M R 6.415 4 -0.286 M +nWE C14M R 0.691 4 0.684 4 +nWE80 C14M R 2.845 4 -0.260 M + + +// Clock to Output Delay + +Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade +------------------------------------------------------------------------ +BA[0] C14M R 8.629 4 2.885 M +BA[1] C14M R 8.629 4 2.885 M +CKE C14M R 8.629 4 2.885 M +DQMH C14M R 8.609 4 2.892 M +DQML C14M R 8.609 4 2.892 M +Dout[0] C14M F 8.955 4 3.164 M +Dout[1] C14M F 8.955 4 3.164 M +Dout[2] C14M F 8.944 4 3.158 M +Dout[3] C14M F 8.955 4 3.164 M +Dout[4] C14M F 8.944 4 3.158 M +Dout[5] C14M F 8.944 4 3.158 M +Dout[6] C14M F 8.955 4 3.164 M +Dout[7] C14M F 8.955 4 3.164 M +LED C14M R 19.941 4 8.191 M +RA[0] C14M R 10.013 4 3.186 M +RA[10] C14M R 8.629 4 2.885 M +RA[11] C14M R 8.629 4 2.885 M +RA[1] C14M R 8.695 4 2.890 M +RA[2] C14M R 8.695 4 2.890 M +RA[3] C14M R 10.013 4 3.186 M +RA[4] C14M R 8.695 4 2.890 M +RA[5] C14M R 8.695 4 2.890 M +RA[6] C14M R 8.695 4 2.890 M +RA[7] C14M R 8.695 4 2.890 M +RA[8] C14M R 8.629 4 2.885 M +RA[9] C14M R 8.629 4 2.885 M +Vout[0] C14M F 9.553 4 3.402 M +Vout[1] C14M F 9.553 4 3.402 M +Vout[2] C14M F 9.553 4 3.402 M +Vout[3] C14M F 9.553 4 3.402 M +Vout[4] C14M F 9.553 4 3.402 M +Vout[5] C14M F 9.553 4 3.402 M +Vout[6] C14M F 9.553 4 3.402 M +Vout[7] C14M F 9.553 4 3.402 M +nCAS C14M R 8.629 4 2.885 M +nCS C14M R 8.629 4 2.885 M +nDOE C14M R 11.976 4 3.776 M +nRAS C14M R 8.629 4 2.885 M +nRWE C14M R 8.629 4 2.885 M +WARNING: you must also run trce with hold speed: 4 diff --git a/CPLD/LCMXO2-640HC/msg_file.log b/CPLD/LCMXO2-640HC/msg_file.log new file mode 100644 index 0000000..fe5110d --- /dev/null +++ b/CPLD/LCMXO2-640HC/msg_file.log @@ -0,0 +1,29 @@ +SCUBA, Version Diamond (64-bit) 3.12.1.454 +Wed Sep 20 04:17:14 2023 + +Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. +Copyright (c) 1995 AT&T Corp. All rights reserved. +Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. +Copyright (c) 2001 Agere Systems All rights reserved. +Copyright (c) 2002-2020 Lattice Semiconductor Corporation, All rights reserved. + +BEGIN SCUBA Module Synthesis + + Issued command : C:\lscc\diamond\3.12\ispfpga\bin\nt64\scuba.exe -w -n REFB -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 14.4 -ufm -ufm_ebr 190 -mem_size 1 -memfile ../RAM2E-LCMXO2.mem -memformat hex -wb -dev 640 + Circuit name : REFB + Module type : efb + Module Version : 1.2 + Ports : + Inputs : wb_clk_i, wb_rst_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_adr_i[7:0], wb_dat_i[7:0] + Outputs : wb_dat_o[7:0], wb_ack_o, wbc_ufm_irq + I/O buffer : not inserted + EDIF output : REFB.edn + Verilog output : REFB.v + Verilog template : REFB_tmpl.v + Verilog purpose : for synthesis and simulation + Bus notation : big endian + Report output : REFB.srp + Estimated Resource Usage: + +END SCUBA Module Synthesis + diff --git a/CPLD/LCMXO2-640HC/promote.xml b/CPLD/LCMXO2-640HC/promote.xml new file mode 100644 index 0000000..2c3c713 --- /dev/null +++ b/CPLD/LCMXO2-640HC/promote.xml @@ -0,0 +1,3 @@ + + + diff --git a/CPLD/LCMXO2-640HC/reportview.xml b/CPLD/LCMXO2-640HC/reportview.xml new file mode 100644 index 0000000..146942a --- /dev/null +++ b/CPLD/LCMXO2-640HC/reportview.xml @@ -0,0 +1,10 @@ + + + + + + + + + + diff --git a/CPLD/MAXII/RAM2E-MAXII.qpf b/CPLD/MAXII/RAM2E-MAXII.qpf new file mode 100644 index 0000000..83d5b38 --- /dev/null +++ b/CPLD/MAXII/RAM2E-MAXII.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +# Date created = 07:26:23 August 20, 2023 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "19.1" +DATE = "07:26:23 August 20, 2023" + +# Revisions + +PROJECT_REVISION = "RAM2E" diff --git a/CPLD/MAXII/RAM2E.qsf b/CPLD/MAXII/RAM2E.qsf new file mode 100644 index 0000000..722f2da --- /dev/null +++ b/CPLD/MAXII/RAM2E.qsf @@ -0,0 +1,248 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +# Date created = 07:26:23 August 20, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# RAM2E_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX II" +set_global_assignment -name DEVICE EPM240T100C5 +set_global_assignment -name TOP_LEVEL_ENTITY RAM2E +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:26:23 AUGUST 20, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND" + +set_location_assignment PIN_12 -to C14M +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C14M + +set_location_assignment PIN_37 -to PHI1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI1 +set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to PHI1 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI1 + +set_location_assignment PIN_51 -to nWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE + +set_location_assignment PIN_28 -to nEN80 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nEN80 +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nEN80 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80 + +set_location_assignment PIN_33 -to nWE80 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80 +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80 + +set_location_assignment PIN_52 -to nC07X +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nC07X +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nC07X +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nC07X + +set_location_assignment PIN_56 -to Ain[0] +set_location_assignment PIN_54 -to Ain[1] +set_location_assignment PIN_43 -to Ain[2] +set_location_assignment PIN_47 -to Ain[3] +set_location_assignment PIN_44 -to Ain[4] +set_location_assignment PIN_34 -to Ain[5] +set_location_assignment PIN_39 -to Ain[6] +set_location_assignment PIN_53 -to Ain[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Ain +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Ain +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Ain + +set_location_assignment PIN_38 -to Din[0] +set_location_assignment PIN_40 -to Din[1] +set_location_assignment PIN_42 -to Din[2] +set_location_assignment PIN_41 -to Din[3] +set_location_assignment PIN_48 -to Din[4] +set_location_assignment PIN_49 -to Din[5] +set_location_assignment PIN_36 -to Din[6] +set_location_assignment PIN_35 -to Din[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Din +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Din + +set_location_assignment PIN_55 -to nDOE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE + +set_location_assignment PIN_77 -to Dout[0] +set_location_assignment PIN_76 -to Dout[1] +set_location_assignment PIN_74 -to Dout[2] +set_location_assignment PIN_75 -to Dout[3] +set_location_assignment PIN_73 -to Dout[4] +set_location_assignment PIN_72 -to Dout[5] +set_location_assignment PIN_84 -to Dout[6] +set_location_assignment PIN_85 -to Dout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout +set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout + +set_location_assignment PIN_50 -to nVOE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE + +set_location_assignment PIN_70 -to Vout[0] +set_location_assignment PIN_67 -to Vout[1] +set_location_assignment PIN_69 -to Vout[2] +set_location_assignment PIN_62 -to Vout[3] +set_location_assignment PIN_71 -to Vout[4] +set_location_assignment PIN_68 -to Vout[5] +set_location_assignment PIN_58 -to Vout[6] +set_location_assignment PIN_57 -to Vout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Vout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Vout +set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout + +set_location_assignment PIN_4 -to CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE +set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE + +set_location_assignment PIN_8 -to nCS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS + +set_location_assignment PIN_2 -to nRWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE + +set_location_assignment PIN_5 -to nRAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS + +set_location_assignment PIN_3 -to nCAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS + +set_location_assignment PIN_6 -to BA[0] +set_location_assignment PIN_14 -to BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to BA +set_instance_assignment -name SLOW_SLEW_RATE ON -to BA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA + +set_location_assignment PIN_18 -to RA[0] +set_location_assignment PIN_20 -to RA[1] +set_location_assignment PIN_30 -to RA[2] +set_location_assignment PIN_27 -to RA[3] +set_location_assignment PIN_26 -to RA[4] +set_location_assignment PIN_29 -to RA[5] +set_location_assignment PIN_21 -to RA[6] +set_location_assignment PIN_19 -to RA[7] +set_location_assignment PIN_17 -to RA[8] +set_location_assignment PIN_15 -to RA[9] +set_location_assignment PIN_16 -to RA[10] +set_location_assignment PIN_7 -to RA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA +set_instance_assignment -name SLOW_SLEW_RATE ON -to RA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA + +set_location_assignment PIN_100 -to DQMH +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQMH +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH + +set_location_assignment PIN_98 -to DQML +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQML +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML + +set_location_assignment PIN_97 -to RD[0] +set_location_assignment PIN_90 -to RD[1] +set_location_assignment PIN_99 -to RD[2] +set_location_assignment PIN_89 -to RD[3] +set_location_assignment PIN_91 -to RD[4] +set_location_assignment PIN_92 -to RD[5] +set_location_assignment PIN_95 -to RD[6] +set_location_assignment PIN_96 -to RD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD +set_instance_assignment -name SLOW_SLEW_RATE ON -to RD +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD + +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name VERILOG_FILE "../RAM2E-MAX.v" +set_global_assignment -name QIP_FILE UFM.qip +set_global_assignment -name MIF_FILE ../RAM2E.mif +set_global_assignment -name SDC_FILE ../RAM2E.sdc +set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc" +set_location_assignment PIN_88 -to LED +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED +set_instance_assignment -name SLOW_SLEW_RATE ON -to LED \ No newline at end of file diff --git a/CPLD/MAXII/RAM2E.qws b/CPLD/MAXII/RAM2E.qws new file mode 100644 index 0000000000000000000000000000000000000000..8de3d3ecec64b3ff743c66893051e3ad1a1fae78 GIT binary patch literal 619 zcmbV}y-LGS6vzLG4njNh0UR7eLLt)D3XbC7jWk-8%b+CHKklYb_pRdc=!zasn2hVJ7eVAvVg$kRq(9CzX2&NLYYX~a{ z6Lji2cjgJ+7>25@51SMXk=DE}$Rz)T_?YXa-}e + + + + + + + diff --git a/CPLD/MAXII/output_files/RAM2E.map.rpt b/CPLD/MAXII/output_files/RAM2E.map.rpt new file mode 100644 index 0000000..da29b55 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2E.map.rpt @@ -0,0 +1,306 @@ +Analysis & Synthesis report for RAM2E +Thu Sep 21 05:34:32 2023 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis IP Cores Summary + 9. General Register Statistics + 10. Inverted Register Statistics + 11. Multiplexer Restructuring Statistics (Restructuring Performed) + 12. Port Connectivity Checks: "UFM:UFM_inst" + 13. Analysis & Synthesis Messages + 14. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2019 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:34:32 2023 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX II ; +; Total logic elements ; 205 ; +; Total pins ; 70 ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EPM240T100C5 ; ; +; Top-level entity name ; RAM2E ; RAM2E ; +; Family name ; MAX II ; Cyclone V ; +; Maximum processors allowed for parallel compilation ; 4 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Block Design Naming ; Auto ; Auto ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+ +; ../RAM2E-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v ; ; +; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.mif ; ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Total logic elements ; 205 ; +; -- Combinational with no register ; 93 ; +; -- Register only ; 27 ; +; -- Combinational with a register ; 85 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 103 ; +; -- 3 input functions ; 29 ; +; -- 2 input functions ; 42 ; +; -- 1 input functions ; 3 ; +; -- 0 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 191 ; +; -- arithmetic mode ; 14 ; +; -- qfbk mode ; 0 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 1 ; +; -- asynchronous clear/load mode ; 0 ; +; ; ; +; Total registers ; 112 ; +; Total logic cells in carry chains ; 15 ; +; I/O pins ; 70 ; +; UFM blocks ; 1 ; +; Maximum fan-out node ; C14M ; +; Maximum fan-out ; 112 ; +; Total fan-out ; 850 ; +; Average fan-out ; 3.08 ; ++---------------------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ +; |RAM2E ; 205 (205) ; 112 ; 1 ; 70 ; 0 ; 93 (93) ; 27 (27) ; 85 (85) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ; +; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ; +; |UFM_altufm_none_lbr:UFM_altufm_none_lbr_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component ; UFM_altufm_none_lbr ; work ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+ +; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1 ; N/A ; N/A ; |RAM2E|UFM:UFM_inst ; UFM.v ; ++--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 112 ; +; Number of registers using Synchronous Clear ; 1 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 60 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------+---------+ +; nCS~reg0 ; 1 ; +; nRAS~reg0 ; 1 ; +; nCAS~reg0 ; 1 ; +; nRWE~reg0 ; 1 ; +; DQML~reg0 ; 1 ; +; DQMH~reg0 ; 1 ; +; Total number of inverted registers = 6 ; ; ++----------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |RAM2E|RA[0]~reg0 ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ; +; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[0] ; +; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RWMask[4] ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "UFM:UFM_inst" ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ +; ardin ; Input ; Info ; Stuck at GND ; +; oscena ; Input ; Info ; Stuck at VCC ; +; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Thu Sep 21 05:33:57 2023 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXII -c RAM2E +Info (20032): Parallel compilation is enabled and will use up to 4 processors +Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2e/cpld/ram2e-max.v + Info (12023): Found entity 1: RAM2E File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1 +Info (12021): Found 2 design units, including 2 entities, in source file ufm.v + Info (12023): Found entity 1: UFM_altufm_none_lbr File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 47 + Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 166 +Info (12127): Elaborating entity "RAM2E" for the top level hierarchy +Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 93 +Info (12128): Elaborating entity "UFM_altufm_none_lbr" for hierarchy "UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component" File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 217 +Info (21057): Implemented 276 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 22 input pins + Info (21059): Implemented 40 output pins + Info (21060): Implemented 8 bidirectional pins + Info (21061): Implemented 205 logic cells + Info (21070): Implemented 1 User Flash Memory blocks +Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 13144 megabytes + Info: Processing ended: Thu Sep 21 05:34:32 2023 + Info: Elapsed time: 00:00:35 + Info: Total CPU time (on all processors): 00:00:49 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXII/output_files/RAM2E.map.smsg. + + diff --git a/CPLD/MAXII/output_files/RAM2E.map.smsg b/CPLD/MAXII/output_files/RAM2E.map.smsg new file mode 100644 index 0000000..06be456 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2E.map.smsg @@ -0,0 +1,3 @@ +Warning (10273): Verilog HDL warning at RAM2E-MAX.v(46): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 46 +Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXII/UFM.v Line: 189 diff --git a/CPLD/MAXII/output_files/RAM2E.map.summary b/CPLD/MAXII/output_files/RAM2E.map.summary new file mode 100644 index 0000000..8b68ed4 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2E.map.summary @@ -0,0 +1,9 @@ +Analysis & Synthesis Status : Successful - Thu Sep 21 05:34:32 2023 +Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition +Revision Name : RAM2E +Top-level Entity Name : RAM2E +Family : MAX II +Total logic elements : 205 +Total pins : 70 +Total virtual pins : 0 +UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXII/output_files/RAM2E.pin b/CPLD/MAXII/output_files/RAM2E.pin new file mode 100644 index 0000000..f8fa7ef --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2E.pin @@ -0,0 +1,165 @@ + -- Copyright (C) 2019 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (2.5V/3.3V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +CHIP "RAM2E" ASSIGNED TO AN: EPM240T100C5 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND* : 1 : : : : 2 : +nRWE : 2 : output : 3.3-V LVCMOS : : 1 : Y +nCAS : 3 : output : 3.3-V LVCMOS : : 1 : Y +CKE : 4 : output : 3.3-V LVCMOS : : 1 : Y +nRAS : 5 : output : 3.3-V LVCMOS : : 1 : Y +BA[0] : 6 : output : 3.3-V LVCMOS : : 1 : Y +RA[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y +nCS : 8 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 9 : power : : 3.3V : 1 : +GNDIO : 10 : gnd : : : : +GNDINT : 11 : gnd : : : : +C14M : 12 : input : 3.3-V LVCMOS : : 1 : Y +VCCINT : 13 : power : : 2.5V/3.3V : : +BA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y +RA[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y +RA[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y +RA[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y +RA[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y +RA[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y +RA[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y +RA[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y +TMS : 22 : input : : : 1 : +TDI : 23 : input : : : 1 : +TCK : 24 : input : : : 1 : +TDO : 25 : output : : : 1 : +RA[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y +RA[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y +nEN80 : 28 : input : 3.3-V LVCMOS : : 1 : Y +RA[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y +RA[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 31 : power : : 3.3V : 1 : +GNDIO : 32 : gnd : : : : +nWE80 : 33 : input : 3.3-V LVCMOS : : 1 : Y +Ain[5] : 34 : input : 3.3-V LVCMOS : : 1 : Y +Din[7] : 35 : input : 3.3-V LVCMOS : : 1 : Y +Din[6] : 36 : input : 3.3-V LVCMOS : : 1 : Y +PHI1 : 37 : input : 3.3-V LVCMOS : : 1 : Y +Din[0] : 38 : input : 3.3-V LVCMOS : : 1 : Y +Ain[6] : 39 : input : 3.3-V LVCMOS : : 1 : Y +Din[1] : 40 : input : 3.3-V LVCMOS : : 1 : Y +Din[3] : 41 : input : 3.3-V LVCMOS : : 1 : Y +Din[2] : 42 : input : 3.3-V LVCMOS : : 1 : Y +Ain[2] : 43 : input : 3.3-V LVCMOS : : 1 : Y +Ain[4] : 44 : input : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 45 : power : : 3.3V : 1 : +GNDIO : 46 : gnd : : : : +Ain[3] : 47 : input : 3.3-V LVCMOS : : 1 : Y +Din[4] : 48 : input : 3.3-V LVCMOS : : 1 : Y +Din[5] : 49 : input : 3.3-V LVCMOS : : 1 : Y +nVOE : 50 : output : 3.3-V LVCMOS : : 1 : Y +nWE : 51 : input : 3.3-V LVCMOS : : 1 : Y +nC07X : 52 : input : 3.3-V LVCMOS : : 2 : Y +Ain[7] : 53 : input : 3.3-V LVCMOS : : 2 : Y +Ain[1] : 54 : input : 3.3-V LVCMOS : : 2 : Y +nDOE : 55 : output : 3.3-V LVCMOS : : 2 : Y +Ain[0] : 56 : input : 3.3-V LVCMOS : : 2 : Y +Vout[7] : 57 : output : 3.3-V LVCMOS : : 2 : Y +Vout[6] : 58 : output : 3.3-V LVCMOS : : 2 : Y +VCCIO2 : 59 : power : : 3.3V : 2 : +GNDIO : 60 : gnd : : : : +GND* : 61 : : : : 2 : +Vout[3] : 62 : output : 3.3-V LVCMOS : : 2 : Y +VCCINT : 63 : power : : 2.5V/3.3V : : +GND* : 64 : : : : 2 : +GNDINT : 65 : gnd : : : : +GND* : 66 : : : : 2 : +Vout[1] : 67 : output : 3.3-V LVCMOS : : 2 : Y +Vout[5] : 68 : output : 3.3-V LVCMOS : : 2 : Y +Vout[2] : 69 : output : 3.3-V LVCMOS : : 2 : Y +Vout[0] : 70 : output : 3.3-V LVCMOS : : 2 : Y +Vout[4] : 71 : output : 3.3-V LVCMOS : : 2 : Y +Dout[5] : 72 : output : 3.3-V LVCMOS : : 2 : Y +Dout[4] : 73 : output : 3.3-V LVCMOS : : 2 : Y +Dout[2] : 74 : output : 3.3-V LVCMOS : : 2 : Y +Dout[3] : 75 : output : 3.3-V LVCMOS : : 2 : Y +Dout[1] : 76 : output : 3.3-V LVCMOS : : 2 : Y +Dout[0] : 77 : output : 3.3-V LVCMOS : : 2 : Y +GND* : 78 : : : : 2 : +GNDIO : 79 : gnd : : : : +VCCIO2 : 80 : power : : 3.3V : 2 : +GND* : 81 : : : : 2 : +GND* : 82 : : : : 2 : +GND* : 83 : : : : 2 : +Dout[6] : 84 : output : 3.3-V LVCMOS : : 2 : Y +Dout[7] : 85 : output : 3.3-V LVCMOS : : 2 : Y +GND* : 86 : : : : 2 : +GND* : 87 : : : : 2 : +LED : 88 : output : 3.3-V LVTTL : : 2 : Y +RD[3] : 89 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[4] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[5] : 92 : bidir : 3.3-V LVCMOS : : 2 : Y +GNDIO : 93 : gnd : : : : +VCCIO2 : 94 : power : : 3.3V : 2 : +RD[6] : 95 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[7] : 96 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[0] 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Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Fmax Summary + 7. Setup Summary + 8. Hold Summary + 9. Recovery Summary + 10. Removal Summary + 11. Minimum Pulse Width Summary + 12. Setup: 'DRCLK' + 13. Setup: 'ARCLK' + 14. Setup: 'C14M' + 15. Hold: 'ARCLK' + 16. Hold: 'DRCLK' + 17. Hold: 'C14M' + 18. Setup Transfers + 19. Hold Transfers + 20. Report TCCS + 21. Report RSKM + 22. Unconstrained Paths Summary + 23. Clock Status Summary + 24. Unconstrained Input Ports + 25. Unconstrained Output Ports + 26. Unconstrained Input Ports + 27. Unconstrained Output Ports + 28. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2019 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; RAM2E ; +; Device Family ; MAX II ; +; Device Name ; EPM240T100C5 ; +; Timing Models ; Final ; +; Delay Model ; Slow Model ; +; Rise/Fall Delays ; Unavailable ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.2% ; ++----------------------------+-------------+ + + ++------------------------------------------------------+ +; SDC File List ; ++------------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++------------------+--------+--------------------------+ +; ../RAM2E.sdc ; OK ; Thu Sep 21 05:34:44 2023 ; +; ../RAM2E-MAX.sdc ; OK ; Thu Sep 21 05:34:44 2023 ; ++------------------+--------+--------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; ARCLK ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ; +; C14M ; Base ; 69.841 ; 14.32 MHz ; 0.000 ; 34.920 ; ; ; ; ; ; ; ; ; ; ; { C14M } ; +; DRCLK ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ; ++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ + + ++-------------------------------------------------+ +; Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; +; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; +; 61.13 MHz ; 61.13 MHz ; C14M ; ; ++-----------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++---------------------------------+ +; Setup Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; DRCLK ; -23.265 ; -23.265 ; +; ARCLK ; -23.125 ; -23.125 ; +; C14M ; -8.026 ; -92.836 ; ++-------+---------+---------------+ + + ++---------------------------------+ +; Hold Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -16.874 ; -16.874 ; +; DRCLK ; -16.746 ; -16.746 ; +; C14M ; 1.415 ; 0.000 ; ++-------+---------+---------------+ + + +-------------------- +; Recovery Summary ; +-------------------- +No paths to report. + + +------------------- +; Removal Summary ; +------------------- +No paths to report. + + ++--------------------------------+ +; Minimum Pulse Width Summary ; ++-------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------+ +; C14M ; 34.654 ; 0.000 ; +; ARCLK ; 70.000 ; 0.000 ; +; DRCLK ; 70.000 ; 0.000 ; ++-------+--------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -23.265 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.725 ; 1.541 ; +; -23.253 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.725 ; 1.529 ; +; 100.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 200.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -23.125 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.001 ; -1.597 ; 1.529 ; +; 100.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 200.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'C14M' ; ++--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ +; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[4] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ; +; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[5] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ; +; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[7] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ; +; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[0] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ; +; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[1] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ; +; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[2] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ; +; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[3] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ; +; -8.026 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; RWMask[6] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.419 ; +; -7.612 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; LEDEN ; DRCLK ; C14M ; 0.001 ; 1.725 ; 9.005 ; +; -7.370 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMInitDone ; DRCLK ; C14M ; 0.001 ; 1.725 ; 8.763 ; +; -7.319 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMReqErase ; DRCLK ; C14M ; 0.001 ; 1.725 ; 8.712 ; +; -6.327 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFMD[8] ; DRCLK ; C14M ; 0.001 ; 1.725 ; 7.720 ; +; 27.280 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.307 ; +; 27.280 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.307 ; +; 27.332 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.255 ; +; 27.332 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.255 ; +; 27.332 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.255 ; +; 27.583 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ; +; 27.583 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ; +; 27.583 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ; +; 27.583 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ; +; 27.583 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ; +; 27.583 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.004 ; +; 27.585 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.002 ; +; 27.590 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.997 ; +; 27.761 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ; +; 27.761 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ; +; 27.761 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ; +; 27.761 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ; +; 27.761 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ; +; 27.761 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.826 ; +; 27.763 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.824 ; +; 27.768 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.819 ; +; 27.779 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ; +; 27.779 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ; +; 27.779 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ; +; 27.779 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ; +; 27.779 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ; +; 27.779 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.808 ; +; 27.781 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.806 ; +; 27.786 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.801 ; +; 27.878 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.709 ; +; 27.878 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.709 ; +; 27.930 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.657 ; +; 27.930 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.657 ; +; 27.930 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.657 ; +; 28.203 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ; +; 28.203 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ; +; 28.203 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ; +; 28.203 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ; +; 28.203 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ; +; 28.203 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.384 ; +; 28.205 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.382 ; +; 28.210 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.377 ; +; 28.368 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.219 ; +; 28.368 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.219 ; +; 28.368 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.219 ; +; 28.431 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.156 ; +; 28.431 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.156 ; +; 28.483 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.104 ; +; 28.483 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.104 ; +; 28.483 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.104 ; +; 28.546 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.041 ; +; 28.546 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 6.041 ; +; 28.598 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.989 ; +; 28.598 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.989 ; +; 28.598 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.989 ; +; 28.966 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.621 ; +; 28.966 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.621 ; +; 28.966 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.621 ; +; 29.519 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.068 ; +; 29.519 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.068 ; +; 29.519 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 5.068 ; +; 29.634 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.953 ; +; 29.634 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.953 ; +; 29.634 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 4.953 ; +; 53.482 ; FS[15] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 16.026 ; +; 53.855 ; FS[14] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 15.653 ; +; 54.606 ; FS[15] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.902 ; +; 54.773 ; FS[15] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.735 ; +; 54.979 ; FS[14] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.529 ; +; 55.110 ; FS[15] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.398 ; +; 55.146 ; FS[14] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.362 ; +; 55.483 ; FS[14] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 14.025 ; +; 55.674 ; FS[11] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.834 ; +; 55.804 ; FS[10] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.704 ; +; 56.000 ; FS[8] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.508 ; +; 56.341 ; FS[9] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 13.167 ; +; 56.591 ; FS[12] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.917 ; +; 56.798 ; FS[11] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.710 ; +; 56.928 ; FS[10] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.580 ; +; 56.931 ; FS[13] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.577 ; +; 56.965 ; FS[11] ; RA[10]~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 12.543 ; +; 56.994 ; S[2] ; RWMask[4] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ; +; 56.994 ; S[2] ; RWMask[5] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ; +; 56.994 ; S[2] ; RWMask[7] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ; +; 56.994 ; S[2] ; RWMask[0] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ; +; 56.994 ; S[2] ; RWMask[1] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ; +; 56.994 ; S[2] ; RWMask[2] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ; +; 56.994 ; S[2] ; RWMask[3] ; C14M ; C14M ; 69.841 ; 0.000 ; 12.514 ; ++--------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.874 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.000 ; -1.597 ; 1.529 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.746 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.725 ; 1.529 ; +; -16.734 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.725 ; 1.541 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_lbr:UFM_altufm_none_lbr_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------+ +; Hold: 'C14M' ; ++-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+ +; 1.415 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.636 ; +; 1.421 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.642 ; +; 1.639 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 1.860 ; +; 1.639 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.860 ; +; 1.660 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.881 ; +; 1.669 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.890 ; +; 1.701 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.922 ; +; 1.701 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.922 ; +; 1.730 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.951 ; +; 1.732 ; S[0] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 1.953 ; +; 1.822 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.043 ; +; 1.844 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.065 ; +; 1.953 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 2.174 ; +; 1.981 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.202 ; +; 1.991 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.212 ; +; 2.107 ; LEDEN ; LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ; +; 2.107 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ; +; 2.107 ; CmdBitbangMAX ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 2.328 ; +; 2.118 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 2.339 ; +; 2.126 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ; +; 2.126 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.347 ; +; 2.134 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.355 ; +; 2.138 ; CmdPrgmMAX ; CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.359 ; +; 2.143 ; CmdPrgmMAX ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.364 ; +; 2.144 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.365 ; +; 2.146 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.367 ; +; 2.152 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.373 ; +; 2.152 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.373 ; +; 2.162 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.383 ; +; 2.165 ; CmdEraseMAX ; CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 2.386 ; +; 2.199 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.420 ; +; 2.207 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.428 ; +; 2.218 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.439 ; +; 2.233 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.454 ; +; 2.247 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.468 ; +; 2.249 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.470 ; +; 2.260 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.481 ; +; 2.262 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.483 ; +; 2.268 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.489 ; +; 2.273 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.494 ; +; 2.290 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.511 ; +; 2.291 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.512 ; +; 2.295 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.516 ; +; 2.308 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.529 ; +; 2.309 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.530 ; +; 2.382 ; UFMReqErase ; UFMReqErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.603 ; +; 2.390 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.611 ; +; 2.448 ; UFMD[14] ; UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.669 ; +; 2.455 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.676 ; +; 2.461 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.682 ; +; 2.622 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 2.843 ; +; 2.624 ; UFMBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.845 ; +; 2.626 ; RWBank[3] ; RA[11]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 2.847 ; +; 2.645 ; UFMD[13] ; UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.866 ; +; 2.655 ; PHI1reg ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.876 ; +; 2.720 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 2.941 ; +; 2.732 ; UFMD[15] ; RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.953 ; +; 2.766 ; RWSel ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 2.987 ; +; 2.823 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.044 ; +; 2.844 ; UFMD[9] ; RWMask[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.065 ; +; 2.851 ; RWBank[5] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.072 ; +; 2.911 ; S[3] ; nCS~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.132 ; +; 2.913 ; S[3] ; BA[0]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.134 ; +; 2.952 ; RTPBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.173 ; +; 2.958 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.179 ; +; 2.966 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.187 ; +; 2.984 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.205 ; +; 2.984 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.205 ; +; 2.992 ; RWMask[2] ; RWBank[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.213 ; +; 3.041 ; RWBank[0] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.262 ; +; 3.063 ; RWMask[0] ; RWBank[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.284 ; +; 3.069 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.290 ; +; 3.077 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.298 ; +; 3.095 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.316 ; +; 3.095 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.316 ; +; 3.096 ; RWSel ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 3.317 ; +; 3.098 ; RWSel ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.319 ; +; 3.118 ; S[0] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.339 ; +; 3.134 ; RWBank[1] ; RA[9]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.355 ; +; 3.163 ; UFMD[11] ; RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.384 ; +; 3.168 ; DRCLKPulse ; DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 3.389 ; +; 3.170 ; RWBank[7] ; RA[8]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.391 ; +; 3.173 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.394 ; +; 3.187 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.408 ; +; 3.188 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.409 ; +; 3.189 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.410 ; +; 3.189 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.410 ; +; 3.200 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.421 ; +; 3.203 ; RWMask[1] ; RWBank[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.424 ; +; 3.206 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.427 ; +; 3.208 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.429 ; +; 3.213 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.434 ; +; 3.218 ; CmdSetRWBankFFLED ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.439 ; +; 3.222 ; CmdSetRWBankFFLED ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.443 ; +; 3.230 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.451 ; +; 3.230 ; RWSel ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.451 ; +; 3.236 ; S[0] ; nCS~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 3.457 ; +; 3.241 ; UFMD[12] ; RWMask[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.462 ; +; 3.274 ; UFMD[14] ; RWMask[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.495 ; +; 3.299 ; FS[8] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.520 ; ++-------+-------------------+-------------+--------------+-------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ; +; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ; +; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ; +; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ; +; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 29 ; 29 ; +; Unconstrained Input Port Paths ; 169 ; 169 ; +; Unconstrained Output Ports ; 48 ; 48 ; +; Unconstrained Output Port Paths ; 67 ; 67 ; ++---------------------------------+-------+------+ + + ++-------------------------------------+ +; Clock Status Summary ; ++--------+-------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++--------+-------+------+-------------+ +; ARCLK ; ARCLK ; Base ; Constrained ; +; C14M ; C14M ; Base ; Constrained ; +; DRCLK ; DRCLK ; Base ; Constrained ; ++--------+-------+------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; Ain[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PHI1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nWE80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; CKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; Ain[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PHI1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nWE80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; CKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Thu Sep 21 05:34:43 2023 +Info: Command: quartus_sta RAM2E-MAXII -c RAM2E +Info: qsta_default_script.tcl version: #1 +Info (20032): Parallel compilation is enabled and will use up to 4 processors +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332104): Reading SDC File: '../RAM2E.sdc' +Info (332104): Reading SDC File: '../RAM2E-MAX.sdc' +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. +Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -23.265 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -23.265 -23.265 DRCLK + Info (332119): -23.125 -23.125 ARCLK + Info (332119): -8.026 -92.836 C14M +Info (332146): Worst-case hold slack is -16.874 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -16.874 -16.874 ARCLK + Info (332119): -16.746 -16.746 DRCLK + Info (332119): 1.415 0.000 C14M +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 34.654 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 34.654 0.000 C14M + Info (332119): 70.000 0.000 ARCLK + Info (332119): 70.000 0.000 DRCLK +Info (332001): The selected device family is not supported by the report_metastability command. +Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. +Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 13089 megabytes + Info: Processing ended: Thu Sep 21 05:34:45 2023 + Info: Elapsed time: 00:00:02 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/CPLD/MAXII/output_files/RAM2E.sta.summary b/CPLD/MAXII/output_files/RAM2E.sta.summary new file mode 100644 index 0000000..8103b71 --- /dev/null +++ b/CPLD/MAXII/output_files/RAM2E.sta.summary @@ -0,0 +1,41 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Setup 'DRCLK' +Slack : -23.265 +TNS : -23.265 + +Type : Setup 'ARCLK' +Slack : -23.125 +TNS : -23.125 + +Type : Setup 'C14M' +Slack : -8.026 +TNS : -92.836 + +Type : Hold 'ARCLK' +Slack : -16.874 +TNS : -16.874 + +Type : Hold 'DRCLK' +Slack : -16.746 +TNS : -16.746 + +Type : Hold 'C14M' +Slack : 1.415 +TNS : 0.000 + +Type : Minimum Pulse Width 'C14M' +Slack : 34.654 +TNS : 0.000 + +Type : Minimum Pulse Width 'ARCLK' +Slack : 70.000 +TNS : 0.000 + +Type : Minimum Pulse Width 'DRCLK' +Slack : 70.000 +TNS : 0.000 + +------------------------------------------------------------ diff --git a/CPLD/MAXV/RAM2E-MAXV.qpf b/CPLD/MAXV/RAM2E-MAXV.qpf new file mode 100644 index 0000000..a756065 --- /dev/null +++ b/CPLD/MAXV/RAM2E-MAXV.qpf @@ -0,0 +1,31 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +# Date created = 07:27:32 August 20, 2023 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "19.1" +DATE = "07:27:32 August 20, 2023" + +# Revisions + +PROJECT_REVISION = "RAM2E" diff --git a/CPLD/MAXV/RAM2E.qsf b/CPLD/MAXV/RAM2E.qsf new file mode 100644 index 0000000..d4f161d --- /dev/null +++ b/CPLD/MAXV/RAM2E.qsf @@ -0,0 +1,247 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2019 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +# Date created = 07:27:32 August 20, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# RAM2E_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX V" +set_global_assignment -name DEVICE 5M240ZT100C5 +set_global_assignment -name TOP_LEVEL_ENTITY RAM2E +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 19.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:27:32 AUGUST 20, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "19.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name NUM_PARALLEL_PROCESSORS 4 +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND" + +set_location_assignment PIN_12 -to C14M +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C14M + +set_location_assignment PIN_37 -to PHI1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI1 +set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to PHI1 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI1 + +set_location_assignment PIN_51 -to nWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE + +set_location_assignment PIN_28 -to nEN80 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nEN80 +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nEN80 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80 + +set_location_assignment PIN_33 -to nWE80 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80 +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80 + +set_location_assignment PIN_52 -to nC07X +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nC07X +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nC07X +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nC07X + +set_location_assignment PIN_56 -to Ain[0] +set_location_assignment PIN_54 -to Ain[1] +set_location_assignment PIN_43 -to Ain[2] +set_location_assignment PIN_47 -to Ain[3] +set_location_assignment PIN_44 -to Ain[4] +set_location_assignment PIN_34 -to Ain[5] +set_location_assignment PIN_39 -to Ain[6] +set_location_assignment PIN_53 -to Ain[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Ain +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Ain +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Ain + +set_location_assignment PIN_38 -to Din[0] +set_location_assignment PIN_40 -to Din[1] +set_location_assignment PIN_42 -to Din[2] +set_location_assignment PIN_41 -to Din[3] +set_location_assignment PIN_48 -to Din[4] +set_location_assignment PIN_49 -to Din[5] +set_location_assignment PIN_36 -to Din[6] +set_location_assignment PIN_35 -to Din[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Din +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Din + +set_location_assignment PIN_55 -to nDOE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE + +set_location_assignment PIN_77 -to Dout[0] +set_location_assignment PIN_76 -to Dout[1] +set_location_assignment PIN_74 -to Dout[2] +set_location_assignment PIN_75 -to Dout[3] +set_location_assignment PIN_73 -to Dout[4] +set_location_assignment PIN_72 -to Dout[5] +set_location_assignment PIN_84 -to Dout[6] +set_location_assignment PIN_85 -to Dout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout +set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout + +set_location_assignment PIN_50 -to nVOE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE + +set_location_assignment PIN_70 -to Vout[0] +set_location_assignment PIN_67 -to Vout[1] +set_location_assignment PIN_69 -to Vout[2] +set_location_assignment PIN_62 -to Vout[3] +set_location_assignment PIN_71 -to Vout[4] +set_location_assignment PIN_68 -to Vout[5] +set_location_assignment PIN_58 -to Vout[6] +set_location_assignment PIN_57 -to Vout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Vout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Vout +set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout + +set_location_assignment PIN_4 -to CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE +set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE + +set_location_assignment PIN_8 -to nCS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS + +set_location_assignment PIN_2 -to nRWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE + +set_location_assignment PIN_5 -to nRAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS + +set_location_assignment PIN_3 -to nCAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS + +set_location_assignment PIN_6 -to BA[0] +set_location_assignment PIN_14 -to BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to BA +set_instance_assignment -name SLOW_SLEW_RATE ON -to BA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA + +set_location_assignment PIN_18 -to RA[0] +set_location_assignment PIN_20 -to RA[1] +set_location_assignment PIN_30 -to RA[2] +set_location_assignment PIN_27 -to RA[3] +set_location_assignment PIN_26 -to RA[4] +set_location_assignment PIN_29 -to RA[5] +set_location_assignment PIN_21 -to RA[6] +set_location_assignment PIN_19 -to RA[7] +set_location_assignment PIN_17 -to RA[8] +set_location_assignment PIN_15 -to RA[9] +set_location_assignment PIN_16 -to RA[10] +set_location_assignment PIN_7 -to RA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA +set_instance_assignment -name SLOW_SLEW_RATE ON -to RA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA + +set_location_assignment PIN_100 -to DQMH +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQMH +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH + +set_location_assignment PIN_98 -to DQML +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQML +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML + +set_location_assignment PIN_97 -to RD[0] +set_location_assignment PIN_90 -to RD[1] +set_location_assignment PIN_99 -to RD[2] +set_location_assignment PIN_89 -to RD[3] +set_location_assignment PIN_91 -to RD[4] +set_location_assignment PIN_92 -to RD[5] +set_location_assignment PIN_95 -to RD[6] +set_location_assignment PIN_96 -to RD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD +set_instance_assignment -name SLOW_SLEW_RATE ON -to RD +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD + +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name VERILOG_FILE "../RAM2E-MAX.v" +set_global_assignment -name QIP_FILE UFM.qip +set_global_assignment -name MIF_FILE ../RAM2E.mif +set_global_assignment -name SDC_FILE ../RAM2E.sdc +set_global_assignment -name SDC_FILE "../RAM2E-MAX.sdc" +set_location_assignment PIN_88 -to LED +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to LED +set_instance_assignment -name SLOW_SLEW_RATE ON -to LED \ No newline at end of file diff --git a/CPLD/MAXV/RAM2E.qws b/CPLD/MAXV/RAM2E.qws new file mode 100644 index 0000000000000000000000000000000000000000..8de3d3ecec64b3ff743c66893051e3ad1a1fae78 GIT binary patch literal 619 zcmbV}y-LGS6vzLG4njNh0UR7eLLt)D3XbC7jWk-8%b+CHKklYb_pRdc=!zasn2hVJ7eVAvVg$kRq(9CzX2&NLYYX~a{ z6Lji2cjgJ+7>25@51SMXk=DE}$Rz)T_?YXa-}e + + + + + + + diff --git a/CPLD/MAXV/output_files/RAM2E.map.rpt b/CPLD/MAXV/output_files/RAM2E.map.rpt new file mode 100644 index 0000000..6f3badf --- /dev/null +++ b/CPLD/MAXV/output_files/RAM2E.map.rpt @@ -0,0 +1,306 @@ +Analysis & Synthesis report for RAM2E +Thu Sep 21 05:34:33 2023 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Analysis & Synthesis IP Cores Summary + 9. General Register Statistics + 10. Inverted Register Statistics + 11. Multiplexer Restructuring Statistics (Restructuring Performed) + 12. Port Connectivity Checks: "UFM:UFM_inst" + 13. Analysis & Synthesis Messages + 14. Analysis & Synthesis Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2019 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++---------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-----------------------------+---------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Thu Sep 21 05:34:33 2023 ; +; Quartus Prime Version ; 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Revision Name ; RAM2E ; +; Top-level Entity Name ; RAM2E ; +; Family ; MAX V ; +; Total logic elements ; 205 ; +; Total pins ; 70 ; +; Total virtual pins ; 0 ; +; UFM blocks ; 1 / 1 ( 100 % ) ; ++-----------------------------+---------------------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++------------------------------------------------------------------+--------------------+--------------------+ +; Device ; 5M240ZT100C5 ; ; +; Top-level entity name ; RAM2E ; RAM2E ; +; Family name ; MAX V ; Cyclone V ; +; Maximum processors allowed for parallel compilation ; 4 ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Block Design Naming ; Auto ; Auto ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ++------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+ +; ../RAM2E-MAX.v ; yes ; User Verilog HDL File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v ; ; +; UFM.v ; yes ; User Wizard-Generated File ; //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v ; ; +; ../RAM2E.mif ; yes ; User Memory Initialization File ; //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E.mif ; ; ++----------------------------------+-----------------+----------------------------------+-------------------------------------------+---------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Total logic elements ; 205 ; +; -- Combinational with no register ; 93 ; +; -- Register only ; 27 ; +; -- Combinational with a register ; 85 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 103 ; +; -- 3 input functions ; 29 ; +; -- 2 input functions ; 42 ; +; -- 1 input functions ; 3 ; +; -- 0 input functions ; 1 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 191 ; +; -- arithmetic mode ; 14 ; +; -- qfbk mode ; 0 ; +; -- register cascade mode ; 0 ; +; -- synchronous clear/load mode ; 1 ; +; -- asynchronous clear/load mode ; 0 ; +; ; ; +; Total registers ; 112 ; +; Total logic cells in carry chains ; 15 ; +; I/O pins ; 70 ; +; UFM blocks ; 1 ; +; Maximum fan-out node ; C14M ; +; Maximum fan-out ; 112 ; +; Total fan-out ; 850 ; +; Average fan-out ; 3.08 ; ++---------------------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Entity Name ; Library Name ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ +; |RAM2E ; 205 (205) ; 112 ; 1 ; 70 ; 0 ; 93 (93) ; 27 (27) ; 85 (85) ; 15 (15) ; 0 (0) ; |RAM2E ; RAM2E ; work ; +; |UFM:UFM_inst| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst ; UFM ; work ; +; |UFM_altufm_none_p8r:UFM_altufm_none_p8r_component| ; 0 (0) ; 0 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |RAM2E|UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component ; UFM_altufm_none_p8r ; work ; ++-----------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-----------------------------------------------------------------------+---------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++--------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis IP Cores Summary ; ++--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+ +; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; ++--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+ +; Altera ; ALTUFM_NONE Intel FPGA IP ; 19.1 ; N/A ; N/A ; |RAM2E|UFM:UFM_inst ; UFM.v ; ++--------+---------------------------+---------+--------------+--------------+---------------------+-----------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 112 ; +; Number of registers using Synchronous Clear ; 1 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 0 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 60 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------+ +; Inverted Register Statistics ; ++----------------------------------------+---------+ +; Inverted Register ; Fan out ; ++----------------------------------------+---------+ +; nCS~reg0 ; 1 ; +; nRAS~reg0 ; 1 ; +; nCAS~reg0 ; 1 ; +; nRWE~reg0 ; 1 ; +; DQML~reg0 ; 1 ; +; DQMH~reg0 ; 1 ; +; Total number of inverted registers = 6 ; ; ++----------------------------------------+---------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |RAM2E|RA[0]~reg0 ; +; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |RAM2E|S[2] ; +; 4:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |RAM2E|CS[0] ; +; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |RAM2E|RWMask[4] ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ + + ++------------------------------------------------------------------------------------------------------------------+ +; Port Connectivity Checks: "UFM:UFM_inst" ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ +; Port ; Type ; Severity ; Details ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ +; ardin ; Input ; Info ; Stuck at GND ; +; oscena ; Input ; Info ; Stuck at VCC ; +; osc ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ++--------+--------+----------+-------------------------------------------------------------------------------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Analysis & Synthesis + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Thu Sep 21 05:33:58 2023 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RAM2E-MAXV -c RAM2E +Info (20032): Parallel compilation is enabled and will use up to 4 processors +Info (12021): Found 1 design units, including 1 entities, in source file //mac/icloud/repos/ram2e/cpld/ram2e-max.v + Info (12023): Found entity 1: RAM2E File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 1 +Info (12021): Found 2 design units, including 2 entities, in source file ufm.v + Info (12023): Found entity 1: UFM_altufm_none_p8r File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 47 + Info (12023): Found entity 2: UFM File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 166 +Info (12127): Elaborating entity "RAM2E" for the top level hierarchy +Info (12128): Elaborating entity "UFM" for hierarchy "UFM:UFM_inst" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 93 +Info (12128): Elaborating entity "UFM_altufm_none_p8r" for hierarchy "UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component" File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 217 +Info (21057): Implemented 276 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 22 input pins + Info (21059): Implemented 40 output pins + Info (21060): Implemented 8 bidirectional pins + Info (21061): Implemented 205 logic cells + Info (21070): Implemented 1 User Flash Memory blocks +Info (144001): Generated suppressed messages file /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg +Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 13144 megabytes + Info: Processing ended: Thu Sep 21 05:34:33 2023 + Info: Elapsed time: 00:00:35 + Info: Total CPU time (on all processors): 00:00:50 + + ++------------------------------------------+ +; Analysis & Synthesis Suppressed Messages ; ++------------------------------------------+ +The suppressed messages can be found in /Repos/RAM2E/CPLD/MAXV/output_files/RAM2E.map.smsg. + + diff --git a/CPLD/MAXV/output_files/RAM2E.map.smsg b/CPLD/MAXV/output_files/RAM2E.map.smsg new file mode 100644 index 0000000..0b3ca79 --- /dev/null +++ b/CPLD/MAXV/output_files/RAM2E.map.smsg @@ -0,0 +1,3 @@ +Warning (10273): Verilog HDL warning at RAM2E-MAX.v(46): extended using "x" or "z" File: //Mac/iCloud/Repos/RAM2E/CPLD/RAM2E-MAX.v Line: 46 +Warning (10463): Verilog HDL Declaration warning at UFM.v(73): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 73 +Warning (10463): Verilog HDL Declaration warning at UFM.v(189): "program" is SystemVerilog-2005 keyword File: //Mac/iCloud/Repos/RAM2E/CPLD/MAXV/UFM.v Line: 189 diff --git a/CPLD/MAXV/output_files/RAM2E.map.summary b/CPLD/MAXV/output_files/RAM2E.map.summary new file mode 100644 index 0000000..e2665d6 --- /dev/null +++ b/CPLD/MAXV/output_files/RAM2E.map.summary @@ -0,0 +1,9 @@ +Analysis & Synthesis Status : Successful - Thu Sep 21 05:34:33 2023 +Quartus Prime Version : 19.1.0 Build 670 09/22/2019 SJ Lite Edition +Revision Name : RAM2E +Top-level Entity Name : RAM2E +Family : MAX V +Total logic elements : 205 +Total pins : 70 +Total virtual pins : 0 +UFM blocks : 1 / 1 ( 100 % ) diff --git a/CPLD/MAXV/output_files/RAM2E.pin b/CPLD/MAXV/output_files/RAM2E.pin new file mode 100644 index 0000000..e88a551 --- /dev/null +++ b/CPLD/MAXV/output_files/RAM2E.pin @@ -0,0 +1,165 @@ + -- Copyright (C) 2019 Intel Corporation. All rights reserved. + -- Your use of Intel Corporation's design tools, logic functions + -- and other software and tools, and any partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Intel Program License + -- Subscription Agreement, the Intel Quartus Prime License Agreement, + -- the Intel FPGA IP License Agreement, or other applicable license + -- agreement, including, without limitation, that your use is for + -- the sole purpose of programming logic devices manufactured by + -- Intel and sold by Intel or its authorized distributors. Please + -- refer to the applicable agreement for further details, at + -- https://fpgasoftware.intel.com/eula. + -- + -- This is a Quartus Prime output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus Prime input file. This file cannot be used + -- to make Quartus Prime pin assignments - for instructions on how to make pin + -- assignments, please see Quartus Prime help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.8V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition +CHIP "RAM2E" ASSIGNED TO AN: 5M240ZT100C5 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : 1 : gnd : : : : +nRWE : 2 : output : 3.3-V LVCMOS : : 1 : Y +nCAS : 3 : output : 3.3-V LVCMOS : : 1 : Y +CKE : 4 : output : 3.3-V LVCMOS : : 1 : Y +nRAS : 5 : output : 3.3-V LVCMOS : : 1 : Y +BA[0] : 6 : output : 3.3-V LVCMOS : : 1 : Y +RA[11] : 7 : output : 3.3-V LVCMOS : : 1 : Y +nCS : 8 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 9 : power : : 3.3V : 1 : +GND : 10 : gnd : : : : +GND : 11 : gnd : : : : +C14M : 12 : input : 3.3-V LVCMOS : : 1 : Y +VCCINT : 13 : power : : 1.8V : : +BA[1] : 14 : output : 3.3-V LVCMOS : : 1 : Y +RA[9] : 15 : output : 3.3-V LVCMOS : : 1 : Y +RA[10] : 16 : output : 3.3-V LVCMOS : : 1 : Y +RA[8] : 17 : output : 3.3-V LVCMOS : : 1 : Y +RA[0] : 18 : output : 3.3-V LVCMOS : : 1 : Y +RA[7] : 19 : output : 3.3-V LVCMOS : : 1 : Y +RA[1] : 20 : output : 3.3-V LVCMOS : : 1 : Y +RA[6] : 21 : output : 3.3-V LVCMOS : : 1 : Y +TMS : 22 : input : : : 1 : +TDI : 23 : input : : : 1 : +TCK : 24 : input : : : 1 : +TDO : 25 : output : : : 1 : +RA[4] : 26 : output : 3.3-V LVCMOS : : 1 : Y +RA[3] : 27 : output : 3.3-V LVCMOS : : 1 : Y +nEN80 : 28 : input : 3.3-V LVCMOS : : 1 : Y +RA[5] : 29 : output : 3.3-V LVCMOS : : 1 : Y +RA[2] : 30 : output : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 31 : power : : 3.3V : 1 : +GND : 32 : gnd : : : : +nWE80 : 33 : input : 3.3-V LVCMOS : : 1 : Y +Ain[5] : 34 : input : 3.3-V LVCMOS : : 1 : Y +Din[7] : 35 : input : 3.3-V LVCMOS : : 1 : Y +Din[6] : 36 : input : 3.3-V LVCMOS : : 1 : Y +PHI1 : 37 : input : 3.3-V LVCMOS : : 1 : Y +Din[0] : 38 : input : 3.3-V LVCMOS : : 1 : Y +Ain[6] : 39 : input : 3.3-V LVCMOS : : 1 : Y +Din[1] : 40 : input : 3.3-V LVCMOS : : 1 : Y +Din[3] : 41 : input : 3.3-V LVCMOS : : 1 : Y +Din[2] : 42 : input : 3.3-V LVCMOS : : 1 : Y +Ain[2] : 43 : input : 3.3-V LVCMOS : : 1 : Y +Ain[4] : 44 : input : 3.3-V LVCMOS : : 1 : Y +VCCIO1 : 45 : power : : 3.3V : 1 : +GND : 46 : gnd : : : : +Ain[3] : 47 : input : 3.3-V LVCMOS : : 1 : Y +Din[4] : 48 : input : 3.3-V LVCMOS : : 1 : Y +Din[5] : 49 : input : 3.3-V LVCMOS : : 1 : Y +nVOE : 50 : output : 3.3-V LVCMOS : : 1 : Y +nWE : 51 : input : 3.3-V LVCMOS : : 1 : Y +nC07X : 52 : input : 3.3-V LVCMOS : : 2 : Y +Ain[7] : 53 : input : 3.3-V LVCMOS : : 2 : Y +Ain[1] : 54 : input : 3.3-V LVCMOS : : 2 : Y +nDOE : 55 : output : 3.3-V LVCMOS : : 2 : Y +Ain[0] : 56 : input : 3.3-V LVCMOS : : 2 : Y +Vout[7] : 57 : output : 3.3-V LVCMOS : : 2 : Y +Vout[6] : 58 : output : 3.3-V LVCMOS : : 2 : Y +VCCIO2 : 59 : power : : 3.3V : 2 : +GND : 60 : gnd : : : : +GND* : 61 : : : : 2 : +Vout[3] : 62 : output : 3.3-V LVCMOS : : 2 : Y +VCCINT : 63 : power : : 1.8V : : +GND* : 64 : : : : 2 : +GND : 65 : gnd : : : : +GND* : 66 : : : : 2 : +Vout[1] : 67 : output : 3.3-V LVCMOS : : 2 : Y +Vout[5] : 68 : output : 3.3-V LVCMOS : : 2 : Y +Vout[2] : 69 : output : 3.3-V LVCMOS : : 2 : Y +Vout[0] : 70 : output : 3.3-V LVCMOS : : 2 : Y +Vout[4] : 71 : output : 3.3-V LVCMOS : : 2 : Y +Dout[5] : 72 : output : 3.3-V LVCMOS : : 2 : Y +Dout[4] : 73 : output : 3.3-V LVCMOS : : 2 : Y +Dout[2] : 74 : output : 3.3-V LVCMOS : : 2 : Y +Dout[3] : 75 : output : 3.3-V LVCMOS : : 2 : Y +Dout[1] : 76 : output : 3.3-V LVCMOS : : 2 : Y +Dout[0] : 77 : output : 3.3-V LVCMOS : : 2 : Y +GND* : 78 : : : : 2 : +GND : 79 : gnd : : : : +VCCIO2 : 80 : power : : 3.3V : 2 : +GND* : 81 : : : : 2 : +GND* : 82 : : : : 2 : +GND* : 83 : : : : 2 : +Dout[6] : 84 : output : 3.3-V LVCMOS : : 2 : Y +Dout[7] : 85 : output : 3.3-V LVCMOS : : 2 : Y +GND* : 86 : : : : 2 : +GND* : 87 : : : : 2 : +LED : 88 : output : 3.3-V LVTTL : : 2 : Y +RD[3] : 89 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[1] : 90 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[4] : 91 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[5] : 92 : bidir : 3.3-V LVCMOS : : 2 : Y +GND : 93 : gnd : : : : +VCCIO2 : 94 : power : : 3.3V : 2 : +RD[6] : 95 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[7] : 96 : bidir : 3.3-V LVCMOS : : 2 : Y +RD[0] : 97 : bidir : 3.3-V LVCMOS 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Analyzer report for RAM2E +Thu Sep 21 05:34:46 2023 +Quartus Prime Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Parallel Compilation + 4. SDC File List + 5. Clocks + 6. Fmax Summary + 7. Setup Summary + 8. Hold Summary + 9. Recovery Summary + 10. Removal Summary + 11. Minimum Pulse Width Summary + 12. Setup: 'DRCLK' + 13. Setup: 'ARCLK' + 14. Setup: 'C14M' + 15. Hold: 'ARCLK' + 16. Hold: 'DRCLK' + 17. Hold: 'C14M' + 18. Setup Transfers + 19. Hold Transfers + 20. Report TCCS + 21. Report RSKM + 22. Unconstrained Paths Summary + 23. Clock Status Summary + 24. Unconstrained Input Ports + 25. Unconstrained Output Ports + 26. Unconstrained Input Ports + 27. Unconstrained Output Ports + 28. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 2019 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. + + + ++-----------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++-----------------------+-----------------------------------------------------+ +; Quartus Prime Version ; Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition ; +; Timing Analyzer ; Legacy Timing Analyzer ; +; Revision Name ; RAM2E ; +; Device Family ; MAX V ; +; Device Name ; 5M240ZT100C5 ; +; Timing Models ; Final ; +; Delay Model ; Slow Model ; +; Rise/Fall Delays ; Unavailable ; ++-----------------------+-----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 4 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 0.0% ; ++----------------------------+-------------+ + + ++------------------------------------------------------+ +; SDC File List ; ++------------------+--------+--------------------------+ +; SDC File Path ; Status ; Read at ; ++------------------+--------+--------------------------+ +; ../RAM2E.sdc ; OK ; Thu Sep 21 05:34:45 2023 ; +; ../RAM2E-MAX.sdc ; OK ; Thu Sep 21 05:34:45 2023 ; ++------------------+--------+--------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ +; ARCLK ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { ARCLK } ; +; C14M ; Base ; 69.841 ; 14.32 MHz ; 0.000 ; 34.920 ; ; ; ; ; ; ; ; ; ; ; { C14M } ; +; DRCLK ; Base ; 200.000 ; 5.0 MHz ; 0.000 ; 100.000 ; ; ; ; ; ; ; ; ; ; ; { DRCLK } ; ++------------+------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+ + + ++-------------------------------------------------+ +; Fmax Summary ; ++-----------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++-----------+-----------------+------------+------+ +; 10.0 MHz ; 10.0 MHz ; ARCLK ; ; +; 10.0 MHz ; 10.0 MHz ; DRCLK ; ; +; 25.52 MHz ; 25.52 MHz ; C14M ; ; ++-----------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++---------------------------------+ +; Setup Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; DRCLK ; -24.019 ; -24.019 ; +; ARCLK ; -23.863 ; -23.863 ; +; C14M ; -15.767 ; -176.992 ; ++-------+---------+---------------+ + + ++---------------------------------+ +; Hold Summary ; ++-------+---------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+---------+---------------+ +; ARCLK ; -16.136 ; -16.136 ; +; DRCLK ; -15.980 ; -15.980 ; +; C14M ; 2.440 ; 0.000 ; ++-------+---------+---------------+ + + +-------------------- +; Recovery Summary ; +-------------------- +No paths to report. + + +------------------- +; Removal Summary ; +------------------- +No paths to report. + + ++--------------------------------+ +; Minimum Pulse Width Summary ; ++-------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------+ +; C14M ; 34.581 ; 0.000 ; +; ARCLK ; 70.000 ; 0.000 ; +; DRCLK ; 70.000 ; 0.000 ; ++-------+--------+---------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -24.019 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.057 ; 2.963 ; +; -24.019 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.001 ; -1.057 ; 2.963 ; +; 100.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 200.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -23.863 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.001 ; -0.901 ; 2.963 ; +; 100.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 200.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Setup: 'C14M' ; ++---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ +; -15.767 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMReqErase ; DRCLK ; C14M ; 0.001 ; 1.057 ; 16.504 ; +; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[4] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ; +; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[5] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ; +; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[7] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ; +; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[0] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ; +; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[1] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ; +; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[2] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ; +; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[3] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ; +; -15.215 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; RWMask[6] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.952 ; +; -14.411 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; LEDEN ; DRCLK ; C14M ; 0.001 ; 1.057 ; 15.148 ; +; -13.177 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMInitDone ; DRCLK ; C14M ; 0.001 ; 1.057 ; 13.914 ; +; -11.917 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFMD[8] ; DRCLK ; C14M ; 0.001 ; 1.057 ; 12.654 ; +; 16.803 ; S[1] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ; +; 16.803 ; S[1] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ; +; 16.803 ; S[1] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ; +; 16.803 ; S[1] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ; +; 16.803 ; S[1] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ; +; 16.803 ; S[1] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.796 ; +; 16.806 ; S[1] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.793 ; +; 16.809 ; S[1] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 17.790 ; +; 18.727 ; S[2] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ; +; 18.727 ; S[2] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ; +; 18.727 ; S[2] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ; +; 18.727 ; S[2] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ; +; 18.727 ; S[2] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ; +; 18.727 ; S[2] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.872 ; +; 18.730 ; S[2] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.869 ; +; 18.733 ; S[2] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.866 ; +; 19.149 ; S[3] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.450 ; +; 19.149 ; S[3] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.450 ; +; 19.196 ; S[3] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.403 ; +; 19.196 ; S[3] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.403 ; +; 19.196 ; S[3] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.403 ; +; 19.260 ; S[0] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.339 ; +; 19.260 ; S[0] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.339 ; +; 19.307 ; S[0] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.292 ; +; 19.307 ; S[0] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.292 ; +; 19.307 ; S[0] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 15.292 ; +; 20.893 ; S[0] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ; +; 20.893 ; S[0] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ; +; 20.893 ; S[0] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ; +; 20.893 ; S[0] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ; +; 20.893 ; S[0] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ; +; 20.893 ; S[0] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.706 ; +; 20.896 ; S[0] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.703 ; +; 20.899 ; S[0] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 13.700 ; +; 22.101 ; S[3] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.498 ; +; 22.101 ; S[3] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.498 ; +; 22.101 ; S[3] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.498 ; +; 22.212 ; S[0] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.387 ; +; 22.212 ; S[0] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.387 ; +; 22.212 ; S[0] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 12.387 ; +; 23.092 ; S[3] ; Dout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ; +; 23.092 ; S[3] ; Dout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ; +; 23.092 ; S[3] ; Dout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ; +; 23.092 ; S[3] ; Dout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ; +; 23.092 ; S[3] ; Dout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ; +; 23.092 ; S[3] ; Dout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.507 ; +; 23.095 ; S[3] ; Dout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.504 ; +; 23.098 ; S[3] ; Dout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 11.501 ; +; 23.710 ; S[1] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.889 ; +; 23.710 ; S[1] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.889 ; +; 23.757 ; S[1] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.842 ; +; 23.757 ; S[1] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.842 ; +; 23.757 ; S[1] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.842 ; +; 24.349 ; S[2] ; Vout[0]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.250 ; +; 24.349 ; S[2] ; Vout[4]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.250 ; +; 24.396 ; S[2] ; Vout[1]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.203 ; +; 24.396 ; S[2] ; Vout[2]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.203 ; +; 24.396 ; S[2] ; Vout[5]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 10.203 ; +; 26.662 ; S[1] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.937 ; +; 26.662 ; S[1] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.937 ; +; 26.662 ; S[1] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.937 ; +; 27.301 ; S[2] ; Vout[3]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.298 ; +; 27.301 ; S[2] ; Vout[6]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.298 ; +; 27.301 ; S[2] ; Vout[7]~reg0 ; C14M ; C14M ; 34.920 ; 0.000 ; 7.298 ; +; 30.659 ; FS[15] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 38.861 ; +; 31.593 ; FS[14] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 37.927 ; +; 32.392 ; FS[15] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 37.128 ; +; 32.513 ; FS[2] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 37.007 ; +; 33.326 ; FS[14] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 36.194 ; +; 33.452 ; FS[15] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 36.068 ; +; 33.715 ; S[1] ; CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 35.805 ; +; 34.111 ; FS[1] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.409 ; +; 34.246 ; FS[2] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.274 ; +; 34.386 ; FS[14] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 35.134 ; +; 35.112 ; FS[11] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 34.408 ; +; 35.288 ; FS[10] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 34.232 ; +; 35.392 ; S[1] ; CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 34.128 ; +; 35.639 ; S[2] ; CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 33.881 ; +; 35.844 ; FS[1] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 33.676 ; +; 36.147 ; FS[8] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 33.373 ; +; 36.765 ; FS[9] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.755 ; +; 36.845 ; FS[11] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.675 ; +; 37.021 ; FS[10] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.499 ; +; 37.152 ; FS[4] ; nRAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 32.368 ; +; 37.316 ; S[2] ; CmdPrgmMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 32.204 ; +; 37.805 ; S[0] ; CmdEraseMAX ; C14M ; C14M ; 69.841 ; 0.000 ; 31.715 ; +; 37.880 ; FS[8] ; nCS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 31.640 ; +; 37.905 ; FS[11] ; nCAS~reg0 ; C14M ; C14M ; 69.841 ; 0.000 ; 31.615 ; ++---------+---------------------------------------------------------------------------------------------+--------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'ARCLK' ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -16.136 ; ARShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; C14M ; ARCLK ; 0.000 ; -0.901 ; 2.963 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|maxii_ufm_block1~OBSERVABLEADDRESSREGOUT ; ARCLK ; ARCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Hold: 'DRCLK' ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +; -15.980 ; DRDIn ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.057 ; 2.963 ; +; -15.980 ; DRShift ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; C14M ; DRCLK ; 0.000 ; -1.057 ; 2.963 ; +; 60.000 ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; UFM:UFM_inst|UFM_altufm_none_p8r:UFM_altufm_none_p8r_component|wire_maxii_ufm_block1_drdout ; DRCLK ; DRCLK ; 0.000 ; 0.000 ; 80.000 ; ++---------+---------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------+ +; Hold: 'C14M' ; ++-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+ +; 2.440 ; UFMBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 2.479 ; +; 3.130 ; UFMD[12] ; UFMD[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.169 ; +; 3.153 ; UFMD[9] ; UFMD[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.192 ; +; 3.166 ; UFMD[14] ; UFMD[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.205 ; +; 3.170 ; UFMD[13] ; UFMD[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.209 ; +; 3.385 ; UFMD[10] ; UFMD[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.424 ; +; 3.414 ; FS[0] ; FS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.453 ; +; 3.442 ; CmdEraseMAX ; CmdEraseMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 3.481 ; +; 3.443 ; S[2] ; S[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.482 ; +; 3.451 ; S[2] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.490 ; +; 3.451 ; CmdTout[0] ; CmdTout[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.490 ; +; 3.453 ; CmdTout[0] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.492 ; +; 3.454 ; CmdTout[0] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.493 ; +; 3.528 ; CS[0] ; CS[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.567 ; +; 3.538 ; CS[0] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.577 ; +; 3.740 ; S[0] ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.779 ; +; 3.740 ; DRDIn ; DRDIn ; C14M ; C14M ; 0.000 ; 0.000 ; 3.779 ; +; 3.741 ; RTPBusyReg ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 3.780 ; +; 3.779 ; RWSel ; RWSel ; C14M ; C14M ; 0.000 ; 0.000 ; 3.818 ; +; 3.810 ; S[1] ; S[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.849 ; +; 3.827 ; CmdPrgmMAX ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 3.866 ; +; 3.831 ; S[1] ; DOEEN ; C14M ; C14M ; 0.000 ; 0.000 ; 3.870 ; +; 3.833 ; CmdTout[1] ; CmdTout[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.872 ; +; 3.839 ; CmdTout[1] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.878 ; +; 3.843 ; CS[2] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 3.882 ; +; 4.011 ; PHI1reg ; S[0] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.050 ; +; 4.210 ; UFMD[8] ; UFMD[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.249 ; +; 4.278 ; CmdEraseMAX ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 4.317 ; +; 4.279 ; UFMD[11] ; UFMD[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 4.318 ; +; 5.056 ; RTPBusyReg ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.095 ; +; 5.228 ; LEDEN ; LEDEN ; C14M ; C14M ; 0.000 ; 0.000 ; 5.267 ; +; 5.241 ; FS[15] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.280 ; +; 5.243 ; FS[5] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.282 ; +; 5.252 ; FS[8] ; FS[8] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.291 ; +; 5.268 ; Ready ; Ready ; C14M ; C14M ; 0.000 ; 0.000 ; 5.307 ; +; 5.272 ; FS[7] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.311 ; +; 5.278 ; FS[10] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.317 ; +; 5.281 ; FS[9] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.320 ; +; 5.286 ; CmdPrgmMAX ; CmdPrgmMAX ; C14M ; C14M ; 0.000 ; 0.000 ; 5.325 ; +; 5.360 ; CS[1] ; CS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.399 ; +; 5.361 ; CS[1] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.400 ; +; 5.440 ; FS[3] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.479 ; +; 5.441 ; FS[4] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.480 ; +; 5.441 ; FS[2] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.480 ; +; 5.442 ; FS[11] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.481 ; +; 5.452 ; FS[1] ; FS[1] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.491 ; +; 5.464 ; FS[14] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.503 ; +; 5.473 ; UFMErase ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.512 ; +; 5.474 ; UFMProgram ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 5.513 ; +; 5.475 ; FS[13] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.514 ; +; 5.476 ; FS[12] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.515 ; +; 5.476 ; FS[6] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.515 ; +; 5.478 ; UFMInitDone ; UFMInitDone ; C14M ; C14M ; 0.000 ; 0.000 ; 5.517 ; +; 5.486 ; CmdTout[2] ; CmdTout[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.525 ; +; 5.541 ; S[3] ; S[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.580 ; +; 5.613 ; CS[0] ; CS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 5.652 ; +; 5.664 ; RWBank[2] ; RA[10]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 5.703 ; +; 5.753 ; CmdPrgmMAX ; UFMErase ; C14M ; C14M ; 0.000 ; 0.000 ; 5.792 ; +; 5.978 ; FS[5] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.017 ; +; 5.987 ; FS[8] ; FS[9] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.026 ; +; 6.013 ; FS[10] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.052 ; +; 6.016 ; FS[9] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.055 ; +; 6.122 ; FS[5] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.161 ; +; 6.131 ; FS[8] ; FS[10] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.170 ; +; 6.157 ; FS[10] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.196 ; +; 6.160 ; FS[9] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.199 ; +; 6.229 ; DRCLKPulse ; DRCLK ; C14M ; C14M ; 0.000 ; 0.000 ; 6.268 ; +; 6.275 ; FS[8] ; FS[11] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.314 ; +; 6.304 ; FS[9] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.343 ; +; 6.419 ; FS[8] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.458 ; +; 6.442 ; FS[3] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.481 ; +; 6.443 ; FS[4] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.482 ; +; 6.444 ; FS[11] ; FS[12] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.483 ; +; 6.454 ; FS[1] ; FS[2] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.493 ; +; 6.466 ; FS[14] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.505 ; +; 6.477 ; FS[13] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.516 ; +; 6.478 ; FS[6] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.517 ; +; 6.507 ; RWBank[5] ; BA[1]~reg0 ; C14M ; C14M ; 0.000 ; 0.000 ; 6.546 ; +; 6.533 ; CmdBitbangMAX ; DRCLKPulse ; C14M ; C14M ; 0.000 ; 0.000 ; 6.572 ; +; 6.586 ; FS[3] ; FS[5] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.625 ; +; 6.587 ; FS[4] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.626 ; +; 6.621 ; FS[13] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.660 ; +; 6.651 ; UFMD[11] ; RWMask[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.690 ; +; 6.724 ; RWMask[4] ; RWBank[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.763 ; +; 6.730 ; FS[3] ; FS[6] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.769 ; +; 6.731 ; FS[4] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.770 ; +; 6.774 ; RWMask[3] ; RWBank[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.813 ; +; 6.793 ; FS[10] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.832 ; +; 6.793 ; FS[10] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.832 ; +; 6.793 ; FS[10] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.832 ; +; 6.816 ; UFMD[15] ; RWMask[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.855 ; +; 6.836 ; CS[0] ; CmdRWMaskSet ; C14M ; C14M ; 0.000 ; 0.000 ; 6.875 ; +; 6.843 ; CS[0] ; CmdSetRWBankFFLED ; C14M ; C14M ; 0.000 ; 0.000 ; 6.882 ; +; 6.874 ; FS[3] ; FS[7] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.913 ; +; 6.895 ; CmdEraseMAX ; UFMProgram ; C14M ; C14M ; 0.000 ; 0.000 ; 6.934 ; +; 6.940 ; FS[9] ; FS[13] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.979 ; +; 6.940 ; FS[9] ; FS[14] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.979 ; +; 6.940 ; FS[9] ; FS[15] ; C14M ; C14M ; 0.000 ; 0.000 ; 6.979 ; +; 6.998 ; FS[2] ; FS[4] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.037 ; +; 6.998 ; FS[2] ; FS[3] ; C14M ; C14M ; 0.000 ; 0.000 ; 7.037 ; ++-------+---------------+-------------------+--------------+-------------+--------------+------------+------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ; +; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ; +; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; ARCLK ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C14M ; ARCLK ; 1 ; 0 ; 0 ; 0 ; +; C14M ; C14M ; 1607 ; 0 ; 64 ; 0 ; +; DRCLK ; C14M ; 13 ; 0 ; 0 ; 0 ; +; C14M ; DRCLK ; 2 ; 0 ; 0 ; 0 ; +; DRCLK ; DRCLK ; 1 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No non-DPA dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths Summary ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 29 ; 29 ; +; Unconstrained Input Port Paths ; 169 ; 169 ; +; Unconstrained Output Ports ; 48 ; 48 ; +; Unconstrained Output Port Paths ; 67 ; 67 ; ++---------------------------------+-------+------+ + + ++-------------------------------------+ +; Clock Status Summary ; ++--------+-------+------+-------------+ +; Target ; Clock ; Type ; Status ; ++--------+-------+------+-------------+ +; ARCLK ; ARCLK ; Base ; Constrained ; +; C14M ; C14M ; Base ; Constrained ; +; DRCLK ; DRCLK ; Base ; Constrained ; ++--------+-------+------+-------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; Ain[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PHI1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nWE80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; CKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++---------------------------------------------------------------------------------------------------+ +; Unconstrained Input Ports ; ++------------+--------------------------------------------------------------------------------------+ +; Input Port ; Comment ; ++------------+--------------------------------------------------------------------------------------+ +; Ain[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Ain[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Din[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; PHI1 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nC07X ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nEN80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nWE ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nWE80 ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ; ++------------+--------------------------------------------------------------------------------------+ + + ++-----------------------------------------------------------------------------------------------------+ +; Unconstrained Output Ports ; ++-------------+---------------------------------------------------------------------------------------+ +; Output Port ; Comment ; ++-------------+---------------------------------------------------------------------------------------+ +; BA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; BA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; CKE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQMH ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; DQML ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Dout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; LED ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[8] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[9] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[10] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RA[11] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; RD[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; Vout[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nCS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nDOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRAS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nRWE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; +; nVOE ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ; ++-------------+---------------------------------------------------------------------------------------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus Prime Timing Analyzer + Info: Version 19.1.0 Build 670 09/22/2019 SJ Lite Edition + Info: Processing started: Thu Sep 21 05:34:43 2023 +Info: Command: quartus_sta RAM2E-MAXV -c RAM2E +Info: qsta_default_script.tcl version: #1 +Info (20032): Parallel compilation is enabled and will use up to 4 processors +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (334003): Started post-fitting delay annotation +Info (334004): Delay annotation completed successfully +Info (332104): Reading SDC File: '../RAM2E.sdc' +Info (332104): Reading SDC File: '../RAM2E-MAX.sdc' +Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Can't run Report Timing Closure Recommendations. The current device family is not supported. +Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. +Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -24.019 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -24.019 -24.019 DRCLK + Info (332119): -23.863 -23.863 ARCLK + Info (332119): -15.767 -176.992 C14M +Info (332146): Worst-case hold slack is -16.136 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): -16.136 -16.136 ARCLK + Info (332119): -15.980 -15.980 DRCLK + Info (332119): 2.440 0.000 C14M +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is 34.581 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= =================== ===================== + Info (332119): 34.581 0.000 C14M + Info (332119): 70.000 0.000 ARCLK + Info (332119): 70.000 0.000 DRCLK +Info (332001): The selected device family is not supported by the report_metastability command. +Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: ARCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. +Warning (332009): The launch and latch times for the relationship between source clock: C14M and destination clock: DRCLK are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 13092 megabytes + Info: Processing ended: Thu Sep 21 05:34:46 2023 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/CPLD/MAXV/output_files/RAM2E.sta.summary b/CPLD/MAXV/output_files/RAM2E.sta.summary new file mode 100644 index 0000000..3d31fdf --- /dev/null +++ b/CPLD/MAXV/output_files/RAM2E.sta.summary @@ -0,0 +1,41 @@ +------------------------------------------------------------ +Timing Analyzer Summary +------------------------------------------------------------ + +Type : Setup 'DRCLK' +Slack : -24.019 +TNS : -24.019 + +Type : Setup 'ARCLK' +Slack : -23.863 +TNS : -23.863 + +Type : Setup 'C14M' +Slack : -15.767 +TNS : -176.992 + +Type : Hold 'ARCLK' +Slack : -16.136 +TNS : -16.136 + +Type : Hold 'DRCLK' +Slack : -15.980 +TNS : -15.980 + +Type : Hold 'C14M' +Slack : 2.440 +TNS : 0.000 + +Type : Minimum Pulse Width 'C14M' +Slack : 34.581 +TNS : 0.000 + +Type : Minimum Pulse Width 'ARCLK' +Slack : 70.000 +TNS : 0.000 + +Type : Minimum Pulse Width 'DRCLK' +Slack : 70.000 +TNS : 0.000 + +------------------------------------------------------------ diff --git a/CPLD/RAM2E-LCMXO2.lpf b/CPLD/RAM2E-LCMXO2.lpf new file mode 100644 index 0000000..ef9437f --- /dev/null +++ b/CPLD/RAM2E-LCMXO2.lpf @@ -0,0 +1,190 @@ +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +LOCATE COMP "Ain[0]" SITE "3" ; +LOCATE COMP "Ain[1]" SITE "2" ; +LOCATE COMP "Ain[2]" SITE "7" ; +LOCATE COMP "Ain[3]" SITE "4" ; +LOCATE COMP "Ain[4]" SITE "78" ; +LOCATE COMP "Ain[5]" SITE "84" ; +LOCATE COMP "Ain[6]" SITE "86" ; +LOCATE COMP "Ain[7]" SITE "8" ; +LOCATE COMP "C14M" SITE "62" ; +LOCATE COMP "Din[0]" SITE "96" ; +LOCATE COMP "Din[1]" SITE "97" ; +LOCATE COMP "Din[2]" SITE "98" ; +LOCATE COMP "Din[5]" SITE "99" ; +LOCATE COMP "Din[4]" SITE "1" ; +LOCATE COMP "Din[6]" SITE "88" ; +LOCATE COMP "Din[7]" SITE "87" ; +LOCATE COMP "PHI1" SITE "85" ; +LOCATE COMP "nC07X" SITE "34" ; +LOCATE COMP "nEN80" SITE "82" ; +LOCATE COMP "nWE" SITE "29" ; +LOCATE COMP "nWE80" SITE "83" ; +LOCATE COMP "BA[0]" SITE "58" ; +LOCATE COMP "BA[1]" SITE "60" ; +LOCATE COMP "CKE" SITE "53" ; +LOCATE COMP "DQMH" SITE "49" ; +LOCATE COMP "DQML" SITE "48" ; +LOCATE COMP "Dout[0]" SITE "30" ; +LOCATE COMP "Dout[1]" SITE "27" ; +LOCATE COMP "Dout[2]" SITE "25" ; +LOCATE COMP "Dout[3]" SITE "28" ; +LOCATE COMP "Dout[4]" SITE "24" ; +LOCATE COMP "Dout[5]" SITE "21" ; +LOCATE COMP "Dout[6]" SITE "31" ; +LOCATE COMP "Dout[7]" SITE "32" ; +LOCATE COMP "LED" SITE "35" ; +LOCATE COMP "RA[0]" SITE "66" ; +LOCATE COMP "RA[1]" SITE "68" ; +LOCATE COMP "RA[2]" SITE "70" ; +LOCATE COMP "RA[3]" SITE "74" ; +LOCATE COMP "RA[4]" SITE "75" ; +LOCATE COMP "RA[5]" SITE "71" ; +LOCATE COMP "RA[7]" SITE "67" ; +LOCATE COMP "RA[6]" SITE "69" ; +LOCATE COMP "RA[8]" SITE "65" ; +LOCATE COMP "RA[9]" SITE "63" ; +LOCATE COMP "RA[10]" SITE "64" ; +LOCATE COMP "RA[11]" SITE "59" ; +LOCATE COMP "Vout[0]" SITE "18" ; +LOCATE COMP "Vout[1]" SITE "15" ; +LOCATE COMP "Vout[2]" SITE "17" ; +LOCATE COMP "Vout[3]" SITE "13" ; +LOCATE COMP "Vout[4]" SITE "19" ; +LOCATE COMP "Vout[5]" SITE "16" ; +LOCATE COMP "Vout[6]" SITE "14" ; +LOCATE COMP "Vout[7]" SITE "12" ; +LOCATE COMP "nCAS" SITE "52" ; +LOCATE COMP "nCS" SITE "57" ; +LOCATE COMP "nDOE" SITE "20" ; +LOCATE COMP "nRAS" SITE "54" ; +LOCATE COMP "nRWE" SITE "51" ; +LOCATE COMP "nVOE" SITE "10" ; +LOCATE COMP "RD[0]" SITE "36" ; +LOCATE COMP "RD[1]" SITE "37" ; +LOCATE COMP "RD[2]" SITE "38" ; +LOCATE COMP "RD[3]" SITE "39" ; +LOCATE COMP "RD[4]" SITE "40" ; +LOCATE COMP "RD[5]" SITE "41" ; +LOCATE COMP "RD[6]" SITE "42" ; +LOCATE COMP "RD[7]" SITE "43" ; +IOBUF PORT "Ain[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Ain[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Ain[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Ain[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Ain[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Ain[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Ain[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Ain[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "C14M" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Din[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Din[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Din[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Din[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Din[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Din[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Din[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "Din[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "PHI1" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "nC07X" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "nEN80" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "nWE" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "nWE80" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "BA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "BA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "CKE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "DQMH" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "DQML" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "Dout[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ; +IOBUF PORT "Dout[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ; +IOBUF PORT "Dout[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ; +IOBUF PORT "Dout[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ; +IOBUF PORT "Dout[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ; +IOBUF PORT "Dout[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ; +IOBUF PORT "Dout[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ; +IOBUF PORT "Dout[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 SLEWRATE=FAST ; +IOBUF PORT "LED" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[8]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[9]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[10]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RA[11]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "Vout[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "Vout[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "Vout[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "Vout[3]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "Vout[4]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "Vout[5]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "Vout[6]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "Vout[7]" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "nCAS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "nCS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "nDOE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "nRAS" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "nRWE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "nVOE" IO_TYPE=LVCMOS33 PULLMODE=NONE DRIVE=4 ; +IOBUF PORT "RD[0]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ; +IOBUF PORT "RD[1]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ; +IOBUF PORT "RD[2]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ; +IOBUF PORT "RD[3]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ; +IOBUF PORT "RD[4]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ; +IOBUF PORT "RD[5]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ; +IOBUF PORT "RD[6]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ; +IOBUF PORT "RD[7]" IO_TYPE=LVCMOS33 PULLMODE=KEEPER DRIVE=4 CLAMP=ON ; +OUTPUT PORT "LED" LOAD 100.000000 pF ; +OUTPUT PORT "BA[1]" LOAD 5.000000 pF ; +OUTPUT PORT "BA[0]" LOAD 5.000000 pF ; +OUTPUT PORT "CKE" LOAD 5.000000 pF ; +OUTPUT PORT "DQMH" LOAD 5.000000 pF ; +OUTPUT PORT "DQML" LOAD 5.000000 pF ; +OUTPUT PORT "Dout[0]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[1]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[2]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[3]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[4]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[5]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[6]" LOAD 15.000000 pF ; +OUTPUT PORT "Dout[7]" LOAD 15.000000 pF ; +OUTPUT PORT "RA[0]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[1]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[2]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[3]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[4]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[5]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[6]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[7]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[8]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[9]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[10]" LOAD 5.000000 pF ; +OUTPUT PORT "RA[11]" LOAD 5.000000 pF ; +OUTPUT PORT "Vout[0]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[1]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[2]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[3]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[4]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[5]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[6]" LOAD 15.000000 pF ; +OUTPUT PORT "Vout[7]" LOAD 15.000000 pF ; +OUTPUT PORT "nCAS" LOAD 5.000000 pF ; +OUTPUT PORT "nCS" LOAD 5.000000 pF ; +OUTPUT PORT "nDOE" LOAD 10.000000 pF ; +OUTPUT PORT "nRAS" LOAD 5.000000 pF ; +OUTPUT PORT "nRWE" LOAD 5.000000 pF ; +OUTPUT PORT "nVOE" LOAD 10.000000 pF ; +OUTPUT PORT "RD[0]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[1]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[2]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[3]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[4]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[5]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[6]" LOAD 9.000000 pF ; +OUTPUT PORT "RD[7]" LOAD 9.000000 pF ; +LOCATE COMP "Din[3]" SITE "9" ; diff --git a/CPLD/RAM2E-LCMXO2.mem b/CPLD/RAM2E-LCMXO2.mem new file mode 100644 index 0000000..f97b126 --- /dev/null +++ b/CPLD/RAM2E-LCMXO2.mem @@ -0,0 +1,7 @@ +// Auto-generated by memint 09/20/2023 04:19:47 +#Format=Hex +#Depth=16 +#Width=8 +#AddrRadix=3 +#DataRadix=3 +#Data diff --git a/CPLD/RAM2E-LCMXO2.v b/CPLD/RAM2E-LCMXO2.v new file mode 100644 index 0000000..14cc526 --- /dev/null +++ b/CPLD/RAM2E-LCMXO2.v @@ -0,0 +1,831 @@ +module RAM2E(C14M, PHI1, LED, + nWE, nWE80, nEN80, nC07X, + Ain, Din, Dout, nDOE, Vout, nVOE, + CKE, nCS, nRAS, nCAS, nRWE, + BA, RA, RD, DQML, DQMH); + + /* Clocks */ + input C14M, PHI1; + + /* Control inputs */ + input nWE, nWE80, nEN80, nC07X; + + /* Delay for EN80 signal */ + //output DelayOut = 1'b0; + //input DelayIn; + wire EN80 = !nEN80; + + /* Activity LED */ + reg LEDEN = 0; + output LED; + assign LED = !(!nEN80 && LEDEN); + + /* Address Bus */ + input [7:0] Ain; // Multiplexed DRAM address input + + /* 6502 Data Bus */ + input [7:0] Din; // 6502 data bus inputs + reg DOEEN = 0; // 6502 data bus output enable from state machine + output nDOE; + assign nDOE = !(EN80 && nWE && DOEEN); // 6502 data bus output enable + output reg [7:0] Dout; // 6502 data Bus output + + /* Video Data Bus */ + output nVOE; + assign nVOE = !(!PHI1); /// Video data bus output enable + output reg [7:0] Vout; // Video data bus + + /* SDRAM */ + output reg CKE = 0; + output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1; + output reg [1:0] BA; + output reg [11:0] RA; + output reg DQML = 1, DQMH = 1; + wire RDOE = EN80 && !nWE80; + inout [7:0] RD; + assign RD[7:0] = RDOE ? Din[7:0] : 8'bZ; + + /* RAMWorks Bank Register and Capacity Mask */ + reg [7:0] RWBank = 0; // RAMWorks bank register + reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask + reg RWSel = 0; // RAMWorks bank register select + reg CmdRWMaskSet = 0; // RAMWorks Mask register set flag + // Causes RWBank to be zeroed next RWSel access + //reg CmdSetRWBankFFMAX = 0; + //reg CmdSetRWBankFFSPI = 0; + reg CmdSetRWBankFFMXO2 = 0; + reg CmdSetRWBankFFLED = 0; + reg CmdLEDSet = 0; + reg CmdLEDGet = 0; + + /* Command Sequence Detector */ + reg [2:0] CS = 0; // Command sequence state + reg [2:0] CmdTout = 0; // Command sequence timeout + + /* UFM Interface */ + reg wb_rst; + reg wb_cyc_stb; + reg wb_req; + reg wb_we; + reg [7:0] wb_adr; + reg [7:0] wb_dati; + wire wb_ack; + wire [7:0] wb_dato; + wire ufm_irq; + REFB ufmefb( + .wb_clk_i(C14M), + .wb_rst_i(wb_rst), + .wb_cyc_i(wb_cyc_stb), + .wb_stb_i(wb_cyc_stb), + .wb_we_i(wb_we), + .wb_adr_i(wb_adr), + .wb_dat_i(wb_dati), + .wb_dat_o(wb_dato), + .wb_ack_o(wb_ack), + .wbc_ufm_irq(ufm_irq)); + + /* UFM State and User Command Triggers */ + //reg CmdBitbangMAX = 0; // Set by user command. Loads UFM outputs next RWSel + //reg CmdBitbangSPI = 0; + reg CmdBitbangMXO2 = 0; + reg CmdExecMXO2 = 0; + //reg CmdPrgmMAX = 0; // Set by user command. Programs UFM + //reg CmdEraseMAX = 0; // Set by user command. Erases UFM + + /* State Counters */ + reg PHI1reg = 0; // Saved PHI1 at last rising clock edge + reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15 + reg [15:0] FS = 0; // Fast state counter + reg [3:0] S = 0; // IIe State counter + + /* State Counters */ + always @(posedge C14M) begin + // Increment fast state counter + FS <= FS+16'h0001; + // Synchronize Apple state counter to S1 when just entering PHI1 + PHI1reg <= PHI1; // Save old PHI1 + S <= (PHI1 && !PHI1reg && Ready) ? 4'h1 : + S==4'h0 ? 4'h0 : + S==4'hF ? 4'hF : S+4'h1; + end + + /* UFM Control */ + always @(posedge C14M) begin + if (S==4'h0) begin + if (FS[15:14]==2'b00) wb_rst <= 1'b1; + else if (FS[15:14]==2'b01) wb_rst <= 1'b0; + else if (FS[15:14]==2'b10) begin + wb_rst <= 1'b0; + if (wb_ack || (FS[7:0]==0)) wb_cyc_stb <= 0; + else if ((FS[7:0]==1) && wb_req) wb_cyc_stb <= 1; + case (FS[13:8]) + 0: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 1: begin // Enable configuration interface - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h74; + wb_req <= 1; + end 2: begin // Enable configuration interface - operand 1/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h08; + wb_req <= 1; + end 3: begin // Enable configuration interface - operand 2/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 4: begin // Enable configuration interface - operand 3/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 5: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + + end 6: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 7: begin // Poll status register - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h3C; + wb_req <= 1; + end 8: begin // Poll status register - operand 1/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 9: begin // Poll status register - operand 2/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 10: begin // Poll status register - operand 3/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 11, 12, 13, 14: begin // Read status register 1-4 + wb_we <= 1'b0; + wb_adr[7:0] <= 8'h73; + wb_dati[7:0] <= 8'h3C; + wb_req <= 1; + end 15: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + + end 16: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 17: begin // Set UFM address - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'hB4; + wb_req <= 1; + end 18: begin // Set UFM address - operand 1/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 19: begin // Set UFM address - operand 2/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 20: begin // Set UFM address - operand 3/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 21: begin // Set UFM address - data 1/4 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h40; + wb_req <= 1; + end 22: begin // Set UFM address - data 2/4 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 23: begin // Set UFM address - data 3/4 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 24: begin // Set UFM address - data 4/4 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 190; + wb_req <= 1; + end 25: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + + end 26: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 27: begin // Read UFM page - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'hCA; + wb_req <= 1; + end 28: begin // Read UFM page - operand 1/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h10; + wb_req <= 1; + end 29: begin // Read UFM page - operand 2/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 30: begin // Read UFM page - operand 3/3 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h01; + wb_req <= 1; + end 31: begin // Read UFM page - data 0 + wb_we <= 1'b0; + wb_adr[7:0] <= 8'h73; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + if (wb_ack) RWMask[7:0] <= wb_dato[7:0]; + end 32: begin // Read UFM page - data 1 + wb_we <= 1'b0; + wb_adr[7:0] <= 8'h73; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + if (wb_ack) LEDEN <= wb_dato[0]; + end 33, 34, + 35, 36, 37, 38, + 39, 40, 41, 42, + 43, 44, 45, 46: begin // Read UFM page - data 2-15 + wb_we <= 1'b0; + wb_adr[7:0] <= 8'h73; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 47: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + + end 48: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 49: begin // Disable configuration interface - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h26; + wb_req <= 1; + end 50: begin // Disable configuration interface - operand 1/2 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 51: begin // Disable configuration interface - operand 2/2 + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end 52: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + + end 53: begin // Open frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h80; + wb_req <= 1; + end 54: begin // Bypass - command + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h71; + wb_dati[7:0] <= 8'hFF; + wb_req <= 1; + end 55: begin // Close frame + wb_we <= 1'b1; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 1; + end default: begin + wb_we <= 1'b0; + wb_adr[7:0] <= 8'h70; + wb_dati[7:0] <= 8'h00; + wb_req <= 0; + end + endcase + end else begin + wb_rst <= 1'b0; + wb_cyc_stb <= 1'b0; + wb_req <= 1'b0; + wb_we <= 1'b0; + wb_adr[7:0] <= 8'h00; + wb_dati[7:0] <= 8'h00; + end + end else begin + // UFM bitbang control + wb_rst <= 1'b0; + wb_req <= 1'b0; + + if (RWSel && S==4'hC) begin + // LED control + if (CmdLEDSet) LEDEN <= Din[0]; + + // Set capacity mask + if (CmdRWMaskSet) RWMask[7:0] <= {Din[7], ~Din[6:0]}; + + // Set EFB address + if (CmdBitbangMXO2) begin + wb_adr[7:0] <= Din[7:0]; + wb_dati[7:0] <= wb_adr[7:0]; + end + + // Excecute EFB R/W cycle + if (CmdExecMXO2) begin + wb_we <= Din[0]; + wb_cyc_stb <= 1; + end else if (wb_ack) wb_cyc_stb <= 0; + end + end + end + + /* SDRAM Control */ + always @(posedge C14M) begin + if (S==4'h0) begin + // SDRAM initialization + if (FS[15:0]==16'hFFC0) begin + // Precharge All + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b0; + RA[10] <= 1'b1; // "all" + end else if (FS[15:4]==16'hFFD && FS[0]==1'b0) begin // Repeat 8x + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end else if (FS[15:0]==16'hFFE8) begin + // Set Mode Register + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b0; + RA[10] <= 1'b0; // Reserved in mode register + end else if (FS[15:4]==12'hFFF && FS[0]==1'b0) begin // Repeat 8x + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end else begin // Otherwise send no-op + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end + // Enable SDRAM clock after 65,280 cycles (~4.56ms) + CKE <= FS[15:8] == 8'hFF; + + // Mode register contents + BA[1:0] <= 2'b00; // Reserved + RA[11] <= 1'b0; // Reserved + // RA[10] set above ^ + RA[9] <= 1'b1; // "1" for single write mode + RA[8] <= 1'b0; // Reserved + RA[7] <= 1'b0; // "0" for not test mode + RA[6:4] <= 3'b010; // "2" for CAS latency 2 + RA[3] <= 1'b0; // "0" for sequential burst (not used) + RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst) + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + + // Begin normal operation after 128k init cycles (~9.15ms) + if (FS == 16'hFFFF) Ready <= 1'b1; + end else if (S==4'h1) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h2) begin + // Enable clock + CKE <= 1'b1; + + // Activate + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // SDRAM bank 0, high-order row address is 0 + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + // Row address is as previously latched + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h3) begin + // Enable clock + CKE <= 1'b1; + + // Read + nCS <= 1'b0; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= 1'b1; + + // SDRAM bank 0, RA[11,9:8] don't care + BA[1:0] <= 2'b00; + RA[11] <= 1'b0; + RA[10] <= 1'b1; // (A10 set to auto-precharge) + RA[9] <= 1'b0; + RA[8] <= 1'b0; + // Latch column address for read command + RA[7:0] <= Ain[7:0]; + + // Read low byte (high byte is +4MB in ramworks) + DQML <= 1'b0; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h4) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h5) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h6) begin + // Enable clock + CKE <= 1'b1; + + if (FS[5:4]==0) begin + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + end else begin + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + end + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h7) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for activate command + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h8) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // Activate if '245 output enabled + nCS <= nEN80; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // SDRAM bank, RA[11:8] determine by RamWorks bank + BA[1:0] <= RWBank[5:4]; + RA[11:8] <= RWBank[3:0]; + // Row address is as previously latched + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h9) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // Read/Write if '245 output enabled + nCS <= nEN80; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= nWE80; + + // SDRAM bank still determined by RamWorks, RA[11,9:8] don't care + BA[1:0] <= RWBank[5:4]; + RA[11] <= 1'b0; + RA[10] <= 1'b1; // (A10 set to auto-precharge) + RA[9] <= 1'b0; + RA[8] <= RWBank[7]; + // Latch column address for R/W command + RA[7:0] <= Ain[7:0]; + + // Latch RAMWorks low nybble write select using old row address + RWSel <= RA[0] && !RA[3] && !nWE && !nC07X; + + // Mask according to RAMWorks bank (high byte is +4MB) + DQML <= RWBank[6]; + DQMH <= !RWBank[6]; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'hA) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'hB) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hC) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + + // RAMWorks Bank Register Select + if (RWSel) begin + // Latch RAMWorks bank if accessed + if (CmdSetRWBankFFLED || + //CmdSetRWBankFFMAX || + //CmdSetRWBankFFSPI || + CmdSetRWBankFFMXO2 || + (CmdLEDGet && LEDEN)) RWBank <= 8'hFF; + else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]}; + + // Recognize command sequence and advance CS state + if ((CS==3'h0 && Din[7:0]==8'hFF) || + (CS==3'h1 && Din[7:0]==8'h00) || + (CS==3'h2 && Din[7:0]==8'h55) || + (CS==3'h3 && Din[7:0]==8'hAA) || + (CS==3'h4 && Din[7:0]==8'hC1) || + (CS==3'h5 && Din[7:0]==8'hAD) || + CS==3'h6 || CS==3'h7) CS <= CS+3'h1; + else CS <= 0; // Back to beginning if it's not right + + if (CS==3'h6) begin // Recognize and submit command in CS6 + //CmdSetRWBankFFMAX <= Din[7:0]==8'hFF; + //CmdSetRWBankFFSPI <= Din[7:0]==8'hFE; + CmdSetRWBankFFMXO2 <= Din[7:0]==8'hFD; + CmdSetRWBankFFLED <= Din[7:0]==8'hF0; + + CmdRWMaskSet <= Din[7:0]==8'hE0; + CmdLEDSet <= Din[7:0]==8'hE2; + CmdLEDGet <= Din[7:0]==8'hE3; + + //CmdBitbangMAX <= Din[7:0]==8'hEA; + //CmdBitbangSPI <= Din[7:0]==8'hEB; + CmdBitbangMXO2 <= Din[7:0]==8'hEC; + CmdExecMXO2 <= Din[7:0]==8'hED; + + //if (Din[7:0]==8'hEE) CmdEraseMAX <= 1; + //if (Din[7:0]==8'hEF) CmdPrgmMAX <= 1; + end else begin // Reset command triggers + //CmdSetRWBankFFMAX <= 0; + //CmdSetRWBankFFSPI <= 0; + CmdSetRWBankFFMXO2 <= 0; + CmdSetRWBankFFLED <= 0; + CmdRWMaskSet <= 0; + CmdLEDSet <= 0; + CmdLEDGet <= 0; + //CmdBitbangMAX <= 0; + //CmdBitbangSPI <= 0; + CmdBitbangMXO2 <= 0; + CmdExecMXO2 <= 0; + end + + CmdTout <= 0; // Reset command timeout if RWSel accessed + end else begin + CmdTout <= CmdTout+3'h1; // Increment command timeout + // If command sequence times out, reset sequence state + if (CmdTout==3'h7) CS <= 0; + end + end else if (S==4'hD) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hE) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for next video read + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hF) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for next video read + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end + end + always @(negedge C14M) begin + // Latch video and read data outputs + if (S==4'h6) Vout[7:0] <= RD[7:0]; + if (S==4'hC) Dout[7:0] <= RD[7:0]; + end +endmodule diff --git a/CPLD/RAM2E-MAX.sdc b/CPLD/RAM2E-MAX.sdc new file mode 100644 index 0000000..e0b0052 --- /dev/null +++ b/CPLD/RAM2E-MAX.sdc @@ -0,0 +1,2 @@ +create_clock ARCLK -period 200ns +create_clock DRCLK -period 200ns diff --git a/CPLD/RAM2E-MAX.v b/CPLD/RAM2E-MAX.v new file mode 100644 index 0000000..3ab994b --- /dev/null +++ b/CPLD/RAM2E-MAX.v @@ -0,0 +1,682 @@ +module RAM2E(C14M, PHI1, LED, + nWE, nWE80, nEN80, nC07X, + Ain, Din, Dout, nDOE, Vout, nVOE, + CKE, nCS, nRAS, nCAS, nRWE, + BA, RA, RD, DQML, DQMH); + + /* Clocks */ + input C14M, PHI1; + + /* Control inputs */ + input nWE, nWE80, nEN80, nC07X; + + /* Delay for EN80 signal */ + //output DelayOut = 1'b0; + //input DelayIn; + wire EN80 = !nEN80; + + /* Activity LED */ + reg LEDEN = 0; + output LED; + assign LED = !(!nEN80 && LEDEN); + + /* Address Bus */ + input [7:0] Ain; // Multiplexed DRAM address input + + /* 6502 Data Bus */ + input [7:0] Din; // 6502 data bus inputs + reg DOEEN = 0; // 6502 data bus output enable from state machine + output nDOE; + assign nDOE = !(EN80 && nWE && DOEEN); // 6502 data bus output enable + output reg [7:0] Dout; // 6502 data Bus output + + /* Video Data Bus */ + output nVOE; + assign nVOE = !(!PHI1); /// Video data bus output enable + output reg [7:0] Vout; // Video data bus + + /* SDRAM */ + output reg CKE = 0; + output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1; + output reg [1:0] BA; + output reg [11:0] RA; + output reg DQML = 1, DQMH = 1; + wire RDOE = EN80 && !nWE80; + inout [7:0] RD; + assign RD[7:0] = RDOE ? Din[7:0] : 8'bZ; + + /* RAMWorks Bank Register and Capacity Mask */ + reg [7:0] RWBank = 0; // RAMWorks bank register + reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask + reg RWSel = 0; // RAMWorks bank register select + reg CmdRWMaskSet = 0; // RAMWorks Mask register set flag + // Causes RWBank to be zeroed next RWSel access + reg CmdSetRWBankFFMAX = 0; + //reg CmdSetRWBankFFSPI = 0; + //reg CmdSetRWBankFFMXO2 = 0; + reg CmdSetRWBankFFLED = 0; + reg CmdLEDSet = 0; + reg CmdLEDGet = 0; + + /* Command Sequence Detector */ + reg [2:0] CS = 0; // Command sequence state + reg [2:0] CmdTout = 0; // Command sequence timeout + + /* UFM Interface */ + reg [15:8] UFMD = 0; // *Parallel* UFM data register + reg ARCLK = 0; // UFM address register clock + // UFM address register data input tied to 0 + reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment + reg DRCLK = 0; // UFM data register clock + reg DRDIn = 0; // UFM data register input + reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address + reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy + reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy + wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous + wire RTPBusy; // 1 if real-time programming in progress. Asynchronous + wire DRDOut; // UFM data output + // UFM oscillator always enabled + wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz) + UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V) + .arclk (ARCLK), + .ardin (1'b0), + .arshft (ARShift), + .drclk (DRCLK), + .drdin (DRDIn), + .drshft (DRShift), + .erase (UFMErase), + .oscena (1'b1), + .program (UFMProgram), + .busy (UFMBusy), + .drdout (DRDOut), + .osc (UFMOsc), + .rtpbusy (RTPBusy)); + reg UFMBusyReg = 0; // UFMBusy registered to sync with C14M + reg RTPBusyReg = 0; // RTPBusy registered to sync with C14M + + /* UFM State and User Command Triggers */ + reg UFMInitDone = 0; // 1 if UFM initialization finished + reg UFMReqErase = 0; // 1 if UFM requires erase + reg CmdBitbangMAX = 0; // Set by user command. Loads UFM outputs next RWSel + //reg CmdBitbangSPI = 0; + //reg CmdBitbangMXO2 = 0; + //reg CmdExecMXO2 = 0; + reg CmdPrgmMAX = 0; // Set by user command. Programs UFM + reg CmdEraseMAX = 0; // Set by user command. Erases UFM + reg DRCLKPulse = 0; // Set by user command. Causes DRCLK pulse next C14M + + /* State Counters */ + reg PHI1reg = 0; // Saved PHI1 at last rising clock edge + reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15 + reg [15:0] FS = 0; // Fast state counter + reg [3:0] S = 0; // IIe State counter + + /* State Counters */ + always @(posedge C14M) begin + // Increment fast state counter + FS <= FS+16'h0001; + // Synchronize Apple state counter to S1 when just entering PHI1 + PHI1reg <= PHI1; // Save old PHI1 + S <= (PHI1 && !PHI1reg && Ready) ? 4'h1 : + S==4'h0 ? 4'h0 : + S==4'hF ? 4'hF : S+4'h1; + end + + /* UFM Control */ + always @(posedge C14M) begin // Synchronize asynchronous UFM signals + UFMBusyReg <= UFMBusy; RTPBusyReg <= RTPBusy; + end + always @(posedge C14M) begin + if (S==4'h0) begin + if ((FS[15:13]==3'b101) || (FS[15:13]==3'b111 && UFMReqErase)) begin + // In states AXXX-BXXX and also EXXX-FXXX if erase/wrap req'd + // shift in 0's to address register + ARCLK <= FS[0]; // Clock address register + DRCLK <= 1'b0; // Don't clock data register + ARShift <= 1'b1; // Shift address registers + DRDIn <= 1'b0; // Don't care DRDIn + DRShift <= 1'b0; // Don't care DRDShift + end else if (!UFMInitDone && FS[15:13]==3'b110 && FS[4:1]==4'h4) begin + // In states CXXX-DXXX (substep 4) + // Xfer to data reg (repeat 256x 1x) + ARCLK <= 1'b0; // Don't clock address register + DRCLK <= FS[0]; // Clock data register + ARShift <= 1'b0; // Don't care ARShift + DRDIn <= 1'b0; // Don't care DRDIn + DRShift <= 1'b0; // Don't care DRShift + end else if (!UFMInitDone && FS[15:13]==3'b110 && (FS[4:1]==4'h7 || FS[4]==1'b1)) begin + // In states CXXX-DXXX (substeps 8-F) + // Save UFM D15-8, shift out D14-7 (repeat 256x 8x) + DRCLK <= FS[0]; // Clock data register + ARShift <= 1'b0; // ARShift is 0 because we want to increment + DRDIn <= 1'b0; // Don't care what to shift into data register + DRShift <= 1'b1; // Shift data register + // Shift into UFMD + if (FS[0]) UFMD[15:8] <= {UFMD[14:8], DRDOut}; + + // Compare and store mask + if (FS[4:1]==4'hF) begin + ARCLK <= FS[0]; // Clock address register to increment + // If byte is erased (0xFF, i.e. all 1's, is erased)... + if (UFMD[15:8]==8'hFF && DRDOut==1'b1) begin + // Current UFM address is where we want to store + UFMInitDone <= 1'b1; // Quit iterating + // Otherwise byte is valid setting (i.e. some bit is 0)... + end else begin + // Set RWMask, but if saved mask is 0x80, store ~0xFF + if (UFMD[15:8]==8'b10000000) begin + RWMask[7:0] <= {1'b1, ~7'h7F}; + end else RWMask[7:0] <= {UFMD[15], ~UFMD[14:8]}; + // Set LED setting + LEDEN <= DRDOut ^ UFMD[15]; + // If last byte in sector... + if (FS[12:5]==8'hFF) begin + UFMReqErase <= 1'b1; // Mark need to erase + end + end + end else ARCLK <= 1'b0; // Don't clock address register + end else begin + ARCLK <= 1'b0; + DRCLK <= 1'b0; + ARShift <= 1'b0; + DRDIn <= 1'b0; + DRShift <= 1'b0; + end + + // Don't erase or program UFM during initialization + UFMErase <= 1'b0; + UFMProgram <= 1'b0; + // Keep DRCLK pulse control disabled during init + DRCLKPulse <= 1'b0; + end else begin + // Can only shift UFM data register now + ARCLK <= 1'b0; + ARShift <= 1'b0; + DRShift <= 1'b1; + + // UFM bitbang control + if (CmdBitbangMAX && RWSel && S==4'hC) begin + DRDIn <= Din[6]; + DRCLKPulse <= Din[7]; + DRCLK <= 1'b0; + end else begin + DRCLKPulse <= 1'b0; + DRCLK <= DRCLKPulse; + end + + if (RWSel && S==4'hC) begin + // LED control + if (CmdLEDSet) LEDEN <= Din[0]; + + // Set capacity mask + if (CmdRWMaskSet) RWMask[7:0] <= {Din[7], ~Din[6:0]}; + end + + // UFM programming sequence + if (CmdPrgmMAX || CmdEraseMAX) begin + if (!UFMBusyReg && !RTPBusyReg) begin + if (UFMReqErase || CmdEraseMAX) UFMErase <= 1'b1; + else if (CmdPrgmMAX) UFMProgram <= 1'b1; + end else if (UFMBusyReg) UFMReqErase <= 1'b0; + end + end + end + + /* SDRAM Control */ + always @(posedge C14M) begin + if (S==4'h0) begin + // SDRAM initialization + if (FS[15:0]==16'hFFC0) begin + // Precharge All + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b0; + RA[10] <= 1'b1; // "all" + end else if (FS[15:4]==16'hFFD && FS[0]==1'b0) begin // Repeat 8x + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end else if (FS[15:0]==16'hFFE8) begin + // Set Mode Register + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b0; + RA[10] <= 1'b0; // Reserved in mode register + end else if (FS[15:4]==12'hFFF && FS[0]==1'b0) begin // Repeat 8x + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end else begin // Otherwise send no-op + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end + // Enable SDRAM clock after 65,280 cycles (~4.56ms) + CKE <= FS[15:8] == 8'hFF; + + // Mode register contents + BA[1:0] <= 2'b00; // Reserved + RA[11] <= 1'b0; // Reserved + // RA[10] set above ^ + RA[9] <= 1'b1; // "1" for single write mode + RA[8] <= 1'b0; // Reserved + RA[7] <= 1'b0; // "0" for not test mode + RA[6:4] <= 3'b010; // "2" for CAS latency 2 + RA[3] <= 1'b0; // "0" for sequential burst (not used) + RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst) + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + + // Begin normal operation after 128k init cycles (~9.15ms) + if (FS == 16'hFFFF) Ready <= 1'b1; + end else if (S==4'h1) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h2) begin + // Enable clock + CKE <= 1'b1; + + // Activate + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // SDRAM bank 0, high-order row address is 0 + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + // Row address is as previously latched + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h3) begin + // Enable clock + CKE <= 1'b1; + + // Read + nCS <= 1'b0; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= 1'b1; + + // SDRAM bank 0, RA[11,9:8] don't care + BA[1:0] <= 2'b00; + RA[11] <= 1'b0; + RA[10] <= 1'b1; // (A10 set to auto-precharge) + RA[9] <= 1'b0; + RA[8] <= 1'b0; + // Latch column address for read command + RA[7:0] <= Ain[7:0]; + + // Read low byte (high byte is +4MB in ramworks) + DQML <= 1'b0; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h4) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h5) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h6) begin + // Enable clock + CKE <= 1'b1; + + if (FS[5:4]==0) begin + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + end else begin + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + end + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h7) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for activate command + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h8) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // Activate if '245 output enabled + nCS <= nEN80; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // SDRAM bank, RA[11:8] determine by RamWorks bank + BA[1:0] <= RWBank[5:4]; + RA[11:8] <= RWBank[3:0]; + // Row address is as previously latched + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h9) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // Read/Write if '245 output enabled + nCS <= nEN80; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= nWE80; + + // SDRAM bank still determined by RamWorks, RA[11,9:8] don't care + BA[1:0] <= RWBank[5:4]; + RA[11] <= 1'b0; + RA[10] <= 1'b1; // (A10 set to auto-precharge) + RA[9] <= 1'b0; + RA[8] <= RWBank[7]; + // Latch column address for R/W command + RA[7:0] <= Ain[7:0]; + + // Latch RAMWorks low nybble write select using old row address + RWSel <= RA[0] && !RA[3] && !nWE && !nC07X; + + // Mask according to RAMWorks bank (high byte is +4MB) + DQML <= RWBank[6]; + DQMH <= !RWBank[6]; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'hA) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'hB) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hC) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + + // RAMWorks Bank Register Select + if (RWSel) begin + // Latch RAMWorks bank if accessed + if (CmdSetRWBankFFLED || + CmdSetRWBankFFMAX || + //CmdSetRWBankFFSPI || + //CmdSetRWBankFFMXO2 || + (CmdLEDGet && LEDEN)) RWBank <= 8'hFF; + else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]}; + + // Recognize command sequence and advance CS state + if ((CS==3'h0 && Din[7:0]==8'hFF) || + (CS==3'h1 && Din[7:0]==8'h00) || + (CS==3'h2 && Din[7:0]==8'h55) || + (CS==3'h3 && Din[7:0]==8'hAA) || + (CS==3'h4 && Din[7:0]==8'hC1) || + (CS==3'h5 && Din[7:0]==8'hAD) || + CS==3'h6 || CS==3'h7) CS <= CS+3'h1; + else CS <= 0; // Back to beginning if it's not right + + if (CS==3'h6) begin // Recognize and submit command in CS6 + CmdSetRWBankFFMAX <= Din[7:0]==8'hFF; + //CmdSetRWBankFFSPI <= Din[7:0]==8'hFE; + //CmdSetRWBankFFMXO2 <= Din[7:0]==8'hFD; + CmdSetRWBankFFLED <= Din[7:0]==8'hF0; + + CmdRWMaskSet <= Din[7:0]==8'hE0; + CmdLEDSet <= Din[7:0]==8'hE2; + CmdLEDGet <= Din[7:0]==8'hE3; + + CmdBitbangMAX <= Din[7:0]==8'hEA; + //CmdBitbangSPI <= Din[7:0]==8'hEB; + //CmdBitbangMXO2 <= Din[7:0]==8'hEC; + //CmdExecMXO2 <= Din[7:0]==8'hED; + + if (Din[7:0]==8'hEE) CmdEraseMAX <= 1; + if (Din[7:0]==8'hEF) CmdPrgmMAX <= 1; + end else begin // Reset command triggers + CmdSetRWBankFFMAX <= 0; + //CmdSetRWBankFFSPI <= 0; + //CmdSetRWBankFFMXO2 <= 0; + CmdSetRWBankFFLED <= 0; + CmdRWMaskSet <= 0; + CmdLEDSet <= 0; + CmdLEDGet <= 0; + CmdBitbangMAX <= 0; + //CmdBitbangSPI <= 0; + //CmdBitbangMXO2 <= 0; + //CmdExecMXO2 <= 0; + end + + CmdTout <= 0; // Reset command timeout if RWSel accessed + end else begin + CmdTout <= CmdTout+3'h1; // Increment command timeout + // If command sequence times out, reset sequence state + if (CmdTout==3'h7) CS <= 0; + end + end else if (S==4'hD) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hE) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for next video read + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hF) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA[1:0] <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for next video read + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end + end + always @(negedge C14M) begin + // Latch video and read data outputs + if (S==4'h6) Vout[7:0] <= RD[7:0]; + if (S==4'hC) Dout[7:0] <= RD[7:0]; + end +endmodule diff --git a/CPLD/RAM2E-old.v b/CPLD/RAM2E-old.v new file mode 100644 index 0000000..bcb3b6c --- /dev/null +++ b/CPLD/RAM2E-old.v @@ -0,0 +1,636 @@ +module RAM2E(C14M, PHI1, + nWE, nWE80, nEN80, nC07X, + Ain, Din, Dout, nDOE, Vout, nVOE, + CKE, nCS, nRAS, nCAS, nRWE, + BA, RA, RD, DQML, DQMH); + + /* Clocks */ + input C14M, PHI1; + + /* Control inputs */ + input nWE, nWE80, nEN80, nC07X; + + /* Delay for EN80 signal */ + //output DelayOut = 1'b0; + //input DelayIn; + wire EN80 = ~nEN80; + + /* Address Bus */ + input [7:0] Ain; // Multiplexed DRAM address input + + /* 6502 Data Bus */ + input [7:0] Din; // 6502 data bus inputs + reg DOEEN = 0; // 6502 data bus output enable from state machine + output nDOE = ~(EN80 & nWE & DOEEN); // 6502 data bus output enable + output reg [7:0] Dout; // 6502 data Bus output + + /* Video Data Bus */ + output nVOE = ~(~PHI1); /// Video data bus output enable + output reg [7:0] Vout; // Video data bus + + /* SDRAM */ + output reg CKE = 0; + output reg nCS = 1, nRAS = 1, nCAS = 1, nRWE = 1; + output reg [1:0] BA; + output reg [11:0] RA; + output reg DQML = 1, DQMH = 1; + wire RDOE = EN80 & ~nWE80; + inout [7:0] RD = RDOE ? Din[7:0] : 8'bZ; + + /* RAMWorks Bank Register and Capacity Mask */ + reg [7:0] RWBank = 0; // RAMWorks bank register + reg [7:0] RWMask = 0; // RAMWorks bank reg. capacity mask + reg RWSel = 0; // RAMWorks bank register select + reg RWMaskSet = 0; // RAMWorks Mask register set flag + reg SetRWBankFF = 0; // Causes RWBank to be zeroed next RWSel access + + /* Command Sequence Detector */ + reg [2:0] CS = 0; // Command sequence state + reg [2:0] CmdTout = 0; // Command sequence timeout + + /* UFM Interface */ + reg [15:8] UFMD = 0; // *Parallel* UFM data register + reg ARCLK = 0; // UFM address register clock + // UFM address register data input tied to 0 + reg ARShift = 0; // 1 to Shift UFM address in, 0 to increment + reg DRCLK = 0; // UFM data register clock + reg DRDIn = 0; // UFM data register input + reg DRShift = 0; // 1 to shift UFM out, 0 to load from current address + reg UFMErase = 0; // Rising edge starts erase. UFM+RTP must not be busy + reg UFMProgram = 0; // Rising edge starts program. UFM+RTP must not be busy + wire UFMBusy; // 1 if UFM is doing user operation. Asynchronous + wire RTPBusy; // 1 if real-time programming in progress. Asynchronous + wire DRDOut; // UFM data output + // UFM oscillator always enabled + wire UFMOsc; // UFM oscillator output (3.3-5.5 MHz) + UFM UFM_inst ( // UFM IP block (for Altera MAX II and MAX V) + .arclk (ARCLK), + .ardin (1'b0), + .arshft (ARShift), + .drclk (DRCLK), + .drdin (DRDIn), + .drshft (DRShift), + .erase (UFMErase), + .oscena (1'b1), + .program (UFMProgram), + .busy (UFMBusy), + .drdout (DRDOut), + .osc (UFMOsc), + .rtpbusy (RTPBusy)); + reg UFMBusyReg = 0; // UFMBusy registered to sync with C14M + reg RTPBusyReg = 0; // RTPBusy registered to sync with C14M + + /* UFM State & User Command Triggers */ + reg UFMInitDone = 0; // 1 if UFM initialization finished + reg UFMReqErase = 0; // 1 if UFM requires erase + reg UFMBitbang = 0; // Set by user command. Loads UFM outputs next RWSel + reg UFMPrgmEN = 0; // Set by user command. Programs UFM + reg UFMEraseEN = 0; // Set by user command. Erases UFM + reg DRCLKPulse = 0; // Set by user command. Causes DRCLK pulse next C14M + + /* State Counters */ + reg PHI1reg = 0; // Saved PHI1 at last rising clock edge + reg Ready = 0; // 1 if done with init sequence (S0) and enter S1-S15 + reg [15:0] FS = 0; // Fast state counter + reg [3:0] S = 0; // IIe State counter + + /* State Counters */ + always @(posedge C14M) begin + // Increment fast state counter + FS <= FS+1; + // Synchronize Apple state counter to S1 when just entering PHI1 + PHI1reg <= PHI1; // Save old PHI1 + S <= (PHI1 & ~PHI1reg & Ready) ? 4'h1 : + S==4'h0 ? 4'h0 : + S==4'hF ? 4'hF : S+1; + end + + /* UFM Control */ + always @(posedge C14M) begin + // Synchronize asynchronous UFM signals + UFMBusyReg <= UFMBusy; + RTPBusyReg <= RTPBusy; + + if (S==4'h0) begin + if ((FS[15:13]==3'b101) | (FS[15:13]==3'b111 & UFMReqErase)) begin + // In states AXXX-BXXX and also EXXX-FXXX if erase/wrap req'd + // shift in 0's to address register + ARCLK <= FS[0]; // Clock address register + DRCLK <= 1'b0; // Don't clock data register + ARShift <= 1'b1; // Shift address registers + DRDIn <= 1'b0; // Don't care DRDIn + DRShift <= 1'b0; // Don't care DRDShift + end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4:1]==4'h4) begin + // In states CXXX-DXXX (substep 4) + // Xfer to data reg (repeat 256x 1x) + ARCLK <= 1'b0; // Don't clock address register + DRCLK <= FS[0]; // Clock data register + ARShift <= 1'b0; // Don't care ARShift + DRDIn <= 1'b0; // Don't care DRDIn + DRShift <= 1'b0; // Don't care DRShift + end else if (~UFMInitDone & FS[15:13]==3'b110 & FS[4]==1'b1) begin + // In states CXXX-DXXX (substeps 8-F) + // Save UFM D15-8, shift out D14-7 (repeat 256x 8x) + DRCLK <= FS[0]; // Clock data register + ARShift <= 1'b0; // ARShift is 0 because we want to increment + DRDIn <= 1'b0; // Don't care what to shift into data register + DRShift <= 1'b1; // Shift data register + // Shift into UFMD + if (FS[0]) UFMD[15:8] <= {UFMD[14:8], DRDOut}; + + // Compare and store mask + if (FS[4:1]==4'hF) begin + ARCLK <= FS[0]; // Clock address register to increment + // If byte is erased (0xFF, i.e. all 1's, is erased)... + if (UFMD[14:8]==7'b1111111 & DRDOut==1'b1) begin + // Current UFM address is where we want to store + UFMInitDone <= 1'b1; // Quit iterating + // Otherwise byte is valid setting (i.e. some bit is 0)... + end else begin + // Set RWMask, but if saved mask is 0x80, store ~0xFF + if (UFMD[14:8]==7'b1000000 & DRDOut==1'b0) begin + RWMask[7:0] <= {1'b1, ~7'h7F}; + end else RWMask[7:0] <= {UFMD[14], ~UFMD[13:8], ~DRDOut}; + // If last byte in sector... + if (FS[12:5]==8'hFF) begin + UFMReqErase <= 1'b1; // Mark need to erase + end + end + end else ARCLK <= 1'b0; // Don't clock address register + end else begin + ARCLK <= 1'b0; + DRCLK <= 1'b0; + ARShift <= 1'b0; + DRDIn <= 1'b0; + DRShift <= 1'b0; + end + + // Don't erase or program UFM during initialization + UFMErase <= 1'b0; + UFMProgram <= 1'b0; + // Keep DRCLK pulse control disabled during init + DRCLKPulse <= 1'b0; + end else begin + // Can only shift UFM data register now + ARCLK <= 1'b0; + ARShift <= 1'b0; + DRShift <= 1'b1; + + // UFM bitbang control + if (UFMBitbang & CS==3'h7 & RWSel & S==4'hC) begin + DRDIn <= Din[6]; + DRCLKPulse <= Din[7]; + DRCLK <= 1'b0; + end else begin + DRCLKPulse <= 1'b0; + DRCLK <= DRCLKPulse; + end + + // Set capacity mask + if (RWMaskSet & RWSel & S==4'hC) RWMask[7:0] <= {Din[7], ~Din[6:0]}; + + // UFM programming sequence + if (UFMPrgmEN | UFMEraseEN) begin + if (~UFMBusyReg & ~RTPBusyReg) begin + if (UFMReqErase | UFMEraseEN) UFMErase <= 1'b1; + else if (UFMPrgmEN) UFMProgram <= 1'b1; + end else if (UFMBusyReg) UFMReqErase <= 1'b0; + end + end + end + + /* SDRAM Control */ + always @(posedge C14M) begin + if (S==4'h0) begin + // SDRAM initialization + if (FS[15:0]==16'hFFC0) begin + // Precharge All + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b0; + RA[10] <= 1'b1; // "all" + end else if (FS[15:4]==16'hFFD & FS[0]==1'b0) begin // Repeat 8x + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end else if (FS[15:0]==16'hFFE8) begin + // Set Mode Register + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b0; + RA[10] <= 1'b0; // Reserved in mode register + end else if (FS[15:4]==12'hFFF & FS[0]==1'b0) begin // Repeat 8x + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end else begin // Otherwise send no-op + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + RA[10] <= 1'b0; + end + // Enable SDRAM clock after 65,280 cycles (~4.56ms) + CKE <= FS[15:8] == 8'hFF; + + // Mode register contents + BA[1:0] <= 2'b00; // Reserved + RA[11] <= 1'b0; // Reserved + // RA[10] set above ^ + RA[9] <= 1'b1; // "1" for single write mode + RA[8] <= 1'b0; // Reserved + RA[7] <= 1'b0; // "0" for not test mode + RA[6:4] <= 3'b010; // "2" for CAS latency 2 + RA[3] <= 1'b0; // "0" for sequential burst (not used) + RA[2:0] <= 3'b000; // "0" for burst length 1 (no burst) + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + + // Begin normal operation after 128k init cycles (~9.15ms) + if (FS == 16'hFFFF) Ready <= 1'b1; + end else if (S==4'h1) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h2) begin + // Enable clock + CKE <= 1'b1; + + // Activate + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // SDRAM bank 0, high-order row address is 0 + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Row address is as previously latched + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h3) begin + // Enable clock + CKE <= 1'b1; + + // Read + nCS <= 1'b0; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= 1'b1; + + // SDRAM bank 0, RA[11,9:8] don't care + BA <= 2'b00; + RA[11] <= 1'b0; + RA[10] <= 1'b1; // (A10 set to auto-precharge) + RA[9] <= 1'b0; + RA[8] <= 1'b0; + // Latch column address for read command + RA[7:0] <= Ain[7:0]; + + // Read low byte (high byte is +4MB in ramworks) + DQML <= 1'b0; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h4) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h5) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h6) begin + // Enable clock + CKE <= 1'b1; + + if (FS[5:4]==0) begin + // Auto-refresh + nCS <= 1'b0; + nRAS <= 1'b0; + nCAS <= 1'b0; + nRWE <= 1'b1; + end else begin + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + end + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h7) begin + // Enable clock + CKE <= 1'b1; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for activate command + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h8) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // Activate if '245 output enabled + nCS <= nEN80; + nRAS <= 1'b0; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // SDRAM bank, RA[11:8] determine by RamWorks bank + BA <= RWBank[5:4]; + RA[11:8] <= RWBank[3:0]; + // Row address is as previously latched + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'h9) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // Read/Write if '245 output enabled + nCS <= nEN80; + nRAS <= 1'b1; + nCAS <= 1'b0; + nRWE <= nWE80; + + // SDRAM bank still determined by RamWorks, RA[11,9:8] don't care + BA <= RWBank[5:4]; + RA[11] <= 1'b0; + RA[10] <= 1'b1; // (A10 set to auto-precharge) + RA[9] <= 1'b0; + RA[8] <= RWBank[7]; + // Latch column address for R/W command + RA[7:0] <= Ain[7:0]; + + // Latch RAMWorks low nybble write select using old row address + RWSel <= RA[0] & ~RA[3] & ~nWE & ~nC07X; + + // Mask according to RAMWorks bank (high byte is +4MB) + DQML <= RWBank[6]; + DQMH <= ~RWBank[6]; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'hA) begin + // Enable clock if '245 output enabled + CKE <= EN80; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Inhibit data bus output + DOEEN <= 1'b0; + end else if (S==4'hB) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hC) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + + // RAMWorks Bank Register Select + if (RWSel) begin + // Latch RAMWorks bank if accessed + if (SetRWBankFF) RWBank <= 8'hFF; + else RWBank <= Din[7:0] & {RWMask[7], ~RWMask[6:0]}; + + // Recognize command sequence and advance CS state + if ((CS==3'h0 & Din[7:0]==8'hFF) | + (CS==3'h1 & Din[7:0]==8'h00) | + (CS==3'h2 & Din[7:0]==8'h55) | + (CS==3'h3 & Din[7:0]==8'hAA) | + (CS==3'h4 & Din[7:0]==8'hC1) | + (CS==3'h5 & Din[7:0]==8'hAD) | + CS==3'h6 | CS==3'h7) CS <= CS+1; + else CS <= 0; // Back to beginning if it's not right + + if (CS==3'h6) begin // Recognize and submit command in CS6 + SetRWBankFF <= Din[7:0]==8'hFF; + if (Din[7:0]==8'hEF) UFMPrgmEN <= 1'b1; + if (Din[7:0]==8'hEE) UFMEraseEN <= 1'b1; + UFMBitbang <= Din[7:0]==8'hEA; + RWMaskSet <= Din[7:0]==8'hE0; + end else begin // Reset command triggers + SetRWBankFF <= 1'b0; + UFMBitbang <= 1'b0; + RWMaskSet <= 1'b0; + end + + CmdTout <= 0; // Reset command timeout if RWSel accessed + end else begin + CmdTout <= CmdTout+1; // Increment command timeout + // If command sequence times out, reset sequence state + if (CmdTout==3'h7) CS <= 0; + end + end else if (S==4'hD) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hE) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for next video read + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end else if (S==4'hF) begin + // Disable clock + CKE <= 1'b0; + + // NOP + nCS <= 1'b1; + nRAS <= 1'b1; + nCAS <= 1'b1; + nRWE <= 1'b1; + + // Don't care bank, RA[11:8] + BA <= 2'b00; + RA[11:8] <= 4'b0000; + // Latch row address for next video read + RA[7:0] <= Ain[7:0]; + + // Mask everything + DQML <= 1'b1; + DQMH <= 1'b1; + + // Enable data bus output + DOEEN <= 1'b1; + end + end + always @(negedge C14M) begin + // Latch video and read data outputs + if (S==4'h6) Vout[7:0] <= RD[7:0]; + if (S==4'hC) Dout[7:0] <= RD[7:0]; + end +endmodule diff --git a/CPLD/RAM2E.mif b/CPLD/RAM2E.mif new file mode 100644 index 0000000..80fa213 --- /dev/null +++ b/CPLD/RAM2E.mif @@ -0,0 +1,25 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=16; +DEPTH=512; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + [000..1FF] : FFFF; +END; diff --git a/CPLD/RAM2E.qsf b/CPLD/RAM2E.qsf new file mode 100644 index 0000000..c9ec12d --- /dev/null +++ b/CPLD/RAM2E.qsf @@ -0,0 +1,259 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition +# Date created = 22:58:44 May 05, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# RAM2E_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX II" +set_global_assignment -name DEVICE EPM240T100C5 +set_global_assignment -name TOP_LEVEL_ENTITY RAM2E +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:58:44 MAY 05, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1" +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS" +set_global_assignment -name VERILOG_FILE RAM2E.v +set_global_assignment -name SDC_FILE constraints.sdc +set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" +set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name SAFE_STATE_MACHINE ON +set_global_assignment -name PARALLEL_SYNTHESIS OFF +set_global_assignment -name SYNTH_MESSAGE_LEVEL HIGH +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name MIF_FILE RAM2E.mif +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" + +set_location_assignment PIN_12 -to C14M +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to C14M +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to C14M + +set_location_assignment PIN_37 -to PHI1 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHI1 +set_instance_assignment -name PAD_TO_CORE_DELAY 1 -to PHI1 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to PHI1 + +set_location_assignment PIN_51 -to nWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE + +set_location_assignment PIN_28 -to nEN80 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nEN80 +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nEN80 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nEN80 + +set_location_assignment PIN_33 -to nWE80 +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nWE80 +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nWE80 +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nWE80 + +set_location_assignment PIN_52 -to nC07X +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nC07X +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to nC07X +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nC07X + +set_location_assignment PIN_56 -to Ain[0] +set_location_assignment PIN_54 -to Ain[1] +set_location_assignment PIN_43 -to Ain[2] +set_location_assignment PIN_47 -to Ain[3] +set_location_assignment PIN_44 -to Ain[4] +set_location_assignment PIN_34 -to Ain[5] +set_location_assignment PIN_39 -to Ain[6] +set_location_assignment PIN_53 -to Ain[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Ain +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Ain +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Ain + +set_location_assignment PIN_38 -to Din[0] +set_location_assignment PIN_40 -to Din[1] +set_location_assignment PIN_42 -to Din[2] +set_location_assignment PIN_41 -to Din[3] +set_location_assignment PIN_48 -to Din[4] +set_location_assignment PIN_49 -to Din[5] +set_location_assignment PIN_36 -to Din[6] +set_location_assignment PIN_35 -to Din[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Din +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to Din +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Din + +set_location_assignment PIN_55 -to nDOE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nDOE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nDOE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nDOE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nDOE + +set_location_assignment PIN_77 -to Dout[0] +set_location_assignment PIN_76 -to Dout[1] +set_location_assignment PIN_74 -to Dout[2] +set_location_assignment PIN_75 -to Dout[3] +set_location_assignment PIN_73 -to Dout[4] +set_location_assignment PIN_72 -to Dout[5] +set_location_assignment PIN_84 -to Dout[6] +set_location_assignment PIN_85 -to Dout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Dout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Dout +set_instance_assignment -name SLOW_SLEW_RATE ON -to Dout +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Dout +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Dout + +set_location_assignment PIN_50 -to nVOE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nVOE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nVOE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nVOE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to nVOE + +set_location_assignment PIN_70 -to Vout[0] +set_location_assignment PIN_67 -to Vout[1] +set_location_assignment PIN_69 -to Vout[2] +set_location_assignment PIN_62 -to Vout[3] +set_location_assignment PIN_71 -to Vout[4] +set_location_assignment PIN_68 -to Vout[5] +set_location_assignment PIN_58 -to Vout[6] +set_location_assignment PIN_57 -to Vout[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to Vout +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to Vout +set_instance_assignment -name SLOW_SLEW_RATE ON -to Vout +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to Vout +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to Vout + +set_location_assignment PIN_4 -to CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CKE +set_instance_assignment -name SLOW_SLEW_RATE ON -to CKE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CKE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to CKE + +set_location_assignment PIN_8 -to nCS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nCS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCS + +set_location_assignment PIN_2 -to nRWE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRWE +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRWE +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRWE + +set_location_assignment PIN_5 -to nRAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nRAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nRAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nRAS + +set_location_assignment PIN_3 -to nCAS +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to nCAS +set_instance_assignment -name SLOW_SLEW_RATE ON -to nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to nCAS +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to nCAS + +set_location_assignment PIN_6 -to BA[0] +set_location_assignment PIN_14 -to BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to BA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to BA +set_instance_assignment -name SLOW_SLEW_RATE ON -to BA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to BA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to BA + +set_location_assignment PIN_18 -to RA[0] +set_location_assignment PIN_20 -to RA[1] +set_location_assignment PIN_30 -to RA[2] +set_location_assignment PIN_27 -to RA[3] +set_location_assignment PIN_26 -to RA[4] +set_location_assignment PIN_29 -to RA[5] +set_location_assignment PIN_21 -to RA[6] +set_location_assignment PIN_19 -to RA[7] +set_location_assignment PIN_17 -to RA[8] +set_location_assignment PIN_15 -to RA[9] +set_location_assignment PIN_16 -to RA[10] +set_location_assignment PIN_7 -to RA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RA +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RA +set_instance_assignment -name SLOW_SLEW_RATE ON -to RA +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to RA +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RA + +set_location_assignment PIN_100 -to DQMH +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQMH +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQMH +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQMH + +set_location_assignment PIN_98 -to DQML +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to DQML +set_instance_assignment -name SLOW_SLEW_RATE ON -to DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DQML +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to DQML + +set_location_assignment PIN_97 -to RD[0] +set_location_assignment PIN_90 -to RD[1] +set_location_assignment PIN_99 -to RD[2] +set_location_assignment PIN_89 -to RD[3] +set_location_assignment PIN_91 -to RD[4] +set_location_assignment PIN_92 -to RD[5] +set_location_assignment PIN_95 -to RD[6] +set_location_assignment PIN_96 -to RD[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to RD +set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to RD +set_instance_assignment -name SLOW_SLEW_RATE ON -to RD +set_instance_assignment -name PAD_TO_CORE_DELAY 0 -to RD +set_instance_assignment -name ENABLE_BUS_HOLD_CIRCUITRY ON -to RD +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to RD + +set_global_assignment -name QIP_FILE UFM.qip \ No newline at end of file diff --git a/CPLD/RAM2E.sdc b/CPLD/RAM2E.sdc new file mode 100644 index 0000000..eac36a3 --- /dev/null +++ b/CPLD/RAM2E.sdc @@ -0,0 +1 @@ +create_clock [get_ports C14M] -period 69.841ns